AGC with non-linear gain for PLL circuits

Abstract: A circuit automatically changes the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency, and a lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range. A circuit responsive to the sense signal output selectively applies the first frequency to clock the counter when the PLL is within the predetermined phase difference range, and to apply the second frequency to clock the counter when the PLL is operating outside of the predetermined phase difference range.

Description: This invention relates to improvements in circuitry and methods for operating a phase-locked loop (PLL), and more particularly to improvements in circuitry and methods for reducing the steady state error of the PLL and increasing the capture range of the PLL during convergence by automatically changing the gain of the phase detector. This invention pertains to phase-locked loop circuits of the type that use a phase detector, an integrating filter, and a variable frequency feedback circuit to track accurately an input signal at a reference frequency. In a broad sense, the variable frequency circuit can be a voltage-controlled oscillator (VCO). However, in the embodiment illustrated herein, the variable frequency circuit includes a variable speed motor and a generator that produces a signal of frequency dependent upon the speed of the motor. A phase detector determines the phase of the variable frequency signal with respect to the reference frequency. The phase detector then generates a dc voltage signal, which may be filtered by the integrating filter, to control the variable frequency signal, for example, by controlling the frequency of a VCO or by controlling the speed of the motor. The voltage signal forces the VCO to compensate, or changes the speed of the motor, when the variable frequency drifts from the reference frequency. Typically when a PLL begins operation, the variable frequency requires a certain time to converge to the frequency of the input signal, until "lock" occurs. When lock occurs, the variable frequency tracks the input signal, and the PLL circuit functions in a feedback mode to maintain the lock. As known in the art, a higher gain applied to the signal from the phase detector reduces the steady state operation error. On the other hand, a low gain applied to the phase detector output signal widens the lock, or capture, range. European Patent Application Publication No. 0571148, which forms part of the state of the art by virtue of Article 54(3) of the EPC, discloses a circuit and method for generating drive signals having a frequency synchronised to a reference frequency signal. The circuit includes a PLL that includes a motor, and a circuit for generating a signal having a frequency proportional to the speed of the motor. A phase detector produces a signal for a time proportional to a phase difference between the motor speed signal and a reference frequency signal. A first phase difference measuring circuit, clocked only by a first fixed frequency signal, produces a first voltage output signal at a first gain proportional to the phase difference when the duration of the phase detector signal is less than a predetermined time. A second phase difference measuring circuit, selectively clocked only by a second fixed frequency signal, produces a second output signal at a second gain when the duration of the phase detector signal is greater than the predetermined time. The first and second output signals are summed and applied to control the speed of the motor. US Patent No. 4,564,794 discloses circuitry for controlling the speed of a DC motor by a servo which includes a digital phase lock loop. The motor drives a tachometer whose pulse frequency is low relative to the frequency of a clock. The clock continuously drives a counter whose ever increasing number content is gated to a data latch upon the occurrence of each successive tachometer pulse, thus this data latch contains a first time-number of ever increasing magnitude. A second data latch contains a second number. The difference in magnitude of two consecutive time-numbers is indicative of motor speed. Initially, this second number is set to contain a reference number which is equal in magnitude to the number of clock pulses which will occur between adjacent tachometer pulses when the motor is running at desired speed. A pair of limit numbers are provided to define the upper and lower limits of servo saturation. The difference between the first number and the second number is detected upon the occurrence of each tachometer pulse to generate a third or difference number. This difference number is compared to the two limit numbers to determine if the servo is in saturation. If it is not in saturation, the second number is reset to a value which is equal to the old value plus the reference number. If the servo is in saturation, the second number is reset to a number which is a function of the first number, the reference number, and that limit number which is associated with the particular mode of saturation. What is needed is a circuit and method that will provide a lower gain when the phase error between the reference frequency and the variable frequency is large, during convergence, and a higher gain when the phase error is low, when lock has been, or is close to being, attained. Considering the above, therefore, it is an object of the invention to provide an improved apparatus and method for reducing steady-state errors in a PLL circuit. It is another object of the invention to provide a method and circuit for increasing the capture range bandwidth in the operation of a PLL circuit. It is another object of the invention to provide a PLL circuit in which the gain of the phase detector automatically increases when the PLL circuit is operating in locked-mode and lowers when the circuit is operating in a convergence mode. It is still another object of the invention to provide an improved apparatus and method of the type described to reduce steady-state error, and increase capture range bandwidth, in the operation of a PLL circuit used for driving a motor. It is yet another object of the invention to provide an improved circuit having the advantages of the above described method and apparatus that can be integrated in a single integrated-circuit chip. These and other objects, features, and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read with the drawings and appended claims. According to one aspect of the present invention there is provided a circuit for automatically changing the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation, comprising: a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference; a counter; a motor driving circuit for driving said motor in response to the count reached by said counter through the duration of the phase detector output signal; a source of clock pulses at a first frequency and a second frequency, said second frequency being lower than said first frequency; a lock range sense circuit to produce a sense signal output that indicates when said PLL is within a predetermined phase difference range; and a circuit responsive to said sense signal output for selectively applying said first frequency to clock said counter, and for selectively applying said second frequency to clock said counter when said PLL is operating outside said predetermined phase difference range. According to another aspect of the present invention there is provided a method for automatically changing the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation, comprising: producing a signal of duration proportional to a phase difference between the motor speed signal and a reference frequency; enabling a counter to count clock pulses during the duration of the signal of duration proportional to the phase difference; driving the motor to operate at a speed relative to the count of said counter; detecting whether the PLL is within a predetermined phase difference range; and controlling the frequency of clock pulses to the counter to be at a first frequency within a predetermined phase difference range and at a second frequency outside the predetermined phase difference range. The invention provides a circuit for automatically changing the gain in a PLL used for driving a motor. The motor is of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency. The phase detector produces an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency. A lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range. A circuit responsive to the sense signal output selectively applies the first frequency to clock the counter when the PLL is within the predetermined phase difference range, and applies the second frequency to clock the counter when the PLL is operating outside the predetermined phase difference range. The invention further provides, a method for automatically changing the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation is provided. A signal of duration proportional to a phase difference between a motor speed signal and a reference frequency is produced, and a counter is enabled to count clock pulses during the duration of the signal of duration proportional to the phase -difference. The motor is driven at a speed relative to the count of the counter. If the PLL is within a predetermined phase difference range the frequency of clock pulses to the counter is controlled to be at a first frequency. If the PLL is outside the predetermined phase difference range, the frequency of clock pulses to the counter is controlled to be at a second frequency, lower than said first frequency. The invention is illustrated in the drawings, in which: Figure 1 is an electrical schematic diagram of a PLL circuit with non-linear gain according to a preferred embodiment of the invention for driving a motor connected to the PLL circuit. Figure 2 is an electrical schematic diagram of the edge detector circuit of Figure 1. Figure 3 is an electrical schematic diagram of the saturation detector of Figure 1. Figure 4 is an electrical schematic diagram of the lock detector of Figure 1. And Figure 5 is a graph of the output voltage of the phase detector circuit as a function of the phase difference between the reference frequency and a motor speed signal, showing two gain operating ranges, according to the invention. In the various figures of the drawings, like reference numerals denote like or similar parts. An electrical schematic block diagram of a digital AGC circuit 10 in which the apparatus and method according to the preferred embodiment of the invention may be incorporated is shown in Figure 1. The Figure 1 embodiment shows the subject matter of the invention and the associated processing and motor devices to provide a suitable context for the invention. The digital AGC circuit 10 provides different gains for use in a PLL circuit. Although the digital AGC circuit 10 can be constructed of discrete components, preferably it is integrated onto a single semiconductor chip adapted for connection into a PLL system. While PLL systems sometimes find particular application in motor driving circuits, it is to be appreciated that PLL circuits, and therefore the digital AGC circuit 10, may be employed in a variety of applications. The PLL circuit 10 embodiment shown in Figure 1 is used for driving a motor 12. Accordingly, standard motor driving circuitry is provided including a transconductance loop and other associated circuitry, denoted by the box 13 labeled "motor driver." A signal is derived on a line 16 from the motor 12 and associated electronics that indicates the speed at which the motor 12 is rotating. The signal is referred to herein as the "motor speed signal." The motor speed signal on the line 16 is connected to one input of a phase detector 18. A reference frequency signal is applied on a line 19 to another input of the phase detector 18 for comparison with the motor speed signal on the line 16. Thus, the frequency/phase detector 18, which may be, for example a commercially available phase detector, such as an MC4044 phase/frequency detector circuit, detects a phase difference between the two signals. The frequency/phase detector 18 has two outputs, one on line 20 and the other on line 22. The output on the line 20 indicates that the reference frequency on line 19 leads the phase motor speed signal on line 16. This indicates that the motor speed is less than the desired speed, and needs to be increased. On the other hand, the output on the line 22 indicates that the phase motor speed signal on line 16 leads the reference frequency on line 19. This indicates that the motor speed exceeds the desired speed, and needs to be slowed. In addition, the frequency/phase detector 18 determines the time difference between the occurrence of the incoming pulse edges of the motor speed signal on line 16 and the reference frequency on line 19. Thus, the output on either line 20 or 22 from the frequency/phase detector 18 is a pulse of length equal or proportional to the time difference between the active edges of the pulses on lines 16 and 19. The pulses on lines 20 and 22 control the counter 24 to which they are respectively applied to count either up or down for that time. If the frequency/phase detector 18 detects the falling edge of a motor speed signal pulse on line 16 before it detects a falling edge of the reference frequency on line 19, it will emit a pulse on the "down" line 22 to control the counter 24 to count down. On the other hand, if the falling edge of the reference frequency on line 19 arrives before the falling edge of the motor speed signal pulse on line 16, the frequency/phase detector 18 emits a pulse on the "up" line 20. As noted, the length of the frequency/phase detector 18 output pulse in any event is equal or proportional to the phase difference of the incoming signals. The counter 24 is connected to receive clock pulses on a line 25, the clock pulses being either at a system frequency, f SYS , or a divided system frequency, f SYS /N, as below described in greater detail. In addition, the counter 24 is connected to be preset to a predetermined mid-value count (for example, 10000000 in an 8-bit counter) by a preset signal on a line 53 from an edge detector circuit 28, also below described in greater detail. The outputs from the counter 24 on lines 40-40 are applied to a saturation detector 30. The saturation detector 30 produces an output signal on a line 33 for use in selecting the clock frequency applied to the counter 24, as below described. The function of the counter 24 can be performed by other types of counters. For instance, counters may be used that have a single input for counting either up or down depending on the sign of the pulse emitted from the phase detector 18. A qualifying gate pulse also may be provided to gate the clock in such embodiment. The clock signals applied to the counter 24 are received from a switch 35. The switch 35 has two positions. The first position connects the line 25 directly to the system frequency, f SYS , on input node 36. The other position connects the line 25 to a divided system frequency, f SYS /N, derived by a frequency divider 38. The clock signals provided by the switch 25 are determined by whether the counter is operating in a saturation condition, as determined by the saturation detector 30. The details of the saturation detector 30 are shown in Figure 3. The saturation detector 30 includes an AND gate 31 to the inputs of which each line 40-40 is connected. The output from the AND gate 31 is connected to one input of an OR gate 34. Additionally, a NOR gate 37 is provided to the inputs of which the lines 40-40 also are applied. The output from the NOR gate 37 is connected to another input of the OR gate 34. The output from the OR gate 34 represents the over/underflow, or saturation, signal that occurs when the counter 44 reaches a saturation state of either all ones or all zeros. The output from the saturation detector 30 is applied by an OR gate 42 to reset a "set-reset flip-flop 44." The Q output of the flip-flop 44 is connected to control the switch 35 to select either the system frequency, f SYS , directly from the node 36 or the divided system frequency, f SYS /N, from the frequency divider 38. Thus, depending upon whether the counter 24 is saturated or not, as detected by the saturation detector 30, either the system frequency, f SYS , or the divided system frequency, f SYS /N, clocks the counter 24. If desired, other reset conditions can be used to control the clocking frequency of the counter 24. For example, a power on reset (POR) signal can be applied to the OR gate 42 also to serve to reset the flip-flop 44. When the counter 24 is reset, it is initialized to count up or down from an intermediate count value centered between its upper and lower saturation values. Thus, for example, if the counter 24 is an 8-bit counter, when it is reset, it may be initialized to the count 10000000, from which either an up or down count can be made. Additionally, the counter 24 is of the type that stops counting when an overflow or underflow condition occurs to hold at the over- or underflow count, instead of continuing to count, or wrapping around. For this purpose the clock signal 25 can be gated by the output of the saturation detector. The counter 24 is reset after the termination of the counting period generated by either signal on line 20 or line 22. The termination of the signal is detected in the edge detector circuit 28, the details of which are shown in Figure 2. The edge detector circuit 28 receives inputs from the up and down lines 20 and 22 at the inputs of a NAND gate 45. The output from the NAND gate 45 is connected to the D-input of a first D-type flip-flop 46. The Q output of the first D-type flip-flop 46 is connected to the D-input of a second D-type flip-flop 47, and to one input of a NOR gate 50. The output of the NOR gate 50 provides a "latch" signal on line 54 for use in the circuitry shown in Figure 1. The Q output of the second D-type flip-flop 47 is connected to the D-input of a third D-type flip-flop 48 and to one input of a NOR gate 49. The output of the NOR gate 49 on the line 53 is used to provide the "preset" signal to the circuitry shown in Figure 1. On the other hand, the Q(bar) output of the flip-flop 47 is connected to another input of the NOR gate 50. Finally, the Q(bar) output of the D-type flip-flop 48 is connected to another output of the NOR gate 49. The flip-flops 46, 47, and 48, as well as the NOR gates 49 and 50 are clocked by a system clock applied to the node 36. A data latch 52 receives on its inputs the data carried on lines 40-40 from the counter 24. The function of the latch 52 is enabled by a "latch" signal on the line 54 from the edge detector circuit 28, indicating completion of the phase difference measurement. At this point the data output from the counter 24 is latched into the latch 52. The time in which the phase difference measurement is completed is, for example, when the falling edge of the last occurring pulse of the motor speed signal or the reference frequency occurs, as determined by the edge detector circuit 28. The output of the latch 52 developed upon lines 60-60 is applied to a digital-to-analog converter circuit 62. The current output from the digital-to-analog converter 62 is connected to the inverting input of an amplifier circuit 69. The amplifier circuit 69 includes an operational amplifier 68 having a resistor 76 connected to an analog ground 75 from its non-inverting input terminal, and a feedback resistor 72 connected between its output and the inverting input. The amplifier circuit 69 is biased by the resistor 76 so that the voltage applied to the inverting input by the digital to analog converter 62 is equal to the voltage on the analog ground 75 when the digital to analog converter 62 is driven by the "reset" value (for example, 10000000). The amplifier circuit 69 can be eliminated if the digital to analog converter 62 has a voltage output, by exchanging the lines 20 and 22 to the counter 24 to maintain the correct sign of the signal. The voltage output on the node 71 from the amplifier circuit 69 is applied to a filter circuit 80 and an integrator circuit 89 for application to the motor driver circuit 13. The integrator circuit 89 is of known construction, having an operational amplifier 86 and a resistor 94 connected between the non-inverting input terminal 92 and the analog ground 75. The output node 85 of the operational amplifier 86 is connected to the inverting input terminal by a capacitor 90 and resistor 88, connected in series. The output from the power driver circuit 13 is connected to the motor 12 to control its rotation. In operation, when the motor 12 and the PLL circuit 10 are initially started, the set-reset flip-flop 44 is reset by the POR signal. The flip-flop 44 operates the switch 35 to select the divided system frequency, f SYS /N, produced at the output of the frequency divider 38. In addition, a great difference will initially exist between the frequencies of the motor speed signal on the line 16 and the reference frequency on line 19. During this time, the counter 24 rapidly counts until it reaches saturation. When this occurs, the saturation detector circuit 30 continues a signal to the reset terminal of the flip-flop 44 to hold the flip-flop 44 in its reset state. Thus, the counter 24 counts the pulses until the end of the duration of the pulse on the line 20 or its own saturation. Then, the count of the counter 24 is latched into the latch 52. This binary number latched by the latch 52 is converted to an analog signal by the digital to analog converter 62 to produce an output voltage on the node 71. During the initial startup time, or when the counter 24 is saturated, with the divided clock frequency at the output of the frequency divider 38 applied to clock the counter 24, the gain at which the output voltage is produced on node 71 is relatively low, as shown by line 110 in Figure 5. Having a low gain during this time, or during a time in which lock may be lost for another reason, such as a temporary interruption or perturbation to the rotor of the motor 12, the low gain along line 110 assists in rapidly returning the circuit to a lock condition without significantly overshooting or over-correcting to achieve the lock condition (typically due to the saturation of the phase detector 18). In contrast, when the PLL circuit 10 is operated within the lock range (i.e., the reference frequency closely matches and tracks the frequency and phase of the motor frequency signal as determined by the lock detector circuit 61) the counter 24 no longer saturates between reset pulses from the edge detector 28. The determination that the circuit 10 is operating within a predetermined phase difference, herein the "lock range," is determined by a lock detector circuit 61. The details of the lock detector circuit 61 are shown in Figure 4. The lock detector circuit 61 has two AND gates 63 and 64. The four most significant bits are compared with the fifth most significant bit to find whether the states on the 5 most significant bit lines within lines 60-60 are either "01111" or "10000," to decide whether the count on lines 60-60 is within a predetermined range from the preset value (for example between 01111xxx and 10000xxx around the center count, 10000000). It will be appreciated, of course, that any desired lock range precision can be selected by the selection of the number of most significant bits compared by the AND gates 63 and 64. The outputs from the respective AND gates 63 and 64 are connected to the inputs of an OR gate 65, the output of which provides the "lock" signal on line 66. The detection of a lock condition by the detector 61 on line 66 is used to set the flip-flop 44. To avoid false detections, a series of D-type flip-flops 100, 103, . . . 104 may be provided, as shown. Thus, the output from the lock detector 61 is applied to the D-input of a first D-type flip-flop 101. The flip-flop 101 is clocked by the preset signal on line 53 developed by the edge detector circuit 28. In addition, the D-type flip-flop 101 is reset by the signal on the line 53 when the lock detector is producing no output. This condition is determined by AND gate 102. The number of similar flip-flops 103, . . . 104 determines the number of cycles in which lock is detected before the gain of the PLL is changed. In the lock condition (or within the lock range as described above), as determined by the lock detector 61 and confirmed by passage through the series of D-type flip-flops 101, 103 . . . 104, the flip-flop 44 is set, thus commutating switch 35 to apply the system frequency, f SYS , from node 36 directly to clock the counter 24. During operation in this range, the counter 24 produces a voltage on node 71 that follows the line 111 as shown in Figure 5. It can therefore be seen that in the lock range, the circuit 10 has a higher gain throughout the range of the counter 24, due to the difference in the clocking frequency. It should be noted that multiple break points can be provided, if desired, by using a counter (not shown) in place of the flip-flop 44 and multiple dividers (also not shown) in conjunction with divider 38, so that in each range, a "set" pulse moves into a higher frequency range, and a "reset" returns to the previous, lower frequency, range. In addition the output range of the digital to analog converter 62 may also be changed by the Q output of the flip-flop 44, if appropriate for system stability.

Claims: A circuit for automatically changing the gain in a PLL (10) for driving a motor (12) of the type having a motor speed signal (16) that indicates the speed of motor rotation, comprising: a phase detector (18) for sensing a phase difference between the motor speed signal (16) and a reference frequency (FREF) and for producing an output signal (20,22) of duration proportional to the sensed phase difference; a counter (24); a motor driving circuit (13,89) for driving said motor (12) in response to the count reached by said counter (24) through the duration of the phase detector output signal (20,22); a source of clock pulses at a first frequency (FSYS) and a second frequency, said second frequency being lower than said first frequency (FSYS); a lock range sense circuit (61) to produce a sense signal output (66) that indicates when said PLL is within a predetermined phase difference range; and a circuit (35,30,33,24,44) responsive to said sense signal output (66) for selectively applying said first frequency (FSYS) to clock said counter (24) when said PLL is within said predetermined phase difference range, and for selectively applying said second frequency to clock said counter (24) when said PLL is operating outside said predetermined phase difference range. The circuit of claim 1, further comprising a saturation detector (30) to produce a saturation signal (33) when said counter (24) is in saturation, said circuit (35,30,33,24,44) responsive to said sense signal (66) output for selectively applying said second frequency to clock said counter (24) responsive to said saturation signal (33). The circuit of claim 2, wherein said circuit responsive to said sense signal (66) output for selectively applying said first frequency (FSYS) to clock said counter (24) and responsive to said saturation signal (33) to apply said second frequency to clock said counter (24) comprises a flip flop (44) that is set by the sense signal (66) output and reset by said saturation signal (33), an output of said flip flop (44) being connected to select said first (FSYS) or second frequency in response to said flip flop (44) being set or reset. The circuit of any one of claims 1 to 3, further comprising a latch (52) connected to receive the count reached by said counter (24), and circuitry (28) to determine the duration of said phase detector (18) output signal (20,22) and having an output connected to said latch (52) to hold the count reached by said counter (24). The circuit of claim 4, wherein said lock range sense circuit (61) is connected to receive an output (60) of said latch (52) to produce a sense signal output (66) that indicates when said PLL is within a predetermined phase difference range. The circuit of claim 5, wherein said lock range sense circuit (61) is connected to detect the states on a predetermined number of output lines (60) from said latch (52). The circuit of claim 6, further comprising a delay circuit (101,103,104) to which the output (66) of said lock range sense circuit (61) is applied, said delay circuit (101,103,104) having an output connected to select said first frequency (FSYS) only after said lock range sense circuit (61) has sensed that said PLL is within the predetermined phase difference range for a predetermined number of comparisons between the motor speed signal (16) and the reference frequency (FREF). The circuit of claim 7, wherein said delay circuit (101,103,104) comprises a plurality of flip flop circuits (101,103,104). The circuit of claim 8, wherein said plurality of flip flop circuits (101,103,104) provide one flip flop circuit for each number of said predetermined number of comparisons between the motor speed signal (16) and the reference frequency (FREF). The circuit of any one of claims 1 to 9, wherein said source of clock pulses comprises a source of clock pulses at the first frequency (FSYS), and a frequency divider (38) to receive clock pulses at the first frequency (FSYS) to produce an output at a second frequency divided from said first frequency (FSYS). The circuit of any one of claims 1 to 10, wherein said phase detector (18) produces a pulse in response to a comparison between said motor speed signal (16) and the reference frequency (FREF) on a first line (20) if the motor speed signal (16) lags the reference frequency (FREF) and on a second line (22) if the motor speed signal (16) leads the reference frequency (FREF). The circuit of claim 11, wherein said first (20) and second (22) lines of said phase detector (18) are connected to produce up and down counts of said counter (24). The circuit of any preceding claim, further comprising circuitry (28) to preset said counter (24) to a mid-range value after the duration of each of said phase detector (18) output signals (20,22). The circuit of any preceding claim, wherein said motor driving circuit (13,89) comprises an integrating filter (89) and a motor driver (13). A method for automatically changing the gain in a PLL (10) for driving a motor (12) of the type having a motor speed signal (16) that indicates the speed of motor rotation, comprising: producing a signal of duration proportional to a phase difference between the motor speed signal (16) and a reference frequency (FREF); enabling a counter (24) to count clock pulses (25) during the duration of the signal (20,22) of duration proportional to the phase difference; driving the motor (12) to operate at a speed relative to the count of said counter (24); detecting whether the PLL (10) is within a predetermined phase difference range; and controlling the frequency of clock pulses (25) to the counter (24) to be at a first frequency (FSYS) within a predetermined phase difference range and at a second frequency outside the predetermined phase difference range. The method of claim 15, wherein said step of controlling the frequency of clock pulses (25) to the counter (24) to be at a first frequency (FSYS) within a predetermined phase difference range and at a second frequency outside the predetermined phase difference range comprises providing the first frequency (FSYS) at a higher frequency than the second frequency.

Inventors: CAROBOLANTE FRANCESCO, CAROBOLANTE, FRANCESCO
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS, INC.
Application year: 1993
Main classification: H03L7
IPC codes: H03L7, H02P29, G05B11