Semiconductor read only memory

Abstract: A semiconductor read only memory of the present invention includes a plurality of word lines disposed in parallel. The semiconductor read only memory has a plurality of units. Each of the plurality of units includes: a first main bit line and a second main bit line which cross the word lines; first, second, third, and fourth sub-bit lines which are disposed substantially in parallel to the first and second main bit lines, and each of which has a first end and a second end; four memory cell columns, each of the memory cell columns including a plurality of memory cells connected in parallel between respective adjacent two of the sub-bit lines; and a plurality of bank selecting switches for selecting one of the four memory cell columns. In the semiconductor read only memory, the first ends of the first sub-bit line and the third sub-bit line are connected to the first main bit line, and the second ends of the second sub-bit line and the fourth sub-bit line are connected to the second main bit line. First and second ones of the bank selecting switches are disposed in parallel between the first main bit line and the first sub-bit line, and third and fourth ones of the bank selecting switches are disposed in parallel between the second main bit line and the fourth sub-bit line. A fifth one of the bank selecting switches is disposed between the first main bit line and the third sub-bit line, and a sixth one of the bank selecting switches is disposed between the second main bit line and the second sub-bit line.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a semiconductor read only memory, and more particularly to a semiconductor read only memory in which MOSFETs (metal-oxide-semiconductor field effect transistors) constituting memory cells are connected in parallel. 2. Description of the Related Art: Figure 5 shows an equivalent circuit of a semiconductor read only memory (hereinafter, referred to as "ROM") which is conventionally and widely used. The ROM in Figure 5 is a lateral ROM including a plurality of word lines 1 , a plurality of bit lines 2 which cross the word lines 1 and memory cells 3 each constituted by a MOSFET. Each memory cell 3 is connected in parallel between two adjacent bit lines 2 . It is known that each of the bit lines 2 is a diffusion bit line formed of a diffusion layer or a metal bit line formed of a metal. Further, for example in Japanese Patent Application No. 3-77914, (Japanese Publication No. 4-311900), in order to dispose memory cells more densely, a hierarchical bit line system including main bit lines and sub-bit lines has been proposed for the ROM. Figure 6 shows a circuit diagram showing part of a ROM using the hierarchical bit line system. In the hierarchical bit line system, each of main bit lines such as MB 1 is disposed between two adjacent sub-bit lines, namely, an odd-numbered sub-bit line such as SB 1 and an even-numbered sub-bit line such as SB 2 . Each of the memory cells M ij constituted by MOSFETs is connected between such two adjacent sub-bit lines. The two adjacent sub-bit lines function as a source and a drain, respectively, for each of the memory cells M ij . Further, gates of the memory cells M ij are connected to a word line WL j . The main bit lines MB 1 , MB 2 , ..., etc. are connected to sense amplifiers SA 1 , SA 3 , ..., etc. or grounded via transistors Q 2 , Q 4 ,..., etc. Here, the odd-numbered main bit lines are each connected to a sense amplifier, and the even-numbered main bit lines are each grounded. Ends of the odd-numbered sub-bit lines such as SB 1 on the side of the memory cells M i1 (i.e., on the upper side in Figure 6 ) are connected to bank selecting MOSFETs BSO m , respectively. Two adjacent bank selecting MOSFETs, for example, BSO 1 and BSO 2 are also connected to the odd-numbered main bit line MB 1 disposed therebetween. Further, a gate of each of the odd-numbered bank selecting MOSFETs BSO 1 , BSO 3 , ..., etc. is connected to a bank selecting line BO 1 , and a gate of each of the even-numbered bank selecting MOSFETs BSO 2 , BSO 4 , ..., etc. is connected to a bank selecting line BO 2 . Further, ends of the even-numbered sub-bit lines such as SB 2 on the side of the memory cells M ij (i.e., on the lower side in Figure 6) are connected to bank selecting MOSFETs BSE m , respectively. Two adjacent bank selecting MOSFETs, for example, BSE 1 and BSE 2 are also connected to the even-numbered main bit line MB 2 disposed therebetween. Further, a gate of each of the odd-numbered bank selecting MOSFETs BSE 1 , BSE 3 , ..., etc. is connected to a bank selecting line BE 1 , and a gate of each of the even-numbered bank selecting MOSFETs BSE 2 , BSE 4 , ..., etc. is connected to a bank selecting line BE 2 . Figure 7 shows a pattern on a surface of a semiconductor substrate in the case where diffusion bit lines are used as the sub-bit lines in the circuit shown in Figure 6 . In the ROM with the hierarchical bit line system shown in Figure 6 , the wiring pitch of the main bit lines can be made double as compared with that of the conventional lateral ROM shown in Figure 5 . Accordingly, the ROM with the hierarchical bit line system has an advantage of reducing the parasitic capacitance of bit lines. Moreover, in the case where the diffusion bit lines are used in the ROM with the hierarchical bit line system shown in Figure 6 , the wiring resistance can be greatly reduced. Therefore, the resistance to a discharge current for reading out information from each memory cell can be uniform regardless of positions of the memory cells from which information is read out. However, in the ROM shown in Figure 6 , since the bank selecting MOSFETs are connected to the memory cells in series, the discharge current for reading out information from each memory cell greatly depends on a driving current for the bank selecting MOSFET connected thereto. Accordingly, in order to realize a high-speed reading operation, the discharge current should be increased by enlarging areas where the bank selecting MOSFETs are provided. Such an enlargement increases the chip size. In the ROM shown in Figure 6 , information is read out, for example, from a memory cell M 41 in the following manner. In this case, the bank selecting lines BO 1 and BE 2 are set to be High, the bank selecting lines BO 2 and BE 1 are set to be Low, and the word line WL 1 is set to be High. In addition, a control signal VG 1 for the transistor Q 2 connected to the main bit line MB 2 is set to be High, so that the main bit line MB 2 is grounded. Figure 4 schematically shows a discharge current flow for reading out information from the memory cell M 41 . The discharge current flows through the main bit line MB 3 , the bank selecting MOSFET BSO 3 , the sub-bit line SB 5 , the memory cell M 41 , the sub-bit line SB 4 , the bank selecting MOSFET BSE 2 , and the main bit line MB 2 , in this order. Due to such a current flow in the circuit, the discharge current greatly depends on the driving current for the two bank selecting MOSFETs BSO 3 and BSE 2 both connected to the memory cell M 41 in series. If the driving currents for the bank selecting MOSFETs BSO 3 and BSO 2 are increased, the discharge current can be increased. When areas where the bank selecting MOSFETs are provided are enlarged so as to increase the driving currents for the bank selecting MOSFETs, however, there arises a problem that the chip size is enlarged. EP-A-0 329 141 against which claim 1 is delimited relates to a sense circuit incorporated in a semiconductor memory device. SUMMARY OF THE INVENTION The present invention provides a semiconductor read only memory as set out in claim 1. In one embodiment of the invention, the plurality of memory cells and the plurality of selecting switches are MOSFETs. In another embodiment of the invention, a first sub-bit line, second sub-bit line, third sub-bit line, and fourth sub-bit line are each formed of a diffusion layer. In still another embodiment of the invention, a first main bit line and a second main bit line are formed of metal. Thus, the invention described herein makes possible the advantage of providing a semiconductor read only memory capable of reading out at a high speed while provided with memory cells densely disposed. This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram showing part of a ROM in an example of the present invention. Figure 2 shows a pattern on a surface of a semiconductor substrate in the case where diffusion bit lines are used as sub-bit lines in the ROM shown in Figure 1 . Figure 3 is a circuit diagram schematically showing a discharge current flow when information is read out from a memory cell in the ROM shown in Figure 1 . Figure 4 is a circuit diagram schematically showing a discharge current flow when information is read out from a memory cell in a conventional ROM with a hierarchical bit line system. Figure 5 is a circuit diagram of a conventional lateral ROM. Figure 6 is a circuit diagram showing part of a conventional ROM with a hierarchical bit line system. Figure 7 shows a pattern on a surface of a semiconductor substrate in the case where diffusion bit lines are used as sub-bit lines in the conventional ROM shown in Figure 6 . DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described by way of illustrating an example with reference to the accompanying drawings. Figure 1 shows part of a circuit of a ROM in an example of the present invention. The ROM of the present example uses a hierarchical bit line system. The ROM in this present example has a memory cell region including a plurality of units, each unit having two main bit lines (for example, MB 1 and MB 2 ) and four sub-bit lines (for example, SB 1 , SB 2 , SB 3 , and SB 4 ). Memory cells M ij constituted by MOSFETs are each connected in parallel between two adjacent sub-bit lines. Each of the sub-bit lines is formed of a diffusion layer which is formed on a semiconductor substrate. The MOSFETs each have part of the sub-bit lines connected thereto as a source and a drain. A gate of each of the memory cells M ij is connected to a word line WL j . The main bit lines MB 1 and MB 2 , ..., etc. are connected to sense amplifiers SA 1 , SA 3 , ..., etc. or grounded via transistors Q 2 , Q 4 , ..., etc. Herein, the odd-numbered main bit lines are each connected to a sense amplifier, and the even-numbered main bit lines are each grounded. Hereinafter, the structure of the ROM will be described with reference to a unit including two main bit lines MB 1 and MB 2 , four sub-bit lines SB 1 , SB 2 , SB 3 , and SB 4 , and four columns of memory cells M 1n , M 2n , M 3n , and M 4n . To one end of the sub-bit line SB 1 on the side of the memory cell M 11 (i.e., on the upper side in Figure 1 ), two bank selecting MOSFETs BSO 1 and BSO 2 are connected in parallel. Gates of the bank selecting MOSFETs BSO 1 and BSO 2 are both connected to a bank selecting line BO 1 . To one end of the sub-bit line SB 3 on the side of the memory cell M 31 , the bank selecting MOSFET BSO 3 is connected. A gate of the bank selecting MOSFET BSO 3 is connected to a bank selecting line BO 2 . Further, these three adjacent bank selecting MOSFETs BSO 1 , BSO 2 , and BSO 3 are also connected to the main bit line MB 1 . To one end of the sub-bit line SB 2 on the side of the memory cell M 2n (i.e., on the lower side in Figure 1 ), the bank selecting MOSFET BSE 1 is connected. A gate of the bank selecting MOSFET BSE 1 is connected to a bank selecting line BE 1 . To one end of the sub-bit line SB 4 on the side of the memory cell M 4n , the two bank selecting MOSFETs BSE 2 and BSE 3 are connected in parallel. Gates of the bank selecting MOSFETs BSE 2 and BSE 3 are both connected to a bank selecting line BE 2 . Further, these three bank selecting MOSFETs BSE 1 , BSE 2 , and BSE 3 are also connected to the main bit line MB 2 . Figure 2 shows an example of a layout pattern on a surface of a semiconductor substrate in the case where diffusion bit lines are used as the sub-bit lines in the circuit shown in Figure 1 . In the conventional ROM using diffusion bit lines as sub-bit lines as shown in Figure 7 , bank selecting lines BO 1 , BO 2 , BE 1 , and BE 2 all have the same width. In this example, an interval between the bank selecting lines BO 1 and BO 2 , and an interval between the bank selecting lines BE 1 and BE 2 are equal to those of the ROM shown in Figure 7 . However, the width of the bank selecting lines BO 1 and BE 2 is smaller and the width of the other bank selecting lines BO 2 and BE 1 is larger than those of the ROM shown in Figure 7 . Further, in the conventional ROM as shown in Figure 7 , the bank selecting lines BO 1 and BE 2 are connected to the sub-bit lines via one bank selecting MOSFET, respectively, whereas in the ROM of this example, the bank selecting lines BO 1 and BE 2 having a smaller width than in Figure 7 are connected to the sub-bit lines SB 1 and SB 4 via two bank selecting MOSFETs connected in parallel, respectively. Due to this structure, channel widths of the bank selecting MOSFETs BSO 3 and BSE 1 connected to the bank selecting lines BO 2 and BE 1 can be enlarged, without varying the chip size, and two bank selecting MOSFETs BSO 1 and BSO 2 connected to the bank selecting line BO 1 can be arranged in parallel, and MOSFETs BSE 2 and BSE 3 connected to the bank selecting line BE 2 can be arranged in parallel. In the ROM having the above-mentioned structure, information is read out from the memory cell M 11 in the following manner. The bank selecting lines BO 1 and BE 1 are set to be High, the bank selecting lines BO 2 and BE 2 are set to be Low, and the word line WL 1 is set to be High. Further, a control signal VG 1 for the transistor Q 2 connected to the main bit line MB 2 is set to be High, so that the main bit line MB 2 is grounded. Figure 3 schematically shows a discharge current flow for reading out information in the ROM shown in Figure 1 . As is shown in Figure 3 , a discharge current for reading information from the memory cell M 11 flows through the main bit line MB 1 , the bank selecting MOSFETs BSO 1 and BSO 2 , the sub-bit line SB 1 , the memory cell M 11 , the sub-bit line SB 2 , the bank selecting MOSFET BSE 1 , and the main bit line MB 2 in this order. In this circuit, to the bank selecting line BO 1 , two bank selecting MOSFETs BSO 1 and BSO 2 are connected in parallel. To the bank selecting line BE 1 , one MOSFET BSE 1 having a larger channel width than that in Figure 6 is connected. Accordingly, the discharge current can be made larger than that in the conventional hierarchical system shown in Figure 6 . As a result, the discharge current can be increased without enlarging the chip size, so that the high-speed reading operation is realized. In the above example, though a mask ROM has been described, the invention is applicable to any type of semiconductor read only memory such as an erasable programmable ROM (EPROM) or an electrically erasable programmable ROM (E 2 PROM) in which a plurality of memory cells are disposed in a matrix array. As is described above, according to the present invention, driving currents for bank selecting MOSFETs can be greatly increased without enlarging the chip size. Accordingly, a larger discharge current for reading information can be obtained. As a result, the reading operation can be performed at a higher speed, and a wide operation margin can be ensured, thereby guaranteeing a stable reading operation. Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope of this invention.

Claims: A semiconductor read only memory comprising: a plurality of memory cell groups, each memory cell group including a plurality of memory cells (M ij ); a plurality of selecting switches (BSO 1 , BSO 2 , BSO 3 ) for selecting among a plurality of memory cell groups, each selecting switch connecting a memory group to a main bit line (MB 1 ) ; characterised in that a first one of adjacent selecting switches consists of two selecting transistors coupled in parallel (BSO 2 ,BSO 3 ) and a second one of the adjacent selecting switches consists of a single selecting transistor, and in that the channel width of the single selecting transistor (BSO 1 ) of the second one of the adjacent selecting switches is wider than the channel width of each of the selecting transistors (BSO 2 ,BSO 3 ) of the first one. The semiconductor read only memory according to claim 1, wherein the plurality of memory cells (M ij ) and the plurality of selecting switches (BSO m , BSE n ) are MOSFETs. The semiconductor read only memory according to claim 1, further including a hierarchial bit line system in which for each of a plurality of main bit lines (MB 1 , MB 2 , MB 3 ) there is provided a respective set of sub-bit lines (SB 1 - SB 8 ), and in which each one of a given said set of sub-bit lines (SB 1 - SB 8 ) is connected via a respective one of the plurality of selecting switches (BSO m , BSE n ) to the associated main bit line (MB 1 , MB 2 , MB 3 ). The semiconductor read only memory according to claim 1, wherein at least one sub-bit line of the set of sub-bit lines (SB 1 - SB 8 ) is formed of a diffusion layer. The semiconductor read only memory according to claim 1, wherein at least one main-bit line of the plurality of main bit lines (MB 1 , MB 2 , MB 3 ) is formed of metal.

Inventors: HOTTA YASUHIRO, HOTTA, YASUHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1993
Main classification: G11C17
IPC codes: G11C7, H01L21, H01L27, G11C17