Clock recovery circuit of a demodulator

Abstract: A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same. The interpolator operates at the same cycle as the symbol clock on an average.

Description: BACKGROUND OF THE INVENTION i) Field of the Invention: The present invention relates to a clock recovery circuit to be used for a demodulator according to the pre-characterizing part of one of claims 1 to 3. ii) Description of the Related Arts: Fig. 11 illustrates a conventional clock recovery circuit, as disclosed in "A Study on High Speed Clock Recovery Circuit for all digital demodulator - Block Clock Recovery Scheme - ", The Institute of Electronics, Information and Communication Engineers of Japan, Technical Report SAT90-31, November 1990. In Fig. 11, Ich and Qch signals obtained by a quasi-coherent detection are input to A/D (analog-digital) converters 4 and 5 from input terminals 1 and 2, respectively. A clock oscillator 3 generates a fixed frequency clock of this receiver to the A/D converters 4 and 5 and the A/D converters 4 and 5 operate in synchronism with this fixed frequency clock to perform the A/D conversion. Two random access memories RAM1 6 and RAM2 7 store one slot length of digital Ich and Qch signals. The RAM1 6 and the RAM2 7 constitute a two-port RAM 100. In this two-port RAM 100, while the signals are stored in one of the RAM1 6 and the RAM2 7, the signals stored in the other of the same are processed. A non-linear processor 8 inputs the digital Ich and Qch signals and produces a clock component from the received signals. A clock phase detector 9 inputs the output signal of the non-linear processor 8 and detects a phase of a symbol clock of the received signals. The non-linear processor 8 and the clock phase detector 9 constitute a clock phase estimator 101. An interpolator 10 calculates an interpolation from the output signals of the two-port RAM 100 and the clock phase estimator 101 and outputs decision point data and the interpolated Ich and Qch data are output from respective output terminals 11 and 12. Fig. 12 shows a construction of the non-linear processor 8 shown in Fig. 11. In Fig. 12, the digital Ich and Qch signals are input to first and second square circuits 22 and 23 via input terminals 20 and 21, respectively, and the first and second square circuits 22 and 23 square the input signals. An adder 24 sums the output signals of the first and second square circuits 22 and 23 and outputs the sum of them from an output terminal 25. Fig. 13 shows a construction of the clock phase detector 9 shown in Fig. 11. In Fig. 13, a phase generator 32 inputs the clock signal output from the clock oscillator 3 via a clock input terminal 31 and operates in synchronism with the clock signal to output phase information (0 to 2π or -π to π) of a symbol clock cycle. A COS/SIN wave generator 33 outputs sine (SIN) and cosine (COS) values corresponding to the output values of the phase generator 32. The output signal of the non-linear processor 8 is fed to first and second multipliers 34 and 35 via an input terminal 30 and the cosine and sine values output from the COS/SIN wave generator 33 are also sent to the first and second multipliers 34 and 35. The first and second multipliers 34 and 35 multiply the respective input signals and output the multiplication results to first and second integrators 36 and 37, respectively. The first and second integrators 36 and 37 each integrate one slot length of the respective multiplication result values. A phase calculator 38 calculates an estimated phase difference between the symbol clock included in the received signals and the output value of the phase generator 32 from the output signals of the first and second integrators 36 and 37 to output the estimated phase difference from an output terminal 39. Next, the operation of the above-described conventional clock recovery circuit will now be described. First, the Ich and Qch signals input via the input terminals 1 and 2 are converted into digital Ich and Qch signals in synchronism with the clock signal of the clock oscillator 3 of the receiver in the A/D converters 4 and 5. At this time, the oscillation frequency of the clock oscillator 3 is set to nearly N times the symbol rate. That is, with n times of oversampling, the A/D conversion of the signals is carried out. The obtained digital Ich and Qch signals are separated into two, and are input to the two-port RAM 100 and to the non-linear processor 8. In the non-linear processor 8, the Ich and Qch signals are squared in the respective first and second square circuits 22 and 23 and the squared results are summed in the adder 24 to output the addition result P(n). This is expressed in formula (1) P(n) = {I(n)} 2 + {Q(n)} 2 (N = 0, 1, 2. ...) wherein I(n) and Q(n) represent the A/D-converted Ich and Qch signals, respectively, at a sampling time n. Next, the output signal P(n) of the non-linear processor 8 is fed to the first and second multipliers 34 and 35 which calculate the multiplication of the output signal P(n) by the respective cosine and sine values output from the COS/SIN wave generator 33 to output D c (n) and D s (n), respectively, as follows. D c (n) = P(n) x COS{ clk (n)} D s (n) = P(n) x SIN{  clk (n)} (n = 0, 1, 2, ...) In these formulas,  clk (n) = 2π/N·n (N = an oversampling number) (n = 0, 1, 2, ...) wherein  clk (n) is a modulus of 2π and its obtainable value is 0 ≦  clk (n) < 2π. Then, the first and second integrators 36 and 37 integrate one slot length of the outputs of the respective first and second multipliers 34 and 35 to output integrated values S c and S s as follows. L: a sample number within one slot The phase calculator 38 inputs the S c and the S s and calculates an estimated phase difference  o (rad) between the symbol clock of the received signals and the output value of the phase generator 32 to output the calculation result to the output terminal 39. A calculation method of  o will be described as follows. First, it is assumed that S comp is represented as a complex number as follows. S comp = S c + jS s At this time,  o is expressed as follows.  o = arg(S comp ) (0 ≦  o < 2π) That is, in the phase calculator 38, after the received signals are squared, a Discrete Fourier Transform (DFT) of the squared values at the frequency of the symbol clock of the received signals is calculated to obtain the phase information of the clock component of the received signals. Then, the interpolator 10 interpolates the signals stored in the two-port RAM 100 by using the estimated phase difference  o as the output signal of the clock phase estimator 101 and calculates a value at a decision point (in the case of a Nyquist waveform, a Nyquist point) to output this value. As one example of an interpolating calculation, a method using the first-order Lagrange's formula will be described. First, the interpolator 10 calculates the position of the decision point of the signals stored in the two-port RAM 100 from the estimated phase difference  o . Now, it is assumed that  o is within the following formula 2π/N·i ≦  o < 2π/N·(i+1) but i is an integer within a range of 0 ≦ i ≦ (N-1). At this time, the a phase  D (n) at the decision point of the m-th symbol of the data stored in the two-port RAM 100 exists in a range represented in the following formula. In this case, L is the sample number within one slot. N·m+i ≦  D (n) ≦ N·m+(i+1) (m = 0, 1, 2, ...) N·m+(i+1) ≦ L-1 Next, in the interpolator 10, in order to calculate the respective Ich and Qch decision point data I(m) and Q(m) of the m-th symbol by using the interpolation, the Ich and Qch data with subscript are read out of the two-port RAM 100 as follows. I - (m) = I(N·m+i) I + (m) = I(N·m+i+1) Q - (m) = Q(N·m+i) Q + (m) = Q(N·m+i+1) By using the following formula, the decision point data I(m) and Q(m) are calculated and output. Fig. 14 illustrates a principle of an interpolation process relating to Ich. As is apparent from Fig. 14, the following formula can be derived. I(m) = {a·I - (m) + b·I + (m)}/(a+b) Q(m) = {a·Q - (m) + b·Q + (m)}/(a+b) wherein a = 2π/N·(i+1) -  o and b =  o - 2π/N·i. The interpolator 10 calculates one slot of data as described above and outputs the decision point data I(m) and Q(m) from the respective output terminals 11 and 12. At this time, the number of the data taken out of the two-port RAM 100 for the interpolation is different depending on an interpolation system applied and, for example, in the case of the second-order Lagrange's formula, three points near the decision point can be used. As described above, although a case of the first-order Lagrange's formula has been described, a case of the second-order Lagrange's formula is also similarly described in the aforementioned document. In the conventional clock recovery circuit, as shown in Fig. 11 to Fig. 14, the recovered clock can be produced based on the estimated phase difference between the output value of the phase generator and the symbol clock of the received signals. Hence, the period of the recovered clock becomes the period of the output signal of the phase generator operating in synchronism with the fixed frequency clock. In other words, in the conventional clock recovery circuit, of the recovered clock, only the phase difference from the output value of the phase generator is corrected but the frequency difference can not be controlled. Therefore, in case of communication using a burst mode in which the estimated phase difference between the symbol clock of the received signals and the output value of the phase generator is hardly varied during a so-called burst, no problem arises, but in the case of a continuous mode transmission, this estimated phase difference can not be ignored. As a result, a slip of the recovered clock will occur. Further, GLOBECOM 92, Vol. 1, 9 December 1992, Orlando-Florida, pages 360-364, L.P. SABEL ET AL "A RECURSIVE ALGORITHM FOR THE ESTIMATION OF SYMBOL TIMING IN PSK BURST MODEMS" already discloses a symbol timing recovery structure wherein the received nominal baseband signal is sampled at twice the symbol rate after receive filtering with the samples being stored in a buffer. The samples are then fed into a timing estimator and the resultant timing estimate is used by an interpolator to shift the received signal to the estimated optimum timing location. The estimation process is repeated until 9 iterations have been performed. Finally, EP 0 412 234 A2 refers to a demodulated data recognition and decision device comprising a detector demodulation circuit for demodulating an input signal and outputting a base band signal; a comparator for determining a binary value of said base band signal and outputting the binary signal; a clock recovery circuit for reproducing a recovered clock signal having the same frequency as that of a bit rate of transmitted data and generating a higher rate clock signal than said recovered clock signal; multi-timing decision means for sampling said binary signal with said higher rate clock signal, performing a majority rule decision operation for a plurality of values corresponding to a plurality of points of the sampled binary signal, and outputting a value obtained through said majority rule decision operation; and a latch circuit for latching the value output by said multi-timing decision means with said recovered clock signal and outputting the latched value as a demodulated digital data. SUMMARY OF THE INVENTION Accordingly, the present invention is completed in order to solve the aforementioned problem and it is the object of the present invention to provide a clock recovery circuit which is capable of outputting decision point data without causing any slip of a recovered clock in the case of a continuous mode as well in a demodulator for sampling received signals by using a fixed frequency clock. In order to achieve the object of the present invention. according to a first aspect of the present invention, there is provided a clock recovery circuit to be used for a demodulator, comprising: means for sampling quasi-coherent detection received signals by a fixed frequency clock; means for storing sample values of the received signals; non-linear processing means for producing a clock component from the sample values of the received signals; clock phase detecting means for obtaining an estimated phase difference between a symbol clock of the received signals and an output value of a phase generator operated by the fixed frequency clock on the basis of a non-linearly processed signal by the non-linear processing means; and interpolating means (53) for inputting the sample values stored in the storing means (52) and obtaining decision point data of each symbol; characterized by decision point detecting means (51) for producing timing information and phase information of a decision point representing a leading edge of the recovered clock between two sample points on the basis of the estimated phase difference; wherein the decision point data are obtained by interpolation on the basis of timing information and the phase information of the decision point, the interpolating means (53) operation at the same cycle as the symbol clock of the received signals on an average. In order to achieve the object of the present invention according to a second aspect of the present invention, there is provided a clock recovery circuit to be used for a demodulator, comprising: means for sampling quasi-coherent detection received signals by a fixed frequency clock; means for storing sample values of the received signals; non-linear processing means for producing a clock component from the sample values of the received signals; clock phase detecting means for obtaining an estimated phase difference between a symbol clock of the received signals and an output value of a phase generator operated by the fixed frequency clock on the basis of a non-linearly processed signals by the non-linear processing means; and a latch circuit for inputting the sample values stored in the storing means and obtaining decision point data for each symbol by using a latch pulse; characterized by decision point detecting means for extracting a nearest sampling time to a decision point representing a leading edge of the recovered clock between two sampling points and producing a latch pulse at this sampling time on the basis of an output signal of the clock phase detecting means; wherein the latch circuit operates at the same cycle as the symbol clock of the received signals on an average. In order to achieve the object of the present invention, according to a third aspect of the invention, there is provided a clock recovery circuit to be used for a demodulator, comprising: means for sampling quasi-coherent detection received signals by a fixed frequency clock; means for storing sample values of the received signals; non-linear processing means for producing a clock component from the sample values of the received signals; means for inputting an output signal of the non-linear processing means and extracting a symbol clock component of the received signals; and interpolating means for inputting the sample values stored in the storing means and obtaining decision point data of each symbol; characterized in that the means for extracting a symbol clock component is a band pass filter and that decision point detecting means are provided for producing timing information and phase information of a decision point representing a leading edge of the recovered clock between two sample points on the basis of the symbol clock component extracted by the band pass filter means; wherein the decision point data are obtained by interpolation on the basis of the phase information of the decision point, the interpolating means (53) operating at the same cycle as the symbol clock of the received signals on an average. In the clock recovery circuit of the present invention, by using the timing information and the phase information of the decision point, which are produced based on the estimated phase difference between the symbol clock of the received signals and the output value of the phase generator operated by the fixed frequency clock, the interpolating means takes in the sample values from the storing means and obtains the decision point data of each symbol by the interpolation. The interpolating means is operated at the symbol clock frequency of the received signals on an average to output the decision point data without causing any slip of the recovered clock. In the clock recovery circuit of the present invention, by using the latch pulse produced by extracting the nearest sampling time to the decision point based on the estimated phase difference between the symbol clock of the received signals and the output value of the phase generator operated by the fixed frequency clock, the latch circuit takes in the sample values from the storing means and obtains the decision point data of each symbol. The latch circuit is operated at the symbol clock frequency of the received signals on an average to output the decision point data without causing any slip of the recovered clock. In the clock recovery circuit of the present invention, by using the timing information and the phase information of the decision point, which are produced based on the output value of the band pass filter means for extracting the symbol clock component of the received signals, the interpolating means is operated at the symbol clock frequency of the received signals on an average to output the decision point data without causing any slip of the recovered clock. BRIEF DESCRIPTION OF THE DRAWINGS The objects, features and advantages of the present invention will become more apparent from the consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a first embodiment of a clock recovery circuit according to the present invention; Fig. 2 is a block diagram of a clock phase detector shown in Fig. 1; Fig. 3 is a block diagram of a decision point detector shown in Fig. 1; Fig. 4 is a timing chart showing one example of a production of an interpolation start pulse used in the clock recovery circuit shown in Fig. 1; Fig. 5 is a block diagram of a decision point detector of a second embodiment a clock recovery circuit according to the present invention; Fig. 6 is a block diagram of a third embodiment of a clock recovery circuit according to the present invention; Fig. 7 is a block diagram of a decision point detector shown in Fig. 6; Fig. 8 is a block diagram of a fourth embodiment of a clock recovery circuit according to the present invention; Fig. 9 is a block diagram of a decision point detector shown in Fig. 8; Fig. 10 is a timing chart showing one example of an output of a band pass filter used in the clock recovery circuit shown in Fig. 8; Fig. 11 is a block diagram of a conventional clock recovery circuit; Fig. 12 is a block diagram of a non-linear processor shown in Fig. 11; Fig. 13 is a block diagram of a clock phase detector shown in Fig. 11; and Fig. 14 is a schematic view showing a principle of an interpolation processing according to the first-order Lagrange's formula in the clock recovery circuit shown in Fig. 11. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in connection with its preferred embodiments with reference to the accompanying drawings, wherein like reference characters designate like or corresponding parts throughout the views and wherein the same parts as those of the conventional embodiment described above are designated by the same reference characters and thus the repeated description of the same parts can be omitted for brevity. The first embodiment of the present invention will now be described. In Fig. 1, there is shown the first embodiment of a clock recovery circuit according to the present invention. In Fig. 1, the clock recovery circuit includes a non-linear processor 8, a clock phase detector 50, a decision point detector 51, a shift register 52 and an interpolator 53, as hereinafter described in detail. The non-linear processor 8, the clock phase detector 50 and the decision point detector 51 constitute a clock phase estimator 102. Fig. 2 shows one embodiment of the clock phase detector 50 and Fig. 3 shows one embodiment of the decision point detector 51. In the drawings, the clock phase detector 50 has as an input an output signal of the non-linear processor 8 and a fixed frequency clock generated by a clock oscillator 3 and calculates an estimated phase difference between a symbol clock of the received signals and an output value of a phase generator 32 to output the output value of the phase generator 32 from an output terminal 62. The decision point detector 51 produces an interpolation start pulse (timing information of an decision point) and phase information of the decision point from the output signal of the clock phase detector 50. The shift register 52 operates in synchronism with the clock signal sent from the clock oscillator 3 to store digital Ich and Qch signals output from A/D converters 4 and 5. The interpolator 53 inputs the timing information of the decision point and the phase information of the decision point, takes in the digital Ich and Qch signals stored in the shift register 52 and calculates decision point data of each symbol by interpolation. In Fig. 2, first and second integrators 60 and 61 integrate outputs of the respective first and second multipliers 34 and 35 in a time length corresponding to a time constant of the clock recovery circuit and the integrated results are fed to a phase calculator 38. In Fig. 3, the estimated phase difference (hereinafter referred to as an estimated phase difference of the symbol clock of the received signals) as the output signal of the clock phase detector 50 is input to a subtracter 65 via one input terminal 63. This estimated phase difference is the phase difference between the symbol clock of the received signals and the output value of the phase generator 32 operating by the clock of the clock oscillator 3. Also, the output value of the phase generator 32 is input to the subtracter 65 via another input terminal 64. The subtracter 65 subtracts the estimated phase difference of the symbol clock of the received signals, input from the input terminal 63, from the output value of the phase generator 32, input from the input terminal 64. A modulus circuit 66 of 2π calculates a modulus (-π to +π) of 2π of the output value of the subtracter 65. A leading edge detector 67 detects a negative to positive transition of the output value of the modulus circuit 66 to output the interpolation start pulse from one output terminal 68. The output signal of the modulus circuit 66 is output from another output terminal 69. Next, the operation of the clock recovery circuit described above will now be described with reference to Fig. 1 to Fig. 3. First, the Ich and Qch signals obtained by a quasi-coherent detection are converted into digital signals in the A/D converters 4 and 5, and the obtained digital Ich and Qch signals are separated into two. That is, the signals are input to the clock phase estimator 102 and are also input to the shift register 52 operating by the clock signal of the clock oscillator 3. In the clock phase estimator 102, the estimated phase difference between the symbol clock of the received signals and the output value of the phase generator 32 operating by the fixed frequency clock is calculated in the same manner as the conventional method described above. In this embodiment, one of the purposes is to apply the present invention to a continuous mode which can not ignore variation of the value of the estimated phase difference with the passage of time and thus this estimated phase difference is expressed by a time variant  o (n). In the subtracter 65, the estimated phase difference  o (n) is subtracted from the output value  clk (n) of the phase generator 32 and in the modulus circuit 66 of 2π, the subtraction result is restricted to a range of -π to +π. The output signal  R (n) of the modulus circuit 66 is represented as follows.  R (n) = MOD{ clk (n) -  o (n), 2π} In this case,  R (n) is operated by the clock of the clock oscillator 3 but the output value becomes a phase of a symbol clock component included in the received signals. Hence,  R (n) represents the symbol clock component included in the received signals respecting both the frequency and phase. Next, the leading edge detector 67 discriminates a sign of  R (n) as indicated as follows.  SIGN (n) = +1 (when  R (n) ≧ 0) = -1 (when  R (n) < 0) When  SIGN (n) changes from -1 to +1, it is discriminated that a decision point exists between the sample points, and thus an interpolation start pulse is output. Fig. 4 illustrates a timing chart showing one example of a production of the interpolation start pulse. In this case, an estimated phase difference  o (n) is changed from 179 degrees to 181 degrees by an oversampling of 4 times. The interpolator 53 inputs the interpolation start pulse and takes in the digital Ich and Qch signals stored in the shift register 52. Now, assuming that the output value of the phase generator 32 at an output timing of the interpolation start pulse is  P , a stage number of the shift register 52 is set so that the A/D converted values multiplied by  P in the first and second multipliers 34 and 35 after being squared and summed may be positioned in the central portion of the shift register 52. In this case, since the output signal of the phase generator 32 has a periodicity of 2π, the A/D converted values of n cycles before (n = 0, 1, 2, ...) can obtain similar functions and effects. The interpolator 53 calculates the decision point data of each symbol by interpolation by using the A/D converted values taken in and the output signal of the modulus circuit 66 of 2π as the phase information of the decision point and the obtained decision point data are output from output terminals 11 and 12 for respective Ich and Qch. The second embodiment of the present invention will now be described. Fig. 5 shows another embodiment of a decision point detector 51 in the second embodiment of a clock recovery circuit according to the present invention. In this embodiment, as shown in Fig. 5, different from Fig. 3, a modulus circuit 70 of 2π calculates a modulus (0 to 2π) of 2π of the output value of the subtracter 65. A delay circuit 71 delays the output signal of the modulus circuit 70 one clock period of the clock oscillator 3. A subtracter 72 subtracts the output value of the modulo circuit 70 from the output value of the delay circuit 71, and a comparator 73 compares the output value of the subtracter 72 with a predetermined threshold value and outputs the interpolation start pulse when the output value of the subtracter 72 is beyond the threshold value. Next, the operation of the decision point detector 51 shown in Fig. 5 will now be described. The output signal of the subtracter 65 is restricted to a range of 0 to 2π, that is, the output value of the modulo circuit 70 is restricted to 0 to 2π thereby. The output signal of the modulo circuit 70 is divided into three, that is, it is input to the delay circuit 71, the subtracter 72 and the interpolator 53 from the output terminal 69. Now, assuming that the output value of the modulo circuit 70 of 2π is R(n), the output W(n) of the subtracter 72 is represented in the following formula. W(n) = R(n-1) - R(n) When a rising edge of a recovered clock exists between the output values R(n-1) and R(n) of the modulus circuit 70, the phase is changed from 2π to 0 and hence the phase variation amount W(n) between the two samplings becomes large. Thus, W(n) is supplied to the comparator 73, and, when W(n) is beyond the predetermined threshold value in the comparator 73, it is discriminated that the leading edge of the recovered clock exists between the two samplings. As a result, the interpolation start pulse is output. The third embodiment of the present invention will now be described. Fig. 6 illustrates the third embodiment of a clock recovery circuit according to the present invention. In this embodiment, as shown in Fig. 6, a shift register 80 is operated by a fixed frequency clock and stores the digital Ich and Qch signals. A decision point detector 81 calculates a sampling time nearest to the decision point on the basis of the output signal (estimated phase difference between the symbol clock of the received signals and the output signal of the phase generator 32) of the clock phase detector 50 and produces a latch pulse. In this embodiment, the non-linear processor 8, the clock phase detector 50 and the decision point detector 81 constitute a clock phase estimator 103. A latch circuit 82 takes in the digital Ich and Qch signals stored in the shift register 80 and outputs the decision point data of each symbol. Fig. 7 shows a construction of the decision point detector 81 shown in Fig. 6. In Fig. 7, an absolute value circuit 90 calculates an absolute value of the output signal of the modulus circuit 66 of 2π. A delay circuit 91 delays the output signal of the absolute value circuit 90 one clock period of the clock signal output from the clock oscillator 3. A comparator 92 compares the output signal of the absolute value circuit 90 with the output signal of the delay circuit 91. A second delay circuit 93 delays the output pulse of the leading edge detector 67 one clock period of the clock signal of the clock oscillator 3. A selector 94 inputs the output signal of the leading edge detector 67 and the output signal of the second delay circuit 93 and outputs one of these signals based on the output signal of the comparator 92. One signal selected by the selector 94 is output from an output terminal 95. Next, the operation of the third embodiment of the clock recovery circuit described above will be described. When the leading edge detector 67 of the decision point detector 81 shown in Fig. 7 discriminates that a decision point exists between two sampling points in the same manner as the first embodiment, the leading edge detector 67 outputs the latch pulse. The output signal of the modulus circuit 66 of 2π is input to the absolute value circuit 90, and the comparator 92 compares the output signal of the absolute value circuit 90 with the one clock delayed signal output from the delay circuit 91. Depending on the result of this comparison, it is detected which of the sampling points before or after the latch pulse is nearer to the decision point. The selector 94 receives the output signal of the comparator 92 and selects the output signal of the leading edge detector 67 when the preceding sampling point is nearer to the decision point or output signal of the second delay circuit 93 when the following sampling point is nearer to the decision point. The latch pulse as the selected signal of the selector 94 is output from the output terminal 95 to the latch circuit 82. As described above, the latch circuit 82 inputs the latch pulse from the decision point detector 81 and latches the sampling values of the Ich and Qch signals nearest to the decision point in the shift register 80 to output the latched sampling values as the decision point data via the output terminals 11 and 12. In this embodiment, in comparison with the above-described first embodiment, no interpolation calculation by the interpolator is executed, and the latch circuit is used. As a result, the construction of the clock recovery circuit is simplified. The fourth embodiment of the present invention will now be described. Fig. 8 illustrates the fourth embodiment of a clock recovery circuit according to the present invention. In this embodiment, as shown in Fig. 8, there is provided a BPF (band pass filter) 200 whose central frequency is the same as the symbol clock frequency of the received signals, and a decision point detector 201 produces an interpolation start pulse and decision point phase information on the basis of the output signal of the BPF 200. The non-linear processor 8, the BPF 200 and the decision point detector 201 constitute a clock phase estimator 104. Fig. 9 shows one embodiment of the decision point detector 201 shown in Fig. 8. In Fig. 9, the output signal of the BPF 200 is input to a leading edge detector 211 and a phase difference detector 212 via an input terminal 210. The leading edge detector 211 detects the leading edge of the input signal and outputs an interpolation start pulse on one output terminal 213. The phase difference detector 212 detects phase information of the input signal and outputs the phase information on another output terminal 214. Next, the operation of the fourth embodiment of the clock recovery circuit described above will be described. The output signal of the non-linear processor 8 is input to the BPF 200 whose central frequency is the same as the symbol clock frequency of the received signals and in the BPF 200, the symbol clock component of the received signals is extracted. In this case, the central frequency of the BPF 200 is the symbol clock frequency, as described above, and its band is set to the time constant that the clock recovery circuit operates. Fig. 10 shows one example of the output signals of the band pass filter. In Fig. 10, a case where an A/D conversion is carried out by an oversampling of 4 times is shown. In Fig. 10, a sine wave indicated by a broken line represents the extracted symbol clock component and solid lines are actual sample values which represent the output signals of the BPF 200. As shown in Fig. 9, in the decision point detector 201, after the output value of the BPF 200 is taken in via the input terminal 210, the changing timing of the sign of  R (n) shown in formula (22) from negative to positive is detected by the leading edge detector 211 and the interpolation start pulse is output via the output terminal 213. Also, the phase difference detector 212 detects the phase difference between the sampling points and the zero cross point on the basis of the output signal values of the BPF 200 at the timings before and after the interpolation start pulse is output and outputs the detected phase difference from the output terminal 214. In this case, this phase difference detection method can be preferably carried out as follows. That is, for example, the relationship between the phase differences and the output values of the BPF 200 at the timings before and after the interpolation start pulse is output is stored in a ROM in advance and the output values of the BPF 200 at the above-described timings are applied to the ROM as addresses to use the data output as the phase difference. The interpolator 53 inputs the digital Ich and Qch signals from the shift register 52 on the basis of the interpolation start pulse and the phase information output from the clock phase estimator 104 and executes the interpolation calculation to obtain the decision point data. The obtained decision point data are output from the output terminals 11 and 12. In this embodiment, different from the above-described embodiments, without carrying out the discrete Fourier transform by the clock recovery circuit, the band pass filter such as the BPF 200 is used and thus its construction is further simplified.

Claims: A clock recovery circuit to be used for a demodulator, comprising: means (4, 5) for sampling quasi-coherent detection received signals by a fixed frequency clock; means (52) for storing sample values of the received signals; non-linear processing means (8) for producing a clock component from the sample values of the received signals; clock phase detecting means (50) for obtaining an estimated phase difference between a symbol clock of the received signals and an output value of a phase generator (32) operated by the fixed frequency clock on the basis of a non-linearly processed signal by the non-linear processing means (8): and interpolating means (53) for inputting the sample values stored in the storing means (52) and obtaining decision point data of each symbol; characterized by decision point detecting means (51) for producing timing information and phase information of a decision point representing a leading edge of said estimated phase difference between two sampling points of the recovered clock; wherein the decision point data are obtained by interpolation on the basis of timing information and the phase information of the decision point, the interpolating means (53) operation at the same cycle as the symbol clock of the received signals on an average. A clock recovery circuit to be used for a demodulator, comprising: means (4, 5) for sampling quasi-coherent detection received signals by a fixed frequency clock; means (80) for storing sample values of the received signals; non-linear processing means (8) for producing a clock component from the sample values of the received signals; clock phase detecting means (50) for obtaining an estimated phase difference between a symbol clock of the received signals and an output value of a phase generator (32) operated by the fixed frequency clock on the basis of a non-linearly processed signals by the non-linear processing means; and a latch circuit (82) for inputting the sample values stored in the storing means (80) and obtaining decision point data for each symbol by using a latch pulse; characterized by decision point detecting means (81) for extracting a nearest sampling time to a decision point representing a leading edge of said estimated phase difference between two sampling points of the recovered clock and producing a latch pulse at this sampling time on the basis of an output signal of the clock phase detecting means (50); wherein the latch circuit (82) operates at the same cycle as the symbol clock of the received signals on an average. A clock recovery circuit to be used for a demodulator, comprising: means (4, 5) for sampling quasi-coherent detection received signals by a fixed frequency clock; means (52) for storing sample values of the received signals; non-linear processing means (8) for producing a clock component from the sample values of the received signals; means (200) for inputting an output signal of the non-linear processing means (8) and extracting a symbol clock component of the received signals; and interpolating means (53) for inputting the sample values stored in the storing means (52) and obtaining decision point data of each symbol; characterized in that the means for extracting a symbol clock component is a band pass filter (200) and that decision point detecting means (201) are provided for producing timing information and phase information of a decision point representing a leading edge of the symbol clock component extracted by the band pass filter between two sampling points of the recovered clock; wherein the decision point data are obtained by interpolation on the basis of the timing information and the phase information of the decision point, the interpolating means (53) operating at the same cycle as the symbol clock of the received signals on an average.

Inventors: ISHIZU FUMIO, ISHIZU, FUMIO, ISHIZU, FUMIO, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: H04L7
IPC codes: H04L7, H04L27, H04L25