Digital circuit to regulate the gain of an amplifier stage

Abstract: A digital circuit for controlling the gain of an amplifier stage (FA) of a coded signal receiving channel (1) comprising a peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a digital comparator (6) having two input terminals respectively connected to an output terminal of the peak detecctor and to a memory (8), and an output terminal coupled to a gain control terminal of the amplifier stage and to address select terminals of the memory containing predetermined peak values in coded form.

Description: This invention relates to a digital circuit for controlling the gain of an amplifier stage. Such a circuit is known, for example from US-A- 5 134 631. In particular, the invention concerns a circuit effective to prevent distortion phenomena due to clipping, that is to say due to the dynamic saturation of an amplifier, in a receive channel for voice signals in digital form. The field of application of the invention pertains, particularly but not exclusively, to digital telephone equipment connected to integrated service digital networks, and the description which follows will make reference to that field of application for simplicity of illustration only. In this type of communications networks, analog voice signals are converted to digital signals by sampling. The digital signal, which for example may be coded with 8 bits, contains information as to both the amplitude (bits 7-1) and the sign (bit 0) of the sampled analog signal. Digital telephone equipment of medium-high level using the PCM technique requires final amplifiers which can drive a speaker with sufficient power to allow "room" listening, even from a distance of a few meters from the telephone set. In general, the digital and analog circuits present in the signal path are all designed to supply the speaker with the highest possible power at a low (e.g. < 0.2%) distortion when input a maximum amplitude signal. However, it is unlikely that a voice signal can attain and retain for some time a level corresponding to the maximum amplitude envisaged. It follows that the level of a standard phone call may be found low even at the highest volume setting of the called set. On the other hand, if both the digital circuits and the analog ones present in the signal path are designed to provide maximum output power with low distortion at a medium level of the input signal -- leaving it for the subscriber to select a lower sound volume, then a sufficiently high level of telephone talk can be obtained even with the speakerphone operated. At above-medium level of the input signal, however, distortion problems due to clipping are encountered. Thus, the channel ought to be provided with an anti-clipping circuit affording, when required, maximum output power and low distortion. To fill that demand, state-of-art proposals include approaches of the analog type and of the mixed analog-digital type, which both make ample use of external components. Such approaches involve, however, high power consumption and increased costs. It is an object of this invention to provide a gain control circuit for an amplifier stage, which is a fully digital type and has such structural and functional features as to prevent the occurrence of signal distortion phenomena due to dynamic saturation of the amplifier stage of the receiving channel. Another object of this invention is to avoid distortion phenomena even with the amplifier stage is operated at full power. The present invention is defined by the appended independent claim with advantageous embodiments defined by the dependent claims. The features and advantages of a circuit according to the invention will become apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawing, the single Figure whereof shows diagramatically an amplifier stage embodying this invention, for a digital-coded signal receiving channel. The digital control circuit is shown in the diagram to consist of two main blocks: a digital peak detector 2 and a gain control stage 3. The digital peak detector comprises a digital comparator 5 coupled to an up/down counter 4 which has two inputs intended for up and down count selection and being connected to two outputs of the digital comparator via two AND gates 14. Two further inputs of the AND gates receive two clock signals identified as FAST CLOCK and SLOW CLOCK. The digital comparator outputs issue mutually complementary signals. To the two inputs of the digital comparator are applied: the digital input signal rectified by digital method and the up/down counter output, respectively. The clock signals 18, FAST CLOCK and SLOW CLOCK, are issued by a divider pair; one of these dividers is programmable through a storage register, and they both receive as input a common clock signal MASTER CLOCK. The gain control stage 3 comprises a digital comparator 6 having two inputs connected to the up/down counter 4 output in the first block and to the output of a read-only memory 8, respectively. This comparator has two outputs, for mutually complementary signals, which are coupled to two count select inputs of an up/down counter 7 via two AND gates 13, each having an input to which a clock signal is applied. The counter output is connected to a first input of a digital adder 9. A second input of this adder is connected to a storage register 11, and its output is connected to the address select inputs of the read-only memory and to a gain control input of the amplifier stage. Variations in the amplifier stage gain can be obtained in a known manner to the skilled ones by means of electronic switches connected in the negative feedback network of the amplifier stage. The operation of the digital control circuit according to the invention will now be described, an essential feature of which circuit being that its input side is connected to the receiving channel input. A digital signal coded with 8 bits DR(7-0) is "rectified" by just removing its sign bit. The remaining 7 bits DR(7-1) are input to the digital peak detector 2. When the rectified digital input signal DR(7-1) is greater than or equal to the output signal CR(7-1) of the up/down counter appearing on the other comparator input, the up-count select input of the up/down counter is enabled through the logic AND gate connected to it, and the counter will increment its contents quite rapidly until CR(7-1) attains the same value as the digital input signal DR(7-1). On the contrary, when the digital input signal DR(7-1) is smaller than the signal present at the other comparator input, the counter is enabled to decrement its contents very slowly. The up and down counting rates, which actually determine the "on" and "down" time constants of the peak detector, can be varied by merely selecting, through programmable dividers, different divisors for a system clock signal indicated as MASTER CLOCK in the drawing. In the preferred embodiment, we have selected to keep the up-count rate fixed and to provide four different options as to the down-count rate. The digital peak detector output is connected to the gain control stage 3, which will generate a digital code AT(3-0), of 4 bits in this example, effective to drive through an appropriate decode circuit not shown a certain number of electronic switches connected in the negative feedback network of the amplifier stage, thereby controlling the stage gain. The digital signal CR(7-1) is compared by the comparator 6 with the contents of the read-only storage cell 8 whose address is indicated by the signal AT(3-0). Those contents represent the maximum admissible peak value when the final amplifier gain equals the gain setting performed by means of the digital code AT(3-0). The code AT(3-0) is obtained by adding the output signal from the up/down counter 7 and designated AC(3-0) in the drawing plus the code designated AL(3-0) and corresponding to the volume setting performed by the subscriber through the register 11. The outputs from the comparator 6 control the up/down counter 7 to decrement its contents when the peak value of the input signal exceeds the maximum admissible value, to avoid clipping, thereby lowering the amplifier gain, and to increment its contents when the peak value of the input signal is below the threshold value. Using another register 12 connected to inputs of the ROM, the threshold value for operation of the anti-clipping circuit can be selected from a predetermined range of values. Thus, the circuit of this invention does solve the technical problem and affords a number of advantages, a first of which is that a gain control circuit for an amplifier stage can be provided which is fully digital, and accordingly, easy to integrate monolithically without involving the provision of any external components. Another advantage comes from the improved inherent flexibility afforded by a digital approach over analog ones, whereby a desired setting can be obtained by appropriate programming, either by the subscriber himself or by the manufacturer of the telephone equipment. It will be appreciated that many modifications, adaptations, integrations, changes, and replacements of elements with equivalents thereof may be made unto the embodiment described above by way of non-limitative example, without departing from the protection scope of the appended claims.

Claims: A digital circuit for controlling the gain of an amplifier stage of a coded signal receiving channel (1) having at least one signal input terminal, at least one gain control terminal of the amplifier stage (FA), and at least one output terminal for coupling to an electroacoustic device, comprising a digital peak detector (2) coupled to the input terminal of the receiving channel through a coded signal rectifying circuit means, and a gain control stage (3) comprising a first digital comparator (6), characterised in that said first comparator has at least first and second input terminals respectively connected to an output terminal of the peak detector and to a memory (8) containing coded peak values dependent on predetermined gain control values, and at least first and second output terminals respectively coupled to first and second count select input terminals of a first up/down counter (7) through first and second logic AND gate circuit means (13), each having an input terminal connected to a first clock signal generator (18), such first counter having at least one output terminal coupled to at least one address select input terminal of the memory and to said gain control terminal of the amplifier stage. A circuit according to Claim 1, characterized in that the first comparator outputs complementary signals. A circuit according to either Claim 1 or 2, characterized in that the digital peak detector comprises a second digital comparator (5) having at least first and second output terminals respectively coupled to first and second count select input terminals of a second up/down counter (4) through third and fourth logic AND gate circuit means (14), each having an input terminal respectively connected to second and third clock signal generators (16,17), said second digital comparator having at least first and second input terminals respectively connected to said coded signal rectifying circuit means and to an output terminal of the second up/down counter. A circuit according to Claim 3, characterized in that the second comparator outputs complementary signals. A circuit according to Claim 4, characterized in that the second and third generators coupled to the second up/down counter (4) generate clock signals at different frequencies from each other. A circuit according to Claim 5, characterized in that the clock signal generator (17) coupled to the input terminal reserved for up-count selection (UP) of the second up/down counter (4) generates clock signals having a higher frequency than the frequency of the clock signals generated by the generator (16) coupled to the input terminal reserved for down-count selection. A circuit according to Claim 5, characterized in that at least one (16) of said clock signal generators is driven by a programming circuit means (15). A circuit according to any of Claims 3, 4, 5, 6 and 7, characterized in that the second and third clock signal generators are dividers acting on a primary clock signal. A circuit according to any of the preceding claims, characterized in that, connected between the first up/down counter and the memory, is a digital adder (9) having at least one output terminal connected to at least one address select input terminal of the memory and to the gain control terminal of the amplifier stage, and having at least two input terminals respectively connected to at least one output terminal of the counter and to a storage register (11) for coded values of sound volume. A circuit according to Claim 9, characterized in that at least some of the address select inputs of the ROM are connected to a storage register (12) for coded values of a distortion threshold.

Inventors: CONFALONIERI PIERANGELO, CRIPPA CARLO, DALLAVALLE CARLO, CONFALONIERI, PIERANGELO, CRIPPA, CARLO, DALLAVALLE, CARLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H03G3
IPC codes: H03G3, H03G5