Circuit arrangement for driving of a MOS field-effect transistor

Abstract: A circuit arrangement for gate-controlling a MOS field-effect transistor (T o ) comprises a discharge circuit (12) via which the charge stored in the gate-source capacitance (C GS ) can be discharged according to a time constant, the value of which depends on the internal impedance of said discharge circuit (12). This discharge circuit (12) can be switched between two conditions determined by a relatively large and a relatively small internal impedance respectively and assumes the condition dictated by the relatively small internal impedance as soon as the gate-source voltage (U GS ) has dropped below a predetermined limit.

Description: The invention relates to a metal-oxide semiconductor (MOS) field-effect transistor gate control circuit as defined in the precharacterizing part of claim 1. It is often the case in power output stages that care must be taken to ensure that the corresponding power MOS field-effect transistors are not switched on/off too quickly, so as to keep to the prescribed maximum values of the slew rates of the output voltage or output current. As a rule, for the correspondingly slow switch-off a discharge circuit is provided switchable between the gate electrode and the source electrode of the MOS field-effect transistor in each case. The gate-source capacitance of the MOS field-effect transistor is thus discharged according to a time constant, the value of which depends on the capacitance and on the internal impedance of the discharge circuit. The desired fall time of the gate voltage is usually established by an ohmic resistance circuited in series with the gate-source capacitance or by a current impressed on the discharge circuit. Although such a means of controlling the MOS field-effect transistor allows the slew rate of the output voltage or of the output current to be limited to a predetermined value, whereby the internal impedance of the discharge circuit is to be selected all the more higher, the lower the required fall rate, this has the disadvantage that the gate electrode of the MOS field-effect transistor is loaded with the relatively large internal impedance of the discharge circuit which in the case of noise being coupled into the circuit, particularly via the reverse capacitance, may result in an uncontrolled return ON of the of the already switched-off MOS field-effect transistor. From EP-A-0 327 160 a discharge circuit for a pull transistor of a push-pull stage is known, which comprises two current paths connected in parallel. One of the current paths is switched on or off via a NAND-gate in dependence of the gate-source voltage of the pull transistor. According to the invention a MOS field-effect transistor gate control circuit of the aforementioned kind is provided which comprises the features defined in the characterizing part of claim 1. Accordingly the relatively high impedance dictating slow discharge of the gate-source capacitance is practically short-circuited with the relatively small internal impedance, preferably located in the region of zero, as soon as the prederemined voltage limit value is fallen short of. As a result of this embodiment an extremely reliable gate control circuit is achieved by simple means which is practically insensitive to accumulating (noise) voltages coupled into the circuit and which, nevertheless, permits a controlled switch-off of the MOS field-effect transistor, whereby the time required for discharging the gate-source capacitance and thus the fall time of the gate voltage is extended. By these means any predetermined upper limit values can be maintained without problem for the slew rate of the output signals of the MOS field-effect transistor without having to take into account an increased sensitivity with respect to accumulating (noise) voltages. The switch-off action is divided into two subsequent time periods, of which the first, during which the gate-source voltage is still higher than the predetermined limit value, is characterized by the relatively large internal impedance of the discharge circuit and the second period establishes the relatively small internal impedance as soon as the gate-source voltage has dropped below the predetermined limit value. Whilst the relatively large internal impedance dictating the first period ensures a relatively slow discharge of the gate-source capacitance the resulting, relatively small internal impedance subsequently ensures that the accumulating (noise) voltages coupled into the circuit, particularly via the reverse capacitance, at the gate electrode remain sufficiently small to maintain the MOS field-effect transistor in the switched-off condition. When the internal impedance of the discharge circuit at a gate-source voltage less than the pretermined limit value assumes a value in the region of zero, any accumulated voltages resulting at the gate electrode are reduced to a minimum. The predetermined limit value of the gate-source voltage is preferably selected so that the drain current corresponding to this limit value is already so small as to be negligable or assumes a value in the region of zero, thus making it impossible for any remaining accumulated voltage spikes detrimental to the transistor to result due to a remaining fast discharge of the gate-source capacitance at the output of the MOS field-effect transistor, caused, for instance, by an inductive load or by the line inductance normally existing. In accordance with one practical embodiment of the circuit arrangement the gate electrode of the MOS field-effect transistor can be additionally assigned a charging circuit comprising a charging resistor by means of which the time constant dictating charging of the gate-source capacitance is established. Assigning the charging circuit and the discharge circuit is usefully done alternatively so that the gate electrode of the MOS field-effect transistor is always assigned only one of these two circuits. The dependent claims cite further advantegous embodiments of the circuit arrangement according to the invention. The invention will now be described in more detail on the basis of an example embodiment of the circuit arrangement according to the invention with reference to the drawing in which: Fig. 1 shows a conventional circuit arrangement for gate-controlling a metal-oxide semiconductor field-effect transistor via an ohmic resistance: Fig. 2 shows a conventional circuit arrangement for gate-controlling a metal-oxide semiconductor field-effect transistor via an impressed current: Fig. 3 shows the circuit principle of a circuit arrangement for gate-controlling a metal-oxide semiconductor field-effect transistor according to the invention; Fig. 4a shows the time profile of the gate-source voltage of the metal-oxide semiconductor field-effect transistor gate-controlled by the circuit arrangement according to the invention as shown in Fig. 3, during the switch-off action, and Fig. 4b shows the time profile of the internal impedance of the discharge circuit of the circuit arrangement according to the invention as shown in Fig. 3. Fig. 1 shows a conventional circuit arrangement for gate-controlling a metal-oxide semiconductor (MOS) field-effect transistor T o comprising a resistor R s circuited in series with the gate electrode G of the MOS field-effect transistor T o , this resistor being connectable via a switch S1 to a supply voltage VGH and via switch S2 to ground (M). The drain electrode D of the MOS field-effect transistor T o is connected to an output terminal A. The source electrode S is grounded (M). If the MOS field-effect transistor T o is to be switched on, switch S1 is closed, whilst switch S2 remains open. Accordingly, the gate-source capacitance C GS is charged via the resistor R S until the gate voltage is substantially the same as the supply voltage VGH. If the MOS field-effect transistor T o is to be switched off, switch S1 is opened, whilst switch S2 remains closed. Accordingly, the gate-source capacitance C GS is discharged via the resistor R S . By selecting a correspondingly high value of the resistor R S circuited in series with the gate-source capacitance CGS, relatively high values for the time constants dictating the switch-on/off action can be achieved, i.e. in comparison with a gate electrode G connected directly to the supply voltage VGH or ground M, so that the slew rate in the output signals of the MOS field-effect transistor T o remains within limits. This known circuit arrangement has the disadvantage, however, that the gate electrode G is loaded by the relatively high internal impedance R s of the control circuit, particularly when the MOS field-effect transistor is already OFF. Noise signals (accumulated voltages) coupled into the circuit, for instance, via the reverse capacitance C r may thus result in the gate voltage being raised to such an extent that the MOS field-effect transistor T o is switched on undesirably so. Such an uncontrolled switching on action of the MOS field-effect transistor T o may result in actual practice as soon as noise pulses (spikes) occur, amounting to four to ten times the threshold voltsge of the MOS field-effect transistor T o ., this resulting from the fact that the reverse capacitance C r in actual practice, and depending on the transistor concerned, has a value in the region of 1/4 to 1/10 of C GS , for example. Fig. 2 shows a further conventional circuit arrangement for gate-controlling a MOS field-effect transistor T o which differs from that shown in Fig. 1 merely by the ohmic resistor R s being replaced by two sources of constant current to impress a current I e and I a respectively during ON/OFF action. In this case too, a relatively high internal impedance of the control circuit is caused by means of which the gate electrode of the MOS field-effect transistor T o itself is loaded even when the transistor is OFF. Particularly noise coupled into the circuit via the reverse capacitance C r can thus result in the gate voltage increasing to such an extent that the MOS field-effect transistor T o is again unwantedly switched on. Fig. 3 shows the principle of one embodiment of a circuit arrangement 10 according to the invention which, in turn, is designed for gate-control of a metal-oxide semiconductor (MOS) field-effect transistor T o which in particular may be a power MOS field-effect transistor of a power output stage. Here, the drain electrode D of the MOS field-effect transistor T o is again connected to an output terminal A. The source connection S of this MOS field-effect transistor T o is, in turn, connected to ground M. Between the gate electrode G and the source electrode S the gate-source capacitance C GS is applied, whilst between the drain electrode D and the gate electrode G the reverse capacitance C r is applied. Due to the reverse capacitance C r noise currents I s must be reckoned with between the drain and gate electrodes D and G respectively of the MOS field-effect transistor T o . The circuit arrangement 10 comprises a discharge circuit 12 switchable between the gate electrode G and the source electrode S of the MOS field-effect transistor T o via two electronic switches. Via the discharge circuit 12 the charge stored in the gate-source capacitance C GS can be discharged during switch-off action of the transistor T o according to a time constant t, the value of which depends on the internal impedance Z 1 of the discharge circuit 12. The discharge circuit 12 comprises two current paths 14, 16 circuited in parallel, in which one each of the two electronic switches N1 and N2 respectively controlled in common is arranged. It is, however, also generally feasible to activate these two parallel current paths 14, 16 of the gate electrode G of the MOS field-effect transistor T o via a single, common switch. The current path 14 further contains a voltage divider of three resistors in series R1, R2 and R3 which, on the one hand, can be connected via the series arrangement of the electronic switch N1 to the gate electrode G of the MOS field-effect transistor T o and, on the other, is grounded at M. When the electronic switch N1 is closed this current path 14 of the discharge circuit 12 has a relatively high internal impedance Z i which is substantially determined by the three ohmic resistors R1, R2 and R3. The current path 16 of the discharge circuit 12 in parallel and switchable to the gate electrode G of the MOS field-effect transistor T o via the electronic switch N2 comprises a further electronic switch N4 which is circuited in series with the electronic switch N2. When the electronic switches N2 and N4 are closed, this current path 16 of the discharge circuit 12 has a relatively small internal impedance which may be practically in the region of zero. The electronic switch N4 of the current path16 which, on the one hand, is grounded at M and, on the other, is connected via the electronic switch N2 to the gate electrode G of the MOS field-effect transistor T o is controllable via a switching transistor N3, the gate of which G receives a control voltage U St which is tapped at the junction between the two resistors R1 and R2 of the voltage divider R1 - R3 and which is determined by the drop in voltage across the two resistors R2, R3. In the example embodiment illustrated the switching transistor N3 is formed by a field-effect transistor, the source electrode of which is grounded at M and the gate electrode of which G is connected to the junction between the two resistors R1 and R2. The drain electrode of the switching transistor N3 forming the control output for controlling the electronic switch N4 is connected to a constant current source 18 which receives the supply voltage V CC and furnishes an impressed current I. Via the control output or the drain electrode of the switching transistor N3 a further electronic switch N5 is controllable, via which the resistor R3 can be bypassed when the switching transistor N3 is OFF. The two electronic switches N4, N5 are thus controlled by the switching transistor N3 in such a way that they are open when the switching transistor N3 is ON and closed when the switching transistor N3 is OFF. In the example embodiment shown all electronic switches N1 - N5 are each formed by a field-effect transistor, whereby the two gate electrodes of the electronic switches N4, N5 are connected to the drain electrode of the switching transistor N3 and the two gate electrodes of the electronic switches N1, N2 can be controlled in common via a control discharge signal S E . This control discharge signal S E can be applied to an output E E which is connected to the gate electrodes of the two electronic switches N1, N2 and through which a discharge of the gate-source capacitance C GS and thus the corresponding reduction in the gate-source voltage U GS of the MOS field-effect transistor T o can be activated. The voltage divider comprising the three ohmic resistors R1, R2 and R3 of the current path 14 is dimensioned so that switching transistor N3 is OFF when the discharge circuit 12 is active via the discharge signal S E , thus closing the electronic switch N4 of the current path 16 as soon as the gate-source voltage U GS applied to the discharge circuit 12 has fallen below an assignable clamp value U GSB ( viz. Fig. 4). This clamp value is usefully selected so that the corresponding drain current I D of the MOS field-effect transistor T o has such a small value as to be negligable which can preferably be in the region of zero. For switching on the MOS field-effect transistor T o a charging circuit 20 is provided which comprises an electronic switch N6 in series with a charging resistor R L via which the gate-source capacitance C GS of the MOS field-effect transistor T o can be charged up to a voltage V GH to which the charging resistor R L can be applied via the electronic switch N6. The gate electrode of the electronic switch N6 which is in turn formed by a field-effect transistor is connected to an input E L to which the control charge signal S L can be applied as soon as the MOS field-effect transistor T o is to be switched on and, accordingly, its gate-source capacitance C GS is to be charged. Fig. 4A shows the switch-off action time profile of the gate-source voltage U GS of the MOS field-effect transistor T o controlled by the circuit arrangement 10 according to the invention as shown in Fig. 3. By comparison, Fig. 4B illustrates the resulting time profile of the internal impedance Z 1 of the discharge circuit 12 of the circuit arrangement 10 according to the invention as shown in Fig. 3. during the switch-off action. The function of the circuit arrangement according to the invention is as follows: To switch on the MOS field-effect transistor T 0 it is necessary that the input E L receives a control charge signal S L which closes the electronic switch N6. The electronic switches N1, N2 remain open due to the absence of a control discharge signal at the other input E E . Accordingly, the gate electrode G of the MOS field-effect transistor T o merely receives the charging circuit 20 so that the gate-source capacitance C GS is charged via the charging resistor R L up to the voltage V GH. If the MOS field-effect transistor T o is to be switched off, it is necessary that the other input E E receives a control charge signal S E which closes the electronic switches N1, N2 in the two current paths 14, 16 of the discharge circuit 12 so that the discharge circuit 12 is applied to the gate electrode G of the MOS field-effect transistor T o , causing the discharge of the gate-source capacitance C GS to be initiated. In this situation the electronic switch N6 of the charging circuit 20 is again open, this having resulted from reducing the control charging signal S L at the input E L . On commencement of the discharge action and with the electronic switch N1 closed, the voltage divider R1 - R3 receives a gate-source voltage U GS of the MOS field-effect transistor T o which is substantially still equal to the voltage VGH (viz. Fig. 4A). As soon as the electronic switch N1 is closed at time t o a control voltage U St materializes at the gate electrode G of the switching transistor N3 depending on the gate-source voltage U GS of the MOS field-effect transistor T o and on the dimensioning of the voltage divider R1 - R3. This voltage divider R1 - R3 is now dimensioned such that the switching transistor N3 is ON with closure of the electronic switch N1 so that both the electronic switch N5 bypassing the resistor R3 and the electronic switch N4 in the current path 12 are open. Application of the resistor R3 resulting from the electronic switch N5 being opened is equivalent to a positive feedback of the output signal of the switching transistor N3 to its input so that this switching transistor N3 is switched on relatively quickly (hard ON). During this initial switch-off phase the gate-source capacitance C GS of the MOS field-effect transistor T o is thus discharged via the series arrangement of the resistors R1, R2 and R3 of the voltage divider R1 - R3. The sum of these resistors R1, R2 and R3 is defined so that a relatively high internal impedance results for the current path 14 of the discharge circuit 12 to make sure that the gate-source capacitance CGS is discharged firstly in accordance with a desired, in general relatively large time constant t. During this initial discharge phase the discharge circuit 12 accordingly has a relatively high internal impedance Z½ 1 which is determined exclusively by the current path 14 (viz. Fig. 4B). As soon as the gate-source voltage U GS of the MOS field-effect transistor T o drops below the assignable clamp value U GSB (viz. Fig. 4A) the control voltage U St dropped across the resistors R2 and R3 for the switching transistor N3 has fallen to such an extent that the latter is OFF. At time time t 1 (viz. Figs 4A and 4B) the two electronic switches N4 and N5 are closed via the OFF action of transistor N3, so that, on the one hand, the resistor R2 in the current path 14 is bypassed and, on the other, the gate-source capacitance C GS of the MOS field-effect transistor T o is practically shorted via the two closed electronic switches N2, N4 of the current path 16 of the discharge circuit 12. As of time t 1 the remaining discharge of the gate-source capacitance C GS is thus very quick as illustrated in Fig. 4A by the steep slope in the time profile of the gate-source voltage U GS . As is evident from Fig. 4B the internal impedance Z 1 of the discharge circuit 12 collapses at time t 1 from the relatively high value Z½ 1 to the relatively low value Z'' 1 in the region of zero. Whilst the relative high impedance Z½ 1 during the initial discharge phase is dictated by the current path 14 comprising the voltage divider R1 - R3, the relatively low internal impedance Z'' 1 results from the sum of the two negligably small output impedances of the closed, i.e. ON electronic switches N2, N4 of the current path16. By bypassing the resistor R3 by means of the closed electronic switch N5 the return ON point of the switching transistor N3 with respect to the OFF point is elevated, achieving an hysteresis. Accordingly, for a repeat ON of the switching transistor N3 a higher gate-source voltage U GS is necessary than is the case during switch-off. Since the gate electrode G of the MOS field-effect transistor T o in the OFF condition is loaded practically merely by the relatively low internal impedance Z'' 1 as determined by current path 16, it is impossible for any noise signals I S coupled into the circuit via the reverse capacitance C r to increase the gate voltage to such an extent that this could result in an unwanted repeat ON of the transistor T o .

Claims: A metal-oxide semiconductor (MOS) field-effect transistor (FET) gate control circuit comprising: a switchable discharge circuit (12) connected between a source (S) and a gate (G) of said MOSFET (To) wherein said discharge ciruit (12) comprises: a first current path (14) and a second current path (16) coupled to said gate (G) of said MOSFET wherein said first current path (14) has a substantially larger impedance than said second current path (16) and during turn-off of said MOSFET said first current path (14) is selected and said second current path (16) is deselected until the gate-source voltage (U GS ) of said MOSFET drops below a predetermined value (U GSB ) said current paths (14, 16) being connected in parallel, characterized in that both said second current path (16) and a bypass of a portion of said first current path (14) are selected via a switching transistor (N3) having its gate connected to a node in the first current path (14) when the gate-source voltage of said MOSFET drops below said predetermined value (U GSB ) such that the gate-source voltage of said MOSFET is discharged essentially only via said first current path (14) prior to reaching said predetermined value (U GSB ) and via said second current path (16) after reaching said predetermined value (U GSB ). The circuit of claim 1, wherein said first current path (14) and said second current path (16) are connected to said MOSFET via at least one electronic switch (N 1 , N 2 ), said electronic switch being controlled by a discharge signal. The circuit of claim 2, characterized in that said at least one electronic switch (N 1 , N 2 ) comprises a first electronic switch (N 1 ) connected in series to said first current path (14) and a second electronic switch (N 2 ) connected in series to said second current path (16). The circuit of any of the preceding claims, characterized in that said first current path (14) comprises a voltage divider. The circuit of any of the preceding claims, wherein said second current path (16) comprises a third electronic switch (N 4 ). The circuit of claim 5, characterized in that said third electronic switch (N 4 ) is controlled by said switching transistor (N 3 ). The circuit of any of the preceding claims, characterized in that said switching transistor (N 3 ) is connected to a constant current source (18). The circuit of any of the preceding claims 4 to 7, characterized in that said switching transistor (N 3 ) is controlled by a control voltage provided by said voltage divider. The circuit of claim 8, characterized by a fourth electronic switch (N 5 ) controlled by said switching transistor (N 3 ) through which said portion of said first current path (14) is bypassed to reduce said control voltage after said gate source voltage of said MOSFET drops below said predetermined value (U GSB ). The circuit of any of the preceding claims, characterized by a charging circuit (20) connected to said MOSFET to charge a capacitance between said gate and said source of said MOSFET which comprises a charging resistor (R L ) and a fifth electronic switch (N 6 ) connected in series with said charging circuit and controlled by a control charge signal.

Inventors: BAYER ERICH, BAYER, ERICH
Applicants: TEXAS INSTRUMENTS DEUTSCHLAND, TEXAS INSTRUMENTS DEUTSCHLAND GMBH
Application year: 1993
Main classification: H03K17
IPC codes: H03K17