Code search mode selection for radio pager

Abstract: In the event that a radio pager falls into frame async while receiving information, an appropriate code search mode is desirably selected. Firstly, a controller of the pager checks to see if a bit sync indicating signal obtained from a bit synchronizer demonstrates bit sync. If the bit sync indicating signal indicates bit synchronization, the controller selects an operation mode for searching for synchronization code (SC). On the other hand, if the bit sync indicating signal indicates for searching for synchronization code (SC). On the synchronization, the controller selects an operation mode for searching for synchronization code (SC). On the other hand, if the bit sync indicating signal indicates bit async, the controller selects a preamble code search mode. Accordingly, in the case where the pager becomes out of synchronism and immediately thereafter restores same during information acquisition, the pager is able to successfully obtain subsequent information by means of very simplified arrangement.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to a method of selecting an appropriate code search mode in a battery operated radio pager during data acquisition, and more specifically to such a method via which the most desirable code search mode is chosen when a pager falls into frame asynchronization or "frame async" while obtaining data. The present invention is able to attain an effective reduction in pager hardware for controlling code search modes. Description of Prior Art Radio paging systems have proven very popular and many efforts have been made to reduce their size, weight, and power consumption through the use of integrated circuits. In connection with power conservation, it is well known in the art to utilize battery saving circuits to minimize power consumption by periodically supplying power to high power drain circuitry in short bursts instead of continuously. Presently known battery saving circuits operating in such a type of radio pager, periodically supply power to a front end (viz., a high frequency receiver section), enabling the search for the presence of a preamble code. If the preamble is detected, the front end is further energized for ascertaining an initial synchronization codeword (SC). Following this, if the first SC is detected (viz., frame sync is established), an address which follows the first SC is checked if it coincides with a subscriber's identification (ID) or unique word. In the case where the address coincides with the subscriber's ID, a message directed to the subscriber is acquired. Before turning to the instant invention it is deemed advantageous to describe known techniques for selecting the most desirable pager's code search mode with reference to Figs. 1 to 5B Fig. 1 is a block diagram schematically showing a known arrangement of a battery operated radio pager 10. In Fig. 1, a front end 12 is provided for amplifying and demodulating a code-modulated carrier wave received by an antenna 14. The front end 12 is comprised of a high frequency amplifier, a frequency converter, an IF (Intermediate Frequency) amplifier, and a discriminator (neither is shown). The front end 12 is periodically energized by a plurality of successive preamble search pulses which are applied thereto from a controller 16. The controller 16 usually takes the form of central processing unit (CPU) and is arranged to control the overall operations of the pager 10. The front end 12 is coupled, in addition to the controller 16, to a bit synchronizer 18, a preamble detector 20, a transmission (denoted by TX) rate detector 22, a frame sync code (SC) detector 24, and an address coincidence circuit 26. As shown in Fig. 1, the bit synchronizer 18 is coupled to the blocks 16, 20, 22, 24 and 26, while the controller 16 is coupled to the blocks 20, 22, 24 and 26. Further, the controller 16 is operatively coupled to a ROM (Read Only Memory) 28, a RAM (Random Access Memory) 30, an oscillator 32, a pager power switch 34, a battery 36, a driver 38, a display 40, a light source 42 such as a light emitting diode (LED), and a speaker 44. The ROM 28 is provided for storing a program which controls the overall operations of the pager 10, while the RAM 30 is used to define a work space required in connection with pager operations. The operations of the pager 10 shown in Fig. 1 will be described with reference to Figs. 2A-2B. Fig. 2A is a schematic representation of an incoming signal and the power applied to the front end 12 from the controller 16. The incoming signal takes the form of a standard code format proposed by the POCSAG (British Post Office Standardization Advisory Group). Although the present invention is not limited to such a code format, it is believed that a brief description thereof will facilitate a better understanding of this invention. According to the POCSAG specification, a transmission consists of a preamble (PA) followed by a plurality of batches 1, 2, ... each of which includes one synchronization code (SC) and eight (8) frames as shown in Fig. 2A. The transmission ceases when there are no further calls. Each transmission starts with a preamble to permit the recipient pager to attain bit synchronization. The preamble is a pattern of reversals, 101010..., repeated for a period of at least 576 bits. Although only two of preamble search pulses Pa are shown in Fig. 2A, it is well known in the art that the controller 16 continues to periodically supply pulses Pa until the preamble detector 20 (Fig. 1) detects a preamble. As shown in Fig. 2A, it is assumed that the detector 20 (Fig. 1) has been able to specify a preamble during a preamble search mode at a pulse Pa (second occurrence in Fig. 2A). When the preamble detector 20 defines the preamble, the controller 16 is responsive to this (via a line L1) and extends power supply to the front end 12. Further, the controller 16 induces the frame sync code detector 24 (via a line L2 (Fig. 1)) to search for the SC which follows the detected preamble (viz., SC search mode). If the detector 24 ascertains the SC as in the case shown in Fig. 2A, the detector 24 advises the controller 16 of the detection of the SC via a line L3. Following this, the controller 16 periodically supplies the front end 12 with a plurality of frame sync pulses Pf for acquiring data included in a predetermined frame of each batch (viz., frame search mode). Information which is indicative of the location of the data in the predetermined frame of each batch, has previously been stored in the ROM 28. An address is transmitted in the first batch 1. If the address coincidence circuit 26 ascertains that the address located in the first batch 1 coincides with the subscriber's ID (which is applied thereto from the ROM 28 via a line L4), the circuit 26 informs the controller 16 of the address coincidence via a line L5. Subsequently, the controller 16 activates the driver 38 and alerts the subscriber using the speaker 44 and/or the LED 42. Further, the message received is exhibited on the display 40. Fig. 2B is a diagram showing "frame async" which undesirably occurs in the incoming signal while the pager 10 acquires the message directed thereto. Further, Fig. 2B also shows the intermittent power supply to the front end 12. Once the aforesaid frame async occurs during the message or data acquisition, the controller 16 fails to obtain the data during the frame sync pulse Pf. Thus, the controller 16 assumes that the incoming signal terminates. As a result, even if the frame sync is restored immediately after the frame sync pulse Pf, the controller 16 has already moved into the preamble search mode and thus, is applying preamble search pulses Pa to the front end 12 for detecting the next preamble as shown in Fig. 2B. This means that the pager 10 no longer acquires the complete data directed thereto. In order to eliminate the above-mentioned problem, the pager 10 shown in Fig. 1 is provided with the transmission (TX) rate detector 22. Fig. 3 is a block diagram showing the arrangement of the TX rate detector 22 of Fig. 1. As shown, the arrangement shown in Fig. 3 is provided with an edge detector 50, a window signal generator 52, a discriminator 54, an up/down counter 56, and a comparator 58, all of which are coupled as illustrated. The operations of the arrangement of Fig. 3 will be described with reference to timing charts depicted in Fig. 4. The edge detector 50 is supplied with the demodulated digital signal Sfe from the front end 12 and outputs a signal Sed which includes a series of pulses Sed' each of which is generated at leading and trailing edges of the signal Sfe. The window signal generator 52 receives bit sync clock Csync from the bit synchronizer 18 and outputs a signal Sw which includes a series of window pulses Sw'. Each of the window pulses Sw' is produced by counting reference clocks applied thereto from the controller 16 after detecting the trailing edge of the bit sync clock Csync. The discriminator 54 outputs two signals Pwi and Pwo. More specifically, the discriminator 54 generates a pulse Pwi' if the edge pulse Sed' is generated within the window pulse Sw'. Contrarily, the discriminator 54 outputs a pulse Pwo' in the case where the edge pulse Sed' is generated outside of the window pulse Sw'. The pulses Pwi' and Pwo' thus generated are applied to the up/down counter 56. The counter 56 operates such as to increase and decrease the content thereof in response to the pulses Pwi' and Pwo', respectively. The output of the counter 56 (denoted by Cout) is applied to the comparator 58 to which a reference value (eight (8) for example) is also applied from the controller 16. When the output Cout of the counter 56 exceeds the reference value, the comparator 58 supplies the controller 16 (via a line L6) with the output thereof (denoted by CP) which in this instance assumes a logic 1 (for example). The controller 16 determines that the signal applied to the front end 12 is a calling signal if the output CP of the comparator 58 assumes a logic 1. Contrarily, if the output CP assumes a logic 0, the controller 16 determines that the signal applied to the pager is simply noise. As shown in Figs. 1 and 3, the controller 16 applies the above-mentioned reference value to the comparator 58 via a line L7, and also applies a reference clock to the blocks 50 and 52 via a line L8. Further, the controller 16 applies a bit sync reference signal Cref to the bit synchronizer 18. Reference is made to Fig. 5A. In the event that the controller 16 (Fig. 1) is informed of frame async from the detector 24 (see Fig. 2B) while the pager 10 receives a message, the controller 16 examines the output CP of the comparator 58. If the output CP assumes a logic 1, this means that the pager 10 is still receiving the message. Therefore, as shown in Fig. 5A, the controller 16 extends the power supply to the front end 12 (viz., the pager 10 enters into the SC search mode). If the frame async terminates at a time point T1, the controller 16 is able to restore frame sync using the following SC. Thus, the pager 10 is able to obtain the complete message directed thereto using the subsequent frame sync pulses Pf as shown in Fig. 5A. On the other hand, if the output CP assumes a logic 0 during the frame search mode, the controller 16 determines that the incoming signal terminates and the pager 10 is now receiving noise. In this case, the controller 16 moves into the preamble search mode as best shown in Fig. 5B. As mentioned above, the known arrangement of Fig. 1 inevitably requires the transmission (TX) detector 22 for implementing the aforesaid code mode selection. However, it is highly desirable to omit the detector 22 for the purposes of reducing the pager's size, weight, and power consumption in addition to simplifying the arrangement. GB 2,144,565 describes a pager responsive to a transmission which includes a preamble sequence followed by batches each containing a synchronization word followed by a plurality of address and/or message words, the decoder being operative to detect a single synchronization word. Thereafter, the decoder searches in its specific frame in each batch by means of a clock which has been synchronized with the transmission and which provides the timing for searching in the specific frame of all subsequent batches. The clock may have coarse and fine modes of timing control, the coarse mode being applicable when initial bit synchronization is being attained and the fine mode being applied subsequently to reduce the risk of the clock drifting out of synchronization. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of selecting the most desirable code search mode when a pager falls into "frame async" during data acquisition without the need for the circuitry which is dedicated to the above-mentioned mode selection. It is another object of the present invention to provide a method of selecting the most desirable code search mode when a pager falls into "frame async" during data acquisition without the use of the transmission rate detector of the prior art. In a first aspect, the present invention provides a method of selecting between a preamble search mode and a frame search mode when a pager falls into frame asynchronization during said frame search mode, said pager including a front end, a bit synchronizer and a controller, said bit synchronizer being coupled to said front end and said controller and generating a clock in synchronization with bits of an incoming signal applied thereto from said front end, said method comprising the steps of: (a) determining, at said controller, that said bit synchronizer has gone out of bit synchronization by comparing a phase of a signal, which is produced based on said incoming signal, to a phase of said clock, and providing an output signal indicative of the determination; (b) selecting said frame search mode, by periodically issuing frame synchronization pulses from said controller, when said bit synchronizer immediately restores the bit synchronization as indicated by said output signal; and (c) selecting said preamble search mode by periodically applying preamble search pulses to said front end from said controller, when said synchronizer fails to immediately restore the bit synchronization as indicated by said output signal. In a second aspect, the present invention provides a pager for selecting between a preamble search mode and a frame search mode when said pager falls into frame asynchronization during said frame search mode, said pager comprising: a front end; a controller; and a bit synchronizer, coupled to said front end and controller, for generating a clock in synchronism with bits of an incoming signal applied thereto from said front end and producing a signal based on said incoming signal, said controller being arranged to determine that said bit synchronizer has gone out of bit synchronization by comparing a phase of said signal with a phase of said clock, and providing an output signal indicative of said determination; said controller being arranged to select said frame search mode, by periodically issuing frame synchronization pulses to said front end, when said bit synchronizer immediately restores the bit synchronization as indicated by said output signal, and to select said preamble search mode, by periodically applying preamble search pulses to said front end, when said bit synchronizer fails to immediately restore the bit synchronization as indicated by said output signal. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become more clearly appreciated from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a block diagram schematically showing a known arrangement of a pager, referred to in the opening paragraphs of the instant disclosure; Figs. 2A and 2B are diagrams depicting the code search operation modes of the arrangement shown in Fig. 1; Fig. 3 is a block diagram showing in detail one block of the arrangement of Fig. 1; Fig. 4 is a timing chart depicting the operations which occur in the arrangement shown in Fig. 3; Figs. 5A and 5B are diagrams which demonstrate the code search modes of the arrangement of Fig. 1; Fig. 6 is a block diagram schematically showing an arrangement of a pager to which the present invention is applicable; and Fig. 7 is a block diagram showing one block of Fig. 6 which is pertinent to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is now made to Fig. 6, wherein a pager 10' embodying the instant invention is schematically illustrated in block diagram form. The arrangement of Fig. 6 differs from that of Fig. 1 in that the former arrangement is not provided with the transmission (TX) rate detector 22. Other than this, the arrangement of Fig. 6 is similar to that shown in Fig. 1, except as hereinafter described. In order to effectively achieve the above-mentioned code search mode selection upon the pager 10' falling into "frame async" during receiving a message, a bit synchronizer 18' applies a bit sync indicating signal S b to the controller 16. Fig. 7 is a block diagram showing the arrangement of the bit synchronizer 18' which is pertinent to the present invention. As shown in Fig. 7, the bit synchronizer 18' includes an edge detector 70, a phase comparator 72, and a bit synchronized clock generator 74. The controller 16 applies the bit sync reference clock (denoted by Cref) to the edge detector 70 and the bit synchronized clock generator 74. The reference clock Cref is 16,384Hz (512Hz x 32) for example. The bit synchronized clock generator 74 takes the form of variable frequency divider and produces a bit synchronized clock of 512Hz when bit sync is established. The edge detector 70 is essentially identical to the edge detector 50 of Fig. 3 and produces a series of pulses each of which has a predetermined pulse width and which is generated at each of the leading and trailing edges of the demodulated digital signal Sfe. The edge indicating pulses outputted from the edge detector 70, are applied to the phase comparator 72 which is supplied with the bit sync clock Csync from the clock generator 74. In the case where a calling signal such as shown in Fig. 2A is applied to the front end 12, the phase difference detected at the phase comparator 72 is gradually reduced due to the feedback loop including the blocks 72 and 74. When the bit synchronization is established, the bit sync indicating signal S b exhibits zero value in that the phase difference in the output of the phase comparator 72 is rendered zero. When the preamble detector 20 ascertains a preamble, the bit synchronizer 18' has established bit sync. It is assumed that the pager 10' enters into the frame search mode after completing the above-mentioned SC search mode. During the frame search mode, if the controller 16 detects "frame async" as mentioned above in connection with Fig. 2B, the bit sync indicating signal S b no longer indicates "zero value". This is because the synchronized state of the pager 10' implies "bit async" at the bit synchronizer 18' . In this case, if the controller 16 detects the bit sync recovery by monitoring the bit sync indicating signal S b the controller 16 extends the supply of power to the front end 12. Thus, the frame sync code detector 24 is able to search for a SC (viz., SC search mode) as mentioned in connection with Fig. 2A. On the other hand, if the controller 16 detects that the bit sync is not restored, the controller 16 applies a series of preamble search pulses Pa as discussed regarding Fig. 2B (this means that the pager 10' enters into the preamble search mode). The bit synchronizer 18' itself is known in the art except that the bit sync indicating signal is used for the above-mentioned best mode selection when the pager falls into frame async. As seen from the foregoing, the present invention in its preferred embodiment effectively reduces the pager's size, weight, and power consumption and simplifies the circuitry. It will be understood that the above disclosure is representative of only one possible embodiment and that various modifications can be made without departing from the concept of the instant invention as defined by the claims.

Claims: A method of selecting between a preamble search mode and a frame search mode when a pager falls into frame asynchronization during said frame search mode, said pager including a front end (12), a bit synchronizer (18') and a controller (16), said bit synchronizer being coupled to said front end and said controller and generating a clock in synchronization with bits of an incoming signal applied thereto from said front end, said method comprising the steps of: (a) determining, at said controller, that said bit synchronizer has gone out of bit synchronization by comparing a phase of a signal, which is produced based on said incoming signal, to a phase of said clock, and providing an output signal indicative of the determination; (b) selecting said frame search mode, by periodically issuing frame synchronization pulses from said controller, when said bit synchronizer immediately restores the bit synchronization as indicated by said output signal; and (c) selecting said preamble search mode, by periodically applying preamble search pulses to said front end from said controller, when said synchronizer fails to immediately restore the bit synchronization as indicated by said output signal. A method as claimed in Claim 1, wherein said bit synchronizer includes: first means (70) for producing said signal which includes a series of pulses, each of which being generated at leading and trailing edges of said incoming signal; means (72) coupled to said first means and for receiving said series of pulses therefrom, said second means generating said output indicative of a phase difference between each of said pulses and said clock which is to be synchronized with said bits of said incoming signal; and third means (74) arranged to receive said output of said second means and to generate said clock, said third means feeding back said clock to said second means; and wherein said controller (16) is arranged to receive said output of said second means and select between said preamble search mode and said frame search mode based on said output. A method as claimed in Claim 1 or 2, further comprising the steps of: producing said signal which includes a series of pulses, each of which being generated at leading and trailing edges of said incoming signal; generating said output indicative of a phase difference between each of said pulses and said clock which is to be synchronized with said bits of said incoming signal; and generating said clock based on said output. A pager for selecting between a preamble search mode and a frame search mode when said pager falls into frame asynchronization during said frame search mode, said pager comprising: a front end (12); a controller (16); and a bit synchronizer (18'), coupled to said front end (12) and controller (16), for generating a clock in synchronism with bits of an incoming signal applied thereto from said front end and producing a signal based on said incoming signal, said controller being arranged to determine that said bit synchronizer has gone out of bit synchronization by comparing a phase of said signal with a phase of said clock, and providing an output signal indicative of said determination; said controller being arranged to select said frame search mode, by periodically issuing frame synchronization pulses to said front end, when said bit synchronizer immediately restores the bit synchronization as indicated by said output signal, and to select said preamble search mode, by periodically applying preamble search pulses to said front end, when said bit synchronizer fails to immediately restore the bit synchronization as indicated by said output signal. A pager as claimed in Claim 4, wherein said bit synchronizer includes; means (70) for producing said signal which includes a series of pulses, each of which being generated at leading and trailing edges of said incoming signals; second means (72) coupled to said first means (70) and for receiving said series of pulses therefrom, said second means generating said output indicative of a phase difference between each of said pulses and said clock which is to be synchronized with said bits of said incoming signal; and a third means (74) arranged to receive said output of said second means to generate said clock, said third means feeding back said clock to said second means.

Inventors: KURAMATSU HIROYASU, KURAMATSU, HIROYASU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H04Q7
IPC codes: H04L7, H04W88