Apparatus for generating a trigger signal used to transmit an ultrasonic wave

Abstract: An apparatus for generating a trigger pulse signal to be used for transmitting an ultrasonic wave includes a reference signal generator (11) for generating a reference signal (a) as a reference to the generation of the trigger pulse signal (i), a pulse generator (15, 25) for generating the trigger pulse signal after the elapse of a delay time from the reference signal (a), and a delay time control circuit (12, 13a,13b, 14a, 14b) for controlling the delay time. The delay time control circuit includes a multi-phase clock generator (12) for generating a plurality of clock signals of different phases from each other, a clock selector (13a, 13b) for selecting one or more of the clock signals, and a pulse generation start circuit (14a) for supplying a signal (h1) to start the generation of the trigger pulse signal by the pulse generator (15, 25) in accordance with a count derived by counting one (g1) of the clock signals selected by the clock selector (13a, 13b).

Description: The present invention relates to an apparatus for generating a trigger pulse (so-called delayed pulse generator) used to generate an ultrasonic wave in an ultrasonic diagnose equipment or an ultrasonic doppler blood flow measurement equipment. Description of the Related Art In the ultrasonic diagnose or ultrasonic doppler blood flow measurement equipment, offset trigger signals are applied to a plurality of ultrasonic transducing elements of an ultrasonic transducer to trigger them in order to focus or deflect an ultrasonic transmission beam. In order to generate the offset trigger pulses and apply them to the ultrasonic transducer, the prior art ultrasonic diagnose equipment comprises, as shown in Fig. 5, a start of transmission reference signal generator 31 for sending a reference pulse signal a to start the transmission, a delay line circuit 32 for converting the reference pulse signal a to a number of transmission start signals b1, b2, b3, ....., bn which are delayed from each other by a predetermined time, a pulse oscillation circuit 33 for converting the transmission start pulse signals to trigger pulse signals c1, c2, c3, ....., cn having desired frequencies and numbers of waves, and a transducer drive circuit 34 for converting the trigger pulse signals c1, c2, c3, ....., cn to high voltage transmission pulse signals 1, d2, d3, ....., dn. The transmission pulse signals produced by the transducer drive circuit 34 are supplied to a transducer 35 which sends ultrasonic pulses e1, e2, e3, ....., en to a human body. The pulse oscillation circuit 33 has n RC burst oscillation circuits which produce the trigger pulse signals c1, c2, c3, ....., cn by oscillation. The oscillation frequencies of the respective oscillation circuits (the pulse frequencies of the trigger pulse signals) are determined by resistors and capacitors of the oscillation circuits. It is therefore necessary to select the values of the resistors and the capacitors so that the oscillation frequencies meet the desired values. Waveforms of the pulse signals produced in the apparatus are shown in Fig. 6. The delays in the respective trigger pulse signals which are required for focusing and deflecting the transmission ultrasonic beams are introduced in the conversion by the delay line circuit 32. SUMMARY OF THE INVENTION In the prior art apparatus shown in Figs. 5 and 6, since all of the delay times for the respective trigger pulse signals are derived by the delay line of the delay line circuit 32, a delay line having a large delay time should be adopted. However, it is difficult to enhance a precision of the delay line having a large delay time. As a result, it is difficult to improve the precision of the delay time of the trigger pulse signals. Further, the adoption of the delay line having the large delay time means the increase of the amount of delay lines used and high frequency characteristics are required by the increase. This will leads to the increase of the cost of the trigger pulse generator and the increase of the circuit scale. Further, in the pulse oscillator 33 of the prior art apparatus, it is necessary to provide as many oscillators as the number n of pulses to be transmitted, and the circuit scale increases as the number n of pulses increases. Since the oscillators primarily comprise resistors and capacitors, the compactness is not attained and the precision of the oscillation frequencies is degraded by the instability factors of constants inherent to the resistors and the capacitors. DE 3440853 A (= US Patent 4,611,494)discloses an ultrasonic imaging apparatus using digital control to delay the transmission of pulses. A single clock signal is selected and used to start the pulses, to determine their duration and to stop the pulses. This has disadvantages that the state of the transmitter to which the pulse signal is applied may be influenced and the duration of the output signal can only be coarsely adjusted. It is an object of the present invention to provide a trigger pulse generator which alleviates at least some of the problems encountered in the prior art. In order to achieve the above object, in accordance with one aspect of the present invention, there is provided an apparatus for generating a trigger pulse signal to be used for generating an ultrasonic wave comprising: reference signal generation means for generating a reference signal as a reference to the generation of the trigger pulse signal; pulse generation means for generating the trigger pulse signal after the elapse of a delay time from the reference signal, and delay time control means for controlling the delay time; said delay time control means including multi-phase clock generation means for generating a plurality of clock signals of different phases from each other, clock selection means for selecting two or more of the clock signals, pulse generation start means for supplying a start signal to start the generation of the trigger pulse signal by said pulse generation means in accordance with a count derived by counting one of the clock signals selected by said clock selection means and pulse generation stop means for producing a stop signal to stop the oscillation of the trigger pulse signal by said pulse generation means in accordance with a count derived by counting another of the clock signals selected by said clock selection means. In accordance with the present apparatus, the delay time before the generation of the trigger pulse signal is a sum of a first time corresponding to a phase shift of the one of the clock pulses selected by the clock selector and a second time required to count up the one of the clock pulses selected by the clock selector to a predetermined count. Accordingly, even if a delay line is used as the multi-phase clock generator, the maximum delay time of the delay line is shorter than one period of the clock signal and the delay time of the delay line is much smaller than that in at least some of the prior art apparatus. Accordingly, in accordance with the present apparatus the precision of the delay line may be enhanced without increasing the cost and hence the precision of the delay time of the trigger pulse may be enhanced without the increase of cost. The pulse generator may further include a control circuit for controlling at least one of frequencies, duty factors and the numbers of pulses of the trigger pulses in accordance with a count derived by counting one of the clock signals selected by the clock selector. In this case, since at least one of the frequencies, duty factors and the numbers of pulses of the trigger pulse signals are controlled in accordance with the count of one of the clock signals, a circuit corresponding to the pulse oscillation circuit 33 in the prior art apparatus is not necessary. Accordingly, the apparatus is reduced in size and the precision is enhanced. Where the delay time control unit includes the pulse generation stop circuit, the clock selector may select two of the clock signals, the pulse generator may include a control circuit which controls the frequencies and the duty factors of the trigger pulse signals in accordance with a count derived by counting the one of the two clock signals selected by the clock selector, and the pulse generation stop circuit mat include a circuit for producing the signal to stop the generation of the trigger pulse signals by the pulse generator in accordance with a count derived by counting the other of the two clock signals selected by the clock selector. Where the delay time control unit includes the pulse generation start circuit, the pulse generator may include a control circuit for logically operating the signal to start the generation of the trigger pulse signal supplied to the pulse generation start circuit and the signal to stop the generation of the trigger pulse signal supplied to the pulse generation stop circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram of a trigger pulse generator in accordance with a first embodiment of the present invention, Fig. 2 shows waveforms of signals in the circuit of Fig. 1, Fig. 3 shows a block diagram of a trigger pulse generator in accordance with another embodiment of the present invention, Fig. 4 shows waveforms of signals in the circuit of Fig. 3, Fig. 5 shows a block diagram of a prior art trigger pulse generator, and Fig. 6 shows waveforms of signals in the circuit of Fig. 5. DESCRIPTION OF THE PREFERRED EMBODIMENTS An apparatus for generating the trigger pulse to be used for generating the ultrasonic wave in accordance with the present invention is now explained with reference to the drawings. <First Embodiment> A trigger pulse generator in accordance with a first embodiment comprises, as shown in Fig. 1, a transmission start reference signal generator 11 for generating a reference signal a for the start of transmission, a high frequency multi-phase clock generator 12 for generating a plurality of high frequency clock signals f1, f2, ....., fm having phases thereof shifted from each other, in synchronism with the reference signal a, a first clock selector 13a for selecting one of the high frequency multi-phase clocks f1, f2, ....., fm to output it as a signal g1, a second clock selector 13b for selecting another one of the high frequency multi-phase clock signals to output is as a signal g2, a first counter 14a for counting the high frequency clock signal gl and producing an output signal h1 when the count reaches a predetermined count M, a second counter 14b for counting the high frequency clock signal g2 and switching the output signal h2 from a high level to a low level when the count reaches a predetermined count N (N>M), and a third counter 15 for cyclically counting the high frequency clock gl during the period from the switching of the signal h1 form the high level to the low level to the switching of the signal h2 from the high level to the low level and producing a pulse as a trigger pulse signal i which is switched from the high level to the low level and from the low level to the high level each time the count reaches sequential preset counts Yu and Yi, respectively. In the present embodiment, the third counter 15 forms a pulse generator which generates the trigger pulse signal after the elapse of the delay time from the reference signal. The high frequency multi-phase clock generator 12, the first clock selector 13a, the second clock selector 13b, the first counter 14a and the second counter 14b form the delay time control unit which controls the delay time. When the pulse generator is used for the ultrasonic diagnose equipment, the trigger pulse signal i outputted from the third counter 15 is supplied to the transducer drive circuit of the ultrasonic diagnose equipment, as it is in the prior art apparatus shown in Fig. 5. While a configuration for one transmission channel is shown in Fig. 1, as many combinations of the clock selectors 13a and 13b, the counters 14a and 14b and the third counter 15 as the number of transmission channels may be provided for the multi-channel configuration. The apparatus shown in Fig. 1 operates as follows. The reference signal a generated by the transmission start reference signal generator 11 is sent to the high frequency multi-phase clock generator 12, the first counter 14a and the second counter 14b. When the high frequency multi-phase clock generator 12 receives it, it outputs the m high frequency clock signals f1, f2, ....., fm which are synchronous with the reference signal a as shown in Fig. 2. The high frequency clock signals f1, f2, ....., fm may have the same frequency and phases thereof shifted from each other. A time difference between the two adjacent high frequency clock signals is set to Tc/m where Tc is a period of the high frequency clock signals. The high frequency multi-phase clock generator 12 for this purpose may be constructed by a delay line having a much smaller delay time than that of the delay line of the delay line circuit 32 of the prior art apparatus. The high frequency multi-phase clock generator 12 may be a product TQW-100 marketed by a Japanese corporation Showa Electric Wire & Cable Co., Ltd. Of the m high frequency clock signals, two clock signals g1 and g2 are selected by the first clock selector 13a and the second clock selector 13b, respectively, and they are sent to the first counter 14a and the second counter 14b, respectively. The counts M and N are preset in the first counter 14a and the second counter 14b, respectively. The counts M and N may be modified in response to an external control signal. After the first counter 14a and the second counter 14b are reset by the reference signal a, they start to count, and when the counts thereof reach the preset counts M and N, respectively, the counter outputs h1 and h2 are changed from the high level to the low level (or vice versa), respectively. Assuming that the first clock selector 13a selects the X-th high frequency clock fx of the high frequency multi-phase clock signals and the preset count of the first counter 14a is M, the output h1 of the first counter 14a is changed from the high level to the low level after the elapse of the time Tc(X/m+M) from the time when the reference signal a was received (in the present embodiment it is a fall time of the reference signal a although it may be a rise time of the reference signal a). The elapse time corresponds to the delay time of the trigger pulse signal i generated by the third counter. The third counter 15 receives the output h1 as the count start command signal and start to count the high frequency clock signal g1 after the output h1 has changed form the high level to the low level, that is after the elapse of the delay time. The count Yu for defining the period to maintain the output i at the high level and the count Yi for defining the period to maintain the output i at the low level are preset in the third counter 15 (the counts Yu and Yi may be modified in response to an external control signal) so that the third counter 15 maintains the output i at the high level until it counts the high frequency clock signal g1 by Yu. Immediately after the count reaches Yu, the output i is changed to the low level and the output Yi is maintained at the low level until the count reaches Yi. Then, the output i is again changed to the high level. The third counter 15 repeats the above operation to output the trigger pulse signals i and stops the counting when the output h2 sent from the second counter 14b changes from the high level to the low level. The period of the trigger pulse signals i produced by the third counter 15 is Tc(Yu+Yi) and a reciprocal thereof is a frequency. A duty factor of the trigger pulse signal is Yu/(Yu+Yi). A length of a pulse train of the trigger pulse signals is determined by the preset count N of the second counter 14b and the high frequency multi-phase clock signal fz (Z-th high frequency clock signal) selected by the second clock selector 13b and it is given by Tc{(X-Z)/m+(M-N)} Where the preset count Yu for the third counter 15 is set to the maximum count of the third counter 15, the preset count Yi is set to 0 and the third counter 15 is configured to be reset by the output h2 of the second counter 14b, the third counter 15 outputs the trigger pulse signal i having only one pulse. The width of one pulse of the trigger pulse signal i is given by Tc{(X-Z)/m+(M-N)} In the trigger pulse generator of the first embodiment, the trigger pulse signal having any number of pulses from one to a multiple may be generated in various states. Since the delay time of the pulse is Tc(X/m+M), the length of the delay may be controlled by changing the clock period Tc of the high frequency multi-phase clock signal generated by the high frequency multi-phase clock generator 12, the number m of phases thereof, the selection number X of the first clock selector 13a and/or the preset count M of the first counter 14a. Since the delay time has a minimum unit of Tc/m which is small, the delay time may be set precisely. By increasing the frequency of the high frequency multi-phase clock signal, the unit may be further reduced. The frequency and the duty factor of the trigger pulse signal may be controlled by changing the preset count Yu or Ti of the third counter 15. The length of the pulse train which determines the number of pulses contained in the trigger pulse signal may be controlled by changing the selection value Z of the second clock selector 13b and the preset count N of the second counter 14b. The high frequency clock signal to be sent to the second counter 14b may be the high frequency clock g1 selected by the first clock selector 13a. In order to output the last pulse of the pulse train in a complete form, it is desirable to stop the generation of the pulse by the clock signal g2 which is phase-delayed from the clock signal g1. <Second Embodiment> As shown in Fig. 3, a trigger pulse generator in accordance with a second embodiment is provided with a logic operation circuit 25 which receives the output h1 of the first counter 14a and the output h2 of the second counter 14b. The logical operation circuit 25 is a substitution of the third counter 15 in the trigger pulse generator of the first embodiment (Fig. 1). Other configuration is identical to that of the trigger pulse generator of the first embodiment. As shown in Fig. 4, the logical operation circuit 25 performs an logical operation (for example, exclusive OR function) to the outputs h1 and h2 of the first and second counters 14a and 14b. It outputs a trigger pulse signal having one pulse which is at the high level only when the levels of the outputs h1 and h2 differ. The delay time of the trigger pulse signal is same as that in the first embodiment. The pulse width of the one pulse contained in the trigger pulse signal is given by Tc{(X-Z)/m+(M-N)} Where the logical operation circuit 25 is used, it is not necessary to set the preset counts Yu and Ti as opposed to the third counter 15 in the first embodiment. However, the trigger pulse signal generated contains only one pulse. The trigger pulse generators shown in the first and second embodiments may generate high precision and stable trigger pulses because they do not use the large delay time delay line and analog passive components such as resistors and capacitors which raise the problems of instability of constants with surrounding temperature and the scatter of constants but fully comprise digital components. Since the digital circuit components may be implemented by a gate array, the size of the apparatus is reduced and the cost is reduced. The present trigger pulse generator may be used to generate the trigger pulse in various equipments including the ultrasonic diagnose equipment and the ultrasonic doppler blood flow measurement equipment. As is apparent from the above description, the trigger pulse generator of the present invention has a high precision and stable characteristic because it primarily comprises the digital circuit components. Further, since the minimum unit to adjust the delay time of the pulse generation is small, the delay time can be precisely set. Further, since the pulse width of the pulse generated, the rise and fall times thereof and the pulse stop time are controlled by the counts of the clocks, the risk of change of the generated pulse by the change of environment is eliminated. In addition, by implementing the digital circuit by the gate array, the apparatus is reduced in size and the manufacturing cost may be reduced.

Claims: An apparatus for generating a trigger pulse signal to be used for generating an ultrasonic wave comprising: reference signal generation means (11) for generating a reference signal (a) as a reference to the generation of the trigger pulse signal (i); pulse generation means (15, 25) for generating the trigger pulse signal after the elapse of a delay time from the reference signal (a); and delay time control means (12, 13a,13b, 14a, 14b) for controlling the delay time; said delay time control means including multi-phase clock generation means (12) for generating a plurality of clock signals of different phases from each other, clock selection means (13a, 13b) for selecting two or more of the clock signals, pulse generation start means (14a) for supplying a start signal (h1) to start the generation of the trigger pulse signal by said pulse generation means (15, 25) in accordance with a count derived by counting one (g1) of the clock signals selected by said clock selection means (13a, 13b), and pulse generation stop means (14b) for producing a stop signal (h2) to stop the oscillation of the trigger pulse signal by said pulse generation means (15, 25) in accordance with a count derived by counting another (g2) of the clock signals selected by said clock selection means (13a, 13b). An apparatus for generating a trigger pulse signal according to Claim 1 wherein said pulse generation means further includes means (15) for controlling a frequency, a duty factor and the number of pulses of the trigger pulse signal in accordance with a count derived by counting one (g1) of the clock signals selected by said clock selection means (13a, 13b). An apparatus for generating a trigger pulse signal according to Claim 1 wherein said clock selection means (13a, 13b) selects two of the clock signals, said pulse generation means (15, 25) includes means (15) for controlling a frequency and a duty factor of the trigger pulse signal in accordance with a count derived by counting one (g1) of the two clock signals selected by said clock selection means (13a, 13b), and said pulse generation stop means (14b) includes means for producing the stop signal (h2) to stop the generation of the trigger pulse signal by said pulse generation means (15, 25) in accordance with a count derived by counting the other (g2) of the two clock signals selected by said clock selection means (13a, 13b). An apparatus for generating a trigger pulse signal according to Claim 1 wherein said pulse generation means includes means (25) for receiving and performing a logical operation on the start signal (h1) and the stop signal (h2).

Inventors: NAKAMURA YASUHIRO, TANNAKA YOSHINAO, WATANABE YOSHINOBU, NAKAMURA, YASUHIRO, TANNAKA, YOSHINAO, WATANABE, YOSHINOBU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1993
Main classification: G10K11
IPC codes: G05B24, G10K11, G06F1, A61B8, H03K5