Semiconductor logic circuit

Abstract: A semiconductor logic circuit includes a plural number of gate circuits (10,20) and a voltage supply (5). Each of the gate circuits (10,20) includes a series circuit (13,23) comprising the same plural number of transistors of one conductivity type connected in series, and a parallel circuit (16,26) comprising the same plural number of transistors of a different conductivity type connected in parallel. The series and parallel circuits (13,23;16,26) are connected in series between a voltage supply (5) and ground. The semiconductor logic circuit includes further the same plural number of input pins (1,2), and an output pin (6) connected in common to all of the plural number of gate circuits (10,20). Each of the input pins (1,2) is connected to a different one of the transistors in the series circuit (13,23) and to a different one of the transistors in the parallel circuit (16,26) of each of the gate circuits (10,20). The control electrode of the k-th transistor from the end of each series circuit (13,23) closer to the voltage supply (5) is connected to a different one of the input pins (1,2), and the control electrode of the m-th transistor from the end of each parallel circuit (16,26) closer to the input pins (1,2) is connected to a different one of the input pins (1,2).

Description: The present invention relates to a logic circuit formed on a gate array integrated circuit which comprises rows of first conductivity type transistors alternating with rows of second conductivity type transistors and, in particular, to a multiple-input gate circuit including series combinations of a plurality of transistors of the same conductivity type the gate electrodes of which are connected to different input pins. BACKGROUND OF THE INVENTION Japanese Unexamined Patent Publication No. SHO 59-23924 discloses a dual-input gate circuit. The dual-input gate circuit of this Japanese publication is shown in Figure 1. The circuit comprises a series circuit 13 including transistors 11 and 12 of a first conductivity type, and a parallel circuit 16 including transistors 14 and 15 of a second conductivity type. Series circuit 13 and parallel circuit 16 are connected in series between a voltage supply 5 and ground. The gate electrodes of transistors 11 and 14 are connected to an input pin 1, and the gate electrodes of transistors 12 and 15 are connected to an input pin 2. An output pin 6 is connected to the junction between circuits 13 and 16. The above-cited Japanese Unexamined Patent Publication No. SHO 59-23924 shows another dual-input gate circuit. As shown in Figure 3, this dual input gate circuit comprises the same circuit as the one shown in Figure 1, except that another series circuit 19 including transistors 17 and 18 is connected in parallel with series circuit 13. The gate electrode of transistor 17 is connected to input pin 2, and the gate electrode of transistor 18 is connected to input pin 1. In the circuit shown in Figure 1, let it be assumed that the supply voltage is +5V, and transistors 11 and 12 become non-conductive when the voltage at their gate electrodes are 0 volts, and become conductive when their gate voltage is +5V. On the other hand, transistors 14 and 15 become conductive when the gate voltage is 0V, and become non-conductive when the gate voltage is +5V. First, it is assumed that the voltage at input pin 1 is 0V, and that the voltage at input pin 2 is +5V. Then, transistors 11 and 15 are non-conductive, while transistors 12 and 14 are conductive. As a result, a voltage equal to the supply voltage is developed across transistor 11, and the voltage at output pin 6 becomes +5V. Next, assume that the voltage at input pin 1 changes to +5V, with input pin 5 being maintained at +5V. This renders transistors 11 and 14 conductive and non-conductive, respectively. This results in that a voltage equal to the supply voltage is developed across transistors 14 and 15, so that the voltage at output pin 6 becomes 0V. Conversely, if input pin 1 is at +5V and input pin 2 is at 0V, transistors 11 and 15 are conductive, while transistors 12 and 14 are non-conductive. Output pin 6 is then at +5V. If the voltage at input pin 2 is changed to +5V, while maintaining the voltage at input pin 2 at +5V, transistors 12 and 15 are rendered conductive and non-conductive, respectively. The result is that a voltage equal to the supply voltage appears across transistors 14 and 15, and output pin 6 assumes 0V. As explained above, when the voltage at either of input pins 1 and 2 changes from 0V to +5V, the voltage at output pin 6 changes from +5V to 0V. A problem is that the response time of the voltage at output pin 6 when the voltage at input pin 1 changes is different from the response time when the voltage at input pin 2 changes, as described below. When input pin 1 is at 0V and input pin 2 is at +5V, transistor 12 is conductive so that the end of transistor 11 of the transistor 12 side is at the ground potential or 0V. Accordingly, when the voltage at input pin 1 changes to +5V, it takes only a little time for the end of transistor 11 on the output pin side, and, hence, output pin 6 to assume the ground potential, since it is only transistor 11 that intervenes between output pin 6 and the transistor 12 side end of transistor 11. Conversely, when input pin 1 is at +5V and input pin 2 is at 0V, transistor 12 is non-conductive and, therefore, it is the ground side end of transistor 12 that is at the ground potential. Since two transistors 11 and 12 intervene, it takes a longer time for output pin 6 to assume the ground potential when the voltage at input pin 2 changes to +5V. Figure 3 shows a circuit which can eliminate the above-described defect and align the output response times, as proposed in Japanese Unexamined Patent Publication No. SHO 59-23924. The same reference numerals denote the same components used in the circuit shown in Figure 1. A series circuit 19 comprising transistors 17 and 18 having the same characteristics as transistors 11 and 12 is connected in parallel with series circuit 13, with the gate electrode of transistor 17 being connected to input pin 2 and with the gate electrode of transistor 18 being connected to input pin 1. In operation, when input pin 1 is at 0V and input pin 2 is at +5V, transistor 11 of circuit 13 remoter from the ground potential and transistor 18 of circuit 19 nearer to the ground potential are non-conductive, while, when input pin 1 is at +5V and input pin 2 is at 0V, transistor 12 of circuit 13 nearer to the ground potential and transistor 17 of circuit 19 remoter from the ground potential are cut off. Thus, for both input pin voltage conditions, the operating conditions of the circuit of Figure 3 are the same and, therefore, difference between the output responses encountered in the circuit of Figure 1 can be eliminated. However, there is a problem in the circuit shown in Figure 3. That is, when the circuit of Figure 3 is implemented in a gate array integrated circuit form, transistors in the integrated circuit are not efficiently used. The circuit of Figure 1 may be implemented by transistors arranged as shown in Figure 2. In Figure 2, rows of transistors of one conductivity type 100 and 102 alternate with rows of transistors of opposite conductivity type 101 and 103. Four transistors shown in Figure 1 are within an area 105 indicated by a broken-line rectangle in Figure 2, in which transistors 11 and 12 are in row 101 and transistors 14 and 15 are in row 102. On the other hand, the transistors of the circuit of Figure 3 may be arranged in the gate array integrated circuit, as shown in Figure 4, in which four transistors 11, 12, 17 and 18 are in row 101 and only two transistors in row 102 are used, as transistors 14 and 15. As a result, transistors 24 and 25 adjacent to transistors 17 and 18 within a rectangular -area 106 indicated by broken lines in Figure 4 cannot be used for other purpose and, hence, they are wasted. Another problem is that in both of the circuits shown in Figures 1 and 3, the internal impedance viewed from output pin 6 when either input pin 1 or 2 is at 0V is relatively high, because it is dependent on the internal resistance of one of transistors 14 and 15. Accordingly, these circuits are not suitable for driving a load of large current capacity. In view of the above-described disadvantages of the prior art circuits, an object of the present invention is to provide a semiconductor logic circuit which is free of difference in response time of output voltage at an output pin with respect to voltage changes at input pins, which has a reduced internal impedance viewed from the output pin, and which has increased device utilization efficiency. SUMMARY OF THE INVENTION This object is achieved by a semiconductor logic circuit as claimed in claims 1 and 3, respectively. In an advantageous development, n transistors provided outside each series circuit with which they are associated are connected in parallel, and the parallel circuit is connected in series with the associated series circuit between the power supply and ground. Each of the n input pins is also connected to the control electrodes of different ones of transistors in the respective parallel circuits, and the control electrode of the m-th transistor in each parallel circuit form the end of that parallel circuit closer to the input pins is connected to a different one of the input pins, where m is an integer of from 1 to n. Incidentally, in this application, the ordinal numbers, such as "first", "second" and "third", used for transistors in the series circuits denote the order of transistors from the end of the series circuits closer to the voltage supply. Similarly, the ordinal numbers used for transistors in the parallel circuits denote the order of transistors from the end of the parallel circuits closer to the input pins. In a further advantageous development, a semiconductor logic circuit comprises two three-input gate circuits each including a series circuit of three transistors, namely, first, second and third transistors from the power supply side, and three input pins, namely, first, second, and third input pins. The first input pin is connected to the control electrode of the first transistor of the series circuit in a first one of the two three-input gate circuits and also to the control electrode of the third transistor of the series circuit of a second one of the two three-input gate circuits. The second input pin is connected to the control electrodes of the second transistors of the series circuits of the first and second three-input gate circuits. The third input pin is connected to the control electrode of the third transistor of the series circuit of the first three-input gate circuit and to the control electrode of the first transistor of the series circuit of the second three-input gate circuit. Typical embodiments of the invention are considered. First, let it be assumed that n is equal to 2. The relation between two series circuits and two input pins is the same as the one of the prior art circuit shown in Figure 3. However, since the same number of transistors as the number of transistors in each series circuit can be used in an associated parallel circuit, the internal impedance viewed from the output pin side can be reduced, and, in addition, the efficiency of utilization of transistors on a substrate can be increased. When the number n=3, a first input pin is connected to the control electrode of the first transistor of a first series circuit, to the control electrode of the second transistor of a second series circuit, and to the control electrode of the third transistor of a third series circuit. A second input pin is connected to the the control electrode of the second transistor of the first series circuit, to the control electrode of the third transistor of the second series circuit, and to the control electrode of the first transistor of the third series circuit. A third input pin is connected to the control electrode of the third transistor of the first series circuit, to the control electrode of the first transistor of the second series circuit, and to the control electrode of the second transistor of the third series circuit. Thus, each input pin is connected to all of first, second and third transistors which respectively belong to different series circuits, and, therefore, the circuit conditions are equalized for the respective input pins. Thus, equal response characteristics are obtained for voltage changes at the respective input pins. The same relationship can exist between input pins and transistors forming series circuits when the number n is 4 or larger, too, so that the output responses to voltage changes at the respective input pins can be aligned. Furthermore, because, regardless of the number n, the number of transistors forming each series circuit is equal to the number of transistors forming an associated parallel circuit, the internal impedance when viewed from the output pin is low. In addition, the transistor utilization factor is high. In case of the aforementioned special case in which two three-input gate circuits each having a series circuit of three transistors are used, difference in response of the output voltage to voltage changes at the input pins is significant between voltage changes at the input pins connected to the first and third transistors of the respective series circuits, but difference in response is relatively small between voltage changes at the input pins connected to the first and second or second and third transistors of the respective series circuits. The responses of the output voltage to voltage changes at the first and third input pins can be aligned, as in the case of n=2, and the output response to voltage changes at the second input pin does not largely differ from them. Thus, differences in output response to voltage changes at the three input pins can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a circuit diagram of a conventional two-input gate circuits comprising a series combination of a series circuit of two transistors and a parallel circuit of two transistors. Figure 2 is a layout of the transistors of the two-input gate circuits of Figure 1 on a gate array integrated circuit substrate. Figure 3 is a circuit diagram of another example of conventional two-input gate circuit which includes a parallel combination of two series circuits each comprising two transistors. Figure 4 shows a layout of the transistors of the two-input gate circuit of Figure 3 on a gate array integrated circuit substrate. Figure 5 shows a semiconductor logic circuit which comprises two two-input gate circuits each including a series circuit of two transistors and a parallel circuit of two transistors. Figure 6 shows a layout of the transistors of Figure 5 on a gate array integrated circuit substrate. Figure 7 shows a semiconductor logic circuit according to the present invention which also comprises two dual-input gate circuits similar to the ones shown in Figure 5. Figure 8 shows a semiconductor logic circuit, in which the positions of the series circuit and the parallel circuit in each dual-input gate circuit shown in Figure 5 or 7 are reversed. Figure 9 shows a semiconductor logic circuit which comprises two three-input gate circuits each including a series circuit comprising three transistors and a parallel circuit comprising three transistors. Figure 10 shows a semiconductor logic circuit according to a further embodiment of the present invention which comprises three three-input gate circuits each including a series circuit comprising three transistors and a parallel circuit comprising three transistors. DESCRIPTION OF EMBODIMENTS Referring to Figure 5, a semiconductor logic circuit comprises N-channel MOS transistors 11, 12, 21 and 22. N-channel transistors 11 and 12 form a series circuit 13, and N-channel transistors 21 and 22 form another series circuit 23. P-channel transistors 14 and 15 form a parallel circuit 16, and P-channel transistors 24 and 25 form another parallel circuit 26. Series circuit 13 and parallel circuit 16 are connected in series with a power supply 5 and ground, to thereby form a dual-input gate circuit 10. Similarly, series circuit 23 and parallel circuit 26 are connected in series between power supply and ground, to thereby form a dual-input gate circuit 20. The configuration and operation of each of dual-input gate circuits 10 and 20 are the same as those of the prior art circuit shown in Figure 1. In the circuit shown in Figure 5, the gate electrodes of transistors 11, 14, 22 and 24 are connected to an input pin 1, and the gate electrodes of transistors 12, 15, 21 and 25 are connected to an input pin 2. The junction of circuits 13 and 16 and the junction of circuits 23 and 26 are connected in common to an output pin 6. Figure 6 shows a layout of the transistors used in the circuit of Figure 5 on a gate array integrated circuit chip. N-channel MOS transistors 11, 12, 21 and 22 are in a row 101 of N-channel MOS transistors, and P-channel MOS transistors 14, 15, 24 and 25 are in a row 102 of a different conductivity type transistors, namely, P-channel transistors. Like this, all of the transistors within an area indicated by a broken-line rectangle 106 are effectively utilized. The circuit shown in Figure 5 is considered in detail. In gate circuit 10, transistor 11 in series circuit 13, which is closer to voltage supply 5 is connected input pin 1, while transistor 12 remote from voltage supply 5 is connected to input pin 2. On the other hand, in gate circuit 12, transistor 22 of series circuit 23, which is remote from voltage supply 5 is connected to input pin 1, and transistor 21 closer to voltage supply 5 is connected to input pin 21. With this circuit arrangement, the operating conditions of series circuits 13 and 23 for input signals applied to input pins 1 and 2, respectively, can be equalized. Furthermore, since parallel circuits 16 and 26 are connected in parallel between output pin 6 and voltage supply 5, the circuit impedance viewed from output pin 6 is reduced to one half the impedance exhibited when only one such parallel circuit is used as in the prior art circuit shown in Figure 4. The circuit shown in Figure 7 is similar to the circuit shown in Figure 5, except the connection of the input pins to the transistors of the parallel circuits. Input pin 1 is connected to transistor 15 of parallel circuit 16, which is shown remote from input pin 1, and to transistor 24 of parallel circuit 26, which is shown closer to input pin 1, whereas input pin 2 is connected to transistor 14 of parallel circuit 16, which is shown closer to input pin 2, and to transistor 25 of parallel circuit 26, which is shown remote from input pin 2. With this circuit arrangement, in addition to compensation for difference in operating conditions caused by difference in connection between input pins and and transistors in series circuits present in the prior art circuit shown in Figure 1, difference in magnitude of input impedances caused by difference between distances from input pins to transistors in parallel circuits, as seen in the embodiment shown in Figure 5, can be compensated for. Thus, according to this embodiment, the operating conditions are aligned to a greater extent. The circuit shown in Figure 8 includes gate circuits 30 and 32 which differ from the circuit arrangement shown in Figure 5 in that series circuits 13 and 23 are closer to voltage supply 5 and parallel circuits 30 and 32 are closer to ground. With this circuit arrangement, as the circuit arrangement shown in Figure 5, operating conditions for input signals applied to input pins 1 and 2 can be aligned. In this circuit, too, by reversing the connections of the transistors in one of the two parallel circuits to input pins 1 and 2, the same effects as achieved in the circuit of Figure 7 can be achieved. The circuit shown in Figure 9 includes two three-input gate circuits 40 and 50. Three-input gate circuit 40 includes a series circuit 44 which comprises transistors 41, 42 and 43, and a parallel circuit 48 which comprises transistors 45, 46 and 47. Series circuit 44 is connected between a voltage supply 5 and an output pin 16, and parallel circuit 48 is connected between output pin 16 and ground. Similarly, three-input gate circuit 50 includes a series circuit 54 which comprises transistors 51, 52 and 53, and a parallel circuit 58 which comprises transistors 55, 56 and 57. Series circuit 54 is connected between voltage supply 5 and output pin 16, and parallel circuit 58 is connected between output pin 16 and ground. An input pin 1 is connected to the gate electrodes of transistors 41, 45, 53 and 55, an input pin 2 is connected to the gate electrodes of transistors 42, 46, 52 and 56, and an input pin 3 is connected to the gate electrodes of transistors 43, 47, 51 and 57. The circuit of Figure 9, if input pin 2 and transistors 42, 46, 52 and 56 were removed, would result in the circuit shown in Figure 8. In case that a series circuit comprises three transistors, as series circuits 44 and 54 of Figure 9, difference in operating conditions is relatively small between transistors 41 and 42, between transistors 42 and 43, between transistors 51 and 52, and between transistors 52 and 53, but it will be significant between uppermost transistor 41 and lowermost transistor 43 in series circuit 44 and between uppermost transistor 51 and lowermost transistor 53 in series circuit 54. Accordingly, the technique shown in Figure 9 is to compensate for difference between the operating condition for input signal changes at input pin 1 and the operating condition for input signal changes at input pin 3, which could be caused by the difference in position of uppermost and lowermost transistors 41 and 43, and 51 and 53, by means of the technique shown in Figure 8. Thus, difference in operating condition can be minimized. Figure 10 shows a semiconductor logic circuit according to an embodiment of the present invention. The circuit includes three three-input gate circuits 40, 50 and 60. Gate circuit 40 comprises a series circuit 44 including transistors 41, 42 and 43 connected in series between a voltage supply 5 and an output pin 6, and a parallel circuit 48 of transistors 45, 46 and 47 connected between output pin 6 and ground. Gate circuit 50 also comprises a series circuit 54 including transistors 51, 52 and 53 connected in series between voltage supply 5 and output pin 6, and a parallel circuit 58 of transistors 55, 56 and 57 connected between output pin 6 and ground. Similarly, gate circuit 60 also comprises a series circuit including transistors 61, 62 and 63 connected in series between voltage supply 5 and output pin 6, and a parallel circuit of transistors 65, 66 and 67 connected between output pin 6 and ground. An input pin 1 is connected to the gate electrode of transistor 41 in series circuit 44 closest to voltage supply 5 and to the gate electrode of transistor 45 of parallel circuit 48 closest to input pin 1, in the gate circuit 40; to the gate electrodes of center transistors 52 and 56 of the series and parallel circuits 54 and 58, respectively, of the gate circuit 50; and to the gate electrode of transistor 63 remotest from voltage supply 5 in series circuit 64 and to the gate electrode of transistor 67 remotest from pin 1 in parallel circuit 68, of gate circuit 60. An input pin 2 is connected to the gate electrodes of center transistors 42 and 46 in series and parallel circuits 44 and 48, respectively, of gate circuit 40; to the gate electrode of transistor 53 remotest from voltage supply 5 in series circuit 54 and to the gate electrode of transistor 57 remotest from input pin 2 in parallel circuit 58, of gate circuit 50; and to the gate electrode of transistor 61 closest to voltage supply 5 in series circuit 64 and to the gate electrode of transistor 65 closest to input pin 2 in parallel circuit 68, of gate circuit 60. Similarly, an input pin 3 is connected to the gate electrode of transistor 43 remotest from voltage supply 5 in series circuit 44 and to the gate electrode of transistor 47 remotest from input pin 3 in parallel circuit 48 of gate circuit 40; to the gate electrode of transistor 51 closest to voltage supply 5 in series circuit 54 and to the gate electrode of transistor 55 closest to input pin 3 in parallel circuit 58, of gate circuit 50; and to the gate electrodes of center transistors 62 and 66 in series and parallel circuits 64 and 68, respectively, of gate circuit 60. As described in detail, in the semiconductor logic circuit shown in Figure 10, each input pin is connected to one of the transistors closest to voltage supply 5, one of the center transistors, and one of the transistors remotest from voltage supply 5, of the three three-input gate circuits 40, 50 and 60, and, therefore, substantially no difference in operating condition results. In addition, since similar considerations are given for connections to parallel circuits 48, 58 and 68 in the respective gate circuits, variations in operating conditions are further reduced. As described in detail, according to the present invention, variations in response to input signal changes at different input pins of a multiple-input gate circuit including serially connected transistors of the same conductivity type can be reduced, the internal impedance of the circuit viewed from the output pin can be reduced, and, further, transistors in a gate array semiconductor integrated circuit can be efficiently utilized. A semiconductor logic circuit includes a plural number of gate circuits and a voltage supply. Each of the gate circuits includes a series circuit comprising the same plural number of transistors of one conductivity type connected in series, and a parallel circuit comprising the same plural number of transistors of a different conductivity type connected in parallel. The series and parallel circuits are connected in series between a voltage supply and ground. The semiconductor logic circuit includes further the same plural number of input pins, and an output pin connected in common to all of the plural number of gate circuits. Each of the input pins is connected to a different one of the transistors in the series circuit and to a different one of the transistors in the parallel circuit of each of the gate circuits. The control electrode of the k-th transistor from the end of each series circuit closer to the voltage supply is connected to a different one of the input pins, and the control electrode of the m-th transistor from the end of each parallel circuit closer to the input pins is connected to a different one of the input pins.

Claims: A semiconductor logic circuit comprising: a voltage supply (5) ; a plural number, n, of multiple-input gate circuits (10, 20; 30, 32; 40, 50 60) , each multiple-input gate circuit including: n inputs; a series circuit (13, 23; 44, 54, 64) including n transistors (11, 12, 21, 22; 41, 42, 43, 51, 52, 53, 61, 62, 63) of one conductivity type connected in series, and n transistors (14, 15, 24, 25; 45, 46, 47, 55, 56, 57, 65, 66, 67) of a different conductivity type connected to said series circuit; n input pins (1, 2; 1, 2, 3) each connected to the control electrode of a different one of the n transistors in the series circuit of each of said n multiple-input gate circuits; and an output pin (6) connected in common to the all of said multiple-input gate circuits; wherein the control electrode of the k-th transistor, from the end of said series circuit closer to said voltage supply, in each series circuit of a respective one of said n multiple-input gate circuits is connected to a different one of said n input pins than in the series circuit in the other n-1 multiple-input gate circuits, where k is from 1 to n; wherein said transistors connected to the series circuit in each of said multiple-input gate circuits are connected in parallel to form a parallel circuit, said parallel circuit being connected in series with the series circuit; and wherein the control electrode of the m-th transistor in each parallel circuit from the end closer to the input pins is connected to a different one of said n input pins, where m is from 1 to n. A semiconductor logic circuit according to claim 1, wherein said plural number n is 2. A semiconductor logic circuit comprising: first and second multiple-input gate circuits (40, 50) , each multiple-input gate circuit including three inputs, a series circuit (44, 54) including three transistors (41-43, 51-53) of one conductivity type connected in series, and a parallel circuit (48, 58) including three transistors (45-47, 55-57) of a different conductivity type connected in parallel, said parallel circuit being connected in series with said series circuit; three input pins (1, 2, 3) each connected to the control electrode of a different one of the three transistors in the series circuit; and an output pin (16) connected in common to said first and second multiple-input gate circuits; the control electrodes of the first (41) , the second (42) and the third (43) transistors from a voltage supply (5) for said logic circuit of said first multiple-input gate circuit are connected to first (1) , second (2) and third ones (3) of said three input pins, respectively, and the control electrodes of the first (51) , second (52) and third (53) transistors from said voltage supply (5) of said second multiple-input gate circuit are connected to said third (3) , second (2) and first (1) input pins, respectively, wherein the control electrode of the first or third transistor in each parallel circuit from the end closer to the input pins is connected to a different one of said first or third input pins. A semiconductor logic circuit according to claim 1, wherein said plural number n is 3. A semiconductor logic circuit according to claim 4, wherein the control electrodes of the first (41) , second (42) and third (43) transistors from said voltage supply end of the series circuit (44) of a first one (40) of said multiple-input gate circuits are connected to first (1) , second (2) and third (3) ones of said input pins, respectively; the control electrodes of the first (51) , second (52) and third (53) transistors from said voltage supply end of the series circuit (54) of a second one (50) of said multiple-input gate circuits are connected to said third (3) , first (1) and second (2) input pins, respectively; the control electrodes of the first (61) , second (62) and third (63) transistors from said voltage supply end of the series circuit (64) of a third one (60) of said multiple-input gate circuits are connected to said second (2) , third (3) and first (1) input pins, respectively. A semiconductor logic circuit according to claims 4 or 5, wherein the control electrodes of the first (45) , second (46) and third (47) transistors from the input pin end of said parallel circuit (48) of a first one (40) of said three multiple-input gate circuits are connected to first (1) , second (2) and third (3) ones of said input pins, respectively; the control electrodes of the first (55) , second (56) and third (57) transistors from said input pin end of said parallel circuit (58) of a second one (50) of said three multiple-input gate circuits are connected to said third (3) , first (1) and second (2) input pins, respectively; the control electrodes of the first (65) , second (66) and third (67) transistors from said input pin end of said parallel circuit (68) of a third one (60) of said three multiple-input gate circuits are connected to said second (2) , third (3) and first (1) input pins, respectively. A semiconductor logic circuit according to claim 1, wherein said plural number n is greater than 3.

Inventors: DEGUCHI MITSUHIRO, KOMODA MICHIO, DEGUCHI, MITSUHIRO, KOMODA, MICHIO, Deguchi, Mitsuhiro, c/o Mitsubishi Denki K.K., Komoda, Michio, c/o Mitsubishi Denki K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: H03K19
IPC codes: H03K19, H01L27, H01L21