Image processor and method

Abstract: To enable high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operations such as MPEG etc, eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image information can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-bell operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.

Description: This invention relates to the processing of digital images, and especially to methods and devices used for processing a digital image in uniform smaller blocks of pixels. In digital image processing, a memory is needed to store the image information. Figure 26 shows the configuration of a conventional image memory used for MPEG (Moving Picture Expert Group) encoding, a standard moving picture compression technology. This image memory is made of multiple general-purpose DRAM (Dynamic Random Access Memory) 100 and an MPEG interface circuit 102. In MPEG, image processing is performed in units of blocks of 8 pixels x 8 lines, each pixel having 8 bits. The image information is written into and read from the image memory in units of 8 x 8 blocks. In the write operation, the image information for a picture is input in order as 8 x 8 blocks according to prescribed specifications. Consequently, the blocks may be stored in memory regions in several DRAMs 100, which regions correspond to block sites in the image information address space. In the read operation, it should be possible to designate at any site a desired area AR with a size equal to that of the input block unit regardless of the boundaries of the input block units, and it should be possible to designate the desired blocks area by means of the mid-points of the pixel grid, that is, on the half grid. Corresponding to the designated area AR, 8 x 8 pixels (each of 8 bits) are to be output. The MPEG specifications are determined to meet these requirements. When the desired area AR is designated on the half grid, a larger working block of 9 x 9 pixels containing the desired area is read from DRAM 100 to interface circuit 102 for MPEG processing. After the half-pel processing in the interface circuit 102, an 8 x 8 block of averaged pixels is output. In this half-pel processing, the average of the values of the pixels opposite sides of the half grid is taken, and the obtained average value is processed as the pixel on the half grid. In the interface circuit 102, a DRAM control circuit 104 carries out such functions as write/read control, address generation, allocation of image information, etc., with respect to each DRAM 100. In the read operation, the image information of 9 pixels x 9 lines containing the designated area AR are fetched from DRAM 100 and placed in data register 106. Adders 108, 110 and 112 are used for the half-pel processing. The image information of 8 x 8 pixels in the case of non-half-pel processing or the image information of 8 x 8 pixels after the half-pel processing are temporarily stored in data register 114. A half-pel processing control circuit 116 determines whether or not half-pel processing should be carried out in the case of the read operation, based on the address signal from DRAM control circuit 104 designating the area. The operation of data registers 106, 114, and adders 108-112, is controlled on the basis of this determination. Figure 27 shows the configuration of DRAM 100. Just like a conventional DRAM, this DRAM 100 includes a memory array 120 with multiple memory cells arranged in matrix form; a row decoder 122 and a column decoder 124 which decode and select the memory address in memory array 120 designated by an incoming address signal AD; and a timing control circuit 126 which provides the prescribed timing signals to the various parts of the DRAM 100 in response to external memory control signals RAS-, CAS-. However, in MPEG, since the image information for a compressed moving picture is processed, a large-volume, high-speed image memory is needed. As an example, one set of the specifications include a memory volume of 4 Mb and a write/read cycle time of 35 nsec. The aforementioned conventional image memory is made of 4-Mb memory containing 16 parallel-connected 256K (x4) DRAMs for realizing high speed operation. However, for each cycle of memory access, the DRAM must be refreshed, and an 8-bit or 10-bit adder is needed to perform half-pel processing for the image information read from DRAM. Consequently, it is impossible to achieve continuous output of the image information for 9 x 9 pixel blocks in a 35 nsec cycle. A purpose of the present invention is to address the aforementioned problems of the conventional methods by providing a method and device for image processing in which the write and read operations of the image information can be performed in block units at high speed, and the image information operation can fully meet the specifications as required by the high-speed operation of MPEG, etc.. US-A 4 758 881 describes a memory for television pictures, having two pairs of memory banks. Luminance data for pixels within each line are stored alternately in the memory banks of a pair, while lines within a field alternate between pairs of memory banks. The least significant bits of the address are used to identify the banks, so that repeatedly incrementing an address register enables the pixel luminance data for a field to be retrieved serially in the correct order. Only two of the four banks are used for chrominance data. GB-A 2 092 785, on which the preambles of claims 1 and 6 are based, describes a memory in which data for individual sample points are distributed across four submemories so that any four adjacent points in a square can be read in parallel, one from each submemory, and combined to form interpolated values. The invention provides a pipeline image processor for a digital image in the form of a matrix having a grid of pixels in a predetermined number of rows and columns, midpoints between pixels being referenced to a notional half-grid, comprising: a plurality of memory arrays for holding a set of pixels representing the digital image; and address input terminal for receiving an image address signal indicating a designated read area of pixels; a memory control circuit responsive to the image address signal for simultaneously reading pixels of the digital image from the memory arrays; a pixel selector circuit responsive to the image address signal for selecting pixels from the memory arrays; and processing circuitry connected to receive the selected pixels; characterised in that the plurality of memory arrays store the digital image by blocks, each block having a grid of pixels in a predetermined number of rows and columns, so that any four adjacent blocks forming a rectangle in the digital image are stored in different memory arrays, and the plurality of memory blocks are simultaneously readable a block at a time; in that the pixel selector circuitry comprises row selection circuitry for selecting a first row of pixels from a first memory array of the plurality of memory arrays, for selecting a second row of pixels from a second memory array of the plurality of memory arrays, for selecting a third row of pixels from a third memory array of the plurality of memory arrays, and for selecting a fourth row of pixels from a fourth memory array of the plurality of memory arrays and column selection circuitry for selecting a portion of the first row of pixels and a portion of the second row of pixels to form a first working row of pixels in response to the image address signal, and for selecting a portion of the third row of pixels and a portion of the fourth row of pixels to form a second working row of pixels in response to the image address signal; and in that the processing circuitry simultaneously operates on each pixel of the first working row of pixels to output a row of computed pixels of the designated read area. The invention also provides a method of pipeline image processing a digital image in the form of a matrix having a grid of pixels in a predetermined number of rows and columns to compute averaged midpoints between pixels on a notional half-grid, comprising the steps of: providing a plurality of memory arrays for holding a set of pixels representing the digital image; storing the digital image in the memory arrays; providing an image address signal indicating a designated read area of pixels; simultaneously reading from the memory arrays pixels of the digital image required for computing the designated read area in response to the image address signal; selecting pixels from the memory arrays in response to the image address signal; and processing the selected pixels; characterised in that the step of storing stores the digital image by blocks, each block having a grid of pixels in a predetermined number of rows and columns, so that any four adjacent blocks forming a rectangle in the digital image are stored in different memory arrays, and the plurality of memory blocks are simultaneously readable a block at a time; in that the step of selecting selects a first row of pixels from a first memory array of the plurality of memory arrays, a second row of pixels from a second memory array of the plurality of memory arrays, a third row of pixels from a third memory array of the plurality of memory arrays, and a fourth row of pixels from a fourth memory array of the plurality of memory arrays, and further selects a portion of the first row of pixels and a portion of the second row of pixels to form a first working row of pixels and selects a portion of the third row of pixels and a portion of the fourth row of pixels to form a second working row of pixels in response to the image address signal; and in that the step of processing simultaneously operates on each pixel of the first working row of pixels to output a row of computed pixels of the designated read area. Application examples in accordance with the present invention will now be descnbed by way of example only with reference to the accompanying drawings, in which: Figure 1 is a block diagram illustrating the overall configuration of one application example of image memory for MPEG in accordance with the present invention. Figure 2 illustrates an example of the address space MAS of the image of one picture stored in the image memory in the embodiment of Figure 1. Figure 3 illustrates the allocation (distribution) of the pixels in the blocks of image information address space MAS. Figure 4 illustrates the state when input block B1,1 of row 1 and column 1 is loaded in first data register DREG1 corresponding to first memory array MA1. Figure 5 illustrates the state when input block B1,2 of row 1 and column 2 is loaded in second data register DREG2 corresponding to second memory array MA2, while block B1,1 of row 1 and column 1 is transferred from first data register DREG1 to first memory array MA1. Figure 6 illustrates the state when input block B1,3 of row 1 and column 3 is loaded in first data register DREGI, while block B1,2 of row 1 and column 2 is transferred from second data register DREG2 to second memory array MA2. Figure 7 shows the configuration of the allocation of the image information in first memory array MA1. Figure 8 illustrates the state in which the input row-2 blocks B2,1, B2,2,... are written with a prescribed allocation into third and fourth memory arrays MA3, MA4. Figure 9 illustrates the state in which the blocks in the odd-numbered row 4N + 1 in the image information address space are allocated and written in first memory array MA1. Figure 10 illustrates the state in which all of the blocks in the image information address space are allocated and written in the first through eighth memory arrays MA1-MA8. Figure 11 shows the method of allocation of addresses in this application example. Figure 12 illustrates the case in which area AR overlapping four blocks Bi,j, Bi,j+1, Bi+1,j, Bi+1,j+1 is designated. Figure 13 shows the first pattern of the designated read area. Figure 14 shows the second pattern of the designated read area. Figure 15 shows the third pattern of the designated read area. Figure 16 shows the fourth pattern of the designated read area. Figure 17 shows the pattern of the 9 x 9 pixels read from the memory arrays corresponding to the first through fourth read patterns in this application example. Figure 18 shows the state of the read operation of the various pixel data of block Bij in row i and column j from first memory array MA1. Figure 19 is a circuit diagram illustrating a configuration example of the selector circuit that may be used in column selector XSEL in the application example. Figure 20 is a circuit diagram illustrating another configuration example of the selector circuit that may be used in column selector XSEL in the application example. Figure 21 illustrates the configuration of connection between the output terminal of column selector XSEL and the input terminal of the various operation units of half-pel operation circuit 24. Figure 22 is a circuit diagram illustrating the configuration of a circuit of the various operation units of half-pel operation circuit 24. Figure 23 is a timing diagram illustrating the operation of first operation unit HPALU1 of half-pel operation circuit 24 in the application example. Figure 24 is a timing diagram illustrating the state of the parallel operation of the first through eighth operation units HPALU1-HPALU8 of half-pel circuit 24 in the application example. Figure 25 is a timing diagram illustrating the operation of the operation unit when the read operation of one designated read area is switched to the read operation of another designated read area. Figure 26 is a block diagram illustrating the configuration of the conventional image memory for MPEG. Figure 27 illustrates a typical configuration of DRAM used for the conventional image memory. Figure 1 shows the overall configuration of the image memory for MPEG in an application example of this invention. This information memory is manufactured in the form of 1-chip memory with a volume of 4 Mb. In this image memory, image memory unit 10 is made of 8 conventional memory arrays MA1-MA8 connected in parallel. In this configuration, each memory array MAi can perform write/read of the individual image information under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to 8 data registers DREG1-DREG8, respectively of an input/output buffer 18. Each data register DREGi performs serial-in/parallel-out operation in write mode and parallel-in/parallel out operation in read mode. Each data register DREGi has 512 bits, and so can store 8 x 8 pixels of 8 bits each (one block) of the image information at a time. The image information, in 8 x 8 pixel blocks, is input to and output from each memory array MAi through the corresponding data register DREGi. The output terminals of data registers DREG1-DREG8 can be respectively connected to the input terminals of the 8 row selectors YSEL1-YSEL8 of selector circuit 20. Each of these row selectors YSEL1-YSEL8 can select the pixels belonging to a prescribed row from the block read by one memory array MAi. The output terminals of row selectors YSEL1-YSEL8 are connected to the input terminals of a common column selector XSEL. This column selector XSEL is used for selecting the pixels in columns within the designated area AR from the pixels of the rows selected by the row selectors YSEL1-YSEL8. The output terminals of the column selector XSEL are connected to the input terminals of half-pel processing operation circuit 24 via data bus 22 of 9 pixels x 2 bits. The half-pel processing operation circuit 24 is made of 8 operation units HPALU1-HPALU8. These operation units HPALU1-HPALU8 perform half-pel operate in parallel to procedure respective output pixels 1-8. In this way, half-pel processing is carried out one row at a time. The output terminals of operation units HPALU1-HPALU8 are connected to respective input terminals of 8 registers DG1-DG8 of a data register 26. These registers DG1-DG8 have their output terminals connected in common to a data output buffer 28. The output terminals of data output buffer 28 are connected to an 8-bit data output bus 30. In this image memory, the write operation to image memory unit 10 is carried out under control of write address generating circuit 12 and memory array control logic 14. In the following, the write operation will be explained with reference to Figures 2-10. Figure 2 shows an example of address space MAS of the image information of one picture stored in the image memory. Figure 3 shows the allocation (distribution) of the pixels in the blocks of image information address space MAS. As can be seen from Figure 2, one picture of 720 pixels x 480 lines is divided in matrix form into 90 x 60 (5400) blocks B1,1, B1,2,...B60,90 according to image processing format. As shown in Figure 3, each block Bi,j contains 8 pixels x 8 lines of pixels (of 8 bits each). For example, the one-picture image information having the aforementioned image information address space can be obtained from the receiving/demodulation unit of a TV receiver. First, as shown in Figure 4, block B1,1 of the first block row and first block column is loaded as input data D in into first data register DREG1. Then, as shown in Figure 5, block B1,2 of the first row and second column is loaded as input data D in into second data register DREG2. While block B1,2 is loaded into second data register DREG2, block B1,1, which has been loaded into first data register DREGI, is transferred to the first row of first memory array MA1. This transfer command is generated by memory array control logic 14. Then, as shown in Figure 6, while block B1,3 in first row and third column is loaded as input data D in into first data register DREG1, block B1,2, which has been loaded into second data register DREG2, is transferred to the first row of second memory array MA2. In this way, from blocks B1,1-B1,90 of the first row, blocks B1,1, B1,3,...B1,89 of the odd columns are written in order into first memory array MA1 through first data register DREG1, and blocks B1,2, B1,4,...B1,90 of the even columns are written in order into second memory array MA2 through second data register DREG2. Figure 7 shows the memory map illustrating the configuration of the image information in first information array MA1. Stored in the first row (row A1) of first memory array MA1 are the data for the 64 pixels B1,1, a1,1; B1,1, a1,2;...B1,1, a1,8;...B1,1, a8,8 contained in block B1,1 of the first row and first column in image information address space MAS. Stored in the second row (row A2) of first memory array MA1 are the data for the 64 pixels B1,3, a1,1; B1,3, a1,2;...B1,3, a1,8;...B1,3, a8,8 contained in block B1,3 of the first row and third column in image information address space MAS. In this way, rows 1-45 of first memory array MA1 store the data for the 64 pixels contained in each of the 45 blocks B1,1, B1,3,...B1,89 of the odd-numbered columns in the first row. Similarly, rows 1-45 of second memory array MA2 store the data for the 64 pixels contained in each of the 45 blocks B1,2, B1,4,...B1,90 of the even-numbered columns in the first row, respectively. As pointed out in the above, first-row blocks B1,1, B1,2,...B1,90 are written into first and second memory arrays MA1, MA2, respectively. Then, as shown in Figure 8, with the same method of allocation as above, second-row blocks B2,1, B2,2,...B2,90 are written into third and fourth memory arrays MA3, MA4, respectively. That is, from among the blocks B2,1-B2,90 of the second row, blocks B2,1, B2,3,...B2,89 of the odd columns are written in order into third memory array MA3 through third data register DREG3, and blocks B2,2, B2,4,...B2,90 of the even columns are written in order into fourth memory array MA4 through fourth data register DREG4. After the end of the write operation of the second-row blocks, and with the same allocation method, third-row blocks B3,1, B3,2,...B3,90 are written into fifth and sixth memory arrays MA5, MA6 through fifth and sixth data registers DREG5 and DREG6, respectively. Then, with the same allocation method, fourth-row blocks B4,1, B4,2,...B4,90 are written into seventh and eighth memory arrays MA7, MA8 through seventh and eight data registers DREG7 and DREG8, respectively. In this way, blocks B1,1,...B4,90 in rows 1-4 are written into the eight memory arrays MA1-MA8. Then, fifth-row blocks B5,1, B5,2,...B5,90 are written into first and second memory registers MA1 and MA2, respectively. As shown in Figure 10, in first memory array MA1, after first-row odd-numbered-column blocks B1,1,...B1,89, fifth-row odd-numbered-column blocks B5,1, B5,3,...B5,89 are stored in order into memory addresses A45, A46,..., respectively. In second memory array MA2, after first-row even-numbered-column blocks B1,2,...B1,90, fifth-row even-numbered-column blocks B5,2, B5,4,...B5,90 are stored in order. In the aforementioned allocation method, the image information of one picture is written in 8 x 8 pixel block units into 8 memory arrays MA1-MA8. As a result, as can be seen from Figure 10, the blocks in the odd-numbered columns and even-numbered columns in row (4N + 1) (N = 0, 1,...14) are stored in first and second memory arrays MA1 and MA2, 1 block/1 row at a time; the blocks in the odd-numbered columns and even-numbered columns in row (4N + 2) are stored in third and fourth memory arrays MA3 and MA4, 1 block/1 row at a time; the blocks in the odd-numbered columns and even-numbered columns in row (4N + 3) are stored in fifth and sixth memory arrays MA5 and MA6, 1 block/1 row at a time; and the blocks in the odd-numbered columns and even-numbered columns in row (4N + 4) are stored in seventh and eighth memory arrays MA7 and MA8, 1 block/1 row at a time. Figure 11 shows the allocation of the addresses in this application example. In write mode, the memory address is generated as a 19-bit address signal, which is a special combination, to be explained later, of 10 bits of X-address (X9, X8,...X0) and 9 bits of Y-address (Y8, Y7,...Y0), by a write generating circuit 12. Each address value corresponds to a pixel datum (8 bits). Write generating circuit 12 has an address counter; it starts the operation corresponding to write reset signal RSTW-, and it generates the write address signal with an increment of unity for each period of clock signal CLCK Corresponding to the write signal from write address generating circuit 12, memory address control logic 14 provides the desired command signals to the various memory arrays MAi and various data registers DREGi. Of these memory addresses, X-address (X9, X8,...X0) and Y-address (Y8, Y7,...Y0) correspond to the addresses (coordinates) of the image address space MAS in the X direction and Y direction, respectively. In the image information address space MAS, the lower 3 bits (X2, X1, X0) of the X-address represent the positions of the various columns within a block Bi,j, and the lower 3 bits (Y2, Y1, Y0) of the Y-address represent the positions of the various rows within a block Bi,j. Consequently, the 6-bit addresses formed of these lower 3 bits (Y2, Y1, Y0, X2, X1, X0) represent the allocation positions of the 64 pixels within any block Bij. In this image memory, the 6-bit address (Y2, Y1, Y0, X2, X1, X0) is the column address representing the position of any of the 64 pixels, that is, the position of one of the columns, within a block stored as a row of a memory array MAi. The fourth bit (X3) in the X-address, counting from the lower bit takes on value "0" for blocks in even-numbered columns and value "1" for blocks in odd-numbered columns in image address space MAS. In this image memory, this bit (X3) takes on value "0" for the odd-numbered memory arrays MA1, MA3, MA5 and MA7, and value "1" for the even-numbered memory arrays MA2, MA4, MA6, and MA8. In the image information address space MAS, the two bits, that is, the fourth and fifth bits, (Y4, Y3) of the Y-address, counting from the lower bit, represent which of the four row groups of row 4N + 1, row 4N + 2, row 4N + 3, and row 4N + 4 (N = 0, 1,...14) the block is located in. These two bits take on the values "0," "0" for row 4N + 1, the values "0," "1" for row 4N + 2, the values "1," "0" for row 4N + 3, and the values "1," "1" for row 4N + 4. In this image memory, these two bits (Y4, Y3) take on the values "0," "0" for the first and second memory arrays MA1, MA2, the values "0," "1" for third and fourth memory arrays MA3, MA4, the values "1," "0" for fifth and sixth memory arrays MA5, MA6, and the values "1," "1" for seventh and eighth memory arrays MA7, MA8. In the image information address space MAS, the upper 6 bits (X9, X8, X7, X6, X5, X4) of the X-address represent positions among the odd-numbered columns or positions among the even-numbered columns. Namely, each row contains 45 odd-numbered column blocks and 45 even-numbered blocks. These 45 odd-numbered column blocks or 45 even-numbered blocks within a row are continuously written into a corresponding memory array MAi, one block/one line at a time. The upper 4 bits of the Y-address (Y8, Y7, Y6, Y5) represent the positions of the 14 rows in any one of the four groups of row 4N + 1, row 4N + 2, row 4N + 3, and row 4N + 4 (N = 0, 1,...14) in image information address space MAS. These blocks belonging to the 15 rows in each of the groups are continuously written into the appropriate memory array MAi, one row at a time. In this image memory, the 10-bit address (Y8, Y7, Y6, Y5, X9, X8, X7, X6, X5, X4) made up of a sum of the upper 6 bits of the X-address (X9, X8, X7, X6, X5, X4) and the upper 4 bits of the Y-address (Y8, Y7, Y6, Y5) is the row address which represents the position of a row of each memory array MAi. In the following, the read operation in the image memory in this application example will be explained with reference to Figures 12-25. The read operation is performed in units of the size of a block. On the other hand, agreement with the blocks Bi,j of the matrix form into which the image was divided in the write operation may be present or absent, and an area with the same size 8 x 8 as a block Bi,j, designated at any site in image information address space MAS, can be externally designated. In order to assign designate the area to be read, the address which represents the upper-left end position of the desired area in image information address space MAS is input as external address A in to the read address generating circuit 16. Also, read start signal BRAS- is input into read address generating circuit 16 and memory address control logic 14. When read start signal BRAS- and external address A in are input to read address generating circuit 16, the read address signal needed for reading the image information in the corresponding area with reference to said external address A in is generated in the period of clock CLCK. Corresponding to the read address signal from read address generating circuit 16, memory address control logic 14 sends the necessary command signals to the various memory arrays MAi and various data registers DREGi. Figure 12 shows the case when area AR extends to the four blocks Bi,j, Bi,j+1, Bi+1,j, Bi+1,j+1. Although the size of the assigned read area AR is constant at 8 x 8, there are 4 types of patterns in consideration of the relation with the grids of the blocks. As shown in Figure 13, the first pattern has the pixels of area AR in agreement with the grids of the various blocks. In the example shown in the figure, the pixels Bi,j, a3,6 in block Bi,j of row i and column j are assigned the upper-left position of area AR by external address signal A in . In this case, from the four blocks Bij, Bi,j+1, Bi+1,j, Bi+1,j+1, the 8 x 8 pixel information in area AR, Bi,j, a3,6; Bij, a3,7;...Bi+1,j+1, d2,5 are read and directly output. As shown in Figure 14, in the second pattern, the pixels of the assigned read area AR are located on the midpoints between the existing X grid points, that is, on the X half-grids, of the various blocks. In the example shown in the figure, the midpoint between pixels Bi,j, a3,6 and Bi,j, a3,7 in block Bij of row i and column j is assigned as the upper-left position of area AR by means of external address signal A in . In this case, external address signal A in has a Y address with an integer value and an X address to one decimal place (0.5). For the pattern of this type, not only the pixels in area AR, but also the adjacent pixels can be read from blocks Bi,j, Bi,j+1, Bi,j, Bi+1,j+1. For every two pixels in the X-direction, the average value is derived in the half-pel processing, and these average values are output as the 8 x 8 pixel information in area AR. This processing for deriving the average value is known as half-pel processing in the X (horizontal) direction. As shown in Figure 15, in the third read pattern, the pixels of the assigned read area AR are located at the midpoints of the Y grid points, that is, on the Y half-grids, of the various blocks. In the example shown in the figure, the midpoint between pixels Bi,j, a3,6 and Bi,j, a4,6 in block Bi,j of row i and column j is assigned the upper-left position of area AR by means of external address signal A in . In this case, external address signal A in has an X address with an integer value and a Y address to one decimal place (0.5). For patterns of this type, not only the pixels in area AR, but also the adjacent pixels can be read from blocks Bi,j, Bi,j+1, Bi+1,j, Bi+1,j+1. For every two pixels in the Y-direction, the average value is derived in half-pel processing, and this average value is output as the 8 x 8 pixel information in area AR. As shown in Figure 16, in the fourth read pattern, the pixels of the assigned read area AR are located at the midpoints of the X and Y grid points, that is, on the XY half-grids, of the various blocks. In the example shown in the figure, the half-grid of four pixels Bij, a3,6; Bi,j, a3,7; Bi,j, a4,6 and Bi,j, a4,7 in block Bi,j of row i and column j is assigned the upper-left position of area AR by means of external address signal A in . In this case, external address signal A in has both an X address and a Y address to one decimal place (0.5). For the pattern of this type, not only the pixels in area AR, but also the adjacent pixels can be read from blocks Bi,j, Bi,j+1, Bi+1,j, Bi+1,j+1. For every four pixels in the X- and Y-direction, the average value is derived with the half-pel processing, and this average value is output as the 8 x 8 pixel information in area AR. In the image memory in this application example, with respect to any of said first to fourth read patterns, as shown in Figure 17, 9 x 9 pixels can be read from the adjacent four blocks Bi,j, Bi,j+1, Bi+1,j, Bi+1,j+1. The read image information is then sent to half-pel processing circuit 24. These adjacent four blocks Bij, Bi,j+1, Bi+1,j, Bi+1,j+1 are stored in different memory arrays. For example, they may be stored in the first, second, third, and fourth memory arrays MA1, MA2, MA3, and MA4, respectively. In this case, reading of the 9 x 9 pixel information shown in Figure 17 is carried out under control of read address generating circuit 16 and memory array control logic 14 by means of the aforementioned four memory arrays MA1-MA4, the four data registers DREG1-DREG4 related to them, four row selectors YSEL1- YSEL4, and column selector XSEL. First of all, from these four memory arrays MA1-MA4, blocks Bi,j, Bi,j+1, Bi+1,j, Bi+1,j+1 are read by data registers DREG1-DREG4 at the same time. Figure 18 illustrates the state of transfer of information for the 64 pixels a1,1, a1,2,...a1,8, a2,1,...a8,8 in block Bi,j from first memory array MA1 to first data register DREGI in a parallel format. The 64 pixels of information a1,1, a1,2,...a1,8, a2,1,...a8,8 in block Bi,j transferred to first data register DREG1 are each 8-bit data. Each piece of pixel information is transferred in 4 cycles, with 2 bits per cycle, from the lower bit, from first data register DREG1 to first row selector Y SEL1. First row-selector YSEL1 receives the lower 3 bits of the Y-address (Y2, Y1, Y0) from read address generating circuit 16, and it selects the pixels located on the row within the block assigned by the three bits of address. In the example shown in Figure 17, row-3 pixels a3,1, a3,2,...a3,8 initially designated by these three bits of address are pixels on the third row a3,1, a3,2,...a3,8. Consequently, from the eight output terminals y1, y2,...y8 of first row-selector YSEL1, the 8-bit data of the 8 pixels in row-3 in block Bi,j are transferred to column selector XSEL in 4 cycles, two bits per cycle. While data transfer is made from row-1 selector YSEL1 to column selector XSEL, the 8-bit data b3,1, b3,2,...b3,8 of the 8 pixels in row-3 in block Bi,j+1 are transferred to column selector XSEL in 4 cycles, two bits per cycle, by means of the second row-selector YSEL2 corresponding to second memory array MA2. Column selector XSEL receives the lower 3 bits (X2, X1, X0) of the X-address from read address generating circuit 16, and selects the column in the particular range designated by these 3 bits of address. In the case shown in Figure 17, the 3 bits of X-address (X2, X1, X0) designate the column of the pixels in the upper-left corner of the area Bi,j, a3,6, that is, column 6. In this case, column selector XSEL selects the pixels of the sixth and higher columns a3,6, a3,7, a3,8 for block Bi,j, and the pixels of the sixth and lower columns b3,1, b3,2, b3,3, b3,4, b3,5, b3,6 for block Bi,j+1. Then, these selected 9 pixels a3,6, a3,7, a3,8, b3,1, b3,2, b3,3, b3,4, b3,5, b3,6 are input to half-pel processing circuit 24 through data bus 22 from the 9 output terminals x1, x2,...x9, in four cycles, with two bits per cycle, from the lowest bit. As pointed out above, among the 9 x 9 pixels corresponding to the assigned read area AR (Figure 17), first of all, the various pixels in the first row a3,6, a3,7, a3,8, b3,1, b3,2, b3,3, b3,4, b3,5, b3,6 are read in four cycles, with two bits per cycle. In the following, in the same way as above, the various pixels in the second row a4,6, a4,7, a4,8, b4,1, b4,2, b4,3, b4,4, b4,5, b4,6 are read in four cycles, with two bits per cycle; the various pixels in the third row a5,6, a5,7, a5,8, b5,1, b5,2, b5,3, b5,4, b5,5, b5,6 are read in four cycles, with two bits per cycle; and finally, the various pixels in the last row, the ninth row c3,6, c3,7, c3,8, d3,1, d3,2, d3,3, d3,4, d3,5, d3,6 are read in four cycles, with two bits per cycle. Figure 19 shows an example of a selector circuit used as column selector XSEL. In this selector circuit, 3 bits of X-address (X2, X1, X0) are input, and all of the output signals SEi, SEi+1,... higher than the value Pi of address (X2, X1, X0) are set on "H" level. That will not be described in detail. It is a dynamic type decoder. SE1-SE8 are maintained at "L" in the standby condition. In the active state, the selected output (one out of Z1-Z8) becomes "H," and the remaining nonselected outputs become floating "L." For example, when (X2, X1, X0) is 110, output terminal Z6 of decoder 32 becomes "H," while the output terminals become the floating state "L." As "L" output signal is obtained from invertor circuit VF6 connected to this decoder output terminal Z6, MOS transistor TR7A connected to output terminal Z7 of the adjacent upper decoder is turned on, and decoder output terminal Z7 also becomes "H." Similarly, decoder output terminal Z8 also becomes "H." All of lower decoder output terminals Z1 to Z5 remain as "L." As a result, the upper 3 output signals SE6-SE8 become "H," and the 6 lower output signals SE1-SE5 become "L." By means of the register circuit of this type, it is possible to select the pixels of column 6 and higher columns a3,6, a3,7, a3,8, as pointed out above. In addition, if the complement of X-address (X2, X1, X0) is input to decoder 32, and the more significant bits and the less significant bits of output signals SE1-SE8 are swapped, all of the output signals SEi, SEi-1,... lower than the value of X-address (X2, X1, X0) can be set on "H." In this way, it is possible to select the pixels of column 6 and lower columns b3,1, b3,2, b3,3, b3,4, b3,5, b3,6 for block Bi,j+1. Figure 20 shows an example of the configuration of a selector circuit which can be used in column selector XSEL. The selector circuit in Figure 20 is made of gate circuits. Figure 21 illustrates the configuration of connection between output terminals x1, x2,...x9 of column selector XSEL and the input terminals of operation units HPALU1-HPALU8 of half-pel processing circuit 24. In this configuration, the upper bits x1u and x2u of output terminals x1, x2 of column selector XSEL are connected to upper bit input terminals SAU and SBU of first operation unit HPALU1, respectively. The lower bits x1L and x2L of output terminals x1, x2 are connected to lower bit input terminals SAL and SBL of first operation unit HPALU1, respectively. Upper bit x2u and lower bit x2L of output terminal x2 are also connected to upper bit input terminal SAU on one side and lower bit input terminal SAL on the other side of second operation unit HPALU2, respectively. The other upper bit input terminal SBU and lower bit input terminal SEL of second operation unit HPALU2 are connected to upper bit x3u and lower bit x3L of output terminal x3, respectively. In the same way, the other output terminals x4-x9, 2 bits for each of them, are connected to the input terminals of the other operation units HPALU3-HPALU8, respectively. Figure 22 shows an example of the configuration of the circuit of various operation units HPALUi. In this operation unit, first 2-position full adder circuit 44 made of a pair of half-adders 40, 42 and second full adder circuit 50 made of a pair of half-adders 46, 48 are connected to each other in series. Between these adder circuits 44, 50, there is a data register 52 with a size of 2 x 5 bits. In addition, the output terminal of second adder circuit 50 is connected to data register 54 with a size of 2 x 5 bits. While the carry output terminal C 0 of first adder circuit 44 is directly connected to one input terminal A of half-adder circuit 56, it is also connected to the other input terminal B of half-adder circuit 56 via a one-bit register 58. In the following, the operation of operation unit HPALUi with respect to the fourth read pattern shown in Figure 16 will be described. As pointed out above, that read pattern corresponds to the case in which the pixels of the designated area AR are located at the middle point between the X-grids and Y-grids of the various blocks, that is, on the XY half grids. In this case, half-pel processing is performed to derive the average value of the adjacent 4 pixels in both the X-direction and Y-direction. The derived average values are output as 8 x 8 pixel information in area AR. In the 8 x 8 output block shown in Figure 16, for example, the average value pixel of the first column, first row is generated as (a3,6 + a3,7 + a4,6 + a4,7)/4 in first operation unit HPALU1; for example, the average value pixel of the second column, first row is generated as (a3,7 + a3,8 + a4,7 + a4,8)/4 in second operation unit HPALU2; and, for example, the average value pixel of the eighth column, first row is generated as (b3,5 + b3,6 + b4,5 + b4,6)/4 in eighth operation unit HPALU8. In the following, the operation of first operation unit HPALU1 will be explained with reference to Figures 22 and 23. In first clock cycle T1, lowest bits a3,6(1), a3,7(1) of pixels a3,6, a3,7 are input through AND gates 60, 62 to two input terminals A, B of half-adder 40 for lower bit of first adder circuit 44, respectively. Half-adder 40 adds these bits a3,6(1), a3,7(1), and outputs the sum from output terminal S. In the case when a carry is generated, the carry is output from carry output terminal CO. The sum is stored in data register 52, and the carry is sent to carry input terminal Ci of half-adder 42 for the upper bit. Also, next lowest bits a3,6(2), a3,7(2) of pixels a3,6, a3,7 are input through AND gates 64, 66 to two input terminals A, B of half-adder 42 for upper bit, respectively. Half-adder 42 adds these bits a3,6(2), a3,7(2), and any carry bit received, and outputs the sum from output terminal S. In the case when a carry is generated, the carry is output from carry output terminal CO. The sum is stored in data register 52, and the carry is stored in register 70. In the next cycle of the operation, the carry is sent from this register 70 to carry input terminal Ci of half-adder 40 via AND gate 68. In second clock cycle T2, third lowest bits a3,6(3), a3,7(3) of pixels a3,6, a3,7 are input through AND gates 60, 62 to two input terminals A, B of half-adder 40 for lower bit of first adder circuit 44, respectively. Half-adder 40 adds these bits a3,6(3), a3,7(3) and any carry from the preceding two lower bits a3,6(1,2), a3,7(1,2), and outputs the sum from output terminal S. In the case when a carry is generated, the carry is output from carry output terminal CO. The sum is stored in data register 52 in FIFO format, and the carry is sent to carry input terminal Ci of half-adder 42 for the upper bit. Also, fourth lowest bits a3,6(4), a3,7(4) of pixels a3,6, a3,7 are input through AND gates 64, 66 to two input terminals A, B of half-adder 42 for upper bit, respectively. Half-adder 42 adds these bits a3,6(4), a3,7(4) and any carry, and outputs the sum from output terminal S. In the case when a carry is generated, the carry is output from carry output terminal CO. The sum is stored in data register 52 in the FIFO format, and the carry is stored in register 70. In the next cycle of the operation, the carry is sent from this register 70 to carry input terminal Ci of half-adder 40 via AND gate 68. In the same way as explained above, in cycle T3, the fifth bits counted from the lowest bit a3,6(5), a3,7(5) and the sixth bits counted from the lowest bit a3,6(6) and a3,7(6) of pixels a3,6, a3,7 are added respectively. In cycle T4, the seventh bits counted from the lowest bit a3,6(7), a3,7(7) and the eighth bits counted from the lowest bit (that is, the uppermost bits) 3,6(8) and a3,7(8) of pixels a3,6, a3,7 are added respectively. Consequently, the value of the sum of pixels a3,6, a3,7 (8 bits) is stored in register 52 in FIFO format from the lowest bit, two bits at a time. Any carry output to register 70 in the addition operation of the last two bits is transferred to register 58 in the timing of carry control signal CTL5. As explained above, the addition operation of the two adjacent pixels in the X-direction, a3,6, a3,7 is carried out in four cycles T1-T4. Then, among the 9 x 9 block corresponding to the read area AR, pixels a4,6, a4,7 in columns 1 and 2 in row 2 are input by means of column register XSEL into first operation unit HPALU1 in four cycles, with 2 bits per cycle, from the lowest bit. First of all, in cycle T5, the addition operation is performed for the lowest bits a4,6(1), a4,7(1) of pixels a4,6, a4,7 at half-adder 40. At the same time, the addition operation is performed for the second lowest bits a4,6(2), a4,7(2) of pixels a4,6, a4,7 at half-adder 42. The sums of the two lower bits of pixels a4,6, a4,7, namely, (a4,6(1) + a4,7(1)); (a4,6(2) + a4,7(2), output from said half-adders 40, 42 are stored in the FIFO format into data register 52. At the same time, through AND gates 72, 74, they are input to one input terminal B of half-adder circuits 46, 48 of second adder circuit 50. The sum of the lowest bits of row-1 pixels a3,6, a3,7; (a3,6(1) + a3,7(1)), is sent from data register 52 to the other input terminal A of half-adder circuit 46. Half-adder circuit 46 performs the addition operation for the aforementioned two inputs a4,6(1) + a4,7(1); a3,6(1) + a3,7(1), and it sends the sum from output terminal S. When a carry is generated, it is output from carry output terminal CO. The value of the sum is loaded in data register 54 in the FIFO format. Any carry is input into carry input terminal Ci of half-adder 48. The sum of the second lowest bits of row-1 pixels a3,6, a3,7; a3,6(2) + a3,7(2), is sent from data register 52 to the other input terminal A of half-adder circuit 48. Half-adder circuit 48 performs the addition operation for the aforementioned two inputs a4,6(2) + a4,7(2); a3,6(2) + a(3,7(2) and any carry, and it sends the sum from output terminal S. When a carry is generated, it is output from carry output terminal CO. The value of the sum is loaded in data register 54 in the FIFO format. Any carry is input into carry input register 78. In the next cycle, the carry is sent from this register 78 to carry input terminal Ci of half-adder 46 via AND gate 76. In the next cycle T6, first adder circuit 44 performs the addition operation of the third bits counted from the lowest bit a4,6(3), a4,6(3) and the fourth bits counted from the lowest bit a4,6(4), a4,6(4) of pixels a4,6, a4,7 in the second row, respectively. In the second adder circuit 50, the sum of the third bits counted from the lowest bit a3,6(3), a3,7(3) and the sum of the fourth bits counted from the lowest bit a3,6(4), a3,7(4) of the row-1 pixels a3,6, a3,7 from data register 52 are added, respectively, to the sum of the third bits counted from the lowest bit a4,6(3), a4,7(3) and the sum of the fourth bits counted from the lowest bit a4,6(4), a4,7(4) of the row-2 pixels a4,6, a4,7 obtained in the first adder circuit 44. The sum of the third and fourth bits counted from the lowest bit of the four pixels a3,6, a3,7, a4,6, a4,7 obtained from second adder circuit 50 is loaded in the FIFO format to data register 54. In a similar way, by means of second adder circuit 50, in cycle T7, the sum of the fifth and sixth bits counted from the lowest bit of the four pixels a3,6, a3,7, a4,6, a4,7 is derived. In cycle T8, a sum of the seventh and eighth bits counted from the lowest bit of the four pixels a3,6, a3,7, a4,6, a4,7 is derived. These sums are loaded successively in data register 54. In cycle T8, the carry generated by half-adder 42 for the upper bit of first adder circuit 44 is input to input terminal A of half-adder 56, and it is also loaded into register 58. In this case, the carry of the sum of pixels a3,6 a3,7 loaded in the preceding cycle T4 is kept on the output side of register 58. In the next cycle T9, half-adder 56 adds the carry of the sum of pixels a3,6, a3,7 and the carry of the addition result of pixels a4,6, a4,7, and the sum and carry obtained are loaded in data register 54. As a result, the sum (10 bits) of the four pixels a3,6, a3,7, a4,6, a4,7, which surround the upper-left half grid of assigned read area AR is stored in data register 54. By shifting the data in data register 54 by two bits, the sum is divided by 4, and the average value pixel (a3,6 + a3,7 + a4,6 + a4,7)/4 is derived. This average value pixel's datum is sent to first register DG1 of data register 26. When cycle T13 is reached after a prescribed time, pixels a5,6, a5,7 in columns 1 and 2 in row 3 in the 9 x 9 working block corresponding to read area AR are input by means of column selector XSEL into first operation unit HPALU1, in 4 cycles, with 2 bits per cycle. First adder circuit 44 then performs the same operation as above, and these pixels a5,6, a5,7 are added from the lowest bit in 4 cycles T13-T16, with 2 bits per cycle. On the other hand, in second adder circuit 50, the same operation as above is also performed, and the sum of these pixels a5,6, a5,7 and the sum of pixels a4,6, a4,7 stored in data register 52 are added from the lowest bit in 4 cycles T13-T16, with 2 bits per cycle. Then, in cycle T17, half-adder 56 adds the carry of the sum of pixel a4,6, a4,7 and the carry of the sum of pixels a5,6, a5,7, and the sum (10 bits) of the four pixels a4,6, a4,7, a5,6, a5,7, which surround the half grid on row 2 and column 1 in designated read area AR is stored in data register 54, and the average value pixel (a4,6 + a4,7 + a5,6 + a5,7)/4 is sent from said data register 54 to first register DG1 of data register 26. In the above, the operation of the first operation unit HPALU1 has been explained. The other operation units HPALU2-HPALU8 also perform (parallel) operations with the first operation unit HPALU1, and generate the average value pixels of columns 2-8 in the respective 8x8 output blocks. Figure 24 illustrates the state of the parallel operation of the eight operation units HPALU1-HPALU8 in half-pel operation circuit 24. Figure 25 shows the state in which, soon after 8 x 8 pixels are output for an assigned read area AR, the processing for the next assigned read area AR is started at the various operation units HPALUi. From data register 26, eight average value pixels are output continuously in the order from first register DG1 to the eighth register DG8 in eight cycles, with a rate of 1 average value pixel (8 bits)/1 cycle, to data output buffer 28. After one iteration of this operation, the same transfer operation is repeated, and the next eight row of average value pixels are output continuously without any interruption. In the operation unit shown in Figure 22, control signals CTL1, CTL2, CTL4 are set selectively on levels of "H" and "L" corresponding to YES/NO of requirement on the half-pel processing. For example, for the first read pattern, shown in Figure 13, CTL1 is on "H," while CTL2 and CTL4 are on "L"; for the second read pattern, shown in Figure 14, CTL1 and CTL2 are on "H," while CTL4 is on "L;" for the third read pattern, shown in Figure 15, CTL1 and CTL4 are on "H," while CTL2 is on "L;" and for the fourth read pattern, shown in Figure 16, CTL1, CTL2, and CTL4 are on "H." In this way, in the image memory in this application example, when the image information of the read area AR designated at an arbitrary site is to the read out at 8 x 8 size, the image information of the various blocks Bi,j are read together to data registers DREGi from 1-4 independent memory arrays related to the aforementioned area; the desired pixels are sent first from data registers DREGi in the pipeline format, two bits at a time, to various operation units HPALUi of half-pel operation circuit 24; at various operation units HPALUi, the two input pixels are added, two bits at a time, from the lowest bit; at the same time, the sum is added to the two bits corresponding to the sum of the two pixels of the preceding row. In this way, in four cycles, the four 8-bit pixels are added and averaged, and the average value pixels are output without interruption in each cycle. Consequently, even when the clock cycle is selected as 35 nsec, there is still a significant margin for carrying out the half-pel processing for the 9 x 9 pixels and outputting as 8 x 8 pixels. In the aforementioned application example, eight memory arrays MA1-MA8 are used. However, this number is not a necessity. For example, it is also possible to use four memory arrays MA1-MA4. The main point required in this invention is that it has a configuration which allows allocation of multiple, for example, 80 x 60, blocks to multiple memory arrays so that all of the blocks adjacent to an arbitrary block can be stored in corresponding memory arrays different from that of the aforementioned arbitrary block. The image memory of this invention may also be used in applications other than MPEG. For example, it is possible to perform the write operation in units of 1 row instead of 8 x 8 blocks, and to perform the read operation from any site in size of 8 x 8 as above. In the aforementioned application example, the various operation units of the half-pel operation circuit have a configuration corresponding to addition from the lowest bit with 2 bits at a time. However, that circuit may also have a configuration in which the addition operation is carried out from the lowest bit, with 4 bits at a time. As explained above, in this invention, multiple blocks are allocated to multiple memory arrays so that all of the blocks adjacent to an arbitrary block are stored in the corresponding memory arrays different from the aforementioned arbitrary block; when a read area is designated at any site and with the same size as the block, the image information is read simultaneously from the adjacent blocks at least partially overlapped with the aforementioned read area; then, the half-pel processing is carried out so as to extract the necessary image information corresponding to the designated read area from the read image information; in this way, the desired pixels can be output at a high rate. In the half-pel processing method of this invention, the operation is carried out using a pipeline format; hence, the desired pixels can be output without interruption. Consequently, this invention can also be used for MPEG and other specifications with sufficient margin.

Claims: A pipeline image processor for a digital image in the form of a matrix having a grid of pixels (a i,i ) in a predetermined number of rows and columns, midpoints between pixels being referenced to a notional half-gnd, comprising: a plurality of memory arrays (MA1-MA8) for holding a set of pixels representing the digital image; an address input terminal (Ain) for receiving an image address signal indicating a designated read area (AR) of pixels; a memory control circuit (14) responsive to the image address signal for simultaneously reading pixels of the digital image from the memory arrays; a pixel selector circuit responsive to the image address signal for selecting pixels from the memory arrays; and processing circuitry connected to receive the selected pixels; charactensed in that the plurality of memory arrays store the digital image by blocks (B 1,1 - B 60,90 ), each block having a grid of pixels in a predetermined number of rows and columns (a 1,1 - a 8,8 ), so that any four adjacent blocks forming a rectangle in the digital image are stored in different memory arrays (MA), and the plurality of memory blocks are simultaneously readable a block at a time; in that the pixel selector circuitry comprises row selection circuitry (YSEL) for selecting a first row of pixels from a first memory array (MA1) of the plurality of memory arrays, for selecting a second row of pixels from a second memory array (MA2) of the plurality of memory arrays, for selecting a third row of pixels from a third memory array (MA3) of the plurality of memory arrays, and for selecting a fourth row of pixels from a fourth memory array (MA4) of the plurality of memory arrays and column selection circuitry (XSEL) for selecting a portion of the first row of pixels and a portion of the second row of pixels to form a first working row of pixels in response to the image address signal, and for selecting a portion of the third row of pixels and a portion of the fourth row of pixels to form a second working row of pixels in response to the image address signal; and in that the processing circuitry (24) simultaneously operates on each pixel of the first working row of pixels to output a row of computed pixels of the designated read area. An image processor according to claim 1, characterised in that the processing circuitry comprises a plurality of half-pel operation units (HPALU1-HPALU8) each operable to simultaneously form a computed pixel on the half-grid by taking an average of two pixels selected from the first working row of pixels and two pixels selected from the second working row of pixels and to output a row of computed pixels of the designated read area (AR) on the half-grid. An image processor according to claim 2, characterised in that the processing circuitry comprises a half-pel operation unit (HPALU1 - HPALU8) for each column of the designated read area (AR), each comprising: a horizontal adder (44) for averaging a horizontally adjacent pair of pixels from the first working row of pixels as a current horizontally-averaged pixel; an internal pixel register (52) for storing the current horizontally-averaged pixel; and a vertical adder (50) for averaging a horizontally adjacent pair of pixels from the second working row of pixels with the stroed horizontally-averaged pixel stored in the internal pixel register (52), to output a computed pixel of the designated read area (AR) on the half-grid. An image processor according to any of claims 1 to 3, charactensed in that each memory array (MA) compnses a corresponding data register (DREG) for receiving and holding a block of pixels from the memory array corresponding to an entire block of pixels; and the pixel selector circuitry comprises, for each data register (DREG) a corresponding row selector (YSEL) responsive to the image address signal for sequentially outputting each row of the block held I the data register required for computing the designated read area (AR). An image processor according to any one of claims 1 to 4, charactensed in that the row selection circuitry (XSEL) is responsive to the image address signal (Mai) to select from each row output by the row selection circuitry (YSEL) just those pixels required for computing the designated read area (AR) as a row of working pixels. A method of pipeline image processing a digital image in the form of a matrix having a grid of pixels (a i,i ) in a predetermined number of rows and columns to compute averaged midpoints between pixels on a notional half-grid, comprising the steps of: providing a plurality of memory arrays (MA1-MA8) for holding a set of pixels representing the digital image; storing the digital image in the memory arrays; providing an image address signal (Ain) indicating a designated read area (AR) of pixels; simultaneously reading from the memory arrays pixels of the digital image required for computing the designated read area (AR) in response to the image address signal (Ain); selecting pixels from the memory arrays in response to the image address signal; and processing the selected pixels; charactensed in that the step of storing stores the digital image by blocks (B 1,1 - B 60,90 ), each block having a grid of pixels (a 1,1 - a 8,8 ) in a predetermined number of rows and columns, so that any four adjacent blocks forming a rectangle in the digital image are stored in different memory arrays, and the plurality of memory blocks are simultaneously readable a block at a time; in that the step of selecting selects a first row of pixels from a first memory array (MA1) of the plurality of memory arrays, a second row of pixels from a second memory array (MA2) of the plurality of memory arrays, a third row of pixels from a third memory array (MA3) of the plurality of memory arrays, and a fourth row of pixels from a fourth memory array (MA4) of the plurality of memory arrays, and further selects a portion (a 3,6 - a 3,8 ) of the first row of pixels and a portion (b 3,1 - b 3,6 ) of the second row of pixels to form a first working row of pixels and selects a portion (a 4,6 - a 4,8 ) of the third row of pixels and a portion (b 4,1 - b 4,6 ) of the fourth row of pixels to form a second working row of pixels in response to the image address signal; and in that the step of processing simultaneously operates on each pixel of the first working row of pixels to output a row of computed pixels of the designated read area. A method according to claim 6, characterised in that the step of processing simultaneously forms a plurality of computed pixels on the half-grid by taking for each such computed pixel an average of two pixels selected from the first working row of pixels and two pixels selected from the second working row of pixels and outputting a row of computed pixels of the designated read area (AR) on the half-grid. A method according to claim 7, characterised in that the step of processing compnses simultaneously performing a half-pel operation for each column of the designated read area (AR), each comprising: adding a horizontally adjacent pair of pixels from the first working row of pixels as a current honzontally-added pixel; storing the current horizontally-averaged pixel; adding a horizontally adjacent pair of pixels from the second working row of pixels with the stored horizontally-averaged pixel; and dividing by four to form a computed pixel of the designated read area (AR) on the half-grid. A method according to any one of claims 6 to 8, characterised in that the step of selecting in response to the image address signal (Mai) comprises selecting, from each row output by the row selection circuitry (YSEL), just those pixels required for computing the designated read area (AR) as a row of working pixels.

Inventors: HASHIMOTO MASASHI, YAMAGUCHI HIROHISA, HASHIMOTO, MASASHI, YAMAGUCHI, HIROHISA
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1993
Main classification: G06T9
IPC codes: G09G3, G11C7, H04N5, G06T9, H04N7, G11C11, G06T1, G09G5