INPUT/OUTPUT PROTECTIVE CIRCUIT

Abstract: The cathode of an input protective diode (40) is connected directly to the drain (30D) of an input protective MOS transistor (30). The source (30S), the gate (30G), and the anode of the input protection diode (40) are grounded. Thus, overvoltage inputted from the external terminal is received by the cathode of the diode (40) and the drain (30D) before such a voltage is transferred to the internal circuit of a semiconductor device. Hence there is no increase in the junction capacitance of the input protective diode due to the pattern of the diode (40). The voltage value at which the input protective MOS transistor (30) conducts can be lowered because the input protective diode (40) breaks down by overvoltage before it reaches the internal circuit. As a result, it is possible to achieve reliable input protection at a high speed. Also, since the input terminal can be connected directly to the drain (30D) of the input protective MOS transistor (30), the input protective circuit shown is applicable to an output protection circuit and an output MOS transistor, thus making it possible to protect the internal output circuit reliably.

Description: The present invention relates to an input protection circuit for protecting an internal input circuit or to an output protection circuit for protecting an internal output circuit (collectively called an i/o protection circuit hereinafter) when an excessive input voltage is applied to an external electrode of a semiconductor device. A diode and resistors are arranged on the side of the input electrode relative to an input protection MOS transistor for lengthening a rise time of voltage surge input thereto to'cope with an abrupt surge of voltage by way of the time constant of the junction capacitance of the diode and the resistances of the resistors. The output circuit is substantially identical to the i/o protection circuit for protecting the input circuit which is described above. In case of the output protection circuit, an output MOS transistor itself serves as the output protection MOS transistor. Since the output MOS transistor generally occupies a large area, the protection diode serving as a capacitor is not used. The conventional input or output protection circuit, however, reacts as a delay element also to normal signals since it is equipped with a protection diode and protection resistors for lengthening the rise time of input voltage. As a result, the transmission of signal in the input or output circuit is delayed so that speeding up device operation as a whole is prevented. Particularly elements are miniaturized and the speeding up a device operation is in progress nowadays, so that it is not negligible as a factor preventing the speeding up. The Patent Abstracts of Japan vol. 11, 277 and JP-A-62 76676 disclose providing a protection circuit at an input terminal and at an output terminal to prevent distruction due to electrostatic. Also this document discloses a transistor T1 (or T3) and a diode D1 (or D2) constitute such protecting circuits. The transistor T1 (or T3) has a gate electrode connected to a source electrode which is grounded, and a drain electrode connected to an input terminal (or to an output terminal). JP-A-62 76676 further discloses that one end of the diode D1 is connected to the drain electrode of the transistor T1, and that one end of the diode D2 is connected to the output terminal. Patent Abstracts of Japan vol. 3, 111 and JP-A-54 89586 disclose that a diode 43 constitutes a protection circuit, and that one end of the diode 43 is connected to an external connecting member 44 and the other end of the diode 43 is grounded. The European Patent Application 0 215 493 discloses a protected MOS transistor circuit having P-type semiconductor substrate, power terminal, input MOS transistor, resistor connected to the gate electrode of transistor and MOS transistor which has a gate electrode connected to terminal and a current pass connected between power terminal and the junction of resistor and the gate electrode of input MOS transistor. It is an object of the present invention to provide an input protection circuit or an output protection circuit which realizes the speeding up of a device operation by solving the problem that the transmission of signal is delayed by the protection diode and protection resistors set forth above. An input protection cicuit for solving the problem is given in the indipendent claims 1 and 3. Preferred embodiments of the invention and the features thereof are given in the subclaims. Preferred embodiments of the invention will now be described in detail in conjunction with the accompanying drawings in which: Fig. 1 is a circuit diagram of an i/o protection circuit according to a first embodiment of the present invention, Fig. 2 shows a pattern layout of the i/o protection circuit in Fig. 1, Fig. 3 is a cross-sectional view of Fig. 2 taken along line X1 - X2, Fig. 4 is a view for explaining the operation of the i/o protection circuit in Fig. 1, Fig. 5 shows a pattern layout of the i/o protection circuit according to a second embodiment of the present invention, Fig. 6 is a cross-sectional view of Fig. 5 taken along line Y1 - Y2 and Fig. 7 shows a pattern layout for explaining the i/o protection circuit according to a third embodiment of the present invention. An i/o protection circuit according to the present invention will be described with reference to drawings. Fig. 1 is a circuit diagram of the i/o protection circuit 100 according to a first embodiment of the present invention. The operation of the i/o protection circuit 100 illustrated in Fig. 1 serving as an input protection circuit will be described hereinafter. Denoted at 23 is a terminal connected to an input electrode and an input circuit, 30 is an input protection MOS transistor, 40 is an input protection diode, 51 and 52 are parasitic resistors and 60 is a parasitic bi-polar transistor. The cathode of the input protection diode 40, the drain 30D of the input protection MOS transistor 30 and the emitter of the parasitic bi-polar transistor 60 are connected to the terminal 23. The anode of the input protection diode 40 is connected to a ground potential V ss by way of the parasitic resistors 51 and 52. The gate 30G and source 30S of the input protection MOS transistor 30 are connected to the ground potential V ss . The base of the parasitic bi-polar transistor 60 is connected to a node between the parasitic resistors 51 and 52 and the collector thereof is connected to the ground potential V ss . Fig. 2 shows a pattern layout of the i/o protection circuit 100 in Fig. 1 and Fig. 3 is a cross-sectional view of Fig. 2 taken along line X1 - X2. In Figs 2 and 3, the input protection MOS transistor 30 and input protection diode 40 are formed in a region surrounded by a field insulating film 21 for separating elements on a p-type substrate 20. That is, the input protection MOS transistor 30 comprises the source 30S and drain 30D each formed of n-type diffusion layer spaced away from each other by a given distance. The gate 30G made of polycide etc. is formed on the p-type substrate between the source 30S and drain 30D by way of a gate insulating film 31. The input protection diode 40 is made of a p-type diffusion layer 40P which is lower in density then the drain 30D and an n-type n-type diffusion layer 40N connected to the p-type diffusion layer 40P. The diffusion layer 40N is connected to the drain 30D. An insulating film 22 are formed over the input protection MOS transistor 30, input protection diode 40 and field insulating film 21. Metal wirings 24 and 25 of Al or Al alloy etc. are formed on the insulating film 22. The metal wiring 24 is connected to the drain 30D by way of a contact 26. The metal wiring 24 is also connected to the input electrode and input circuit. That is, the terminal 23 in Fig. 1 corresponds to the metal wiring 24 (or the contact 26). The metal wiring 25 is connected to the gate 30G by way of a contact 27 and to the source 30S by way of a contact 28. The metal wiring 25 is also connected to the ground potential V SS. The base input of the parasitic bipolar transistor 60 is the p-type substrate on which the input protection MOS transistor 30 is formed, the emitter thereof is the source 30S and the emitter thereof is the drain 30D, while the parasitic resistors 51 and 52 are formed on the p-type substrate. Denoted at A and B in Fig. 3 are portions having low breakdown voltage. Suppose that the secondary breakdown voltage of the input protection MOS transistor 30 (the breakdown voltage between the collector and emitter of the parasitic bi-polar transistor 60) is BV and that between the source and drain of the input protection MOS transistor 30 is BV SD . Likewise suppose that the breakdown voltage of the input protection diode 40 is BV D . The p-type diffusion layer 40P and n-type diffusion layer 40N which constitute the input protection diode 40 are designed in density and in the widths W n and W p thereof to meet the following inequality: BV < BV D < BV SD . For example, supposing that the impurity density of the input protection MOS transistor 30 is 8 × 10 16 ions/cm 3 , the thickness of the gate insulating film 31 thereof is 200 Å and the gate length thereof is 0.8 µm, BV SD ≈ 13 V and BV ≈ 9 V are established. If the impurity density of each of the n-type diffusion layer 40N and p-type diffusion layer 40P which constitute the input protection diode 40 is 5 × 10 17 ions/cm 3 , BV D ≈ 11 V is established in case W n , W p > 0.25 µm so that the above condition can be met. The operation of the i/o protection circuit 100 according to the present invention will be described with reference to drawings hereinafter. Fig. 4 is a view for explaining the operation of the i/o protection circuit 100 according to the present invention, wherein Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c) show the breakdown state of the input protection diode 40, the operating state of the parasitic bi-polar transistor 60 and the conductive state of the input protection MOS transistor 30 respectively. At first, as illustrated in Fig. 4 (a), when an excessive voltage such as electrostatic surge etc. is input to the input electrode, the input voltage is applied to the drain 30D by way of the metal wiring 24 and contact 26. When the excessive voltage is applied to the drain 30D, the portion A illustrated in Fig. 3 of the input protection diode 40 having low breakdown voltage breaks down so that electric current starts flowing therethrough The current flows to the source 30S or the ground electrode by way of the p-type substrate 20. The current raises the voltage of the base (which corresponds to the p-type substrate 20) of the parasitic bi-polar transistor 60 by way of the parasitic resistors 51 and 52 as illustrated in Fig. 4 (b). As a result, current flows between the source and drain of the input protection MOS transistor 30 due to the amplifying operation of the parasitic bi-polar transistor 60. When current flows between the source and drain of the input protection MOS transistor 30, the input protection MOS transistor 30 consequently becomes conductive at a source-drain voltage lower than the source-drain breakdown voltage BV SD thereof. The conductive state of the input protection MOS transistor 30 causes the drop of the source-drain voltage as low as the secondary breakdown voltage BV. As a result, the input electricity consumes its power therein. As described above according to this embodiment, since the input protection diode 40 is provided in such a way as to be connected to the drain 30D of the input protection MOS transistor 30 adjacent thereto, the input protection diode 40 is free from the increase of junction capacitance due to the pattern thereof. Moreover, if an excessive voltage is input, the input protection diode 40 breaks down prior to the input protection MOS transistor 30 to lower the voltage at which the input protection MOS transistor 30 starts to conduct, so that it is possible to lower the voltage applied to an input circuit 2 inside the element. As a result, certain input protection is possible without obstructing the speed-up of operation of elements. Furthermore, since the input electrode can be directly connected to the drain 30D of the input protection MOS transistor 30, the input protection circuit in Fig. 1 is applicable to the output protection circuit, so that an internal output circuit can be protected certainly by applying the input circuit to the output MOS transistor. The present invention is not limited to the above embodiments. Modifications thereof will be described hereinafter. [Second Embodiment; Figs. 5 and 6] Fig. 5 shows the pattern layout of the input protection circuit according to a second embodiment of the present invention and Fig. 6 is a cross-sectional view of Fig. 5 taken along line Y1 - Y2. In this embodiment, the n-type diffusion layer 40N that was one of the constituents of the input protection diode 40 in the first embodiment is omitted and the drain 30D of the input protection MOS transistor 30 is used in place of that. A p-type diffusion layer 40P is formed by providing an element separating region 29 made of field insulating film having a given width of d µm between the drain 30D and itself. The p-type diffusion layer 40P and the n-type diffusion layer of the drain 30D form the input protection diode 40. The width d µm is set also in this example so that the breakdown voltage BV D of the input protection diode 40 may meet the following inequality: BV < BV D < BV SD . For example, d = 0.4 µm + α must be established to meet the condition BV D ≈ 11 V, wherein α represents the lateral extension of the drain 30D and the p-type diffusion layer 40P of the input protection diode 40. Accordingly, supposing that the n-type diffusion layer of the drain 30D and p-type diffusion layer 40P have a common depth of 0.25 µm and the lateral extension is about 80 % of the depth of the junction, the lateral extension can be roughly approximated to: α = 0.4 µm. As a result, if the width d = 0.8 µm is established, it is possible to set the target breakdown voltage BV D . Similar effect can be obtained also in the second embodiment by performing the similar operation in the first embodiment illustrated in Fig. 1. Since the input electrode is directly connected to the drain 30D also in this embodiment, it is also applicable to the output MOS transistor as an output protection circuit. [Third Embodiment; Fig. 7] It is desirable to previously set the resistance of the parasitic resistor 51 as large as possible and that of the parasitic resistor 52 as small as possible in Fig. 1. By doing so, the voltage of the node between the parasitic resistors 51 and 52, i.e., the voltage applied to the base of the parasitic bi-polar transistor 60 can faster reach the breakdown voltage BV between the collector and emitter thereof so that the parasitic bi-polar transistor 60 can operate more easily. Moreover, it is possible to increase the current amplification factor h fe of the parasitic bi-polar transistor 60 and reduce the secondary breakdown voltage BV thereof. As a result, it is possible to improve the electrostatic breakdown resistance of the i/o protection circuit. In order to make the resistance of the parasitic resistor 51 as small as possible and that of the parasitic resistor 52 as large as possible, the p-type diffusion layer 40P which forms the input protection diode 40 is formed in such a way as to surround the drain 30D and source 30S which form the input protection MOS transistor 30 so as to be of low impedance as illustrated in Fig. 7 and a resistor element made of diffusion resistors etc. is formed instead of the parasitic resistor 52. Although the p-type substrate is used in the above embodiment, it is also possible to provide p-type well regions in an n-type substrate and form i/o protection MOS transistor and i/o protection diode therein. In this case, the ground potential is applied to the n-type diffusion layer used as a source. In this arrangement, since the p-type well regions are floating so that the parasitic resistance becomes infinite, the parasitic bi-polar transistors is easily operable. The n-type diffusion layers forming the source and drain of the input protection MOS transistor, the p-type well layer and the n-type substrate form a parasitic bi-polar transistor also in this case to contribute to the input protection particularly at the parasitic bi-polar transistor formed on the source side, causing the further improvement of the protecting ability. Various other modifications are possible such as changing the conductive polarity of the i/o protection MOS transistor and i/o protection diodes, using a pattern layout other than that illustrated in the drawings, etc. INDUSTRIAL UTILIZATION As described above in detail according to the present invention, an input protection diode in which the breakdown voltage BV D thereof meets the inequality BV < BV D < BV SD has one end thereof connected to the drain of an input protection MOS transistor connected to an external electrode and the other end thereof connected to a constant potential by way of a resistor together with the source of the input protection MOS transistor. Consequently there is no increase of junction capacitance due to the pattern of the input diode. Moreover, when an excessive voltage is input thereto, the input protection diode breaks down prior to the i/o protection circuit to reduce the voltage value at which the input protection MOS transistor starts to conduct. As a result, it is possible to lower the voltage applied to the input circuit inside the element. As a result, certain input protection is possible without obstructing the speed up of operation of elements. Since the input electrode can be directly connected to the drain of the input protection MOS transistor, the input protection circuit is applicable to an output protection circuit so as to certainly protect internal output circuit by applying the input protection circuit to an output MOS transistor.

Claims: An input/output protection circuit (100) for protecting internal circuits from an excessive voltage applied from an external electrode comprising: a terminal (23) (23) connected to said external electrode and said internal circuits; a transistor (30) having a first electrode (30D) connected to said terminal (23), a grounded second electrode (30S) and a grounded control electrode (30G); and a diode (40) having one end directly connected to said first electrode (30D) of said transistor (30), said diode (40) being arranged reversely to said voltage applied to said terminal (23) (23) ; wherein said first electrode (30D) and said second electrode (30S) of said transistor (30) are formed in a substrate (20) of a first conductive type as first and second diffusion layers of second conductive type respectively, said first and second diffusion layers being spaced apart from each other; and a parasitic transistor is formed of said first and second diffusion layers and the substrate; characterized in that the other end of said diode (40) is grounded; that said diode (40) formed in said substrate (20) is composed of a third diffusion layer (40P) of the first conductive type which is lower in density than said substrate (20); that an element separating region (29) is provided between the third diffusion layer (40P) and the first electrode (30D); that an insulating film (22) is formed on said substrate (20) over said first and said third diffusion layers and said control electrode; and that said third diffusion layer and said element separating region (29) are set in density and width in such a manner that the breakdown voltage BV D of said diode is smaller than the breakdown voltage BV SD of said transistor and the breakdown voltage BV of said parasitic transistor is smaller than BV D . An input/output protection circuit (100) according to claim 1, characterized in that said first diffusion layer (30D) of said transistor and said third diffusion layer (40P) of said diode (40) are connected to each other. An input/output protection circuit (100) for protecting internal circuits from an excessive voltage applied from an external electrode comprising: a terminal (23) (23) connected to said external electrode and said internal circuits; a transistor (30) having a first electrode connected to said terminal (23) (30D), a grounded second electrode (30S) and a grounded control electrode (30G); and a diode (40) having one end directly connected to said first electrode (30D) of said transistor (30), said diode (40) being arranged reversely to said voltage applied to said terminal (23) (23) ; wherein said first electrode (30D) and said second electrode (30S) of said transistor (30) are formed in a substrate (20) of a first conductive type as first and second diffusion layers of second conductive type respectively, said first and second diffusion layers being spaced apart from each other; and a parasitic transistor is formed of said first and second diffusion layers and the substrate; characterized in that the other end of said diode (40) is grounded; that said diode (40) formed in said substrate (20) is composed of a third diffusion layer (40P) of the first conductive type which is lower in density than said substrate (20) and a fourth diffusion layer (40N) of the second conductivity type which is lower in density than said first diffusion layer; that an insulating film (22) is formed on said substrate (20) over said first and said third diffusion layers and said control electrode; and that said third and fourth diffusion layers are set in density and width in such a manner that the breakdown voltage BV D of said diode is smaller than the breakdown voltage BV SD of said transistor and the breakdown voltage BV of said parasitic transistor is smaller than BV D . An input/output protection circuit (100) according to claim 1 or 3, characterized by: a first metal wiring which is formed on said insulating film and is connected to said first diffusion layer through said insulating film; and a second metal wiring which is formed on said insulating film and is connected to said control electrode and said second diffusion layer through said insulating film. An input/output protection circuit (100) according to claim 4, characterized in that: the ground potential is applied to said second metal wiring.

Inventors: FUKUDA YASUHIRO, KATAKURA YOSHIAKI, FUKUDA, YASUHIRO, KATAKURA, YOSHIAKI, FUKUDA, YASUHIRO, OKI ELECTRIC INDUSTRY CO. LTD., KATAKURA, YOSHIAKI, OKI ELECTRIC INDUSTRY CO. LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1993
Main classification: H01L29
IPC codes: H01L27