Analog-to-digital converter

Abstract: The present invention discloses an improved analog-to-digital converter. A second sampling circuit samples the voltage difference between an analog signal and a reference voltage, before a first sampling circuit moves to a follow operation from a sample operation. Owing to pipelining by the first and second sampling circuits, even after the first sampling circuit moves to a follow operation, the difference between an analog signal and a reference voltage is still applied to a logical-level amplifier. The output of the logical-level amplifier, amplified to a logical voltage, is converted by a logic device into an A/D conversion output. Therefore, ADC differential non linearity error can be reduced.

Description: The invention relates to analogue-to-digital converters (ADCs) adopting a voltage transfer method as set forth in the preamble of claim 1. From WO 91/15 899, an ADC is known comprising a first ADC stage for performing a relatively coarse conversion of a sample of an analogue input signal, a sample and hold stage for holding the sample of the analogue signal fed to the first ADC stage while it is converted by the first ADC stage, a digital-to-analogue conversion (DAC) stage to which the digital output from the ADC stage is fed, a difference circuit for generating an analogue difference signal representing the difference between the signal held by the sample and hold stage and the output from the DAC stage, a second ADC stage for generating a digital output corresponding to the difference signal, and a combining unit for combining the digital outputs of the first and second ADC stages to generate a digital output representing the sampled analogue input signal. The sample and hold stage and the first and second ADC stages each responds to a respective pair of differential input signals. The sample and hold and the DAC stages each generate output signals in the form of differential pairs of currents. The different circuits arithmetically combine appropriate pairs of the currents from the sample and hold and DAC stages to generate a differential current pair for input to the second ADC stage. This ADC operates throughout on a differential principle. Thereby, due to the symmetry between the two signals making up each differential pair, inherent errors introduced by the electronic components are automatically compensated when the two signals are processed together. Further, construction of the difference means is simplified. The difference means may comprise a pair of resistors connected in series, the resistor pair being connected in parallel with the second ADC stage, the current outputs of opposite type from the sample and hold and DAC stages being combined at respective points connected in parallel with the resistor pair. From JP-A-63,300627 an ADC is known having two capacitor arrays connected in series with reference to a reference voltage or voltage to be converted, respectively, at one end and at the inputs of a differential amplifier at their other ends. In the discharge mode of the capacitors, they are connected to the reference voltage and are short-circuited, whereas the inputs of the differential amplifier are short-circuited with one another. In the voltage follow mode, the short-circuit of the capacitors is removed and they are connected to the input voltage to be converted, whereas the inputs of the differential amplifier remain short-circuited. In the sample and hold mode, the capacitors are connected to the reference voltage, whereas the inputs of the differential amplifier are disconnected from one another so as to allow measuring of the voltage difference existent at its input terminals. Thus, both capacitor arrays operate parallel to one another. For the case of an ADC capable of performing the function of quantizing an analog voltage value into a digital voltage value, conversion precision (resolution and differential non linearity error), conversion frequency, and power consumption are most important characteristics. The problems is that these characteristics conflict with one another and thus various types of ADCs have been developed to applications. ADCs have been finding applications in image processing, and in particular they are often applied to video cameras of a portable type for signal processing. Such a video camera (conversion frequency: in vicinity of 20MHz for processing image sensor output signals) must be designed to operate with less power because it is battery-powered. Referring now to Figure 7, the organization of a conventional ADC is described. A sampling circuit 77, composed of a capacitor and a buffer circuit, samples an analog voltage. A voltage amplifier 78 amplifies the voltage difference between the sampled analog voltage and a reference voltage. The amplified voltage difference is amplified by a logical-level amplifier 10 to a logical-level voltage and is converted by a logic device 11 into an A/D conversion output 12. One example of these ADCs for use in image processing equipment is shown in Figure 8, which is a monolithic type composed of CMOS transistors. Prior to describing analog-to-digital conversion, the operation of a voltage comparator, which is one of the components of the ADC, is explained. A lower voltage comparator 96 has switches SW5, SW6, SW7, and SW8. These switches can be configurated by PMOS transfer gates, by NMOS transfer gates, or by CMOS transfer gates. One of the terminals of SW6 is connected to an analog signal 1 and the other is connected to a capacitor C1. One of the terminals of SW5 is connected to a reference resistor/switch row 84 and the other is connected to one of the terminals of C1 to which SW6 is connected. The other terminal of C1 is connected to an input terminal of an inverter 82. An inverter 83 and inverter 97 are provided. These inverters including the inverter 82 can be formed by CMOS inverters, by E/D inverters, or by E/E inverters. One of the terminals of SW7 is connected to the input terminal of the inverter 82 and the other is connected to an output terminal of the inverter 82. One of the terminals of a capacitor C2 is connected to an input terminal of the inverter 83 and the other is connected to the output terminal of the inverter 82. One of the terminals of SW8 is connected to the output terminal of the inverter 83 and the other terminal is connected to an output terminal of the inverter 83. The output terminal of the inverter 83 is connected to an input terminal of the inverter 97. This is the organization of the lower voltage comparator 96. Next, the operation is described. Figure 9 is a diagram with regard to the timing of SW5, SW6, SW7, and SW8. In this timing diagram, each switch is in the ON-state when a clock is at high level, whereas each switch is in the OFF-state when a clock is at low level. During the sample period, SW6, SW7, and SW8 each enter the ON-state. This connects the analog signal 1 and C1, as a result of which the voltage of the analog signal 1 is applied to one of the terminals of C1. A voltage value of V a appears at the other terminal of C1. This is explained as follows. Since SW7 is in the ON-state, voltages at the input and output terminals of the inverter 82 are V a (i.e. the voltage value at the point where the inverter input/output static characteristic curve and the straight line where the input voltage and the output voltage become the same cross). Likewise, since SW8 is in the ON-state, voltages at the input and output terminals of the inverter 83 are V a . Next, during the hold period, SW6, SW7, and SW8 are in the OFF-state. At this point, analog voltage is held at C1. In other words, the voltage across C1 becomes, at the time when the timing enters the hold period, the voltage difference between the analog voltage held and Va is held by C1. The relationship between the storage electric charge of a parallel-plate capacitor and the terminal voltage difference is applicable to the case where the voltage difference held at C1 = the amount of electric charge Q1, then Q1 = C1 (V in - V a ) where C1 is the value of capacitance of C1 and V in is the analog voltage held. Next, at the comparison period, when SW5 enters the ON-state, the voltage difference between a voltage of V b at the input terminal of the inverter 82 and a reference voltage of V ref is applied across C1. Since SW7 is in the OFF-state and the input terminal of the inverter 82 is a MOS transistor gate, the input impedance is great. Thus, the entering and leaving gate currents can be ignored. Since the electric charge of the input terminal of the inverter 82 has been held since the hold period, this allows the following formula to hold: Q1 = C1 (V ref - V b ) where V ref is the reference voltage. When the formula (1) is substituted in the formula (2) so as to eliminate Q1, V b is: V b = V ref - V in + V a With regard to the input terminal of the inverter 82, V ref - V in varies more than V a . Accordingly, the output voltage of the inverter 82 (i.e. V of ) is given by: V of = Gf (V ref - V in ) + Va Gf < - 1 where Gf is the voltage gain of the inverter 82 (see Fig. 19). Also, in the inverter 83, its input voltage is amplified in the same way. Since the voltage variable from V a of the inverter 83 becomes the amount of change from V a of V of of the inverter 82, an output voltage of V os is: V os = Gf•Gs (V ref - V in ) + V a Gs < - 1 where Gs is the voltage gain of the inverter 83. The formula (5) shows that V os is proportional to V ref -V in , and that Gf•Gs is the proportional coefficient. In other words, the voltage difference between the reference voltage V ref and the sampled analog signal voltage V in is amplified Gf•Gs times and is output. The resulting voltage, that is, V os is further amplified by the inverter 97 to a logical-level voltage and then is output as a voltage comparison result. Next, the entire ADC, shown in Figure 8, is described. This ADC is a 5-bit series-parallel ADC with two bits for upper voltage comparison range and the remaining three bits for lower voltage comparison range. This ADC has an upper comparator row 79, formed by a group of upper voltage comparators, for comparing voltages in the upper voltage comparison range, lower comparator rows 80 and 94, each formed by a group of lower voltage comparators, for comparing voltages in the lower voltage comparison range, a reference resistor/switch row 84 capable of performing the function of applying comparison results produced by the upper comparator row 79 to the lower comparator rows 80 and 94, an upper logic device 86, lower logic devices 87 and 95, and an adder 88. Connection among these elements is described. Terminals of switches SW2 of the upper voltage comparator group are connected to capacitors Cl and the other terminals of SW2's are connected to 1/4, 2/4, and 3/4 division points produced by dividing a reference voltage 2a and reference voltage 2b by using a reference resistor row 98. Each SW1 of the upper voltage comparator group is connected to the analog signal 1. An output terminal of the upper comparator row 79 is connected to the upper logic device 86. Each SW5 of the lower comparator row 80 is connected to switch rows 85, and 91 to 93. Each SW6 of the row 80 is connected to the analog signal 1. The lower comparator row 80 is connected to the lower logic device 87. Connection as to voltage comparators constituting the lower comparator row 94 is the same. In the switch rows 85 and 91 to 93, switches are connected to 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 division points of the upper voltage comparison range. The upper logic device 86, lower logic device 87, and lower logic device 95 are connected to the adder 88. Further, the adder 88 sends out an A/D conversion output 89. The operation contents of an upper voltage comparator is described in Figure 9. Figure 9 also shows the operation contents of a lower voltage comparator. During the sample period, SW1, SW3, and SW4 of the upper voltage comparator group, and SW6, SW7, and SW8 of the lower voltage comparator group each have an ON-state. Both the upper voltage comparator group and the lower voltage comparator group, therefore, sample analog signal voltages in common. Then, the upper voltage comparator group enter the upper comparison period, during which period SW1, SW3, and SW4 are in the OFF-state and SW2 is in the ON-state. The upper voltage comparator group output upper comparison results based on which the upper logic circuit 86 sends out either one of signals S1, S2, S3, and S4 so as to select one of the switch rows 85, 91, 92, and 93. When the upper voltage comparator group remain in the upper comparison period, the first lower voltage comparator group (i.e. the lower comparator row 80) are in the hold period and have to hold analog voltage until the upper voltage comparator group output comparison results so as to determine the lower voltage comparison range. When the lower voltage comparison range is determined, the timing now enters the lower comparison period. Then, SW5's of the first lower voltage comparator group are connected to one of the switch rows 85, 91, 92, and 93 selected according to comparison results produced by the upper voltage comparison group. The first lower voltage comparator group output lower comparison results. The upper comparison result becomes 2-bit data at the upper logic device 86, whereas the lower comparison result becomes 3-bit data at the first lower logic device 87. The adder 88 adds these two items of data and outputs the sum, i.e. a 5-bit A/D conversion output 89. In order to execute the above-described operation, the upper voltage comparator group carry out one-cycle conversion and thus one period of a reference clock is required. Since the lower voltage comparator group carry out conversion after the lower voltage comparator range is fixed, one cycle of a reference clock must be taken for the lower voltage comparator comparison period. As a result, the sampling of analog signal voltage is carried out before carrying out upper and lower operations. This indicates that two cycles of a reference clock is needed until the results of comparison is output. In order to output both the results of upper comparison and the results of lower comparison by one cycle of a reference clock, the additional provision of the second lower comparator row 94 is required. The first and second lower comparator rows 80 and 94 operate in turn. More specifically, when the first lower comparator row 84 enters the lower comparison period, the second lower comparison row 94 enters the sample period. Since, at this point in time, the upper comparator row 79 has already given upper comparison results used to determine the first lower comparator row's 80 lower comparison range, the upper comparator row 79 and second lower comparator row 94 sample analog signal voltages in common. The subsequent operation is the same as the operation of the upper comparator row 79, and as the operation of the first lower comparator row 80. Since two comparator rows, that is, the first and second lower comparator rows 80 and 94 operate in turn, this makes it possible to output the A/D conversion output 89 for every one period of a reference clock. Incidentally, voltage comparator comparison precision is dependent on the threshold voltage of the change point of ADC digital output results. The drop in comparison precision results in the degradation in differential non linearity error. In order to obtain adequate comparison precision, it is important to reduce the amount of amplification by means of logical-level amplification for amplifying the voltage difference between an analog voltage and a reference voltage to a logical-level and to take a longer amplification time. Switches SW5, SW6, SW7, and SW8, which are components of the lower voltage comparator 96, can take the form of NMOS transfer gates, of PMOS transfer gates, or of CMOS transfer gates. By the application of a clock signal (hereinafter called the switch control signal) to the gate of a MOS transistor, these transfer gates perform the function of switching between an ON-state (drain-to-source conduction) and an OFF-state (non-conduction). One of the characteristics of transfer gates is a phenomenon known as feedthrough. When a switch control signal makes a transition from ON-state voltage level to OFF-state voltage level (or from OFF-state voltage level to ON-state voltage level) due to the gate-to-drain capacitance (or gate-to-source capacitance) of a MOS transistor, it undergoes alternate current coupling and thus electric charge is implanted into the drain (or source), which is know as the feedthrough. In an operation for holding an analog input signal voltage of V in at the time when transition is made from the sample state to the hold state, when SW6, SW7, and SW8 make a transition to the OFF-state, electric charge is implanted or extracted into or from the connection of capacitor C1 and the inverter 82, and into or from the connection of capacitor C2 and the inverter 83. As a result, errors occur to V in . The amount of implanted electric charge by feedthrough depends much upon the value of drain voltage (or source voltage) of MOS transistors, the gate length, the gate width, and the threshold voltage (hereinafter these being called the device parameters). The ADC requires a great number of voltage comparators, and differential non linearity error relates to the matching of device parameters. If the amounts of electric charge being implanted to voltage comparators vary due to device parameter variations, this causes holding voltages to vary. This gives rise to the degradation of differential non linearity error. It is already described that the degradation of differential non linearity error occurs even in a single lower comparator row due to holding voltage variations. For the case of employing two lower comparator rows (Fig. 8), holding voltage variation occurs even between the two rows. A further problem arises that the degradation of differential non linearity error becomes more serious. Since holding voltage error due to feedthrough degrades the voltage comparison precision of a group of voltage comparators, this determines minimum voltage comparison range thereby determining the limit of ADC resolution. Further, since all of the three inverters used in a voltage comparator are biased to V a during the sample period as well as during the hold period, this increases the total amount of passing-through current. As a result, consumption power becomes increased. DISCLOSURE OF THE INVENTION Bearing in mind the above-described problems existing in the prior art techniques, the present invention was made. It is a main object of the present invention to alleviate the degradation of differential non linearity error caused by device parameter variations. This object is attained by the features of claim 1. Preferred embodiments of the invention are subject matter of the dependent claims. The ADC of the invention has a first sampling circuit and a second sampling circuit. The first sampling circuit follows an analog signal while holding it and outputs the voltage difference between such a holding voltage and a reference voltage. The second sampling circuit follows the voltage difference between the aforesaid holding voltage and said reference voltage and holds it. Because of such arrangement, even if the first sampling circuit follows the analog signal, the voltage difference between the holding voltage of the analog signal and the reference voltage can be held for a longer time owing to the second sampling circuit holding operation. In other words, the voltage difference between the analog voltage and the reference voltage is transferred from a sampling circuit at one stage to another sampling circuit at the next stage by means of pipelining, in order to prolong the voltage difference holding time. This is used as a comparison signal of an ADC and thus differential non linearity error can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a first ADC of the present invention; Figure 2 is a second ADC of the present invention; Figure 3 is a third ADC of the present invention; Figure 4 is a fourth ADC of the present invention; Figure 5 is a fifth ADC of the present invention; Figure 6 is a sixth ADC of the present invention; Figure 7 is a conventional ADC; Figure 8 is a conventional ADC of a 5-bit series-parallel type; and Figure 9 is a timing diagram of an ADC of Figure 8. DESCRIPTION OF THE PREFERRED EMBODIMENTS By reference to the accompanying drawings, different ADCs in accordance with the present invention are now described below. Example 1 Referring now to Figure 1, the organization of a first embodiment of an ADC of a voltage transfer type is described. A first sampling circuit 3 has a holding capacitor 4a, switch 4, and buffer circuit 5. A first terminal of the holding capacitor 4a is connected to the earth. A second terminal of the holding capacitor 4a is connected to a second terminal of the switch 4 whose first terminal is connected to an analog signal 1. A first input terminal of the buffer circuit 5 is connected to a connection at which the second terminal of the switch 4 and the second terminal of the holding capacitor 4a are interconnected. A second terminal of the buffer circuit 5 is connected to a reference voltage 2. An output terminal of the buffer circuit 5 is connected to a first terminal of a switch 6 that also serves as an input terminal of a second sampling circuit 9. In addition to the switch 6, the second sampling circuit 9 has a holding capacitor 7 and buffer circuit 8. A second terminal of the switch 6 and a second terminal of the holding capacitor 7 whose first terminal is connected to the earth are connected to an input terminal of the buffer circuit 8. An output terminal of the buffer circuit 8 is connected to an input terminal of a logical-level amplifier 10. An output terminal of the logical-level amplifier 10 is connected to an input terminal of a logic device 11. An A/D conversion output is represented by reference numeral 12. The operation of the first ADC is explained. The analog signal 1 is sampled by the first sampling circuit 3. The output of the second sampling circuit 9 varies with the voltage difference between such a sampled analog signal voltage (i.e. the output voltage of the first sampling circuit 3) and the reference voltage 2. Before the first sampling circuit 3 moves to a follow operation from a sample operation, the second sampling circuit 9 samples the output voltage of the first sampling circuit 3. This ensures that the voltage difference between the analog signal 1 and the reference voltage 2 is still applied to the logical-level amplifier 10, even after the first sampling circuit 3 has moved into a follow operation. Having been amplified to a logical-level voltage, the output of the logical-level amplifier 10 is converted by the logic device 11 into the A/D conversion output 12. The present example achieves a higher amplification precision compared to the prior art techniques, since the present example allows the logical-level amplifier 10 to take a longer amplification time for its voltage amplification operation. This results in the reduction in differential non linearity error. Example 2 Referring now to Figure 2, the organization of a second embodiment of an ADC of a voltage transfer type is described. A first sampling circuit 13 has a holding capacitor 4a, switch 4, and buffer circuit 14. A first terminal of the holding capacitor 4a is connected to the earth. A second terminal of the holding capacitor 4a is connected to a second terminal of the switch 4 whose first terminal is connected to an analog signal 1. An input terminal of the buffer circuit 14 is connected to a connection at which the second terminal of the switch 4 and the second terminal of the holding capacitor 4a are interconnected. An output terminal of the buffer circuit 14 is connected to a first terminal of a voltage amplifier 15 whose second terminal is connected to a reference voltage 2. An output terminal of the voltage amplifier 15 is connected to a first terminal of a switch 6 that also serves as an input terminal of a second sampling circuit 9 which is identical in configuration with its counterpart in the first example. The second embodiment further includes a logical-level amplifier 10 and a logical device 11 which are identical in configuration with their counterparts in the first example. The operation of the second embodiment is explained. The analog signal 1 is sampled by the first sampling circuit 13. The voltage amplifier 15 amplifies the voltage difference between such a sampled analog signal voltage (i.e. the output voltage of the first sampling circuit 13) and the reference voltage 2 and outputs the amplified voltage difference. The output of the second sampling circuit 9 varies with the amplified voltage difference that is the output of the voltage amplifier 15. Before the first sampling circuit 13 moves to a follow operation from a sample operation, the second sampling circuit 9 samples the output voltage of the voltage amplifier 15. This ensures that the voltage difference between the analog signal 1 and the reference voltage 2 is still applied to the logical-level amplifier 10, even after the first sampling circuit 13 has moved into a follow operation. Having been amplified to a logical-level voltage, the output of the logical-level amplifier 10 is converted by the logic device 11 into the A/D conversion output 12. The present example achieves a higher amplification precision compared to the prior art techniques, since the present example not only allows the logical-level amplifier 10 to take a longer amplification time for its voltage amplification operation, but also divides voltage amplification work between the voltage amplifier 15 and the logical-level amplifier 10. This leads to the reduction of differential non linearity error. Example 3 Referring now to Figure 3, the organization of a third embodiment of an ADC of a voltage transfer type is described. As seen from Figure 3, the third embodiment is identical in configuration with the first one except that a subtracter 16 is inserted between the output terminal of the first sampling circuit 3 and the input terminal of the second sampling circuit 9. The subtracter 16 subtracts offset voltage. The present example achieves a higher amplification precision compared to the prior art techniques, since the present example not only allows a logical-level amplifier 10 to take a longer amplification time for its voltage amplification operation, but also employs the subtracter 16 so as to remove offset voltage generated to the output of the first sampling circuit 3. This leads to the reduction of differential non linearity error. Example 4 Referring now to Figure 4, the organization of a fourth embodiment of an ADC of a voltage transfer type is described. As seen from Figure 4, the forth embodiment is identical in configuration with the second one except that a subtracter 16 is inserted between an output terminal of the voltage amplifier 15 and the input terminal of the second sampling circuit 9. The subtracter 16 subtracts offset voltage. The present example achieves a higher amplification precision compared to the prior art techniques, since the present example allows a logical-level amplifier 10 to take a longer amplification time for its voltage amplification operation, divides voltage amplification work between the voltage amplifier 15 and a logical-level amplifier 10, and employs the subtracter 16 so as to remove offset voltage generated to the output of the voltage amplifier 15. This leads to the reduction of differential non linearity error. Example 5 Referring now to Figure 5, the organization of a fifth embodiment of an ADC of a voltage transfer type is described. A first sampling circuit 24 has a switch 25, a holding capacitor 26, a first voltage amplifier 27 whose input and output terminals are short-circuited. An output terminal of the first sampling circuit 24, or a connection at which the switch 25 and the holding capacitor 26 are interconnected, is connected to a first terminal of a second voltage amplifier 28 whose second terminal is connected to a reference voltage 2. An output terminal of the second voltage amplifier 28 is connected to an input terminal of a second sampling circuit 9 which is the same configuration as that of the second sampling circuit 9 of the first example. The fifth embodiment further includes a logical-level amplifier 10 and a logic device 11 which are identical in configuration with their counterparts in the first example. The operation of the fifth embodiment is explained. The first sampling circuit 24 holds in the holding capacitor 26 the voltage difference between the bias voltage of the first voltage amplifier 27 biased when short circuiting takes place between its input and output terminals and the analog signal voltage so as to sample the analog signal 1. The second voltage amplifier 28 amplifies the voltage difference between such a sampled analog voltage (i.e. the output voltage of the first sampling circuit 24) and the reference voltage 2 and outputs the amplified voltage difference. The output of the second sampling circuit 9 varies with the amplified voltage difference which is the output of the second voltage amplifier 28. Before the first sampling circuit 24 moves to a follow operation from a sample operation, the second sampling circuit 9 samples the output voltage of the second voltage amplifier 28. This ensures that the aforesaid amplified voltage difference is still applied to the logical-level amplifier 10, even after the first sampling circuit 24 has moved into to a follow operation. Having been amplified to a logical-level voltage, the output of the logical-level amplifier 10 is converted by the logic device 11 into the A/D conversion output 12. The present example achieves a higher amplification precision compared to the prior art techniques, since the present example not only allows the logical-level amplifier 10 to take a longer amplification time for its voltage amplification operation, but also divides voltage amplification work between the second voltage amplifier 28 and the logical-level amplifier 10. This leads to the reduction of differential non linearity error. Example 6 Referring now to Figure 6, the organization of a sixth embodiment of an ADC of a voltage transfer type is described. A first sampling circuit 24 has a switch 25, a holding capacitor 26, a first voltage amplifier 27 whose input and output terminals are short-circuited. An output terminal of the first sampling circuit 24, or a connection at which the switch 25 and the holding capacitor 26 are interconnected, is connected to a first terminal of a second voltage amplifier 28 whose second terminal is connected to a reference voltage 2. The output voltage of the second voltage amplifier 28 is applied to a second sampling circuit 31. Like the first sampling circuit 24, the second sampling circuit 31 has a switch 32, a holding capacitor 33, and a third voltage amplifier 34 whose input and output terminals are short-circuited. An output terminal of the second sampling circuit 31, or a connection at which the switch 32 and the holding capacitor 33 are interconnected, is connected to a first terminal of a fourth voltage amplifier 30 whose second terminal is connected to the output terminal of the first voltage amplifier 27. An output terminal of the fourth voltage amplifier 30 is connected to an input terminal of a logical-level amplifier 10. An output terminal of the logical-level amplifier 10 is connected to an input terminal of a logic device 11. An A/D conversion output is indicated by reference numeral 12. The operation of the sixth embodiment is explained. The first sampling circuit 24 holds in the holding capacitor 26 the voltage difference between the bias voltage of the first voltage amplifier 27 biased when short circuiting takes place between its input and output terminals and the analog signal voltage so as to sample the analog signal 1. The second voltage amplifier 28 amplifies the voltage difference between such a sampled analog voltage (i.e. the output voltage of the first sampling circuit 24) and the reference voltage 2 and outputs the amplified voltage difference. That is, the input voltage of the second sampling circuit 31 varies with the voltage difference between the analog signal 1 and the reference signal 2. The second sampling circuit 31 holds in the holding capacitor 33 the voltage difference between the bias voltage of the third voltage amplifier 34 biased when short circuiting takes place between its input and output terminals and the output voltage of the second voltage amplifier 28 so as to sample the output voltage of the second voltage amplifier 28 before the first sampling circuit 24 moves to a follow operation from a sample operation. The fourth voltage amplifier 30 amplifies a voltage as a result of subtracting the bias voltage of the first voltage amplifier 27 from the output voltage of the second sampling circuit 31, and outputs the result. This ensures that the amplified voltage difference is still applied to the logical-level amplifier 10, even after the first sampling circuit 24 has moved into a follow operation. Having been amplified to a logical-level voltage, the output of the logical-level amplifier 10 is converted by the logic device 11 into the A/D conversion output 12. The present example achieves a higher amplification precision compared to the prior art techniques, since the present example not only allows the logical-level amplifier 10 to take a longer amplification time for its voltage amplification operation, but also divides voltage amplification work among the second voltage amplifier 28, the fourth voltage amplifiers 30, and the logical-level amplifier 10. This leads to the reduction of differential non linearity error.

Claims: An analogue-to-digital converter (ADC) comprising first sampling means (3; 13, 24) for following, sampling and holding an analogue input voltage (1), and second sampling means (9; 31) provided with the output from the first sampling means (3; 13; 24), characterised in that the second sampling means (9; 31) is sampling and holding the voltage difference between the sampled analogue input voltage and a reference voltage (2), that the analogue-to-digital converter executes analogue-to-digital conversion, using the output voltage of the second sampling means (9; 31) as a comparison signal, and that the second sampling means (9; 31) operate to hold the voltage difference even while the first sampling means (3; 13; 24) follows the analogue input voltage, so that the comparison signal is output by a specified logic (11) for a longer time than the first sampling means (2; 13; 24) is in its hold operation. The ADC as in claim 1, further comprising amplifying means (15;28) for amplifying the voltage difference between the sampled analogue input voltage and the reference voltage (2), wherein the second sampling means (9;31) samples an output voltage of the amplifying means (15;28). The ADC as in claim 1, further comprising subtracting means (16) for subtracting an offset voltage of the first sampling means (3;13), wherein the second sampling means (9;31) samples an output voltage of the subtracting means (16). The ADC as in claim 1, further comprising: amplifying means (15) for amplifying the voltage difference between the sampled analogue input and the reference voltage (2); and subtracting means (16) for subtracting an offset voltage of the amplifying means (15) from an output voltage of the amplifying means (15), wherein the second sampling means (9) samples an output voltage of the subtracting means. The ADC as in claim 1, wherein the first sampling means includes: a holding capacitor (26); and an amplifier (27) for producing, when deliberate short circuiting occurs between input and output terminals, a bias voltage at the input and output terminals. The ADC as in claim 1 or 5, wherein the second sampling means includes: a holding capacitor (33); and an amplifier (34) for producing, when deliberate short circuiting occurs between input and output terminals, a bias voltage at the input and output terminals.

Inventors: KUSUMOTO KEIICHI, MATSUZAWA AKIRA, KUSUMOTO, KEIICHI, MATSUZAWA, AKIRA
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1993
Main classification: H03M1
IPC codes: H03M1