Monolithic high-voltage capacitor

Abstract: A high voltage capacitor (10) structure for integrated circuits or the like. The capacitor includes a provision for equalizing charge when multiple capacitors are series coupled. Charge is equalized by a SiN layer (18) overlaying, and in contact with one terminal (13) of, the capacitor. A ground ring (17) surrounds the capacitor structure and is also overlayed by, and in contact with, the SiN layer.

Description: Background of the Invention Field of the Invention This invention relates to capacitors in general and, more particularly, to high-voltage capacitors integratable with other circuitry on a common substrate. Description of the Prior Art For an increasing number of applications, such as for power supply and telephony applications, coupling capacitors are needed that can sustain high voltages (e.g., 1000 volts or greater) while providing moderate amounts of capacitance. Preferably, the capacitors are integrated along with other circuitry on a common silicon substrate. Most monolithic capacitors, fabricated using existing integrated circuit processing technology, have a breakdown voltage limited to about 1500 volts. For some applications this may be insufficient to meet circuit requirements. To be able to tolerate voltages higher than the breakdown voltage of a single capacitor, two or more monolithic capacitors are placed in series. Thus, the total voltage impressed across the capacitors is the sum of the voltages across each capacitor in series. In theory, the voltage across each capacitor is less than the breakdown voltage thereof. However, if there is any leakage current through one of the capacitors, the voltage across that capacitor will tend toward zero, forcing a higher voltage across the remaining capacitor(s). The higher voltage may be greater than the remaining capacitor(s) can handle, causing a catastrophic breakdown in the remaining capacitor(s). Intentional leakage across each capacitor is sometimes used to force equalization of the voltages across the individual capacitors. A fixed resistor is coupled across each series capacitor to provide the intentional leakage. The amount of resistance is sufficiently low such that the leakage current therethrough is much greater than the amount of expected leakage through the corresponding capacitor. The intentional leakage overcomes the effect of the leakage through the capacitor. This solution may not be acceptable because the amount of intentional leakage may be more than what can be tolerated in a particular application. In addition, adding resistors to each capacitor may not be possible nor desirable depending on the topology of the capacitor. Thus, it would be desirable to provide a monolithic capacitor that does not require a leakage resistor when disposed in series with other similar capacitors in high-voltage applications. According to the present invention, there is provided an integrated capacitor as defined in claim 1, and a method of manufacturing it as defined in claim 5. Brief Description of the Drawing The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following detailed description of the drawings, in which: FIG. 1 is a cross section (not to scale) of a high-voltage capacitor according to one embodiment of the invention; and, FIG. 2 is a top view (not to scale) of the high-voltage capacitor of FIG. 1 with layer 18 of FIG. 2 removed; and, FIG. 3 is an illustration of two pairs of serially coupled exemplary, high-voltage capacitors according to the capacitors in the pairs being disposed on separate chips. Detailed Description In an exemplary embodiment of the invention, a high-voltage monolithic capacitor 10 is shown in FIG. 1 (not to scale) formed on a substrate 11. A first plate (not numbered) of the capacitor 10 is formed by a conductive region 12 in the substrate 11. Dielectric layers 14 and 16 insulate a second plate 13 of the capacitor 10 from the first plate. In addition to the second plate 13, a conductor 17 (here a ring) is disposed on the dielectric layers 14 and 16. The conductor 17 is separate (i.e., spaced) from the second plate 13. Added over the plate 13 and the conductor 17 is a layer of semi-insulating material 18. Thus, the semi-insulating layer 18 contacts both the second plate 13 of the capacitor 10 and the conductor 17. With the conductor 17 connected to a fixed potential (e.g., ground), the semi-insulating layer 18 serves to equalize the voltage on the capacitor 10 when multiple capacitors 10 are coupled in series. Alternatively, the conductor 17 may be coupled to the first plate (region 12) of the capacitor 10 to equalize the voltage thereon. Discussing the exemplary capacitor 10 in more detail, the first plate is preferably formed by implanting a dopant into the substrate 10 to form region 12. For purposes here, the region 12 is also referred to as the first plate of the capacitor 10. Next, a layer of oxide 14 is deposited, then a layer of phosphorus doped glass (P-glass) 16. It is noted that one of the layers 14, 16 may be removed or other dielectric layers may be added to the disclosed embodiment. Such layers may include silicon nitride layer(s). On top of the P-glass 16 a metal layer is deposited and patterned to form the top, or second, plate 13 of the capacitor 10 and a conductor 17. The conductor 17 (here, shaped as a ring) is spaced from, and not in contact with, the plate 13. Over the plate 13 and the conductor 17 a layer 18 of semi-insulating material, such as SiN (a silicon nitride), is deposited. The layer 18 is opened over the plate 13 for contacting thereto by, for example, wire-bonding. In FIG. 2, a top-view of the exemplary capacitor 10 is shown but with layer 18 (FIG. 1) omitted. Here, metal plate 13 is shown surrounded by conductor 17 on the dielectric layer 16 (not shown). The region 12 in the substrate (normally hidden by the dielectric layers 14 and 16 in FIG. 1) is shown being contacted by metal conductor 19 using a conventional substrate-to-metal connection 20. Although the conductor 17 is shown as a ring completely surrounding plate 13, it is understood that other geometrical shapes may be used for the'ring" conductor 17 and that the ring need not be closed. Further, the shape of plate 13 and region 12 need not be that as shown in the figures. Still further, the first plate of the capacitor need not be formed in the substrate; a metal layer supported between dielectric layers below the second plate 13 may be used. The thicknesses and composition of the dielectric layers 16 and 18 (FIG. 1) may be adjusted to establish the breakdown voltage of the capacitor 10 as well as the capacitance thereof. In addition, the area of the plates (12, 13) may be changed to adjust the capacitance of the capacitor 10. The SiN layer 18 acts both as a passivation layer and as a path for current when the voltage on the capacitor is too large - a "safety valve" for the capacitor 10 process for how current "leaks" though the silicon nitride is by a Frenkel-Poole conduction mechanism within the nitride. In FIG. 3, two separate chips, 22, 23 have each formed thereon two exemplary high-voltage capacitors 10, similar to the capacitor 10 shown in FIGs. 1 and 2. The capacitors 10 on chip 22 are wire bonded to the corresponding capacitor 10 on the chip 23 by wire bonds 24, 25. Conductors 17 and the first plate (conductive region 12, FIGs. 1, 2) of each capacitor 10 connect to circuitry (not shown) on the corresponding chip 22, 23. It is noted that conductor 17 for each capacitor 10 is shown outlined since it is under layer 18 (FIG. 1). The wire bonds are made to the exposed portion of plates 13. Using the exemplary structure shown in FIGs. 1 and 2, the following materials and approximate thicknesses/sizes were used to make a 2 pF, 1600 volt capacitor on a silicon substrate: region 12 10 ohm-square N-type silicon 600 x 600 µm layer 13 aluminum 2x10 5 µm 2 layer 14 SiO 2 1.8 µm layer 16 phosphorus doped glass 1.6 µm ring 17 aluminum 590 µm inner diameter, 20 µm wide layer 18 SiN 2 µm

Claims: A monolithically integrated capacitor (10) having a first plate (12) and a second plate (13), the second plate being formed over, and insulated from the first plate by a dielectric layer (14, 16), CHARACTERIZED BY: a layer of semi-insulating material (18) disposed on the dielectric layer and in contact with the second plate; and, a conductor (17), disposed on the dielectric layer, separate from the first and second plates and in contact with the layer of semi-insulating material. The capacitor as recited in claim 1, wherein the semi-insulating material is disposed over the second plate. The capacitor as recited in claim 2, wherein the conductor is a ring disposed adjacent to, and surrounding, the second plate. The capacitor as recited in claim 3, wherein the semi-insulating material is silicon nitride. A method of making a monolithically integrated capacitor (10) having a first plate (12) and a second plate (13), the second plate being formed over, and insulated from, the first plate by a dielectric layer (14,16), CHARACTERIZED BY THE STEPS OF: forming a conductor (17) on the dielectric layer and separate from the first and second plates; and, depositing a layer of semi-insulating material (18) on the dielectric layer and in contact with the second plate and the conductor. The method of claim 5, wherein the semi-insulating layer is deposited over the second plate and the conductor. The method as recited in claim 6, wherein the conductor is a ring disposed adjacent to the second plate. The method as recited in claim 7, wherein the semi-insulating material is silicon nitride.

Inventors: EMBREE MILTON LUTHER, EMBREE, MILTON LUTHER
Applicants: AT & T CORP, AT&T CORP.
Application year: 1993
Main classification: H01L29
IPC codes: H01G4, H01L21, H01L29, H01L27