Contrast control circuit

Abstract: The present invention provides a contrast control circuit capable of controlling the contrast even if the back porch is comparatively short. The contrast control circuit comprises monostable multivibrators (24, 26) which provides a background pulse and a reference pulse alternately, respectively, a switch (SW1) which clamps a video signal while the background pulse is HIGH so that the potential of the pedestal level is zero on an (N+l)th horizontal scanning line, and a switch (SW2) samples the leading edge of a reference pulse inserted in the video signal while the reference pulse is HIGH on an nth horizontal scanning line.

Description: The present invention relates to contrast control circuits. Some CRT monitor which displays pictures represented by signals provided by a computer inserts a reference pulse for contrast control in the back porch of the horizontal blanking interval of a video signal. Referring to Fig. 4 showing a previously proposed CRT controller of such a type, an adder 2 inserts a reference pulse of a specified level in the back porch of a video signal in each horizontal scanning cycle, a video frequency amplifier 4 subjects the output of the adder 2 to gain control, a driver amplifier 6 amplifies the video signal provided by the video frequency amplifier 4 and gives its output to a CRT 8. The video signal provided by the video frequency amplifier 4 is applied also to a contrast control circuit 10. The contrast control circuit 10 detects the voltage of the reference pulse inserted in the video signal, compares the detected voltage of the reference pulse with a contrast voltage set by the user, and controls the gain of the video frequency amplifier 4 so that the detected voltage of the reference pulse coincides with the contrast voltage. Fig. 5 is a block diagram of the contrast control circuit 10 and Fig. 6 is a time chart showing the output signals of the component of the contrast control circuit 10. A synchronous separation circuit 22 extracts the horizontal synchronizing signal from the input video signal and gives the extracted horizontal synchronizing signal to a monostable multivibrator 23. The monostable multivibrator 23 is triggered by the input horizontal synchronizing signal to give a reference pulse to a monostable multivibrator 25. Then, the monostable multivibrator 25 is triggered by the input pulse to give a background pulse as a closing command signal through a buffer 30A to a switch SW1. The reference pulse is given as a closing command signal through a buffer 32A to a switch SW2. A capacitor C1 is inserted between an input terminal to which the output signal of the video frequency amplifier 4 (Fig. 4) is applied, and the input terminal of the switch SW2. The junction of the capacitor C1 and the switch SW2 is grounded through the switch SW1. A resistor R is inserted between the output terminal of the switch SW2 and one of the input terminals of an operational amplifier OP1. A variable voltage source is inserted between the other input terminal of the operational amplifier OP1 and a ground. The user operates the variable voltage source to set a contrast voltage VR1. A capacitor C2 is inserted between the former input terminal and the output terminal of the operational amplifier OP1. The output video signal of the capacitor C1 is clamped by the switch SW1 so that the pedestal level is zero while the background pulse is HIGH. The switch SW2 samples the leading edge of the reference pulse inserted in the video signal while the reference pulse is HIGH. Accordingly, the level of the reference pulse is positive with respect to the ground potential for each horizontal scanning cycle. The operational amplifier OP1 compares the voltage level of the reference pulse sampled by the switch SW2 with the contrast voltage VR1 set by the user and feeds back a voltage to control the gain of the video frequency amplifier 4 so that the voltage level of the reference pulse will coincide with the contrast voltage VR1 to the video frequency amplifier 4. As shown in Fig. 7, the duration of the back porch must be about 1.6 µ sec or above to detect the leading edge of the reference pulse inserted in the video signal while the reference pulse is HIGH by inserting the reference pulse in the back porch and clamping the video signal so that the pedestal level is zero while the background pulse is HIGH. However, the duration of the back porch of some video signal among those used in recent years is less than 1.6 µ sec. When such video signals are used, the previously proposed contrast control circuit shown in Fig. 5 is unable to control the contrast. US-A-3 760 099, EP-A-0 185 775 and The Radio and Electronic Engineer, vol.37, no.5, May '69, GB, pp.299-302 : M.Nurse : "Contrast and Brightness Control in Colour Television Picture Monitors" disclose the use of reference pulses inserted during the horizontal blanking period to allow the dc level (brightness) and the gain (contrast) of a video signal to be adjusted. This invention provides a contrast control circuit comprising: a clamping means for clamping a video signal so that the potential of the pedestal level is held zero once every N horizontal scanning cycles, where N is an integer not smaller than two; a voltage detecting means for detecting the reference voltage of a reference pulse inserted in a horizontal back porch, once every N horizontal scanning cycles and in horizontal scanning cycles other than the horizontal scanning cycles in which said clamping means clamps a video signal so that the potential of the pedestal level is held zero; and a control means which generates a contrast control signal on the basis of the reference voltage detected by said voltage detecting means and a specified voltage specified by operating a specified voltage setting source. The clamping means preferably comprises, for example, a monostable multivibrator (24), a D flip-flop (28) and a switch (SW1) as shown in Fig. 1. The voltage detecting means may comprise, for example, a monostable multivibrator (26), a D flip-flop (28) and a switch (SW2) as shown in Fig. 1. The control means may comprise, for example, an operational amplifier (OP1) as shown in Fig. 1. Desirably, N = 2. The contrast control circuit of the present invention clamps a video signal so that the potential of the pedestal level is held zero once every N horizontal scanning cycles, detects the reference voltage in a horizontal back porch other than the horizontal back porch in which the a video signal is clamped to hold the potential of the pedestal level zero once every N horizontal scanning cycles, and generates a contrast control signal on the basis of the detected reference voltage and the specified voltage. Accordingly, the back porch used for contrast control can be shortened. If N = 2, the reference voltage of the reference pulse inserted in the horizontal back porch is detected in a horizontal scanning cycle subsequent to a horizontal scanning cycle in which the potential of the pedestal level is held zero. Accordingly, the reference voltage can be accurately detected for accurate contrast control even if the back porch is comparatively short. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Fig. 1 is a circuit diagram of a contrast control circuit according to a preferred embodiment of the present invention; Fig. 2 is a time chart showing signals generated by the components of the contrast control circuit of Fig. 1; Fig. 3 is a diagram showing the relation between a video signal, a reference pulse and a background pulse used in the contrast control circuit of Fig. 1; Fig. 4 is a block diagram of a previously proposed CRT controller; Fig. 5 is a circuit diagram of a previously proposed contract control circuit; Fig. 6 is a time chart showing signals generated by the components of the contrast control circuit of Fig. 5; and Fig. 7 is a diagram showing the relation between a video signal, a reference pulse and a background pulse used in the contrast control circuit of Fig. 5. A contrast control circuit shown in Fig. 1 corresponds to the contrast control circuit 10 of the CRT controller shown in Fig. 4 and the configuration of a portion of the contrast control circuit comprising capacitors C1 and C2, switches SW1 and SW2, a resistor R and a variable voltage source for setting a specified contrast voltage VR1 and an operational amplifier OP1 is the same as that of the corresponding portion of the previously proposed contrast control circuit shown in Fig. 5. Referring to Fig. 1, a synchronous separation circuit 22 extracts a horizontal synchronizing signal HD and a vertical synchronizing signal VD from an input video signal, and applies the horizontal synchronizing signal HD to monostable multivibrators 24 and 26. The monostable multivibrator 24 is triggered by the horizontal synchronizing signal to provide a background pulse. The monostable multivibrator 26 is triggered by the horizontal synchronizing signal to provide a reference pulse. The horizontal synchronizing signal HD is applied also to the clock input terminal D of a D flip-flop 28. The inverted output of the D flip-flop is applied to the D input terminal of the D flip-flop 28. The output of the D flip-flop 28 and the inverted output are applied respectively to the reset terminal of the monostable multivibrator 24 and the reset terminal of the monostable multivibrator 26. Then, the monostable multivibrators 24 and 26 provide output pulses alternately in alternate horizontal scanning cycles 1H, respectively, as shown in Fig. 2. If horizontal scanning frequency is decreased, there is a minute difference in gain between the sampling of a reference pulse inserted in a white line and the sampling of a reference pulse inserted in a black line by an on/off signal for each line, i.e., by the on/off operation of the switch SW2 by the reference pulse. If the number of all the lines is an odd number, the lines flickers. Therefore, the D flip-flop 28 is reset by the vertical synchronizing signal VD provided by the synchronous separation circuit 22 so that the sampling condition is the same for all the fields. The background pulse is applied as a closing command signal through a buffer 30 to the switch SW1. The reference pulse is applied as a closing command signal through a buffer 32 to the switch SW2. The output signal of the video frequency amplifier 4 of the CRT control circuit shown in Fig. 4 applied to the capacitor C1 is clamped by the switch SW1 so that the potential of the pedestal level is zero while the background pulse is HIGH on an (n+1)th horizontal scanning line as shown in Fig. 3. The leading edge of the reference pulse inserted in the video signal is sampled by the switch SW2 while the reference pulse is HIGH on an nth horizontal scanning line as shown in Fig. 3. Accordingly, the reference pulse of a positive potential with respect to the ground is detected in every other horizontal scanning cycle, i.e., once in two horizontal scanning cycle. The operational amplifier OP1 compares the voltage of the peak value of the reference pulse sampled by the action of the switch SW2 with a contrast voltage VR1 specified by the user, and provides a control voltage to control the gain of the video frequency amplifier 4 so that the voltage of the peak value of the reference pulse will coincide with the contrast voltage VR1 and applies the control voltage to the video frequency amplifier 4 for feed back control. The contrast control circuit of the present embodiment is capable of controlling the contrast even if the length of the back porch is about half the 1.6 µ sec. The contrast control circuit of the present embodiment shown in Fig. 1 differs from the previously proposed contrast control circuit shown in Fig. 5 only in the method of producing the reference pulse and the background pulse, and is provided additionally only the D flip-flop 28 which generates a reset pulse in order that the cycles of the outputs of the monostable multivibrators 24 and 26 are twice the horizontal scanning cycle, and the phases of the outputs of the monostable multivibrators 24 and 26 are shifted by one horizontal scanning cycle relative to each other. Accordingly, the embodiment of figure 1 provides a contrast control circuit capable of controlling contrast even if the duration of the back porch is less than 1.6 µ sec. Although the invention has been described in its preferred form with a certain degree of particularity, obviously many changes and variations are possible therein. It is therefore to be understood that the present invention may be practiced otherwise than as specifically described herein without departing from the scope thereof, as defined by the appended claims.

Claims: A contrast control circuit comprising: a clamping means (24, 28, SW1) for clamping a video signal so that the potential of the pedestal level is held zero once every N horizontal scanning cycles, where N is an integer not smaller than two; a voltage detecting means (26, 28, SW2) for detecting the reference voltage of a reference pulse inserted in a horizontal back porch, once every N horizontal scanning cycles and in horizontal scanning cycles other than the horizontal scanning cycles in which said clamping means clamps a video signal so that the potential of the pedestal level is held zero; and a control means (OP1) which generates a contrast control signal on the basis of the reference voltage detected by said voltage detecting means and a specified voltage specified by operating a specified voltage setting source. A contrast control circuit according to claim 1, wherein N = 2.

Inventors: NAKAZONO HIROYUKI, UMEMURA JUNJI, NAKAZONO, HIROYUKI, UMEMURA, JUNJI, Nakazono, Hiroyuki, c/o Intellectual Property Div., Umemura, Junji, c/o Intellectual Property Division
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: G09G1
IPC codes: G09G1, H04N5