Method for planarization of an integrated circuit

Abstract: After a first conducting layer (22) is deposited and patterned, a first insulating layer (24) is deposited over the device. A planarizing layer (26) is then deposited over the integrated circuit and etched back. Portions of the planarizing layer (26) may remain in the lower topographical regions of the first insulating layer (24) to planarize the surface of the device. A second insulating layer (28) is then deposited over the integrated circuit, followed by a third insulating layer (30). A contact via (32) is formed through the layers to expose a portion of the first conducting layer (22). A second conducting layer (34) can now be deposited and patterned on the device to make electrical contact with the first conducting layer (22).

Description: The present invention relates generally to the fabrication of semiconductor integrated circuits, and more specifically to a method for manufacturing integrated circuits having multilayers of metal interconnect lines. By increasing the density of components in an integrated circuit, it is necessary to use multiple layers to fabricate the various components, and contacts between the layers to connect one layer to another. Fabricating the contacts and multiple layers, however, results in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to maintain constant cross sections when crossing over uneven topography. This can lead to step coverage problems, such as voids in the metal interconnect lines and contacts. Step coverage problems can also result in the metal interconnect lines having a higher current density. These defects can cause electromigration or other related device failure mechanisms. Therefore, it would be desirable to provide a method for fabricating integrated circuits which alleviates step coverage problems and presents a planarized topography. It is also desirable that such a method does not significantly increase the complexity of the manufacturing process. European patent application publication number 0387098 discloses a process for making a multi-level interconnection structure in which a first conductive layer is formed, an interlayer insulating layer is formed, a spin-on-glass layer is formed and etched back, a further glass layer is formed and a contact opening to the first conductive layer is formed. A further conductive layer is then formed in the opening to contact the first conductive layer. German patent application publication number 4102422 discloses a process for fabricating a multi-level wiring structure in which lower-level wiring strips are formed and covered with a first intermediate insulating film. The entire surface is coated with organic glass, etched, coated with inorganic glass, etched, and covered with a second intermediate insulating layer. Thus a method is provided for better planarization of an integrated circuit. After a first conducting layer is deposited and patterned, a first insulating layer is deposited over the device. A thick planarizing layer is then deposited over the integrated circuit and etched back. Portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the device. A second insulating layer is then deposited over the integrated circuit, followed by a third insulating layer. A contact via is formed through the layers to expose a portion of the first conducting layer. A second conducting layer can now be deposited and patterned on the device to make electrical contact with the first conducting layer. According to claim 1 of the present invention there is provided a structure in an integrated circuit, comprising a first conductive layer defining an interconnect layer, a first insulating layer overlying the integrated circuit, wherein an upper surface of the first insulating layer is non-planar and contains lower and higher topographical regions, a plurality of planarizing material regions on the first insulating layer, wherein the planarizing material regions fill in the lower topographical regions so that an upper surface of the first insulating layer is substantially coplanar with upper surfaces of the planarizing material regions thereby forming a substantially planar upper surface, wherein no planarizing material regions lie above a selected portion of the first conductive layer, a layer of insulating material overlying the first insulating layer and the planarizing material regions, an opening through the layer of insulating material and the first insulating layer exposing the selected portion of the first conductive layer and a second conductive layer overlying portions of the layer of insulating material and extending into the opening to make electrical contact with the first conductive layer, characterized in that the layer of insulating material is a multi layer comprising a second insulating layer overlying the integrated circuit and a third insulating layer overlying the second insulating layer, wherein the third insulating layer is formed from a material which can be selectively etched over the second insulating layer. According to claim 9 of the present invention there is provided a method for forming an integrated circuit structure, comprising the steps of forming a conductive element on an underlying region in the integrated circuit having a non-planar upper surface containing lower and higher topographical regions, forming a first insulating layer over the integrated circuit, forming a planarizing layer over the first insulating layer, etching the first insulating and planarizing layers wherein portions of the planarizing layer remain in lower topographical regions of the first insulating layer, such that the upper surface of the integrated circuit is planarized, forming a layer of insulating material over the integrated circuit, forming a contact via through the layer of insulating material and first insulating layer and any remaining planarizing layer to expose a portion of the conductive element and depositing and patterning a conductive layer over portions of the integrated circuit, which layer extends into the contact via to make electrical contact with the conductive element, characterized in that the step of forming the layer of insulating material comprises forming a second insulating layer over the integrated circuit and forming a third insulating layer over the second insulating layer, the third insulating layer being formed of a material which can be selectively etched over the second insulating layer. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Figures 1 - 7 are sectional views of an integrated circuit illustrating a preferred method for planarization of an integrated circuit according to the present invention. The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. With reference to Figure 1, an integrated circuit will be built on a substrate 10 . Field oxide region 12 is formed to isolate the active areas within the substrate 10 . Gate electrodes 14 , 16 are formed on the device using methods known in the art, followed by the deposition of a first insulating layer 18 . The first insulating layer 18 is typically made of oxide and has a thickness of approximately 5000 angstroms. The first insulating layer 18 is patterned to expose a portion of the substrate 10 , and conductive interconnect 20 is then formed in the opening to make electrical contact with the substrate 10 . Conductive interconnect 22 is formed on the first insulating layer 18 . Conductive interconnects 20 , 22 can be made from metal or polycrystalline silicon. Referring to Figure 2 , a second insulating layer 24 is deposited over the integrated circuit. The second insulating layer 24 is preferably made from boron doped oxide, but can consist of other insulating materials, depending upon which etch back process and via formation process is used. As known in the art, boron doped oxide is conformal to its underlying structures, which allows it to fill in and adhere to sidewalls and lower topographical areas on the integrated circuit. A planarizing layer 26 is then deposited over the second insulating layer 24 . The planarizing layer 26 is preferably made from spin on glass, and has a thickness of approximately 5500 angstroms. The thick coating of spin on glass will planarize the surface of the integrated circuit. Figure 3 illustrates the integrated circuit after an anisotropic etch is performed to remove portions of the planarizing layer 26 . As known in the art, the second insulating layer 24 helps to minimize the loading effects created during the etchback. As can be seen, portions of the planarizing layer 26 may remain in the lower topographical regions of the second insulating layer 24 , creating a planarized surface. Alternatively, planarizing layer 26 can be completely etched away so that the second insulating layer 24 planarizes the surface of the integrated circuit. Referring to Figure 4 , a third insulating layer 28 is deposited over the device. The third insulating layer 28 is preferably made of boron doped oxide, and has a thickness of approximately 1500 angstroms. A fourth insulating layer 30 is then deposited over the third insulating layer 28 . The fourth insulating layer 30 is preferably made of undoped oxide, and has a thickness of approximately 4000 angstroms. Figure 5 illustrates the device after a contact via 32 is formed through the layers to expose a portion of the metal interconnect 20 . The contact via 32 is preferably created by first performing an isotropic etch through the fourth insulating layer 30 . During this process, the third insulating layer 28 acts as an etch stop and protects the underlying layers from damage during the isotropic etch. To complete formation of the contact via 32 , an anisotropic etch is performed through the remaining layers to expose a portion of the metal interconnect 20 . Alternatively, an anisotropic etch can be performed to create the contact via 32 . Referring to Figure 6 , a second metal interconnect layer 34 is deposited and patterned on portions of the fourth insulating layer 30 and extends into the contact via 32 to make electrical contact with the metal interconnect 20 . The integrated circuit is now ready for further processing steps. Figure 7 illustrates the integrated circuit after the processing steps described in connection with Figures 2 - 6 are repeated. As shown, a fifth insulating layer 36 similar to the second insulating layer 24 is deposited over the device and covers the second metal interconnect 34 . A layer of planarizing material has been deposited over the fifth insulating layer (not shown) and etched back creating pockets of planarizing material 38 . A sixth insulating layer 40 similar to the third insulating layer 28 is deposited over the device, followed by a seventh insulating layer 42 . The seventh insulating layer 42 is similar to the fourth insulating layer 30 . A contact via is formed as described with reference to Figure 5, and a third metal interconnect 44 is created in the contact via. The third metal interconnect 44 is formed by depositing and patterning a metal such that electrical contact is made between metal interconnect layers 34 and 44 . As described above, the present invention provides a method for improved planarization of the surface of an integrated circuit. The advantages of this method include the ability to form contact vias by performing an isotropic etch followed by a anisotropic etch. Moreover, underlying layers are protected during formation of the contact vias through the use of an etch stop. The boron doped oxide also has excellent conformality and adheres to the sidewalls and fills in the lower portion of the contact vias. Consequently, reduced amounts of planarizing material are required to planarize the surface of the integrated circuit. Finally, this method does not significantly increase the complexity of the manufacturing process.

Claims: A structure in an integrated circuit, comprising: a first conductive layer (20) defining an interconnect layer; a first insulating layer (24) overlying the integrated circuit, wherein an upper surface of the first insulating layer (24) is non-planar and contains lower and higher topographical regions; a plurality of planarizing material regions (26) on the first insulating layer (24), wherein the planarizing material regions (26) fill in the lower topographical regions so that an upper surface of the first insulating layer (24) is substantially coplanar with upper surfaces of the planarizing material regions (26) thereby forming a substantially planar upper surface, wherein no planarizing material regions (26) lie above a selected portion of the first conductive layer (20); a layer (28,30) of insulating material overlying the first insulating layer (24) and the planarizing material regions (26); an opening (32) through the layer of insulating material (28,30) and the first insulating layer (24) exposing the selected portion of the first conductive layer (20), and a second conductive layer (34) overlying portions of the layer of insulating material (28,30) and extending into the opening (32) to make electrical contact with the first conductive layer (20), characterized in that the layer of insulating material is a multi layer comprising: a second insulating layer (28) overlying the integrated circuit; and a third insulating layer (30) overlying the second insulating layer (28), wherein the third insulating layer (30) is formed from a material which can be selectively etched over the second insulating layer (28). The structure of claim 1 wherein the opening extends vertically through the first (24) and second (28) insulating layers, and wherein the opening (32) has rounded upper corners within the third insulating layer (30). The structure of claim 1 or claim 2 wherein the second insulating layer (28) is made of boron doped oxide. The structure of claim 1, 2 or 3 wherein the third insulating layer (30) is made of undoped oxide. The structure of any one of claims 1 to 4 wherein the first conductive layer (20) is made of metal. The structure of any one of claims 1 to 5 wherein the second conductive layer (34) is made of a metal. The structure of any one of claims 1 to 6 wherein the planarising material is made of spin-on-glass. The structure of any one of claims 1 to 7 wherein the first insulating layer (24) comprises boron doped oxide A method for forming an integrated circuit structure, comprising the steps of: forming a conductive element (20) on an underlying region in the integrated circuit having a non-planar upper surface containing lower and higher topographical regions; forming a first insulating layer (24) over the integrated circuit; forming a planarizing layer (26) over the first insulating layer (24); etching the first insulating (24) and planarizing (26) layers wherein portions of the planarizing layer (26) remain in lower topographical regions of the first insulating layer (24), such that the upper surface of the integrated circuit is planarized; forming a layer of insulating material (28,30) over the integrated circuit; forming a contact via (32) through the layer (28,30) of insulating material and first insulating layer (24) and any remaining planarizing layer (26) to expose a portion of the conductive element (20); and depositing and patterning a conductive layer (34) over portions of the integrated circuit, which layer (34) extends into the contact via (32) to make electrical contact with the conductive element (20); characterized in that the step of forming the layer of insulating material comprises: forming a second insulating layer (28) over the integrated circuit; and forming a third insulating layer (30) over the second insulating layer (28), the third insulating layer (30) being formed of a material which can be selectively etched over the second insulating layer (28). The method of claim 9 wherein said step of forming the contact via (32) comprises isotropically etching through portions of the third insulating layer (30), followed by anisotropically etching through any remaining third insulating layer (30) and planarizing layer (26), and the second (20) and first (24) insulating layers to expose a portion of the conductive element (20). The method of claim 9 or claim 10 wherein said step of forming the conductive element (20) comprises depositing and patterning a layer of metal over a portion of the underlying region in the integrated circuit. The method of claim 11 wherein said underlying region comprises a semiconductor substrate (10). The method of any one of claims 9 to 12 wherein said step of forming a first insulating layer (24) comprises depositing a layer of oxide over the integrated circuit. The method of any one of claims 9 to 13 wherein said step of forming the planarizing layer (26) comprises depositing a spin-on-glass over the first insulating layer (24). The method of any one of claims 9 to 14 wherein said step of etching the planarizing (26) and first (24) insulating layers comprises anisotropically etching said layers.

Inventors: HUANG KUEI-WU, LIN YIH-SHUNG, LU LUN-TSENG, HUANG, KUEI-WU, LIN, YIH-SHUNG, LU, LUN-TSENG
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS, INC.
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L23