High electron mobility transistor

Abstract: A compound semiconductor device including a substrate; a first epitaxial layer formed on the substrate, the first epitaxial layer having an impurity concentration of 1 × 10¹⁵ ≦ p ≦ 1 × 10¹⁶ (cm⁻³); and a second epitaxial layer formed on the first epitaxial layer for allowing travel of two-dimensional electrons, the second epitaxial layer having an impurity concentration of n ≦ 1 × 10¹⁴ (cm⁻³) and p ≦ 1 × 10¹⁴ (cm⁻³). Accordingly, a short channel effect due to a reduction in gate length is hard to occur, thereby ensuring high characteristics of the compound semiconductor device.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a high electron mobility transistor (which will be hereinafter abbreviated to HEMT). 2. Description of the Prior Art A HEMT, a kind of FET, employing a GaAs/n-AlGaAs selectively doped hetero junction has now been developed to realize a very high speed computer and a high speed signal processing system. In such a HEMT, a crystal region (e.g., undoped GaAs) for allowing travel of electrons and a crystal region (e.g., Si doped n-AlGaAs) for supplying electrons are separated from each other by a hetero junction, and scattering of electrons by donor impurities is reduced to thereby increase an electron mobility and improve a high-speed performance. Fig. 1 schematically shows a device structure of a GaAs/AlGaAs HEMT in the prior art, cf. Fig. 1 of US-A-5028968. An undoped GaAs layer 11 as an active layer is formed on a semi-insulating GaAs substrate 10. An i-AlGaAs layer 12 is formed on the undoped GaAs layer 11. An Si doped n-AlGaAs layer 13 as an electron supplying layer is formed on the i-AlGaAs layer 12. An Si doped n-GaAs layer 14 is formed on the n-AlGaAs layer 13. Further, a gate electrode 15 ,a source electrode 16 and a drain electrode 17 are formed on the n-GaAs layer 14. In Fig. 1, a hatched portion under the source electrode 16 and the drain electrode 17 is an ohmic region. The formation of a current channel (shown by a broken line in Fig. 1) for realizing an FET operation is based on the phenomenon that the electrons supplied from the donor impurities added in the n-AlGaAs layer 13 as the electron supplying layer are moved to the undoped GaAs layer 11 as the active layer and are accumulated in a portion of the undoped GaAs layer 11 in the vicinity of a junction interface between the n-AlGaAs layer 13 and the undoped GaAs layer 11. This current channel is a so-called two-dimensional electron channel. There is a tendency that a gate length L g has increasingly been shortened, so as to realize a high performance of the HEMT. However, the reduction in the gate length L g causes a short channel effect such that the two-dimensional electrons exude toward the substrate to reduce a mutual conductance g m and accordingly deteriorate the characteristics of the HEMT. To prevent the short channel effect, the following three techniques have conventionally been proposed. (A) To substitute the undoped GaAs layer as the active layer by a p - -GaAs layer. (B) To make the active layer into an InGaAs strain layer channel (C) To provide an i-AlGaAs layer in the undoped GaAs layer as the active layer and form a hetero junction. In the technique (A), the electrons in the active layer are scattered by the impurities existing in the active layer to reduce the electron mobility. Further, the number of two-dimensional electron carriers is also reduced. In the technique (B), a lattice constant of the InGaAs layer is different from that of the n-GaAs layer, and a strain of the InGaAs layer increases with an increase in thickness of the InGaAs layer. As a result, lattice defect in the InGaAs layer increases to reduce the electron mobility. Accordingly, the thickness of the InGaAs layer is limited to a critical thickness of 15 to 20 nm, and the InGaAs layer cannot be thickened. However, in the InGaAs layer having such a critical thickness, the number of two-dimensional electron carriers is reduced. In the technique (C), the two-dimensional electron gas is scattered in the vicinity of the hetero junction interface between the undoped GaAs layer and the i-AlGaAs layer to reduce the electron mobility, causing the generation of noise. SUMMARY OF THE INVENTION It is an object of the present invention to provide a compound semiconductor device having high characteristics which can suppress a short channel effect due to a reduction in gate length L g . According to the present invention attaining the above object, there is provided an InGaAs/InAlAs heterojunction high electron mobility semiconductor device comprising a substrate; a first epitaxial layer of p-type InGaAs formed on said substrate, said first epitaxial layer having an impurity concentration of 1 × 10 15 ≦ p ≦ 1 × 10 16 (cm -3 ); and a second epitaxial layer of InGaAs formed on said first epitaxial layer for allowing travel of two-dimensional electrons, said second epitaxial layer having an impurity concentration of n ≦ 1 × 10 14 (cm -3 ) and p ≦ 1 × 10 14 (cm -3 ), an undoped layer of InAlAs formed on said second epitaxial layer, and an n-type layer of InAlAs formed on said undoped layer of InAlAs. The first epitaxial layer has a thickness of preferably 500 to 1000 nm, and the second epitaxial layer has a thickness of preferably 20 to 100 nm. In the compound semiconductor of the present invention, the two-dimensional electrons traveling in the second epitaxial layer is little susceptible to scattering by the impurities. Accordingly, a high electron mobility can be attained. Further, since the first epitaxial layer is provided, the two-dimensional electrons can be effectively confined in the hetero junction interface between the first epitaxial layer and the second epitaxial layer. Therefore, a short channel effect is hard to occur. Moreover, since the two-dimensional electrons travel in a portion of the second epitaxial layer remote from the first epitaxial layer, a reduction in number of carriers by acceptors existing in the first epitaxial layer does not occur. Accordingly, a high sheet carrier concentration can be obtained. Other objects and features of the invention will be more fully understood from the following detailed description and appended claims when taken with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic sectional view of a HEMT in the prior art; and Fig. 2 is a schematic sectional view of a compound semiconductor device according to the present invention, said view being substantially identical to Fig. 2 of US-A-5028968. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the compound semiconductor device according to the present invention will now be described with reference to the drawings. Fig. 2 shows a schematic sectional view of a HEMT as a compound semiconductor device which differs from the "Radiation Hard GaAs High Electron Mobility Transistor" of US-A-5028968 mainly in the thicknesses and impurity concentrations of the semiconductor layers. The semiconductor device is manufactured by MOCVD in the following manner. First, a first epitaxial layer 21 is formed on a semi-insulating GaAs substrate 10. The first epitaxial layer 21 is a p - -GaAs layer having a thickness of 500 nm. An impurity concentration in the first epitaxial layer 21 is p = 5 x 10 15 (cm -3 ). The impurity concentration in the first epitaxial layer 21 may be fixed or sloped. Then, a second epitaxial layer 22 is formed on the first epitaxial layer 21. The second epitaxial layer 22 is an i-GaAs layer having a thickness of 50 nm. An impurity concentration in the second epitaxial layer 22 is n = 1 × 10 14 (cm -3 ) and p = 1 × 10 14 (cm -3 ). The first epitaxial layer 21 and the second epitaxial layer 22 may be formed by controlling a ratio of AsH 3 and Ga(CH 3 ) 3 in MOCVD, for example. Then, an i-Al 0.3 Ga 0.7 As layer 23 is formed on the second epitaxial layer 22. Then, an n-Al 0.3 Ga 0.7 As layer 24 is formed on the i-Al 0.3 Ga 0.7 As layer 23. Then, an n-GaAs layer 25 is formed on the n-Al 0.3 Ga 0.7 As layer 24. Then, on the basis of a conventional HEMT manufacturing process, element separation is carried out, and source and drain electrode metal (Au·Ge/Ni) is deposited under vacuum on the n-GaAs layer 25 to carry out alloying for obtaining ohmic contact with the second epitaxial layer 22. Then, photoresist is coated on the whole surface of the metal layer, and a T-shaped gate electrode pattern is then formed through the photoresist. Then, the n-GaAs layer 25 and the n-Al 0.3 Ga 0.7 As layer 24 are etched to form a recess as shown in Fig. 2. Then, gate electrode metal (Ti-Pt-Au or Al) is deposited under vacuum on the n-Al 0.3 Ga 0.7 As layer 24 in the recess. Thus, a T-shaped gate electrode 26 having a gate length L g of 0.15µm, a source electrode 27 and a drain electrode 28 are formed to complete a low-noise HEMT. In this HEMT, a two-dimensional electron channel is formed in the second epitaxial layer 22 about a position remote by about 10 nm from the interface between the second epitaxial layer 22 and the i-Al 0.3 Ga 0.7 As layer 23 The compound semiconductor device described so far is basically known from the US-A-5,028,968. According to the present invention the basic principles of the HEMT as described forming the GaAs/AlGaAs heterojunction are to be applied to a HEMT forming an InGaAs/InAlAs heterojunction, wherein the InGaAs layer comprises the first and second epitaxial layers characterized in the appended claims. Although each layer is formed by MOCVD in the above preferred embodiment, it may be formed by MBE rather than MOCVD. Further, a buffer layer may be formed between the semi-insulating substrate and the first epitaxial layer. In the compound semiconductor device of the present invention, a short channel effect due to a reduction in gate length can be suppressed and C gs can be reduced, so that a high mutual conductance g m can be obtained to ensure a superior low-noise characteristic. Furthermore, since the compound semiconductor device has no critical thickness as in the InGaAs strain layer channel mentioned previously, the two epitaxial layers can be optimally set. Further, there is no generation of noise due to the hetero junction interface as in the traditional case where the i-AlGaAs layer is provided in the undoped GaAs layer as the active layer. While the invention has been described with reference to specific embodiments, the description is illustrative and is not to be construed as limiting the scope of the invention. Various modifications and changes may occur to those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims: An InGaAs/InAlAs hetero junction high electron mobility semiconductor device comprising: a substrate (10); a first epitaxial layer (21) of p-type InGaAs formed on said substrate, said first epitaxial layer having an impurity concentration of 1 x 10 15 ≤ p ≤ 1 x 10 16 (cm -3 ); a second epitaxial layer (22) of InGaAs formed on said first epitaxial layer for allowing travel of two-dimensional electrons, said second epitaxial layer having an impurity concentration of n ≤ x 10 14 (cm -3 ) and p ≤ 1 x 10 14 (cm -3 ); an undoped layer of InAlAs (23) formed on said second epitaxial layer; and a n-type layer of InAlAs (24) formed on said undoped layer of InAlAs. The semiconductor device as defined in claim 1, wherein said second epitaxial layer (22) has a thickness of 20 to 100 nm. The semiconductor device as defined in claim 1, wherein said first epitaxial layer (21) has a thickness of 500 to 1000 nm. The semiconductor device as defined in any of the preceding claims, wherein a buffer layer is formed between said substrate (10) and said first epitaxial layer (21).

Inventors: HIRAMATSU SHIGERU, HIRAMATSU, SHIGERU, HIRAMATSU, SHIGERU, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H01L29
IPC codes: H01L21, H01L29