Methods for growing compound semiconductor layers

Abstract: In a method for producing a compound semiconductor device such as laser diodes, FET and HEMT, compound semiconductor is grown at a substrate temperature not greater than 500°C to form a semiconductor layer on a substrate of the semiconductor device. Then, an appropriate treatment, such as heat-treatment in reducing atmosphere, current flow treatment and hydrogen plasma treatment, is conducted to reduce crystal defects in the semiconductor layer attributable to the crystal growth at the low substrate temperature not greater than 500°C.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to methods for producing semiconductor devices, in which a substrate or a layer formed thereon is composed of GaAs, AlGaAs, Si, ZnSe or the like, and their substrate or growth temperatures are relatively low, for example, not greater than 500°C. In such methods, crystallinity or crystallization of the devices is improved by an appropriate process conducted after the layer-growth process. The method is preferably utilized as a method of producing a semiconductor device which includes a sharp and flat compound semiconductor hetero-interface or boundary plane, typically, a quantum well structure having a hetero boundary plane of two flat compound semiconductors. Related Background Art It has been conventionally known that a boundary plane having a steep composition profile in a direction perpendicular to a substrate plane can be readily formed by controlling a supply of III group (e.g., Al) molecules when a hetero-junction between different kinds of III - V group compound semiconductors (e.g., GaAs and AlGaAs) is fabricated by the molecular beam epitaxy (MBE) method. This kind of crystal growth of III - V group compound semiconductors by MBE is generally two or three dimensional growth from a growth core, and the hetero boundary plane is formed at an arbitrary timing by opening or closing of a shutter for controlling the supply of III group molecules. In this hetero-interface, there is a step of at least one atomic layer in a plane parallel to the substrate plane. The existence of the step can be known from facts that a plurality of peaks appear in photoluminescence from AlGaAs/GaAs quantum well structure or GaAs/AlAs quantum well structure, and that an energy interval between the peaks is equal to difference in a bound-state energy in the quantum well occurring when the thickness of quantum well is changed by one atomic layer. For example, it is reported that the boundary plane becomes flat by momentary interruption of the crystal growth at the hetero interface (see Jpn. J. Appl. Phys. 24, 1417 (1985)). Further, the crystal growth by the migration enhanced epitaxy (MEE) method is also known. For example, it is reported that crystal having excellent crystallinity and interface flatness can be obtained by MEE in which Ga and As are alternately grown one by one atomic layer (see Jpn. J. Appl. Phys. 25, 868 (1986)). Following techniques are also known: Conventionally, it has been reported that the threshold current density of a semiconductor laser fabricated by the molecular beam epitaxy (MBE) method was raised when the semiconductor laser was produced at a growth temperature in a relatively low temperature range, as, for example, Appl. Phys. Lett. Vol. 36, p. 118 (1980) W. T. Tsang et al. discloses. Fig. 1 shows the structure of such laser. Fig. 2 illustrates the relationship between the threshold current density J th and the substrate temperature. In Fig. 1, there are formed, on an n-GaAs substrate 201, an Si doped GaAs buffer layer 202 having a thickness of 0.5 µ m, an Si doped Al 0.3 Ga 0.7 As layer 203 having a thickness of 1.5 µ m, an undoped GaAs active layer 204 having a thickness of 0.1 µ m, a Be doped Al 0.3 Ga 0.7 As layer 205 having a thickness of 1.5 µ m, a Be doped GaAs contact layer 206 having a thickness of 0.5 µ m and a Cr/Au alloy electrode 207 deposited on the contact layer 206. After the n-GaAs substrate 201 is thinned to a thickness of approx. 100 µ m, an AuGe/Ni/Au electrode 208 is deposited on the bottom surface of the substrate 201. As is seen from Fig. 2 showing a substrate temperature dependency of threshold current density J th of the thus fabricated laser which has a stripe width of 100 µ m and a cavity length of 300 µ m, the J th of such laser is small near the substrate temperature of 650°C. Namely, its performance is improved near such substrate temperature. In contrast, J th becomes greater than 14 kA/cm 2 in the vicinity of substrate temperature of 300°C. This value of threshold current density far surpasses the value of about 3 kA/cm 2 below which a laser can practically be utilized. Thus, it is seen that the characteristic of a laser is lowered at such low substrate temperatures. In recent years, there has been a growing interest in opto-electronic integrated circuits (OEIC) in which optical devices and electric or electronic devices are integrated on a common substrate (see J. Vac. Sci. Technol. B2(2), 259 (1984), Very low threshold current GaAs-AlGaAs GRIN-SCH lasers grown by MBE for OEIC applications). The OEIC features an enhanced reliability, relatively low cost, compactness in size and so forth, and is considered an important technology. However, its fabrication temperature becomes a problem when the integration is conducted. That is, in conventional methods, the fabrication or substrate temperature is high when devices are produced, and hence inter-diffusions of composite elements and impurities are caused, leading to incapability of creating ideal doping profiles or distributions and ideal structures. As is described above, optical devices such as semiconductor lasers are usually fabricated at temperatures greater than 600 °C , and presently at still higher temperatures of about 700°C in order to better their performances. In contrast, electronic devices are principally produced at the growth temperature of about 500 °C so that inter-diffusions of impurities or the like should be prevented. So, there is presently a temperature difference of about 200 °C. between fabrication temperatures of optical devices and electronic devices. Therefore, electronic devices are always produced after optical devices have been fabricated in order to achieve their integration while maintaining good characteristics of the electronic devices. Thus, the fabrication process becomes complicated since a plurality of epitaxial growths having different steps are to be conducted. Fig. 3 illustrates an example of diffusion in Si doped GaAs. As seen from Fig. 3, an ideal duping shape 182 in fact greatly collapses at the growth temperature of 550 °C as indicated by a line 183. As is discussed in the foregoing, a low temperature growth is a very critical technique in semiconductor processes. In particular, a low temperature growth of semiconductor lasers which are key optical devices is important for the integration of optical and electronic devices. A hetero-epitaxy technique for growing a III - V group compound semiconductor such as GaAs on an Si substrate has been particularly highlighted in recent years in the light of hetero-junctions with lattice mismatching. If GaAs and the like can be grown on an Si substrate, a less expensive substrate having a large area becomes available, and hence the following advantages will be obtained. 1 ○ A highly efficient solar battery can be obtained. 2 ○ It becomes possible to monolithicly form Si and GaAs materials, and hence OEIC's with satisfying performances can be achieved. 3 ○ High speed GaAs ICs and high electron mobility transistor (HEMT) ICs can be fabricated on a substrate having a large area. 4 ○ Heat radiation of power devices and semiconductor devices is improved because Si has a larger thermal conductivity than GaAs. However, such growths are difficult to attain by usual methods since there exist 4 % lattice mismatching and a difference in thermal expansion coefficients between Si and GaAs. There have been developed the following methods for alleviating the lattice mismatching between Si and GaAs. 1 ○ A GaAs/Ge/Si structure is fabricated using an intermediate layer of Ge. 2 ○ After an Si substrate is cleaned at high temperatures, a thin, amorphous GaAs layer is grown at low temperatures and the temperature is raised in order to grow GaAs at normal growth temperatures. This is a two-step growth method for obtaining a structure of GaAs/low temperature GaAs/Si. 3 ○ A GaAs/AlGaAs super-lattice is grown on Si and then GaAs is grown thereon to produce a structure of GaAs/GaAs-AlGaAs super-lattice/Si. 4 ○ A strain super-lattice is formed as an intermediate layer to obtain a structure of GaAs/strain super-lattice/Si. The MBE and metal-organic chemical vapor deposition (MOCVD) methods are used for growth of Layers, and single crystal GaAs has been obtained in all of those methods. Samples of various devices such as FETs, solar batteries and semiconductor lasers are made using GaAs grown on Si. It has also been reported that a GaAs/AlGaAs double hetero-laser fabricated on a Si substrate was successfully radiated at room temperature, though this is inferior to those grown on a GaAs substrate in characteristic. Figs. 4, 5A and 5B show characteristics of such example and its structure. In Fig. 4, an MOCVD apparatus at normal temperatures is used. There are provided, on an n-type Si substrate 171 of (100) 2° off, a GaP layer 172 having a thickness of 0.1 µ m formed at temperature of 900 °C, a GaP/GaAsP strain super-lattice (20 nm/20 nm × 5) layer 173 formed at 750 °C, an n-GaAs layer 174 having a thickness of 2 µ m and impurity concentration of 2 × 10 18 cm -3 , an n-Al x Ga 1-x As lower cladding layer 175 having a thickness of 1.4 µ m and impurity concentration of 1 × 10 18 cm -3 , an undoped GaAs active layer 176 having a thickness of 0.08 µ m, a p-Al x Ga 1-x As upper cladding layer 177 having a thickness of 1.4 µ m and impurity concentration of 4×10 17 cm -3 and a p-GaAs layer 178 having a thickness of 0.65 µ m and impurity concentration of 1.3 × 10 18 cm -3 . On this structure, an Au-Zn/Au electrode 180 is deposited at a p-side while an Au-Ge/Au electrode 181 is deposited at an n-side. Its stripe width and cavity length are respectively set to 10 µ m and about 100 µ m. Fig. 5A illustrates the characteristic of a laser formed on a GaAs substrate, and Fig. 5B illustrates the characteristic of the above-mentioned laser produced on Si substrate 171. It can be seen therefrom that oscillations of the TE+TM mode and TM mode occur in the laser on Si while an oscillation of only TE mode is caused in a double-hetero (DH) laser on GaAs. This phenomenon is considered to be attributable to the fact that the GaAs layer grown on Si receives a strain of about 10 8 Pa (10 9 dyn/cm 2 ) since the thermal expansion coefficient is different between Si and GaAs and that its degenerated hole energy level is split to create light and heavy hole levels. Thus, although the laser oscillation is somehow achieved in the laser produced on a Si substrate with improvement, such semiconductor laser has the following drawbacks as yet. 1 ○ Presently, a GaAs layer grown on Si substrate has an etch pit of 1×10 6 cm -2 , but the value of the etch pit is preferably less than 1 × 10 -3 cm -2 in light of the lifetime of lasers. 2 ○ The GaAs laser is produced at a high temperature of 700 °C, and hence a large stress occurs due to the difference in thermal expansion coefficient between Si and GaAs. In fact, this influence appears in the laser characteristic of TM mode oscillation and the like. Thus, strain and the like have not yet been solved completely due to the differences in lattice constants between Si and GaAs and in thermal expansion coefficient, and the lifetime of laser is adversely affected. Unless those problems are solved, it is difficult to reduce such semiconductor lasers fabricated on the Si substrate into practice. Next, a compound technique of semiconductor materials is important for optical communication technique, display technique and the like. For example, it has been attempted to integrate semiconductor materials corresponding to three primary colours of light on a common substrate for satisfying requirements of flat panel displays and the like. As examples of such materials, AlGaAs can be cited for red colour, GaP for yellow, and ZnSe for blue. A GaAs substrate can generally be cited as a substrate. Lattice constants of AlGaAs, GaP and GaAs are generally equal to each other, and light emitting diodes and semiconductor lasers and the like using these materials are already reduced into practice. Devices using ZnSe, however, have not yet been employed practically. This is because a proper doping of ZnSe is hard to perform and because the growth temperature of ZnSe is quite different from that of GaAs layers. In general, an optimum growth condition of ZnSe resides in a range between 250 °C and 350°C while that of GaAs is in a range higher than 500°C. Therefore, it has been usual in conventional growth examples to fabricate ZnSe on the GaAs substrate at temperatures from 250 °C to 350 °C. If a GaAs layer were grown on a ZnSe layer, inter-diffusions of Ga, As, Zn and Se occur and an n-p junction would be formed at a boundary plane between GaAs and ZnSe. Figs. 6 and 7 show such examples. In Fig. 6, an n-ZnSe layer 152 is formed on an n-GaAs substrate 151. The growth temperature therein is 300 °C. Then, as shown in Fig. 7, an n-GaAs layer 153 is grown at the growth temperature of 500°C. At this time, Zn is diffused from the ZnSe layer 152 to the GaAs layer 153. As a result, part 155 of the GaAs layer 153 becomes a p-type GaAs region. Similarly, Ga is diffused from the GaAs layer 153 to the ZnSe layer 152 and an n-type region 154 is formed in the ZnSe layer 152. Consequently, an npn junction is created between substrate 151 and GaAs layer 153. Thus, except for the junction between n-ZnSe and p-GaAs, such a device having a diode characteristic will inevitably be created since there is a great difference in growth temperature between ZnSe and GaAs. This is a great obstacle to the achievement of ZnSe devices. Further, if GaAs is grown at low temperatures, many crystalline defects would occur. In order to fabricate an efficient light emitting device, such material having a different band gap from ZnSe and at the same time having a lattice constant equal thereto is needed. As materials satisfying these conditions, GaAs and AlGaAs series are considered appropriate. Thus, a need for technique to grow GaAs and so forth on ZnSe layer is great. If such technique is established, it becomes possible to integrate light emitting devices including a ZnSe layer, GaAs devices. ZnSe devices, GaP devices and so forth on a common substrate. Further, this technique is an important technique for crystal growth of II - VI group systems whose growth temperature is generally low. However, in the above-discussed growth interruption method for achieving a flat boundary plane, it is necessary to interrupt the crystalline growth the moment III group atoms for forming one atomic layer are supplied, and if the timing of interruption is a little off, an island inevitably remains though the diameter of the island having a step difference of one atomic layer can be made larger than the radius of excitons. Further, the above-discussed MEE method for obtaining crystal having excellent crystallinity and boundary-plane flatness is not suitable for mass production since the speed of crystal growth is exceedingly slow. Furthermore, the above-discussed semiconductor layers grown at low temperatures have comparatively a lot of crystal defects, and hence are inferior to layers grown at normal or relatively high growth temperatures. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for producing compound semiconductor devices, whose crystallinity is improved, according to which high quality crystal layers can be fabricated on a substrate made up of material different therefrom, at low temperatures, so that inter-diffusions are eliminated and that stresses due to the difference in thermal expansion coefficient are suppressed. It is another object of the present invention to provide a method for producing semiconductor devices, whose crystallinity and boundary-plane flatness are improved, at low growth temperatures. The present invention is generally directed to a method of fabricating a semiconductor device which includes a step of growing compound semiconductor at a substrate temperature not greater than 500°C to form a semiconductor layer on a substrate of the devic, and a step of reducing crystal defects of the semiconductor layer attributable to the growth at the low substrate temperature not greater than 500°C. According to an aspect of the present invention, a method for producing a compound semiconductor device is characterized in that a crystal layer of the device is formed on a substrate with materials belonging to at least two different groups of the periodic table of the elements, at a crystal growth temperature not greater than or below 500 °C, and that a current is caused to flow into the thus formed crystal layer. According to the present invention, a substrate temperature at the time of growth of compound semiconductor hetero-interface is set to a value not greater than 500 °C, and the diameter of an island having a step difference of one atomic layer is reduced, so that an effectively flat boundary plane is formed for excitons in the quantum well or carriers in the vicinity of the boundary plane. More concretely, in the first step in which the substrate temperature is below 500°C and layers are formed in vacuum by a deposition method such as MBE, the growth of layers is conducted under a condition that the flux ratio of numbers of V / III group arrival molecules (a value of the number of V group arrival molecules whose vapor pressure is high divided by the number of III group arrival molecules whose vapor pressure is low) is maintained not greater than 2.5 (preferably below 2). As a result, a high quality crystal growth can be obtained (in this connection, see the copending U.S. application of the same assignee). At the time of crystal growth, the diameter of an island having a step difference of one atomic layer is reduced, and an effectively flat boundary plane can be fabricated for excitons in the quantum well or carriers in the vicinity of the boundary plane. Further, defects in the crystal are reduced by subjecting the semiconductor layer grown at low temperatures to the current flow treatment. These advantages and others will be more readily understood in connection with the following detailed description of the preferred embodiments in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view for explaining a prior art example of a semiconductor laser. Fig. 2 illustrates a graph for showing the substrate temperature dependency of threshold current density of a prior art example of a semiconductor laser. Fig. 3 illustrates a graph for showing the manner of diffusion in a prior art example of Sn-doped GaAs. Fig. 4 is a cross-sectional view for explaining a prior art example of a double-hetero junction laser using an Si substrate. Figs. 5A and 5B respectively illustrate graphs for explaining characteristics of prior art examples. Fig. 6 is a view showing a prior art growth method example in which a ZnSe layer is grown on a GaAs substrate. Fig. 7 is a view for explaining the prior art example of Fig. 6. Fig. 8 is a cross-sectional view of a semiconductor laser produced by a first embodiment of the present invention. Fig. 9 illustrates a graph for showing the change of a threshold current density with time. Figs. 10A and 10B respectively illustrate graphs for explaining ambient temperature-current change amount characteristics and current flow amount-current change amount characteristics. Fig. 11 is a cross-sectional view of a semiconductor laser produced by a second embodiment of the present invention. Fig. 12 illustrates a view for explaining a growth method of Si-doped GaAs. Fig. 13 is a cross-sectional view of a semiconductor laser produced by a sixth embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT A first embodiment will be explained. Fig. 8 shows a cross-sectional view of a single quantum well (SQW) laser fabricated by the first embodiment of a crystallinity improvement method of the present invention. As shown in Fig. 8. on an n-type GaAs substrate 51, a buffer layer 52 of Si-doped GaAs and a Si-doped Al 0.5 Ga 0.5 As layer 53 having a thickness of 1.5 µ m are formed in this order. Further, on the buffer layer 52, a lower optical confinement layer 54, an active layer 55, an upper optical confinement layer 56, Be-doped Al 0.5 Ga 0.5 As layer 57 and a cap layer 58 are formed in this order. The lower optical confinement region 54 consists of undoped Al y Ga 1-y As having a thickness of 200 nm, the Al mole fraction y is gradually changed from 0.5 to 0.3 toward the active layer 55. The active layer 55 consists of undoped GaAs having a thicknes of 7 nm, the upper optical confinement region 56 having a thickness of 200 nm consists of undoped Al z Ga 1-z As, and its Al mole fraction z gradually increases from 0.3 to 0.5, symmetrically to the lower optical confinement layer 54. The layer 57 has a thickness of 1.5 µ m, and the cap layer 58 consists of Be-doped GaAs having a thickness of 0.5 µ m. After the respective layers are grown, the substrate 51 is thinned to approx. 100 µ m, and a p-side electrode 59 of Cr/Au and an n-side electrode 60 of AuGe/Ni/Au are formed. Thus, the SQW laser having a ridge type waveguide is completed. A current is caused to flow into the thus fabricated SQW laser at an atmospheric temperature of 70 °C. Fig. 9 illustrates the change with time in the threshold current density due to that current flow treatment. In Fig. 9, the abscissa indicates a current flow treatment period and the ordinate indicates a threshold current (mA) of the SQW laser. As is shown in Fig. 9, the threshold current decreases as the current flow period increases, and there is a tendency of saturation after a predetermined time. As a result of the current flow treatment, the threshold current of SQW laser becomes two thirds, compared with the laser not subjected to the current flow treatment. According to the condition, there may be a case where the threshold of SQW laser becomes a half. When the threshold current value becomes stable and constant, the value is kept unchanged thereafter as shown in Fig. 9. The current flow treatment of SQW laser is desirably conducted under the condition that the laser is not oscillated, as far as possible. This is because there is a possibility that the end surface of the laser will be degraded by laser light if the laser oscillation should occur. Further, this is because the crystallinity improvement highly depends on the amount of current flow treatment and its ambient temperature, irrespective of light output of the laser. An example will be explained that explicates the dependency of the crystallinity improvement on the amount of current flow treatment and ambient temperature. Fig. 10A shows a relationship between the ambient temperature and the change in threshold current when the amount of supplied current of the current flow treatment is constant, and Fig. 10B shows a relationship between the amount of supplied current of the current flow treatment and the change in threshold current when the ambient temperature is constant. As is seen from Fig. 10, the decrease in threshold current grows large as the ambient temperature is raised, and the improvement speed is large as the amount of supplied current of the current flow treatment increases. When the current flow treatment is conducted at the same level, the improvement is greater and the degradation of the device's end surface is less as the ambient temperature increases under the condition that no laser oscillation is conducted. A second embodiment will be explained. Fig. 11 shows a cross-sectional view of a semiconductor laser having an active layer of multiple quantum well (MQW) structure. In Fig. 11, reference numeral 71 designates a p-type GaAs substrate having a thickness of 0.5 µ m, reference numeral 72 designates a buffer layer of Be-doped GaAs having a thickness of 0.5 µ m, reference numeral 73 designates a cladding layer of Be-doped Al 0.5 Ga 0.5 As having a thickness of 1.5 µ m, reference numeral 74 designates an optical confinement layer of Be-doped Al x Ga 1-x As having a thickness of 200nm, reference numeral 75 designates an active layer of five-layer structure of undoped GaAs and Al 0.3 Ga 0.7 As. On the active layer 75, an upper optical confinement layer 76, a Si-doped Al 0.5 Ga 0.5 As layer 77, and a cap layer 78 are layered in this order. The Al mole fraction of the optical confinement layer 74 is 0.5 at its boundary plane with the cladding layer 73, and gradually decreases to 0.3 toward its boundary plane with the active layer 75. In the active layer 75, an undoped GaAs layer is initially formed to a thickness of 6nm, an undoped Al 0.3 Ga 0.7 As is formed thereon to a thickness of 10nm, and then five-pairs of undoped GaAs layers and undoped Al 0.3 Ga 0.7 As layers are layered. Thus, the active layer 75 is fabricated. Further, in Fig. 11, reference numeral 76 designates the upper optical confinement layer 76 of Si-doped Al x Ga 1-x As having a thickness of 200nm, reference numeral 77 designates the cladding layer of Si-doped Al 0.5 Ga 0.5 As having a thickness of 1.5 µ m, and reference numeral 78 designates the cap or contact layer of Si-doped GaAs having a thickness of 0.5 µ m. The Al mole fraction of the cladding layer 77 is 0.3 at its boundary plane with the active layer 75, and gradually increases to 0.5 toward its boundary plane with the upper cladding layer 77. Further, reference numeral 79 designates an n-side electrode of AuGe/Au, and reference numeral 80 designates a p-side electrode of Cr/Au. The crystallinity of MQW laser having the above-discussed structure is effectively improved by the current flow treatment. For example, the threshold of the MQW laser is reduced to approx. two thirds by the current flow treatment that is performed for about 10 hours at the ambient temperature of 70 °C. Furthermore, the same effect is obtained in a normal double-hetero (DH) structure in which the thickness of an active layer is approx. 0.1 µ m. Thus, it has been clearly demonstrated that the crystallinity improvement of a semiconductor laser whose growth temperature is low can be achieved by the current flow treatment. Further, the crystallization improvement method can be applied to the fabrication of a low-temperature growth light emitting diode. In fields of optical communications and so forth, the integration of semiconductor devices is a key technology for achieving a high-speed communication. In the integration process of semiconductor devices, the low-temperature growth technology is important, and all processes can be conducted at low temperatures below 500°C by combining the low-temperature growth method and the crystallization improvement method of this embodiment. Further, optimum conditions make it possible to conduct all processes at low temperatures of approx. 350°C. A laser of AlGaAs series can be fabricated on a Si substrate by using the low-temperature growth technology and the crystallization improvement method with current flow treatment. An example thereof will be described hereinbelow. Fig. 12 explains a growth method in which a Si-doped GaAs layer 83 is grown on a Si substrate 82 at a substrate temperature of 350°C. The defect density of the Si-doped GaAs layer 83 is 1×10 5 cm -2 . Improvement of more than two orders can be obtained, compared with prior art, and this improvemnt is attributable to mitigation of stress due to differences in thermal expansion coefficient and so on. Fig. 13 is a cross-sectional view of a semiconductor laser of a third embodiment. The stress mitigation method is used for fabricating the semiconductor laser. The semiconductor laser structure is formed on a Si substrate, and the Al mole fraction of the cladding layer is 0.5. In Fig. 13, reference numeral 91 designates a (001) plane n-type Si substrate, reference numeral 92 designates a Si-doped GaAs layer having a thickness of 0.5 µ m, reference numeral 93 designates a Si-doped Al 0.5 Ga 0.5 As layer having a thickness of 2.0 µ m, reference numeral 94 designates an optical confinement layer of Si-doped Al x Ga 1-x As having a thickness of 50 nm ( x is changed from 0.5 to 0.3), reference numeral 95 designates an undoped GaAs active layer having a thickness of 7 nm, reference numeral 96 designates an upper optical confinement layer of Be-doped Al y Ga 1-y As having a thickness of 50 nm ( y is changed from 0.3 to 0.5), reference numeral 97 designates an upper cladding layer of Be-doped Al 0.5 Ga 0.5 As having a thickness of 1.5 µ m, reference numeral 98 designates a cap layer of Be-doped GaAs, reference numeral 99 designates a p-type electrode and a reference numeral 100 designates an n-type electrode. The MBE method is adopted as a growth method, and conditions are set so that the growth speed of GaAs layer 95 is 0.7 µ m/hour, that the substrate temperature is 350 °C and that the rotation speed of substrate 100 is 12rpm. A pressure is controlled so that flux ratios for the respective layers are maintained below 2. As a result, the threshold current density turs out to be 2kA/cm 2 . Further, when the current flow treatment is performed for approx. 10 hours at the ambient temperature of 60 °C, the threshold current is improved to be 1kA/cm 2 . Thus, even when GaAs is grown on the Si substrate, a high quality layer can be produced even at low temperatures by utilizing the current flow treatment. In such a case where the Si substrate is used, an MQW structure, and GaAs having a thickness of about 0.1 µ m and having no quantum effect, other than the above-mentioned SQW structure, may also be used as an active layer. Although the MBE method is used in the above-discussed embodiments, a layer or layers of the semiconductor device may be formed by the MEE (Migration Enhanced Epitaxy) method. In the MBE method, materials are supplied continuously, while in the MEE method, Ga, Al, As and the like are independently supplied alternately, or alternately with being each of the groups III and V as a unit. In the MEE method, the process is performed at low temperatures throughout, so that AlGaAs, GaAs and the like having a high quality (highly crystallized) can be obtained. But, since in the MEE method the materials are alternately supplied, its growth speed is slow. This drawback can be solved by combining the MEE method and the above-discussed growth method at a low flux ratio. Growth methods partially involving the MEE method will be described below. For example, in the second embodiment of Fig. 11, the lower light confinement layer 74 made of undoped Al 0.4 Ga 0.6 As, MQW layer 75 and upper light confinement layer 76 made of undoped Al 0.4 Ga 0.6 As can be grown by the MEE method. Here, Al and Ga are paired, and such pair and As are alternately applied to the substrate. The composition ratio or mole fraction is determined by respective flux amounts. In this example, the threshold current density of 1.5kA/cm 2 is obtained, and this value is improved to 800A/cm 2 by the current flow treatment. The II / VI group series materials may be used. For example, ZnSe, CdTe and the like are materials required to be grown at low temperatures, and GaAs series and AlGaAs series are degraded in crystal quality when grown at low temperatures. Those materials, however, can be improved in crystal quality by using the current flow treatment. Namely, low-temperature growth materials such as ZnSe and III / V group compound semiconductor series such as GaAs can be compounded by means of the cryastallinity improvement method using the current flow treatment. As described in the above-discussed embodiments, the substrate temperature is set below 500°C when the compound semiconductor hetero boundary plane or interface is grown, so that the diameter of an island having a step difference of one atomic layer is reduced. Therefore, an effectively flat boundary plane can be formed for excitons in quantum wells or carriers in the vicinity of the boundary planes. Further, crystal layers can be fabricated at low temperatures and the crystallinity thereof can be improved by the current flow treatment of the grown crystal layers. Therefore, all processes of the semiconductor devices can be performed at low temperatures, and the compounding with low-temperature materials such as ZnSe and CdTe and the crystal growth of strain material series such as GaAs formed on Si substrate can be achieved. Therefore, all low-temperature process of semiconductor devices can be realized, and the compounding of low-temperature materials such as ZnSe and CdTe and the AlGaAs series and the like, and a high quality crystal growth of strain material series such as GaAs formed on the Si substrate, can be achieved. Materials are not limited to the above described ones, but the principle can also be applied to materials such as InGaAsP, InAlAs and the like. While the present invention has been described with respect to what is presently considered to be the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments.

Claims: A method of fabricating a semiconductor device, said method comprising the steps of: growing compound semiconductor at a substrate temperature not greater than 500 °C by a vacuum deposition to form a semiconductor layer on a substrate of the device; and causing a current to flow into the semiconductor layer formed on the substrate in order to reduce the defect density. A method of fabricating a semiconductor device according to claim 1, wherein a semiconductor laser device is fabricated, the semiconductor laser device comprising a substrate (51; 71; 91) and a plurality of semiconductor layers including a laser active layer (55; 75; 95), and wherein the current flow treatment is conducted under the condition that the semiconductor laser device is not oscillated. A method of fabricating a semiconductor device according to claim 1 or 2, wherein the compound semiconductor contains at least III and V group elements. A method of fabricating a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer is formed under a condition under which a value of the number of incoming molecules of material of group V having a higher vapor pressure divided by the number of incoming molecules of material of group III having a lower vapor pressure is equal to 2.5 or less than 2.5. A method of fabricating a semiconductor device according to claim 3 or 4, wherein the semiconductor layer includes at least As and Ga. A method of fabricating a semiconductor device according to claim 3 or 4, wherein the semiconductor layer includes at least Al. A method of fabricating a semiconductor device according to claim 1 or 2, wherein the compound semiconductor contains at least II and VI group elements. A method of fabricating a semiconductor device according to any one of the preceding claims, wherein the current is caused to flow into the semiconductor layer at a temperature not greater than the substrate temperature. A method of fabricating a semiconductor device according to any one of the preceding claims, wherein the vacuum deposition is a molecular beam epitaxy method.

Inventors: MIYAZAWA SEIICHI, MIZUTANI NATSUHIKO, MIYAZAWA, SEIICHI, MIZUTANI, NATSUHIKO, MIYAZAWA, SEIICHI, C/O CANON KABUSHIKI KAISHA, MIZUTANI, NATSUHIKO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01S5, H01L33