Disc data reproducing apparatus and signal processing circuit

Abstract: An apparatus, a signal processing circuit and a method for reproducing data stored on a disc(1) to prevent a buffer memory(22) from going overflow/underflow. Writing information data read from the disc(1) to the buffer memory(22) is performed in synchronism with a reproduction stage clock signal(PCK), and reading from the buffer memory(22) is in synchronism with a signal processing stage clock(XCK). The signal processing stage clock(XCK) for reading information data from the buffer memory(22) is changed in accordance with the amount of information data stored in the buffer memory(22) for preventing interruptions in data reproduction.

Description: The present invention generally relates to an optical record disc player such as the compact disc player, its signal processing circuit and a method for data reproduction, and more particularly, to apparatus and method for reading out reproduced data from a buffer memory. As is well known in the field of audio equipment, digital record reproducing systems have been generally adopted for the purpose of reproducing recorded data of high density and high fidelity. In these systems, audio analog signals are converted into digitized data by a PCM(Pulse Code Modulation) technique and this data is recorded on a recording medium, such as a disc or a magnetic tape, to be reproduced. Among these systems, the compact disc is mainly used at present. In this case, a binary digit(bit) corresponding to the digitized data is formed on a disc of about 12cm in diameter, and is optically read. A reproducing device for reproducing the data recorded on the compact disc as described above, moves an optical pickup provided with a semiconductor laser and a photo-electric conversion device in a constant linear velocity tracking system(CLV) from the inner periphery side to the outer periphery side of the disc, and by rotating the compact disc the data recorded on the compact disc may be read. The data read out from the disc is supplied to an RF circuit. This RF circuit extracts a focus error signal and tracking error signal from an output of the optical pickup, and supplies a servo control circuit with these extracted signals. The RF circuit also quantizes the signal read from the disc, and supplies a signal processing circuit with the quantized signal as an eight to fourteen bit modulated(EFM) signal. This signal processing circuit operates an EFM demodulation, a subcode demodulation and an error correction processing, then its output is supplied to a D/A(digital/analog) converter(hereinafter called DAC). An output of the DAC is supplied to a low pass filter(LPF), and an output of the LPF corresponds to a reproduced audio output signal. In a reproduction device used with a CD, in order to prevent a final audio output from causing wow and flutter, the EFM demodulated signal is stored in a buffer memory and read out after the error correction processing using a stable frequency clock signal. This clock signal is generally synchronous with a clock signal generated by a crystal oscillator. Besides the well-known audio CD player, a CD-ROM player is also one of the reproducing apparatus using discs. The CD-ROM player reproduces two kinds of data co-existing on the disc, i.e. the audio signal and ROM data, such as image information and character codes. When the audio signal is read out, the reproduction is performed by a normal rate corresponding to audible information. On the other hand, when ROM data is read out, the reproduction is performed at a faster rate, such as a double rate. In such a CD-ROM player, frequent switching from the normal rate to the double rate or from the double rate to the normal rate are essential. As shown in FIG.1, to change the reproduction rate, a rate control signal(HS) is used. When the signal HS is changed from "L" to "H", the rate is switched from the normal rate to the double rate, and when the signal HS is changed from "H" to "L", the rate is switched from the double rate to the normal rate. In such cases, the rotation speed of a disc motor does not change promptly but changes gradually from the normal rate to the double rate or from the double rate to the normal rate. As a result, the frequency of the reproduction stage clock signal(PCK), which is generated by a PLL circuit in accordance with the rotation speed of the disc motor, flutters frequently like the motor rotation. On the other hand, a signal processing stage clock signal(XCK) for the error correction processing and the audio output processing is switched promptly. As a result, within a transitional period of the disc motor until the rotation speed reaches the required speed, the frequency difference between the reproduction stage clock signal(PCK) and the signal processing stage clock signal(XCK) is relatively large. In the buffer memory, storing (writing) is performed by a reproduction stage frame clock signal(PFS) synchronous with the signal PCK, and reading is performed by a signal processing stage frame clock signal(XFS) synchronous with the signal XCK. For this reason, the address difference between storing and reading caused by the frequency difference exceeds an allowed value for the buffer memory. This means an overflow or underflow i.e., emptying, which results in an interruption in the reproduction. The problem mentioned above is not limited to the CD-ROM player. For example, the problem also exists for a CD player which comprises a shock proof memory to eliminate effects of the data pick-up interruption caused by a shock from outside. The shock proof memory, usually a large capacity memory such as 4MB DRAM(four megabit dynamic random access memory), is employed between the buffer memory and the DAC to store the reproduced output of the buffer memory. The reproduced output is stored in the shock proof memory, then read out. In this system, storing in the shock proof memory is controlled to keep a predetermined data quantity in the shock proof memory in the following manner. When storing is interrupted by a shock from outside, the reproduced data in the shock proof memory is reduced because reading-out continues. If the quantity reduction in the shock proof memory is detected, then in order to recover the predetermined quantity in the shock proof memory, a reading rate from the buffer memory is switched to the faster rate. In this case, because the rotation speed of the disc motor changes gradually, the difference between the reproduction stage clock and the signal processing stage clock is increased. As a result, an underflow occurs in the buffer memory, which produces an interruption in the reproduction. As described above, in systems such as the shock proof memory and CD-ROM in which the reproduction rate is switched, the reproduction can be interrupted because of overflow or underflow. Sudden speed change also occurs, by a search operation, in a conventional CD player which does not employ the reproduction rate switching. The disc rotates at about 8Hz when the pickup is at the inner periphery side of the disc, and 3Hz when the pickup is at the outer periphery side so as to maintain a constant linear velocity. For this reason, in order to switch so as to track the data in the outer periphery side when the pickup has been tracking the inner periphery side, the rotation speed of the disc motor should be reduced to below one-half. In the opposite case, when the pickup has been at the outer periphery side, the speed should be increased to two times greater to track the data in the inner periphery side. The frequencies of the signals PCK and PFS obtained by supplying the RF circuit and the PLL circuit with the signal from the pickup, is synchronous with the disc rotation rate. For this reason, at the moment when the pickup moves to a target point, for example from the inner periphery side to the outer periphery side, the frequencies of the signals PCK and PFS are higher than their predetermined value for the target point until the disc motor decreases its speed to the predetermined speed. When the pickup moves from the outer periphery side to the inner periphery side, the frequencies of the signals PCK and PFS are lower than their predetermined value for the target point. These cases can result in underflow or overflow, by the frequency difference between the signals PFS and XFS, which results in interruption in the reproduction. Particularly, in the system in which high-speed access is required, a long muting period until the reproduction is restarted is one of the serious problems. Although the use of high-controllability motors which have a shortened transitional period can be effective to solve the above problems these motors are expensive and result in an increased price of the CD player set. Accordingly, the present invention seeks to provide an improved disc player wherein reproduction interruptions, or muting caused by the reproduction speed switching are reduced. The present invention further seeks to provide an improved signal processing circuit and a reproduction method for reducing interruptions of the reproduction caused by the reproduction speed switching. A signal processing circuit and a method according to the preamble of claims 1 and 10 are known from JP-A-0 400 1972. According to a first aspect of the present invention there is provided a signal processing circuit for use in processing data read from a disc comprising: means for generating a first clock signal synchronous with the data; memory means for storing data; means for generating a second clock signal; and means for controlling a writing operation to the memory means in synchronism with the first clock signal and for controlling a reading operation from the memory means in synchronism with the second clock signal, characterised in that the means for generating a second clock signal comprises means for generating a plurality of clock signals having different predetermined frequencies from a constant clock signal, and means for selecting as the second clock signal one of the plurality of different clock signals, the second clock signal being selected during a predetermined interval following a command for changing the speed of rotation of the disc in accordance with the activated speed of rotation, and with the amount of data stored in the memory means. According to a second aspect of the present invention there is provided a method for reproducing data stored on a disc comprising: reading out data from a rotating disc on which the data is stored; generating a first clock signal synchronous with the digitized signal; generating a second clock signal; storing the data in synchronism with the first clock signal to a memory; reading the data stored in the memory means in synchronism with the second clock signal; and characterised in that the step of generating a second clock signal includes the steps of deriving a plurality of clock frequencies having different predetermined frequencies from a constant clock frequency, the second clock signal being selected from the plurality of clock frequencies during a predetermined interval following a command for changing the speed of rotation of the disc in accordance with an amount of data stored in the memory and in accordance and with the activited speed of rotation of the disc. For a better understanding of the present invention, and to show how it may be brought into effect, reference will now be made, by way of example, to the accompanying drawings, in which: FIG.1 is a timing chart showing the relationship between the reproduction stage frame clock signal(PFS) and the signal processing stage frame clock signal(XFS) according to a known system; FIG.2 is a block diagram of a disc data reproducing apparatus according to the present invention; Fig.3 is a block diagram of part of the reproducing apparatus of Figure 2; Fig.4 is a block diagram of a clock generating circuit of part of the reproducing apparatus of Figure 2; Fig.5 is a chart representing the relationship between control signals and the output of a selector according to the present invention; Fig.6 is a timing chart representing the relationship between the reproduction stage frame clock signal(PFS) and the signal processing stage frame clock signal(XFS) according to the present invention; Fig.7 is a block diagram of a signal processing circuit of another aspect according to the present invention; Fig.8 is a block diagram of a clock generating circuit of a second aspect according to the present invention; Fig.9 is a timing chart representing the relationship between rate control signal(HS) and activating signal(E/D); and Fig.10 is a block diagram of a clock generating circuit of a third aspect according to the present invention. Preferred embodiments of the present invention will be described in detail with reference to Figures 2-10 of the drawings. Referring now to Figures 2-5, an embodiment of the disc data reproducing apparatus for reducing reproduction interruptions will be described in detail. In Figure 2, a disc 1 such as the CD(compact disc) is rotated by a disc motor 2. Recorded data on the disc 1 is read by an optical pickup 3, and the data read out is supplied to an EFM signal generation circuit(hereinafter called RF circuit) 4. The RF circuit 4 extracts a focus error signal and a tracking error signal from an output of the optical pickup 3, and supplies these extracted signals to a servo control circuit 5. Further, the RF circuit 4 quantizes the signal read from the disc 1 and supplies a PLL circuit 6 with the quantized signal as the EFM signal. The PLL circuit 6 generates a reproducing stage clock signal(PCK) synchronous with the EFM signal for demodulating the EFM signal in the following signal processing circuit 7. The PLL circuit 6 supplies the signal processing circuit 7 with the signal PCK and the EFM signal. The servo control circuit 5 comprises a focus servo control circuit, a tracking servo circuit, a spindle servo control circuit and a sled servo control circuit. The focus servo control circuit controls an optical focus of the pickup 3 to make the focus error signal equal to zero. The tracking servo control circuit controls an optical tracking of the pickup 3 to make the tracking error signal equal to zero. The spindle servo control circuit controls a disc motor 2, such as a spindle motor, which drives the disc 1 at a predetermined speed. The sled servo control circuit, moves the pick up 3 to a target track point designated by a system controller 8. (These detailed components of the servo control circuit are not shown in the drawings.) The signal processing circuit 7 performs an EFM demodulation, a subcode demodulation and an error correction processing. The output of circuit 7 is supplied to a digital/analog converter(hereinafter called DAC) 9. An output of the DAC 9 is supplied to a low pass filter(LPF) 10, and an output of the LPF 10 corresponds to a reproduced audio output signal. The system controller 8 supplies a clock generating circuit 11 with rate control signals including rate control signal(HS) and clock switching signal(SW). The system controller 8 also supplies the signal processing circuit 7 and the servo control circuit 5 with many other control signals for play, stop, search. attenuating, etc. The system controller 8 generates the signal HS and the signal SW on the basis of control signals from a processor 12, which controls the whole system of the CD player. Information about the contents of the disc is obtained by reading TOC(Table of Contents) data on the disc. From TOC data, respective positions of the audio data and ROM data(such as image data and character codes) are obtained. The processor 12 controls the system controller 8 to generate the signal HS and the signal SW in accordance with the required(designated) data. When the designated data is the audio data, the signal SW of "L" level is generated to prevent the signal processing stage clock signal from being switched. On the other hand, when the designated signal is the ROM data, the signal SW of "H" level is generated. The signal processing circuit 7 will be described in detail with reference to Figure 3. The signal processing circuit 7 of this embodiment comprises an EFM demodulating circuit 21, a buffer memory 22, an error correction circuit 23, a subcode demodulating circuit 24, an output circuit 25 and a memory control circuit 26. The EFM demodulating circuit 21 receives the reproducing stage clock signal(PCK) which is generated by the PLL circuit 6 and is synchronous with the EFM signal. After extracting a synchronous signal, the EFM signal is demodulated and stored into the buffer memory 22 as 33-symbol data, per one frame, which consists of 1-symbol subcode data and 32-symbol main data including parity data. The buffer memory 22 is used for jitter absorption and an interleaving in the error correction process. The jitter on the time axis is absorbed, or eliminated by writing the EFM demodulated signal to the buffer memory 22 in synchronism with the reproduction stage clock signal and by reading in synchronism with the signal processing stage clock signal which is generated from an accurate clock such as a crystal-oscillator clock. An output of the buffer memory 22 is supplied to the error correction circuit 23, in which C1 and C2 system error correction are performed. The error corrected data is again stored to the buffer memory 22. Subsequently, the error corrected data is read from the buffer memory 22, and supplied to the output circuit 25. The output circuit 25 outputs reproduced data(DATA) after, if uncorrectable data exists, mean value interpolation and mute functions are performed. The subcode demodulating circuit 24 reads out subcode data from the buffer memory 22, performs an error check of Q data(one component of the subcode), and outputs the result(SUBQ) to the system controller 8. The memory control circuit 26 outputs an address signal, a chip enable signal(CE) and a read/write signal(R/W) to the buffer memory 22. In this case, the address to be supplied to the buffer memory 22 is classified into one of the following four kinds. These addresses are a Wr address for writing the demodulated EFM data in the buffer memory 22, a C1 address for reading C1 system data to detect an error of C1 system from the data written in the buffer memory 22 and for writing in and reading from the buffer memory 22 to correct the detected erroneous data, a C2 address for reading C2 system data to detect an error of C2 system from the data written in the buffer memory 22 and for writing in and reading from the buffer memory 22 to correct the detected erroneous data, and an Re address for reading the data from the buffer memory 22 to output to the DAC 9. The memory control circuit 26 has an address circuit(not shown in the drawings) including counters. One of the counters counts up the reproducing stage frame clock(PFS) generated on the basis of the frame synchronizing signal of the EFM data read from the disc 1, and generates the frame address of Wr. As a result, jitter occurs during the writing-in processing of the demodulated EFM data into the buffer memory. Other counters count the signal processing stage frame clock signal(XFS), and generate the frame address of C1, C2, and Re. As described above, while writing of the demodulated EFM data is performed using Wr address in synchronism with the signal PFS, the reading is performed using the Re address in synchronism with the signal XFS. Therefore, jitter is absorbed. In FIG.3, while detailed circuit configuration on a semiconductor chip is not shown, all elements of the signal processing circuit 7 may be formed on one semiconductor chip. Figure 4 is a block diagram showing the clock generating circuit 11 in detail. When a sampling frequency is 44.1kHz, the frequency of 22.5972MHz clock(512fs) generated by a crystal oscillator(X'tal) is used. Through a divide-by-2 circuit 31, a 512fs clock is supplied to a divide-by-2 circuit 32, a divide-by-4 circuit 33 and a divide-by-8 circuit 34. Outputs of each dividing circuits, i.e., a 256fs clock, a 128fs clock, a 64fs clock and a 32fs clock are supplied to A-input, B-input, C-input and D-input of a selector 35, respectively. In accordance with a control signal from a decoder circuit 36, the selector 35 outputs one of the inputs as a signal 2BCK. A bit clock signal(BCK) is obtained by supplying a divide-by-2 circuit 37 with the signal 2BCK. Furthermore, the signal BCK is supplied to a divide-by-6 circuit 38, through a divide-by-32 circuit 39, to obtain a channel clock LRCK and the signal processing stage frame clock XFS. LRCK and XFS have values of 44.1kHz and 7.35kHz, respectively, as the normal reproducing rate, when selector 35 selects the C-input. The signal XFS is supplied to an X-counter circuit 40. The signal PFS generated by the PLL circuit 6 is supplied to a P-Counter circuit 41. Outputs of each of the counter circuits 40 and 41 are received by a [P-X] calculating (subtraction) circuit 42. The output of the P-counter 41 may be used as the writing frame address to the buffer memory 22, and the output of the X-counter may be used as the reading-out frame address for the buffer memory 22. For example, if a required jitter absorption ability of the buffer memory 22 is ± 6 frames, then the writing frame address(P-counter value) is greater than the reading-out frame address(X-counter value) by 7 frames. Each counter counts up one unit for every one frame. The [P-X] calculating circuit 42 subtracts the value of the X-counter 40 from the value of the P-counter 41. On one hand, when the rotation speed of the disc motor 2 is slower than its required speed, the P-counter 41 counts up slower than the X-counter 40, and the value [P-X] reduces. On the other hand, when the rotation speed of the disc motor 2 is faster than its required speed, the P-counter 41 counts up faster than the X-counter 40, and the value [P-X] is increased. In the former case, for example [P-X] is smaller than four frames, the [P-X] calculating circuit 42 supplies the decoder 36 with a signal UNDER. In the latter case, for example [P-X] is greater than 12, the circuit 42 supplies the decoder 36 with a signal OVER. The decoder circuit 36 receives signals UNDER and OVER from the [P-X] calculating circuit 42, and receives the reproducing rate control signal(HS) and the clock switching signal(SW) from the system controller 8. In FIG.5, the relationship between these signals and the output of the selector 35 is shown. When the signal SW is "H"(high level), the signal processing stage clock(XCK) is switched in accordance with both the value [P-X] and the signal HS. When the signal SW is "L"(low level), the signal XCK is switched only by the signal HS. The signal HS represents the reproduction rate, "H"(high level) corresponds the double rate reproduction and "L"(low level) corresponds the-normal rate. "X" in signals UNDER or OVER means "don't care". Next, referring to Figure 6, the operation when the signal SW represents "H" is explained in detail. At the timing 1, the signal HS is switched from "L" to "H", the signal XFS changes from the normal rate to the double rate promptly. The signal PFS changes from the normal to the double gradually. At the timing 2, reduction in the value [P-X] occurs, the signal UNDER changes from "L" to "H", and the signal XFS changes from the double to the normal. At the timing 3, the signal UNDER changes from "H" to "L", and the signal XFS changes to the double again. At the timings 4 and 5, the operation is the same as at timings 2 and 3, respectively. At the timing 6, the rotation speed of the disc motor 2 goes over the required speed for the double rate temporarily, and the signal PFS also goes over the required frequency for the double rate. As a result, the value [P-X] increases, the signal OVER changes to "H", and the signal XFS changes from the double rate to quadruple rate. At the timing 7, the signal OVER changes to "L", and the signal XFS changes to the double. During the timings 7-8, the disc motor 2 rotates steadily at the double rate. At the timing 8, the signal HS is switched from "H" to "L". By this switching, the signal XFS changes from the double to the normal, and PFS changes gradually. At the timing 9, an increase in the value [P-X] occurs, the signal OVER changes from "L" to "H", and the signal XFS changes from the normal to the double. At the timing 10, the signal OVER changes from "H" to "L". and the signal XFS changes to the normal again. At the timings 11 and 12, the operation is the same as at timings 9 and 10, respectively. At the timing 13, the rotation speed of the disc motor 2 goes under required speed for the normal rate, and the signal PFS also goes under the required frequency for the normal rate. As a result, the value [P-X] decreases, the signal UNDER changes to "H", and the signal XFS changes from the normal rate to the half rate. At the timing 14, the signal UNDER changes to "L" and the signal XFS changes to the normal rate. As described above, by changing the speed of reading-out from the buffer memory 22 in accordance with the rotation speed of the disc motor, the underflow and the overflow are prevented. Therefore, according to this embodiment of the present invention, the interruption of the data reproduction is reduced, and the reproduction data is available before the disc motor achieves the required speed. Thus the present invention is effective for a reproduction system, such as the shock proof system and CD-ROM system, in which the reproduction rate is switched. In the embodiment described above, the present invention is applied to the data reproduction apparatus with the signal processing circuit shown in FIG.3. In this data reproduction apparatus, the subcode data is synchronized with the signal processing stage clock, so that the subcode data is always synchronous with the reproduction data. Storing and reading out the demodulated EFM data to/from the buffer memory in units of single subcode blocks, the reproduction data is obtained continuously. Now, another embodiment of the present invention will be described. The present invention as applied to data reproduction apparatus can be practiced with a signal processing circuit shown in FIG.7. In the signal processing circuit shown in FIG.7, the reproduction stage clock signal(PCK), which is synchronous with the EFM signal and is for demodulating the EFM signal, is generated by the PLL circuit 6. The reproduction stage clock signal(PCK) is supplied to the EFM demodulating circuit 21 and the subcode demodulating circuit 24. The subcode data in the demodulated EFM signal-is provided to the subcode demodulating circuit 24, the subcode is demodulated and is output as SUBQ to the system controller 8. Because the reproduction stage clock is supplied to the subcode demodulating circuit 24, the demodulated subcode data (SUBQ) is output in synchronism with the reproduction stage clock. For this reason, the jitter, or difference, between the demodulated subcode data(SUBQ) and the reproduction data synchronous with the signal processing stage clock(XCK) is generated. In this manner, the present invention can be applied to this type of signal processing circuit shown in FIG.7. As shown in FIG.7, the signal processing circuit 7 may be formed on one semiconductor chip with the PLL circuit 6. The clock generating circuit 11, the servo control circuit 5 and system controller 8 also may be formed on the same semiconductor chip. In FIG.7, the memory control circuit 26 (Fig.3) is not shown, but may be formed on the same semiconductor chip. Next, referring FIGS. 8 and 9, a clock generating circuit for low power consumption will be described. In the clock generating circuit 11 shown in FIG.4, dividing circuits are always operating for supplying divided clock signals after the reproduction rate switching. However, when the disc motor is in the stable operation, changing the signal processing stage clock. or changing reading-out clock for buffer memory is not needed. Thus, by activating the dividing circuit only after the reproduction rate control signal(HS) is changed, a circuit with low power consumption is provided. As shown in FIG.8, each dividing circuit 32-34 has a control input, or an activating input, and an activating signal(E/D1-3; E for enable and D for disable) is supplied to this input, respectively. When the activating signal represents "enable", a source voltage is supplied to the dividing circuit corresponding to the activating signal so as to make the corresponding circuit operate. Such activating signals(E/D1-3) are generated by a decoder 36'. The decoder 36' is usually generating "L"(low level) signal representing "disable", but by detecting edge(rising edge/falling edge) of the provided reproduction rate control signal(HS), generates an "H"(high level) signal representing "enable" during the predetermined period(Δ t1, Δ t2) (Figure 9). This relationship between the signal HS and E/D is shown in FIG.9. The predetermined period(Δ t1, Δ t2) is, for example, determined in accordance with the transitional period which depends on operation of the disc motor 2. The transition period Δ t1 and Δ t2 may have different values, if the transitional period changing from the normal rate to the double and the transitional period in changing from the double to the normal is different. As described above, by changing each activating signal in accordance with outputs of the decoder 36', only the required divided clock signal is obtained. In this case, to obtain a stable divided clock, activating a dividing circuit before its divided clock is required, is effective. To implement this technique, a required divided clock is predicted by using the differential value of [P-X](i.e., [P-X]'). In FIG.10, a clock generating circuit which includes the dividing circuit using a prediction technique is shown. The same elements as shown in FIG.4 are numbered by the same numbers. The [P-X] calculating circuit supplies a prediction circuit 52 with the value [P-X]. This prediction circuit 52 includes a [P-X]' calculating circuit (not shown) and predicts a dividing circuit which will be required for the next timing. A dividing circuits control means 51 is supplied with the prediction result and the output of the decoder 36. Then, the dividing circuits control means 51 outputs activating signals(E/D1-3) to the dividing circuits(32-34) for activating the dividing circuit which is required at present and for activating the dividing circuit which will be required next. While, in the clock generating circuits shown in FIG.4 and FIG.10, the number of dividing circuits controlled by the activating signals is three, but the number of the dividing circuits may be increased to reduce the capacity of the buffer memory by strict clock control. As described above, according to the present invention, the reading-out clock for the buffer memory 22 is changed in the transition period caused by the reproduction rate switching and large movement of the pickup. Thus, the overflow and underflow do not occur, any interruption of the data reproduction is very short, and the reproduction data is available before the disc motor reaches the required speed.

Claims: A signal processing circuit for use in processing data read from a disc comprising: means (6) for generating a first clock signal synchronous with the data; memory means (22) for storing data; means (11) for generating a second clock signal; and means (26) for controlling a writing operation to the memory means (22) in synchronism with the first clock signal and for controlling a reading operation from the memory means (22) in synchronism with the second clock signal, characterised in that the means (11) for generating a second clock signal comprises means for generating a plurality of clock signals having different predetermined frequencies from a constant clock signal, and means for selecting as the second clock signal one of the plurality of different clock signals, the second clock signal being selected during a predetermined interval following a command for changing the speed of rotation of the disc in accordance with the activated speed of rotation of the disc, and with the amount of data stored in the memory means (22). The signal processing circuit according to claim 1 wherein the amount of data stored in the memory means (22) is represented by a difference between the current read and write addresses of the memory means (22). The signal processing circuit according to claim 2 wherein the second clock signal generating means (11) includes: first counting means (41) for counting frames in the first clock signal as a first result; second counting means (40) for counting frames in the second clock signal as a second result; and means (42) for calculating a difference between the first and second results wherein the frequency of the second clock signal is controlled in accordance with said difference. A signal processing circuit according to claim 3 wherein the second clock generating means (11) further includes: a plurality of clock generating means (32,33,34) for generating a plurality of clock signals of different frequencies; and selecting means (35) for selecting a clock signal from the plurality of clock signals according to said difference. The signal processing circuit according to claim 4 wherein each clock generating means (32,33,34) among the plurality of clock generating means (32,33,34) is activated by a different activating signal. The signal processing circuit according to claim 5 wherein the second clock signal generating means further includes activating means (51) for supplying said activating signals wherein said activating means activates the presently required clock generating means. The signal processing circuit according to claim 6 wherein the second clock signal generating means further includes a prediction circuit (52) for predicting on the basis of the difference between the first and second results which clock signal will be required next, wherein the activating means (51) supplies an activating signal to the next required clock generating means as well as to the presently req ired clock generating means. The signal processing circuit according to claim 5 further comprising switching means (8) for changing the speed of rotation of the disc motor according to a supplied control signal wherein the different activating signals are changed by detecting edges of the control signal. An apparatus for reproducing data stored on a disc comprising: means for reading out data from a rotating disc; means for generating a digitised signal by quantising the read data; means for demodulating the data; and the signal processing circuit as claimed in any preceding claims for processing the demodulated data. A method for reproducing data stored on a disc comprising: reading out data from a rotating disc on which the data is stored; generating a first clock signal synchronous with the digitized signal; generating a second clock signal; storing the data in synchronism with the first clock signal to a memory; reading the data stored in the memory means in synchronism with the second clock signal; and characterised in that the step of generating a second clock signal includes the steps of deriving a plurality of clock frequencies having different predetermined frequencies from a constant clock frequency, the second clock signal being selected from the plurality of clock frequencies during a predetermined interval following a command for changing the speed of rotation of the disc in accordance with an amount of data stored in the memory and in accordance with the activated speed of rotation of the disc.

Inventors: INAGAWA JUN, KODAMA KUNIHIKO, NAGUMO MASAHIDE, INAGAWA, JUN, KODAMA, KUNIHIKO, NAGUMO, MASAHIDE, INAGAWA, JUN, C/O INTELLECTUAL PROPERTY DIVISION, KODAMA, KUNIHIKO, C/O INTELLECTUAL PROPERTY DIV., NAGUMO, MASAHIDE, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA AVE KK, TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA, TOSHIBA AVE CO., LTD
Application year: 1993
Main classification: G11B20
IPC codes: H01L27, G11B20, G11B7, G11B19, G06F5