Method of producing a field effect transistor

Abstract: A method of producing a field effect transistor includes depositing a first insulating film (5) and a refractory metal film (6) on a semiconductor epitaxial substrate, forming a first aperture (5a) penetrating the first insulating film (5) and the refractory metal film (6), which aperture provides a gate electrode production region, forming a second insulating film (8) on the refractory metal film (6), etching the second insulating film (8) in a direction perpendicular to the surface of the substrate leaving portions on opposite side walls of the first aperture (5a) to form a second aperture (8a), which second aperture provides a gate length, depositing a gate metal (13) on the whole surface of the substrate, and patterning the gate metal layer, the first insulating film, and the refractory metal film in a prescribed width to form a T-shaped gate structure (15). During etching the second insulating film (8), since the refractory metal film (6) serves as an etching stopper layer, the first insulating film (5) is not etched and its thickness remains as it is deposited. Therefore, the space between the over-hanging portion (15b) of the T-shaped gate electrode (15) and the source electrode (13a) increases with a reduction in the gate-to-source capacitance.

Description: The present invention relates to a method of producing a field effect transistor having a T-shaped gate electrode. Figures 4(a) to 4(k) are cross-sectional views illustrating process steps in a method for fabricating a prior art HEMT (High Electron Mobility Transistor) disclosed in, for example, Japanese Published Patent Application No. 63-174374 and Electronics Letters 24, 1988, p. 1327. Initially, a GaAs buffer layer 21, an intrinsic type (hereinafter referred to as i type) GaAs layer 22, an n type AlGaAs layer 23, and an n + type GaAs layer 24 are successively grown on a semi-insulating GaAs substrate (not shown) by epitaxial growth. Then, an SiO 2 film is deposited on the substrate to a thickness of about 3000 Å (1Å≡0.1 nm), forming a first insulating film 25. Then, a resist pattern 27 having an aperture of 0.5 µm (micron) width is formed on the first insulating film 25 (figure 4(a)). Then, as illustrated in figure 4(b), the first insulating film 25 is etched using the first resist pattern 27 as a mask to form a first aperture 25a. Preferably, the first insulating film 25 is etched by dry etching using a mixture gas of CHF 3 and O 2 or CF 4 and O 2 . Then, using the resist pattern 27 and the first insulating film 25 as a mask, the n + type GaAs layer 24 is etched to form a recess 24a having a depth of about 1000 angstroms. Preferably, the GaAs layer 24 is etched by reactive ion etching using CCl 2 F 2 or by wet etching using a mixture of tartaric acid and hydrogen peroxide solution as an etchant (figure 4(c)). In figure 4(c), although the n + type GaAs layer 24 is etched to expose the surface of the n type AlGaAs layer 23, the etching may be stopped in the n + type GaAs layer 24. After removing the resist pattern 27 using O 2 ash or organic -solvent as shown in figure 4(d), an SiO 2 film is deposited on the n type AlGaAs layer 23 and the first insulating film 25 to a thickness of about 3000 angstroms, forming a second insulating film 28 (figure 4(e)). Preferably, the SiO 2 film is deposited by plasma CVD. Then, as illustrated in figure 4(f), the second insulating film 28 is etched in the perpendicular direction to the surface of the substrate by sputter etching or reactive ion etching, leaving portions at opposite sides of the first aperture 25a to form a second aperture 28a. A width w 1 of the n type AlGaAs layer 23 exposed at the bottom of the second aperture 28a is about 0.25 micron. Then, as illustrated in figure 4(g), a refractory metallic material 29, such as WSi, is deposited on the substrate to a thickness of 1500 angstroms by sputtering, followed by annealing. Then, a low resistance metal layer 30 comprising Ti 500 angstroms thick, Pt 1000 angstroms thick, and Au 3000 angstroms thick is formed on the refractory metallic layer 29 by sputtering. Then, a resist pattern 31 is formed on the low resistance metal layer 30. Using the resist pattern 31 as a mask, the low resistance metal layer 30 comprising Ti/Pt/Au is patterned by ion milling, and the refractory metallic layer 29 comprising WSi and the insulating film 25 comprising SiO 2 are patterned by reactive ion etching (figure 4(h)). During the etching process, the refractory metallic layer 29 and the insulating film 25 are excessively etched, so that the width of the refractory metallic layer 29 is narrower than the width of the low resistance metal layer 30. Figure 4(i) illustrates a case where the etching rate of the reactive ion etching is further increased. In this case, the width of the refractory metallic layer 29 is further decreased and the insulating film 25 is completely removed. After removing the resist pattern 31 as shown in figure 4(j), a resist pattern for forming ohmic electrodes (not shown) is formed on the substrate, followed by a deposition of an ohmic electrode metal 32 comprising AuGe/Ni/Au and lift-off, resulting in a T-shaped gate electrode 33 and ohmic electrodes, i.e., source and drain electrodes 32a and 32B. Thereafter, the substrate is annealed at 400°C for two minutes to complete the HEMT of figure 4(k). Since the insulating film 25 comprising SiO 2 lying under the refractory metallic layer 29 is completely removed in the step of figure 4(i), the gate-to-source capacitance (Cgs) is reduced. The insulating film 28 remaining on opposite sides of the lower part of the T-shaped gate electrode 33 protects the surface of the n type AlGaAs layer 23. A process similar to that just described, but using a lift-off technique for the gate electrode definition, is described by U.K. Mishra et al., in IEEE International Electron Devices Meeting, Technical Digest (1989), pages 101-104. After gate recess etching and evaporation and lift-off of a gate electrode metal, a SiO 2 sidewall is formed by depositing the oxide using PECVD and subsequent reactive ion etching iN a SF 6 plasma. Next the source and drain ohmic metals are evaporated, alloyed and an overlay metal is evaporated and lifted off. In the conventional HEMT, a crystal region in which electrons travel, i.e., a region of the i type GaAs layer 22 where a two-dimensional electron gas is formed, is spaced apart from a crystal region that supplies electrons, i.e., the n type AlGaAs layer 23, by the heterojunction to prevent the electrons from being scattered by donor impurities, whereby the electron mobility of the transistor is increased. In the HEMT, in order to increase the cut-off frequency (f t ), the maximum oscillation frequency (f max ), and the unilateral gain (U) and reduce the noise factor (F o ), it is necessary reduce the gate length (Lg), the source resistance (Rs), the gate-to-source capacitance (Cgs), and the gate resistance (Rg). In the conventional method for producing the HEMT illustrated in figures 4(a)-4(k), since the gate electrode and the source and drain electrodes are formed self-alignedly, it is possible to reduce the gate length and the source resistance. In addition, since the gate electrode is formed in a T shape, the gate resistance is reduced to some extent. In the steps of figures 4(e) and 4(f), the second insulating film 28 is deposited on the substrate to fill the first aperture 25a and then etched away leaving portions on opposite side walls of the aperture 25a, which portions form a second aperture 28a having a width w 1 of 0.25 micron that would be a gate length. Thereafter, a refractory metallic material 29 is-deposited in the aperture 28a to form the lower part of the gate electrode. However, during etching the second insulating film 28, the first insulating film 25 is also etched and the thickness thereof is reduced, whereby, in the structure of figure 4(k), the interval between the over-hanging part 33a of the T-shaped gate electrode 33 and the surface of the n + type GaAs layer 24 whereon the source and drain electrodes 32a and 33b are present is reduced, resulting in an increase in the gate-to-source capacitance. Although it is thought that the above-described problem can be solved by increasing the thickness of the first insulating film 25, if the thickness of the first insulating film 25 increases, the etching precision when the aperture 25a is formed in the first insulating film 25 is reduced, and the aperture 25a is not completely filled with the second insulating film 28 when the insulating film 28 is deposited on the substrate. In this case, it is difficult to form the fine aperture 28a having a width w 1 of about 0.25 micron with high controllability. In the step of figure 4(f), the width w 1 of the aperture 28a at the n type AlGaAs layer 23 varies according to the thickness of the second insulating film 28 deposited in the step of figure 4(e). More specifically, the width w 1 decreases with an increase in the thickness of the second insulating film 28. When the second insulating film 28 is deposited to 3000 angstroms as described above, the width w 1 is about 0.25 micron. If the thickness of the second insulating film 28 is further increased to further reduce the gate length, the width of the V-shaped aperture 28a decreases. When the refractory metallic material 29 is deposited in the narrow V-shaped aperture 28a, the angle of the V-shaped groove 29a formed opposite the V-shaped aperture 28a gradually decreases and the refractory metallic material 29 is not evenly deposited on the surface of the groove 29a. As a result, a cavity 30a is formed in the low resistance metal layer 30 deposited on the refractory metallic layer 29, which cavity increases the gate resistance. Meanwhile, Japanese Published Patent Application No. 63-204772 proposes an improved method of forming a T-shaped gate structure, in which an upper metal layer of the T-shaped gate electrode is formed by a plating method using a lower metal layer of the gate electrode as a feeding electrode. In this plating method, however, it is difficult to apply ions onto the uneven surface, such as the surface with the V-shaped groove 29a, with keeping the ion concentration constant, so that it is impossible to grow the upper metal layer with no cavity. A modification of the aforesaid process has now been considered with the aim of reducing gate-to-source capacitance. In the process according to this invention, which is defined in claim 1 attached, an etching stopper film is deposited, on the insulating film covering the substrate, prior to resist pattern definition and gate recess etching. It is effective to prevent the etching of the insulating film during the formation of sidewall insulation in the recess. Since, in this case, the insulating film is not etched during the sidewall formation, the thickness of this film is as deposited. The vertical distance between the overhanging portion of the T-shaped gate electrode and the source (drain) electrode is thus minimal and the cause of increased gate-to-source (drain) capacitance, i.e. insulator film erosion, has been eliminated. Since in this process, as in the conventional process, a sidewall insulation is formed in the recess, a small geometry gate length e.g. 0.5 µm or less can be achieved, if and as required. The etching stopper film may also be patterned to the prescribed width of the T-shaped gate electrode at the time of forming the T-shaped gate electrode. It may be of refractory metallic material, e.g. WSi, and incorporated thus as part of the gate electrode metallisation. Optionally, the sidewall insulation in the recess and A remainder of the insulating film beneath the overhanging portion of the T-shaped gate electrode may be removed to provide a further decrease in the gate-to-source (drain) capacitance. By using pulse plating or electroless plating techniques, instead of evaporation, it is possible to provide overlay metal on the T-shaped gate electrode without cavitation. In the accompanying drawings Figure 1 is a cross-sectional view illustrating a HEMT in accordance with a first embodiment of the present invention; Figures 2(a) to 2(1) are cross-sectional views illustrating process steps in a method of producing the HEMT of Figure 1; Figures 3(a) and 3(b) are cross-sectional views illustrating process steps in a method of producing a HEMT in accordance with a second embodiment of the present invention; Figures 4(a) to 4(k) are cross-sectional views illustrating process steps in a method of producing a HEMT according to the prior art; and Figure 5 is a cross-sectional view for explaining a problem in the method according to the prior art. Figure 1 is a cross-sectional view illustrating a HEMT in accordance with a first embodiment of the present invention. Figures 2(a) to 2(1) are cross-sectional views illustrating process steps in a method of producing the HEMT of figure 1. In figure 1, reference numeral 1 designates a GaAs buffer layer. An i type GaAs layer 2 is disposed on the buffer layer 1. An n type AlGaAs layer 3 is disposed on the GaAs layer 2, An n + type GaAs layer 4 is disposed on the AlGaAs layer 3. A recess 4a penetrates through a portion of the GaAs layer 4. A T-shaped gate electrode 15a is disposed on the n type AlGaAs layer 3 exposed at the bottom of the recess 4a. The T-shaped gate electrode 15a comprises a refractory metallic layer 9, a low resistance metal layer 10, and a metal layer 13 for ohmic electrodes. The ohmic electrodes, i.e., source and drain electrodes 13a and 13b, are disposed on the GaAs layer 4 spaced apart from each other. The whole surface of this HEMT is covered with an insulating film 12 except for the metal layer 13. Reference numeral 14 designates a feeding metal layer. A description is give of the production method. Initially, as illustrated in figure 2(a), there are successively grown on a semi-insulating GaAs substrate (not shown) by epitaxial growth, the GaAs buffer layer 1, the i type GaAs layer 2, the n type AlGaAs layer 3, and the n + type GaAs layer 4. Then, SiO 2 is deposited on the substrate to a thickness of about 3000 angstroms by plasma CVD to form a first insulating film 5. Then, WSi is deposited on the first insulating film 5 to a thickness of about 500 angstroms by sputtering to form a refractory metallic thin film 6, and a resist pattern 7 having an aperture of 0.5 micron is formed on the refractory metal thin film 6. Then, as illustrated in figure 2(b), using the resist pattern 7 as a mask, the refractory metallic thin film 6 is etched by dry etching using SF 6 and the insulating film 5 is etched by dry etching using CHF 3 , CF 4 , or the like, forming a first aperture 5a. Thereafter, using the resist pattern 7 and the first insulating film 5 as a mask, the n + GaAs layer 4 is etched by reactive ion etching using CCl 2 F 2 , Cl 2 , or SiCl 4 , or wet etching using a mixture of tartaric acid and hydrogen peroxide solution as an etchant, forming a recess 4a having a depth of about 1000 angstroms (figure 2(c)). In figure 2(c), although the n + type GaAs layer 4 is etched to expose the surface of the n type AlGaAs layer 3, the etching may be stopped in the n + type GaAs layer 4. After removing the resist pattern 7 using O 2 ash or organic solvent as shown in figure 2(d), SiO 2 is deposited over the surface of the substrate to a thickness of 3000 to 5000 angstroms by plasma CVD, forming a second insulating film 8. Then, as illustrated in figure 2(f), the second insulating film 8 is etched in the vertical direction to the surface of the substrate by sputter etching or reactive ion etching, leaving portions on the opposite side walls of the first aperture 5a. During the etching, since the refractory WSi thin film 6 serves as an etching stopper layer, the thickness of the first insulating film 5 lying under the WSi thin film 6 is not reduced. For example, while the etching rate of a mixture gas of CHF 3 and O 2 to SiO 2 is about 500 angstroms/min, the etching rate of the gas to WSi is only 100 angstroms/min. In this case, a time interval required for etching the second insulating film 8 comprising SiO 2 5000 angstroms thick is 10 min, and a time interval required for etching the WSi thin film 6 500 angstroms thick is 5 min and, therefore, the first insulating film 5 is not etched even if the second insulating film 8 is excessively etched by 50 percent. In the step of figure 2(f), the width w 2 of the second aperture 8a, which is equivalent to a gate length, varies according to the thickness of the second insulating film 8 deposited in the step of figure 2(e). For example, when the thickness of the second insulating film 8 increases from 3000 angstroms to 5000 angstroms, the width w 2 decreases from 0.25 micron to 0.15 micron. Then, as illustrated in figure 2(g), a refractory metallic material, such as WSi, is deposited on the whole surface of the substrate to a thickness of about 1500 angstroms by sputtering, resulting in a refractory metallic layer 9. Thereafter, the substrate is annealed at 400 to 500°C to remove damages on the surface of the aperture 8a due to the sputtering. Then, Au or the like is deposited on the refractory metallic layer 9 to a thickness of about 500 angstroms, forming a feeding metal layer 14 which serves as a feeding electrode when a metal layer is plated thereon. Then, Au or the like is applied onto the feeding metal layer 14 to a thickness of about 4000 angstroms by pulse plating or electroless plating, forming a low resistance metal layer 10. The pulse plating and the electroless plating employed for growing the low resistance metal layer 10 have the following advantages. When the width w 2 of the aperture 8a is narrower than 0.2 micron, the width of the V-shaped groove 9a formed on the surface of the refractory metal layer 9 during depositing the metal layer 9 by sputtering is very narrow. However, since the feeding metal layer 14 is present on the surface of the V-shaped groove 9a, when the low resistance metal layer 10 comprising Au is grown on the feeding metal layer 14, Au ions are evenly applied to the surface of the feeding metal layer 14 in the V-shaped groove 9, resulting in no cavity in the low resistance metal layer 10. Then, as illustrated in figure 2(h), a resist pattern 11 having a prescribed width is formed on the low resistance metal layer 10. Then, using the resist pattern 11 as a mask, the low resistance metal layer 10 and the feeding metal layer 14 are etched by ion milling, and the WSi refractory metallic layer 9, the WSi refractory metallic thin film 6, and the first insulating film 5 are etched by reactive ion etching. During the etching, the refractory metallic layers 9 and 6 and the insulating film 5 are excessively etched. After removing the resist pattern 11 as shown in figure 2(i), the substrate is soaked in a fluoric acid comprising HF and NH 4 F (HF:NH 4 F = 1:6) for a few minutes to completely remove the first and second insulating films 5 and 8 as shown in figure 2(j), resulting in a T-shaped gate structure 15. Then, as illustrated in figure 2(k), SiO 2 is deposited on the whole surface of the structure to a thickness of 500 angstroms or less by plasma CVD, forming a third insulating film 12. Then, using a resist pattern (not shown) as a mask, portions of the third insulating film 12 on the top of the T-shaped gate structure 15 and on regions of the n + type GaAs layer 4 where source and drain electrodes are to be disposed are removed by reactive ion etching, followed by a deposition of an ohmic electrode metal 13 and lift-off, resulting in a T-shaped gate electrode 15a and ohmic electrodes, i.e., source and drain electrodes 13a and 13b (figure 2(1)). Finally, the substrate is annealed at 400°C for a few minutes to complete the HEMT of figure 1. When the third insulating film 12 is formed in the step of figure 2(k), since the material, i.e., SiO 2 , is not sufficiently applied to the over-hanging portions 15b of the T-shaped gate structure 15, the thickness of the insulating film 12 on the over-hanging portions is very thin. While in the step of figure 2(g) the Au layer 14 is formed on the refractory metallic layer 9, a Ti refractory metal film may be formed in place of the WSi refractory metallic layer 9 and then the Au layer 14 is deposited to a thickness of 2000 angstroms. A description is given of a comparison between the gate-to-source capacitance of the HEMT of figure 1 fabricated by the process steps of figures 2(a)-2(1) according to the first embodiment and the gate-to-source capacitance of the prior art HEMT fabricated by the process steps of figures 4(a)-4(K). These two HEMTs have the same length of the over-hanging portion of the T-shaped gate structure and the same gate width. The thickness of the first insulating film 5 deposited in the step of figure 2(a) is 2000 angstroms, and the thickness of the first insulating film 25 etched in the step of figure 4(f) is 1000 angstroms. Therefore, the interval between the over-hanging portion 15b of the T-shaped gate structure 15a and the n + type GaAs layer 4 of the HEMT of figure 1 is 1000 angstroms greater than that of the prior art HEMT because the thickness of the insulating film 5 is not reduced, whereby the capacitance beneath the over-hanging portion 15b is reduced to half of that of the prior art HEMT, resulting in a reduction in the gate-to-source capacitance. In the prior art HEMT of figure 4(k), portions of the second insulating film 28 remain on opposite sides of the lower part of the T-shaped gate structure 33. In the HEMT of figure 1, however, only the insulating film 12 as thin as or thinner than 500 angstroms is present under the T-shaped gate structure 15a, so that the dielectric constant between the over-hanging portion 15b and the n + type GaAs layer 4 is reduced as compared with that of the prior art HEMT, resulting in a further reduction in the gate-to-source capacitance Cgs. As described above, according to the first embodiment of the present invention, a high-performance HEMT with short gate length, reduced gate-to-source capacitance, and reduced gate resistance is achieved. Figures 3(a) and 3(b) are cross-sectional views illustrating process steps in a method of producing a HEMT according to a second embodiment of the present invention. In the figures, the same reference numerals as in figures 2(a)-2(1) designate the same parts. After producing the semiconductor epitaxial layers 1 to 4, the first insulating film 5, the second insulating film 8, the refractory metallic layers 6 and 9, and the feeding metal layer 14 in the same manner as described with respect to figures 2(a) to 2(g), a resist pattern 16 having an aperture of prescribed width is formed on the feeding metal layer 14 and then the low resistance metal layer 10 is grown on the feeding metal layer 14 by pulse plating or electroless plating (figure 3(a)). After removing the resist pattern 16, using the low resistance metal layer 10 as a mask, the feeding metal layer 14, the refractory metallic layers 6 and 9, and the first insulating film 5 are patterned to form the T-shaped gate structure 15. Then, the first and second insulating films 5 and 8 are removed in the same manner as described in the first embodiment, followed by the deposition of the third insulating film 12 and the formation of the source and drain electrodes 13a and 13b. Also in this second embodiment, a high-performance HEMT with short gate length, reduced gate-to-source capacitance, and reduced gate resistance is achieved. While in the above-described first and second embodiments the GaAs heterojunction epitaxial substrate comprising the GaAs buffer, the i type GaAs, the n type AlGaAs, and the n + GaAs is employed, a GaAs heterojunction epitaxial substrate for a pseudomorphic HEMT including an i type InGaAs between the i type GaAs and the n type AlGaAs may be employed. Alternatively, the epitaxial substrate may comprises other semiconductor materials, such as InP. While in the above-described embodiments HEMTs are employed, the present invention may be applied to other field effect transistors.

Claims: A method of producing a field effect transistor in which a T-shaped gate electrode (15a) and source and drain electrodes (13a,13b) are self aligned on a semiconductor epitaxial substrate (1-4), which method comprises the following sequence of steps of: depositing a first insulating film (5) on said semiconductor epitaxial substrate (1-4); forming a first resist pattern (7) having an aperture pattern of prescribed width on said first insulating film (5); forming a first aperture (5a) by etching said first insulating film (5) using said first resist pattern (7) as a mask; removing said first resist pattern (7), and depositing a second insulating film (8) having a prescribed thickness on said first insulating film (5) and said semiconductor epitaxial substrate (1-4) exposed in said first aperture (5a); etching said second insulating film (8) in a direction perpendicular to the surface of said semiconductor epitaxial substrate (1-4) leaving portions (8) on opposite side walls of said first aperture (5a) to produce a second aperture (8a) in said first aperture (5a); depositing a gate electrode metallic material (9) and forming therefrom a T-shaped gate electrode (15) while removing at least that portion of said first insulating film (5) covering regions of said semiconductor epitaxial substrate where source and drain electrodes are to be formed; forming a second resist pattern on said semiconductor epitaxial substrate (1-4), said second resist pattern having apertures opposite said regions on said semiconductor epitaxial substrate (1-4) where source and drain electrodes are to be formed; and depositing an ohmic electrode metal (13) on the whole surface of said semiconductor epitaxial substrate (1-4), and removing said second resist pattern with overlying portions of said ohmic electrode metal (13) by lift-off, producing source and drain electrodes (13a,13b); characterised by: a step of depositing an etching stopper film (6) of a refractory metallic material on said first insulating film (5), which step is performed prior to the forming of said first resist pattern (7), wherein the etching stopper film (6), exposed by said first resist pattern, is removed by etching during said forming of said first aperture (5a), and the remainder of said etching stopper film (6) is effective to act as an etch stop to prevent etching of said first insulating film (5) during said etching of said second insulating film (8). A method according to claim 1, wherein said gate electrode metallic material (9) is deposited on the exposed surfaces of said semiconductor epitaxial substrate (1-4) and said etching stopper film (6) , and thereafter said gate electrode metallic material (9), said etching stopper film (6) and said first insulating film (5) are patterned in a prescribed width in forming said T-shaped gate electrode (15). A method according to claim 2 wherein steps of: depositing a first gate metal layer (14) on the whole surface of said gate electrode metallic material (9); forming a second gate metal layer (10) on the whole surface of said first gate metal layer (14) by pulse plating or electroless plating, using said first gate metal layer (14) as a feeding electrode; and patterning said first and second gate metal layers (14,10) in a prescribed width; are performed prior to the patterning of said gate electrode metallic material (9), said etching stopper film (6) and said first insulating film in forming said T-shaped gate electrode (15). A method according to claim 2 wherein steps of: depositing a first gate metal layer (14) on the whole surface of said gate electrode metallic material (9); forming a third resist pattern (16), having an aperture pattern of prescribed width, on said first gate metal (14); forming a second gate metal layer (10) on said first gate metal layer (14) by pulse plating or electroless plating, using said first gate metal layer (14) as a feeding electrode; and removing said third resist pattern (16); are performed prior to the patterning of said gate electrode metallic material (9), said etching stopper film (6) and said first insulating film (5), in forming said T-shape gate electrode (15). A method according to any preceding claim wherein steps of: removing all remainder of said first and second insulating films (5,8); and depositing a third insulating film (12) on the whole surface of said semiconductor epitaxial substrate (1-4) and T-shaped gate electrode (15a); are performed after the forming of said T-shaped gate electrode (15a) and before the forming of said second resist pattern; and that portion of said third insulating film (12) covering said regions of semiconductor epitaxial substrate (1-4) where said source and drain electrodes are to be formed, is removed using said second resist pattern as a mask. A method according to any preceding claim wherein said refractory metallic material is WSi.

Inventors: KOHNO YASUTAKA, OKU TOMOKI, SAKAI MASAYUKI, KOHNO, YASUTAKA, OKU, TOMOKI, SAKAI, MASAYUKI, Kohno, Yasutaka, c/o Mitsubishi Denk K.K., Oku, Tomoki, c/o Mitsubishi Denk K.K., Sakai, Masayuki, c/o Mitsubishi Denk K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L29