Package for integrated circuit chips

Abstract: This invention relates to three dimensional packaging of integrated circuit chips (306) into stacks to form cube structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate (300) having a plurality of conductors (316) one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures (318) can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contains solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate (302) surface or the pin-like structures can be adapted for insertion into apertures (320) in a second substrate. The second substrate provides a means for electrically interconnecting a plurality of these cubes. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cube.

Description: Copending US application, Serial Number 07/760,038, filed September 13, 1991, entitled "Stepped Electronic Device Package" describes an electronic device packaging structure wherein an electronic device is electrically connected to a substrate wherein the electronic device subtends a non-normal angle with respect to the substrate. In a more specific embodiment, a plurality of electronic devices are stacked at an offset with respect to each other to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. This surface is disposed adjacent a substrate having a plurality of contact locations thereon. The electronic device contact locations can be electrically interconnected to the substrate contact locations by solder mounds or alternatively by a cylindrical shaped elastomeric body having metallization bands with a spacing corresponding to the electronic device contact locations. The elastomeric body is pressed between the edge of the stacked electronic devices having the contact locations thereon and substrate surface to form electrical interconnections between electronic device contact locations and substrate contact locations through the electrically conducting bands. The stacked electronic devices can be thermally connected to a heat dissipation means. The stacked electronic devices can have a stepped surface embodying an enhanced area for transfer of heat from the electronic device stack to the heat dissipation means. This invention relates to three dimensional packaging of integrated circuit chips. IC's chips are mounted on both surfaces of a first substrate. Said first substrate has conductors on both surfaces which cantilever from a first substrate edge and contain solder disposed therebetween which is used for solder contact to contact pads on a second substrate. BACKGROUND OF THE INVENTION To reduce the cost and increase the performance of electronic computers, it is desirable to place as many electronic circuits in as small a region as possible in order to reduce the distance over which electrical signals must travel from one circuit to another. This can be achieved by fabricating, on a given area of a semiconductor chip, as many electronic circuits as feasible with a given fabrication technology. Typically, these dense chips are disposed on the surface of a substrate in a side by side arrangement with with space left therebetween to provide regions for electrical conductors for electrical interconnection of the chips. The chip contact locations can be electrically connected to substrate contact locations by means of wires bonded between the chip contact locations and the substrate contact locations. Alternatively, a TAB (Tape Automated Bonding) tape (which is a flexible dielectric layer having a plurality of conductors disposed thereon) can be used for this electrical connection. Alternatively, the semiconductor chips can be mounted in a flip-chip configuration wherein an array of contact locations on the semiconductor chips is aligned with and electrically connected to an array of contact locations on the substrate by means of solder mounds disposed between corresponding chip and substrate contact locations. The side by side arrangement of electronic devices is not the most dense configuration which can be achieved. The most dense packaging configuration for semiconductor chips, in particular for memory chips, such as DRAMs, SRAMs, Flash EEPROMs and the like, may be obtained through the construction of a cuboid structure of semiconductor chips. The difficult problems to solve for such a cube are providing for electrical connections to the chips dissipating heat and reworking bad chips. The electrical connections must include power supply, data and address lines and the like. Prior art shows that it is possible to construct dense packages of stacked semiconductor wafers or chips. The major problems are that of interconnecting the chips electrically and that of solving the problem of thermal dissipation. Chips are generally stacked in orthogonal rectangular or cubiod structures. Generally, the problem of thermal dissipation is either not addressed or is handled by conduction through the structures to the environment. It is in demand to package more memory chips in a given volume. One approach is to package the chips in a 3-D form factor in which the input and output lines of the chips are brought to one edge of the chip and then multiple chips are glued together to form a cube. Since the chips in the cube are permanently bonded together, it is very difficult to rework. The current technology of doing single-chip test and burn-in is also not compatible with this type of cube packaging. US Patent 5,031,072 describes making a baseboard for orthogonal mounting of integrated circuit chips. Plural channels are anisotropically etched in a silicon baseboard and a plurality of chips are inserted into the channels. A number of baseboard contact pads are formed adjacent to each channel and are solder bonded to corresponding chip conductor pads. The baseboard is made of rigid silicon and it requires that a chip must have conduction pads near its edge for bonding to the baseboard. Also, the baseboard must have channels for the chips to be inserted and thus, the interconnection wires on the baseboard must be routed around the channels. As a result, the average length of signal wires is thus longer than desired and the baseboard substantially wider than the footprint of the chips mounted to it. US Patent 5,037,311 describes an interconnect strip to provide electrical interconnection between a plurality of conductor pads disposed on a plurality of circuit boards. The strip can be fabricated from a polymer film carrier having disposed on both sides thereof, a metal foil with preselected spring properties formed into electrical conductors which have ends which cantilever off two opposed edges of the film. Some of the ends are inserted into slots in the circuit boards to locate the remaining adjacent contact locations on the circuit boards. US Patent 5,041,903 describes a structure of a tape frame for Tape-Automated-Bonding (TAB) packages. Chips are mounted onto TAB lead frames, a portion of the leads are parallel to the chip and a portion (the outer lead end) of the lead is formed (bent) to allow the tape to be outer lead bonded to a substrate so that the package can be mounted at any desired non-zero angle with respect to a substrate. The bent portion of the outer lead is soldered to a substrate. The bent portion limits the spacing between adjacent packages to approximately between 50 and 150 mils which is the length of the bent outer lead needed to form a solder bond to the substrate. US Patent 2,568,242 is directed to a method of using a solder filled wire having core of a metal member to store solder in solid form before joining it to another metal member. The member is subsequently sheared so as to place the solder into a non-equilibrium state with the excess solder facilitating a subsequent solder connection to a nearby metal surface. Single layer and multiple layer TAB tape (and methods of fabrication) for electrical interconnection of semiconductor chips is described in US Patent 5,028,983 issued July 2, 1991 to Bickford et al., the teaching of which is incorporated herein by reference. SUMMARY OF THE INVENTION An object of the present invention is to provide a new and improved three dimensional packaging structure which can be beneficially used to package memory and logic integrated circuit chips. According to claim 1 of the present invention, conductors from the first and second surface of a first substrate extend past an edge of the first substrate. The extended portions from the first and second surfaces are aligned and spaced apart by the thickness of the first substrate to form a lead assembly. The space in the lead assembly contains solder which is used to interconnect the electrical conductors on the first substrate to electrical conductors on a second substrate. In a more particular aspect of the present invention, the lead assemblies are inserted into the apertures on the second substrate. According to claim 6 of the present invention a plurality of first substrates is mounted on a second substrate. These and other objects, features and advantages of the present invention will become apparent upon a consideration of the following detailed description of the invention when read in conjunction with the drawing Figures, in which: Figure 1 is a schematic partial disassembled view of the first substrate having a plurality of conductor assemblies for insertion into a plurality of apertures in the second substrate. Figure 2 show details of a solder bonded lead assembly which can be inserted into the apertures shown in Figure 1. The lead assembly is sheared orthogonal to the leads. Figure 3 shows a lead assembly sheared at a nonorthogonal angle. Figure 4 shows a perspective view of the lead assembly of Figures 2 and 3 solder bonded at a nonorthogonal angle to the surface of electrical conductors on a substrate. Figure 5 shows a side view of the lead assembly of Figure 2 solder bonded at an orthogonal angle to the surface of electrical conductors on a substrate. The present invention is a structure for packaging memory chips in a 3-D form factor on a flex circuit while keeping individual chips independent in a way such that each one of them can be replaced freely. The signal lines are in close proximity to a ground plane all the way from the chip to the flex. The use of flex circuit also ensures each of the chips is in good contact with a heat sink or cold plate. Figure 1 is a schematic diagram showing in perspective partially disassembled view of how first flex 300 is physically and electrically connected to main flex 302. Although the invention is being described with reference to flex tape, flex is not required, rigid substrates, such as printed circuit boards, metallized ceramics and metallized silicon wafers can be used (for the first, second and third flexes). Flex 300 can have disposed, on side 304, a plurality of electronic devices, such as semiconductor chips and decoupling capacitors which can be electrically connected by wires (or other electrically conducting means) 314 to conductors 316 on side 304. On the opposite side 308 of flex 300, there can also be disposed a plurality of electronic devices 310 which can be bonded by wires (or other electrically conducting means) 312 to conductors not shown on side 308. Flex 300 has a plurality of pin-like projections 318, which are described herein below. Pin-like members 318 are adapted for insertion into a plurality of apertures 320, on second flex 302 for electrical connection of conductors 316 and conductors on the side 308 of the pin-like members 318 which are not visible to conductors 322 and 324 of second flex 302. Although in one embodiment the pin-like members 318 are inserted into apertures 320, the ends 326 of the pin-like members can be solder bonded directly to the surface of electrical conductors, such as conductors 322 and 324 of flex 302. In one embodiment, the pin-like member 318 is formed from two electrical conductors on either side of an extension of the dielectric base layer 311 of first flex 300. The base layer 311 has a crenellated edge forming a plurality of pin-like members. Each pin-like member 318 can have more than one conductor on each side. In another embodiment, the pin-like members 318 of Figure 1 is a special structure formed from leads of flexible circuits or TAB-like flexes that can contain a certain amount of solder. The amount of solder is large enough to allow the flexes to be soldered reliably on a secondary substrate at any angle. In order to increase packaging density, it is desirable to mount chips, especially memory chips, vertically on a substrate or printed-wiring board whenever power dissipation is permitted. However, to solder leads vertically, or in general, at an arbitrary angle on a substrate is not an easy task. The yield and reliability of the solder joints are big concerns. The lead structure to be disclosed here will mitigate these concerns and result high-yield and reliable solder joints between two angled circuits. A 3-d view of the solder-well structure of a flexible circuit is shown in Figure 2. A flexible circuit consists of a polymer film 411, signal lines 412, ground or power lines 413, and auxiliary lines 416. The lines are conductors which are typically made of copper coated with noble metals or any material that conducts electricity and allows solder to wet on it. The pattern of these conductors on the polymer film depends on the circuits to be interconnected. The solder well 415 is formed by the extended portion of two conductors on both sides of the polymer film 411 which forms pin-like structure 440 of Figure 2 and 442 of Figure 3. The conductors could be both signal lines, both ground (or power) lines, signal and auxiliary lines, and ground and auxiliary lines. Solder is disposed in the well by dipping the well into a pot of molten solder or by other solder deposition tools. The amount of solder remaining in the well depends on the wetting angle of the molten solder on the conductor surface, the length and width of the extended portion of the conductors, the thickness of the polymer film 411, and the degree of parallelism of the extended portion of the conductors. An optional solder dam 414 of nonsolder wettable material such as a preform of polyimide, can be placed near the well area to avoid solder spreading during solder deposition and reflowing. Once the solder-well is prepared. the tip of the well may be sheared away in a designated angle by shearing, micromachining, grinding, or other mechanical and chemical operations, to result in the structure shown in Figure 3. (The solder filled pin-like structure can be fabricated using any type of dielectric substrate, e.g. a polymer, ceramic, glass composite and the like.) The resulting solder joints 421 on a substrate 422 are shown in Figure 4 after solder reflowing. Note that after reflowing, part of the solder from the well has flowed from the well to form a solder fillet 423 around the leads. Because the amount of solder in the solder well can be controlled, the size of each solder fillet can also be controlled. This is important when the connection pitch gets smaller. Furthermore, because solder is held by the leads; there is no need to control the thickness of solders on the solder-pads at the pre-tinning operation of the substrates. One application of the solder-well structured leads is to solder TAB chips vertically or at an angle on a printed-wiring board or other substrate. The side view of this application is shown in Figure 5, in which the solder fillet 432 are formed around the solder well 433. Pin-like structure 440 of Figure 2 and 442 of Figure 3 correspond to the pin-like structure 318 of Figure 1.

Claims: A structure comprising: a first substrate (300) having a first surface (304), a second surface (308) and an edge, said first and second surfaces are parallel and opposite to each other; a first electrical conductor (316) on said first surface; a second electrical conductor on said second surface; said first electrical conductor (316) has a portion which cantilevers over said edge as a first cantilevered lead; Said second electrical conductor has a portion which cantilevers over said edge as a second cantilevered lead; said first cantilevered lead and said second cantilevered lead being substantially aligned and opposite to each other with a space therebetween forming a lead assembly, characterized in that said space contains solder. The structure of claim 1, further including a second substrate having an electrical conductor thereon, said lead assembly being soldered to said electrical conductor on said second substrate. The structure of claim 2, wherein said first substrate is in a nonorthogonal arrangement with respect to said second substrate. The structure of claim 3, wherein said first and said second cantilevered leads have different length to accommodate said nonorthogonal arrangement of said first substrate with respect to said second substrate. The structure of any one of claims 1 to 4, further including an aperture in said second substrate adopted to receive said lead assembly. A structure comprising: a plurality of first substrates; each of said plurality of said first substrates has a first surface and a second surface, said first and second surfaces are parallel and opposite to each other; said first surface has a plurality of electrical conductors disposed thereon; said second surface has a plurality of electrical conductors disposed thereon; at least one electronic device is disposed in electrical contact with said plurality of electrical conductors on said first surface of said first substrate to form a plurality of first assemblies; at least a portion of said plurality of electrical conductors on said first surface extend to an edge of said first substrate and cantilever over said edge as a plurality of first cantilevered leads; at least a portion of said plurality of said second electrical conductors disposed on said second surface extend to said edge and cantilever over said edge as a plurality of second cantilevered leads; each of said first cantilevered leads is aligned with one of said second cantilevered leads with a space therebetween containing solder to form a plurality of lead assemblies; each of said plurality of first assemblies being disposed adjacent another one of said plurality of first assemblies so that said at least one electronic device of one of said adjacent assemblies is adjacent said second side of the other of said adjacent assemblies; a second substrate having conductors, at least a portion of which extend to a plurality of apertures adapted to receive said plurality of lead assemblies; and each of said plurality of lead assemblies being soldered to electrical conductors on said second substrate which extend to said apertures.

Inventors: CIPOLLA THOMAS MARIO, COTEUS PAUL WILLIAM, DAMIANAKIS IOANNIS, JOHNSON GLEN WALDEN, LEDERMANN PETER GERARD, MATTHEW LINDA CAROLYN, MOK LAWRENCE SHUNGWEI, CIPOLLA, THOMAS MARIO, COTEUS, PAUL WILLIAM, DAMIANAKIS, IOANNIS, JOHNSON, GLEN WALDEN, LEDERMANN, PETER GERARD, MATTHEW, LINDA CAROLYN, MOK, LAWRENCE SHUNGWEI
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1993
Main classification: H01L25
IPC codes: H01L25, H05K1, H05K3