Digital error corrected fractional-N synthesizer

Abstract: A digital error corrected Fractional-N synthesizer (100) having a reference frequency generator (112) for providing a reference frequency signal F ref and a voltage controlled oscillator (130) for providing an output signal F out having a frequency equal to a fractional multiple of said reference frequency signal F ref . The output signal F out of the Fractional-N synthesizer (100) includes a residual error signal t e . An error signal compensation circuit (150) is provided for generating a correction signal t cor to cancel the residual error signal t e . In a preferred embodiment, the reference frequency signal F ref is delivered to a loop phase detector (114) which provides an error voltage V err proportional to a phase difference between the reference frequency signal F ref and a feedback signal. The frequency of the output signal F out , which is a fractional multiple of the reference frequency signal F ref and proportional to the error voltage V err , is operated upon by a plurality of divisors of a loop divider circuit (132) to provide the feedback signal. The residual error signal t e appears at an output terminal of the loop phase detector (114). The error signal compensation circuit (150), which includes a binary counter (160) and a magnitude comparator (162), generates the correction signal t cor to cancel the residual error signal t e . A summing node (154) is provided for canceling the residual error signal t e . The resistors (124, 164) of a summing network (152) are scaled so that the total energy in the correction signal t cor is equal to the total energy in the residual error signal t e .

Description: BACKGROUND OF THE INVENTION The present invention relates to synthesizers. More specifically, the present invention relates to an apparatus for reducing spurious frequency errors in Fractional-N type indirect synthesizers. Synthesizers are utilized for selecting specific frequencies in the radio spectrum for either transmission or reception of signals. Synthesizers have the ability to step in precise frequency increments. However, indirect, phase-locked single-loop synthesizers cannot provide frequency step sizes less than an applied reference frequency. Further, certain limitations must be satisfied in single-loop synthesizer design in order to provide small frequency step sizes. Those limitations include that the synthesizer must settle at a particular frequency in a very short time and that the synthesizer provide a spectrally pure output (e.g., frequency components and harmonics not included). To achieve small frequency step sizes, the applied reference frequency (F ref ) must be small since the synthesizer steps in increments of F ref . In order to achieve a fast settling time at a particular synthesizer frequency, the loop filter must exhibit a wide bandwidth. However, a narrow loop filter bandwidth is required to reject the reference frequency (F ref ) component in the phase detector. These loop filter bandwidth requirements are mutually exclusive. The solution in the past to overcome the inability to provide frequency step sizes smaller than F ref and to overcome the mutually exclusive bandwidth problems has been to employ fractional-N synthesizers. A single-loop synthesizer receives the reference frequency (F ref ) signal at the input terminal of a loop phase detector. The output signal of the loop phase detector is transmitted to a low pass loop filter comprised of an operational amplifier and appropriate feedback circuitry. The output of the loop filter is directed to a voltage controlled oscillator (VCO) which provides an output frequency signal. A portion of the output frequency signal is fed back to a loop divider circuit which receives a user-selected program word to program the divide ratio and to provide a divided output frequency signal. The divided output frequency signal is transmitted to the loop phase detector and compared to F ref for generating a loop error voltage. The loop error voltage is filtered in the loop filter for tuning the voltage controlled oscillator. Upon being tuned, the voltage controlled oscillator is forced to slew in frequency with the slewed frequency being controlled by the tuned voltage fed into the voltage controlled oscillator. A slewed output frequency signal is fed back to the loop phase detector via the loop divider circuit for reducing the loop error voltage to zero. Thus, the output frequency signal of the voltage controlled oscillator is also the synthesizer output signal. Ideally, the loop error voltage should eventually become zero by the action of the single-loop. The phase detector monitors the changes in the single-loop due to temperature drift and component age that are responsible for changes in the output frequency signal of the voltage controlled oscillator. The error voltage output of the phase detector signals the presence of and compensates for these variations. The slewed output frequency signal fed back to the loop divider circuit is subjected to division by the user-selected program word "/N" which is actually a variable divide ratio "N div ". The value of "N div " at any time is controlled by the fractional-N control circuit where "N div " can assume the value of "/N" or "/N+1". The fractional-N control circuit comprises an accumulator circuit which includes a latch and an adder. The adder receives a fractional frequency word from an external source. The latch and the adder cooperate with the loop divider to periodically add a "+1" to the program word for changing the divide ratio to "/N+1". The use of two dividers provides for an average divide ratio "DIV" effectively having an integer component and a fractional component. However, the instantaneous divide ratio is either "/N" of "/N+1". The fractional divide ratio of the fractional-N synthesizer is employed to provide frequency step sizes less than F ref . This is accomplished by varying the divide ratio over time as illustrated in the following example. To divide by a non-integer value, such as 10.1, the divider would assume the value N = 10 for nine cycles in succession and then the value of N+1 = 11 for one cycle. Over the ten divide intervals, the average ratio is 10.1. Thus, the resulting synthesizer output frequency is 10.1 times the reference frequency F ref , a fractional multiple. Since the divider changes between two discrete ratios (N = 10, N+1 = 11), a fractional-N error pulse t e is created. The output frequency signal from the voltage controlled oscillator is operating at a fractional multiple of F ref . Dividing by the two ratios "/N" and "/N+1" causes the frequency of the output signal of the loop divider circuit to be somewhat different from the frequency of the constant F ref being transmitted to the loop phase detector. Although the error pulse t e is caused by changing the divide ratio in the loop divider, it manifests itself at the output terminal of the loop phase detector. Without correction, the error pulse t e will result in an undesirable spurious modulation on the synthesizer output signal. The fractional-N error pulse t e appears at the output terminal of the phase detector at each reference clock pulse. The error pulse t e is filtered through the loop filter and generates a voltage error V err at the input terminal of the voltage controlled oscillator. Since an error pulse t e appears at the output terminal of the loop phase detector at each clock pulse, the voltage error V err accumulates over time. The accumulated voltage error V err modulates the output frequency signal of the voltage controlled oscillator causing spurious signals to appear in the synthesizer output signal. Thus, the fractional-N synthesizer is unable to provide a spectrally pure output signal. Several attempts have been made to compensate for the existence of the error pulse t e appearing at the output terminal of the loop phase detector and the corresponding error voltage V err generated at the input terminal of the voltage controlled oscillator. Generally, the compensation schemes of the prior art include correction circuits which utilize digital-to-analog converters or switched current sources. In GB-A1 560 233 a synthesiser is discribed which comprises an adder/storer combination for providing a divider correction to achieve a correct average dividing factor. The storer content is applied to a digital-to-analogue converter to provide an analogue signal which is representative of the phase error between the reference frequency pulses and the nearest preceding pulse input to a programmable divider. The analogue signal is applied to an adder by way of a switch and a resistor network which are scaling the maximum output voltage of the digital-to-analogue converter. The digital-to-analog approach is limited in that the analog output signal can drift with temperature and result in reduced error pulse cancellation. Current sources, when properly implemented, can provide reasonable insensitivity to temperature variations. However, this solution requires expensive precision components to make the current sources reasonably insensitive to temperature variations. Thus, there are cost and performance disadvantages to both prior art approaches. Thus, there is a need in the art for an improvement in error pulse correction schemes for single-loop Fractional-N synthesizers which prevent undesirable spurious modulation of the synthesizer output signal. The need in the art is addressed by the digital error corrected Fractional-N synthesizer of claim 1. The invention includes a reference frequency generator for providing a reference frequency signal and a voltage controlled oscillator for providing an output signal having a frequency equal to a fractional multiple of said reference frequency signal. The output signal of the Fractional-N synthesizer includes a error signal. An error signal compensation circuit is provided for generating a correction signal to cancel the error signal. In a preferred embodiment, the reference frequency signal is delivered to a loop phase detector which provides an error voltage proportional to a phase difference between the reference frequency signal and a feedback signal. The frequency of the output signal, which is a fractional multiple of the reference frequency signal and proportional to the error voltage, is operated upon by a plurality of divisors of a loop divider circuit to provide the feedback signal. The error signal appears at an output terminal of the loop phase detector. The error signal compensation circuit, which includes a binary counter and a magnitude comparator, generates the correction signal to cancel the error signal. A summing node is provided for canceling the error signal. The resistors of a summing network are scaled so that the total energy in the correction signal is equal to the total energy in the error signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a simplified block diagram of an illustrative embodiment of a single-loop Fractional-N synthesizer of the prior art. Fig. 2 is a timing diagram of the sequence of events in the operation of the loop divider and accumulator circuits of the prior art single-loop Fractional-N synthesizer of Fig. 1. Fig. 3 is a timing diagram of the prior art single-loop Fractional-N synthesizer of Fig. 1 particularly illustrating the error pulse (t e ) and the associated error voltage (V err ). Fig. 4 is a graph illustrating the error voltage (V err ) versus time for an uncorrected loop error in the prior art Fractional-N synthesizer of Fig. 1. Fig. 5 is a graph illustrating the error voltage (V err ) versus frequency for an uncorrected loop error in the prior art Fractional-N synthesizer of Fig. 1. Fig. 6 is a simplified block diagram of an illustrative embodiment of a single-loop error corrected Fractional-N synthesizer of the present invention showing the error pulse compensation logic circuitry. Fig. 7 is a timing diagram of the single-loop error corrected Fractional-N synthesizer of Fig. 6 particularly illustrating the error pulse (t e ) and the correction pulse (t cor ) generated in response thereto. Fig. 8 is a graph illustrating the error voltage (V err ) versus time for a corrected loop error in the Fractional-N synthesizer of Fig. 6. Fig. 9 is a graph illustrating the error voltage (V err ) versus frequency for a corrected loop error in the Fractional-N synthesizer of Fig. 6. DESCRIPTION OF THE INVENTION Synthesizers are utilized for selecting specific frequencies in the radio spectrum for either transmission or reception of signals. Synthesizers have the ability to step in precise frequency increments. However, an indirect phase-locked single-loop synthesizer cannot provide frequency step sizes less than the reference frequency F ref . Fractional-N synthesizers of the prior art have overcome this limitation by means of a fractional divide ratio. This is achieved by varying the divide ratio over time. A simplified block diagram of a Fractional-N synthesizer 10 of the prior art is shown in Fig. 1. Shown therein is a reference frequency generator 12 which provides a reference frequency F ref to the input terminal of a loop phase detector 14. The output signal of the loop phase detector 14 is transmitted to a low pass loop filter 16 comprised of an operational amplifier 18 with a series feedback resistor 20 and capacitor 22 and filter elements including resistors 24 and 26 and capacitor 28 connected to electrical ground. The output of the loop filter 16 is directed to a voltage controlled oscillator (VCO) 30 which provides an output frequency signal F out . A portion of the output frequency signal F out is fed back to the loop phase detector 14 via a loop divider circuit 32. The divider circuit 32 receives an external user-selected program word "/N" to program the divide ratio and to provide a divided output frequency signal. The divided output frequency signal is transmitted back to the loop phase detector 14 and compared to F ref for generating a loop error voltage as is known in the art. The loop error voltage is filtered in the loop filter 16 for tuning the voltage controlled oscillator 30 which is forced to slew in frequency. The slewed frequency is controlled by the tuned voltage delivered to the voltage controlled oscillator 30. A slewed output frequency signal F out is fed back to the loop phase detector 14 via the loop divider circuit 32 for reducing the loop error voltage to zero. The output frequency signal F out of the voltage controlled oscillator 30 is also the synthesizer output signal. The loop error voltage will eventually approach zero by the feedback action of the single-loop synthesizer. The phase detector monitors the changes in the single-loop due to temperature drift and component age and permits compensating for these variations. The slewed output frequency signal fed back to the loop divider circuit 32 is subjected to division by the user-selected program word "/N". The divider circuit 32 is represented by the divide ratio "N div " and is equivalent to N div = F out /F ref Therefore, F out = N div x F ref The value of "N div " at any time is controlled by the fractional-N control circuit where "N div " can assume the value of "/N" or "/N+1". The fractional-N control circuit comprises an accumulator circuit 34 which includes a latch 36 and an adder 38. The adder 38 receives a fractional frequency word "F" from an external source. The latch 36 and the adder 38 cooperate with the loop divider 32 to periodically add a "+1" to the program word "/N" for changing the divide ratio to "/N+1". The use of two dividers provides for an average divide ratio "DIV" effectively having an integer component and a fractional component. However, the instantaneous divide ratio is either "/N" or "/N+1". The initial objective is to achieve a frequency step size smaller than F ref . The desired frequency step is an integral submultiple (e.g., fraction) of the loop reference frequency F ref as shown below where f step = F ref /n and "n" is radix of the adder 38. The adder 38 adds the fractional frequency word "F" to the previous sum stored in the latch 36 at each clock edge of F ref . The new sum thereafter replaces the previously stored sum in the latch 36. The latch 36 holds the numerical value of the adder 38 which is located at the input of the latch 36 for one reference clock period. This action is repeated from one reference clock period to the next reference clock period. The adder 38 receives the output of the latch 36 and again adds the fractional frequency word "F" thereto. After each clock cycle, the sum of the adder 38 increases providing an accumulator action. The adder 38 accumulates at a rate controlled by F ref until the value of "n-1" is reached. After the next reference clock, the output of the adder 38 reaches a maximum value. Thereafter, a carryover output "C o " having the value of a logical-1 is produced and the output of the adder 38 goes to zero. The carryover output "C o " is transmitted back to the loop divider circuit 32 as shown in Fig. 1. This action causes the loop divider circuit 32 to increase its divide ratio N div from "/N" to "/N+1" for one reference clock cycle. The following reference clock cycle causes the value of the accumulator circuit 34 carryover output C o to return to zero and the sequence repeats. The periodically varying loop divide ratio N div represents a fraction when averaged over multiple reference clock cycles. Thus, the average divide ratio "DIV" varies over time in which the instantaneous loop divide ratio N div has the value "/N" for (n-1) reference clock cycles and the value "/N+1" for one additional reference clock cycle. A representation of the average divide ratio "DIV" is clearly shown in Fig. 2. The top line shown in Fig. 2 illustrates a plurality of periodic reference clock cycles wherein the maximum value or radix of the adder 38 is indicated to be "n". Additionally, it is shown that the instantaneous divide ratio is "/N" for (n-1) reference clock cycles and that the instantaneous divide ratio is "/N+1" for one additional reference clock cycle. The bottom line in Fig. 2 represents the carryover output C o which is a logical-1 when the divide ratio is "/N+1". The fractional or average divide ratio "DIV" is determined in the following manner. It is known from equation [3] that the small frequency step size "f step " is determined by dividing F ref by "n", the radix of the adder 38. The fractional frequency word "F" (e.g., the fractional portion of the program word) is equal to F = 1/n while the integer portion of the program word is determined by the instantaneous divide ratio "N div which is "/N" for (n-1) reference clock cycles and "/N+1" for one additional reference clock cycle. Therefore, the average divide ratio "DIV" which is averaged over "n" reference clock cycles is determined as follows DIV = [(n-1)N + 1(N+1)]/n Upon simplification of equation [5], the following expression results in DIV = N + (1/n) The term "N" in equation [6] represents the integer portion of the program word and is fed to the loop divider circuit 32 shown in Fig. 1. The term "1/n" as indicated in equation [4] represents the fractional portion "F" of the program word and is fed to the adder 38 also shown in Fig. 1. Therefore, the simplified form of the average divide ratio is DIV = N.F In the single-loop fractional-N divider, the fractional portion "F" provides for the smaller frequency step size while still permitting the larger integer portion "N" to provide the faster settling time. Equation [2] recites that the output frequency F out is equal to the instantaneous divide ratio N div times the reference frequency F ref . Substituting the average divide ratio "DIV" for the instantaneous divide ratio N div in equation [2], the following expression is obtained F out = N.F x F ref Thus when locked, the loop voltage controlled oscillator 30 will provide a frequency output signal F out which is N.F times the reference frequency F ref . While the voltage controlled oscillator 30 is operating at the N.F multiple of the reference frequency F ref as indicated in equation [8], the loop divider circuit 32 can only divide by "/N" or "/N+1". The resulting frequency signal fed back to the loop phase detector 14 from the loop divider circuit 32 is F feedback = (N.F/N) x F ref and this frequency is compared to F ref . Since the loop divider circuit 32 changes between two discrete ratios, a error pulse t e is created. Dividing by the two ratios "/N" and "/N+1" causes the frequency of the output signal F out of the loop divider circuit 32 to vary from the frequency of the reference frequency F ref . The error pulse t e appears at the output terminal of the loop phase detector 14 at each reference clock pulse F ref . The error pulse t e is filtered through the loop filter 16 with the loop voltage error V err . The error pulse t e and the voltage error V err accumulate over time and modulate the output frequency signal F out of the voltage controlled oscillator 30 causing undesirable spurious signals to appear in the synthesizer output signal. The pulse width of the error appearing at the output terminal of the loop phase detector 14 is t e = (1/F ref ) x (1 - N/N.F) A timing diagram is shown in Fig. 3 which includes the error pulse t e . The reference frequency F ref is shown as being a periodic signal. The frequency signal F feedback which is fed back to the loop phase detector 14 from the loop divider circuit 32 recited in equation [9] is shown. During three reference clock cycles, the instantaneous divide ratio N div of the loop divider circuit 32 is "/N". However, during the fourth reference clock cycle, the instantaneous divide ratio N div is "/N+1" in accordance with the description herein. This variation in the divide ratio leads to the error pulse t e . As shown in Fig. 3, an error pulse t e occurs for each reference clock cycle and thus accumulates. The voltage error V err generated at the input of the voltage controlled oscillator (VCO) 30 accumulates in a similar manner with the error pulse t e as shown in Fig. 3. A design computer simulation of a response of the loop filter 16 to the error pulse t e is illustrated in Figs. 4 and 5. In this example, the instantaneous divide ratio "/N" = 8158, the reference frequency F ref = 120KHz, the fractional frequency word "F" = 0.25 and the band-width of the loop filter 16 is 3KHz. The resulting width of the error pulse t e is 0.255 nS as indicated in Fig. 3. The simulation shows a peak-to-peak output of the loop filter 16 to be greater than one millivolt. The error voltage V err shown in Fig. 4 (error voltage V err vs. time) increases over time causing an accumulated error. The corresponding spectrum of the error pulse t e shows frequency components in Fig. 5 (error voltage V err vs. frequency) which are spaced at 30 KHz increments. This incremental spacing is determined by(F ref x F) = 120KHz x 0.25 = 30KHz. The lowest frequency component has a peak amplitude of 400 microvolts (0.0004 volts) as shown at point 40 in Fig. 5. These frequency components 40 will modulate the output frequency F out of the voltage controlled oscillator 30 causing undesirable spurious sidebands. Many of the spurs shown in Fig. 5 are caused by harmonics (as at point 42) which may possibly obliterate a communication on a channel adjacent to the channel that the spurs (40 and 42) appear on. An example of where such a problem might occur is in a cellular telephone system (not shown). This situation leads to the loss of spectral purity in the synthesizer output signal. As an example, if the gain of the voltage controlled oscillator 30 was 10MHz/Volt, a sideband at 30KHz of [20 x Log {(0.0004V x 10 MHz)/(2 x 30 KHz)}] or -23.5 (dBc) would result. Typical values required for a spurious sideband range from (-55 to -75) dBc. Several attempts have been made to compensate for the existence of the error pulse t e appearing at the output terminal of the loop phase detector 14 and the corresponding error voltage V err generated at the input terminal of the voltage controlled oscillator 30. However, these approaches, which generally include compensation schemes utilizing digital-to-analog converters or switched current sources, are both costly to implement and difficult to maintain. As shown in drawing Fig. 6 for purposes of illustration, the invention is embodied in a single-loop, digital error corrected Fractional-N synthesizer 100 of the type having a loop divider circuit 132 employing a variable divide ratio comprising integer "N" and fractional "F" components and an error pulse compensation circuit 150 which cancels the error pulse t e created by the operation of the variable divide ratio. In accordance with the present invention, the error pulse compensation circuit 150 which provides a correction pulse t cor and a resistor summing network 152 which scales the total energy in the correction pulse t cor to be equal to the total energy in the error pulse t e cooperate to cancel the error pulse t e at a summing node 154. Further, the present invention incorporates an all digital design which requires no adjustment, eliminates drifts and variations in temperature and supply voltage associated with analog components, provides a lower cost design with reduced complexity, and has wide applicability in communication technology. The single-loop, digital error corrected Fractional-N synthesizer 100 of the present invention is disclosed in Figs. 6 - 9 and includes many of the main components of the circuitry of the Fractional-N synthesizer 10 of Figs. 1 - 5. Components of the digital error corrected Fractional-N synthesizer 100 of the present invention shown in Figs. 6 - 9 which find substantial correspondence in structure and function to those components of Figs. 1 - 5 are designated with corresponding reference numerals of the one-hundred series. In the present invention, a reference frequency generator 112, a loop phase detector 114, a low pass loop filter 116, a voltage controlled oscillator (VCO) 130 and an accumulator circuit 134 each perform the same function as that described with reference to the Fractional-N synthesizer 10 of Fig. 1. The reference frequency generator 112 provides the reference frequency F ref to the input terminal of the loop phase detector 114. A divided output frequency signal is also delivered to the detector 114 and compared to F ref for generating a loop error voltage V err . The error voltage V err is filtered in a loop filter 116 comprised of an operational amplifier 118 and a series feedback resistor 120 and capacitor 122 and filter elements including resistors 124 and 126 and capacitor 128 connected to electrical ground. The filtered loop error voltage V err is utilized to tune the voltage controlled oscillator 130 which is forced to slew in frequency to provide an output frequency signal F out . A portion of the slewed signal F out is fed back to the phase detector 114 via a loop divider circuit 132 for reducing the error voltage V err to zero. The divider circuit 132, which includes a modulus controller 156, receives an external user-selected program word "/N" to program the divide ratio N div and to provide the divided output frequency signal. The output frequency signal F out of the voltage controlled oscillator 130 is also the synthesizer output signal. The error voltage V err will eventually approach zero by the feedback action. In order to provide an output signal F out that has a frequency equal to a fractional multiple of the reference frequency F ref , the loop divider circuit 132 must exhibit a variable divide ratio N div . The possible values of N div are controlled by the accumulator circuit 134 which includes a latch 136 and an adder 138. The adder 138 receives a fractional frequency word "F" from an external source. The latch 136 and the adder 138 cooperate with the loop divider circuit 132 in the manner described regarding the Fractional-N synthesizer 10. After several reference clock cycles of adding the fractional frequency word "F" to the previous sum in the latch 136, the adder 138 reaches a maximum value. Thereafter, the adder 138 transmits a carryover output "C o " of "+1" to the divider circuit 132 as shown in Fig. 6 for changing the divide ratio from "/N" to "/N+1". The carryover output C o then returns to zero and the process repeats. The use of two divider ratios provides for an average divide ratio "DIV" (see equations [5] - [7]) effectively varying over time in which N div has the value "/N" for (n-1) clock cycles and the value "/N+1" for one clock cycle. Since the loop divider circuit 132 changes between two discrete ratios, the error pulse t e appears at the output terminal of the phase detector 114 at each reference clock pulse F ref . The error pulse t e is filtered through the loop filter 116 with the loop voltage error V err at the voltage controlled oscillator 130. The voltage error V err accumulates over time and modulates the output frequency signal F out causing undesirable spurious signals to appear in the synthesizer output signal. In the present invention, the correction pulse t cor is added to the error pulse t e at the summing node 154 shown in Fig. 6. Since the correction pulse t cor has energy equal to and opposite from that of the error pulse t e , the spurious sidebands are canceled or at least significantly reduced. If the width of the correction pulse t cor was equal to the width of the error pulse t e , a perfect cancellation would result. However, this would require a reference clock speed of several gigahertz for the digital logic to implement this narrow pulse. The approach employed in the present invention utilizes a lower reference frequency and enables the desirable feature of utilizing lower cost CMOS technology. The correction pulse t cor is significantly wider than the error pulse t e when utilizing the lower speed logic. However, by scaling down the amplitude of the correction pulse t cor with the resistor summing network 152, total energy equivalent to that of the error pulse t e is achieved. The loop divider circuit 132 is comprised of the modulus controller 156 and a variable modulus prescaler 158 as shown in Fig. 6. In combination, the controller 156 and prescaler 158 provide the variable divide ratio N div . The clocks for the correction logic are derived from the voltage controlled oscillator 130 through the variable modulus prescaler 158. The modulus prescaler 158 functions to divide the high output frequency F out by a dual modulus to provide a lower frequency signal which is then transmitted to the modulus controller 156. The lower frequency signal permits the use of a conventional divider circuit 132. In particular, the modulus controller 156 can incorporate conventional CMOS technology which is more economical to manufacture and operates at a lower power level and at a lower frequency. The variable modulus prescaler 158 permits lower frequency programmable counters (not shown) to function without the loss of resolution at frequencies of several hundred megahertz. In the present invention, the dual modulus is 64/65 which has been selected to reduce F out (from approximately 900 MHz) to a value that is capable of being divided by conventional CMOS hardware. The logic is sequenced such that the clocks are processed only during the /65 modulus. Thus, the minimum width of the correction pulse t cor for cancellation of the error pulse t e is t cor minimum pulse width = 65/(N.F x F ref ) The voltage controlled oscillator 130 drives the variable modulus prescaler 158 which includes the dual modulus. The divide ratio N div can vary between the two divider values "/64" and "/65". The combination of the two divide ratios of the variable modulus prescaler 158 provides the variable divide ratio N div . Further, the divide ratio N div of the variable modulus prescaler 158 is controlled by the modulus controller 156. It is noted that the equations previously presented in the description of the Fractional-N synthesizer 10 of Fig. 1 (particularly equations 1 - 3) are also applicable to the Fractional-N synthesizer 100 disclosed in Fig. 6. The divided output signal is then fed back from the modulus controller 156 of the divider circuit 132 to the phase detector 114. A portion of the clock signal output of the variable modulus prescaler 158 is used to drive or clock a binary counter 160 as shown in Fig. 6. The binary counter 160 incorporates the same low power CMOS technology employed in the modulus controller 156 and thus is compatible therewith. The function of the binary counter 160 is to provide a periodic multi-digit word to a digital magnitude comparator 162. The value of the multi-digit word in the binary counter 160 is incremented at a multiple of the reference frequency F ref . In the present invention, the output frequency signal of the voltage controlled oscillator 130 divided by N div (where N div = "/64") is delivered to the binary counter 160. The binary counter 160 then increments to the next binary state (0, 1, 2, ..., 16) with each clock transition of the "/64" divider of the modulus prescaler 158. Thus, the incrementing of the binary counter 160 is much faster than the clock period of the reference frequency F ref . The magnitude comparator 162 includes an "A" input terminal, a "B" input terminal and an output terminal as shown in Fig. 6. The latch 136 of the accumulator circuit 134 is connected to the "A" input terminal while the binary counter 160 is connected to the "B" input terminal. The output of the latch 136 of the accumulator circuit 134 represents the incremented value of the fractional portion of the frequency word "F". With every reference clock pulse F ref , the accumulator circuit 134 increments its digital value upward (0, 1, 2, ..., 16). The function of the magnitude comparator 162 is to compare the incremented value of the binary counter 160 with the incremented value of the accumulator circuit 134 and to generate an output signal as a result of the comparison. At each and every increment value of the accumulator circuit 134, the binary counter 160 generates several increment values. Some of the increment values generated by the binary counter 160 are greater than and some are less than the incremented value of the accumulator circuit 134. During the comparison, there is a period of time when the multi-digit word of the binary counter 160 is less than the magnitude of the increment value of the accumulator circuit 134 (e.g., A > B, see Fig. 6). Under these conditions, the magnitude comparator 162 generates a logical one which is transmitted to the resistor summing network 152. Likewise, there is a period of time during the comparison when the multi-digit word of the binary counter 160 is greater than the magnitude of the increment value of the accumulator circuit 134 (e.g., B > A). Under these conditions, the magnitude comparator 162 generates a logical zero. Thus, by comparing the accumulated fractional word "F" incremented with F ref at the "A" input with the multi-digit word incremented at a multiple of F ref at the "B" input, the magnitude comparator 162 generates a pulse width as a function of the value of the two inputs. The output signal of the magnitude comparator 162 is either a logical one or a logical zero. If the output signal is a logical one, a correction pulse t cor is generated to cancel the error pulse t e . The generated correction pulse t cor reflects the presence of the error pulse t e at the output terminal of the phase detector 114. The output of the magnitude comparator 162 is a logical one for a finite number of pulses which is determined by the output signal of the voltage controlled oscillator 130 divided by N div (e.g., "/64"). It is noted that after the initial correction pulse t cor is generated and added to the error pulse t e at the summing node 154, any non-canceled error pulse is referred to as the "residual error pulse" t e . The residual error pulse t e is minimized by repeated feedback action. If the output signal is a logical zero, error correction does not occur at the summing node 154. This condition implies that a residual error pulse t e is not present at the output terminal of the phase detector 114. The logical one generated by the magnitude comparator 162 is summed through the resistor summing network 152 to form the correction pulse t cor . The resistor summing network 152 is comprised of resistor 124 located at the input to the loop filter 116 and a resistor 164 located between the magnitude comparator 162 and the summing node 154. The size ratio of the two resistors 124 and 164 are selected to scale the total energy in the correction pulse t cor to be equal and opposite to the total energy in the error pulse t e . Thus, the summation of the two pulses, t e and t cor , at the summing node 154 results in cancellation of the t e as indicated below. For the total energy in the t cor to equal the total energy in the t e , the following must exist E err + E cor = 0 In the present invention, the supply voltage for all CMOS logic components is designated V cc . If the scaling resistor 124 is designated by R 1 , the total energy in the error pulse t e is defined as E err = (V cc 2 /R 1 ) x t e Further, where scaling resistor 164 is designated by R 2 , the total energy in the correction pulse t cor is defined as E cor = (V cc 2 /R 2 ) x t cor By equating the two equations [13] and [14] and simplifying terms, the following expression is obtained. t e /R 1 = t cor /R 2 Transposition of equation [15] provides R 2 /R 1 = t cor /t e Based upon the expressions for the pulse width of the error pulse t e and the correction pulse t cor in equations [10] and [11], respectively, an expression for the ratio of the scaling resistors 124 and 164 is R 2 /R 1 = (65/N.F x F ref )/{1 - (N/N.F)(1/F ref )} By simplifying equation [17], the final expression which ensures that the energy in the correction pulse t cor is equal to the energy in the error pulse t e is R 2 /R 1 = 65/.F Thus, the ratio of the correction pulse t cor to the error pulse t e is equal to the prescaler divide ratio ("/65") divided by the fractional portion ("F") of the frequency word. It is noted that the ratio is controlled by scaling resistors 124 (R 1 ) and 164 (R 2 ). A detailed timing diagram is shown in Fig. 7. The reference frequency F ref is shown as a periodic signal. The relationship between the error pulse t e , the output signal of the binary counter 160 and the correction pulse t cor is shown. Note that the output signal of the magnitude comparator 162 is at a logical one as long as the output signal of the accumulator circuit 134 is greater than the multi-digit word of the binary counter 160. Thus, a correction pulse t cor is created having a width proportional to the width of the error pulse t e . By selecting the scaling resistors 124 and 164 at the appropriate ratio (65/.F), the energy in the correction pulse t cor will equal the energy in the error pulse t e . A second design computer simulation was conducted. The second simulation was of a response of the loop filter 116 to the error pulse t e and the results are illustrated in Figs. 8 and 9. The circuit parameters in this example are the same as that utilized in the example illustrated in Figs. 4 and 5. Fig. 8 illustrates the corrected error voltage V err vs. time and shows that the error voltage V err is reduced in magnitude. A comparison of Figs. 4 and 8 illustrates that the uncorrected error voltage of Fig. 4 is on the order of (1 - 5) millivolts while the corrected error voltage shown in Fig. 8 is on the order of (5 - 18) microvolts. Fig. 9 illustrates the error voltage V err vs. frequency and shows a reduction in the magnitude of the spurious signals in the output frequency signal F out . The 30 KHz frequency component that originally exhibited a 400 microvolt (0.0004 V) spur amplitude in the uncorrected circuit of Fig. 5 was reduced to 4.4 microvlots (0.0000044 V). This is a significant spur reduction of 39 dB. The resulting (-23.5) dBc spur occurring in the uncorrected example previously disclosed for the Fractional-N synthesizer 10 would be reduced to (-62.5) dBc by employing the corrected Fractional-N synthesizer 100 of the present invention. The single-loop Fractional-N synthesizer 100 of the present invention utilizes a digital approach that can be readily implemented using low cost, off-the-shelf components which reduces the overall circuit complexity and expense. The all digital design approach requires no adjustments. Further, drifts and variations due to temperature and supply voltage associated with previously employed analog components are eliminated. The present invention has wide applicability to communication technology and specifically to dual mode cellular telephone technology. The correction timing and signal generation are performed digitally resulting in close tracking of the error pulse t e by the correction pulse t cor over varying system parameters such as temperature and supply voltage. Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof. For example, although described in the form of a digital application, the error compensation circuit of the present invention can also be implemented in analog form. It is therefore intended by the appended claims to cover any and all such modifications, applications and embodiments within the scope of the present invention.

Claims: A digital error corrected synthesiser (100) comprising: means (112) for providing a reference frequency signal (F ref ); detector means (114) for providing an error voltage (V err ) at an output terminal proportional to a phase difference between said reference frequency signal (F ref ) and a feedback signal; means (130) for providing an output signal (F out ) having a frequency equal to a fractional multiple of said reference frequency signal and proportional to said error voltage (V err ); means (132) for dividing said output signal (F out ) by one of a plurality of divisors to provide said feedback signal to said detector means (114), said plurality of divisors creating an error pulse (t e ) at said output terminal of said detector means; means (150) for generating a correction signal to cancel said error pulse (t e ), said correction means being coupled between said means for providing a reference frequency (112) and said dividing means (132); and cancelling means (124,164) coupled between said correction signal means (150) and the output of said detector means (114), characterised in that said means (150) for generating a correction signal generate a digital correction pulse (t cor ) having a variable pulse width for cancelling said error pulse (t e ); and said cancelling means (124,164) comprises a resistor summing network for scaling the total energy in said correction pulse (t cor ) to be equal to the total energy in said error pulse (t e ). The digital error corrected synthesiser according to claim 1 wherein said means for dividing said output signal comprises a divider circuit having a variable modulus prescaler (158) for down converting the frequency of said output signal. The digital error corrected synthesiser according to claim 2 wherein the divider circuit further includes a modulus controller (156) for controlling the selection of said one of said plurality of divisors. The digital error corrected synthesiser according to any of claims 1-3 further including a loop filter (116) for rejecting undesirable components from said detector means. The digital error corrected synthesiser according to claim 4 wherein said loop filter includes an amplifier (118) for amplifying said error voltage. The digital error corrected synthesiser according to any of claims 1-5 further including an accumulator circuit (134) for transmitting a signal to a modulus controller in communication with said dividing means for selecting a second of said plurality of divisors. The digital error corrected synthesiser according to any of claims 1-6 wherein said means for generating a correction signal (150) comprises a magnitude comparator (162) for sensing the presence of said residual error signal (t e ) and for providing said correction pulse (t cor ) to said cancelling means.

Inventors: FOUNTAIN ERIK C, FOUNTAIN, ERIK C.
Applicants: HUGHES AIRCRAFT CO, HE HOLDINGS, INC.
Application year: 1993
Main classification: H03L7
IPC codes: H03L7