LSI automated design system and method

Abstract: To achieve an LSI automated design satisfying a required function and a required performance with the reuse of existing design data, there are disposed: library element memory means for storing, in the form of elements, existing design data (circuit data) together with design procedures (conversion information) thereof; element arrangement entering means for entering an element arrangement for achieving the desired function; library element specializing means for determining the functions of general-purpose elements; element synthesizing means for synthesizing an element having one function in which the functions of the elements are combined with one another; design data memory means for storing a variety of data; conversion instruction entering means for entering a design target level; conversion method selecting means for selecting a method of converting the elements to the target level, based on information relating to the design procedure of each of the elements; and design data converting means for executing the conversion of the elements according to the selected method.

Description: The present invention relates to a device and a method useful in an LSI automated design system capable of effectively utilizing design property. To achieve an LSI automated design system, a variety of CAD tools have been recently developed. However, when designing a circuit with the use of a plurality of CAD tools, it is required to prepare a dedicated converter for forwarding a design work since such CAD tools lack data conformity. Further, in order to use CAD tools in the respective optimum manners, it is required to know thoroughly a method of invoking each of the tools and interfaces among the tools. Thus, it disadvantageously takes much time to use CAD tools. As means for solving such a problem, there has been developed an integration system for LSI designing CAD tools which is called a framework. This framework has, in addition to a function of integrating CAD tools, a variety of functions including a function of managing design procedures (design processes) to navigate the execution of design tools according to a design methodology, a function of managing design data to be entered in and supplied from the design tools, a design data edition number managing function of managing the version and revision of design data groups. An example of the framework above-mentioned is shown in "A Process Scheduling Technique and an Inter-face Builder for CAD Tool Integration" by Toshiaki MIYAZAKI et al, Automated Design/Research Report No. 56-1, 1991, pp 1 to 8. In this example, the design procedures are managed by using a graphic interface called a design flow-chart editor. That is, the design procedures can be managed based on the relation between CAD tools set by the design flow-chart editor and input/output data thereof. Further, data designed by a designer can be readily utilized by another designer. To efficiently design a high-performance LSI, it is important to flexibly reuse existing design data to improve the design efficiency. As above-mentioned, the framework achieves an LSI automated design by managing design data and design procedures. However, an actual LSI is formed by combination of a variety of circuits and there is the optimum design procedure for each of the circuits. Accordingly, it is difficult to obtain a circuit satisfying a desired performance, merely by forwarding a design work with the application of design procedures previously prepared in the framework. In such an automated design with the reuse of existing design data using the framework, it is difficult to automatically generate a circuit satisfying a required performance since these existing design data to be reused are not related to information relating to the optimum design procedures for the design data. Lanneer, De et al., "An Object-Oriented Framework Supporting the full High-Level Synthesis Trajectory" in Proceedings of the IFIP WG 10.2 Tenth International Symposium on Computer Hardware Description Languages and their Applications, 22-24 April, 1991, Marseille, France, pages 301-320, discloses a CAD framework that supports the different tasks in high-level synthesis. The main parts are: a kernel to represent data-path structure, a unified behavioral data-model for representing real-time signal processing algorithms of all levels at the synthesis trajectory; and a library kernel for capturing architectural design knowledge. It is an object of the present invention to achieve an automated design of an LSI satisfying a required performance and a required function, with the reuse of existing design data. This object is solved according to the invention by a device according to claim 1 and by a method according to claim 5, respectively. Further objects and advantages of the present invention follow from the dependent claims. Figure 1a is a view illustrating the arrangement of a function design device in an LSI automated design system according to an embodiment of the present invention; Figure 1b is a view illustrating the arrangement of a design data converting device in the LSI automated design system according to the embodiment of the present invention; Figure 2 is a view illustrating the arrangement of hardware of the LSI automated design system in Figure 1a and Figure 1b; Figure 3 is a view illustrating the inner arrangement of a memory device in Figure 2; Figure 4 is a processing flow chart of the LSI automated design system in Figure 1a and Figure 1b; Figure 5 is a view illustrating the detail arrangement of circuit arrangement entering means in Figure 1a; Figure 6 is a detail flow chart of a circuit arrangement entry processing in Figure 4; Figure 7 is a detail flow chart of an element specializing processing in Figure 4; Figure 8 is a detail flow chart of an element synthesizing processing in Figure 4; Figure 9 is a view illustrating an element storing method in a library element memory means in the LSI automated design system in Figure 1a and Figure 1b; Figure 10 is a detail flow chart of a conversion instruction transmitting processing in Figure 4; Figure 11 is a processing flow chart of the design data converting device in Figure 1b; Figure 12 is a view illustrating the detail arrangement of a library element specializing means in Figure 1a; Figure 13 is a flow chart of a processing of storing elements in the library element memory means in the LSI automated design system in Figure 1a and Figure 1b; Figure 14 is a view illustrating an example of designing an element layout by the circuit arrangement entering means in Figure 1a; Figure 15a is a view illustrating the arrangement of a function design device in an LSI automated design system according to another embodiment of the present invention; Figure 15b is a view illustrating the arrangement of a design data converting device in the LSI automated design system according to the another embodiment of the present invention; Figure 16 is a processing flow chart of the LSI automated design system in Figure 15a and Figure 15b; Figure 17 is a detail flow chart of a circuit arrangement entering processing in Figure 16; Figure 18 is a detail flow chart of a design object generating processing in Figure 17; Figure 19 is a detail flow chart of a design object generating processing in Figure 18 when generating a plurality of design objects from the same element; Figure 20 is a detail flow chart of a design procedure executing processing in Figure 16; Figure 21 is a detail flow chart of a design procedure executing processing at each of steps 2004 and 2005 in Figure 20; Figure 22 is a detail flow chart of a processing for synthesizing a connection among design objects in Figure 16; Figure 23a is a view illustrating an example of elements stored in library element memory means in the LSI automated design system in Figure 15a and Figure 15b; Figure 23b is a view illustrating an example of design objects generated by the LSI automated design system in Figure 15a and Figure 15b; Figure 24a is a view illustrating a specific example of an element stored in the library element memory means in the LSI automated design system in Figure 15a and Figure 15b; Figure 24b is a view illustrating a specific example of a design object generated in the function design device in Figure 15a; and Figure 24c is a view illustrating a specific example of the final design object as converted by the design data converting device in Figure 15b. Detailed Description of Preferred Embodiments Fig. 1a and Fig. 1b are views illustrating the arrangement of an LSI automated design system according to an embodiment of the present invention. Fig. 1a shows a function design portion for achieving the desired function of a circuit using elements stored in a library, and Fig. 1b shows a design data converting portion for converting a circuit of which function design has been complete, into circuit data on the finally required level. In Fig. 1a, library element memory means 101 has a memory area 102 having areas respectively prepared for elements. The memory area 102 has (i) a library element circuit data memory 103 for storing element names, circuit data, function determining parameters, and information relating to the circuit arrangements of elements, and (ii) a library element conversion information memory 104 for storing information relating to design procedures for obtaining an optimum circuit, such as tools to be used, the order in which the tools are used, the conditions under which the tools are executed, and the like. Fig. 9 shows an example of a method of storing elements in the library element memory means 101. In the library element memory means 101, there are sets of elements classified by function. In a set, each of A, B, C, D, .... itself is a set of elements having a specific function. For example, each of A, B, C, D is a set of elements having a function serving as a CPU, a RAM, a ROM, a timer or the like. An actual circuit design can be carried out with the use of elements thus classified by function. In Fig. 9, a reference numeral 901 shows an example of a method of storing elements forming each element set. In this storing method, as the function of each element becomes more detailed, such element is stored in a lower rank. More specifically, as the function of each element is more specified, such an element is stored in a lower rank. An element on a lower rank, succeeds to all the functions of elements on upper ranks. Thus, by storing elements as succeeding to the functions of upper-rank elements, the retrieval of elements to be used at the design time, can be carried out at a higher speed. In Fig. 9, there is shown an example of an element 902 which has, in addition to a circuit data 103a, a variety of pieces of information required for a design such as information relating to a design procedure 104, information relating to the element arrangement 103b and information relating to parameters for determining the function of the element 103c. Accordingly, merely by giving the same conversion instruction to different elements, different design procedures can be respectively applied to the elements, so that the design can be automatically forwarded. The following will discuss a method of designing a circuit having a predetermined function (a function design method) using elements stored in the library element memory means 101. As shown in Fig. 1a, the library element circuit data memory 103 sends the lists of element names, information relating to the arrangement of each element and information relating to parameters for determining the function of each element, to circuit arrangement entering means (element arrangement entering means) 105 through a signal line 1. Based on the information thus sent, the circuit arrangement entering means 105 selects elements required for achieving a desired circuit, and sets information for determining a function to the parameter information of each of the elements thus selected. Also entered to the circuit arrangement entering means 105 is information relating to design constraints such as working frequency, circuit area and the like required for each element. Also, as to the layout of the elements, disposition places are specified with the floor plan taken into consideration. Out of the information thus set, the information relating to design constraints is stored in design constraint memory means 108 through a signal line 5, while the information relating to the names of selected elements and the information relating to the disposition places of the elements are stored in circuit arrangement information memory means 109 through a signal line 4. With the processings above-mentioned, there is finished setting the information required for achieving a desired circuit using the present system. Fig. 14 shows a design example of element layout specified in the circuit arrangement entering means 105. Each of A, B, C, D, E is an element having a specific function. The outer frame represents the contour of the LSI to be formed at the time when the design thereof will be actually finished. The disposition of each element is related to floor plan information of each element in an actual design. The size of each element in Fig. 14 is related, as it is, to the area of each element on the LSI. It is therefore possible to estimate the area of the LSI. By library element specializing means (design data specializing means) 106, the design data of general-purpose elements are to be converted into circuit data of which functions have been determined. Here, based on information relating to each of the names of elements forming the circuit sent through a signal line 3, a circuit data corresponding to each of the elements is taken out from the library element circuit data memory 103 through a signal line 2, and the circuit data thus taken out is converted, based on the element function determining information sent through the signal line 3, into a circuit data of which function has been specialized. Such function specialization of the circuit data of a library element, is carried out on all the elements forming the circuit. By element synthesizing means 107, there is to be generated a circuit element which satisfies the connection relation among all the elements forming the circuit. Here, sent to the element synthesizing means 107 are (i) information relating to the elements forming the circuit through a signal line 8, (ii) the specialized circuit data generated by the library element specializing means 106 through a signal line 7 and (iii) information relating to a method of converting the circuit data in order to unify the levels of the circuit data, through a signal line 6. Then, the element synthesizing means 107 retrieves information relating to input/output of all the elements forming the circuit, extracts the connection relation among all the circuit data based on the information thus retrieved, and generates a circuit element satisfying the connection relation. Then, the specialized circuit data sent through the signal line 7 and the circuit data generated by the element synthesizing means 107 are stored in circuit data memory means 110 through a signal line 9. With the processings above-mentioned, there are finished the function design of the desired circuit and the specializing processing of the circuit data. All the circuit data memory means 110, the design constraint memory means 108 and the circuit arrangement information memory means 109 may be made in the form of single memory means, i.e., design data memory means 111. In the design data converting portion in Fig. 1b, there is to be executed a processing of converting the circuit of which function design has been complete, to circuit data on the finally required level (target level). In conversion instruction entering means 112, there are entered a conversion instruction and the names of elements to which the conversion instruction is to be given. Then, the conversion instruction which specifies a target level of conversion, and the element names are sent to conversion instruction transmitting means 113 through a signal line 10. Based on the specified element names sent through the signal line 10 and information relating to the circuit arrangement sent from the circuit arrangement information memory means 109 through a signal line 12, the conversion instruction transmitting means 113 retrieves all lower-rank elements forming each of the specified elements. Then, the conversion instruction transmitting means 113 transmits the names of all the elements thus retrieved and the conversion instruction sent through the signal line 10, to conversion method selecting means 114 through a signal line 16. As to elements which have not been stored in the library element memory means 101, the conversion instruction and the names of such elements are sent to the conversion method selecting means 114 through a signal line 15. The conversion method selecting means 114 which has received the conversion instruction and the element names through the signal line 15, then receives (i) the information relating to the layout positions of the elements from the circuit arrangement information memory means 109 through a signal line 11, (ii) the information relating to design constraints from the design constraint memory means 108 through a signal line 13, and (iii) conversion information for the elements which have not been stored in the library element memory means 101, the conversion information being sent, through a signal line 17, from out-of-storage element conversion information memory means 118 in the library element memory means 101. Based on the pieces of information thus received, the conversion method selecting means 114 then determines the optimum tools for element conversion and parameters to be set when the tools are used, and selects the optimum converting means. The element names and information relating to parameters to be set when the tools determined by the conversion method selecting means 114 are used, are sent to circuit data converting means (design data converting means) 115 selected by the conversion method selecting means 114 through a signal line 19. Also, the circuit data corresponding to the specified elements are sent to the circuit data converting means 115 through a signal line 20. By operating the tool in the circuit data converting means 115 on the circuit data with the use of the parameters sent through the signal line 19, the circuit data can be converted into circuit data on a desired level. Further, the conversion method selecting means 114 receives (i) the names of elements forming specified elements and the conversion instruction given to these elements through the signal line 16, (ii) the information relating to design constraints from the design constraint memory means 108 through a signal line 14, and (iii) element conversion information of the elements forming the specified elements through a signal line 18. Based on the pieces of information thus received, the conversion method selecting means 114 determines tools and parameters which are optimum for converting the elements into data on the level specified by the conversion instruction, and the conversion method selecting means 114 selects the optimum converting means for the elements. The circuit data converting means 115 selected by the conversion method selecting means 114, receives (i) the name of an element to be converted and information relating to parameters to be set for a tool to be used for converting the element in the optimum manner, through a signal line 21, and (ii) the circuit data corresponding to the element to be converted through a signal line 20. By operating the tool in the selected circuit data converting means 115 on the circuit data with the use of the parameters sent through the signal line 21, the element can be converted into circuit data on a desired level. The circuit data converted by the circuit data converting means 115, are stored in circuit data memory means 117 through a signal line 22. According to the processings above-mentioned, without special attention paid on the circuit data, the designer can obtain circuit data having a desired function on a desired level, merely by combining elements stored in the library element memory means 101 to carry out a function design and by specifying a target level. It is noted that the circuit data memory means 110 and 117 may be made in the form of single memory means, and that the circuit arrangement information memory means 109, the design constraint memory means 108 and the circuit data memory means 110, 117 may be made in the form of single memory means, i.e., design data memory means 111. Fig. 2 is a view illustrating the arrangement of hardware of the LSI automated design system in Fig. 1a and Fig. 1b. This hardware arrangement is adapted to execute a circuit design processing shown in Fig. 4. In Fig. 2, there are shown an input device 201, a processing device 202, an output device 203 and a memory device 204. The input device 201 is adapted to enter, to the processing device 202, (i) circuit data such as function descriptions, logic circuits, layout data and the like which are required for designing a desired circuit and which are to be stored in an element library, and (ii) information relating to a design method for each circuit data and information relating to the circuit arrangement required for designing the desired circuit. The output device 203 is adapted to supply a circuit which has a function identical with that of the circuit entered thereinto, and which is formed by actually existing elements. The processing device 202 is adadpted to execute a variety of processing programs stored in the memory device 204 for executing circuit design processings such as conversion of the entered design circuit into circuit data on a desired level. Examples of the input device 201 include a keyboard, a card reader, a schematic entry system, a file and the like. Examples of the output device 203 include a character display, a graphic display, a plotter, a file and the like. Fig. 3 is a block diagram illustrating the inner arrangement of the memory device 204. Conversion method memory means 301 contains a variety of processing methods for an LSI design. Library element memory means 302 (101 in Fig. 1a and Fig. 1b) contains elements to be used for an LSI design, together with circuit data, design methods and other information required for a circuit design. Design data memory means 303 (111 in Fig. 1a and Fig. 1b) contains design results such as circuit data, design constraints, LSI circuit arrangement and the like which have been generated in the course of an LSI design. Fig. 4 shows a processing flow chart of the LSI automated design system having the arrangement above-mentioned. The following will discuss the entire operation of the system according to the flow chart. At a circuit arrangement entering step 401, circuit elements required for achieving the desired function are selected from the elements stored in the library element circuit data memory 103 in the library element memory means 101, and there are entered information relating to design constraints required for achieving the desired function and information relating to the layout with the floor plan taken into consideration. At a design constraint storing step 402, there are stored, in the design constraint memory means 108, the elements entered at the circuit arrangement entering step 401 or information relating to design constraints for the entire circuit. At a circuit arrangement information storing step 403, the information relating to the circuit arrangement entered at the step 401 is stored in the circuit arrangement information memory means 109. At an element specializing step 404, there are replaced the parameters of the elements selected at the circuit arrangement entering step 401, and selected component elements based on the parameters, thus specializing the functions of the elements. At an element synthesizing step 405, there is synthesized an element for integrating the elements forming the circuit, based on (i) information relating to input/output of the elements specialized at the element specializing step 404 and (ii) information relating to the circuit arrangement stored at the step 403. At a circuit data storing step 406, there are stored, in the circuit data memory means 110, the circuit data specialized at the step 404 and the circuit data for connecting the circuit component elements which was synthesized at the step 405. At a conversion instruction entering step 407, there is entered a conversion instruction for converting the circuit thus designed, into data on a desired level. At a conversion instruction transmitting step 408, the conversion instruction entered at the step 407 is transmitted to the conversion method selecting means 114. At a conversion method selecting step 409, information relating to converting tools and information relating to parameters to be set when the tools are used, are determined based on the conversion instruction thus transmitted and information 104 (Fig. 1b) relating to conversion methods of elements to be converted. Also, based on the pieces of information thus determined, there is selected the optimum conversion method for each element. At a circuit data converting step 410, the circuit data stored at the step 406 are converted with the use of the conversion methods selected at the conversion method selecting step 409. At a circuit data storing step 411, the conversion results are stored in the circuit data memory means 117. With the steps above-mentioned, the LSI design is complete. The following will discuss a method of storing an element into the library element memory means 101 with refernce to Fig. 13. At an element entering step 1301, design data are to be entered. Here, there are collectively entered, as an element, a general-purpose circuit data, information relating to a method of designing such a circuit data, information relating to the arrangement of the circuit data and information relating to general-purpose parameters. At an element function analyzing step 1302, there is analyzed the function of the element entered at the element entering step 1301. At an element name determining step 1303, there is determined, based on information relating to the function of the element extracted at the function analyzing step 1303, the optimum element name which represents the function of the element. At a memory means analysing step 1304, the memory means 101 in which elements have been already stored, is analyzed. Then, there is extracted information relating to the storage arrangements of the elements already stored therein. Each of the storage arrangements thus extracted has a rank structure according to a function. As an element has a more detailed function, the element is stored in a lower rank. At an element storing position determining step 1305, the name determined at the element name determining step 1303 is compared with the information relating to the storage arrangements of the existing elements which was obtained at the memory means analyzing step 1304, and determines the storing position of the element entered at the element entering step 1301. At the final step 1306, the element is newly stored in the memory means at the storing position thus determined. According to the element storing method above-mentioned, elements can be retrieved at a high speed at the time of a design, and effective element selection can be made with the use of element names relating to functions. With reference to Figs. 5 and 6, the following will discuss in detail the arrangement and processing flow of the circuit arrangement entering means 105 in Fig. 1a. Fig. 5 is a view illustrating the detailed arrangement of the circuit arrangement entering means 105. As shown in Fig. 9, the library element memory means 101 contains design data in the form of elements and other information required for achieving an automated circuit design. In element retrieving means 501, the name of each element required, information relating to parameters for determining the function of the element and information relating to the arrangement of the element, are extracted from information sent to the element retrieving means 501, through a signal line 23, from the library element circuit data memory 103 of the library element memory means 101. The element name, the information relating to parameters and the information relating to element arrangement thus extracted, are sent to means for entering elements to be used 502 through a signal line 24. Based on the element names and the information relating to parameters sent through the signal line 24, the means 502 selects the elements required for designing a circuit which achieves the desired function. Information relating to the elements selected by the means 502, is sent to the circuit arrangement information memory means 109 through a signal line 25, to design constraint entering means 503 through a signal line 26 and to parameter entering means 504 through a signal line 27. More specifically, the element names, the information relating to the element arrangements and the information relating to the final element layout position sent through the signal line 25, are stored, as circuit arrangement information, in the circuit arrangement information memory means 109. The information relating to the element layout position specified at this time, serves as information relating to a circuit floor plan. The design constraint entering means 503 enters, to the elements sent through the signal line 26, design constraints which must be satisfied by the elements. Together with the element names, the information relating to the design constraints is sent to and stored in the design constraint memory means 108 through a signal line 28. To the elements and the information relating to the parameters for determining the functions of these elements sent through the signal line 27, parameter entering means 504 enters parameter information required such that the elements achieve the desired functions. The parameter information thus entered is then sent to the library element specializing means 106 through a signal line 29. Fig. 6 is a processing flow chart of the circuit arrangement entering means 105. At an element list retrieving step 601, the lists of elements stored in the library element memory means 101 are retrieved to extract the names of all elements, information relating to parameters for determining the function of each element and element arrangement information. At a step of entering elements to be used 602, elements required for forming a circuit having a desired function are selected based on the information extracted at the step 601. At a step of selecting an object to be processed 603, an element is selected, as an object to be processed, from the elements selected at the step 602. A parameter entering step 604, there are set function determining parameters to the parameter information which has been retrieved at the step 601 and which corresponds to the element selected at the step 603. At a parameter storing step 605, the parameters thus set are stored in the library element specializing means 106. At a design constraint entering step 606, there are entered design constraints which the element should satisfy for achieving a desired function thereof. At a design constraint storing step 607, the design constraints entered at the design constraint entering step 606, are stored in the memory means 108. At a circuit arrangement information storing step 608, the information relating to the arrangement of the element and the information relating to the final layout position of the element, are stored, as circuit arrangement information, in the circuit arrangement information memory means 109. At a step 609, it is judged whether or not all elements required for forming the circuit were selected. In the affirmative, the function design of the circuit is complete. In the negative, the sequence is returned to the step 603 where selection is made on an element which has not been selected yet. Then, the processings on and after the step 604 are carried out. With the processings above-mentioned, a circuit having a desired function can be designed by selecting elements as obtained from existing design data. Further, such a design can be made with no special attention paid on the contents of design data. With reference to Figs. 12 and Fig. 7, the following will discuss in detail the arrangement and processing flow of the library element specializing means 106 in Fig. 1a. Fig. 12 is a view illustrating the arrangement of the library element specializing means 106. Circuit data analyzing means 1201 analyses (i) the circuit data of elements to be specialized which are sent to the means 1201 from the library element memory means 101 through the signal line 2 and (ii) information relating to function determining parameters, and determines a method of operating function determining information (parameters) which is prepared for function specialization and which is entered to the means 1201 through the signal line 3. Here, there is selected a method of replacing the information set as parameters, or a method of selecting data to be used by the information set as parameters. Sent through a signal line 40 to selected parameter operating means 1202 are (i) circuit data to be specialized and (ii) parameter information for specializing functions with the use of data selected from the circuit data to be specialized. By operating the parameters on the circuit data, there is carried out specialization of the circuit data by selection of data to be used. Sent to replaced parameter operating means 1203 are (i) parameter information for determining functions by parameter replacement and (ii) circuit data in which portions of the functions have been specialized by the selected parameter operating means 1202, the parameter information and the circuit data being sent to the means 1203 through signal lines 41, 42, respectively. When the parameters of the circuit data are replaced with the parameter information sent through the signal line 41, the specialization of the circuit data is complete. As a result, there are obtained circuit data of which functions have been specialized, and the circuit data thus obtained are sent to the element synthesizing means 107 through a signal line 43. Fig. 7 is a processing flow chart of the library element specializing means 106. At a step 701, the circuit data of library elements to be specialized are entered. At a function setting information extracting step 702, the circuit data thus entered are analyzed, and there is determined a method of operating the function determining information (parameters) for function specialization, on the parameters of the circuit data of the elements. At a function determining information entering step 703, there is entered information for determining the function of the circuit data already set. At a step 704, the parameters set at the step 703 are operated on the circuit data entered at the step 701, thus generating circuit data which have no parameters and of which functions have been determined. With the processings above-mentioned, circuit data obtained by combination of general-purpose elements, can be converted into data of which functions have been determined and with which the design work can be forwarded. With reference to Fig. 8, the following will discuss in detail a processing flow of the element synthesizing means 107. At a circuit arrangement information entering step 801, there are entered (i) the relation among elements which are stored in the circuit arrangement information memory means 109 and which form a circuit to be designed, (ii) information relating to the layout positions of the elements and (iii) information indicating a circuit level at which synthesis is to be carried out. At a circuit data entering step 802, there are entered circuit data specialized by the library element specializing means 106. At a step of judging a synthesis level of circuit data 803, there is analyzed the information relating to the element synthesizing level which has been entered at the circuit arrangement information entering step 801. Then, according to the specified level, i.e., a function level, a logic level or a mask layout level, the subsequent processing flow is selected. It is now supposed that the mask layout level is specified. At a circuit data converting step 804, all circuit data entered at the circuit data entering step 802, are converted into circuit data on the mask layout level according to conversion information of the circuit data (information sent from the library element circuit data memory 103 through the signal line 6). At a step of extracting input/output pin information of circuit data 805, there is extracted information relating to the input/output pins of circuit data converted at the step 804. At an inter-element connection information forming step 806, there is formed information relating to the connection relation among the circuit data, based on the information relating to the input/output pins and the information relating to the circuit element arrangement. At a step 807, there is synthesized a circuit data containing (i) wirings satisfying the connection relation among the circuit data and (ii) a layout satisfying the information relating to the layout positions of the circuit data. Finally, at a circuit data storing step 815, the circuit data converted at the step 804 and the circuit data synthesized at the step 807, are stored in the circuit data memory means 110. It is now supposed that the logic level is specified. At a circuit data converting step 808, all circuit data entered at the circuit data entering step 802, are converted into circuit data on the logic level according to conversion information of the circuit data (information sent from the library element circuit data memory 103 through the signal line 6). At a step of extracting input/output pin information of circuit data 809, there is extracted information relating to the input/output pins of the circuit data converted at the step 808. At an inter-element connection information forming step 810, there is formed information relating to the connection relation among the circuit data, based on the information relating to the input/output pins and the information relating to the circuit element arrangement. At a step 811, there is synthesized, based on the information relating to the connection among the circuit data, a logic-level circuit data which satisfies the connection relation among the circuit data and which satisfies constraints relating to cirucit data fan-outs. Finally, at a circuit data storing step 815, the circuit data converted at the step 808 and the circuit data synthesized at the step 811, are stored in the circuit data memory means 110. It is now supposed that the function level is specified. At a step of extracting input/output pin information of circuit data 812, there is extracted information relating to the input/output pins of the circuit data, from all circuit data entered at the circuit data entering step 802. At an inter-element connection information forming step 813, there is formed information relating to the connection relation among the circuit data, based on the information relating to the input/output pins and the information relating to the circuit element arrangement. At a step 814, there is synthesized, based on the information relating to the connection among the circuit data, a function-level circuit data which satisfies the connection relation among the circuit data. Finally, at a circuit data storing step 815, the circuit data entered at the step 802 and the circuit data synthesized at the step 814, are stored in the circuit data memory means 110. According to the processings in Fig. 8 thus discussed, it is possible to form a circuit data for integrating the elements of a circuit as obtained by combining the elements which achieve the desired function of the-circuit. The circuit data thus formed are to be processed by the design data converting portion in Fig. 1b. With reference to Fig. 10, the following will discuss in detail the processing flow of the conversion instruction transmitting means 113. At a conversion instruction entering step 1001, there is entered a conversion instruction for setting a level of circuit data to which a circuit is to be converted. At a circuit arrangement information entering step 1002, information relating to the elements forming the circuit to be converted, is entered from the circuit arrangement information memory means 109 through the signal line 12. At a circuit component element retrieving step 1003, there are extracted the names of the elements forming the circuit to be converted. At a conversion instruction transmitting step 1004, a conversion instruction is transmitted to the element names thus extracted. At a judging step 1005, it is judged whether or not the conversion instruction was transmitted to all the elements. In the negative, the sequence is returned to the conversion instruction transmitting step 1004. The transmitting processing is continued until the transmission of the conversion instruction to all the elements is complete. Thus, the conversion instruction can be transmitted to all the elements. With reference to Fig. 11, the following will discuss in detail the entire processing flow of the design data converting portion in Fig. 1b. At a conversion instruction entering step 1101, there is entered, from the conversion instruction entering means 112, information indicating a data level on which circuit data are to be converted. At a aircuit arrangement information entering step 1102, there are entered, from the circuit arrangement information memory means 109, information relating to the elements forming the circuit and information relating to the layout positions of the elements. At a design constraint entering step 1103, there is entered, from the design constraint memory means 108, information relating to design constraints which should be satisfied for converting the circuit. At an element conversion information entering step 1104, there is entered, from the library element conversion information memory 104, element conversion information which corresponds to each of the elements forming the circuit to be converted. At a step of judging the level specified by a conversion instruction 1105, the conversion method selecting means 114 analyzes the conversion instruction entered at the conversion instruction entering step 1101 and judges whether the specified level is a logic level or a layout level. The subsequent processing method varies with the judgment result. It is now supposed that the conversion instruction specifies the layout level. At a conversion method determining step 1106, there is determined, in the conversion method selecting means 114, a circuit converting method based on the element conversion information entered at the element conversion information entering step 1104. At a circuit data entering step 1107, there are entered, from the circuit data memory means 110, circuit data corresponding to elements to be converted. At a circuit data converting step 1108, the circuit data converting method determined at the conversion method determining step 1106 is operated, by the circuit data converting means 115, on the circuit data entered at the circuit data entering step 1107. Accordingly, the circuit data are converted and there are ultimately carried out. processings of disposing and wiring the circuit data. At a circuit data storing step 1112, the circuit data or conversion result obtained at the circuit data converting step 1108, are stored in the circuit data memory means 117. It is now supposed that the conversion instruction specifies the logic level. At a conversion method determining step 1109, there is determined, by the conversion method selecting means 114, a circuit converting method based on the element conversion information entered at the element conversion information entering step 1104. At a circuit data entering step 1110, there are entered, from the circuit data memory means 110, circuit data corresponding to the elements to be converted. At a circuit data converting step 1111, there is operated, in the circuit data converting means 115, the circuit data converting method determined at the conversion method determining step 1109, on the circuit data entered at the circuit data entering step 1110. Accordingly, the circuit data are converted and there is ultimately carried out a processing of converting the circuit data into logic-level circuit data satisfying circuit data fan-out constrants. At a circuit data storing step 1112, the circuit data or conversion result obtained at the circuit data converting step 1111, are stored in the circuit data memory means 117. According to the processings in Fig. 11 thus discussed, it is possible to convert circuit data without no special attention paid on the circuit data level and the conversion method. When an object-oriented technology is employed in the LSI automated design system above-mentioned, elements can be reused in a more efficient manner. Fig. 15a and Fig. 15b show the arrangement of an LSI automated design system according to another embodiment of the present invention into which the object-oriented technology is introduced. Fig. 15a shows a function design portion for achieving a circuit having a desired function using elements stored in a library, and Fig. 15b shows a design data converting portion for converting a circuit of which function design has been complete, into circuit data on the finally required level. The function design portion in Fig. 15a and the design data converting portion in Fig. 15b are basically identical with those in Fig. 1a and Fig. 1b, respectively. In the system in Fig. 15a and Fig. 15b, elements stored in library element memory means 101 may be handled as objects, and such objects may be operated to carry out design processings. In Fig. 15a, library element memory means 101 has a memory area 102 having areas for respective elements (objects). The memory area 102 has (i) a library element circuit data memory 103 for storing element names, circuit data, function determining parameters and information relating to the circuit arrangements of elements, and (ii) a library element design procedure information memory 104 for storing information relating to design procedures for obtaining the optimum circuit, such as tools to be used, the order in which the tools are used, the conditions under which the tools are executed, and the like. The following will discuss a method of designing a circuit having a desired function (a function design method) using elements stored in the library element memory means 101. As shown in Fig. 15a, the library element circuit data memory 103 sends the lists of element names, information relating to the arrangements of elements, information relating to parameters for determining the functions of the elements, to element arrangement entering means 105 through a signal line 1. Based on the information thus sent, there are entered, in the element arrangement entering means 105, functions required for achieving the desired circuit. There is also entered, as design constraints, information relating to required working frequency, circuit area and the like. Thus, there are specified elements which satisfy the conditions above-mentioned. Elements are selected from the elements thus specified. When each of the elements thus selected is a general-purpose element, parameters for determining the function thereof are set. As to the layout of the elements, too, the disposition places are specified with the floor plan taken into consideration. Of all the pieces of information thus set, the information relating to design constraints is stored in design constraint memory means 108 through a signal line 5, and the information relating to the selected element names and the information relating to the disposition places of the elements, are stored in circuit arrangement information memory means 109 through a signal line 4. With the processings above-mentioned, there is finished setting the information required for achieving the desired circuit with the use of the system. With the use of each of general-purpose elements stored in the library element memory means 101, design object generating means 120 generates a design object having (i) circuit data of which function has been determined and (ii) information relating to the design procedure and rank structure thereof. Here, based on (i) information relating to each of elements used for forming the circuit and (ii) information relating to parameters given to each of the elements forming the circuit, both pieces of information being sent through a signal line 3, a circuit data corresponding to each of the elements is taken out from the library element circuit data memory 103 through a signal line 2. Based on the information sent through the signal line 3, the circuit data thus taken out is converted into a circuit data of which function has been specialized. Further, information relating to design procedure and the like stored in the library element memory means 101, is combined with each specialized circuit data to form a design object. The design object is stored in design object memory means 122 through a signal line 51. Generation of such a design object from a library element, is carried out to all the elements forming the circuit. Then, an object for connecting design objects to one another, is to be synthesized in design-object connection synthesizing means 121. In the synthesizing means 121, there is generated a design object which satisfies the connection relation among all the elements forming the circuit. More specifically, the synthesizing means 121 receives (i) information relating to the elements forming the circuit from the circuit arrangement information memory means 109 through a signal line 8, and (ii) information relating to input/output of the circuit data of each of the objects generated by the design object generating means 120, through a signal line 50. Based on the pieces of information thus received, the synthesizing means 121 extracts the connection relation among all the circuit data and generates a design object which satisfies the connection relation. The design object thus generated is stored in design object memory means 122 through a signal line 52. With the processings above-mentioned, there are finished the function design and the generation of design objects for the desired circuit. All the design object memory means 122, the design constraint memory means 108 and the circuit arrangement information memory means 109 may be made in the form of single memory means, i.e., design data memory means 111. The design data converting portion in Fig. 15b is adapted to execute a processsing of converting a circuit of which function design has been complete, into circuit data on the finally required level (target level). In design target entering means 123, a design target serving as a target to be processed is entered to design objects serving as objects to be designed. The design target and the names of the design objects serving as objects to be processed, are sent to design procedure executing means 125 through a signal line 53. There are instances where a design object serving as an object to be processed has lower-rank design objects. In such a case, based on (i) the name of the design object serving as an object to be processed which is sent through the signal line 53 and (ii) information relating to the circuit arrangement sent from the circuit arrangement information memory means 109 through a signal line 54, the design procedure executing means 125 retrieves all lower-rank design objects forming the design object so that all lower-rank design objects are also to be processed. Further, the design procedure executing means 125 receives (i) information relating to the layout positions of elements from the circuit arrangement information memory means 109 through the signal line 54 and (ii) information relating to design constraints from the design constraint memory means 108 through a signal line 55. Based on the pieces of information thus received, the design procedure executing means 125 generates information for properly executing design procedures on the design objects in the optimum manners. Further, the design procedure executing means 125 receives, through a signal line 57, information relating to real design procedure, such as tools to be used for actually executing the design procedures for the design objects serving as objects to be processed, parameters to be set when the tools are used, the order in which the tools are used, and the like. According to the real design procedure, a processing is executed on each design object, and the circuit data of each object sent through a signal line 56 are converted and verified. In particular, when a design object serving as an object to be processed has lower-rank design objects, the design procedure is executed also on each of the lower-rank design objects. For each of the lower-rank design objects, too, the real design procedure is sent through the signal line 57. Accordingly, the optimum design procedure is also executed to each of the lower-rank design objects. The circuit data thus converted by the design procedure executing means 125 are stored, as one circuit data of a design object serving as an object to be processed, in design object memory means 124 through a signal line 58. With the processings above-mentioned, the designer can obtain circuit data on a desired level having a desired function, or verification results without special attention paid on the circuit data and the design procedures, merely by combining elements stored in the library element memory means 101 to carry out a function design and by specifying a design target serving as a target level. The design object memory means 122, 124 may be made in the form of single memory means. The design object memory means 122 may be different from the design object memory means 124. In such a case, however, it is required to clarify the relation among objects. Fig. 16 is the processing flow chart of the LSI automated design system in Figs. 15a and Fig. 15b. The following will discuss the entire operation of the system according to this flow chart. At a circuit arrangement entering step 1601, there are selected circuit elements required for achieving the function of a desired circuit. Also, there are entered design constraints required for achieving the desired function and information relating to the layout with the floor plan taken into consideration. Further, there are generated, from the elements thus selected, design objects based on which a subsequent design proceeds. By combining such design objects, a function design is to be achieved. At a design constraint storing step 1602, the design constraints entered at the step 1601, are stored in the design constraint memory means 108. At a circuit arrangement information storing step 1603, the information relating to the circuit arrangement entered at the step 1601, is stored in the circuit arrangement information memory means 109. At a design object storing step 1604, the design objects generated at the step 1601, are stored in the design object memory means 122. At a design object connection generating step 1605, there is generated a design object satisfying the connection relation among the design objects generated at the step 1601 such that data can be communicated among these design objects. On the design objects thus generated, a predetermined processing is to be carried out to forward a circuit design. At a design target entering step 1606, there is entered a design target serving as a target to be processed for the design objects. At a design procedure executing step 1607, design procedures corresponding to the design target are executed. Here, a processing is executed by applying the real design procedure of each design object to the design target thus entered. At a design object storing step 1608, the processing results obtained at the step 1607 are stored as parts of the design objects. With the processings above-mentioned, there can be achieved an LSI design using library circuit elements. The following will discuss in detail each of the circuit arrangement entering step 1601, the design object connection generating step 1605 and the design procedure executing step 1607. Fig. 17 is the detail flow chart of the circuit arrangement entering step 1601 in Fig. 16. First, there are to be selected elements required for achieving a desired function. In this connection, at an element list retrieving step 1700, there are retrieved elements prepared for a design. At a function entering step 1701, there are entered the functions of the elements required for a circuit to be designed, thus further specifying elements to be selected. At a design constraint entering step 1702, there is entered information relating to the design constraints and the performance to be achieved by the specified elements. This further specifies elements to be selected. At an element selecting step 1703, there are selected elements to be used in the design, from the elements specified by the steps above-mentioned. Then, design objects are to be generated from the selected elements. At a step 1704, there are entered parameters for determining the actual functions of the elements selected at the step 1703. Accordingly, the elements selected at the step 1703, become elements of which functions have been determined. At a step 1705, there is entered information relating to the layout of the elements of which functions have been determined, such layout being determined with the floor plan taken into consideration. At a step 1706, design objects are generated from the elements selected based on the pieces of information above-mentioned. At a step 1707, it is finally judged whether or not there were entered all the elements required for achieving the desired function. In the negative, the sequence is returned to the step 1701, where there are entered such functional elements, successively. When the entry of information of all the required elements is finished, the circuit arrangement entering processing is complete. The following will discuss in more detail the processing at the design object generating step 1706 with reference to Fig. 18. There are instances where the elemens selected at the step 1703 include elements each of which is designed in a rank structure. Accordingly, at a step 1801, it is judged whether or not each of the selected elements is designed in a rank structure and has lower-rank elements for which design objects have not been generated. In the affirmative, at a step 1802, there is generated a lower-rank design object from each of lower-rank circuit elements. By repeating the steps 1801 and 1802, there are generated lower-rank design objects from all the lower-rank elements of the selected elements. After it has been made sure at the step 1801 that there are no lower-rank elements for which design objects have not been generated, the sequence proceeds to a step 1803 where there are generated design objects of the selected elements themselves. Thus, there are finished the generation of design objects from the selected elements and design objects from the lower-rank elements forming such selected elements. When a lower-rank circuit element is further desinged in a rank structure, such an element is regarded as a selected element and the processings above-mentioned are repeated in a recursive manner. Thus, predetermined all design objects are automatically generated. Fig. 19 is a detail flow chart of each of the design object generating steps 1802, 1803 when a plurality of design objects are generated from the same element. At a step 1901, there is obtained the number N of design objects to be generated. There are instances where a plurality of design objects are generated from the same element, because different design objects are generated dependent on differences among function determining parameters, or because there are used a plurality of objects having the same function. At a step 1902, an initial value 1 is set to a variable i. At a step 1903, the name of the ith design object is determined. It becomes possible to differentiate, by such names, design objects generated from the same element. At a step 1904, there is generated a design object having the name determined at the step 1903. In the design object at this stage, there are stored only information relating to a design procedure and information relating to a rank structure. At a step 1905, data of the design object are generated. Here, a data file of the element is changed according to function determining parameters, causing the data file to be data of the design object. Such data are made as a part of the design object, together with the information relating to the design procedure which has been previously stored. At a step 1906, "1" is added to the variable i. At a step 1907, judgment is made on the size of the variable i. until the variable i becomes greater than the number N of design objects to be generated, there are repeated object generating steps on and after the step 1903. According to the processings in Fig. 19 thus discussed, a plurality of design objects can be generated from the same and single element. This achieves an efficient function design and miniaturization of the design data memory means. It is therefore possible to automatically reuse existing elements, while such element reuse has been manually made in prior art. Fig. 23a shows an example of an element stored in the library element memory means 101, and Fig. 23b shows an example of a design object generated from the stored element. Fig. 23a shows an example of a circuit element designed in a rank structure. A circuit element A 2301 has a certain function, and has lower-rank circuit elements B, C, D. Further, the lower-rank circuit element C has lower-rank circuit elements E, F. Each of the circuit elements has information relating to circuit data, design procedure, lower-rank circuit elements and function determining parameters. Particularly, as to the information relating to the circuit data, each circuit element has areas for storing circuit data for each of the function, logic and layout levels. However, it is not required that all the data are necessarily being prepared. According to the arrangement above-mentioned, when the circuit element A is selected, it means that there are also selected the lower-rank circuit elements B, C, D, E, F which form the circuit element A. It is intended to design a circuit satisfying a desired function by combining elements each having such an arrangement. Fig. 23b shows an example where a design object is generated from the circuit element A in Fig. 23a at the step 1706 in Fig. 17. A design object A1 2301a in Fig. 23b, is formed from the circuit element A 2301, and has lower-rank design objects B1, B2, C1, D1. Further, the lower-rank design object C1 generated from the lower-rank circuit element C, has lower-rank design objects E1, E2, E3, F1. Each of the design objects has information relating to circuit data of which function has been determined, design procedure, and lower-rank design objects. As apparent from the foregoing, a design object generated from a circuit element, succeeds to the information relating to the rank structure, the circuit data and the design procedure of the circuit element. As to the circuit data, it is possible to store the function-, logic- and layout-level circuit data generated at the design procedure executing step 1607 in Fig. 16, in the storage areas for the circuit data on the respective levels of each design object. In fact, there are instances where a plurality of design objects are generated from one circuit element. Such an example is shown as follows. The design objects B1 2302a, B2 2302b are generated from the circuit element B 2302, and the design objects E1 2305a, E2 2305b, E3 2305c are generated from the circuit element E 2305. Each of circuit elements or design objects, has information relating to the one-rank lower circuit element or design object. Accordingly, when an upper-rank element is selected, it is possible to retrieve all lower-rank elements forming such an upper-rank element with the use of such rank information. Fig. 22 is a detail flow chart of the design-object connection generating step 1605 in Fig. 16. At a circuit arrangement information entering step 2201, there is entered, from the circuit arrangement information memory means 109, information relating to the design objects forming the circuit. At a design object selecting step 2202, there is selected, from the design objects forming the circuit, each of design objects which are required to be connected and integrated. At a step 2203, it is judged whether or not the selection of all required design objects was complete. In the negative, the sequence is returned to the step 2202, where each of necessary design objects is to be selected. In the affirmative, the sequence proceeds to a step of extracting input/output information of each design object 2204. At the step 2204, there is extracted information relating to input/output of all design objects selected from the design objects generated by the design object generating means 120. At a step 2205, there is generated, based on the information thus extracted, a design object for connecting the selected design objects. Fig. 20 is a detail flow chart of the design procedure executing step 1607 in Fig. 16. At a step 2001, there are selected objects to which design procedures are executed. Here, it is possible to select all the design objects forming the circuit, individual design objects or lower-rank design objects. At a step 2002, there is entered a design target serving as a target to be processed. The design target to be entered, refers to the final data level when a design processing is forwarded, and to information indicating a design level of verification when a verifying processing is executed. According to the information thus entered, design procedures are to be executed on objects. At a step 2003, it is judged whether or not a design object serving as an object to be processed has lower-rank design objects to which design procedures have not been executed. In the affirmative, at a step 2004, design procedures are executed on lower-rank design objects. By repeating the steps 2003, 2004, there can be finished the execution of the design procedures on (i) the design objects serving as objects to be processed and (ii) the lower-rank design objects forming each of the design objects. At this time, when any of the lower-rank design objects further has lower-rank design objects, the last-mentioned lower-rank design objects are regarded as design objects to be processed, and the step 2006 is repeated in a recursive manner at the steps 2004. Thus, design procedures can be executed on all the design objects forming the design objects serving as objects to be processed. With the processings above-mentioned, merely by setting the design procedure to an upper-rank design object, design procedures can be executed on all the design objects forming such an upper-rank design object. Fig. 21 shows a detail flow chart of the design procedure executing processing at each of the steps 2004, 2005 in Fig. 20. Each design object has a real design procedure indicating tools to be actually used, parameters with which tools are used, the order in which tools are applied, and the like, in order to achieve the design target entered at the step 2002. Accordingly, at a step 2102, such a real design procedure is acquired. At a step 2102, the real design procedure thus acquired at the step 2102, is executed. It is therefore possible to obtain circuit data on a desired level without no special attention paid on the design data and the optimum design procedure of each design object. When the design target entered at the step 2002 refers to a verification level, each real design procedure includes (i) a design procedure according to which data are converted to data on the level at which verification is conducted, and (ii) procedure for giving, to verifying tools, information indicating where circuit data to be verified are located. With reference to Figs. 24a to 24c, the following will discuss a specific example of an LSI design using the LSI automated design system in Fig. 15a and Fig. 15b. In Fig. 24a, a circuit element A (2401) is one of the elements stored in the library element memory means 101. The circuit element A has (i) a function description serving as circuit data in the form of parameters, as shown at 2402, (ii) information serving as conversion information relating to parameters to be set for determining a function, as shown at 2403, and (iii) information relating to design procedure as shown at 2404. This element A is adapted to be selected by the element arrangement entering means 105, and a design object is to be generated therefrom. When parameters are given to the parameter information at 2403, there is generated, as shown in Fig. 24b, a design object A (2405) of which function has been determined. This design object A has, as logic-level circuit data, (i) a function description 2406 of which function has been determined and which has been generated by operating parameters on the function description 2404, and (ii) a design procedure 2407 according to which the data are converted. In this example, "15" is set to a parameter variable NUM to control the bit width and the number of repeat times. While disposing this design object with the floor plan taken into consideration as shown in Fig. 14, the design is forwarded. Then, when a conversion instruction is given to the design object A, there is executed a processing of converting the design object A into actual circuit data. Fig. 24c shows a design object conversion result 2501 obtained when the design object A receives a conversion instruction of converting data into layout data. In fact, the processing is executed by selecting the design object A on a display on which the layout in Fig. 14 is displayed, and by giving a target level of layout to the design object A. The processing is to be executed on the function description 2406 according to the design procedure set at 2407. First, a logic synthesizing tool A is operated on the function description 2406 (2502) under the conditions that the area is minimized. There is thus generated a logic diagram shown at 2503. Then, an automatic layout generating tool B is operated on this logic diagram data 2503 under the conditions that priority is given to wiring of clock lines, thus generating layout data 2504. Thus, merely by selecting elements, giving parameters for achieving a desired function and setting the final target, the desired circuit can be designed without special attention paid on circuit data in the course of the design work. Further, the generated data become circuit data satisfying the desired performance by reusing the optimum design procedures.

Claims: An LSI automated design system comprising a design data converting device with element memory means (101) for collectively managing and storing, in the form of elements, design data and design procedure information relating to the conversion of said elements; characterized in that said design data converting device further comprises: design data memory means (111) for storing (i) information relating to an element arrangement for achieving a desired function, said information includes layout position information and design constraint information of said element arrangement, and (ii) corresponding design data of which function design has been completed; conversion instruction entering means (112) for entering a conversion instruction which specifies a target level on which said design data are to be converted; conversion method selecting means (114) for selecting conversion design procedures based on (i) said design procedure information relating to the conversion of elements in said element memory means and (ii) said conversion instruction relating to said target level entered by said conversion instruction entering means, and for adapting said conversion design procedures to operate on said design data in said design data memory means; and design data converting means (115) for converting, according to said design procedures selected by said conversion method selecting means, said design data in said design data memory means into design data on said target level specified by said conversion instruction. An LSI automated design system according to claim 1, with said design data converting device further comprising conversion instruction transmitting means (113) for transmitting the conversion instruction entered by the conversion instruction entering means, to all design data forming each element to be subjected to said conversion instruction, whereby, when said element to be subjected to said conversion instruction is designed in a rank structure, said all design data are converted, based on the information relating to the element arrangement stored in the design data memory means, into design data on the target level specified by said conversion instruction. An LSI automated design system according to claim 1, wherein the element memory means (101) further has a function of storing information relating to design procedures for the conversion of out-of-storage design data, whereby, even though each element to be subjected to the conversion instruction entered by the conversion instruction entering means, is not stored in the element memory means, the conversion method selecting means selects a design procedure for conversion to design data on the target level specified by said conversion instruction, and the design data converting means carries out said conversion to design data on the target level according to said design procedure selected by said conversion method selecting means. An LSI automated design system according to claim 1, with said design data converting device further comprising: circuit arrangement entering means (105) for entering (i) an element arrangement for achieving a desired function using design data stored in said element memory means and (ii) information for determining the functions to be respectively achieved by design data specified by said element arrangement; design data specializing means (106) for specializing, according to said function determining information entered by said circuit arrangement entering means, said design data specified by said element arrangement; design data synthesizing means (107) for synthesizing a design data for connecting said design data specialized by said design data specializing means; wherein (i) said design data specialized by said design data specializing means and (ii) said design data synthesized by said design data synthesizing means are stored in said design data memory means (111). A method of operating an LSI automated design system comprising: a conversion instruction entering step (1101) of entering a conversion instruction which specifies a target level on which design data are to be converted; a conversion method selecting step (1105) of selecting conversion design procedures based on (i) design procedure information relating to the conversion of design data which is collectively managed and stored, in element memory means (101), said design data and said design procedure information being stored in the form of elements, and (ii) said conversion instruction relating to said target level entered at said conversion instruction entering step (1105), each of said conversion design procedures being adapted by conversion method selecting means to operate on said design data of which function design has been completed and which is stored in design data memory means (111) together with information relating to an element arrangement for achieving a desired function, said information relating to an element arrangement includes layout position information and design constraint information of said element arrangement, and a design data converting step (1111,1108) of converting, according to said design procedures selected and adapted at said conversion method selecting step (1105), said design data in said design data memory means (111) into design data on said target level specified by said conversion instruction. A method according to claim 5, further comprising a conversion instruction transmitting step (1004) of transmitting the conversion instruction entered at the conversion instruction entering step (1101), to all design data forming each element to be subjected to said conversion instruction, whereby, when said element to be subjected to said conversion instruction is designed in a rank structure, said all design data are converted, based on the information relating to the element arrangement stored in the design data memory means (111), into design data on the target level specified by said conversion instruction. A method according to claim 5, further comprising a step of previously storing (1301-1306), in the element memory means (101), information relating to design procedures for the conversion of out-of-storage design data, whereby, even though each element to be subjected to the conversion instruction entered at the conversion instruction entering step (1101), is not stored in the element memory means (101), there is selected a design procedure for conversion to design data on the target level specified by said conversion instruction and, there is carried out said conversion to design data on the target level, according to said design procedure thus selected. A method according to claim 5, wherein the design data converting step comprises the steps of: judging (1801) whether or not the design data of each of the elements specified by the element arrangement has lower-rank design data; and operating (1803) the design procedure on the design data of said specified element when said specified element has no lower-rank design data; or operating (1802) the design procedures on (i) the design data of said specified element and (ii) all lower-rank design data of said first-mentioned design data when said first-mentioned design data has said lower-rank design data. A method according to claim 5, further comprising the following steps: a circuit arrangement entering step (401,1601) of entering (i) an element arrangement for achieving a desired function using design data stored, in element memory means (101), together with design procedure information relating to the conversion of said design data, said design data and said design procedure information being collectively managed and stored in the form of elements, and (ii) information for determining the functions to be respectively achieved by design data specified by said element arrangement; a design data specializing step (404,1604) of specializing, according to said function determining information entered at said circuit arrangement entering step (401,1601), said design data specified by said element arrangement; a design data synthesizing step (405,1605) of synthesizing a design data for connecting said design data specialized at said design data specializing step (404,1604); and a design data storing step (1608) of storing (i) said design data specialized at said design data specializing step (404,1604) and (ii) said design data synthesized at said design data synthesizing step (405,1605).

Inventors: NISHIYAMA TAMOTSU, TOKUNOH SEIJ, TSUBATA SHINTARO, NISHIYAMA, TAMOTSU, TOKUNOH, SEIJ, TSUBATA, SHINTARO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1993
Main classification: G06F17
IPC codes: G06F17