Method of measuring the current of microcontroller memory cells and relative system

Abstract: A method of directly reading the current of cells (7, 8) of a memory (3) forming part of a microcontroller (1, 1') by performing a write operation of the cells and using the existing cell programming logic. For this purpose, the programming voltage supply line (16) is supplied with a low voltage (e.g. 1 V); the word line of the cell for reading is enabled; and a write instruction of a data item presenting a predetermined logic level (e.g. zero) is performed at the bit corresponding to the cell for reading. By providing an additional pass transistor (25) connected to each reference bit line (RBL) and an additional reference cell enabling line (REF-EN), the reference cells (8) may also be read directly.

Description: The present invention relates to a method of measuring the current of microcontroller memory cells and to a system adapted to carry out such method. As known, most single memories (i.e. integrated in a chip housing only the memory) present pins for measuring the current of the cells and on to which a voltage of roughly 1 V is forced directly at the measuring step for measuring the current of each cell. Such a method is extremely useful when checking and engineering the memory. At present, however, the above method is not applicable to microcontrollers featuring nonvolatile EPROM or flash-EEPROM memories, due to the impossibility in general of providing them with the numerous additional pins required, or of performing the cell reading function using the existing pins on the microcontroller, which already provide for diverse functions. Moreover, the same memory configuration may be used for designing various differently structured microcontrollers, so that a solution suitable for one is not necessarily suitable for others. EP-A-0 318 363 discloses a method of reading the current of cells of an EEPROM comprising the steps of supplying a current reading voltage to a program voltage supply line of the memory; performing a write instruction of a predetermined cell; and measuring the current flow through the predetermined cell, wherein the current reading voltage has a value lower than a write voltage and insufficient to write a cell. The article "A 512-kb Flash EEPROM Embedded in a 32-b Microcontroller" by Kuo et al., IEICE TRANSACTIONS, vol. E75-C, no. 4, April 1992, Tokyo, JP, pages 472-479 discloses the general architecture of a microcontroller, according to the preamble of claims 1 and 4. It is an object of the present invention to provide a method designed to overcome the aforementioned drawbacks, and which provides for directly reading the current of even microcontroller integrated memory cells. According to the present invention, there is provided a method of measuring the current of microcontroller memory cells, as claimed in Claim 1. According to the present invention, there is also provided a system comprising a microcontroller as claimed in Claim 4. Two preferred, non-limiting embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which: Fig.1 shows a block diagram of the architecture of a first embodiment of the microcontroller according to the present invention; Fig.2 shows a block diagram of a variation of the Fig. 1 microcontroller. In Fig.1, the microcontroller is indicated as a whole by 1, and, ignoring any elements not specifically relating to the present invention, substantially comprises a microcontroller processing unit 2; a memory array 3; and a memory address, supply and control logic unit 4 including a memory control register 5. Processing unit 2 may be of any known configuration and therefore requires no description herein. Memory array 3 is a nonvolatile EPROM, EEPROM or flash-EEPROM type, and comprises a number of pairs of cells 7, 8 arranged in rows and columns and connected to respective word lines WL and bit lines DBL, RBL. Word lines WL are connected to an address decoding stage 10 in turn connected to processing unit 2 over an address bus 11. The bit lines comprise a number of data bit lines DBL0 ... DBLn and a number of reference bit lines RBL0 ... RBLm connected to one another and respectively to cells 7 (each memorizing an elementary item or bit) and to cells 8 constituting the reference cells and generally consisting of virgin cells, i.e. which have never been written or erased. In known manner, each cell 7, 8 presents its control (gate) terminal connected to a respective word line WL; its drain terminal connected to a respective data or reference bit line DBL, RBL; and its source terminal grounded. Each pair consisting of a data bit line DBL and a reference bit line RBL is connected at one end to a sensing amplifier 12, the output of which is connected to data output line 13 of a data output bus DOB connected to processing unit 2. The other end of each pair of bit lines DBL, RBL is connected to logic unit 4. More specifically, each data bit line DBL is connected to one terminal of a pass transistor 15, another terminal of which defines a node 19 connected, via supply line 16 and a switch 17 formed by a MOS transistor, to a pin 18 supplied with programming voltage V PP . The control terminal of the transistor defining switch 17 is connected to processing unit 2 over a write enable line W-EN. The control terminal of pass transistor 15 is connected to the output of a two-input AND circuit 20 having one input connected to a data enable line D-EN, and the other connected, via an inverter 21, to line 22 of a data input bus DIB. Data enable line D-EN is connected to control register 5, which determines the logic level of the signal on data enable line D-EN on the basis of the content of a cell 23; while data input bus DIB is connected to processing unit 2. Each reference bit line RBL is connected to a terminal of a respective pass transistor 25, the other terminal of which is connected to node 19 and, hence, to supply line 16. The control terminal of pass transistor 25 is connected to the output of a two-input AND circuit 26 having one input connected to the output of inverter 21, and the other connected to a reference enable line REF-EN connected to a cell 27 of control register 5. Fig.1 also shows a programmable voltage source 30, and an ammeter or other current measuring element 31, both external to microcontroller 1 and connected to pin 18 for the reasons explained later on. For measuring the current of cells 7, 8 when checking or engineering microcontroller 1, use is substantially made of logic unit 4 already provided for programming cells 7, the only difference being the addition of a cell (27) in control register 5, pass transistor 25 and AND circuit 26, for also enabling measurement of the reference cell current. Programming a memory word (a group of cells 7 connected to the same word line WL) involves first erasing all the word cells (i.e. memorizing a logic "1") and then writing a logic "0" in the word cells specified by data input bus DIB and bit lines DBL by applying a high voltage (e.g. 5.5-7 V) to the drain terminal of the cells. The current of a specific cell 7 or 8 is measured in the same way, except that the voltage applied to the drain terminal of the cell for measurement is much lower than the programming voltage, typically 1 V. A cell is thus measured by writing the data cell or reference cell read bit into cells 23, 27 of control register 5, selecting a given pair of cells by means of the word lines and data input bus, applying 1 V to programming pin 18, and performing a write instruction (thus generating a high logic level on line W-EN and turning on transistor 17). For example, the data cell corresponding to bit N. 0 of an 8-bit word of address 2412 is read by simply writing the data cell enabling bit (logic "1") into cell 23 of control register 5, writing the disabling bit ("0") into cell 27, applying 1 V to pin 18 (by appropriately regulating source 30), and performing a write instruction with address 2412 and data 01111111. As a result, the cells connected to the word line of address 2412 are enabled; line 22 relative to the first bit presents a logic "0" which, inverted by inverter 21, results in a logic "1" at one input of AND circuit 20 driving pass transistor 15 connected to data bit line DBL0; the other input of AND circuit 20 is high, by virtue of being connected to data enable line D-EN connected to register 23; transistor 15 connected to DBL0 is on, thus enabling DBL0 to be supplied with 1 V; and the selected cell is supplied with current measurable by ammeter 31. Conversely, the reference cell with the same address indicated above is read in exactly the same way, except for the cell of control register 5. In this case, in fact, a logic "1" is memorized in cell 27 as opposed to 23, so as to enable reference enable line REF-EN, AND circuit 26 and pass transistor 25. If V PP pin 18 cannot be used (e.g. by virtue of already being used as a reset pin), the above configuration may be modified as shown in Fig.2 and described below. Microcontroller 1' in Fig.1 is substantially the same as 1 in Fig.1, so that any parts common to both are indicated using the same numbering system and with no further description. Microcontroller 1' presents a further so-called ADMA (Analog Direct Memory Access) pin 35 connected to programmable voltage source 30 and ammeter 31, and also to supply line 16 via a controlled switch 36 formed by a MOS transistor, the control terminal of which is connected over a read enable line A-EN to a cell 38 of control register 5'. Except for the addition of read enable cell 38, control register 5' is the same as 5 in Fig.1. The cell current of memory array 3 of microcontroller 1' is read in the same way as already described with reference to Fig.1, except that, when the data cell or reference cell read bit is written in cells 23, 27, ADMA read enable cell 38 is also written. Consequently, when 1 V is applied to pin 35 (as opposed to 18), and a write operation is performed at the specified address, the required cell is read via ammeter 31. The advantages of the method according to the present invention will be clear from the foregoing description. In particular, it provides for reading the cells of memories forming part of a microcontroller, and so checking the cells as formerly possible only for cells of single memories. Nor does the reading require the addition of a large number of pins. In the worst possible case in which none of the pins on the integrated device is available for performing the read function, only one additional pin (ADMA pin 35) is required. Also, very little additional space is required for implementing the read function, which simply involves the possible addition of a dedicated ADMA pin and ADMA enabling cell, and the addition of reference bit line pass transistor 25 and reference cell selection cell 27. Finally, the method according to the present invention involves no substantial change in the existing procedures of the microcontroller, direct reading of the current, as already stated, involving substantially no more than a write operation preceded simply by setting the ADMA enable and data or reference cell read enable bits, which may be performed as part of other microcontroller instructions. To those skilled in the art it will be clear that changes may be made to the method and architecture described and illustrated herein without, however, departing from the scope of the present invention. In particular, in the event an additional pin is provided or, at any rate, programming pin V PP is not employed for performing the current reading function, control register 5' as shown may be replaced by a more complex stage comprising a register for memorizing only two direct reading bits (in addition to the bits required for other memory 3 functions), and a logic unit, e.g. including a multiplexer, for ADMA read enabling, and enabling the data or reference cell relative to the same memory word bit. Moreover, the voltage applied to the gate terminal of the cells for reading may even be lower than the write voltage, for example equal to supply voltage V CC of the microcontroller, in which case, depending on whether a write instruction or direct reading is to be performed, processing unit 2 (which, in the configurations shown incorporates the write control logic) applies write voltage V PP (e.g. 12 V) or the direct reading voltage (e.g. supply voltage V CC = 5 V).

Claims: A method of measuring the current of cells (7,8) of a memory (3) forming part of a microcontroller (1, 1') comprising a memory array (3) including data cells (7) and reference cells (8), characterized in that the method comprises the steps of: selectively enabling a data enable line (D-EN) or a reference enable line (REF-EN) so as to selectively connect a program voltage supply line (16) to a predetermined data or reference cell (7, 8) whose current is to be measured; supplying a current measuring voltage to said program voltage supply line (16) of said memory (3), said current measuring voltage having a value lower than a write voltage and insufficient to write a cell; performing a write instruction of said predetermined data or reference cell (7, 8) of said memory; and measuring current flow through said predetermined data or reference cell. A Method according to claim 1, for a microcontroller (1) comprising a program pin (18), characterized in that said step of supplying a current reading voltage comprises the step of supplying said current reading voltage to said program pin (18); said step of performing a write instruction comprises the step of enabling a write switch (17) located between said program pin and said program voltage supply line (16); and said step of measuring current flow comprises the step of measuring current flow through said program pin. A method according to claim 1, for a microcontroller (1') comprising a program pin (18) and a direct memory access pin (35), characterized in that said step of supplying a current reading voltage comprises the step of supplying said current reading voltage to said direct memory access pin (35); said step of performing a write instruction comprises the step of enabling a write switch (36) located between said direct memory access pin (35) and said program voltage supply line (16); and said step of measuring current flow comprises the step of measuring current flow through said direct memory access pin. A system comprising a microcontroller (1, 1') including a memory array (3) having a plurality of data cells (7) and reference cells (8) connected to a respective data bit line (DBL) and reference bit line (RBL), said data bit line (DBL) being connected to a program voltage supply line (16), the microcontroller further comprising a control logic unit (4) including write means (W-EN, 16-22) for writing predetermined cells of said memory, characterized by voltage generator means (30) and current detecting means (31) connectable to said program voltage supply line, said voltage generator means (30) generating a current measuring voltage having a value lower than a write voltage and insufficient to write a cell and said current detecting means (31) directly detecting current flow in a selected data or reference cell (7, 8); and in that said control logic unit (4) further comprises: a first and a second pass transistor (15, 25) interposed between said program voltage supply line (16) and said data bit line (DBL), respectively said reference bit line (RBL); a data enable line (D-EN) and a reference enable line (REF-EN) connected to a control terminal of said first and second pass transistors (15, 25), respectively; and means (5, 20, 23, 26, 27) for selectively enabling said data enable line (D-EN) or said reference enable line (REF-EN) so as to selectively connect said program voltage supply line (16) to a predetermined data cell (7) or reference cell (8). A system according to claim 4, characterized in that said means (5, 20, 23, 26, 27) for selectively enabling comprises a first logic gate (20) having an output connected to the control terminal of said first pass transistor (15), a first input connected to said data enable line (D-EN) and a second input connected to a data address line (22); a second logic gate (26) having an output connected to the control terminal of said second pass transistor (25), a first input connected to said reference enable line (REF-EN) and a second input connected to said data address line (22); a storage element (23, 27) connected to said data and reference enable lines (D-EN, REF-EN) for storing enabling data and selectively enable said data or said reference enable line (D-EN, REF-EN). A system according to claim 4 or 5, characterized in that said microcontroller (1) comprises a program pin (18), and in that said voltage generator means (30) and current detecting means (31) are connected to said program pin. A system according to claim 4 or 5, characterized in that said microcontroller (1') comprises a program pin (18) and a direct memory access pin (35), and in that said voltage generator means (30) and current detecting means (31) are connected to said direct memory access pin (35). A system according to claim 7, characterized in that said control logic unit (4) comprises storage elements (38) connected to a direct read enable switch (36) interposed between said direct memory access pin (35) and said program voltage supply line (16).

Inventors: PEZZINI SAVERIO, PEZZINI, SAVERIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C16
IPC codes: G11C17, G11C29, G11C16, G06F15