Current limited power semiconductor device

Abstract: A current limit circuit for protection of an intelligent power switch includes a series circuit of a sense transistor (3) and a sense resistor (4) coupled to the power semiconductor transistor switch (1) so that the sense resistor current (I s ) is a fraction of, and is proportional to, the power transistor current (I p ). A pull-down transistor (6) is coupled to the control electrode of the power transistor switch (1). A feedback circuit including a series connections of a diode-connected transistor (12) and a reference voltage source (14,15) is coupled between the sense resistor (4) and the control electrode of the pull-down transistor (6). The feedback circuit produces a voltage level shift and the circuit provides an accurate limit on the power transistor (I p ) independent of any variations in threshold voltage.

Description: BACKGROUND OF THE INVENTION The invention relates to a current limit circuit comprising: first and second terminals for supplying an operating voltage to the current limit circuit, a power transistor, means for connecting said power transistor and a load in series to said first and second terminals, a sense transistor and a sense resistor connected in a series circuit with the load to said first and second terminals such that the current flow through the sense resistor is proportional to the current flow through the power transistor, means for coupling the control electrode of the power transistor and a control electrode of the sense transistor to a signal input terminal of the circuit, and a further transistor connected between a control electrode of the power transistor and a point of reference potential, said further transistor being biased into cut-off below the current limit value set for the power transistor, a voltage drop being developed across the sense resistor proportional to the current flow in the power transistor which drives the further transistor into conduction when said voltage drop across the sense resistor exceeds a predetermined value, thereby to limit any additional current flow through the power transistor. A current limit circuit of this kind is known for example from the English-language abstract of JP-A-1-68005. Such circuits are useful for providing automatic protection of a power transistor or the like from damage caused by excessive currents flowing therein as a result of an overload condition, such as a short-circuit at the load. More particularly, the invention relates to a current limit circuit adapted to protect the power semiconductor device in a so-called "high side" Intelligent Power Switch (IPS or "smart power" switch). A "smart power" device or intelligent power switch is an integrated circuit in which control functions are provided by low voltage logic devices integrated along side of power semiconductor devices, such as power MOSFETs, together on a common chip. It is customary in known high side power chips to isolate the integrated low power components from the high power components on the chip by the provision of special diffusions or barrier layers of differing conductivity types or by the provisions of dielectric layers. The invention is particularly useful in automotive applications, but is not limited to this field of technology. In recent years there has been a dramatic increase in the use of semiconductor electronic systems in the automobile, such as in ignition/fuel control, switches for headlamps, monitoring of emissions and braking systems. All of these control functions require safe and reliable semiconductor devices for monitoring, logic and power control. A key component for these various automotive applications is an inexpensive and reliable intelligent power switch (IPS) that is able to drive high current loads (for example, up to 10A) such as headlights, solenoids and small electric motors. The IPS must be able to withstand a supply voltage of up to 60 volts and at the same time provide self protection against short circuits and excessive temperatures. A typical IPS device in an automotive electronics system requires an integrated circuit chip which combines 60 volt power components and both low voltage (5V to 12V) and high voltage (60V - 80V) logic components. A typical chip must have the intelligence to protect the switch against various potentially destructive conditions such as a short circuit to ground, a reverse battery and voltage surges due to inductive loads. The intelligent power switch device should also provide thermal shut down, rail-to-rail current limiting and should detect open load and over voltage conditions and provide an indication of any overload condition. The provision of these supervisory and safety features is complicated because of the wide variation of supply voltages, for example, from approximately 6V to 60V, and the varied nature of the fault conditions which may occur. A typical IPS chip consists of four main functional blocks, a gate control unit, a sensor block, a control logic and a power supply. In the case of a high side power switch, the gate control unit provides gate drive to the power switch by means of an oscillator/charge pump circuit. The sensor block contains voltage, current and temperature detectors in order to accurately monitor the condition of the intelligent power switch chip and the load. The control logic block diagnoses potential fault conditions and initiates the necessary corrective action. The power supply block contains precision analog circuits, such as a band-gap reference, so as to provide the necessary reference and bias voltages and currents for the chip. The total supply current flows to ground via a reverse-battery protection circuit. Various techniques have been proposed for limiting the current through a power transistor. One known circuit for providing current limit protection for a high side intelligent power switch is shown in Fig. 1 of the drawing. In this circuit a power switch 1, for example a power MOSFET element, is connected in series with a load resistor 2 between two terminals 31 and 32 which may be connected to a voltage source, for example a battery (not shown), the second terminal 32 being connected to ground. A second series circuit consisting of a sense MOSFET 3 and a sense resistor (R S ) 4 is connected between the first terminal 31 and a junction point 5 between the power MOS switch 1 and the load 2. An NMOS FET 6 is connected between the gate of the power MOS transistor 1 and the junction point 5. The gate of pull-down transistor 6 is connected to a junction point between the field effect transistor 3 and the sense resistor 4. The gates of the field effect transistors 1 and 3 are connected in common to a gate drive input terminal 7. A serious disadvantage of this current limiting scheme is the fact that the current limit value is determined essentially by the threshold voltage of the NMOS transistor 6, which voltage is subject to a wide variation due to variations in the manufacturing process of the IPS chip. In addition, a typical value of the threshold voltage (V th ) is 1V or more and this value produces too high a voltage drop across the sampling sense resistor 4 to provide accurate current mirroring between the field effect transistors 1 and 3. A known variation of the Fig. 1 current limiting power switch circuit includes a comparator connected between the junction point of sense FET 3 and sense resistor 4 and the gate of the pull-down NMOS transistor 6. In this variation, a first input of the comparator is connected to the aforesaid junction point, a second input is connected to a source of reference voltage, and its output is connected to the gate of the NMOS field effect transistor 6. A compensation capacitor of the order of 100 - 150 pF is connected between the comparator output and the drain of the NMOS transistor 6 in order to provide stability. The compensation capacitor is required because the load capacitance to be driven and formed by the gate capacitance of the power of the power MOSFET 1 is very large. This current limit circuit is therefore unattractive because of the chip area requirements and the stability problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide a fast, stable and accurate current limit circuit for protecting a high side intelligent power switch and one that is not subject to the disadvantages of the known intelligent power switch current limit circuits. A current limit circuit in accordance with the invention is characterized in that a feedback circuit is connected between a junction point of the sense transistor and the sense resistor and a control electrode of the further transistor, said feedback circuit including a series connection of a semiconductor device and a reference voltage source which together produce a voltage level shift. As a result, a sense resistor of very low resistance value can be used in series with the sense transistor, which in turn makes it possible for the power transistor and the sense transistor to effectively operate like a current mirror circuit, i.e. the current through the sense transistor is proportional to the current through the power transistor. This comes about because the voltage drop across the very small sense resistor is now negligible so that the power and sense transistors are effectively balanced. One embodiment of the invention is characterized in that said semiconductor device and said reference voltage source of the feedback circuit comprise a diode-connected field effect transistor and a reference resistor, respectively, and said current limit circuit further comprises, a source of reference current connected to said reference resistor and to one terminal of the load, and a bias current source coupled to said first terminal and to a second junction point between the reference resistor and one terminal of the semiconductor device. Since the reference voltage (V r ) is now well defined, we are able to produce an accurate current limit independent of threshold voltage variations. In another embodiment of the invention, a Proportional To Absolute Temperature (PTAT) current source can be used as the reference current source. As a result, the reference voltage drop V r can decrease with an increase in temperature thereby to provide a current limit for the circuit which decreases with increasing temperature so as to better protect the semiconductor power switch. Still another embodiment of the invention is characterized in that said further transistor and said semiconductor device each comprise a field effect transistor and said reference voltage source comprises a bipolar transistor connected in series with a reference current source between the first and second terminals and with a base of the bipolar transistor connected to the field effect transistor semiconductor device, and with the gate of the field effect further transistor connected to a junction point between the bipolar transistor and the reference current source, whereby the current limit value for the power transistor decreases as the temperature increases. A further embodiment of the invention provides a power limiting function for the circuit. This embodiment is characterized in that the semiconductor device comprises a field effect transistor having its gate connected to its drain and its source connected to the sense resistor, said circuit further comprising; a voltage threshold device connected between the first terminal and the gate of the field effect transistor, said voltage threshold device becoming conductive upon an increase in voltage at said first terminal above a given voltage determined by the desired power limit values so that an increased current flows through the field effect transistor so as to increase the gate/source voltage of the field effect transistor as said first terminal voltage increases, whereby the current limit value is reached with a lower value of sense voltage across the sense resistor thereby to provide said power limit function. BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present invention and of the above described and other features and advantages thereof will become apparent from the following detailed description when read in connection with the accompanying drawing, in which: Fig. 1 shows a known current limit circuit; Fig. 2 shows a first embodiment of an intelligent power switch incorporating the current limit circuit of the invention; Fig. 3 is a diagram of load current versus load resistance that illustrates the current limiting feature of the circuit of Fig. 2; Fig. 4 shows a second embodiment of the invention in which the current limit decreases as the temperature increases; Fig. 5 illustrates a third embodiment of the invention which provides a power limiting function. DESCRIPTION OF THE PREFERRED EMBODIMENTS In the various figures of the drawings, elements which are the same are provided with the same reference labels. The known current limit circuit of Fig. 1 has already been described above. Fig. 2 shows a first embodiment of a high side intelligent power switch containing the current limit feature of the present invention. A battery or other voltage source (not shown) has a first terminal connected to the first voltage terminal 31 and a second terminal connected to the second voltage terminal 32 and to a point of reference voltage, for example, ground. The high side switch, i.e. power MOSFET 1, and the load 2 are connected in a first series circuit between the voltage terminals 31 and 32, thus across the battery. The sense MOSFET 3, the sense resistor 4 and the load 2 are connected in a second series circuit between terminals 31 and 32. A circuit junction point 5 is present between sense resistor 4, load 2 and the source electrode of power MOS transistor 1. A first NMOS transistor 6, i.e. a pull-down transistor, is connected between the input gate drive terminal 7 and the junction point 5. The gate electrodes of the MOS transistors 1 and 3 are connected in common to the gate drive terminal 7. A bias current source 11 and a second NMOS transistor 12 are connected in a third series circuit between the supply voltage terminal 31 and a second circuit junction point 13 located between the source of the sense MOS transistor 3 and the top terminal of sense resistor 4. The drain of NMOS transistor 12 is directly connected to its gate and the gate of transistor 12 is connected via a reference resistor 14 (R ref ) to the gate of the pull-down MOSFET 6. The gate of the NMOS transistor 6 is connected to the circuit junction point 5 via a source of reference current 15 through which flows a reference current, I ref . A reference voltage, V r , is developed across resistor 14 which thus functions as a source of reference voltage. In operation, the sense transistor is arranged to carry a fraction of the current flowing through the high side power switch transistor 1. As a result, the resistance R s of the sense resistor 4 can be chosen to have a low value so that the transistors 1 and 3 effectively function as a current mirror. Therefore, the voltage drop, V s , across the sense resistor is proportional to the current, I p , flowing through the power MOS transistor 1. By means of the feedback circuit comprising the NMOS transistor 12 and the reference resistor 14, the voltage V s across the sense resistor 4 of resistance R s is shifted up in value by the gate/source voltage, V gs (T r12 ) of transistor 12, and is then shifted down in value by a well defined reference voltage (V r ) developed across reference resistor 14 so as to derive the following gate-source voltage, V gs (T r6 ) of the pull-down transistor 6, V gs (T r6 ) = V s + V gs (T r12 ) - V r If the current flowing through the power MOSFET 1 increases, so does the current flow through the sense MOSFET 3, and if it increases to a value such that the voltage drop V s across the sense resistor 4 becomes equal to the reference voltage V r across the reference resistor 14, i.e. when V s = V r , then from equation (1) we get: V gs (T r6 ) = V gs (T r12 ) The NMOS transistors 6 and 12 are located very close to one another on an integrated circuit chip so that the condition expressed in equation (2) is independent of threshold voltage (V th ) variations which occur in the fabrication process. Transistor 12 is biased so that V gs (T r12 ) is slightly above the threshold voltage (V th ) of an NMOS transistor. Thus, no current limiting occurs as long as V gs (T r6 ) < V gs (T r12 ). As mentioned above, current limiting occurs when: V s = V r At this point, V gs (T r6 ) = V gs (T r12 ) so that the gate to source voltage, V gs (T r6 ), of NMOS transistor 6 is sufficient to turn on the transistor 6 which in turn pulls down the gate voltage of the power MOS transistor 1. This prevents any further increase in the current flow through the power transistor 1. Since the reference voltage (V r ) is a well defined reference voltage, which may also be generated by means of a band gap reference voltage, a very accurate current limit value is achieved which, at the same time, is independent of threshold voltage variations. If N = (W/L of MOSFET 1)/(W/L of MOSFET 3), then the current limit value I p (limit) of power transistor 1 is given by: I p (limit) = (V r /R s )*N where R s is the resistance value of the sense resistor 4. If both N and R s have fixed values, which is customary, then from equation (4) the current limit is directly controlled by the reference voltage, V r . The reference voltage, V r = I ref *R ref , where I ref and R ref are the values of the reference current in the reference current source 15 and the resistance of the reference resistor 14, respectively. In order to produce a very accurate reference voltage, the current I ref can be generated by means of a temperature stable bandgap voltage, V bgap . As an example, if I ref = 10 µA and R ref = 50K, thenV r = 0.5V. And if R s = 10Ω and N = 1000, then I p (limit) = (0.5/10)*1000 = 50A. . Figure 3 shows the relationship between the current (I p ) in the power MOSFET 1 in amps versus the load resistance R load in ohms for the current limit circuit of Fig. 2. As can be seen from this figure, the current I p increases up to a value of 50A as the load resistance decreases. The current I p is thereafter limited to the value 50A despite a further decrease in the load resistance. In the current limit circuit of Fig. 2, the sense MOS transistor 3 carries a fraction of the current (I p ) of the power MOS transistor 1. As a result, the voltage V s across the sense resistor 4 is proportional to the current I p . The sense voltage V s across the resistor 4 is voltage level shifted upwards by the NMOS transistor 12 and the reference voltage, V r , is subtracted therefrom to derive the gate voltage of NMOS pull-down transistor 6. The voltage V gs (Tr12) effectively offsets the threshold voltage (V th ) which makes it possible to keep the voltage V s as small as possible, thereby allowing the sense resistor current I s to maintain its proportionality to the power transistor current I p . During normal operation of the circuit, that is prior to any current limit action, V gs (Tr12) < V gs (Tr6) so that the pull-down transistor 6 is non-conductive. If the current I p flowing through sense resistor 4 increases to the point where V s = V r , V gs (Tr6) = V gs (Tr12) and the current limit operation commences as pull-down transistor 6 is turned on. The current limit circuit thus provides an accurate current limit independent of any variation of threshold voltage by using a single stage feedback mechanism which is inherently very stable without the use of any compensation. If the resistance R s of the sense resistor 4 increases with temperature, then from the relationship (4) it is apparent that the limit current would decrease with an increase in temperature. A range of values can be chosen for R s , V r and N so as to provide different current limit values. There is another possibility to add the feature that the current limit point decreases as the temperature increases thereby to better protect the power transistor 1. To this end, in the circuit of Fig. 2 the reference voltage, V r , is made to decrease as the temperature increases. This can be achieved by substituting a proportional to absolute temperature (PTAT) current source is substituted for the fixed reference current source 15 of Fig. 2. The PTAT current source produces a current (I PTAT ) which decreases as the temperature increases. The reference voltage, V r , is thus, V r = I PTAT *R ref . As a result, the reference voltage (V r ) developed across the reference resistor 14 decreases with increasing temperature and thereby reduces the current limit value of I p in accordance with equation (4) above. The modified current limit circuit of Figure 2 thus decreases the limiting current value as the temperature of the chip increases. This decrease is determined by the well controlled temperature dependence characteristic of the PTAT current source. The modified temperature responsive current limit circuit otherwise operates in a manner similar to that of the original current limit circuit of Fig. 2. Fig. 4 shows still another current limit circuit in which the current limit value decreases with an increase in temperature and in a well controlled manner. The current limit circuit of Fig. 4 is similar to that of Fig. 2, except that now the reference resistor 14 of Fig. 2 is replaced by an NPN bipolar transistor 16 having its collector connected to the first supply voltage terminal 31, its emitter connected to the gate of the pull-down NMOS transistor 6 and its base connected to the gate of the NMOS transistor 12. In the circuit of Fig. 4, the reference voltage, V r , is implemented by the base/emitter voltage drop, V be , of the bipolar transistor 16. The V be voltage of the NPN transistor 16 decreases as the temperature increases. Thus, the current limit value of the current limit circuit of Fig. 4 decreases in a well controlled manner as the temperature increases. This current limit circuit functions in a similar manner to that of Fig. 2. Fig. 5 shows a variation of the Fig. 2 circuit which provides a power limit function. The circuit is similar to the circuit of Fig. 2 except that a series circuit consisting of a zener diode 17 and a current limiting resistor 18 are connected in parallel with the bias current source 11. In this circuit, the power limiting function is implemented by decreasing the current limit value when the battery voltage at terminal 31 increases. This circuit operates similarly to the circuit of Fig. 2 except that when the battery voltage increases above a given value, the zener diode breaks down so that a current flows through the limit resistor 18 into transistor 12. This additional current flowing into transistor 12 increases as the battery voltage at terminal 31 increases. This in turn causes the gate to source voltage, V gs (Tr12), of transistor 12 to increase as the battery voltage increases. Looking again at equation (1) V gs (Tr6) = V s + V gs (Tr12) - V r The required value of the gate to source voltage of transistor 6, V gs (Tr6), in order for it to pull down the gate of the power MOS transistor 1, and thus to limit the current (I p ) is a fixed quantity. Since the gate/source voltage, V gs (Tr12) of transistor 12 now increases with increasing battery voltage, the required value of V gs (Tr6) is reached at a lower value of the sense voltage, V s , across the sense resistor 4. As a result, the current limiting function is activated at a lower current value when the battery voltage is higher. This achieves the desired power limiting function for the circuit of Fig. 5. The foregoing can also be seen from equation (1). Since V gs (Tr6) and V r are fixed, if V gs (Tr12) increases with the battery voltage, then V s must decrease in order to maintain the equality of equation (1). Finally, it is to be understood that the above-described arrangements are only illustrative of the principles of the present invention. In accordance with these principles, numerous modifications and alternatives may be devised by those skilled in the art without departing from the spirit and scope of the invention.

Claims: A current limit circuit comprising: first and second terminals (31,32) for supplying an operating voltage to the current limit circuit, a power transistor (1), means for connecting said power transistor (1) and a load (2) in series to said first and second terminals (31,32), a sense transistor (3) and a sense resistor (4) connected in a series circuit with the load (2) to said first and second terminals (31,32) such that the current flows (I s ) through the sense resistor (4) is proportional to the current flow (I p ) through the power transistor (1), means for coupling the control electrode of the power transistor and a control electrode of the sense transistor to a signal input terminal (7) of the circuit, and a further transistor (6) connected between a control electrode of the power transistor (1) and a point of reference potential (5), said further transistor (6) being biased into cut-off below the current limit value set for the power transistor (1), a voltage drop (V s ) being developed across the sense resistor (4) proportional to the current flow (I p ) in the power transistor (1) which drives the further transistor (6) into conduction when said voltage drop (V s ) across the sense resistor (4) exceeds a predetermined value (V r ) thereby to limit any additional current flow through the power transistor (1) characterized in that a feedback circuit (11-15) is connected between a junction point (13) of the sense transistor (3) and the sense resistor (4) and a control electrode of the further transistor (6), said feedback circuit (11-15) including a series connection of a semiconductor device (12) and a reference voltage source (11,14,15) which together produce a voltage level shift. A current limit circuit as claimed in Claim 1, characterized in that said semiconductor device (12) and said reference voltage source of the feedback circuit (11-15) comprise a diode-connected field effect transistor (12) and a reference resistor (14), respectively, and said current limit circuit further comprises, a source of reference current (15) connected to said reference resistor (14) and to one terminal (5) of the load (2), and a bias current source (11) coupled to said first terminal (31) and to a second junction point between the reference resistor (14) and one terminal of the semiconductor device (12). A current limit circuit as claimed in Claim 1 or 2, characterized in that said further transistor (6) and said semiconductor device (12) each comprise an NMOS field effect transistor, and said further transistor (6) is biased so that the gate/source voltage thereof is lower than the gate/source voltage of the NMOS semiconductor device (12) below the current limit value set for the power transistor (1), whereby said further transistor (6) is cut-off, and wherein said further transistor (6) is made to conduct when current through the sense resistor (14) produces a voltage drop thereacross such that V s = V r , where V s is the voltage drop across the sense resistor and V r is the reference voltage. A current limit circuit as claimed in Claim 1, 2 or 3, characterized in that said further transistor (6) and said semiconductor device (12) each comprise a field effect transistor with identical threshold voltages. A current limit circuit as claimed in Claim 1, characterized in that said reference voltage source (11,14,15) comprises; a reference resistor (14) connected between the semiconductor device (12) and the control electrode of the further transistor (6), and an inversely temperature-dependent current source (15) connected between the reference resistor (14) and one terminal of the load so that said current source supplies a lower current as the temperature increases, whereby the current limit value for the power transistor decreases as the temperature increases. A current limit circuit as claimed in Claim 5, characterized in that said current source (15) comprises a proportional to absolute temperature (PTAT) current source. A current limit circuit as claimed in Claim 1, characterized in that said further transistor (6) and said semiconductor device (12) each comprise a field effect transistor and said reference voltage source comprises a bipolar transistor (16) connected in series with a reference current source (15) between the first and second terminals (31,32) and with a base of the bipolar transistor connected to the field effect transistor semiconductor device (12), and with the gate of the field effect further transistor (6) connected to a junction point between the bipolar transistor (16) and the reference current source (15), whereby the current limit value for the power transistor (1) decreases as the temperature increases. A current limit circuit as claimed in Claim 7, characterized in that said bipolar transistor (16) comprises an NPN transistor and said reference current source (15) is connected between the emitter of the NPN transistor (16) and one terminal of the load (5) which is connected to the sense resistor (14). A current limit circuit as claimed in any one of the preceding Claims which provides a power limit function, characterized in that the semiconductor device (12) comprises a field effect transistor having its gate connected to its drain and its source connected to the sense resistor (4), said circuit further comprising; a voltage threshold device (17) connected between the first terminal (31) and the gate of the field effect transistor (12), said voltage threshold device (17) becoming conductive upon an increase in voltage at said first terminal above a given voltage determined by the desired power limit values so that an increased current flows through the field effect transistor (12) so as to increase the gate/source voltage of the field effect transistor (12) as said first terminal voltage increases, whereby the current limit value is reached with a lower value of sense voltage across the sense resistor (4) thereby to provide said power limit function. A current limit circuit as claimed in Claim 9, characterized in that said voltage threshold device comprises a zener diode (17) in series with a current limit resistor (18). A current limit circuit as claimed in any one of the preceding Claims, characterized in that all of the circuit elements are integrated together on a single integrated circuit chip with said further transistor (6) and said semiconductor device (12) located in close proximity to one another.

Inventors: VENKITASUBRAHMANIAN SREERAMAN, WONG STEPHEN, VENKITASUBRAHMANIAN, SREERAMAN, WONG, STEPHEN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1993
Main classification: H02H7
IPC codes: H03K17, H02H9, G05F3, H02H7