Method of fabricating a high-density nonvolatile semiconductor memory

Abstract: A nonvolatile semiconductor memory has active regions that form parallel strips extending in a first direction in a semiconductor substrate. Each active region has source areas (73), drain areas (75), and channel areas (76) for a series of memory cells. Floating gates (69) are formed over the channel areas (76), and control gates (71) over the floating gates (69). The upper surfaces of the control gates (71) and the sides of the control gates (71) and floating gates (69) are covered by insulating films (77,79,81). Source interconnecting lines (83) made of a conductive material are formed as parallel strips extending in a second direction different from the first direction on the semiconductor substrate, interconnecting the source areas (73) of the memory cells.

Description: BACKGROUND OF THE INVENTION This invention relates to a method of fabricating a nonvolatile semiconductor memory, more particularly a nonvolatile semiconductor memory having uniform program and erase characteristics and capable of high-density integration. Nonvolatile reprogrammable semiconductor memories such as electrically erasable programmable read-only memory (EEPROM) and flash memory are ideal for storing data that only occasionally need to be modified, because they can retain the data while power is off. Memories of this type are used in many computing devices and systems. Fig. 1 shows a sectional view of the memory cell structure of a conventional reprogrammable nonvolatile memory. The semiconductor substrate 11 comprises crystalline silicon. A floating gate 13 disposed above the substrate 11, a control gate 15 disposed above the floating gate 13, and a source area 17 and drain area 19, which are formed by doping the substrate 11 on either side of the gates 13 and 15 with impurities, are the principal elements of a memory cell 21. These elements form a field-effect transistor with an active region comprising the source area 17, the drain area 19, and a channel 22 disposed in the substrate 11 between the source and drain areas. These elements are covered by an insulating film 23, in which a contact hole 25 is opened to permit a metal interconnecting line 27 (a bit line) to make contact with the drain area 19. The source and drain areas 17 and 19 of the memory cell 21 are shared with other memory cells adjacent in a first direction, which will be marked as the y-direction in the drawings. Fig. 2 shows a plan view of several memory cells in a conventional nonvolatile memory, using the same reference numerals as in Fig. 1. Fig. 1 corresponds to a section through the line I-I. The y-direction is vertical in Fig. 2; the perpendicular direction (now horizontal) is denoted the x-direction. It can be seen that the source areas 17 extend in the x-direction so as to interconnect all memory cells disposed in the same horizontal row. The control gates 15 are also interconnected in the x-direction, forming word lines. The floating gates 13 (hatched) are not interconnected. Fig. 3 is a simplified plan view from which the gates, word lines, and bit lines have been removed to show the shape of the active region 31. Due to the sharing of source and drain areas between adjacent memory cells in the y-direction, and the extensions of the source areas in the x-direction, the active region 31 has the general form of a rectilinear grid. In areas not occupied by the active region 31, the surface of the substrate is oxidized to create insulating field areas 33. Referring again to Fig. 2, the source areas 17 are held at a constant electrical potential by means of metal source lines 35 that run parallel to the bit lines 27 in the y-direction. Each metal source line 35 makes contact with the source areas 17 in the substrate through contact holes 37 which are opened in the insulating layer 23 shown in Fig. 1. One metal source line 35 is provided for every m bit lines 27, where m is a positive integer. For example, one metal source line 35 may be provided per sixteen bit lines 27. One problem with the conventional memory structure illustrated in Figs. 1 to 3 is that the source resistance of a memory cell varies depending on its distance from the metal source lines 35. If there is one metal source line 35 for every sixteen bit lines 27, for example, the eighth memory cell from a metal source line 35 has a higher source resistance than a memory cell disposed adjacent to a metal source line 35. The source resistance can become quite substantial. For example, if the x-pitch of the memory cells is 2.0 µm (indicated by the capital letter X in Fig. 2), the width (in the y-direction) of the source areas 17 is 0.5 µm, and the sheet resistivity of the source areas is 50 Ω, then the source resistance of the eighth memory cell, disposed midway between two metal source lines, is (50 x 2.0 x 8/0.5)/2 = 800 Ω. The final division by two in this formula takes account of the parallel electrical paths to two metal source lines 35. A high source resistance degrades programming and erasing characteristics, i.e. it takes longer to program and erase the memory cells. The large variation in source resistance from one cell to another furthermore makes it difficult to program and erase the cells accurately, increasing the risk of overprogramming and overerasing. Another problem is that providing metal source lines 35 every m bit lines increases the effective x-pitch of the memory cells by a factor of (m + 1)/m, which is a disadvantage from the standpoint of integration density. Impediments to dense integration also exist in the y-direction. The y-pitch of the memory cells, indicated by the capital letter Y in Fig. 2, is the sum of five quantities: y 1 (one-half the y-dimension of the source area 17); y 2 (the gap between the gates 13 and 15 and the active region 31); y 3 (the gate length); y 4 (the gap between the gates 13 and 15 and the contact hole 25); and y 5 (one-half the y-dimension of the contact hole 25). The gap y 2 is needed to ensure that the floating gates 13 and control gates 15 cross the active regions 31 only in the channel areas of the memory cells, and do not overlap the extensions of the source areas 17 in the x-direction. The need for the gap y 4 is apparent from Fig. 1; it keeps the gates from being short-circuited to the bit lines. Both gaps y 2 and y 4 must be big enough to allow a mask overlay tolerance during the memory fabrication process; this restricts the achievable integration density. On the basis of 0.6-µm design rules, the above quantities can be estimated as follows: y 1 = 0.25 µm, y 2 = 0.25 µm, y 3 = 0.7 µm, y 4 = 0.3 µm, and y 5 = 0.3 µm. The y-pitch Y is accordingly 1.8 µm. Details will be omitted, but the x-pitch with the same 0.6-µm design rules is 2 µm. Another problem occurring in the conventional memory is that, due to mask misregistration, in some cases the floating gates 13 may be disposed quite close to the edges of the field areas 33, where the field oxide is relatively thin, while in other cases they are disposed farther from the edges, where the field oxide is relatively thick. This leads to variation in the potential of the floating gates 13, which is a source of further nonuniformity in programming and erasing characteristics. European Patent Application EP-A-0436475 discloses a nonvolatile memory having source metal contact lines that interconnect the source areas of memory cells in the x-direction. The active regions are accordingly formed as parallel strips extending in the y-direction; the source regions do not extend in the x-direction. Pillar-shaped metal contacts are also formed on the drain areas. The fabrication process for the source metal contact lines and drain contacts deposits a metal layer, coats the metal layer with a planarization material, etches the planarization material without a mask to leave strips of planarization material running in the x-direction in troughs of the metal layer, etches the planarization material again with a mask so as to remove planarization material from the spaces between adjacent drain areas, then etches the metal layer with the remaining planarization material serving as an etching mask. US-A-5149665 also discloses a nonvolatile memory with metal source interconnecting lines, but does not form both metal source interconnecting lines and drain contacts by patterning a single metal layer. SUMMARY OF THE INVENTION It is accordingly an object of the present invention to efficiently fabricate a nonvolatile semiconductor memory with uniform programming and erasing characteristics. Another object of the invention is to increase the integration density of a nonvolatile semiconductor memory. Yet another object is to reduce the source resistance of memory cells in a nonvolatile semiconductor memory. Still another object is to overcome fabrication restrictions imposed by the photolithography resolution limit. The inventive method is defined in independent claim 1. The dependent claims define particular embodiments of the invention. The invented fabrication process fabricates a nonvolatile semiconductor memory by forming a plurality of active regions as parallel strips extending in a first direction in a semiconductor substrate. Each active region has source areas, drain areas, and channel areas for a plurality of memory cells. Floating gates are formed over the channel areas, and control gates over the floating gates. The upper surfaces of the control gates and the sides of the control gates and floating gates are covered by insulating films. Source interconnecting lines comprising a conductive material are formed on the semiconductor substrate as parallel strips extending in a second direction different from the first direction, interconnecting the source areas. The invented fabrication process also forms conductive drain pads covering the drain areas. The drain pads are formed from the same material as the source interconnecting lines. The drain pads and source interconnecting lines are formed by depositing a thin film of this material, creating on this thin film a first mask defining the source interconnecting lines, also creating on this thin film a second mask defining the drain pads, and etching the thin film in areas not protected by the first and second masks. The first and second masks are formed by separate photolitographic steps having a certain resolution limit. The first and second masks are separated from one another by a distance less than the resolution limit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional drawing of a conventional nonvolatile semiconductor memory. Fig. 2 is a plan drawing of a conventional nonvolatile semiconductor memory. Fig. 3 is a simplified plan drawing of a conventional nonvolatile semiconductor memory, showing its active regions. Fig. 4 is a sectional drawing of a nonvolatile semiconductor memory fabricated by the method according to the invention. Fig. 5 is a plan drawing of the memory of Fig. 4. Fig. 6 is a simplified plan drawing of the memory of Fig.4, showing its active regions and floating gates. Fig. 7 is a sectional drawing illustrating a stage in a first fabrication method for the memory of Fig. 4. Fig. 8 is a sectional drawing illustrating a succeeding stage in the first fabrication method. Fig. 9 is a sectional drawing illustrating another succeeding stage in the first fabrication method. Fig. 10 is a sectional drawing illustrating another succeeding stage in the first fabrication method. Fig. 11 is a sectional drawing illustrating another succeeding stage in the first fabrication method. Fig. 12 is a sectional drawing illustrating another succeeding stage in the first fabrication method. Fig. 13 is a sectional drawing illustrating another succeeding stage in the first fabrication method. Fig. 14 is a sectional drawing illustrating another succeeding stage in the first fabrication method. Fig. 15 is a sectional drawing illustrating a stage in a second fabrication method for the memory of Fig. 4. Fig. 16 is a sectional drawing illustrating a succeeding stage in the second fabrication method. Fig. 17 is a sectional drawing illustrating another succeeding stage in the second fabrication method. Fig. 18 is a sectional drawing illustrating a stage in a third fabrication method for the memory of Fig. 4. Fig. 19 is a sectional drawing illustrating another stage in the third fabrication method. Fig. 20 is a sectional drawing illustrating another succeeding stage in the third fabrication method. Fig. 21 is a sectional drawing illustrating another succeeding stage in the third fabrication method. Fig. 22 is a sectional drawing illustrating another succeeding stage in the third fabrication method. Fig. 23 is a sectional drawing illustrating another succeeding stage in the third fabrication method. Fig. 24 is a sectional drawing illustrating another succeeding stage in the third fabrication method. Fig. 25 is a sectional drawing of another nonvolatile semiconductor memory. DETAILED DESCRIPTION OF THE INVENTION Embodiments of the invention will now be described with reference to the attached drawings. These drawings are provided only for aid in understanding the invention, and show the dimensions, shapes, and positional relationships of the elements only schematically. Referring to Fig. 4, a memory fabricated according to the invention comprises a semiconductor substrate 61 such as a crystalline silicon substrate for the formation of memory cells 65. Each memory cell 65 comprises a floating gate 69, a control gate 71, a source area 73, and a drain area 75 as in the prior art, with a channel 76 disposed below the floating gate 69 between the source and drain areas. The floating gate 69 is insulated from the channel 76 by a gate insulating film 77 comprising, for example, silicon dioxide, and from the control gate 71 by a similar insulating film 79. The top surface and sides of the gate structure in each memory cell are covered by a further insulating film 81 comprising, in this embodiment, a top insulating film 81a and side insulating films 81b. The top insulating film 81a covers the upper surface of the control gate 71. The side insulating films 81b cover the sides of both the floating and control gates 69 and 71, and of the insulating films 79 and 77 above and below the floating gate 69. The top and side insulating films 81a and 81b in this embodiment are formed separately, as will be described later. The invention can also be practiced, however, by forming a single insulating film covering both the top and sides of the gate structure. The surface of each source area 73, and the adjacent surfaces of the side insulating films 81b, are covered by a source interconnecting line 83 comprising a conductive material: for example, a refractory metal such as tungsten. The source interconnecting lines 83 may also partly cover the top insulating layer 81a, as shown in the drawing. The source interconnecting lines 83 run perpendicular to the page, in the x-direction, as will be shown later. The surface of each drain area 75 is covered by a pad 85, which also covers the adjacent side insulating layers 81b and extends onto the top insulating layers 81a. The pad 85 provides a self-aligned electrical contact between the drain area 75 and a bit line 87. The drain pads 85 are formed of the same material as the source interconnecting lines 83. The bit lines 87 run in the y-direction, which is the horizontal direction in Fig. 4. The bit lines 87 are separated from the underlying structure by an inter-layer insulating film 89, in which contact holes 91 are opened to provide access to the drain pads 85. Fig. 5 shows the memory in plan view, using the same reference numerals as in Fig. 4. The y-direction is now vertical and the x-direction horizontal. Fig. 4 corresponds to a section through the line I-I in Fig. 5. The source areas 73, drain areas 75, and channels 76 that were illustrated in Fig. 4 are indicated only as active regions 63 in Fig. 5. The source interconnecting lines 83 can be seen to have the form of strips running in the x-direction. The control gates 71 are interconnected in the x-direction, forming word lines, as in the prior art. Fig. 6 is a simplified plan view showing only the active regions 63, field areas 67, floating gates 69, and channels 76. The active regions 63 are seen to have the form of parallel strips extending in the y-direction. instead of forming an x-y grid as in the conventional memory. The field areas 67 that separate the active regions 63 comprise, for example, oxidized regions as in a conventional memory. As noted above, Figs. 4 to 6 are schematic and do not necessarily represent the exact shapes of their constituent elements. For example, the active regions 63 need not be perfectly straight strips as shown in Fig. 6; their edges may curve in and out somewhat, following contours defined by diffusion in the source and drain doping process. A description of the operation of the memory of Figs. 4 to 6 will be omitted, as it is the same as the operation of a conventional memory and will be familiar to those skilled in the art. Instead, the advantages of the memory of Figs. 4 to 6 as compared with the conventional memory of Figs 1 to 3, will be described. A first advantage is that the source areas 73 of the memory cells are interconnected by source interconnecting lines 83 formed by depositing a conductive material, instead of by extensions of the source areas formed by doping the substrate with impurities. This feature of the invention can greatly reduce the source resistance of the memory cells. If, for example, the source interconnecting lines 83 comprise a tungsten film 100 nm thick and 0.5 µm wide, with a volume resistivity of 5.4 x 10 -8 Ω·m, and the x-pitch is 2 µm per memory cell, then the source resistance will be (5.4 x 10 -8 x 2 x 10 -6 )/(100 x 10 -9 x 0.5 x 10 -6 ) = 2.16 Ω per memory cell. Even if a source interconnecting line 83 is used to interconnect a row of one thousand memory cells, the source resistance of a memory cell in the center of this row will only be (500 x 2.16)/2 = 540 Ω . The utility of the invention can be understood by comparing this value with the 800 Ω for a row of only sixteen memory cells disposed between two conventional metal source lines in the prior art described in Figs. 1 to 3. A second advantage is that, there is less variation in source resistance from one memory cell to another. A third advantage is that the metal source lines 35 of Fig.3 are unnecessary. Density in the x-direction can therefore be increased by a factor of (m + 1)/m, where m is the number of bit lines between each pair of metal source lines in a conventional memory. A fourth advantage is that the y-pitch of the memory cells can be reduced. Referring to Fig. 4, since the drain pads 85 are self-aligned, no gap between them and the floating and control gates 69 and 71 is necessary, other than the gap provided by the thickness of the side insulating layers 81b. Similarly, no gap is required between the source interconnecting lines 83 and these gates, other than the thickness of the side insulating layers 81b. Referring to Fig. 6, since the active regions 63 do not extend in the x-direction, no gap is necessary to keep the floating gates 69 from overlapping the active regions 63 outside the channel areas 76. Referring to Fig. 5, the y-pitch of the memory cells, indicated by the capital letter Y, is the sum of five quantities: y A (half the distance between adjacent gates); y B (overlap of the source interconnecting lines on the gates); y C (gap between source interconnecting lines and drain pads); y D (alignment margin of contact holes and drain pads); and y E (half the contact-hole diameter). If these dimensions are estimated from 0.6-µm design rules, and if mask registration accuracy is assumed to be 0.3 µm, then y E is 0.3 µm, y D is 0.3 µm (maximum mask misregistration), y C is 0.4 µm (preventing a short circuit even if this degree of misregistration occurs), y B is 0.1 µm, and y A is 0.4 µm. The resulting y-pitch is 1.5 µm, a reduction of 0.3 µm from the conventional 1.8 µm. The values of y A and y B are subject to adjustment depending on the thickness of the side insulating films 81b and variability in the fabrication process. A feature of the invented fabrication methods, which will be described later, is that the value of y C (0.4 µm in the example above) can be less than the design-rule value (0.6 µm) set by the photolithography resolution limit. A fifth advantage, which will be obvious from Fig. 6, is that the potential of the floating gates is not subject to variation due to location over thicker or thinner portions of the field oxide, resulting from mask misregistration in the y-direction. The oxide thickness of the field areas 67 is uniform everywhere in the y-direction, since these areas are not interrupted by the conventional extensions of the active regions in the x-direction. Overall, the first advantage implies improved device characteristics (faster programming and erasing), the second and fifth advantages imply less variability in device characteristics, and the third and fourth advantages imply higher integration density for given design rules. Next, a first method of fabricating the above memory will be described with reference to Figs. 6 to 14, using the same reference numerals as in Fig. 4. Referring again to Fig. 6, fabrication begins with oxidation of the semiconductor substrate 61 by well-known methods to create the field areas 67. The field areas 67 are formed so as to leave active regions 63 in the semiconductor substrate 61, extending as parallel strips in the y-direction. The field areas 67 are insulating areas that isolate the active regions 63 from one another. Referring to Fig. 7, next an insulating film, a thin floating-gate film, another insulating film, a conductive control-gate film, and yet another insulating film are deposited on the substrate 61 in the order stated, and these films are patterned by photolithography and etching techniques to obtain the gate insulating film 77, the floating gates 69, the insulating film 79 between the floating gates 69 and control gates 71, the control gates 71, and the top insulating film 81a. Source areas 73 and drain areas 75 are then formed by doping portions of the substrate 61 adjacent to the gates 69 and 71 with suitable impurities. Deposition, photolithography, etching, and doping methods are well known, so detailed descriptions will be omitted. Referring to Fig. 8, another insulating film is now deposited, then selectively removed by anisotropic etching to create the side insulating films 81b. The steps so far cover the upper surface of the control gates 71 and the sides of the floating and control gates 69 and 71 with an insulating film 81 comprising the insulating films 81a and 81b. This insulating film 81 has been described as being formed by deposition and etching, but other methods can of course be used. For example, if the floating and control gates 69 and 71 comprise polysilicon, the insulating film 81 can be created by oxidation of the side surfaces of the floating and control gates 69 and 71 and the upper surface of the control gates 71. Referring to Fig. 9, a thin conductive film (for example, a tungsten film) 83x is now formed on the entire surface of the memory device, including the exposed surfaces of the source and drain areas 73 and 75. This conductive film 83x will next be patterned to create the source interconnecting lines and drain pads. Two separate masks will be employed, one for the source interconnecting lines and one for the drain pads. Either mask may be formed first. In the description that follows, the source-interconnecting-line mask is formed first, but the invention may of course be practiced by forming the drain-pad mask first. Referring to Fig. 10, the device is next coated with a photoresist, which is patterned by photolithography to obtain a first photoresist pattern 93 that will serve as a mask defining the source interconnecting lines. The first photoresist pattern 93 is then cured by heating, by illumination with ultraviolet light, or by another suitable method that strengthens or hardens the photoresist. The cured photoresist pattern will be denoted by reference numeral 93a in the following drawings. Referring to Fig. 11, a new photoresist is now applied to the entire surface of the device and patterned by photolithography to form a second photoresist pattern 95, which will serve as a mask defining the drain pads. The cured first photoresist pattern 93a is not damaged by the photolithography step that forms the second photoresist pattern 95. Since the first photoresist pattern 93 and second photoresist pattern 95 are formed by separate photolithography steps, the dimensions of the gaps between them, which will become the spaces between the source interconnecting lines and drain pads, are not constrained by the design rules imposed by photolithography resolution; these gaps can be even smaller than the design-rule limit. As noted earlier, this is one of the features of the present invention that enables high integration density. Referring to Fig. 12, the thin conductive film 83x is now selectively etched, using the second photoresist pattern 95 and the cured first photoresist pattern 93a as masks. In this way the source interconnecting lines 83 and drain pads 85 are formed. Referring to Fig. 13, the photoresist patterns 93a and 95 are now removed and an inter-layer insulating film 89 is deposited, covering the entire surface of the device. Contact holes 91 are opened in this film 89 over the drain pads 85. Finally, referring to Fig. 14, the bit lines 87 are created by well-known methods, completing the structure that was shown in Fig. 4. Next a second fabrication method will be described with reference to Figs. 15 to 17. This second method is a modification of the first method, differing in the way in which the masks for the source interconnecting lines and drain pads are created. The initial steps through the formation of the thin conductive film 83x are the same as in the first method, as illustrated in Figs. 6 to 9. Referring to Fig. 15, following the steps in Figs. 6 to 9, a negative photoresist 97 is applied to the entire surface of the device. This negative photoresist will be exposed twice, once to form masks for the source interconnecting lines and once to form masks for the drain pads. Either exposure may be carried out first. Fig. 15 shows the exposure for the source interconnecting lines being made first, the exposed area being denoted Q 1 . Referring to Fig. 16, after the first exposure is completed, the negative photoresist 97 is exposed a second time to form masks for the drain pads. The exposed areas are denoted Q 2 in the drawing. Referring to Fig. 17, when the negative photoresist 97 is developed, the unexposed portions are removed and the exposed portions remain, forming a photoresist pattern 97x comprising a mask 97a for the source interconnecting lines and another mask 97b for the drain pads. The remaining steps of the second fabrication method are identical to the steps of the first fabrication method illustrated in Figs. 12 to 14. An advantage of the second fabrication method is that the step of curing the first photoresist pattern in the first method can be omitted. Next a third fabrication method will be described with reference to Figs. 18 to 26. This third method is also a modification of the first fabrication method, and starts with the same initial steps through the formation of the thin conductive film 83x, as illustrated in Figs. 6 to 9. Referring to Fig. 18, in the next step a thin film 99 comprising a material other than a photoresist is formed on the entire surface of the thin conductive film 83x. The thin film 99 may be, for example, a silicon dioxide or silicon nitride film. Referring to Fig. 19, a photoresist is now applied to the entire surface of this thin film 99 and patterned so as to leave a photoresist pattern 101 defining the source interconnecting lines. Referring to Fig. 20, the thin film 99 is selectively etched using this photoresist pattern 101 as a mask, thereby obtaining a mask 99x that also defines the source interconnecting lines. This etching step is carried out by a selective method that etches the thin film 99, but leaves the thin conductive film 83x substantially intact. If the thin film 99 comprises silicon dioxide and the thin conductive film 83x comprises tungsten, a dry etching process using a mixture of CHF 3 and CF 4 gases can be employed. Referring to Fig. 21, another photoresist is now applied to the entire device and patterned, leaving a mask 103 defining the drain pads. Referring to Fig. 22, the thin conductive film 83x is now selectively etched, removing parts not protected by the masks 99x and 103. This step creates the source interconnecting lines 83 and drain pads 85. Referring to Fig. 23, the drain-pad mask 103 is removed, the inter-layer insulating film 89 is deposited, and contact holes 91 are opened. The mask 99x that defined the source interconnecting lines 83 is left in place. Referring to Fig. 24, the bit lines 87 are now formed. The resulting structure is identical to Fig. 4 except for the presence of the mask 99x on the source interconnecting lines 83. This remaining mask 99x does not impair the operation of the memory. The third fabrication method can be modified in various ways. For example, the mask 99x can be removed before deposition of the inter-layer insulating film 89. Also, it is possible to form the mask for the drain pads first, using a material other than a photoresist (e.g. silicon dioxide), and form the mask for the source interconnecting lines second, using a photoresist material, instead of the other way around. Another alternative is to deposit a silicon nitride film, for example, on the silicon oxide film 99 of Fig. 18, then pattern these films by two sequential photolithography and etching steps. If this alternative is followed, one of the two masks (either the mask defining the source interconnecting lines or the mask defining the drain pads) will comprise a silicon oxide film, and the other mask (either the mask defining the drain pads or the mask defining the source interconnecting lines) will comprise a silicon nitride film. An advantage of the third fabrication method is that a tougher mask is obtained than when the mask is formed only of a photoresist, so an improvement in the patterning accuracy of the source interconnecting lines and drain pads can be expected. The utility of the above three fabrication methods can be readily understood from Fig. 25, which shows a generally similar memory that can be fabricated by more conventional methods. Elements in Fig. 25 that are identical to elements in Fig. 4 have the same reference numerals, and descriptions of these elements will be omitted. The main structural difference between Figs. 4 and 25 is that in Fig. 25, the source interconnecting lines 105 and drain pads 107 are mutually separated by an intermediate insulating film 109. This intermediate insulating film 109 permits the source interconnecting lines 105 to approach the drain pads 107 to within a distance less than the resolution limit of the photolithography process, so that integration can be increased by reducing the dimension y C in Fig. 5. The source interconnecting lines 105 in Fig. 25 partly overlie the intermediate insulating film 109, which partly overlies the drain pads 107. This structure can be created by first depositing and patterning the drain pads 107, then depositing and patterning the intermediate insulating film 109, then depositing and patterning the source interconnecting lines 105. That would be the conventional approach to the fabrication of the memory described above. The memory structure in Fig. 25 provides the same advantages as the structure in Fig. 4 (reduced source resistance, more uniform program/erase characteristics, and improved integration density), but its fabrication requires one deposition, photolithography, and etching process for the drain pads 107, another deposition, photolithography, and etching process for the intermediate insulating film 109, then yet another deposition, photolithography, and etching process for the source interconnecting lines 105. In contrast, the three invented fabrication methods deposited and etched the source interconnecting lines and drain pads simultaneously, and there was no intermediate insulating film 109 to be formed. The invented methods are therefore more efficient, and can be expected to provide higher production throughput. The invented memory fabrication methods are not limited to the materials described in Figs. 4 to 24; other suitable materials can be employed instead, and those skilled in the art will recognize that still further modifications can be made without departing from the scope of the invention which is defined by the appended claims.

Claims: A method of fabricating a nonvolatile semiconductor memory by forming memory cells (65) arranged in columns defining a first direction and rows defining a second direction, perpendicular to the first direction, on a semiconductor substrate (61), each memory cell having a floating gate (69) formed above the semiconductor substrate, a control gate (71) formed above the floating gate, the control gates within each row of memory cells being interconnected, a channel area (76) disposed in the semiconductor substrate below the floating gate, a source area (73) extending from one side of the channel area in the first direction, and a drain area (75) extending from an opposite side of the channel area in the first direction, the upper surface of the control gate and the side surfaces of the control gate and floating gate being covered with an insulating film (81), the source areas and drain areas in each column of memory cells being shared by adjacent memory cells in the column, and the columns of memory cells being isolated from one another by insulating field areas (67), comprising the steps of: depositing a thin conductive film (83x) over all areas of said substrate (11), covering said source areas (73), said drain areas (75), and said insulating film (81); forming on said thin conductive film (83x) a first mask defining source interconnecting lines (83) interconnecting said source areas (73) in said second direction, said first mask being formed by a first photolithographic process having a certain resolution limit; forming on said thin conductive film (83x) a second mask defining pads (85) over said drain areas (75), said second mask being formed by a second photolithographic process also having said resolution limit, leaving gaps less than said resolution limit between said first mask and said second mask; and etching portions of said thin conductive film (83x) not protected by said first mask and said second mask, thereby creating said source interconnecting lines (83) and said pads (85) said pads being separated from said source interconnecting lines by distances less than the design rule value set by said resolution limit. The method of claim 1, wherein said first mask (93) is formed by photolithographically patterning one photoresist, and said second mask (95) is formed by photolithographically patterning another photoresist. The method of claim 2, wherein said first mask (93) is formed before said second mask (95). The method of claim 3, comprising the further step of curing said first mask (93a) before forming said second mask (95). The method of claim 2, wherein said second mask (95) is formed before said first mask (93). The method of claim 5, comprising the further step of curing said second mask (95) before forming said first mask (93). The method of claim 1, wherein said first mask and said second mask are formed by the steps of: depositing a negative photoresist (97) on said thin conductive film (83x): exposing said negative photoresist (97) in a pattern defining said first mask, this step of exposing constituting said first photolithographic process; exposing said negative photoresist (97) in a pattern defining said second mask, this step of exposing constituting said second photolithographic process; and developing said negative photoresist (97). The method of claim 7, wherein the step of exposing said negative photoresist (97) in a pattern defining said first mask is performed before the step of exposing said negative photoresist (97) in a pattern defining said second mask. The method of claim 7, wherein the step of exposing said negative photoresist (97) in a pattern defining said second mask is performed before the step of exposing said negative photoresist (97) in a pattern defining said first mask. The method of claim 1, wherein said first mask and said second mask are formed by the steps of: depositing a first mask material (99) on said thin conductive film (83x); patterning said first mask material (99) in a pattern creating said first mask (99x); depositing a second mask material, different from said first mask material, on said thin conductive film (83x) and on said first mask (99x); and patterning said second mask material in a pattern creating said second mask (103). The method of claim 10, wherein said second mask material is a photoresist and said first mask material is not a photoresist. The method of claim 10, wherein said first mask material and said second mask material are both materials other than photoresists. The method of claim 12, wherein said first mask material comprises silicon dioxide and said second mask material comprises silicon nitride. The method of claim 12, wherein said first mask material comprises nitride and said second mask material comprises silicon dioxide. The method of claim 1, wherein said first mask and said second mask are formed by the steps of: depositing a first mask material on said thin conductive film (83x); patterning said first mask material in a pattern creating said second mask; depositing a second mask material, different from said first mask material, on said thin conductive film (83x) and on said second mask; and patterning said second mask material in a pattern creating said first mask. The method of claim 15, wherein said second mask material is photoresist and said first mask material is not photoresist. The method of claim 15, wherein said first mask material and said second mask material are both materials other than photoresists. The method of claim 17, wherein said first mask material comprises silicon dioxide and said second mask material comprises silicon nitride. The method of claim 17, wherein said first mask material comprises silicon nitride and said second mask material comprises silicon dioxide.

Inventors: ONO TAKASHI, ONO, TAKASHI, ONO, TAKASHI, C/O OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1993
Main classification: H01L27
IPC codes: H01L29, H01L27