Optical switch for fast cell switching networks

Abstract: The optical switch for fast cell-switching networks comprises an optical interconnection network (CM) and an electrical control network (CT). In order to fully exploit optical component capabilities and to overcome the constraints imposed by operating speed limits of electronic components, each input (IN1...INk) of the interconnection network (CM) is associated with means (PAC1...PACk) forming aggregates of cells which are to follow a same path through the interconnection network and time-compressing the aggregates, and each output (OU1...OUk) is associated with means (PAD1...PADk) for the time expansion of the aggregates and separation of the aggregate cells.

Description: The present invention relates to optical telecommunication systems, and more particularly it concerns an optical switch for fast cell-switching networks. Fast cell (or fast packet) switching technique, also called ATM from the initials of the designation in the English language "Asynchronous Transfer Mode", is becoming more and more important for switching digital flows at very high rates, such as the flows present in the digital broadband integrated service networks. In this technique, the information relevant to the various services is organized into adjacent units with a fixed length (about 400 bits), called "cells", comprising an information field and a header field, carrying the connection identifier together with other service information. Due to the rate and bandwidth requirements by integrated service networks, the use of optical technologies is acquiring an increasing interest in the realization of both transmission lines and switching function. At the present state of technique, however, optical technologies do not allow high processing capacities, and the optical switching systems generally proposed provide the use of an electrical control part (therefore with a high processing capacity) and of an optical transport part (with a high capacity of information flow throughput). Examples of these networks have been described, for example, in the European Patent Applications EP-A-0224244 and EP-A-0411562 and in the papers: "A Photonic Knockout Switch For High-Speed Packet Networks", presented by K. Y. Eng at the IEEE/IEICE Global Telecommunications Conference 1987, 15 - 18 November 1987, Tokyo, Japan; "Optical Technology Application to Fast Packet Switching" presented by P. Cinato and A. de Bosio, at the Topical Meeting on Photonic Switching, 1 - 3 March 1989, Salt Lake City, USA; "Electro-Optical switching node based on fast packet and frequency switching techniques", presented by A. de Bosio et al. at the International Switching Symposium, May 1990, Stockholm, Sweden. Also, EP-A-0282071 describes such system wherein electrical signals are converted into optical signals for time-compression and switching, and at the output are reconverted into electrical signals. Electronic control units however have operating speed limits which could prevent full exploitation of the optical part capabilities because they compel to limit the bit rate on the input lines to the node. One of the limits is related to the problem of so-called overhead caused by short packets. For reducing such overhead in an ATM network, it is known from IBM Technical Disclosure Bulletin, Vol. 34 No. 4B, Sept. 1991, pages 360 - 362, to bundle packets sharing common network facilities like links and queues, into an aggregate so as to share the packet control bytes. The interconnection network is an electrical one. The implementation of the described function is not shown in detail, handling by a microcontroller being mentioned. The aim of the invention is to provide an optical switch allowing full exploitation of the capacity of the optical components, and which utilizes hence information flows at a very high rate within it, though in the presence of an electronic control part. According to the invention the switch comprises an optical interconnection network having optical inputs and outputs, an electrical control network controlling the optical interconnection network, input and output termination devices associated to each input and each output of the switch, respectively, input and output converter means for the conversion of electrical signals supplied from the input termination devices into optical signals to be supplied to the optical interconnection network and of optical signals supplied from the optical interconnection network into electrical signals to be supplied to the output termination devices, respectively, and time compression and re-expansion means for the time compression of the signals to be switched and the time re-expansion of switched signals, respectively, and is characterized in that: the input termination devices split the signals to be forwarded to the electrical control network from those to be switched in the interconnection network, and the output termination devices recombine the signals coming from the control network and the interconnection network; between each input termination device and the interconnection network aggregation and compression means are arranged containing an aggregation unit followed by said time compression means, the aggregation unit comprising: a decoding network, presenting a data input at which it receives the cells to be switched, coming from an input line of the switch, and a plurality of outputs, each associated to a different path, the decoding network forwarding each cell on an output selected according to information, taken from said cells and supplied to a control input, which codes the path the cell refers to; a plurality of memories, each of which is associated to an output of the decoding network and organizes a queue of the cells present on said output to form cell aggregates, each memory being associated to control units for the writing/reading, which cause reading whenever a pre-determined number of cells has been written or after a maximum preset time; a selector presenting a plurality of inputs each connected to the output of one of the memories and an output on which the aggregates to be forwarded to the compression means are presented; thereby forming cell aggregates by associating a plurality of cells which must follow the same path through the interconnection network and performing said time compression by acting on the aggregates, in order to form information units the duration of which is equal to a pre-set fraction of the original duration of an aggregate and the information contents of which, as number of bits, is equal to the sum of the information contents of the aggregated cells; the electrical control network is adapted to manage switching, through the optical interconnection network, at cell aggregates level; and the means for the time re-expansion, bringing back to the original duration the aggregates outgoing from the interconnection network, are adapted to separate the individual cells before forwarding them to the output termination devices. Time compression of packets to be switched through an optical switching network is known in se from IT-B-1217130 in the name of the Applicant itself, in which, however, individual packets are compressed made up of electrical signals, which are converted into optical form after compression. The switch is preferably an ATM digital cross-connect system and the aggregation and compression means form cell aggregates relevant to the same virtual path. The application of the invention to a cross-connect system is useful because the traffic to be switched is sufficiently high to allow the formation of cell aggregates without introducing excessive delays. The invention will be better understood with reference to the annexed drawings, wherein: Fig. 1 shows the general structure of a switch according to the invention; Fig. 2 shows the structure of the cell aggregation and compression units; Fig. 3 is a schematic diagram of the compression operation; Fig. 4 shows the structure of the re-expansion units; Fig. 5 is a schematic diagram showing the re-expansion operation. By way of a non limiting example, the invention is described with reference to an ATM digital cross-connect system comprising an optical interconnection network and an electronic control network. As it is known an ATM cross-connect system switches ATM flows at a virtual path level. A virtual path is generally associated to semipermanent calls, so that a cross-connect system does not require very frequent re-configurations; this is a typical application where, after configuring the interconnection network, throughput of a large quantity of traffic must be guaranteed, and it is therefore important that electronic control network should not set any constraint. According to the invention, this is obtained thanks to the presence of cell flow processing units, inserted on one side between the line and exchange termination devices providing re-synchronization, extraction of ATM flows from any transmission synchronous supports, label conversion at a virtual path level, conversion into electrical form of the signalling information to be supplied to the control network etc., and the inputs of the interconnection network, and inserted on the other side between the outputs of the interconnection network and the termination devices providing the complementary operations required for inserting the cells again on the transmission carriers. In Fig. 1 the optical interconnection network is indicated by CM, the electrical control network by CT and the line and exchange termination devices respectively associated to input optical connections E1 ... Eh ... Em ... En and to the output connections U1 ... Uh ... Um ... Un by TE1 ... TEh ... TEm ... TEn, TU1 ... TUh ... TUm ... TUn. The termination devices TE, TU are well known in the art and they are not part of the invention and this is why they will not be described in detail. A possible embodiment is anyhow described in EP-A-0 411 562. Outputs 1 (1-1 ... 1n) of the devices TE are connected to units PAC1 ... PACk, each of which receives the cells outgoing from one or more devices TE. In the drawing, in particular, the outputs of the devices TE1 ... TEh are connected to PAC1 and those of the devices TEm ... TEn to PACk. The number of lines connected to the units PAC is the same for all these units. The units PAC comprise, for each of their input lines: means PA (PA1 ... PAh ... PAm ... PAn) forming cell aggregates relevant to the same virtual path, and joining to each aggregate a label, valid inside the cross-connect system, to allow management of aggregates by the control network CT in the same way as the individual cells are usually managed in an ATM switch. means PC (PC1 ... PCh ... PCm ... PCn), performing a time compression of the bits inside the aggregates present on output 2 (2-1 ... 2h ... 2m ... 2n) of the relevant aggregation device, by reducing the duration of each aggregate by a preset factor C. When the number k of the inputs/outputs IN, OU in the interconnection network CM is lower than the number n of the inputs/outputs E, U of the switch, as shown in the example, each unit PAC includes also a multiplexer MU (MU1 ... MUk) cyclically scanning the outputs 3 (3-1 ... 3h ... 3m ... 3n) of all the compression means PC and concentrating the compressed aggregates on these outputs onto an input line IN (IN1 ... INk) to the interconnection network CM. Control signals for multiplexers MU are supplied by the system time base, which is part of the control network CT, through the proper connection wires 4-1 ... 4k, schematizing as a whole the connections for signal exchange between units PAC and control network CT. In a typical embodiment, the cross-connect system can present 512 input/output links E/U and use an interconnection network CM with 64 inputs/outputs; each input link can convey cells related to 10 virtual paths; the aggregates (having the same dimensions) can comprise from 8 to 16 cells. As a result of the aggregation and compression information units are obtained with a duration substantially equal to that of a cell but with contents equal to the sum of the contents of all the cells of an aggregate, and they convey therefore a much greater quantity of information in the time unit. The electrical control network CT will process these information units instead of the individual ATM cells and it will hence not have any special speed requirements and will not set any constraints to the optimal exploitation of the optical interconnection network. The fact that cell aggregates are to be processed instead of individual cells does not imply any modification in this control network, the structure of which is therefore analogous to that already proposed for some prototypes of ATM switches. As a consequence of aggregation and compression, there will be a proportional increase of the necessary bandwidth, which requires the use of an optical technology for interconnection network CM. Time compression factor C (which can be of the same order of magnitude as the number of cells forming an aggregate) will preferably not be lower than the ratio n/k between the cross-connect system inputs and the interconnection network inputs: in this way guard times between aggregates can be left to make interconnection network operations easier. This becomes specially important if a cell and frequency switching is carried out in the cross-connect system, as described in the mentioned paper by A. de Bosio et al. and in EP-A-0 411 562. Outputs OU1 ... OUk of the interconnection network CM are connected to demultiplexers DM1 ... DMk, belonging to respective units PED1 ... PEDk which perform inverse operations of the units PAC. Each demultiplexer DM has one input and as many outputs as the inputs of a multiplexer MU. Outputs 5-1 ... 5h ... 5m ... 5n of demultiplexers DM are connected to respective means PE1 ... PEn for the time expansion of the aggregates, followed in their turn by means PD1 ... PDn for the decomposition of the aggregates into individual cells. Means PD receive from means PE the aggregates to be decomposed through the respective connections 6-1 ... 6n, eliminate the additional label and supply the individual cells on connections 7-1 ... 7n towards the devices TU1 ... TUn. As the number and the position of the bits making up the label are known and the cells have a constant length, the person skilled in the art has no difficulty in realizing a device capable of performing the required functions: e. g. the units PD can be suitably timed registers. Units PED receive the proper control signals from the control network CT through connections 8-1 ... 8k. Units PAC, PED are the processing units for the ATM cell flow which are the subject matter of the invention. In the preferred embodiment which will be described hereafter, cell aggregation is carried out on electrical signals, and compression and concentration operations are carried out on optical signals. Similarly, expansion is carried out optically and decomposition of aggregates in electrical form. Since connections E, U are supposed to be of an optical type, termination devices TE, TU will incorporate the required optical-to-electrical conversion devices and vice versa. This is not an additional complication for the switching system structure since these conversion devices are provided in any case when optical flows on input/output lines are organized as usual according to the standard synchronous digital hierarchy (SDH), because SDH frames are processed in an electrical form. Connections 100, 101 schematize the connections between termination devices TE, TU and the control network CT. Fig. 2 shows a possible embodiment of units PA, PC. Unit PA mainly consists of a bank of FIFO memories (10 in the example considered) MF1 ... MFp, each of which organizes a queue of cells relevant to the same virtual path to form aggregates. Considering that the memories receive cells at random, the writing/reading control units must be able to recognize that the preset number of cells has been written and, once this number is reached, to start reading even if any cell to be inserted into a successive aggregate is still being written. To avoid excessive delays, reading must start in any case after a maximum preset time is out, even if the aggregate is not complete. This maximum time will be counted by a suitable counter, provided in the control network of the memory itself and started when the first cell of an aggregate arrives, by using clock signals supplied by the time base of the electrical control network CT by means of wire 40 belonging to one of the connections 4 in Fig 1. For drawing simplicity, said control units are incorporated into the blocks MF; memories organized to allow these operating procedures are well known in the art. A label valid within the cross-connect system (containing service information in general and information about the aggregate characteristics in particular) will also be added at the head of each aggregate; the label is supplied by TE through the relevant connection 10-1 ... 10p (which is part of line 1 in Fig. 1) and is loaded into the memory when the arrival of the first cell of an aggregate is recognized. This label will generally be used by the decomposition units PD. Service labels of this type are created by the units TE also in the case of conventional ATM cross-connect systems (e. g. that described by A. L. Fox et al. in the paper "RACE BLINT: a technology solution for the broadband local network", presented at IEE Conference on Integrated Broadband Services and Networks, October 1990, London). Cells to be stored come from TE, through a connection 11 (which is also part of line 1) connected to the input of a decoding network DE presenting p outputs respectively connected to memories MF1 ... MFp. Through connection 12, DE receives from TE, as control signals, the label bits of each cell arriving at TE (and therefore the bits of the label which has not undergone conversion yet) which identify the virtual path and, according to such label, it routes the cell towards the proper memory MF. The outputs of memories MF are connected to the inputs of a selector SL the output of which is output 2 of block PA. The selector must act in synchronism with multiplexer MU, and more precisely it must transfer an aggregate to its output at an instant such that, taking into account the time required for compression, the aggregate is present on output connection 3 of the concerned block PAC at the moment when MU is scanning the connection itself. The aggregate which SL must transfer to the compression means PC will be the or an aggregate ready in one of the memories MF (e. g. the first one completed) or the or an aggregate for which maximum hold time in memory has already expired. The selector will then be associated to a control logic LC receiving from the control networks of the individual memories MF signals indicating that an aggregate has been formed or that the preset time has expired. Alternatively the different selector inputs can be cyclically scanned. It is to be noted that data will be generally written and read in parallel (e. g. on 8 bits) in memories MF. Considering that compression units, as it will later be better examined, must act on one bit at a time, devices for the parallel-to-series conversion of the information flows must be provided. In the drawing, these devices have been incorporated into block SL, which will receive the necessary timing signals from the time base through connection 41. Obviously serialization could be carried out upstream of SL. The formation of aggregates of 8 - 16 cells, as supposed by way of example, allows a significant reduction of the number of information units to be processed in CM without increasing remarkably the delay across the cross-connect system. The necessity of limiting the delay advises to use the invention at the level of a cross-connect system because at this level the traffic concerning a virtual path will be sufficiently high to allow reaching in relatively short times the number of cells desired for an aggregate. Anyhow, in theory, the invention could be used in any switching node, by forming cell aggregates which have to follow the same path in the interconnection network CM. Serialized aggregates, consisting of bit strings where each bit has the same duration and period as the bits of the cells present on connections E, are supplied to electro-optical conversion means and to the bit time compression unit included, in the drawing, in block PC. Block PC comprises: a mode locked laser LA, generating a succession of pulses with a duration much lower than that of the bits present on connection 2 and a period equal to the bit time To of these bits; an electro-optical amplitude modulator MD, which receives the pulses from laser LA and the signal present on connection 2, and in which each bit of this signal modulates the pulses outgoing from laser LA with an on/off modulation; in this way an optical signal consisting of a succession of bits having a duration which is equal to that of the pulses emitted by LA and a period To is obtained; a succession of c elements RP1 ... RPc (with 2 c = C), each of which effects the folding on itself of the bit string relevant to an aggregate, halving its duration each time. As indicated for RP1, each element RP comprises an input coupler A1, sharing the power associated to each optical bit between two different paths, and an output coupler A2 recombining the signals coming from the two paths. An output of the input coupler Al and an input of the output coupler A2 are directly connected and form one of the two paths; the second path is obtained by connecting the second output of A1 to the second input of A2 through a delay element R which causes the bits in the second half of the aggregate to be arranged interleaved with the bits of the first half in the output coupler A2. If y is the number of bits in each aggregate, this is obtained if the delay element R in the first folding element RP1 introduces a delay of (y-1)To/2 with respect to the signals sent along the other path, that of the second folding element RP2 introduces a delay of (y-1)To/4, etc. In general, the delay element of the i-th folding element RPi will introduce a delay (y-1)To/2 i . As a consequence of the forwarding of the bits of an aggregate on two paths and of the successive recombination, at the output of each folding element RP1 ... RPc each aggregate will be associated to a replica. Hence each element RP will be followed by a unit, schematized by switches SW1 ... SWc, which will be operated to eliminate this replica, as it will better be seen further on. These switches are controlled by signals supplied by the control network through connections 43-1 ... 43c, which are part of the proper connection 4 in Fig. 1. Units such as SW1 ... SWc are well known in the art, and hence further information is unnecessary. On output 3 of unit PC there is therefore a succession of aggregates with an overall duration yTo/2 c and period yTo. From the foregoing description it can be clearly seen that once the compression factor is established, it is immediate to determine the instant of the exit of the aggregates from memories MF in such a manner that the aggregates reach multiplexer MU within the time devoted to that particular line 3. During the interval between two aggregates, multiplexer MU will forward on line IN the compressed aggregates supplied by the other units PC of the same block PAC. The compressed aggregates on lines IN are then switched inside CM with the procedures required by the particular network. It is to be noted that at the instant when an aggregate is forwarded to the interconnection network CM, the line and exchange termination devices TE will forward to the control network CT the necessary routing information via line 100: as a matter of fact such information should not undergo compression as the control network would not be able to read them. Operation of unit PC is shown in Figures 3a-3e considering by way of example the case of an aggregate with y = 8 bits to be time compressed by a factor C = 4; two foldings are therefore required. Fig. 3a shows schematically the aggregate to be compressed, formed by bits the duration of which is substantially equal to period To. Figure 3b shows the aggregate converted into optical form, with bits having period To and a strongly reduced duration, arriving at input of coupler A1 of RP1 and, on the one hand, propagating towards A2 without undergoing delays in RP1. On the other hand, the delay element R1 of RP1 introduces a delay 7To/2, by giving the sequence in Fig. 3c: as it can be seen, bit 1 outgoing from R1 occurs at half the interval between bits 4 and 5 of the non delayed sequence (and therefore at the central instant of the duration of the aggregate); bit 2 outgoing from R1 occurs at half the interval separating the arrival of bits 5 and 6 of the non delayed sequence, etc. At the output of RP1 (Fig. 3d), an initial group of bits (bits 1 - 4 of the non delayed aggregate) is followed by a sequence of bits in which the bits of the second half of the original aggregate are interleaved with those of the first half, and this sequence is still followed by a queue of bits consisting of bits 5 - 8 of the delayed sequence. Bit period is T1 = To/2. The initial group (head) and the queue, indicated as a dashed line in Fig 3d, must be eliminated and for this purpose switch SW1 must be closed for a time substantially equal to yTo/2 (duration of compressed aggregate) starting from the instant when the first bit of the aggregate exits from the delay element R of folding element RP1: considering as instant 0 that when the aggregate to be compressed arrives at the input of RP1, the closure of SW1 must substantially take place after a time 7To/2. In the successive folding element RP (RP2), the delay element introduces a delay equal to 7To/4, i. e. 7/2 of the bit time of the aggregate already compressed by RP1: the first bit of the delayed sequence will reach the input of the output coupler A2 at half the interval separating bits 6 and 3 of the non delayed sequence (and therefore again in correspondence with central instant of the duration of the aggregate). In this way the bits in the second half of the aggregate are interleaved again with those of the first half of the aggregate that is entering into the element. At the output of the second folding element the sequence shown in line 3e is obtained, with a duration equal to 1/4 of the original one. Also in this case it will be necessary to eliminate by means of the switch following RP2 the head (bits 1, 5, 2, 6 of the non delayed sequence) and the queue (bits 3, 7, 4, 8 of the delayed sequence) of the bit flow outgoing from RP2: neglecting the propagation time between the output of SW1 and the input of RP2, SW2 will be closed for a time equal to yTo/4 starting from an instant that follows by 7To/4 the arrival of the first bit of the non delayed sequence. These head and queue are not shown any more in Fig. 3e. If C > 4 (and hence c > 2) the operations are repeated identically in the successive folding units and after c foldings, the bit period will be Tc=To/2 c . Comparing lines 3b and 3e, it can be seen clearly that the signal present at the output of a unit PC consists of very short sequences of bits which occupy only a fraction 1/2 c of the original duration of the aggregate. This explains the use of multiplexer MU (Fig. 1), which inserts into the unused time the compressed aggregates relevant to other input lines of the same unit PAC. Referring to Fig. 4, cell aggregates present at output 5 of a demultiplexer DM (Fig. 1) are supplied at the input of an expander ES which has C outputs and are transferred simultaneously on C lines 50-1 ... 50C, which terminate at the inputs of the respective gates CA1 ... CAC, sampling with period To the bit strings present on the respective line 50. Control signals for gates CA are supplied by the control network CT through a line 80 which is part of one of the connections 8 in Fig. 1. Also the realization of gates such as gates CA is well known in the art, and hence further information is unnecessary. Lines 50 have lengths which are different and progressively increasing from line 50-1 to line 50C and so they introduce a progressively increasing delay on the signals conveyed. For what concerns the invention, the interest lies in the relative delay between one line and the line preceding it, which must be equal to the period Tc of the compressed bits. The minimum delay (line 50-1) can therefore be considered as equal to 0, while the generic line 50j (j=1 ... C) will introduce a delay (j-1)Tc. Outputs of gates CA1 ... CAC are connected through respective lines 60-1 ... 60C to an integrator-detector IR which effects an integration in time of the bits received and their conversion into electrical form, so as to reconstruct cell aggregates corresponding to those outgoing from blocks PA (formed therefore by bits with period and duration To). In practice IR will be made up of a unit reconstituting the bit sequence and of an optical-to-electrical converter. Lines 60 have also different lengths, in order to introduce different delays on the bits conveyed. The delay introduced by each line is a multiple of the overall duration y.Tc of a compressed aggregate and it is progressively increasing, by steps of y.Tc, from line 60C to line 60-1. More particulary, the delay will vary from 0 (line 60C) to (C-1)·y·Tc (line 60-1) and, for the generic line 60j, it will be (C-j)·y·Tc. The reasons for the choice of the given values for the delay introduced by lines 50, 60 will appear clearly from the description of the operation of unit PE, with reference to Fig. 5. Here the expansion of the 8-bit aggregate compressed by a factor C = 4 as shown in Fig. 3 has been shown by way of example. Fig. 5a shows the situation of the aggregates on lines 50-1 ... 50-4 at the input of the sampling gates CA, Fig. 5b the situation on lines 60-1 ... 60-4 at the output of the same gates. The first sampling pulse CK0 for the aggregate being examined reaches gates CA at the moment when bit 1 of the aggregate is present at the input of gate CA connected to line 50-4; due to the various delays introduced by lines 50-2 ... 50-4 with respect to line 50-1, at the same instant bits 7, 5, 3 are present respectively on lines 50-1, 50-2, 50-3. The second sampling pulse CK1, which arrives after time To = 4Tc, lets bits 8, 6, 4, 2 pass at the outputs of gates CA1 ... CA4: on the four lines 60 four distinct pairs of bits, each comprising bits that were adjacent in the original aggregate, propagate towards the integrator. The bits of each pair are spaced by the original bit time. Line 60-4 is the one with the least delay and therefore bit 1 is effectively the first bit reaching the input of integrator IR. The immediately preceding line 60-3 introduces a delay of 8Tc (= 2To), and therefore, before a bit present on this line reaches integrator IR, this receives bit 2 from line 60-4. After a time 2To passes, IR will receive bit 3 followed by bit 4, and so on; the original sequence of the bits has therefore been reconstituted at the input of IR. Integrator IR will then bring each bit back to its original duration and convert it into electrical form, giving the sequence in Fig. 5c, which reproduces exactly the one present at the input of unit PC. It is to be noted that the above described expansion scheme requires the overall length of the aggregates, expressed by the number of bits, to be a multiple of compression factor C. This does not constitute a limitation because it is sufficient to choose suitably the number of cells in the aggregate, if the length of same does not satisfy this condition. It is clear that what described has been given only by way of non limiting example and that variations and modifications are possible without going out of the scope of the invention. So, for example, multiplexers MU can be replaced by passive combining devices, receiving in a sequential way the compressed aggregates outgoing from one group of compression means PC. Obviously, the demultiplexers DM will be then replaced by complementary passive distribution units. In this case it will be the time base to establish the reading instant of the various aggregates in memories MF so that they arrive at the inputs of the multiplexing unit with the required sequence. Moreover, the folding elements RP could be realized so as to form a number of replicas of the aggregate different from 2, e. g. 3, 5, etc ... , obtained by delaying the input aggregate by multiples of To/3, To/5 ... ., so that compression ratios will be obtained which are powers of 3, 5, etc. In this case, if z is the number of replicas formed, the delay element R constituting the x-th path inside the i-th element of the succession of folding elements will have to introduce a delay of (x-1) (y-1)To/z i on the signals that run across it.

Claims: An optical switch for fast cell switching networks, comprising an optical interconnection network (CM) having optical inputs (IN1 ... INk) and outputs (OU1 ... OUk), an electrical control network (CT) controlling the optical interconnection network (CM), input and output termination devices (TE1 ... TEn, TU1 ... TUn) associated to each input (E1 ... En) and each output (U1 ... Un) of the switch, respectively, input and output converter means (LA,MD;IR) for the conversion of electrical signals supplied from the input termination devices (TE1 ... TEn) into optical signals to be supplied to the optical interconnection network (CM) and of optical signals supplied from the optical interconnection network (CM) into electrical signals to be supplied to the output termination devices (TU1 ... TUn), respectively, and time compression and re-expansion means (PC, PED) for the time compression of the signals to be switched and the time re-expansion of switched signals, respectively, characterized in that: the input termination devices (TE1 ... TEn) split the signals to be forwarded to the electrical control network (CT) from those to be switched in the interconnection network (CM) , and the output termination devices (TU1 ... TUn) recombine the signals coming from the control network (CT) and the interconnection network (CM) ; between each input termination device (TE1 ... TEn) and the interconnection network (CM) aggregation and compression means (PAC1 ... PACk) are arranged containing an aggregation unit (PA) followed by said time compression means (PC), the aggregation unit (PA) comprising: a decoding network (DE), presenting a data input at which it receives the cells to be switched, coming from an input line (E1 ... En) of the switch, and a plurality of outputs, each associated to a different path, the decoding network (DE) forwarding each cell on an output selected according to information, taken from said cells and supplied to a control input, which codes the path the cell refers to; a plurality of memories (MF1 ... MFp), each of which is associated to an output of the decoding network (DE) and organizes a queue of the cells present on said output to form cell aggregates, each memory (MF1 ... MFp) being associated to control units for the writing/reading, which cause reading whenever a pre-determined number of cells has been written or after a maximum preset time; and a selector (SL) presenting a plurality of inputs each connected to the output of one of the memories (MF) and an output on which the aggregates to be forwarded to the compression means (PC1 ... PCn) are presented; thereby forming cell aggregates by associating a plurality of cells which must follow the same path through the interconnection network (CM) and performing said time compression by acting on the aggregates, in order to form information units the duration of which is equal to a pre-set fraction of the original duration of an aggregate and the information contents of which, as number of bits, is equal to the sum of the information contents of the aggregated cells; the electrical control network (CT) is adapted to manage switching, through the optical interconnection network (CM), at cell aggregates level; and the means (PED1 ... PEDk) for the time re-expansion, bringing back to the original duration the aggregates outgoing from the interconnection network (CM), are adapted to separate the individual cells before forwarding them to the output termination devices (TU1 ... TUn). A switch according to claim 1, characterized in that the time compression means (PC) are arranged between input converter means (LA,MD) and the interconnection network (CM), and the time re-expansion means (PED) are arranged between the interconnection network (CM) and the output converter means (IR). A switch according to claim 1 or 2, characterized in that: the number k of inputs/outputs (IN1 ... INk, OU1 ... OUk) of the optical interconnection network (CM) is lower than the number n of inputs/outputs (E1 ... En, U1 ... Un) of the switch; each of the aggregation and compression means (PAC1 ... PACk) comprises means (MU1 ... MUk) for multiplexing, on each input line (IN1 ... INk) of the interconnection network (CM), the compressed aggregates of cells relevant to a plurality of inputs (E1 ... Eh) of the switch connected to one and the same aggregation and compression means (PAC1 ... PACk); and the re-expansion means (PED1 ... PEDk) include means (DM1 ... DMk) for distributing the compressed aggregates present on the same output of the interconnection network (CM) among a plurality of outputs (U1 ... Un) of the switch. A switch according to any of claims 1 to 3, characterized in that said switch is an ATM digital cross-connect system and the aggregation and compression means (PAC1 ... PACk) form aggregates comprising a preset number of cells relevant to a same virtual path. A switch according to any of claims 1 to 4, characterized in that each memory (MF1 ... MFp) is associated to means for joining to each aggregate a local label, generated by said input termination devices (TE1 ... TEn) and containing service information. A switch according to any of claims 1 to 5, characterized in that the input converter means (LA, MD) and the compression means (PC1 ... PCn) comprise: a mode locked laser (LA), which generates a succession of pulses having a duration (Tc) which is much less than that of the bits of the cell aggregates outgoing from the said selector (SL), and a period (To) equal to the period of the said bits; an electro-optical amplitude modulator (MD), which receives the pulses emitted by the laser (LA) and the bits of the aggregates outgoing from the selector (SL), and amplitude modulates with said bits the pulses emitted by the laser (LA), the modulator emitting an optical signal consisting of a succession of bits with duration (Tc) equal to that of the pulses and period (To) equal to that of the bits of the aggregates; a succession of folding elements (RP1 ... RPc), which receives the signals outgoing from the modulator (MD), and in which each element causes the interleaving between the bits of the first part of an aggregate of the bits in the remaining part or parts of the aggregate itself, so as to reduce the duration of the aggregate to a fraction of the original duration, the output of the succession being connected to an input of a multiplexing means (MU1 ... MUn). A switch according to claim 6, characterized in that each folding element (RP1 ... RPc) comprises: an input coupler (A1) which shares the power associated with each optical bit among a number of outputs associated with as many different paths and forms on each path a replica of the input aggregate; an output coupler (A2) which presents as many inputs as the number of said paths, recombines the replicas present on said paths and has a first input directly connected to a first output of the input coupler to form one of said paths; delay elements (R) inserted between each of the other outputs of the input coupler (A1) and one input of the output coupler (A2) to form one of the other paths, the delay element (R) which constitutes the x-th path introducing a delay of (x-1)(y-1)To/z i on the signals which run across it, where: y is the number of bits in an aggregate; To is the bit period before compression; z is the number of paths; i, 1 ≤ i ≤ c, is the serial number of the folding element in the succession. A switch according to claim 7, characterized in that each folding element (RP1 ... RPc) is apt to halve the duration of an aggregate, wherein: the input coupler (A1) is adapted to share the power associated with each optical bit between two outputs; the output coupler (A2) is adapted to recombine the signals present on the two paths; the delay element (R) is inserted between the second output of the input coupler (A1) and the second input of the output coupler (A2) to form the second path, and introduces a delay (y-1)To/2 i on the signals which run across it. A switch according to claims 7 or 8, characterized in that each folding element (RP1 ... RPc) is followed by a switch (SW) which is closed, for the time corresponding to the duration of an aggregate outgoing from the element, starting from the moment when the first bit of the aggregate exits from the delay element (R), in order to eliminate redundant parts of the replicas of the aggregate. A switch according to any claims of 6 to 9, characterized in that the multiplexing means (MU1 ... MUn) are adapted to scan cyclically the outputs of the compression means (PC) connected to them, and said selector (SL) is associated to a control logic network (LC) which causes transfer to output of an aggregate in synchronism with the operation cycle of the multiplexing means (MU1 ... MUn), in such a way that a compressed aggregate is present at an input of the multiplexing means (MU1 ... MUn) in the time interval designed for the scanning of such input. A switch according to any of claims 6 to 9, characterized in that the multiplexing means (MU1 ... MUn) consist of passive recombining devices, and the control logic (LC) of said selector (SL) is slaved to a time base of the control network (CT) of the switch to cause transfer to output of a compressed aggregate so that it reaches an input of the multiplexing means at a preset instant. A switch according to claims 10 or 11, characterized in that the line and exchange termination devices (TE1 ... TEn) are slaved to a time base of the control network (CT) so as to supply to it the information about the routing of a compressed aggregate in synchronism with the arrival of the aggregate itself to the interconnection network. A switch according to any preceding claim, characterized in that the means (PED1 ... PEDk) for the re-expansion of the aggregates comprise, for each output line (U1 ... Un) of the switch, a unit (PE1 ... PEn) for time re-expansion of the bits of the aggregates and their conversion into electrical form, followed by a unit (PD1 ... PDn) for cell separation acting on electrical signals, and in that the re-expansion and conversion unit (PE1 ... PEn) comprises: an expander (ES), which has an input connected to an output of a respective means (DM) for distributing the compressed aggregates and has a plurality of outputs, in a number equal to a time compression factor by which the duration of the aggregates has been reduced in the compression means (PC1 ... PCn), and which presents on all its outputs the bits constituting the received aggregate; a first group of lines (50-1 ... 50C), which are connected each to an output of the expander and have lengths that are different and progressively increasing from a first line (50-1) to a last one (50C), so as to introduce a progressively increasing delay on the signals conveyed; a group of sampling gates (CA1 ... CAC), each one having an input connected to one of the lines of the first group (50-1 ... 50C), and sampling bit aggregates propagating on said lines with a period equal to the bit time of the non compressed aggregates, in order to form distinct groups of bits which are consecutive in the original aggregate; a second group of lines (60-1 ... 60C), which are connected each to the output of one of said gates and have lengths that are different and progressively decreasing from a first line (60-1) to the last one (60C), so as to introduce on the signals conveyed a progressively decreasing delay such that said signals arrive at the end of the respective lines at such instants as to allow the reconstruction of the succession of the bits in the aggregate received by the re-expansion and conversion unit (PE1 ... PEn); a detector (IR) which forms the output converter means and which: has a plurality of inputs connected to the lines of the second group (60-1 ... 60C) ; reconstitutes the succession of bits, and performs their conversion into electrical form and an integration in the time, reconstituting cell aggregates in which the bits have their original duration. A switch according to claim 13, characterized in that the lines of the first group (50-1 ... 50C) have such lengths that each of them introduces, on the signals conveyed, a delay exceeding by a quantity equal to the period of the compressed bits the delay introduced by the preceding line, and the lines of the second group (60-1 ... 60C) have such lengths that each of them introduces on the signals conveyed a delay exceeding by a quantity equal to the duration of a compressed aggregate the delay introduced by the successive line.

Inventors: BOSTICA BRUNO, CINATO PAOLA, DE BOSIO ALFREDO, BOSTICA, BRUNO, CINATO, PAOLA, DE BOSIO, ALFREDO
Applicants: CSELT CENTRO STUDI LAB TELECOM, CSELT CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A.
Application year: 1993
Main classification: H04Q11
IPC codes: H04Q11, H04Q3, H04L12