Semiconductor memory device and method of fabricating the same

Abstract: A semiconductor device includes a first N-type region (18) formed in a P-type silicon substrate (10), trenches (12₁ - 12 N ) formed in the substrate (10), second N-type regions (14₁ - 14 N ) each formed from at least the bottom of a corresponding one of the trenches (12₁ - 12 N ) into the substrate (10), these second N-type regions (14₁ - 14 N ) contacting each other to constitute a wiring layer (16) and being also in contact with the first N-type region (18), and an electrode (20) for applying a predetermined potential to the second N-type regions (14₁ - 14 N ) via the first N-type region (18). Since a potential is supplied to the wiring layer (16) formed in the substrate (10) via the first N-type region (18), no special design, such as formation of a terminal trench, is required. A potential can be easily supplied to the wiring layer (16) formed in the semiconductor substrate (10), and the device can be easily fabricated.

Description: The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device with an internal wiring layer and a method of fabricating the same. In particular, the semiconductor device comprises: a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type formed in said semiconductor substrate, said first semiconductor region being a deep well-like region; a plurality of trenches formed adjacent to each other with a predetermined depth and intervals in said semiconductor substrate, a plurality of second semiconductor regions of the second conductivity type each formed from at least the bottom of a corresponding one of said plurality of trenches into said semiconductor substrate, said second semiconductor regions contacting each other to constitute a wiring layer and being also in contact with said first semiconductor region, and an electrode, electrically connected to said first semiconductor region, for applying a predetermined potential to said second semiconductor regions via said first semiconductor region. Such a semiconductor device is disclosed in GB-A-2 215 913. A trench capacitor structure for supplying a potential to the plate electrodes of adjacent trench capacitors is known from JP-A-63 136 559. Reference is also made to GB-A-2 199 695 which discloses a dynamic random access memory (DRAM) having a peripheral control circuit in a shallow well of the same conductivity type as the substrate. Conventional examples of a semiconductor device with a wiring layer in a semiconductor substrate are a dynamic RAM cell disclosed in "A 4.2 µm 2 Half-Vcc Sheath-Plate Capacitor DRAM Cell with Self-Aligned Buried Plate-Wiring" T. Kaga et al., International Electron Devices Meeting Technical Digest, 1987, pp. 332 to 335 and a dynamic RAM cell disclosed in "Semiconductor Memory Having Trench Capacitor Formed With Sheath Electrode" United States Patent 4,918,502 to T. Kaga et al. Each DRAM cell disclosed in the above literature has an N-type diffusion layer formed by diffusion into a P-type substrate from the bottom of each trench formed in the P-type substrate. These N-type diffusion layers are electrically connected with each other by contacting each other to thereby constitute a wiring layer inside the substrate. This wiring layer in the above DRAM cell functions as a wire for applying a potential to the plate electrode of a capacitor. In this DRAM cell, however, the wiring layer is formed inside the substrate. Therefore, applying a potential to this wiring layer requires a specific design: one of trenches is caused to serve as an exclusive terminal for the potential supply. For this reason, in the above cell, one trench is caused to serve as a terminal (to be referred to as a "terminal trench" hereinafter) as follows. An oxide film is formed on the side walls of a trench in order to constitute a so-called "sheath capacitor." In the terminal trench, this oxide film is removed by photolithography and an N-type diffusion layer is formed on the entire surfaces of the trench. This N-type diffusion layer is formed in contact with N-type diffusion layers formed by diffusion from the bottoms of the other trenches to together serve as a wiring layer. A potential is supplied to these N-type diffusion layers serving as a wiring layer from the diffusion layer formed on the entire surfaces of the terminal trench. The device of this type is described in, e.g., U.S.P. 4,918,502 with reference to Figs. 10D to 10N. In a semiconductor device having a wiring layer inside a semiconductor substrate, it is not easy to apply a potential to the wiring layer. To supply a potential, therefore, a special design such as formation of a terminal trench 1 as shown in Figs. 1 and 2 is used. This requires an additional photolithography step or the like, and the result is complexity in the whole fabrication process. Especially in formation of the terminal trench 1, a resist 5 must be removed from the terminal trench 1 in order to selectively remove an oxide film 6 on the side surfaces of the trench 1. In this case, if misalignment of patterns occurs as indicated by a resist 5' in Fig. 1, a disconnected portion 8a is formed between an N-type diffusion layer 8 around the terminal trench 1 and an N-type diffusion layer 7 at the bottom of a trench 2, preventing these diffusion layers from making contact with each other. In addition, it is highly probable that the resist 5 is not completely removed but left behind in the terminal trench 1. If the resist 5 remains in the terminal trench 1, the oxide film 6 is not completely removed, and an unremoved portion 6a remains on the wall surface of the terminal trench 1, as shown in Fig. 2. This residual oxide film 6a acts as a diffusion mask to cause, e.g., a diffusion error 8b. The diffusion error 8b introduces problems such as a disconnection in the N-type diffusion layer 8 or an increase in contact resistance between the wiring layer and the terminal. In addition, if the resist remains in the terminal trench, harmful impurities (such as heavy metals) contained in the resist may diffuse into the device to contaminate it. Note that reference numeral 3 denotes an element isolating SiO 2 film; 4, an Si 3 N 4 film; and 10, a P-type semiconductor substrate. The present invention has been made in consideration of the above situation and has its object to provide a semiconductor device with a structure, in which a potential can be easily supplied to a wiring layer formed in a semiconductor substrate, and which can be easily fabricated, and a method of fabricating the same. According to an aspect of the present invention, there is provided a semiconductor device as defined in claim 1. According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps set out in claim 8. Further features of the invention are set out in the dependent claims. This invention can be more fully understood from the following detailed description given by way of example and when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic sectional view for explaining a drawback of a conventional semiconductor device; Fig. 2 is a schematic sectional view for explaining another drawback of a conventional semiconductor device; Fig. 3 is a sectional view showing the arrangement of a semiconductor device that is not according to the present invention but included for a fuller understanding thereof; Fig. 4 is a sectional view showing the arrangement of a semiconductor device not according to the present invention but included for a fuller understanding thereof; Figs. 5A to 5C are sectional views for explaining the arrangement of a semiconductor device according to an embodiment of the present invention; and Figs. 6A-I to 6G-III are sectional views for explaining a method of fabricating the semiconductor device according to the embodiment of the present invention. The embodiment of a semiconductor device and a method of fabricating the same according to the present invention will be described below with reference to the accompanying drawings. Fig. 3 is a sectional view showing the arrangement of a semiconductor device not according to the present invention. As shown in Fig. 3, trenches 12 1 to 12 N are formed in, e.g., a P-type silicon substrate 10. In the substrate 10, N-type diffusion layers 14 1 to 14 N are formed from the bottoms of the trenches 12 1 to 12 N , respectively, by ion implementation or diffusion of an impurity. The N-type diffusion layers 14 1 to 14 N are electrically connected to each other by contacting each other, thereby constituting a buried wiring layer 16 formed inside the substrate 10. In addition, a well-like N-type region 18 is formed in the substrate 10 by ion implantation or by diffusing an impurity from the surface of the substrate 10. This N-type region 18 serves as a potential extracting electrode. This N-type region 18 is electrically connected to the wiring layer 16 and is also electrically connected to an electrode layer 20. Although not shown, an element such as a capacitor having an electrode electrically connected to the wiring layer 16 is formed in each of the trenches 12 1 to 12 N . According to the semiconductor device with the above arrangement, a potential is supplied from a power supply to the wiring layer 16 via the electrode layer 20 and the N-type region 18. This makes potential supply to the wiring layer 16 feasible without forming any special structure, such as a terminal trench, unlike in conventional structures. In addition, the N-type region 18 can be formed not through a complicated step, such as removal of a resist from a trench, but by ion implantation or diffusion of an impurity from the surface of the substrate 10, so the formation of this region is easy. This can reduce occurrence of errors in fabrication and consequently can prevent a reduction in yield of devices. Furthermore, the N-type region 18 can be formed simultaneously with formation of an N-type well region (not shown) or an N-type collector extracting region (not shown) used in a vertical bipolar transistor. This simultaneous formation of the N-type region 18 and the N-type well region or the N-type collector extracting region can suppress an increase in the number of fabrication steps. Fig. 4 is a sectional view showing the arrangement of a semiconductor device useful for understanding the present invention. As shown in Fig. 4, at least one trench 12 0 is formed in a well-like N-type region 18 by the same fabrication steps as for other trenches 12 1 to 12 N . According to the semiconductor device with this arrangement, even if mask misalignment occurs in the formation of the trenches 12 0 to 12 N , contact between the N-type region 18 and a wiring layer 16 can be maintained because an N-type diffusion layer 14 0 at the bottom of the trench 12 0 exists in the N-type region 18. This ensures electrical connection between the N-type region 18 and the wiring layer 16 at any instant. Figs. 5A to 5C are sectional views for explaining the arrangement of a semiconductor device according to the embodiment of the present invention. In the embodiment, a semiconductor device according to the present invention is applied to a dynamic RAM with a sheath capacitor and a peripheral circuit constituted by a CMOS circuit. Fig. 5A is a sectional view showing the device according to the embodiment, Fig. 5B is an enlarged view showing a portion near a buried wiring layer connecting portion b in Fig. 5A, and Fig. 5C is an enlarged view showing a portion near a sheath capacitor portion c in Fig. 5A. N-type wells 18 1 and 18 2 , an N-type well 22, and a P-type well 24 1 are formed in a P-type silicon substrate 10, and a P-type well 24 2 is formed in this N-type well 18 2 . In a memory array formation portion of the N-type well 18 1 and a P-type well 24 1 , a memory cell having a cell transistor, that includes an electrode layer 88 1 for supplying a potential from a first potential source (V bb ), and sheath capacitors supplied with a potential from an electrode layer 20 via the extracting electrode layer 18 1 end a buried wiring layer 16 are formed. A peripheral circuit PMOS having an electrode layer 88 2 for supplying a potential from a second potential source (V cc ) is formed in the N-type well 22. A peripheral circuit NMOS having an electrode 88 3 for supplying a potential from a third potential source (V ss ) is formed in the P-type well 24 2 . As shown in Fig. 5B, the buried wiring layer 16 is constituted by N-type impurity-diffused layers 14 0 to 14 N formed in contact with each other at the bottoms of trenches 12 0 to 12 N , respectively. A portion each of the diffusion layers 14 0 to 14 N is formed in the extracting electrode layer 18 1 . As shown in Fig. 5C, the sheath capacitors are constituted by a plate electrode 38, a storage node electrode 42, and a dielectric film 40 formed between them, all formed in the trenches 12 0 to 12 N . Figs. 6A-I to 6G-III are sectional views for explaining a method of fabricating the semiconductor device according to the embodiment of the present invention. First, as shown in Fig. 6A-I, deep N-type well regions 18 1 and 18 2 are formed in a P-type silicon substrate 10 by, e.g., ion implantation and diffusion. Subsequently, an N-type well 22 and P-type wells 24 1 and 24 2 are formed in the substrate 10 by, e.g., ion implantation and diffusion. A field oxide film 26 is formed on the substrate 10 by, e.g., a LOCOS process. Fig. 6A-II is an enlarged view showing a portion near a buried wiring layer connecting portion b , and Fig. 6A-III is an enlarged view showing a portion near a sheath capacitor portion c . This will be the same in the following description. As shown in Figs. 6B-I to 6B-III, a thin silicon oxide (SiO 2 ) film 28 is formed on the substrate 10 by using, e.g., a thermal oxidation process or a CVD process. Subsequently, a silicon nitride (SiN x ) film 30 is formed on the oxide film 28 by, e.g., the CVD process. A plurality of trenches 12 0 to 12 N about 3 µm in depth are formed adjacent to each other with predetermined intervals between them in the substrate 10 by, e.g., photolithography and RIE. The trenches 12 0 to 12 N are formed particularly in a memory cell array formation portion of the substrate 10, i.e., a region where the P-type well 24 1 is formed. The trenches 12 0 to 12 N are so formed as to reach the substrate 10 through the edge of the field oxide film 26 and the P-type well 24 1 , and at least one trench 12 0 is formed in the deep N-type well 18 1 . Subsequently, a silicon oxide (SiO 2 ) film 32 with a thickness of about 50 nm is formed on the entire upper surface of the substrate 10 by using, e.g., the CVD process. The silicon oxide film 32 is then etched back by RIE to remain on only the side walls of the trenches 12 0 to 12 N . The results are cylindrical portions consisting of the silicon oxide film 32 about 50 nm thick. Subsequently, an N-type impurity, such as phosphorus (P), is doped at a dose of about 1 × 10 16 cm -2 by, e.g., ion implantation. Consequently, N-type impurity-implanted regions 34 0 to 34 N are formed in portions of the substrate 10 exposed to the bottoms of the trenches 12 0 to 12 N , respectively. This ion implantation step is performed by using the nitride film 30 and the side-wall insulating film 32 as masks. As shown in Figs. 6C-I to 6C-III, a phosphorus-doped N-type polysilicon film 38 is formed on the entire upper surface of the substrate 10 including the side and bottom surfaces of the trenches 12 0 to 12 N by using, e.g., the CVD process. Subsequently, annealing is performed to activate the phosphorus present in the impurity-implanted regions 34 0 to 34 N , forming N-type diffusion layers 14 0 to 14 N . These diffusion layers 14 0 to 14 N are so diffused into the substrate 10 as to contact each other, thereby constituting a buried wiring layer 16. The wiring layer 16 is also formed in contact with the deep N-type well 18 1 and is consequently electrically connected with the N-type well 18 1 . Subsequently, a photoresist is coated on the entire upper surface of the substrate 10. The photoresist is then exposed to the middle levels of the trenches 12 0 to 12 N by full-surface exposure, and the exposed portion of the photoresist is removed. The result is a photoresist layer 36 buried to the middle levels of the trenches 12 0 to 12 N . Subsequently, the polysilicon film 38 is removed by using the photoresist layer 36 as a mask. As a result, as shown in Figs. 6C-II and 6C-III in an enlarged scale, polysilicon films 38 0 to 38 N formed to the middle levels of the trenches 12 0 to 12 N are obtained. The polysilicon films 38 0 to 38 N are electrically connected to the wiring layer 16 to serve as the plate electrodes of sheath capacitors. As shown in Figs. 6D-I to 6D-III, the photoresist layer 36 formed on the bottoms of the trenches 12 0 to 12 N is removed. Thereafter, a stacked insulating film 40 consisting of an oxide film (SiO 2 ) and a nitride film (SiN x ) and having a thickness of about 5 nm, as a thickness of an oxide film, is formed on the polysilicon films 38 0 to 38 N by using, e.g., the CVD process or a thermal oxidation/thermal nitriding process. This stacked insulating film 40 serves as the dielectric film of a sheath capacitor. Subsequently, a phosphorus-doped N-type polysilicon film 42 is formed on the entire upper surface of the substrate 10 by, e.g., the CVD process. This polysilicon film is then etched back to remain to the middle levels of the trenches 12 0 to 12 N . Consequently, polysilicon films 42 0 to 42 N are formed. These polysilicon films 42 0 to 42 N serve as the storage-node electrodes of sheath capacitors. Subsequently, a photoresist 44 is coated on the entire upper surface of the substrate 10. Windows 46 1 and 46 2 are formed in portions of the photoresist 44, which serve as storage-node connecting portions. As shown in Fig. 6D-III, the sheath (SiO 2 ) 32 and the stacked insulating film 40 are partially removed by RIE by using the photoresist 44 and the polysilicon films 42 N-1 and 42 N as masks. The results are storage-node connecting portions 48 1 and 48 2 in which the P-type well 24 1 is exposed to the side surfaces of the trenches 12 N-1 and 12 N . As shown in Figs. 6E-I to 6E-III, after the photoresist 44 is removed, an N-type impurity, such as phosphorus (P) or arsenic (As), is doped from the connecting portions 48 1 and 48 2 into the well 24 1 by the use of, e.g., ion implantation. As a result, N-type regions 50 1 and 50 2 are formed in the P-type well 24 1 . Subsequently, a phosphorus-doped N-type polysilicon film 52 is formed on the entire upper surface of the substrate 10 by using, e.g., the CVD process. This polysilicon film is then etched back to remain to the middle levels of the trenches 12 0 to 12 N , thereby forming polysilicon films 52 0 to 52 N . The N-type regions 50 1 and 50 2 and the polysilicon films 42 N-1 and 42 N are electrically connected with each other via the polysilicon films 52 N-1 and 52 N , respectively. Note that the N-type regions 50 1 and 50 2 may also be formed by diffusion of an impurity from the polysilicon films 52 N-1 and 52 N , respectively. As shown in Figs. 6F-I to 6F-III, the surface regions of the polysilicon films 52 0 to 52 N are oxidized by, e.g., thermal oxidation by using the nitride film 30 as a mask, thereby forming silicon oxide (SiO 2 ) films 54 0 to 54 N . Consequently, the sheath-like oxide films 32 and 54 0 to 54 N are formed on the inner side walls and top of the trenches 12 0 to 12 N . The obtained capacitors are sheath capacitors formed inside the trenches 12 0 to 12 N covered with the sheath-like oxide films 32 and 54 0 to 54 N . In the embodiment of the present invention, therefore, the capacitors of the same arrangement are formed inside the individual trenches, and no terminal trench with a specific internal arrangement exists. As shown in Figs. 6G-I to 6G-III, the oxide film 28, the nitride film 30, and exposed portions of the stacked insulating film 40 are removed. Subsequently, the surfaces of element formation regions of, e.g., the N-type well 22 and the P-type wells 24 1 and 24 2 are subjected to, e.g., thermal oxidation to form gate oxide (SiO 2 ) films 58 1 , 56, and 58 2 . A conductive layer consisting of, e.g., N-type polysilicon or a silicide is formed on the entire upper surface of the substrate 10 by using, e.g., the CVD process and patterned to form word lines 60 1 to 60 3 on the memory cell array region and gates 62 1 and 62 2 on the peripheral circuit region. Subsequently, an N-type impurity, such as phosphorus or arsenic, is ion-implanted into the P-type wells 24 1 and 24 2 by using a resist (not shown) or the like as a mask, thereby forming N-type source/drain regions 70 1 , 70 2 and 70 3 of a cell transistor, and N-type source and drain regions 72 1 and 72 2 of an N-channel MOSFET as a peripheral circuit and N-type contact regions 76 1 and 76 2 . The N-type source/drain regions 70 1 and 70 2 are formed in contact with the N-type regions 50 1 and 50 2 , respectively, and are thereby electrically connected with each other. After the resist is removed, a new resist (not shown) or the like is formed, and a P-type impurity, such as boron, is ion-implanted into the N-type well 22 by using this new resist as a mask. The results are P-type source and drain regions 74 1 and 74 2 of a P-channel MOSFET as a peripheral circuit and P-type contact regions 78 1 and 78 2 . Subsequently, as shown in Figs. 5A to 5C, an insulating interlayer 80 consisting of, e.g., a silicon oxide (SiO 2 ) film is formed on the substrate 10 by using the CVD process or the like. Contact holes reaching the N-type source/drain region 70 3 and the like are then formed in the insulating interlayer 80. A conductive layer consisting of, e.g., a silicide or an aluminum alloy is formed on the insulating interlayer 80 by, e.g., the CVD process or sputtering and patterned to form a wiring layer 82 such as bit lines. Subsequently, an insulating interlayer 84 consisting of, e.g., a silicon oxide (SiO 2 ) film is formed on the insulating interlayer 80 so as to cover the wiring layer 82 by using, e.g., the CVD process. Contact holes reaching the N-type contact regions 76 1 and 76 2 , the P-type contact regions 78 1 and 78 2 , and the like are formed in the insulating interlayers 80 and 84. A conductive layer consisting of, e.g., an aluminum alloy is formed on the insulating interlayer 84 by sputtering or the like and patterned to form an electrode layer 20 for supplying a potential to the wiring layer 16, several different wiring layers 86 1 to 86 3 , and electrode layers 88 1 to 88 3 for supplying a potential to the individual wells. The device according to the embodiment of the present invention is fabricated through the above steps. According to the dynamic RAM having the sheath capacitors with the above arrangement, a predetermined potential, such as a half-VCC-level potential, can be supplied to the wiring layer 16 via the N-type well 18 1 . In addition, it is possible to omit the step of forming a terminal trench, which is a problem in formation of conventional devices of this type, from the fabrication steps of the present invention. This makes unnecessary the photolithography step of removing an oxide film from the side surfaces of a terminal trench, eliminating the problem of a residual oxide film. This can solve problems, such as an increase in contact resistance between a wiring layer and a terminal. Furthermore, the above fabrication steps can reduce the probability of a resist remaining in a trench compared to the fabrication steps for conventional devices and can also minimize a problem of contamination due to impurities. The dynamic DRAM described in the above embodiment can also be operated to achieve the effects equivalent to those of the dynamic DRAM introduced in, e.g., "Process Technologies for A High Speed 16M DRAM with Trench Type Cell" S. Yoshikawa et al., Symposium on VLSI Technology Digest of Technical Papers, 1989, pp. 67 and 68. That is, in the dynamic RAM described in the embodiment, the deep N-type well 18 2 is formed in the P-type silicon substrate 10. Therefore, this dynamic DRAM can also be operated in the same fashion as a dynamic RAM with a triple-well structure by supplying a potential Vbb to the electrode layer 88 1 , a potential Vcc (power supply voltage) to the electrode layer 88 2 , a potential Vss to the electrode layer 88 3 , and a potential Vcc/2 (plate potential) to the electrode layer 20. This consequently improves the circuit performance. According to the present embodiment as has been described above, there are provided a semiconductor device with a structure, in which a potential can be easily supplied to a wiring layer formed in a semiconductor substrate, and which can be easily formed, and a method of fabricating the same.

Claims: A semiconductor device comprising: a semiconductor substrate (10) of a first conductivity type; a first semiconductor region (18 1 ) of a second conductivity type formed in said semiconductor substrate (10), said first semiconductor region (18 1 ) being a deep well-like region; a plurality of trenches (12 0 -12 N ) formed adjacent to each other with a predetermined depth and intervals in said semiconductor substrate (10), a plurality of second semiconductor regions (14 0 -14 N ) of the second conductivity type each formed from at least the bottom of a corresponding one of said plurality of trenches (12 0 -12 N ) into said semiconductor substrate (10), said second semiconductor regions (14 0 -14 N ) contacting each other to constitute a wiring layer (16) and being also in contact with said first semiconductor region (18 1 ), and an electrode (20), electrically connected to said first semiconductor region (18 1 ), for applying a predetermined potential to said second semiconductor regions (14 0 -14 N ) via said first semiconductor region (18 1 ), characterised by : a shallow well-like third semiconductor region (24 1 ) of a first conductivity type being formed in said semiconductor substrate (10); a first one (12 0 ) of said trenches being formed in said first semiconductor region (18 1 ), a plurality of second ones (12 2 -12 N ) of said trenches being formed in said third semiconductor region (24 1 ), and a third one (12 1 ) of said trenches being formed between said first trench (12 0 ) and said second trenches (12 2 -12 N ) and a plurality of capacitors (38 0 -38 N , 40, 42 0 -42 N ) respectively formed inside said plurality of trenches (12 0 -12 N ), each capacitor having a storage electrode and a plate electrode, each storage electrode (42 2 -42 N ) formed inside the plurality of second trenches (12 2 -12 N ) being connected to one of the source/drain regions (70 1 , 70 2 , 70 3 ) of a respective cell transistor (60 3 , 70 1 , 70 2 , 70 3 , 78 1 ), and each storage electrode (42 0 , 42 1 ) formed inside said first and third trenches (12 0 , 12 1 ) respectively being isolated from any one of the source/drain regions of the cell transistors. A device according to claim 1, characterised in that said plurality of capacitors (38 0 -38 N , 40, 42 0 - 42 N ) are of the same structure, and said plate electrodes (38 0 -38 N ) are electrically connected to said second semiconductor regions (14 1 -14 N ). A semiconductor device according to Claim 1 which is a dynamic RAM(DRM) wherein said dynamic RAM comprises said plurality of capacitors (38 0 -38 N , 40, 42 0 - 42 N ) formed in said plurality of trenches (12 0 - 12 N ), said cell transistors (60 3 , 70 1 , 70 2 , 70 3 , 78 1 ) each having said source/drain regions (70 1 , 70 2 , 70 3 ) of the second conductivity type and a gate electrode (60 3 ) connected to a word line (60 1 - 60 3 ), and a bit line (82) electrically connected to the other one of said source/drain regions (70 1 , 70 2 ) of said cell transistors (60 3 , 70 1 , 70 2 , 70 3 , 78 1 ). A DRAM according to Claim 3, characterised in that said capacitors (38 0 - 38 N , 40, 42 0 - 42 N ) comprise: a side wall insulating film (32) formed on only side walls of said plurality of trenches (12 0 - 12 N ); a first conductive film (38 0 - 38 N ) of the second conductivity type formed on bottoms of said plurality of trenches (12 0 - 12 N ) and on said side insulating film (32) to a predetermined depth in said trenches (12 0 - 12 N ) and serving as said plate electrode; an insulating film (40) formed on said first conductive film (38 0 - 38 N ) and serving as a dielectric film; and second conductive films (42 0 - 42 N ) of the second conductivity type formed on said insulating film (40) to a predetermined depth in said plurality of trenches (12 0 - 12 N ) and serving as said storage electrodes. A DRAM according to Claim 3, characterised in that said plurality of capacitors (38 0 -38 N , 40, 42 0 - 42 N ) formed in said plurality of trenches (12 0 - 12 N ) have the same structure. A DRAM according to Claim 3, characterized by further comprising: a peripheral circuit MOS transistor with a channel of the first conductivity type formed in a fourth semi-conductor region (22) of the second conductivity type in said semiconductor substrate (10) and having a gate electrode (62 1 ), and source/drain regions (74 1 , 74 2 ) of the first conductivity type; and a peripheral circuit MOS transistor with a channel of the second conductivity type formed in a fifth semiconductor region (24 2 ) of the first conductivity type electrically isolated from said semiconductor substrate (10) and having a gate electrode (62 2 ), and source/drain regions (72 1 , 72 2 ) of the second conductivity type. A DRAM according to claim 6, characterised by further comprising: insulating interlayers (80, 84) formed on the upper surfaces of said plurality of capacitors, said cell transistor (60 3 , 70 1 , 70 2 , 70 3 , 78 1 ), and said MOS transistors; a first electrode (88 1 ) for supplying a first predetermined potential (V bb ) to said contact region (78 1 ) of said cell transistor (60 3 , 70 1 , 70 2 , 70 3 , 78 1 ); a second electrode (88 2 ) for supplying a second predetermined potential (V cc ) to said peripheral circuit MOS transistor with a channel of the first conductivity type; a third electrode (88 3 ) for supplying a third predetermined potential (V SS ) to said peripheral circuit MOS transistor with a channel of the second conductivity type. A method of fabricating a semiconductor device, comprising the steps of: forming a deep well-like first semiconductor region (18 1 ) of a second conductivity type in a semiconductor substrate (10) of a first conductivity type; forming a shallow well-like third semiconductor region (24 1 ) of a first conductivity type in said semiconductor substrate (10) ; forming a plurality of trenches (12 0 - 12 N ) adjacent to each other with a predetermined depth and intervals in said semiconductor substrate (10) such that the first trench (12 0 ) is formed in said first semiconductor region (18 1 ) and a plurality of second trenches (12 2 - 12 N ) are formed in said third semiconductor region (24 1 ) and a third trench (12 1 ) is formed in between said first trench (12 0 ) and said second trenches (12 2 -12 N ) ; doping an impurity of the second conductivity type from at least the bottom portions of said plurality of trenches (12 0 - 12 N ) into said semiconductor substrate (10) ; diffusing said impurity to form a plurality of second semiconductor regions (14 0 - 14 N ) of the second conductivity type in said semiconductor substrate (10) such that said plurality of second semiconductor regions (14 0 - 14 N ) are electrically connected to each other and also connected to said first semiconductor region (18 1 ) to constitute a buried wiring layer (16); forming an insulating film (40) inside said plurality of trenches (12 0 - 12 N ), forming a plurality of storage electrodes (42 0 - 42 N ) respectively inside said plurality of trenches (12 0 - 12 N ) such that each storage electrode (42 2 - 42 N ) formed inside the plurality of second trenches (12 2 - 12 N ) is connected to one of source/drain regions (70 1 , 70 2 , 70 3 ) of a respective cell transistor (60 3 70 1 70 2 , 70 3 , 78 1 ), and each storage electrode (42 0 , 42 1 ) formed inside said first and third trenches respectively is isolated from any one of the source/drain regions of the cell transistors; and forming an electrode layer (20), electrically connected to said first semiconductor region (18 1 ), for applying a predetermined potential to said second semiconductor regions (14 0 - 14 N ) via said first semiconductor region (18 1 ). A method according to claim 8, characterised in that said first semiconductor region (18 1 ) is formed in the same step as for formation of a deep well-like third semiconductor region (18 2 ) of the second conductivity type. A method according to claim 8 of fabricating a semiconductor device in the form of a dynamic RAM, wherein: said impurity of impurity doped regions (34 0 - 34 N ) is diffused by annealing to form a said plurality of impurity-diffused layers (14 0 - 14 N ); said cell transistors are formed of which gate electrodes are connected to word lines; bit lines (82) are formed connected to the other one of said source/drain regions of said transistors; and insulating layers (80, 84) are formed on the entire surface and forming said electrode layer (20) for supplying a potential to said plurality of impurity-diffused layers (14 0 - 14 N ). A method according to claim 10, characterised in that the step of forming said capacitors (38 0 - 38 N , 40, 42 0 - 42 N ) comprises the steps of: forming a side wall insulating film (32) on only side walls of said plurality of trenches (12 0 - 12 N ); forming a first conductive film (38) of the second conductivity type at least on said side wall insulating film (32) to a predetermined depth in said trenches (12 0 - 12 N ) ; forming an insulating film (40) at least on the entire surface of said first conductive film (38); and forming second conductive films (42 0 - 42 N ) of the second conductivity type on said insulating film (40) to a predetermined depth in said trenches (12 0 - 12 N ). A method according to claim 10, characterised by further comprising the step of forming a MOS transistor of the first conductivity type and a MOS transistor of the second conductivity type as peripheral circuits. A method according to claim 12, characterised in that the step of forming said MOS transistor of the second conductivity type comprises the steps of forming a deep well-like third semiconductor region (18 2 ) of the second conductivity type simultaneously with formation of said first semiconductor region (18 1 ), forming a shallow well-like fourth semiconductor region (24 2 ) of the first conductivity type in said third semiconductor region (18 2 ), forming a gate electrode (62 2 ) on said fourth semiconductor region (24 2 ) via a gate insulating film (58 2 ), and doping an impurity of the second conductivity type into said fourth semiconductor region (24 2 ) to form source/drain regions (72 1 , 72 2 ) of the second conductivity type. A method according to claim 12, characterised in that the step of forming said MOS transistor of the first conductivity type comprises the steps of forming a shallow well-like fifth semiconductor region (22) of the second conductivity type in said semiconductor substrate (10), forming a gate electrode (62 1 ) on said fifth semiconductor region (22) via a gate insulating film (58 2 ), and doping an impurity of the first conductivity type into said fifth semiconductor region (22) to form source/drain regions (74 1 , 74 2 ) of the first conductivity type.

Inventors: KOHYAMA YUSUKE, KOHYAMA, YUSUKE, KOHYAMA, YUSUKE, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: H01L27
IPC codes: H01L27, H01L21