Field effect transistor

Abstract: It has a purpose to provide a field effect transistor so as to realize high intensive function in a LSI. A field effect transistor of this invention comprises a plural number of gates, to each of which an independent current is connected, and an output is generated by totalizing of characteristics "gate voltage vs. drain current" of the gates.

Description: FIELD OF THE INVENTION The present invention relates to a field effect transistor. BACKGROUND OF THE INVENTION The development in LSI technology is very remarkable in these days, and a device of high speed, large capacity and low electricity consuming has produced one after another. The motive power of these developments depends on the improvement of a minute processing technology. In order to make a leap of the technology in the future, a plant investment of new LSI processing will be needed. The necessary cost for creating a plant investment of 1 giga bite DRAM is estimated 1, 500,000,000,000 yen: it exceeds the expendable cost of a company. As a result, the improvement of LSI technology independent of a minute processing technology is desired in the future. Further devices are disclosed in Pat. Abs. Jap vol. 6 no. 128 (E-116)(1006) and JP-A-5753151, Pat. Abs. Jap. vol. 11, no.7 (E-469) and JP-A- 61182244 and IBM TDB vol.7 no.11 Apr. 1965, pq.1100. Under such a condition, abandonment of Neuman computers, such as research of a neural network, a highly intensive functions and multi-valuing data in LSI will be highly possibly break through, however. any decisive direction is not given concerning with them. SUMMARY OF THE INVENTION The present invention as claimed in claim 1 is invented considering the state above and has an object to provide a field effect transistor realizing highly intensive functions in a LSI. A field effect transistor relating to the present invention has a plural number of gates, and it generates an output by totalizing characteristics of "gate voltage vs. drain current" of the gates. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a plane pattern in an embodiment of a field effect transistor relating to the present invention. Figure 2 shows vertical cross section of the embodiment. Figure 4 is a graph showing a characteristic of drain current of the field effect transistor of the embodiment. Figure 3 is a graph showing a characteristic of a drain current of a conventional field effect transistor. PREFERRED EMBODIMENT OF THE PRESENT INVENTION Hereinafter, an embodiment of a field effect transistor relating to this invention is described with reference to the attached drawings. Figure 1 is a plane pattern of a field effect transistor of this invention, where a plural number of gates G1, G2....and Gn are set between source S and drain D. A conductor for impressing voltage to each gate is led upward, and the electricity is given from the upper positioned layer (Figure 2). There is no interference of both of source S and drain D positioning in both sides of the gate, and the gate can be given electricity. When a characteristic function of drain current vs. a gate voltage vg of a gate is defined as I(vg), then the characteristic of the plural number of gates is defined as n ΣI (vgi) i = 1 vgi : i-th gate voltage. These characteristics are shown in graphs in Figure 3 and Figure 4. As a result, a field effect transistor has an additional function in itself and realizes intensive functions and high density of functions to be equipped in a LSI. As mentioned above, a field effect transistor relating to this invention establishes a plural number of gates and generates an output by totalizing of characteristics of "gate voltage vs. drain current" of the gates, so it has an effective result realizable a highly intensive function.

Claims: A field effect transistor in a large-scale integrated circuit comprising a common source region, a common drain region and a plurality of gates located in parallel between the common source region and said common drain region, characterised in that each gate is connected to an independent analog voltage source which controls the forming of an independent channel in between said common source region and said common drain region and below the respective gate thus controlling, independently from the other voltages applied to the other gates, the flow of a current between said common source region and said common drain region.

Inventors: SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO, Shou, Guoliang, c/o YOZAN Inc., TAKATORI, SUNAO, C/O YOZAN INC., YAMAMOTO, MAKOTO, C/O YOZAN INC.
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1993
Main classification: H01L29
IPC codes: H01L29