Sense amplifier for an integrated circuit memory

Abstract: A sense amplifier for a very high density integrated circuit memory using CMOS technology is described. Each sense amplifier includes first and second local sense amplifier drive transistors, one (140) connecting the P channel transistors (112, 114) to VCC; the other (142) connecting the N channel transistors (142) to VSS. A read amplifier circuit (150-156) is provided within each sense amplifier and is operated by read control signals (DR, DRB, YR). Internal nodes of the latch of the sense amplifier are coupled by pass transistors (122, 124) that are responsive to column write control signals (YW). Local data write driver transistors (128, 130, 132, 134) are also provided to selectively couple the pass transistors to VCC-Vt or VSS in response to further data write control signals (DW, DWB). A relatively wider power line (184) is coupled to the drive transistors (140) to provide VCC thereto, and a narrower line (181) is used to control those first sense amplifier drive transistors (140). Corresponding wide and narrow lines (190, 186) are used for the second local sense amplifier drive transistors which couple the N channel transistors to ground. Each sense amplifier may be shared between first and second pairs of bit lines (220, 222; 224, 226) through the use of isolation transistors 232, 234, 238, 240) and a corresponding isolation signal (ISOL, ISOR).

Description: The present invention relates to integrated circuit memories and particularly relates to a sense amplifier for use therein of the kind defined in the preamble of Claim 1. Sense amplifiers of this kind, including a respective latch provided with first and second drive transistors, are disclosed in FR-A-2 662 844, specifically in figure 3B thereof and the relevant description. Integrated circuit memories include a large number of memory cells which are usually set forth in an array. The memory cells may be volatile or non-volatile. If they are volatile, they may be static RAM cells or dynamic RAM cells. There may be one large array, or a given memory chip may have several sub-arrays which may be arranged in blocks. Typically, the memory device comprises a large number of bit lines extending in one direction. The bit lines may be paired or non paired. Where they are paired, they are often referred to as complementary bit lines, or paired bit lines. Complementary bit lines are used for both static RAM and dynamic RAM applications. The bit lines generally extend in a first direction, and a plurality of word lines extend in a second direction which is perpendicular to the first direction. Typically, a memory cell is located at or near the crossing of a bit line with a word line. Often, a memory array is divided into subarrays, and each subarray may further be divided into blocks. Each subarray will often have its own "peripheral circuitry" such as decoders. The memory array or subarray is usually said to be organized into rows and columns. Generally, a row indicates the memory cells located along (coupled to) a word line. A column is therefore ordinarily perpendicular to a row and generally indicates a collection of memory cells along (coupled to) a bit line or a bit line pair. Generally, each column is connected to a respective sense amplifier. One job of the sense amplifier is to sense the effect that the memory cell has on the bit line(s) and to amplify that signal for outputting in a read operation. Conversely, the sense amplifier may also drive or control the bit line(s) when the memory is writing data into a memory cell. CMOS technology is prevalent today. Figure 1 illustrates a prior art configuration and shows a sense amplifier 10 using CMOS technology. The operation and configuration of such a sense amplifier 10 is well known and will not be explained except briefly herein. Amplifier 10 contains P channel transistors 12 and 14 having source electrodes commonly coupled to a line 16 which carries from time to time a signal LP also called LATCHP. The sense amplifier also comprises a pair of N channel transistors 18, 20 having source electrodes commonly coupled to a line 22 which sometimes carries a signal which may be called LN or LATCHN. A pair of internal nodes A, B are connected to gate electrodes. In particular, node A is coupled to the gate electrodes of transistors 12 and 18, while node B is coupled to the gate electrodes of transistors 14 and 20. These transistors form a latch. A first bit line BL1 on the left side of sense amplifier 10 is coupled to node B which is also coupled between the drain electrode of P channel transistor 12 and the drain electrode of N channel transistor 18. Likewise, a complementary bit line BL1 BAR is connected to node A which is also coupled between the drain electrode of P channel transistor 14 and N channel transistor 20. Transistors 12 and 14 are referred to as "pull-up" transistors whereas transistors 18 and 20 are referred to as "pull-down" transistors. When a transistor 24 is turned on, it couples VCC through its source-drain path to line 16, thereby providing the LATCHP signal. Sense amplifier 10 forms a flip-flop so that either transistor 12 or 14 but not both will be turned on and will pull the voltage at its corresponding node toward VCC. At or near the same time, one of the transistors 18 or 20 will pull down the voltage at the other node toward VSS which will be connected to line 22 via a transistor 26 being turned on. In this way, one of the two nodes is pulled high and the other is pulled low, and the sense amplifier latches into a stable state. In any large memory, such as a 16 megabit DRAM, there will be thousands of columns and thousands of rows. This is represented in Figure 1 which shows a second sense amplifier 30 connected to corresponding bit line pair BL2 and BL2 BAR, and an N-th sense amplifier 32 coupled to bit lines BLN and BLN BAR. It should be appreciated that N may be on the order of 1000 or more. The LP signal is applied to all N of these sense amplifiers via line 16, and the LN signal is applied to them via the line 22. It will be seen in Figure 1 that a plurality of resistances 34 are illustrated. These are not discrete resistance devices but rather indicate the parasitic resistance of the lines 16 and 22, which, even though they are formed of conductive materials such as metal or the like, nevertheless over great distances will have some resistance value. Over each resistance, there will be a voltage drop from the voltage applied via transistor 24 or 26, as the case may be. Accordingly, the voltage that eventually reaches sense amplifier 32 may be appreciably diminished from VCC or VSS, and that sense amplifier will work inefficiently or slowly. It will also be appreciated that because of this problem, sense amplifier 10 does not activate at the same time as sense amplifier 32 and the resulting skew prolongs access time. Additionally, some prior art designs can be unstable if the selected sense amplifier is connected to the data line (the bit lines) too early. Thus, as power supply (VSS) line 22 is trying to pull down to 0v, transistors start to turn on in the sense amplifiers. A current flows to the right on line 22, and there exists a voltage drop due to the resistance of line 22. Practical limitations prevent the solution of greatly widening line 22 to reduce its resistance -- the chip area is jealously allocated. Hence, in the illustrated architecture, the right-most sense amplifier 10 turns on first, and sense amplifier 32 will turn on thereafter. Generally, one desires to pull down line 22 at a controlled rate. The far end (most remote from transistor 26) of line 22 will drop in voltage slower than the near end. This slows the memory, which is undesirable, but if circuitry drove the near end too fast, then the corresponding near sense amplifiers would become unreliable. Another problem occurs when the near sense amplifiers latch logic "1's" and the far amplifier latches a logic "0." There is a pattern sensitivity because when the bit lines are precharged to ½VCC, the memory cell moves only one of the bit lines lower or higher. Sensing a "1" occurs before sensing a "0" because LN needs to drop only 1 Vt below a voltage level corresponding to a "1." However, to sense a "0" LN must be 1Vt below the "0" level, and this occurs later. Large current flows when "1's" are read. Because of the large currents, the decline in voltage at the far end of line 22 slows to an uncontrolled rate. This effectively can add 7 nsec. to the sensing process -- a substantial and undesirable increase. One approach that has been proposed for addressing this problem is depicted in Figure 2. It shows the same sense amplifiers 10,30, and 32, and has the same signals LP and LATCHN provided by transistors 24 and 26 respectively. However, further N channel transistors have been added beneath the sense amplifiers and a modification has been made so that LN is carried by two distinct lines. One of these lines 40 is constructed relatively wide to carry most of the current, and the other line 42 is relatively narrower because it will carry current for just a single selected sense amplifier. Line 40 is coupled to the sources of a plurality of transistors 44, each sense amplifier having a respective transistor 44. Each transistor 44 has its gate electrode coupled to VCC and is therefore generally on. Transistors 44 are relatively small in size so that they do not carry much current to any single sense amplifier. The narrower line or rail 42 is coupled to the several sense amplifiers by source-drain paths of respective transistors 46, which are shown also as N channel transistors. Transistors 46 are decoded and this is indicated by a low to high transition signal YR 47 shown beside the gate electrode of transistor 46 for sense amplifier 32 at the far left side of Figure 2. The other transistors 46 also are coupled to their YR signals, which are shown illustratively at 0v, i.e. they are not selected columns. Thus, the column which has been selected decodes its YR signal to apply to the gate electrode of the transistor 46 thereby to couple the narrow LATCHN line 42 to the sense amplifier. See also Okamura et al., "Decoded-Source Sense Amplifier for High-Density DRAMs", IEEE J. Solid State Circuits , Vol. 25, No. 1 (Feb 1990), pp 18-23. This solution does reduce the sensing skew since the current flowing through line 40 is reduced due to the weak transistors 44 in the current path. Therefore, the voltage drop down line 40 is reduced. Disadvantages of this approach are that the large transistors 46 must be added and that the capacitive loading on the column select signal YR is increased since it must drive the gates of transistors 46. There is poor control over the current draw and extra loading to the YR line because it is driving an extra transistor per sense amplifier. Chin et al., "An Experimental 16-Mbit DRAM with Reduced Peak-Current Noise," IEEE J. Solid State Circuits, vol. 24, no. 5 (Oct. 1989) at p. 1191 et seq. and particularly in Figure 4 adds both p- channel and n-channel transistors between sense amplifiers and power supply lines. However, it does not use one connection to the VCC line and one connection to the VSS line per sense amplifier. It does not drive these power lines from one end only, but rather from several connections that are distributed in the array. Signals SAP and SAN bar may correspond to LP and LN respectively. Thus, in the architecture disclosed that article, there are several sense amplifiers connected together, and there will still be some pattern sensitivity. An object of the present invention is to improve the sense amplifiers to overcome or reduce the aforementioned problems. This object is achieved according to the invention by the sense amplifier defined in Claim 1. In one of its aspects, while the prior art used narrow and wide lines or rails each carrying a LN signal, the present invention uses narrow and wide lines in connection with the LN signal but connects them differently. Additionally, the present invention in one of its aspects includes narrow and wide lines or rails for the LP supply signal. Thus, in the preferred embodiment, each sense amplifier has a respective N channel transistor having its source-drain path coupled to VSS via the wide line. The gate electrodes of those N channel drive transistors are gated by the narrow drive line which preferably carries the complement LNB of the LN signal. Correspondingly, in another aspect of the invention, each sense amplifier includes a respective P channel drive transistor, the source-drain path of which couples the P channel transistors of the sense amplifier latch to the high voltage such as VCC. That high voltage is carried by one of the wide drive lines. The narrower of the drive lines is coupled to the gate electrodes of these P channel drive transistors and carries a complement LPB of the LP signal. In describing the prior art and the present invention, reference has been made and will be made to accompanying drawings wherein: Figure 1 shows a typical prior art CMOS sense amplifier group; Figure 2 shows the same group of sense amplifiers connected according to one prior art modification; Figure 3 illustrates a sense amplifier, and Figure 4 shows a simplified form of the sense amplifier collected into a group of such sense amplifiers according to the invention. Figure 3 illustrates a sense amplifier 100. Amplifier 100 includes internal nodes 102 and 104 in a latch formed by transistors 112, 114, 118 and 120. Node 102 is coupled to the gate electrodes of P channel transistor 112 and N channel transistor 118, whereas node 104 is coupled to the gate electrodes of P channel transistor 114 and N channel transistor 120. The configuration of the flip-flop itself within the sense amplifier is the same as that of sense amplifier 10. A column write select signal Y w is coupled to the gate electrodes of pass transistors 122, 124. Preferably, the column write signal YW and a column read signal YR describe below are decoded for each four columns, so that each four columns has a unique YW and YR. However, this is unnecessary to embody the principles of the invention. In one configuration, each subarray may be fairly large -- 4Meg illustratively -- and may have a respective column decoder that will generate column select signals for that whole subarray. It is desired to be able to write to just one block within the subarray. That will be an "active block" wherein the sense amplifiers are active. An "inactive block" is one where the sense amplifiers are in precharge. Returning to the description of Fig. 3, however, the source-drain path of pass transistor 122 is coupled to node 104, and the source-drain path of transistor 124 is coupled to node 102. Transistor 122 is also coupled to a node 126 between the source electrode of a local data write driver transistor 128 and the drain of another local data write driver transistor 130. Transistors 128 and 130 are N channel devices having their source-drain paths coupled in series. The drain of transistor 128 is coupled to VCC and the source of transistor 130 is coupled to ground. A data write signal DW is coupled to the gate electrode of transistor 128 and its complement DWB is coupled to the gate electrode of transistor 130. A similar configuration exists on the right side of sense amplifier 100 where transistors 132 and 134 are coupled between VCC and ground and have a node 136 therebetween which is coupled to transistor 124. Note, however, that the data write signal DW is coupled to control transistor 134 whereas its complement DWB is coupled to the gate electrode of transistor 132. That is to say, the data write signal DW turns on a pull-up transistor 128 on the left side of the sense amplifier 100, but turns on a pull down transistor 134 on the right side of sense amplifier 100. Its complementary signal DWB likewise has reciprocal effects on the left and right sides. The source electrodes of P channel transistors 112 and 114 within amplifier 100 are coupled to a further P channel transistor 140, the source electrode of which is coupled to VCC (or LATCHP). The gate electrode of this P channel device 140 is coupled to receive a signal LPB which is the logical complement of LATCHP. FET 140 is referred to as a local sense amplifier drive transistor. Similarly, the source electrodes of the N channel transistors 118 and 120 within amplifier 100 are coupled to ground through the source-drain path of a further local sense amplifier drive transistor 142. The gate electrode of transistor 142 is coupled to receive signal LNB which is the logical complement of LATCHN. The lower portion of Figure 3 includes a local column read amplifier which includes four N channel transistors 150, 152, 154, and 156. The source-drain paths of transistors 150 and 152 are coupled in series. The drain electrode of transistor 150 receives a signal DRB which is a logical complement of a data read signal DR. The source electrode of transistor 152 is coupled to ground. Node 104 is coupled via a conductive line 158 to the gate electrode of transistor 152. The gate electrode of transistor 150 is coupled to a column read signal Y R . The source-drain path of transistors 154 and 156 are coupled in series between the data read signal DR and ground. The gate electrode of transistor 154 is coupled to the gate electrode of transistor 150, and accordingly is coupled to the column read signal Y R . The gate electrode of transistor 156 is coupled to internal node 102 via a conductive line 160. Hence, the circuit of Figure 3 includes data read circuitry formed by transistors 150 through 156. Transistors 128, 130, 132 and 134 comprise local data write transistors. Transistors 140 and 142 comprise local sense amplifier drive transistors. It will be understood that there are thousands of such circuits 100 in a large integrated circuit memory. The signals LPB and LNB connected to the local sense amplifier drive transistors, the data write signal DW and its complement DWB coupled to the local data write driver transistors, and the data read signals DR and DRB are shared among or applied to many sense amplifiers on the memory device. The global Y select signals Y R (for reading) and Y W (for writing) are shared among several sense amplifiers in a direction perpendicular to the LNB, LPB, and data lines. There are separate read and write data buses. DR and DRB comprise a read data bus and DW and DWB comprise a write data bus. To sense (latch) data, the bit line signal is connected to the latch nodes L and LB by circuitry shown in subsequent drawings, or can be connected directly in some embodiments to these latch nodes, and then the local sense amplifier drive transistors 140 and 142 turn on by LPB going low and LNB going high. These transistors 140 and 142 give the advantage over the traditional sense amplifier that each sense amplifier is decoupled from other sense amplifiers, and latching can be more accurately controlled with these two signals LPB and LNB. The sense amplifiers are decoupled from each other because the drains of transistors 140 and 142 are separate for each sense amplifier. Transistors 150, 152, 154, 156 comprise a read amplifier which provides a non-destructive read operation. The column read signal YR can go high at any time, even prior to latching, without upsetting the sense amplifier. Additionally, the data read signals DR and DRB can be at any voltage without upsetting the sense amplifier. A further advantage is that transistors 150 through 156 can be sized independently of the sense amplifiers transistors 112, 114, 118, 120. Writing is accomplished when the column write signal Y W (a decoded signal) is high and either of the data write signals DW or DWB is high. If both of these data write signals are low, writing does not occur. This circuit eliminates the need for a block enable (BE) signal. The local data write driver transistors 128-134 can be shared with other column circuits as long as they have separate column write signals. A modification to this circuit of Figure 3 couples the gate electrode of transistor 128 to its drain, and does the same for transistor 132. This may reduce the number of metal lines required and can save area or improve the layout. They will result in about the same writing speed. The VCC connections at the drain electrodes of transistor 128 and 132 are eliminated, but there is some increased loading on the data write signals DW and DWB. Figure 4 is similar to Figure 1 and Figure 2. For clarity of illustration, sense amplifiers (and associated circuitry) 100 are shown in block form in Figure 4. Each block marked 100 is intended to include all of the devices of Figure 3 with the exception of transistors 140 and 142 which are shown in Figure 4 for each sense amplifier 100. The connections to the bit lines are not shown, and it will be understood that each sense amplifier 100 may be connected to a respective pair of bit lines either directly or selectively through nodes 102 and 104 of Figure 3. In Figure 4, power is supplied to the P channel transistors 112, 114 of each sense amplifier 100 via transistors 140. Preferably each transistor 140 is a P channel device the gate electrode of which is coupled to the signal LPB which stands for Latch P BAR. A relatively narrow line connects the LPB signal to the gate electrodes of an entire group of sense amplifiers 100 as shown in Figure 4. The LPB signal may be generated by a transistor 180, the source-drain path of which is coupled to ground. Transistor 180 may comprise an N channel transistor so that when a positive voltage is applied to its gate electrode, LPB is pulled to ground and all of transistors 140 coupled to that particular transistor 180 should turn on. This would thereby couple the VCC voltage (or LATCHP signal) applied at 182 through a relatively wide line 184 to the source electrodes of transistors 140. A similar configuration is used for the N channel transistors at the bottom of Figure 4. The N channel transistors 118, 120 within sense amplifiers 100 are coupled to ground via N channel transistors 142 as explained with respect to Figure 3. The gate electrodes of transistors 142 are coupled via a relatively narrow line 186 to the signal LNB which stands for Latch N BAR. Signal LNB may be generated by a preferably P channel transistor 188, the source-drain path of which is coupled between VCC and line 186. The gate electrode of transistor 188 and transistor 180 are coupled to suitable control signals. When transistor 188 is conductive (its gate electrode receives a low voltage), the LNB signal is pulled to VCC thereby to turn on transistors 142. This couples each sense amplifier to a relatively wide line 190 which couples VSS (or LATCHN) to the source electrodes of each transistor 142. In Figure 4, the narrow line 181 carries very little current. Each sense amplifier 100 is isolated from the others. Each one has its own connection to the power supply lines 184 and 190. This reduces or eliminates pattern sensitivity of the type which is encountered in architectures such as Chin with distributed connections (multiple sense amps connected together to power supply lines). It will be understood generally that in this specification, the nomenclature of a "B" or "BAR" represents the logical complement of a given signal and typically takes a different voltage than the assertion of the signal. That is to say, if the asserted state is at VCC which is illustratively 5 volts, the complement thereof will be at zero volts, or vice-versa. It will be further understood that the symbol "L" may be understood as a latch signal and when combined with a P symbol stands for latching by turning on P channel transistors, and the LN symbol represents turning on the N channel transistors of a latch. This is true, however, when the LP and LN signals are asserted. When they are not asserted, the P channel and N channel transistors are not turned on. The present invention therefore has been described as including, in various of its aspects, a pair of local sense amplifier drive transistors 140, 142. Preferably each of these cooperates with a respective pair of current carrying lines, one of them being a relatively wider line to carry the greater amount of current, the other being a relatively narrower line because it is coupled to the gate electrode or control electrode of its respective transistor 140 or 142. These have been illustrated in Figure 4.

Claims: A sense amplifier (100) for an integrated circuit memory comprising: a latch circuit (112, 114, 118, 120) having nodes (102, 104) for coupling to respective bit lines, the latch circuit (112, 114, 118, 120) including a pair of P channel transistors (112, 114) and a pair of N channel transistors (118, 120); first (140) and second (142) local sense amplifier drive transistors coupled to said latch circuit (112, 114, 118, 120), the first local sense amplifier drive transistor (140) being coupled to the sources of the P channel transistors (112, 114) , the second local sense amplifier drive transistor (142) being coupled to the sources of the N channel transistors (118, 120), each of said local sense amplifier drive transistors being coupled to provide selectively a respective voltage signal to the corresponding pair (112, 114; 118, 120) of transistors within said latch circuit; wherein said sense amplifier (100) is one of a plurality of identical sense amplifiers (100) corresponding to respective bit line pairs within the memory, and wherein each of said sense amplifiers (100) includes its own respective first and second local sense amplifier drive transistors (140, 142); wherein said first local sense amplifier drive transistor (140) is gate-coupled to a first common control signal line (181), and said second local sense amplifier drive transistor (142) is gate-coupled to a second common control signal line (186) and in that the source-drain path of said first local sense amplifier drive transistor (140) is connected to a first common supply line (184) and the source-drain path of said second local sense amplifier drive transistor (142) is connected to a second common supply line (190) characterized in that said common supply lines (184, 190) are wide with respect to said common control signal lines (181,186). The sense amplifier according to claim 1 wherein said first local sense amplifier drive transistor (140) comprises a P channel transistor, and wherein said second local sense amplifier drive transistor (142) comprises an N channel transistor.

Inventors: HARDEE KIM C, HARDEE, KIM C.
Applicants: NIIPON STEEL SEMICONDUCTOR, UNITED MEMORIES INC, NIPPON STEEL SEMICONDUCTOR CORPORATION, UNITED MEMORIES, INC.
Application year: 1993
Main classification: G11C7
IPC codes: G11C7, G11C11