Photoelectric conversion device and method of driving the same

Abstract: A photoelectric conversion device comprising a photoelectric conversion cell, as an individual pixel, comprises a first transistor having a control electrode region consisting of a semiconductor of one conduction type, and first and second main electrode regions consisting of a semiconductor of opposite conduction type of the one conduction type, for outputting a signal from the first main electrode region based on carriers transferred to the control electrode region, a carrier storage region provided adjacent the first transistor, consisting of a semiconductor of the one conduction type for storing carriers generated by light energy being received, and a second transistor, with the carrier storage region and the control electrode region of the transistor as the source and drain regions, for transferring carriers stored in the carrier storage region to the control electrode region of the transistor.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device using a photoelectric conversion element of the amplification type capable of amplifying and outputting a photoelectrically converted signal with a transistor component. Related Background Art Recently, photoelectric conversion elements of the amplification type capable of amplifying and outputting a photoelectrically converted signal have gained wide attention, because with the higher definition of photoelectric conversion elements, the output of a photoelectrically converted signal may be reduced. Among such photoelectric'conversion elements of the amplification type is a photoelectric conversion element having the same constitution as a unipolar or bipolar transistor, in which electric charge generated by light illumination is stored in the base or gate region which is a control electrode region, and an amplified signal is output from the source or emitter region which is a main electrode region. Fig. 27 is a plan view showing a pixel using a conventional bipolar sensor. In the same figure, 21 is an emitter region, 22 is an output line made of AL or the like, 23 is a contact hole connecting the emitter region 21 with the output line 22, 24 is a base region for storing photoelectric charges, 25 is a drive line made of poly-Si or the like for effecting the sensor action of pixel, 26 is a capacity C OX formed between the base region 24 and the drive line 25, and 27 is a gate electrode of a p-type MOS transistor which is formed with the base regions 24 of adjacent pixels as source and drain regions, consisting of a part of the drive line 25. 28 is a thick oxide film for the separation between pixels. Fig. 28 is a cross-sectional view of Fig. 27, taken along the line X-X', and Fig. 29 is a cross-sectional view of Fig. 27, taken along the line Y-Y'. In Figs. 28 and 29, 29 is a thin oxide film, 30 is an n + layer of high impurity concentration provided for the separation between pixel signals in the Y-Y' direction, 31 is an n - layer of low impurity concentration in which a depletion layer is spread, 32 is a collector region, and 33 is a layer insulation film for the separation between wirings 22, 25. Note that as shown in Fig. 28, a p-type MOS transistor M for the reset (a region encircled by the broken line in the figure) is formed in a horizontal separation region of each pixel. If the gate of the p-type MOS transistor M is turned on, the base region 24 of an adjacent pixel conducts, so that a reset is effected. On the contrary, if the gate is off, the p-type MOS transistor M serves as a pixel separation region. Further, Fig. 30 is an equivalent circuit diagram of a two-dimensional photoelectric conversion device in which the pixels are arranged in two dimensions. In Fig. 30, 41 is a pixel consisting of a bipolar sensor (or equivalently a bipolar transistor) T, a capacitor C OX connected to the base, and a p-type MOS transistor M, 42 is a vertical output line connecting the emitters of pixels 41, 43 is a MOS transistor for resetting the vertical output line 42, 44 is a storage capacitor for storing an output signal from the pixel 41, 45 is a MOS transistor for transferring the output signal to the storage capacitor 44, 46 is a MOS transistor for receiving the output of a horizontal shift register and transferring an output signal to a horizontal output line 47, 48 is a MOS transistor for resetting the horizontal output line 47, 49 is a preamplifier, 50 is a horizontal drive line, 51 is a buffer MOS transistor for receiving the output of a vertical shift register and passing a sensor drive pulse therethrough, 52 is an emitter follower circuit for setting the source voltage of the p-type MOS transistor to effect clamp operation of the pixel 41, 53 is a p-type MOS transistor for setting the base voltage of the emitter follower circuit 52, 54 is a terminal for applying pulses to the gate of the MOS transistor 43, 55 is a terminal for applying pulses to the gate of the transfer MOS transistor 45, 56 is a terminal for applying sensor drive pulses, 57 is a terminal for applying pulses to the gate of the p-type MOS transistor 53, and 58 is an output terminal connected to the preamplifier 49. A two-dimensional solid-state image pickup device as shown in Fig. 30 is of the type in which all the pixels are reset at a time, and is useful for the still video and so on. The operation thereof will be described below. First, the p-type MOS transistor 53 is turned on and the output of the emitter follower circuit 52 is made at a positive voltage, by applying a low-level pulse to the terminal 57 of Fig. 30. The output of this emitter follower circuit 52 is connected to the sources of p-type MOS transistors M for the pixels 41, wherein if the source voltage is higher enough than the gate voltage to fully turn on the p-type MOS transistor M, holes are injected into the base of bipolar sensor T for the pixel through the p-type MOS transistor M. Then, a high-level pulse is applied to the terminal 57, so that the p-type MOS transistor 53 is turned off, and the output of the emitter follower circuit 52 is grounded. Then, a high-level pulse is applied to the terminal 54 of Fig. 30, so that the transistor 43 is turned on, and the vertical output line 42 is grounded (referred to as a first reset). Then, the vertical shift register is driven while in this state, and a reset pulse of pixel is applied to the terminal 56, so that pixels are reset sequentially from one row to another, and the bases of the bipolar sensors T for all the pixels are placed at a constant voltage and reverse-biased (referred to as a second reset). After the storage operation of light carriers is carried out, a low-level pulse is applied to the terminal 54 of Fig. 30, so that the MOS transistor 43 is turned off. For each row selected by the output of vertical shift register, a read pulse is applied from the terminal 56, whereby a signal output is stored through the MOS transistor 45 in the storage capacitor 44. The signal output stored in the storage capacitor 44 is transferred through the transfer MOS transistor 46 selected by the horizontal shift register to the horizontal output line 47, and output through the preamplifier 49 to the output terminal 58. First of all, a first problem with the conventional photoelectric conversion element will be described below. The photoelectric conversion element has been utilized in practice as the sensor element for camera or FAX by virtue of its superior photoelectric conversion characteristics. However, with minuter configuration of sensor elements, (1) Reduced number of light generated carriers with decreased light receiving area, and (2) Lower capacity division ratio with increased parasitic capacity component take place, and as a result, the signal component decreases, and the S/N ratio is lowered. Accordingly, to proceed with further minuter structure, it is necessary that the signal component be maintained as large as possible. There is the following relation between the sensitivity of photoelectric conversion element and the parasitic capacity. Expression 1 S = Ip · Ae · ts C bc + C OX · 1 1 + C T + C vl (C bc + C OX ) h FE = Ip · Ae · ts C bc + C OX · h FE (C bc + C OX ) (C T + C vl ) + (C bc + C OX ) h FE S: Sensitivity Ip: Photocurrent generating density Ae: Opening area ts: Storage time C OX : Overlap capacity between MIS gate electrode and control electrode C bc : Base-collector junction capacity h FE : Current amplification factor of Tr C T : Temporary charge stored capacity C vl : Parasitic capacity on the vertical line As will be clear from the expression (1), to obtain the greatest sensitivity, it is desirable to make C bc +C ox as small as possible in the former term, and to make C vl +C T as small as possible and C bc +C OX as large as possible in the latter term, providing that the opening area, the photocurrent generating density, the storage time and h FE are fixed. When the pixel size is relatively large, the degree of freedom for the layout is high and each capacity value can be easily controlled, whereby the sensitivity could be rendered sufficiently high. However, if the pixel size becomes smaller with further progress of minuter construction, the degree of freedom for the layout decreases due to process constraint such as alignment precision or increased junction capacity component, and reduced opening ratio. On the device operation, the value of C T has a lower limit, due to the constraint in finally reading the value, and the value of C OX has a lower limit from the point of determining the saturation voltage, and an upper limit from the point of maintaining the opening ratio. Also, the value of C bc has an inconsistent requirement that it should be smaller to make the base voltage in reading as high as possible, and be greater to provide the least voltage drop due to capacity division with the reading operation. Accordingly, to provide the greatest sensitivity, it is desirable that the values of C OX , C T are determined from the operational requirements, C bc is set at an optimal value, and C vl is set at minimum, whereas in the conventional structure, C be , a main factor for determining C vl , which is determined by the emitter size, can be little decreased, so that there was a tendency that the sensitivity would decrease with smaller pixel size. Next, a second problem of the conventional photoelectric conversion element will be described below. For the two-dimensional photoelectric conversion device as shown in Fig. 30, the first reset is performed at the same time, as already described, but the subsequent second reset operation that the base of bipolar sensor T for the pixel is placed at a fixed voltage and reverse-biased, is effected sequentially for each pixel from one row to another, so that the start of storage operation takes place at different times for the pixels in each row. Also, the storage operation is terminated immediately before the start of reading operation, but the reading operation is made sequentially for each pixel from one row to another, so that the termination of storage operation takes place at different times for the pixels in each row. Accordingly, a certain drift may arise at the start and termination time of storage operation from one row to another, when a fast motion picture is picked up, so that the output image may be distorted. In particular, when the motion picture is read as a still image, this tendency is remarkable. Document EP-A-0 400 985 discloses a photoelectric conversion device wherein each pixel has a pair of a carrier storage region and a read transistor. It is an object of the present invention to provide an improved photoelectric conversion device. According to the invention this object is accomplished by a photoelectric conversion device according to claim 1. The present invention seeks to contribute to the further advancement in the microstructure of a photoelectric conversion device, as shown in Figs. 27 to 30. In contrast to a conventional constitution in which a transistor is provided for each pixel, light generated carriers are stored in the control electrode region, and a signal is read from one of the main electrode regions adjacent to said control electrode region, the present invention is configured such that the carrier storage region for storing light generated carriers is provided separately from the control electrode region of the transistor for use with the reading operation, and carriers stored in said carrier storage region are transferred to said control electrode region. Herein, if the carrier storage region is arranged in linear symmetry with the control electrode region, the number of main electrodes for the output Qf signal is one-half the conventional number, i.e., one main electrode is commonly used for two pixels, and the value of C vl can be about 50 to 70% of the conventional value. Also, by shifting the main electrode region for the output of signal, conventionally existing in the central portion of one pixel, to a separation portion of the pixel, the effective opening area is increased by about 20 to 30%. The accumulation of such effects will improve the sensitivity. A photoelectric conversion method includes 1) First reset operation to set a plurality of carrier storage regions and control electrode regions to their initial voltages, 2) Subsequent store operation to store carriers generated by light illumination in carrier storage regions, 3) Subsequent transfer operation to transfer carriers stored in one of the carrier storage regions to a control electrode region by allowing one of a plurality of insulated gate transistors to conduct, 4) Subsequent reading operation to read the voltage of the control electrode region uniquely determined by transferred carriers, 5) Second reset operation after reading to initialize the voltage of said control electrode region, 6) Repeating each operation of transfer, reading and reset, according to the operations of 3) to 5), for other carrier storage regions. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view for two pixels (one photoelectric conversion cell) according to an embodiment of a photoelectric conversion device of the present invention. Fig. 2 is a cross-sectional view of Fig. 1 taken along the line A-A'. Fig. 3 is a cross-sectional view of Fig. 1 taken along the line B-B'. Fig. 4 is a cross-sectional view of Fig. 1 taken along the line C-C'. Fig. 5 is a cross-sectional view of a capacitor portion C 1 and its neighborhood of Fig. 1. Fig. 6 is an equivalent circuit diagram for four pixels in this embodiment. Fig. 7 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 8 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 9 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 10 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 11 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 12 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 13 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 14 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 15 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 16 is a cross-sectional view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 17 is a plan view showing a fabrication method of a photoelectric conversion device in this embodiment. Fig. 18 is a timing chart showing the operation of a photoelectric conversion device in this embodiment. Fig. 19 is an equivalent circuit diagram showing the configuration of a first embodiment of a photoelectric conversion device according to the third invention. Fig. 20 is a timing chart showing the operation of a photoelectric conversion device in the first embodiment. Fig. 21 is an equivalent circuit diagram showing the configuration of a second embodiment of a photoelectric conversion device according to the third invention. Fig. 22 is a timing chart showing the operation of a photoelectric conversion device in the second embodiment. Fig. 23 is an equivalent circuit diagram showing the configuration according to a third embodiment of a photoelectric conversion device according to the third invention. Figs. 24A to 24C are schematic views for explaining a photoelectric conversion device according to an embodiment of the present invention. Figs. 25A to 25C are schematic views for explaining a photoelectric conversion device according to another embodiment of the present invention. Figs. 26A and 26B are schematic views for explaining the operation of the photoelectric conversion device in Figs. 25A to 25C. Fig. 27 is a plan view of pixel using a conventional bipolar sensor. Fig. 28 is a cross-sectional view of Fig. 27 taken along the line X-X'. Fig. 29 is a cross-sectional view of Fig. 27 taken along the line Y-Y'. Fig. 30 is an equivalent circuit diagram of a two-dimensional photoelectric conversion device having pixels of Fig. 27 arranged in a two-dimensional array. Fig. 31 is a block diagram of a signal processing system using a photoelectric conversion device of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figs. 24A to 24C are schematic views showing one embodiment of the present invention, Fig. 24A shows an upper face of a photoelectric conversion device, Fig. 24B shows a cross section taken along the line X-X', and Fig. 24C shows an equivalent circuit. A light receiving portion is constituted of a photodiode PD having a P region 12 and an n - region 3, and a first transistor is constituted of a bipolar transistor Q with an n + region 2 and an n - region 3 as the collector, a p region 9 as the base, and an n region 10 as the emitter. And the photodiode PD and the bipolar transistor Q selectively conduct through two p regions 9, 12 with a pMOS transistor MT as a second transistor interposed therebetween. Herein, C p is a storage capacitor, C BC is a base-collector capacitor, and V CC is a reference voltage source for supplying the voltage for reverse-biasing the collector, and a cathode of the photodiode. The basic operation will be described below. If the transistor MT is off and light is incident upon the photodiode, holes are stored in the p region 12. Next, the transistor MT is turned on so that light charges are transferred to the p region 9 as base. After the transistor MT is turned off again, an amplified signal is taken out of the emitter based on carriers stored in the base. The first transistor for use in the present invention may be a bipolar transistor or a unipolar transistor. In particular, the latter is preferably FET or SIT having a junction gate. The second transistor for use in the present invention is preferably an insulated gate transistor, and in particular desirably a MOS transistor. Further, the first and second transistors are preferably shielded from light in part thereof. And if a plurality of photodiodes are provided for one first transistor, the sensitivity can be improved with higher opening ratio. Figs. 25A to 25C are device (line sensor) having three pixels arranged in an array, with a photoelectric conversion device of Figs. 24A to 24C as one pixel. In addition to the configuration of Figs. 24A to 24C, this pixel further comprises a reset transistor as the third transistor. The third transistor MR is a pMOS transistor having the p regions 12, 20 as source and drain and a gate electrode indicated by 11, a p region 20 being carried on a reference voltage for the reset. In this case, it is preferable that the region except for photodiode is shielded from light by a light shielding layer provided via an insulation layer 14, as shown in Fig. 25B. In an embodiment of Figs. 25A to 25C, it is desirable to turn on the pMOS transistor MR and reset the photodiode by applying a negative voltage to the gate electrode 11 before storing operation in the embodiment of Figs. 24A to 24C. Figs. 26A and 26B are views for explaining the operation of a device of Figs. 25A and 25B showing a circuit and a pulse timing, respectively. First, the reset operation takes place by applying a negative pulse to terminals  BRS ,  T , and a positive pulse to a terminal  TT , so that a first reset is effected. At this time, the anode of each photodiode and the base of bipolar transistor are held at a reset reference voltage V BB . Then, a positive pulse is applied to a terminal  ERS so that the emitter of bipolar transistor and capacitor C T are reset at a reset reference voltage V EE . Thus, the bipolar transistor is forward-biased in the base-emitter so that carriers are reset. Then, it is desirable to cause pulse  ERS to fall after rising of pulse  T to suppress any fixed pattern noise as tt. If the reset operation is thus terminated, the storing operation is entered. At this time, transistors MR, MT 1 ... MT 3 , M 1 ... M 3 , MV 1 ... MV 3 , MH 1 ... MH 3 are all in the off state. Then, entering the reading operation, the MOS transistors MT 1 ... MT 3 are turned on by a pulse  T , so that carriers are transferred concurrently to the bases of bipolar transistors Q 1 ... Q 3 . Then, if the transistors M 1 ... M 3 are turned on by a pulse  TT , the emitter is connected to a reading capacitor load C T , so that a signal based on carriers stored in the base is read to the capacitor load C T . Thereafter, the operation of a shift register causes three signals in time series to be output through an amplifier Amp. Of course, it goes without saying that the pixels arranged in two-dimensional array can constitute an area sensor. Embodiment 1 The embodiments of the present invention will be described below with reference to the drawings. Fig. 1 is a plan view for two pixels (two photoelectric conversion cells) in an embodiment of a photoelectric conversion device according to the present invention, Fig. 2 is a cross-sectional view of Fig. 1 taken along the line A-A', Fig. 3 is a cross-sectional view of Fig. 1 taken along the line B-B', Fig. 4 is a cross-sectional view of Fig. 1 taken along the line C-C', and Fig. 5 is a cross-sectional view of a capacitor portion C 1 and its neighborhood of Fig. 1. Fig. 6 is an equivalent circuit diagram for four pixels. Note that in Fig. 1, the wirings and the insulation layer are omitted for the easy understanding. A photoelectric conversion device in this embodiment has two second transistors MT1, MT3 (insulated gate transistor, shown in Figs. 1 and 2) provided corresponding to two carrier storage regions PD1, PD3, as shown in Fig. 6, wherein carriers are stored in the carrier storage regions PD1, PD3 through MOS transistors MT1, MT3 and sequentially transferred to a base region (control electrode region) B 3 of one bipolar transistor Q 1 . By controlling the voltage of the base region B 3 via capacitors C 1 , C 3 , a signal based on carriers transferred to the base region B 3 is output from an emitter region (first main electrode region) 10 via a wiring 15. Residual charges in the carrier storage regions PD1, PD3 are discharged by turning on two third transistors MR1, MR3 (insulated gate transistors), respectively, which are set at a predetermined voltage V BG . When the MOS transistors MR1, MR3 are off, the carrier storage regions PD1, PD3 are electrically isolated from each other. In Figs. 1 to 5, 1 is an n-type semiconductor substrate, 2 is an n-type diffusion layer, 3 is an n-type epitaxial layer, 4 is a field oxide film which is an element separation region, 7 is a gate oxide film, 8a, 8b are poly-side films which act as the gate electrodes of MOS transistors MT1, MT3, 9 is a p-type region acting as the base region of a bipolar transistor Q 1 , as well as the source regions (or drain regions) of MOS transistors MT1, MT3, 10 is an n-type region which is an emitter region of the bipolar transistor Q 1 , and 11 is an electrode acting as the gate electrode of MOS transistors MR1, MR3, as well as constituting the capacitors C 1 , C 3 , as shown in Fig. 5. Also, 12 is a p-type region constituting the carrier storage regions PD1, PD3, 13 is a layer insulation film (BPSG film), 14 is a layer insulation film (PSG film), 15 is a first AL layer, 16 is a second AL layer, and 17 is a passivation film. A fabrication method of a photoelectric conversion cell with the above construction will be described below using Figs. 7 to 17. Note that Fig. 8, Fig. 11 and Fig. 14 are views corresponding to an A-A' cross section of Fig. 1, Fig. 9, Fig. 12 and Fig. 15 are views corresponding to a B-B' cross section of Fig. 1, and Fig. 10, Fig. 13 and Fig. 16 are views corresponding to a C-C' cross section of Fig. 1. Herein, in Fig. 8, Fig. 9, Fig. 11, Fig. 12, Fig. 14 and Fig. 15, an element area 19 is shown in reduced scale for simplification. The n-type semiconductor substrate 1 utilized has a specific resistance of 0.01Ωcm to 10Ωcm. First, an n-type diffusion layer 2 is formed thereon by introducing As impurities 0.1 to 1 µm deep, with a surface density of 1E17 to 1E20/cm 3 , by ion implantation or thermal diffusion. Then, using an epitaxial growth method, an n-type epitaxial layer 3 is formed, with a growth layer density of 5E13 to 5E15/cm 3 , about 3 to 15 µm deep (Fig. 7). Then, using a selective oxidation method, an element forming region 19 and a field oxide film 4 which is an element separation region are formed. At this time, a pad oxide film 5 is made 10 to 50nm (100 to 500 angstroms) thick, a nitride film by low pressure CVD is made 100 to 300nm (1000 to 3000 angstroms) thick, and a field oxide film 4 is made 400 to 1000nm (4000 to 10000 angstroms) thick (Figs. 8 to 10). It is needless to say that when well diffusion is required to form a peripheral drive circuit from CMOS transistors, or an n-type diffusion layer of high density is required, these processes must be completed before the LOCOS method. Then, after the pad oxide film 5 is removed and an element forming region is exposed by etching, oxidation of approximately 100 to 300nm (1000 to 3000 angstroms) is effected, then this oxide film is removed again, and a new gate oxide film 7 is formed approximately 10 to 50nm (100 to 500 angstroms) thick by dry oxidation. Subsequently, a polysilicon film is formed approximately 200 to 400nm (2000 to 4000 angstroms) thick by low pressure CVD method, and a W film is formed approximately 100 to 200nm (1000 to 2000 angstroms) thick by low pressure CVD or sputtering, these laminated films being transformed into poly-side by thermal treatment. Subsequently, photoetching is conducted to leave poly-side films 8a, 8b at only desired portions, and an oxide film is grown approximately 10 to 100nm (100 to 1000 angstroms) thick on the poly-side by thermal oxidation. Then, a polysilicon film is formed approximately 200 to 400nm (2000 to 4000 angstroms) thick by low pressure CVD, this polysilicon film becoming an electrode 11 having both features of the pixel-to-pixel separation in the horizontal direction and the voltage control of control electrode, and a gate electrode for the peripheral circuit, formed from CMOS transistors. Also, when poly-side formation is needed, W film is subsequently formed approximately 100 to 200nm (1000 to 2000 angstroms) thick by low pressure CVD or sputtering, and subjected to thermal oxidation for poly-side formation, and photoetching is conducted to remove other than desired portions. At this stage, a p-type region 12 as carrier storage region and a p-type region 9 as base region are formed concurrently from field oxide film and poly-side film in self-aligned manner, using ion implantation method and thermal diffusion method. The conditions used this time were such that boron ions of 1E12 to 4E12/cm 2 were implanted at 40 keV, and thermal treatment was conducted for 1 to 3 hours in the inert gas atmosphere at 1100°C. Subsequently, when an NMOS transistor exists in the emitter region 10 and the peripheral circuit, the source and drain regions of the NMOS transistor are formed concurrently by a photolithography process and a ion implantation method. In this embodiment, As ions of about 1E15 to 1E16/cm 2 are implanted at 100 keV (Figs. 11 to 13). Also, the formation of a PMOS transistor in forming the peripheral circuit from CMOS transistors, as well as the formation of a high density layer for ohmic contact to the p-type diffusion layer are subsequently conducted by ion implantation. A CVD film 13 for insulation between the wirings is formed approximately 500 to 900nm (5000 to 9000 angstroms) thick by atmospheric pressure CVD. This process typically uses a BPSG film favorable in the subsequent wiring forming process, and therefore the BPSG film has been adopted. Subsequently, a reflow process is conducted for the flattening and the activation of ions implanted in the previous process. Further, contact holes are formed by photoetching, an Al-Si film is formed approximately 600 to 1000nm (6000 to 10000 angstroms) thick by sputtering, and a wiring pattern 15 is formed by photoetching. After undergoing the alloy process, a PSG film 14 is formed approximately 600 to 1000nm (6000 to 10000 angstroms) thick by atmospheric pressure CVD (Figs. 14 to 16). Through holes are opened by photoetching again to allow the connection of Al-Si between the second layer and the first layer to be made at a desired portion, Al-Si 16 of the second layer is formed approximately 800 to 1200nm (8000 to 12000 angstroms) thick by sputtering, with unnecessary portion for Al-Si of the second layer removed by photoetching, the alloy process is then conducted, a plasma nitride film 17 which is a passivation film is formed approximately 600 to 1200nm (6000 to 12000 angstroms) thick by plasma CVD, and bonding pads are bored by photoetching, so that the product is completed (Figs. 2 to 4, Fig. 17). The operation of the photoelectric conversion device will be described below with reference to an equivalent circuit of Fig. 6 and a timing chart of Fig. 18. First, the first reset operation for initializing all the pixels is effected (T1). With  1 ,  2 at high level, the base region B 3 is forward-biased with respect to the emitter region via capacitors C 1 , C 3 , whereby carriers are discharged. Thereafter if  1 ,  2 are set at low level, and  3 ,  4 are set at low level, the MOS transistors of photoelectric conversion cell are turned on, so that the voltage for all the pixels is rendered constant (V BG ). Then, the storage operation for storing light generated carriers is performed (T2). At this time, the MOS transistors MR 1 , MR 3 , MT 1 , MT 3 , MR 2 , MR 4 , MT 2 , MT 4 have been all turned off, and light generated carriers are stored in carrier storage regions PD1, PD3, (PD2, PD4). For the simplicity, two pixels on the left side of the figure will be explained, but two pixels on the right side operate exactly in the same way. Then, with  3 set at low level, carriers generated in the carrier storage region PD1 are transferred through the MOS transistor MT1 to the base region B 3 (T3). Then, carriers transferred are read at a reading pulse Φ1 (T4). At this time, the MOS transistor MR1 is naturally off, and the voltage of the base region B 3 is forward-biased with respect to the emitter region only with an overlap capacitor C 1 between the base region and the electrode, whereby the transistor operation of bipolar transistor Q 1 takes place. Subsequently, with Φ1, Φ3 at low level, the MOS transistors MR1, MT1 are turned on, and the reset operation for carriers generated in the carrier storage region PD1 is effected (T5). Thereby, the base region B 3 is set at an initial voltage again. Then, carriers generated in the carrier storage region PD2 are transferred, read, and reset at T6 to T8 in the same way, whereby a series of operations is completed and the operation returns back to T1. While in the embodiment as above described, the capacitors C 1 , C 2 for controlling the voltage of the base region are provided, it should be noted that the present invention can be also used without provision of such capacitors. As above described, in this embodiment, the opening ratio is raised and the sensitivity is improved by selectively connecting a plurality of photodiodes as the photoelectric converter in sequence with one bipolar transistor for amplification. Embodiment 2 Fig. 19 is an equivalent circuit diagram showing a second embodiment of a photoelectric conversion device according to the present invention. This embodiment will be described with an instance of a total of four pixels consisting of two pixels in the vertical direction and two pixels in the horizontal direction. As shown in the same figure, each pixel S (region as encircled by the broken line in the figure) is constituted of reset switch transistor MR11 to MR22 which is second switch means, transfer transistor MT11 to MT22 which is first switch means, signal reading transistor Q11 to Q22, and light charge storage capacitor C P 11 to C P 22, signal holding capacitor C B 11 to C B 22, and control capacitor C ox 11 to C ox 22, each of which is light signal storing means for a photodiode. In particular, the portions of light charge storage capacitors C P 11 to C P 22 are illuminated by light from the above, and the other portions are light-shielded to prevent light from penetrating therethrough. Note that the signal holding capacitors C B 11 to C B 22 and the control capacitors C ox 11 to C ox 22 constitute light signal holding means, wherein the signal holding capacitors C B 11 to C B 22 are base capacitors for signal reading transistors Q11 to Q22. The operation of the photoelectric conversion device in this embodiment will be described below with reference to a timing chart of Fig. 20. First, with the pulse  T1 set at low level, the PMOS transistors MT11 to MT22 are turned on, so that the light charge storage capacitors C P 11 to C P 22 and the signal holding capacitors C B 11 to C B 22 are set at the same voltage. Note that the common wiring via which pulse  T1 is applied to PMOS transistors MT11 to MT22 and pulse generating means (not shown) for  T1 constitute first control means. Then, if the pulse of  BR is set at low level with the pulse  T1 left at low level (at this time, V BB is set at a higher level than the low level pulse a threshold voltage of PMOS transistor), the PMOS transistors MT11 to MT22 and the MR11 to MR22 are turned on, so that the light charge storage capacitor C P 11 to C P 22 and the signal holding capacitor C B 11 to C B 22 for each pixel are reset to the initial voltage (first reset). Note that the common wiring via which pulse  BR is applied to PMOS transistors MR11 to MR22 and pulse generating means (not shown) for  BR constitute second control means. Then, with the pulse  VC set at high level, the NMOS transistors MV1, MV2 are turned on, and the emitter voltage of each pixel is set at V VC . In this state, the MOS transistors MP1, MP2 are turned on by a pulse number 2 as described below, and the horizontal drive lines VL1, VL2 are set at high level (voltage V CC ), the voltage in the base region of signal reading transistors Q11 to Q22 being elevated via the control capacitors C ox 11 to C ox 22 to forward-bias the base-emitter and discharge residual charges, so that the reset operation is effected concurrently for all the pixels. Thereafter, the MOS transistors MN1, MN2 are turned on by  RES , and the horizontal drive lines VL1, VL2 are caused to fall to low level (GND) at the same time, whereby the potential for the light charge storage capacitor C P 11 to C P 22 and the signal holding capacitor C B 11 to C B 22 for each pixel is made constant and biased in the reverse direction (second reset). Note that an NOR circuit, a pulse  RES , pulse generating means (not shown), MOS transistors MN1, MN2, and MOS transistors MP1, MP2 constitute the third control means. After the second reset is completed, a high pulse is applied to  T1 to turn off the PMOS transistors MT11 to MT22, the storage operation of light carriers is started concurrently for all the pixels in the photodiodes as represented by the light charge storage capacitors C P 11 to C P 22. Then, after the storage operation, with the pulse  T1 at low level for a certain period, carriers of the light charge storage capacitors C P 11 to C P 22 are transferred to the signal holding capacitors C B 11 to C B 22. The transfer efficiency at this time can be expressed by C pmn C pmn + C Bmn + C oxmn (where m, n is equal to 1 or 2) Thereafter, the pulse  R is selected by the NMOS transistor, to which the output of vertical shift register is applied, and then applied to the horizontal drive lines VL1, VL2, whereby a signal is read into the capacitors C T1 , C T2 through the MOS transistors M1, M2 to be controlled by the pulse  T2 . The signal read into the capacitors C T1 , C T2 is transferred to a horizontal output line 100 through the transfer MOS transistors MH1, MH2 to be selected by the horizontal shift register, and output through an output amplifier 101 from an output terminal 102. Note that the reset of the horizontal output line 100 is effected by setting the pulse  HRS to high level. As above described, in this embodiment, the storage operation is performed concurrently for all the pixels, and ended at the same time. Since in this embodiment, when the number of pixels is increased, R ON (on resistance) can be reduced by increasing the dimension corresponding to the NMOS transistors to which the output of vertical shift register is applied, there is no increase in the occupied area of third control means such as NOR circuit, even if the pixel pitch in the vertical direction is narrower or the number of pixels in the horizontal direction is increased. Embodiment 3 While in the second embodiment the PMOS transistors MT11 to MT22 are turned off by the rising of pulse  T1 after the second reset is ended, and immediately the storage operation for all the pixels is started, it is possible with no problem that the PMOS transistors MT11 to MT22 are left on during the storage operation, the transfer operation along with the storage operation is performed (i.e., carriers generated by the light charge storage capacitors C P 11 to C P 22 are instantaneously transferred to the signal holding capacitors C B 11 to C B 22), and after the storage (transfer) operation, the PMOS transistors MT11 to MT22 are turned off by applying a pulse  T1 . Then, the transfer efficiency from the light charge storage capacitors C P 11 to C P 22 to the signal holding capacitors C B 11 to C B 22 may be equal to 1. Embodiment 4 In the second embodiment the third control means is constituted of an NOR circuit, pulse  RES , pulse generating means of pulse number 2 (not shown), MOS transistors MN1, MN2, and MOS transistors MP1, MP2, and the output signal of the vertical shift register is input to NMOS transistors and the NOR circuit, but 1 No pulse  R is applied to the horizontal drive lines VL1, VL2 unless the output of vertical shift register is higher than the high level plus Vth (threshold level) of NMOS transistor. 2 When the micro structure of device is progressed, the reduction in the number of elements for the third control means is desired. In this fourth embodiment, the output signal of vertical shift register and the pulse  RES are input to an OR circuit, as shown in Fig. 21, which is connected to the horizontal drive lines VL1, VL2. With such a configuration, at the second reset, the pulse  RES is set at high level, the horizontal drive lines VL1, VL2 are caused to rise to high level concurrently, the pulse  RES is set at low level, and then the horizontal drive lines VL1, VL2 are set at low level. In the reading operation, read pulses V1, V2 are applied to the horizontal drive lines VL1, VL2 for each row selected by the output of the vertical shift register. The drive pulse in this embodiment is as shown in Fig. 22. According to this embodiment, the third control means can be constituted only of an OR circuit, and pulse generating means (not shown) of pulse  RES , and the high levels for all the pulses can be made equal. Embodiment 5 In the fourth embodiment, for example, when strong light illuminates a pixel at the right upper portion in Fig. 21, the voltage of light charge storage capacitor C P 12 will rise, and if exceeding a certain voltage, holes may flow into adjacent signal holding capacitor C B 11 or C B 12 through PMOS transistor MR 12 or MT 12 , thereby increasing the voltage. As a result, there may occur such a possible problem that a pizel at the left upper portion which is not illuminated by light may output a spurious light signal. Therefore, in this embodiment, the source terminals of PMOS transistors MR11 to MR22 are led out by wiring from each pixel, as shown in Fig. 23, and further the high level of base reset pulse  BR is set at an appropriate value of V CC or less. As a result, even if strong light illuminates a pixel at the right upper portion, and the voltage of light charge storage capacitor C P 12 may rise, carriers passing through the PMOS transistor MR 12 will flow into voltage source V BB , thereby preventing the occurrence of spurious signal between adjacent pixels. Note that the operation timing is exactly the same as in the third embodiment. Fig. 31 is a block diagram showing the configuration of a signal processing system such as a communication system, a facsimile apparatus, or a video recorder, using a photoelectric conversion device of the present invention. OR is an original carrying image information therein, 601 is an imaging lens, and 602 is a photoelectric conversion device of the present invention. The photoelectric conversion device 602 may be a unitary device in a simple communication system, for example, a line sensor for the facsimile, and an area sensor for the video recorder. 603 is a control circuit containing a central processing unit, which is connected via an input line 612, an output line 610 and a voltage source supply line 611 to the device 602. 604 is a recording control circuit which is connected to a recording head 605 to write information into a recording medium 606. The recording head 605 is a magnetic head in the case of video recorder, and a thermal head or an ink jet head in the case of facsimile. And the recording head 605 is contained by a recording apparatus placed at another site via cable in the case of communication system. As above described the number of main electrodes for the output of signal can be reduced to half that as conventionally used, without changing any conventional processes. As a result, the value of parasitic capacitor C vl for the signal line can be reduced to about 50 to 70% of the conventional one. The main electrode region conventionally existing in the central portion of one pixel moves to a separation portion of pixel, and the effective opening area can be increased about 20 to 30%. Also to operate a photoelectric conversion device having this structure, the sensitivity can be improved about 30 to 80% than conventionally, as a result of the accumulated effects such as the reduction in the parasitic capacitor C vl , and the increase in the effective opening area. Also the start and termination of the storage operation can be made coincident for all the pixels, so that it is possible to prevent distortion of output image from occurring when picking up a fast motion picture.

Claims: A photoelectric conversion device comprising: a first transistor (Q; Q 1 ) having a control electrode region (B 3 ) consisting of a semiconductor of one conduction type, and first and second main electrode regions (10) consisting of a semiconductor of opposite conduction type of said one conduction type, for outputting a signal from said first main electrode region (10) based on carriers transferred to said control electrode region (B 3 ); a first carrier storage region (PD1) provided adjacent to said first transistor (Q; Q 1 ), consisting of a semiconductor of said one conduction type for storing carriers generated by light energy being received; a second transistor (MT1), with said first carrier storage region (PD1) and said control electrode region (B 3 ) of said first transistor (Q; Q 1 ) as the source and drain regions, for transferring carriers stored in said first carrier storage region (PD1) to said control electrode region (B 3 ) of said first transistor (Q; Q 1 ); a second carrier storage region (PD3) provided adjacent to said first transistor (Q; Q 1 ), consisting of a semiconductor of said one conduction type for storing carriers generated by light energy being received; and a third transistor (MT3), with said second carrier storage region (PD3) and said control electrode region (B 3 ) of said first transistor (Q; Q 1 ) as the source and drain regions, for transferring carriers stored in said second carrier storage region (PD3) to said control electrode region (B 3 ) of said first transistor (Q; Q 1 ); wherein a first pixel is composed of said first transistor (Q; Q 1 ), said first carrier storage region (PD1) and said second transistor (MT1), and wherein a second pixel adjacent to said first pixel is composed of said first transistor (Q; Q 1 ), said second carrier storage region (PD3) and said third transistor (MT3). The photoelectric conversion device according to claim 1, wherein a capacitor (C 1 ) is made by forming an electrode (11) via an insulation film (4) at least in part on said control electrode region (B 3 ) of said first transistor (Q; Q 1 ), the voltage of said control electrode region (B 3 ) being controlled by the voltage control of said electrode (11). The photoelectric conversion device according to claim 1, wherein said photoelectric conversion cells are arranged in a matrix, adjacent carrier storage regions (PD1, PD3) between pixels in an array direction different from the array direction of said second transistor (MT1) acting as the source and drain regions. The photoelectric conversion device according to claim 1, wherein said first transistor (Q; Q 1 ) is commonly used among a plurality of pixels. A signal communication system having the photoelectric conversion device according to claim 1. The signal communication system according to claim 5, wherein said system further comprises a central processing unit for controlling said photoelectric conversion device. The signal communication system according to claim 5, further comprising a recording head (605). A method of driving the device of claim 1, comprising the steps of: turning on said second transistor (MT1) to read out a signal of said first pixel from said first transistor (Q; Q 1 ); and turning on said third transistor (MT3) to read out a signal of said second pixel from said first transistor (Q; Q 1 ). The method according to claim 8, wherein a plurality of said pixels is provided, and said second and third transistors (MT1, MT3) are turned on concurrently for all the pixels. The method according to claim 9, wherein a signal of each pixel is read sequentially after said second and third transistors (MT1, MT3) are turned on for all the pixels.

Inventors: ARIKAWA SHIRO, NAKAYAMA TOSHIKI, UENO ISAMU, ARIKAWA, SHIRO, NAKAYAMA, TOSHIKI, UENO, ISAMU, Arikawa, Shiro, c/o Canon Kabushiki Kaisha, NAKAYAMA, TOSHIKI, C/O CANON KABUSHIKI KAISHA, UENO, ISAMU, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: H01L27
IPC codes: H01L27