Hysteresis comparator working with a low voltage supply

Abstract: A hysteresis comparator circuit (1) working with a low voltage supply (Vcc) and of a type which comprises a composite structure incorporating first (2) and second (5) differential cells respectively comprised of an npn bipolar transistor pair (T1,T2) with common emitters, on the one side, and a pair of pnp bipolar transistor pair (T3,T4) with common emitters, on the other, such cells (2,5) being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources (A1,A2;A3,A4) associated with each cell (2,5) and tied operatively to the voltage value present on the comparator (1) output (O); in addition, a voltage divider is connected between each interconnection of the bases (B1,B4;B2,B3) of the transistors forming the cells (2,5).

Description: Field of Application This invention relates to an integrated comparator circuit working with a low voltage supply. More specifically, the invention relates to an integrated comparator comprising an input terminal to receive an input voltage, a reference terminal to receive a reference voltage, a first differential cell coupled to said input terminal and said reference terminal and including a pair of npn bipolar transistors with the emitters in common,a second differential cell coupled to said input terminal and said reference terminal and including a pair of pnp bipolar transistors with the emitters in common, said first and second differential cells being coupled together and to said input terminal and said reference terminal through the bases of their respective transistors. The field of application of the invention pertains in particular to hysteresis comparators, and the description to follow will make specific reference to this field of application for convenience of illlustration. Prior Art As is well known, comparators are circuits effective to compare two DC voltage values with each other, and to output two different set voltage values, according to whether an input signal Vin is higher or lower than a reference voltage Vr. Extensive use of comparators is made in integrated circuits, e.g. for controlling logic gates. On the other hand, for certain specific applications, the use of other hysteresis comparators is more appropriate, which comparators distinguish themselves from the former type by that the switching between the two output logic values is brought about by different input voltages. Of course, such comparators may also be implemented in integrated circuit form, and a typical example of a prior art integrated comparator is shown in Figure 1 of the accompanying drawings. The comparator of Figure 1 comprises a differential cell input stage which includes a first pair of bipolar transistors, of the npn type, connected in a common emitter configuration. The collectors of such transistors are connected to a power supply line at a voltage Vcc=1 Volt, via respective resistors. The bases of these transistors are instead available to serve as circuit inputs, the one for the reference voltage Vr and the other for the input signal Vin, for example. A second pair of bipolar transistors, of the pnp type, are associated with the input stage of the comparator. The bases of the transistors in this second pair are connected together and receive a bias voltage Vb1. The collectors of the first pair of npn transistors are each connected to the corresponding emitter of the second pair of pnp transistors, respectively. The comparator output O is taken from the collector of one transistor in the second pair. The circuit of Figure 1 exhibits a fairly small dynamic range in the common mode input voltage of about 0.9 Volts. The common mode voltage is the highest voltage that can be input without causing anomalous operation of the comparator. A development of the circuit in Figure 1 is shown in Figure 2, where an additional circuit portion is clearly discernible which is basically a follower arrangement and functions as a voltage level shifter. That circuit portion comprises a third pair of bipolar transistors, of the common base pnp type, which are connected between the supply Vcc and the signal inputs of the comparator. Each of these transistors is coupled to a resistor having one end connected to a corresponding base terminal of the first transistor pair in the input stage. Thus, the signal will not be applied to the differential stage directly, but supplied thereto through the follower. The voltage drop across each resistor will hold the bases of the first transistor pair in the input stage at a suitable voltage for proper operation of these transistors. However, according to the actual value of the common mode voltage at the inputs, a different variation of the voltage across the resistors may be required to keep the transistors operating correctly. A similar solution is disclosed in the article: "Motorola Technical Developments", vol. 12, April 1991, page 160: G. Allen et al. "Voltage comparator with hysteresis suitable for low, supply referenced thresholds". For situations such as this, the prior art has proposed a further solution shown in Figure 3. The circuit depicted in Figure 3 is structurally similar to that shown in Figure 1, except that a second input stage is provided here which comprises a pair of common-emitter pnp bipolar transistors. The circuit of Figure 3 substantially corresponds to a comparator disclosed in the Japanese patent application JP-A-58 94225 which relates to a circuit having two differential amplifier input stages. In essence, the last-mentioned solution provides a dual differential cell for the input circuit portion, which cell comprises a pair of npn bipolars, on the one side, and a pair of pnp bipolars, on the other. The two pairs are connected in parallel through the bases of their respective transistors. The first cell is driven by signals at a value close to the supply value Vcc, whereas the second cell operation is referenced to a signal ground value. However, with both transistor pairs in the "off" state, an indefinite condition occurs at the output O. This invention pertains to the technical approach represented by the third of the solutions discussed hereinabove. The underlying technical problem of this invention is to provide a hysteresis comparator, working with a low voltage, which has such structural and functional features as to overcome the drawbacks of the solutions currently proposed in the prior art and affords expanded dynamic range of the common mode input voltage. Summary of the Invention The solutive idea of the present invention provides for at least one pair of variable current sources associated with each differential cell and tied operatively to the comparator output voltage value. Based on this idea, the technical problem is solved by a comparator as indicated above in the introductory part and defined in the characterizing part of Claim 1. The features and advantages of a comparator according to the invention will become apparent from the following description of an embodiment thereof, given by way of example and not of limitation, with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a view showing diagramatically a hysteresis comparator circuit according to the prior art; Figure 2 is a view showing diagramatically a second hysteresis comparator circuit according to the prior art; Figure 3 is a view showing diagramatically a third hysteresis comparator circuit according to the prior art; Figure 4 is a view showing diagramatically a comparator circuit according to the invention; Figure 5 is a view showing diagramatically and in greater detail the circuit in Figure 4. Detailed Description With reference to figure 4, generally and schematically shown is a hysteresis comparator circuit embodying this invention. This comparator comprises a first differential cell including a first pair of npn-type bipolar transistors T1 and T2 which have their respective emitters in common. Those emitters are also connected to a signal ground GND via a bias current source which comprises a transistor Tn on whose base a voltage Vb3 appears. The collectors C1, C2 of the transistors T1, T2 are connected, through respective resistors Rc1 and Rc2, to a power supply line 3 on which a relatively low voltage value Vcc of 1 Volt is present. The bases B1, B2 of the transistors T1, T2 are, in turn, connected to the line 3 through respective variable current sources A1, A2. Advantageously, such current sources are controlled by and tied operatively to the value of the voltage at the output O of the comparator. The circuit of figure 4 further comprises a second differential cell 5 including a second transistor pair, T3 and T4. This second pair is formed by pnp-type bipolars being, in turn, interconnected with their respective emitters. Those emitters are also connected to the supply line 3 via a bias current source which comprises a transistor Tp at whose base a bias voltage Vb1 appears. The collectors C3, C4 of the transistors T3, T4 are connected to ground at GND via respective resistors Rc3 and Rc4. The bases B3, B4 of the transistors T3, T4 are also connected to ground at GND, via respective variable current sources A3, A4. These current sources are also controlled by and tied operatively to the value of the voltage present at the comparator output O. The two differential cells 2 and 5 are coupled together through respective connections between the bases B1, B4 and the bases B2, B3 of the corresponding transistors. A voltage divider is connected between each of said base interconnections. Specifically, a first resistor pair R1, R4 are connected between the bases B1, B4, and a second resistor pair R2, R3 are connected between the bases B2 and B3. Preferably, the resistors R1, R2, R3 and R4 have equal values, as equal values have the currents I1, I2 and I3, I4, respectively. The point of interconnection of the first resistor pair R1, R4 is the inverting (IN-) input A of the comparator. On the other hand, the point of interconnection of the second resistor pair R2, R3 is the non-inverting (IN+) input B of the comparator 1. The structure of the circuit of figure 4 is completed by a third pair of pnp-type bipolar transistors T9, T11 having corresponding emitters connected directly to the respective collectors C1, C2 of the first transistor pair T1, T2 in the cell 2. The transistors T9 and T11 have common-base and are supplied by a base voltage Vb2. A fourth bipolar transistor pair T12, T13 of the npn type are provided in association with the second cell 5. Specifically, the transistors T12, T13 which form this fourth pair have corresponding emitters connected directly to the respective collectors C3, C4 of the second transistor pair T3, T4 in the cell 5. The transistors T12 and T13 have common-base, and the first, T12, of them has its base connected to the collector to thereby produce a diode configuration. The first transistor T9 in the third pair is connected to the first transistor T12 in the fourth pair through the connection between their respective collectors. Likewise, the second transistor T11 in the third pair is connected to the second transistor T13 in the fourth pair through the connection between the respective collectors thereof, and the output O from the comparator circuit is actually taken from the common collector of transistors T11 and T13. This output O provides a voltage output value Vo. The operation of the circuit according to the invention will now be described. The composite, npn and pnp, structure of the cells 2 and 5 is connected to the signal inputs A and B, through the resistors R1, R2, R3, R4 and the variable current sources A1, A2, A3, A4, and provides a shift in logic level whose value is controlled by the state of the output O. The value of the output O also controls, as with any hysteresis comparators, the switching phase between the two (upper and lower) circuit thresholds. The current source A1 is suitably sized to ensure proper operation of the first transistor pair in the input stage, and hence an appropriate state of the output O. Assume that the signal voltage Vin(+) at the non-inverting input B is lower than Vin(-) at the inverting input A. For example, Vin(-) could be equal to the upper threshold Vth sup , and the shift level properly selected on the basis of that upper threshold. Under these conditions, the transistor T1 would operate in the active region until the input voltage Vin(+) attains the upper threshold Vth sup . When this threshold value is exceeded, the voltage Vin(+) will drive the comparator to shift its output to the lower threshold value Vth inf . At this time, the variable source A1, being tied operatively to the output O, is forced to change its outgoing current value by activating the second cell 5 formed by the pnp transistor pair T3 and T4. This method of operation affords great freedom of selection of the two discrete threshold levels, thereby expanding the dynamic range of the common mode input voltage. Now, a preferred embodiment of the circuit of figure 4 according to the invention is shown diagramatically in Figure 5. As can be more clearly inferred from Figure 5, the variable sources A1 and A2 are embodied by pnp bipolar transistors driven through their respective bases. The variable sources A3 and A4 are likewise embodied by npn bipolar transistors. The output O of the circuit corresponds to the base terminal of an npn transistor T14 having the emitter grounded and the collector connected to the supply Vcc via a current source I. The collector of this transistor T14 is connected to the base of an npn transistor T5 having the emitter grounded. The base of the transistor T5 also assumes the logic value of negated output O for the comparator. The collector of the transistor T5 is connected to the respective bases of a set of npn transistors T6, T7, T8 and T10 connected in parallel together, with their emitters grounded. The collectors of the transistors T6 and T7 are in common with those of the respective npn transistors incorporated to the current sources A3 and A4. The first, T6, in said transistor set has its collector connected to the collector of a further transistor T15, and through the latter, to the base terminals of the pnp transistors incorporated to the current sources A1 and A2. A diode D1 connects that collector to the supply Vcc as well. The last-mentioned transistor, T15, which is also an npn bipolar type, has its base in common with those of the transistors incorporated to the current sources A3 and A4 and connected between a current source I' associated with the supply Vcc, and a diode D2 connected to ground. A similar structure comprising the series of a current source I" and a diode D3, is associated with the base of the transistor T10. The collector of the transistor T10 is connected to the non-inverting input B, whereto the upper voltage threshold value Vth sup is applied via a resistor R5. Assuming for the lower voltage threshold Vth inf a logic level shift above that required for the upper threshold, then the current source I' will continue to be correlated to this upper threshold value. Upon the output O attaining a "high" logic level, the corresponding negated output O will be at a logic "low". Under this condition, the current I" is allowed to flow through the diode D3 and will be mirrored by the transistor T10 to generate hysteresis of the circuit. Through the transistors T6, T7 and T8, the shift in logic level is expanded as required for the lower threshold Vth inf .

Claims: An integrated comparator (1) comprising: a first input terminal (A) to receive a first input voltage; a second input terminal (B) to receive a second input voltage; a first reference terminal to receive a first reference voltage (Vcc); a second reference terminal to receive a second reference voltage (GND); a first differential cell (2) including a first and a second npn bipolar transistors (T1,T2) with the emitters in common, the base of said first transistor (T1) being coupled to said first input terminal (A) and to said first reference terminal; a second differential cell (5) including a third and a fourth pnp bipolar transistors (T3,T4) with the emitters in common, the base of said fourth transistor (T4) being coupled to said first input terminal (A) and to said second reference terminal; said first and second differential cells (2,5) being coupled together and to said second input terminal (B) and said first and second reference terminals through the bases of said second and third transistors (T2, T3), characterized in that it comprises at least one pair of variable current sources (A1,A2;A3,A4) in each cell (2,5) coupled between the base of each of said four transistors (T1, T2, T3, T4) and the corresponding reference terminal, and generating a current whose value depends on the voltage value present at the output (O) of the comparator (1). A comparator according to Claim 1, characterized in that the comparator further comprises voltage dividers connected between each of the interconnections of the bases (B1,B4;B2,B3) of the transistors forming said cells (2,5). A comparator according to Claim 2, characterized in that each divider comprises a pair of resistors (R1,R4;R2,R3), said input terminal and said reference terminal being connected to the point of interconnection of said pair. A comparator according to Claim 3, characterized in that the resistors (R1,R4;R2,R3) connected in said dividers have equal values. A comparator according to Claim 1, characterized in that each of said variable current sources (A1,A2,A3,A4) comprises a transistor. A comparator according to Claim 5, characterized in that the base of each of said transistors in said variable current sources is coupled to the comparator output (O). A comparator according to Claim 1, characterized in that the variable current sources (A1,A2) in said first differential cell (2) are each connected between the bases (B1,B2) of the npn transistors (T1,T2) and a low-voltage supply line (Vcc). A comparator according to Claim 1, characterized in that the variable current sources (A3,A4) in said second cell (5) are each connected between the bases (B3,B4) of the pnp transistors (T3,T4) and a signal ground (GND).

Inventors: ROSSI DOMENICO, TATEOKA MASAYUKI, ROSSI, DOMENICO, TATEOKA, MASAYUKI, TATEOKA, MASAYUKI, C/O SGS-THOMSON MICROELECT,K.K.
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H03K3
IPC codes: H03K5, G01R19, H03K3