Signal detecting circuit apparatus

Abstract: A signal detecting apparatus is to obtain hysteresis characteristic at a constant ratio regardless of signal amplitude fluctuations by supplying the threshold level adjusting signal corresponding to the input signal amplitude to the comparison circuit. The threshold value setting signal and the hysteresis adjusting signal is supplied to a comparison circuit through an amplifier and a hysteresis adjusting means having the identical characteristic with the peak hold circuit to set a threshold value and a hysteresis range. Therefore even in the case where the operating characteristic of the amplifier and the peak hold circuit for detecting the peak level of signal amplitude fluctuate, the threshold value and the hysteresis range fluctuation corresponding to the fluctuation. As a result, there can not need the adjustment for resetting the operating characteristic, the threshold value and the hysteresis range in each circuit and thus the time and labor required for adjustment can be further saved.

Description: FIELD OF THE INVENTION This invention relates to a signal detecting circuit apparatus, and is applicable to a signal input judging device and its comparison circuit for judging the existence of optical input to be inputted via an optical fiber for example. BACKGROUND OF THE INVENTION Heretofore, as shown in Fig. 1, in the optical fiber transmission system 1 which is transmitted via optical fiber, the transmitting data is reproduced from receiving signals received via the optical fiber. More specifically, when an optical input S1 transmitted via the optical fiber is received at a photodiode 2 for example, which converts it into a input signal S2 to be supplied to a current/voltage converting circuit 3. An input voltage signal S3 converted into by the current/voltage converting is supplied to an optical input receiving unit 4, in which the voltage signal S3 is amplified by a main amplifier 5 so as to reproduce the transmitting data based on the receiving signal S4 obtained therefrom. Thus, in the optical fiber transmission system 1, the transmitting data is reproduced from the receiving signal S4 outputted from the main amplifier 5, but also the receiving signal S4 is supplied to an alarm signal generation circuit 6 to judge whether the optical input S1 to be inputted exists or not. In the alarm signal generation circuit 6, the receiving signal S4 is inputted to a peak hold circuit 7 to detect the peak level and the detecting result is supplied to a comparison circuit 8. Then the comparison circuit 8 judges whether the optical input S1 is inputted or not depending on the comparison result between the peak level detection signal S5 inputted from the peak hold circuit 7 and the reference voltage, and outputs an alarm signal S6. For example, in the case where the signal level of the receiving signal S4 is being dropped when the optical fiber is disconnected from the connector, the comparison circuit 8 judges that the optical input S1 is not inputted and then the peak level is lower than the reference voltage, so as to make the logical value of the alarm signal S6 rise to "H" level which is outputted to the peripheral device. Since there is a possibility of noises to be generated in the preprocessing circuits (i.e., photodiode 2, current/voltage converter 3, etc.) mixing in the peak level detection signal S5 to be inputted to the comparison circuit 8, the hysteresis characteristic is provided in the comparison circuit 8 and the hysteresis range can be adjusted by the hysteresis adjusting signal S7. Furthermore, since the dynamic range of peak level detection signal S5 to be inputted to the comparison circuit 8 fluctuates around 10 times according to the type of the photodiode 2 (e.g., avalanche photodiode and pin photodiode) and the difference of gains of the current/voltage converter 3, the reference voltage can be also adjusted by the threshold level setting signal S8 as shown in Figs. 2A and 2B. However, in case of the optical fiber transmission system 1, whenever the input level of receiving signal S4 fluctuates according to the combination of circuit elements to be used in the preprocessing circuits and the scattering of their operating characteristic and their its operating temperature, the hysteresis range and the reference voltage must be adjusted according to the hysteresis adjusting signal S7 to be inputted from the adjusting terminal and the threshold level setting signal S8. Therefore, it required a great deal of labor for adjustment. Furthermore, as shown in Fig. 3, this type of conventional hysteresis variable type comparison circuit 8 generates the voltage in proportion to the hysteresis by giving comparison outputs V OUT1 and V OUT2 to be outputted from the differential input stage constituted by a pair of NPN-type transistors Q1 and Q2 through buffer transistors Q3 and Q4 to the base of transistors Q5 and Q6 so as to feedback the offset current corresponding to the comparison outputs V OUT1 and V OUT2 to load resistances R1 and R2 (provided, resistance values are both R). More specifically, in the comparison circuit 8, the hysteresis range (R x I2) can be adjusted by adjusting the current I2 to be drawn into the current source 9 connected to the common emitter of transistors Q5 and Q6 which constitute the latch circuit. However, in this type of comparison circuit 8, since the current I2 decreases at a fixed ratio and gains of the latch circuit also decrease as input amplitude decreases if hysteresis would be given to the input amplitude at a constant ratio, in the case where the input amplitude is small and the signal level of the receiving signal S4 is near by reference voltage omit, there become problems that transistors Q5 and Q6 do not function switching, hysteresis does not function properly and the input dynamic range comes narrow. Document US-A-4 375 037 discloses a signal receiving circuit according to the preamble of claim 1. The known circuit awns a pre-processing circuit for an input signal and a reference pre-processing circuit that has the same circuit arrangement as the first mentioned pre-processing circuit. SUMMARY OF THE INVENTION In view of the foregoing, an object of this invention is to provide a signal detecting circuit apparatus capable of making the input dynamic range wider than the prior device as well as canceling the necessity of fine adjustment of the reference voltage and hysteresis range to proper values corresponding to the system construction of an optical fiber transmission system. This aim is achieved by a signal input judging apparatus having the features set out in claim 1. According to the present invention, the threshold value adjusting signal and the hysteresis adjusting signal corresponding to said threshold value adjusting signal are supplied to the comparison means through the hysteresis adjusting means having the identical characteristic with the amplifier and the peak-hold circuit, so that the scattering of circuit elements which compose the amplifier and the peak-hold circuit and the fluctuation of operating temperature of each circuit can be canceled, whereby the adjustment of operating characteristic, threshold value and hysteresis range of each circuit required each time when operating temperature and others fluctuate will become unnecessary. Furthermore, a comparison output of the comparison unit is converted into 2-valued data which is then multiplied by the hysteresis adjusting signal, and the multiplied result corresponding to hysteresis range is feedbacked to the comparison unit as offset voltage, so that the trouble in the prior art that the hysteresis operation becomes unstable in the case where the signal level of input signal is small, can be effectively avoided, whereby the thus the input dynamic range can be made wider. The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: Fig. 1 is a block diagram illustrating the conventional signal judging circuit; Figs. 2A and 2B are signal waveform diagrams showing a operating characteristic of the signal judging circuit shown in Fig. 1; Fig. 3 is an equivalent circuit diagram illustrating the conventional comparison circuit to be used in the signal judging circuit shown in Fig. 1; Fig. 4 is a block diagram illustrating first embodiment of the signal detecting circuit according to this invention; Fig. 5 is an equivalent circuit diagram illustrating the comparison circuit to be used in the signal detecting circuit shown in Fig. 4; and Fig. 6 is a block diagram illustrating other signal detecting circuit (not claimed). DETAILED DESCRIPTION OF THE INVENTION Preferred embodiments of this invention will be described with reference to the accompanying drawings: Fig. 4 denotes one embodiment of the present invention. 20 generally shows an optical fiber transmission system. In the optical fiber transmission system 1, a photodiode 32 receives an optical input S11 which is converted into an input current signal S12 in it, and the input current S12 is converted into input voltage signal S13 in a current to voltage converting circuit 33 so as to input the input voltage signal S13 to a peak hold circuit 37 of an alarm signal generation circuit 22 through a main amplifier 35 of an optical input receiving unit 21. The alarm signal generation circuit 21 comprises a threshold level setting amplifier 23 and a peak hold circuit 24. The threshold level setting amplifier 23 amplifies the alarm signal setting signal S21 to supply it to the peak hold circuit 24, a peak hold voltage of which is supplied to a comparison circuit 30 as threshold level setting signal S18. Moreover, the threshold level setting signal S18 is supplied to the comparison circuit 30 through the hysteresis adjusting amplifier 25 as hysteresis adjusting signal S17, so that the hysteresis range of the comparison circuit 30 can be set in proportion to the input amplitude. Nextly, the construction of comparison circuit 30 of this embodiment will be described with Fig. 5 in detail. The comparison circuit 30 which is composed of a comparison unit 41, a latch unit 42 and a multiplying unit 43, is to convert comparison outputs S31 and S32 of the comparison unit 41 into digital signals D31 and D32 at the latch unit 42 and to output as alarm signal S16 and reverse alarm signal S16I. The comparison unit 41 inputs peak hold voltage S15 and threshold level setting signal S18 to transistors Q31 and Q32 composed of a differential pair, and outputs reverse comparison output S31 and in-phase comparison output S32 from connecting nodes P31 and P32 of load resistances R31 and R32 connected to the collector. Here, the other ends of load resistances R31 and R32 are connected to the connecting nodes P33 and P34 of buffer transistors Q33 and Q34 and current sources 55 and 56, so that offset signals V31 and V32 are feedbacked through the buffer transistors Q33 and Q34. With this arrangement, offset arises corresponding to hysteresis adjusting voltage to the reference potential V CC at connecting nodes P33 and P34, and even in the case where peak hold voltage S15 which is almost equal to threshold level setting signal S18 is inputted, the comparison circuit 30 acts the normal hysteresis function. The comparison unit 41 outputs reverse comparison output S31 and in-phase comparison output S32 to the latch unit 42 of the following stage through buffer transistors Q35 and Q36. In this connection, the common emitter for transistors Q31 and Q32 and emitters of buffer transistors Q35 and Q36 are respectively connected to the current sources 57, 58 and 59. The latch unit 42 sequentially outputs in-phase comparison output S32 and reverse comparison output S31 through an amplifier 60 and a R-S flip flop circuit 61 and converts reverse comparison output S31 and in-phase comparison output S32 which are analog outputs, into digital outputs D31 and D32 so as to output them to a multiplying unit 43 as Q output and IQ output. The multiplying unit 43 is composed of transistors Q37 and Q38, and Q39 and Q40 which form differential pairs respectively, and transistors Q41 and Q42 connected to the differential pairs to form a multiplying circuit. Emitters of the transistors Q41 and Q42 are connected each other through input resistance R34. Also, Q output and IQ output are inputted to the base of transistors Q37 and Q38, and Q39 and Q40 respectively, and hysteresis adjusting signals S17I and S17 to be inputted to the transistors Q41 and Q42 are multiplied. With this arrangement, the multiplying unit 43 generates difference voltage corresponding to the hysteresis range to load resistances R35 and R36 connected to the common corrector with transistors Q38 and Q39, Q37 and Q40 to be given reverse logical output to each other so as to feedback to the comparison unit 41 as offset voltages V32 and V31. The comparison circuit 30 turns off transistors Q37 and Q39 of the multiplying unit 43 and on the other hand, operates transistors Q38 and Q40, in the case where peak-hold voltage V REF + V ΔV which is almost equivalent to the voltage level V REF of threshold level setting signal S18 is inputted and Q output and IQ output of the latch unit 42 are logic "L" and logic "H" respectively. At this point, if the difference of voltages V S17 and V S17I (V S17 > V S17I ) of hysteresis adjusting signals S17I and S17 to be supplied to transistors Q41 and Q42 is V CONT , the transistors Q41 and Q42 produce the current difference as given by the following equations: I13 = I12 - V CONT /R34 I14 = I12 + V CONT /R34 Here, voltages of the load resistances R35 and R36 drop respectively as expressed in the following equations: V CC - V32 = I13 x R V CC - V31 = I14 x R (however, R35 = R36 = R) and between voltages V31 and V32, the offset voltage corresponding to the hysteresis control voltage is produced as expressed in the following equation: V32 - V31 = (I14 - I13) x R = 2 x V CONT x R R34 As a result, the offset voltage corresponding to the hysteresis control voltage V CONT is feedbacked to the comparison unit 41 regardless of input signal amplitude. Therefore the troubles that hysteresis becomes unstable and input dynamic range becomes narrow when the input amplitude is small, can be effectively avoided. Accordingly, the comparison circuit 30 is able to generate the hysteresis range with the prescribed ratio even if the input amplitude is either large or small and thus the hysteresis variable type comparison circuit having wide input dynamic range can be obtained. According to the foregoing construction, in the case where the combination of types of diode elements to be used as a photodiode 32 and gains of a current/voltage converter 33 are fluctuated, the user may input the alarm signal setting voltage S21 corresponding to said combination to an alarm signal generation circuit 21 from the external terminal, and then the threshold level V REF of the comparison circuit 30 and hysteresis range are set at once by inputting the alarm signal setting voltage S21. In Fig. 4, since the threshold level setting amplifier 23 and the peak hold circuit 24 are composed of the identical construction with the conventional block of main amplifier shown in Fig. 1 and the peak hold circuit. That is, in the case where the application conditions (operating temperature, current source voltage and the amount of scattering of operating characteristic during the manufacturing process) of the main amplifier 23 and the peak hold circuit 24 in which the receiving signal S21 is inputted, fluctuate and in the case where the gain fluctuates, the hysteresis adjusting voltage S17 and threshold level setting voltage S18 are increased and decreased according to the fluctuates. Accordingly, in the case where the application condition of the alarm signal generation circuit 21 fluctuates, the comparison circuit 30 also can execute the comparison function with an appropriate threshold level and hysteresis range of the fixed ratio given at the time of setting, and the necessity of re-adjustment on the operating condition of each circuit element which was required before whenever the application condition changes can be canceled. According to the foregoing construction, there is provided the threshold level setting amplifier 23 and the peak hold circuit 24 having the identical construction with the main amplifier 35 and the peak hold circuit 37 which supply the voltage signal S13 converted from the optical input S11 to the comparison circuit 30, and the hysteresis adjusting voltage S17 corresponding to the input amplitude is supplied via said threshold level setting amplifier 23 and the peak hold circuit 24, so that the constant hysteresis function can be obtained in the comparison circuit 30 regardless of the application condition and the combination of circuit elements. The modification of the above embodiment of the present invention will be described. The embodiment discussed above has dealt with the case of amplifying the threshold level setting signal S18 at the hysteresis adjusting amplifier 25 and supplying to the comparison circuit 30 as the hysteresis adjusting signal S17. The present invention is not, however, only limited to this, but also it is applicable to the case of supplying the threshold level setting signal S18 directly to the comparison circuit 30 as the hysteresis adjusting voltage S17. Furthermore, the embodiment discussed above has dealt with the case of forming the hysteresis adjusting signal S17 depending upon the alarm signal setting signal S21. The peak level of the optical input S41 may also be amplified via the amplifier 87 as shown in Fig. 6 and it may be treated as the hysteresis adjusting voltage S47. Such embodiment, however, is not claimed. With this arrangement, the optical fiber transmission system 85 can apply hysteresis to the optical input S41 with the wide input dynamic range and at the fixed ratio constantly. Moreover, the embodiment shown in Fig. 5 discussed above has dealt with the case of constituting the latch unit 42 of the comparison circuit 30 by amplifiers 60 and 61. However, the present invention is not only limited to this, but also the D-latch may be used and also it is widely applicable to the case where utilizing the high gain limiter amplifier without latch function. While there has been described in connection with the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be aimed.

Claims: A signal input judging apparatus for judging an input of an input signal to a receiver (21) by inputting the peak level of receiving signals sequentially detected via an amplifier (35) and a peak hold circuit (37) to a comparison means (30) and by outputting the comparison result of said peak level and a threshold value as a signal input detection signal, characterized by hysteresis adjusting means (23, 24) for supplying a signal of a predetermined level to said comparison means (30) as a threshold value adjusting signal (S18), and simultaneously supplying a hysteresis adjusting signal (S17) corresponding to said threshold value adjusting signal (S18), and for setting the reference signal level of said threshold value and hysteresis range, wherein: said hysteresis adjusting means (23, 24) comprise an amplifier (23) and a peak hold circuit (24) having identical construction with said amplifier (35) and peak hold circuit (37) for sequentially detecting the receiving signals. The signal input judging apparatus of claim 1, characterized in that said hysteresis adjusting means (23, 24) supplies an amplified reference level setting signal to said comparison means (30) as said threshold value adjusting signal (S18). The signal input judging apparatus of claim 1 or 2, characterized in that said comparison means (30) comprises: a comparison unit (41) for comparing said peak level and said threshold value and outputting the comparison result as a comparison output; a latch unit (42) for outputting said comparison output after converting into 2-value data; and a multiplying unit (43) for adjusting a hysteresis range of said threshold value by outputting said 2-value data as a signal input detection signal and simultaneously multiplying said 2-value data by said hysteresis adjusting signal and feedbacking said multiplication result to said comparison unit (41).

Inventors: KIBAYASHI KENJI, MATSUMOTO ISAO, MURAKAMI DAISUKE, NISHIE MITSUAKI, TAKAHASHI SATOSHI, UESAKA KATSUMI, YOSHIDA HIDEKI, KIBAYASHI, KENJI, MATSUMOTO, ISAO, MURAKAMI, DAISUKE, NISHIE, MITSUAKI, TAKAHASHI, SATOSHI, UESAKA, KATSUMI, YOSHIDA, HIDEKI, Kibayashi, Kenji, c/o Sony Corporation, Matsumoto, Isao, c/o Sony Corporation, Murakami, Daisuke, c/o SONY CORPORATION, Nishie, Mitsuaki, c/o Sumitomo Electric Ind., Ltd., Takahashi, Satoshi, c/o Sumitomo Electric Ind. Ltd, Uesaka, Katsumi, c/o Sony Corporation, Yoshida, Hideki, c/o Sony Corporation
Applicants: SONY CORP, SUMITOMO ELECTRIC INDUSTRIES, SONY CORPORATION, SUMITOMO ELECTRIC INDUSTRIES, LTD.
Application year: 1993
Main classification: H03K5
IPC codes: H04B10, H03F3, H03K5, H03K3