Power converter for converting DC voltage into AC phase voltage having three levels of positive, zero and negative voltage

Abstract: In an apparatus for a three-level DC/AC converter, the width of output pulses having the same polarity as the fundamental wave of the converter output phase voltage is adjusted depending upon the DC component of a differential voltage between two DC voltages in a dipolar modulation system of the converter. An imbalance of DC components between the two DC voltages is thereby easily and effectively suppressed.

Description: [Background of the Invention] This invention relates to an apparatus for controlling a power converter which converts a DC voltage fed from a DC voltage dividing capacitors that are connected in series into an AC phase voltage having positive, zero and negative three potentials. When a load such as an induction motor is to be driven by a pulse-width modulation invertor, it is desired that the AC output voltage of the invertor contains harmonic components as little as possible. To satisfy this requirement, there has been proposed an invertor called a three-level invertor. Such an invertor has been proposed in, for example, "A Novel Approach to the Generation and Optimization of Three-Level PWM Wave Forms" (PESC '88 Record, April 1988), pp. 1255-1262 (hereinafter referred to as literature 1). This literature 1 proposes a dipolar modulation system which alternatingly outputs positive and negative pulse voltages via zero voltage as a modulation system suited for improving the wave forms and for controlling very small voltages of the three-level invertor. Voltage utilization factor decreases since very small voltages are controlled by using pulses having a polarity opposite to the fundamental wave of the output phase voltage. This literature 1 further describes a control system which features a high voltage utilization factor, i.e., describes the shifting toward a unipolar modulation system which outputs a plurality of pulse voltages having only the same polarity as the fundamental wave of the output phase voltage. On the other hand, problems inherent in the three-level invertor will be represented by such phenomena as imbalance in the capacitances of the capacitors that are connected in series to divide a DC voltage into two, and imbalance in the DC components between the divided two DC voltages caused by DC components of a current flowing into and out of a point at which the capacitors are connected in series due to variance in the output pulses from the invertor. Technologies which suppress this imbalance have been disclosed in Japanese Patent Laid-Open No. 101969/1990 and in "Balancing of DC Input Capacitor Voltages of an NPC Invertor" (Material of the Society of Study, Japanese Association of Electric Engineering, Society for Studying Semiconductor Power Conversion, SPC-91-37, 1991/6), pp. 111-120 (hereinafter referred to as literature 2). According to the technology for suppressing imbalance of DC components between the two DC voltages disclosed in Japanese Patent Laid-Open No. 101969/1990, the amplitudes of two modulated waves of sinusoidal shapes are changed in the dipolar modulation system of the literature 1. As will be described later, however, this technology causes the shifting amount (bias amount) to be changed, too. To bring the change back, the shifting amount must be adjusted again in the latter stage of control, causing the control operation to become complex. According to the technology of suppressing the imbalance of DC components between the two DC voltages disclosed in the literature 2, a signal corresponding to a DC component of a differential voltage between the two DC voltages is superposed on an invertor voltage instruction in the unipolar modulation system of the literature 1. Now, when the above-mentioned three-level invertor is adapted to an electric car, the output voltage is continuously controlled from zero through up to near a possible maximum voltage. Therefore, it becomes necessary to shift the modulation system (modulation mode) from the dipolar modulation system (modulation mode) into the unipolar modulation system (modulation mode). Here, however, the circuit constitution and control operation become complex if the above-mentioned technologies for suppressing the imbalance of DC components between the two DC voltages are adapted depending upon the modulation systems. [Summary of the Invention] The object of the present invention is to suppress the imbalance of DC components between the two DC voltages simply and efficiently in the dipolar modulation system (modulation mode). Another object of the present invention is to simplify the operation for suppressing the imbalance of DC components between the two DC voltages in an electric car to which are adapted the dipolar modulation system (modulation mode) and another modulation system (modulation mode). The above-mentioned object is achieved by a power converter as disclosed in claim 1. Another object of the present invention is achieved by an apparatus for controlling an electric car as disclosed in claim 10. In the dipolar modulation system, the width of an output pulse having one polarity of the output phase voltage is adjusted depending on the DC component of a differential voltage between the divided two DC voltages, in order to control the DC component of a current that flows into or out of a point where the capacitors are connected in series. Therefore, the imbalance of DC components between the two DC voltages is suppressed requiring a simple control operation and efficiently. In the electric car to which are adapted the dipolar modulation system and another modulation system, furthermore, a means for suppressing the imbalance of DC component between the two DC voltages is commonly used irrespective of the modulation system, contributing to simplifying the control operation. [Brief Description of the Drawings] Fig. 1 is a diagram of a circuit constitution illustrating an embodiment of the present invention. Fig. 2 is a diagram illustrating the operation of a dipolar modulation. Fig. 3 is a diagram illustrating the operation of a partial dipolar modulation. Fig. 4 is a diagram illustrating the operation of a unipolar modulation. Fig. 5 is a diagram illustrating the operation of an over-modulation. Fig. 6 is a diagram illustrating the operation of a one-pulse modulation. Fig. 7 is a diagram illustrating the operation of a current flowing into or out of the neutral point during the dipolar modulation. Fig. 8 is a diagram illustrating the operation of a case when a prior art is adapted to the dipolar modulation. Fig. 9 is a diagram illustrating the operation of a case when a prior art is adapted to the unipolar modulation. Fig. 10 is a diagram illustrating the operation of the dipolar modulation according to the present invention. Fig. 11 is a diagram illustrating the operation of the dipolar modulation according to another embodiment of the present invention. Fig. 12 is a diagram illustrating the operation of the unipolar modulation according to the present invention. Fig. 13 is a diagram illustrating a signal corresponding to a DC component of a differential voltage between the two DC voltages. Fig. 14 is a diagram illustrating the operation of a dipolar modulation different from the dipolar modulation of Fig. 2. Fig. 15 is a diagram of a circuit constitution illustrating an another embodiment of the present invention. [Detailed Description of the Preferred Embodiments] Fig. 1 shows a circuit constitution according to an embodiment of the present invention. Reference numeral 1 denotes a DC trolley wire, 21 denotes a reactor for smoothing the current, 22 and 23 denote voltage-dividing capacitors that are connected in series to divide the voltage V d of the DC stringing 1 into two DC voltages V db and V dn , reference numeral 3 denotes a pulse-width modulation three-level invertor which converts two DC voltages into a three-phase AC voltage, and reference numeral 4 denotes an induction motor driven by the invertor 3. The invertor 3 comprises three level-switching arms of U-phase, V-phase and W-phase. The switching arm of the U-phase (V-phase, W-phase) is made up of switching elements (such as IGBT, GTO, power transistors, etc.) G1U to G4U (G1V to G4V, G1W to G4W) which are capable of extinguishing the arc by themselves, rectifier elements (fly wheel diodes) D1U to D4U (D1V to D4V, D1W to D4W), and auxiliary rectifier elements (cramping diodes) D5U to D6U (D5V to D6V, D5W to D6W). The points at which the auxiliary rectifier elements D5U and D6U, D5V and D6V, and D5W and D6W are connected together, are connected to a point (hereinafter referred to as neutral point) N at which the voltage-dividing capacitors 22 and 23 are connected in series. The turn-on and -off operations of the switching elements G1U to G4U, G1V to G4V and G1W to G4W shown in Table 1 are carried out by the output of the modulation means 5, and voltages (phase voltages) of three levels V dp , 0 and V dn are output between the neutral point N and the output terminals U, V and W. Next, the constitution of the modulation means 5 and the dipolar modulation will be described with reference to Figs. 1 and 2. These drawings illustrate those of one phase only. An output frequency instruction Finv* of the invertor 3 is given by the addition and subtraction of a rotating frequency of the motor 4 and a slip frequency that is obtained based on a deviation between a current instruction for the motor 4 and a real current of the motor 4. In a fundamental wave voltage instruction generating means 51, a fundamental wave (sin) generating means 511 outputs a fundamental sinusoidal wave upon receipt of the invertor output frequency instruction F inv *, and an amplitude calculation means 512 calculates and outputs a fundamental wave voltage amplitude instruction K based on the voltage Vd of the DC trolley wire 1 and an effective value instruction E m * of output voltage which is proportional to the invertor output frequency instruction F inv *. The fundamental wave voltage amplitude instruction K and the fundamental sinusoidal wave are multiplied through a multiplier 513 to output an instantaneous fundamental wave voltage instruction e₀* as shown in Fig. 2(a). In a voltage instruction dividing means 52, the fundamental wave voltage instruction e₀* input from the fundamental wave voltage instruction generating means 51 is divided into 1/2 through a divider 521, and to this signal is added or from this signal is subtracted a bias amount B (this range is a condition for the dipolar modulation) that is set by a bias setting means 522 to be larger than K/2 but smaller than 0.5 through an adder 523 or a subtractor 524, thereby to form two divided voltage instructions e op * and e on * of a sinusoidal shape as shown in Fig. 2(a). From the thus divided voltage instructions e op * and e on *, a positive-side voltage instruction e p * shown in Fig. 2(b) is formed through polarity discrimination/distributors 526p, 526n and an adder 528p, and a negative-side voltage instruction e n * shown in Fig. 2(c) is formed through polarity discrimination/distributors 527p, 527n and an adder 528n. In a pulse generating means 53, a comparator means 532 compares the positive-side voltage instruction e p * and negative-side voltage instruction e n * input from the voltage instruction dividing means 52 with triangular waves such as those shown in Figs. 2(b) and 2(c) that are output from a carrier wave generating means 531, and outputs a pulse signal Gp such as the one shown in Fig. 2(d) and a pulse signal Gn such as the one shown in Fig. 2(g). The pulse signals G p and G n serve as gate signals for the switching elements G1 and G4, and the signals like those shown in Figs. 2(e) and 2(f) obtained by inverting the pulse signals G p and G n through inverters 533 and 534 serve as gate signals for the switching elements G3 and G2. Accordingly, as shown in Fig. 2(h), the invertor 3 alternatingly outputs, as output phase voltages, a positive pulse voltage of a height equal to the voltage V dp of the capacitor 22 and a negative pulse voltage of a height equal to the voltage V dn of the capacitor 23 via zero voltage. In the dipolar modulation of Fig. 2, when the bias amount B set by the bias setting means 522 becomes greater than the fundamental wave voltage amplitude instruction K/2, the divided voltage instructions e op * and e on * become as shown in Fig. 3(a), the negative-side voltage instruction e p * becomes as shown in Fig. 3(b), and the negative-side voltage instruction e n * becomes as shown in Fig. 3(c). As a result, the invertor 3 performs a so-called partial dipolar modulation outputting, as output phase voltages, pulse voltages as shown in Fig. 3(d) in which there exist a period of outputting positive and negative pulse voltages alternatingly via zero voltage and a period of outputting a pulse voltage of the same polarity as the fundamental wave. In the dipolar modulation of Fig. 2, when the bias amount B set by the bias setting means 522 becomes zero, the divided voltage instructions e op * and e on * become as shown in Fig. 4(a), the positive-side voltage instruction e p * becomes as shown in Fig. 4(b), and the negative-side voltage instruction e n * becomes as shown in Fig. 4(c). Referring to Figs. 3(b) and 3(c), the voltage instruction having the same polarity as the fundamental wave voltage instruction e₀* is distorted because of the reason that a voltage of the opposite polarity is output. As a result, the invertor 3 performs a so-called unipolar modulation which outputs a pulse voltage of the same polarity as the fundamental wave as shown in Fig. 4(d). In the unipolar modulation of Fig. 4, when the amplitude K of the fundamental wave voltage instruction e₀*, i.e., when the crest value K of the positive-side voltage instruction e p * and of the negative-side voltage instruction e n * becomes greater than a crest value (= 1) of the carrier triangular waves as shown in Figs. 5(a), 5(b) and 5(c), the invertor 3 outputs, as an output phase voltage, a pulse voltage which has the same polarity as the fundamental wave and in which the number of pulses is reduced during the half period of the fundamental wave as shown in Fig. 5(d). This is a so-called over-modulation. In the over-modulation of Fig. 5, when the amplitude K of the fundamental wave voltage instruction e₀*, i.e., when the crest value K of the positive-side voltage instruction e p * and of the negative-side voltage instruction e n * becomes further greater than the crest value (= 1) of the carrier triangular waves as shown in Figs. 6(a), 6(b) and 6(c), the invertor 3 produces a pulse voltage which has the same polarity as the fundamental wave and in which the number of pulses is one during the half period of the fundamental wave as shown in Fig. 6(d). This is a so-called one-pulse modulation. The aforementioned shifting of modulation system is carried out depending, for example, upon the amplitude K of the fundamental wave voltage instruction e₀*. Which modulation system will be used varies depending upon the application where the electric motor is used. In the case of the apparatus for controlling an electric car, however, it is desired that the power running and braking (regenerative) are controlled in the order mentioned above. Next, described below with reference to Fig. 7 in conjunction with the dipolar modulation system is an electric current hat flows into or out of the neutral point N in the case where the DC components of DC voltages V dp and V dn divided by the capacitors 22 and 23 are equilibrated. A positive-side voltage instruction e p * of Fig. 7(b) and a negative-side voltage instruction e n * of Fig. 7(c) obtained from the two divided voltage instructions e op * and e on * based on the fundamental wave voltage instruction e₀* of Fig. 7(a), are compared with a carrier triangular wave as described above, in order to obtain an invertor output phase voltage as shown in Fig. 7(d). In this case, if harmonic components are neglected, a current of a sinusoidal wave form without DC component as shown in Fig. 7(e) flows into the induction motor 4. Fig. 7(f) illustrates a switching function expressing, using 1 and 0, the condition of current flowing into or out of the neutral point N. Numeral 1 represents the condition where the current is flowing, which corresponds to a period in which the invertor output phase voltage of Fig. 7(d) is zero. Numeral 0 represents the condition where no current is flowing, which corresponds to a period in which the invertor output phase voltage of Fig. 7(d) is not zero. The switching function multiplied by the current of the motor 4 represents a current of one phase of the invertor 3 that flows into the neutral point N, as shown in Fig. 7(g) in which the current is equilibrated in the positive and negative cycles, and no DC component is included. Therefore, the DC components of DC voltages V dp and V dn divided by the capacitors 22 and 23 are equilibrated. However, when the capacitances of the capacitors 22 and 23 are not equilibrated or when DC components are introduced into the current that flows into or out of the neutral point N due to variation in the width of output pulses of the invertor 3 caused by the turn-on and turn-off operations of switching elements in the invertor 3, the DC components of DC voltages V dp and V dn divided by the capacitors 22 and 23 becomes out of equilibrium. As a result, an over-voltage is applied to the switching elements of the side of a higher DC voltage in the invertor 3; i.e., the switching elements may be damaged. Prior art for suppressing the imbalance of DC components between DC voltages V dp and V dn divided by the capacitors 22 and 23 have been disclosed in the aforementioned Japanese Patent Laid-Open No. 101969/1990 which deals with the dipolar modulation system and in the aforementioned literature 2 which deals with the unipolar modulation system. Described below are the case where the suppressing technology disclosed in the literature 2 is adapted to the dipolar modulation system and the case where the suppressing technology disclosed in Japanese Patent Laid-Open No. 101969/1990 is adapted to the unipolar modulation system. The suppressing technology disclosed in the literature 2 is a system which applies to the invertor output voltage instruction a signal that corresponds to a DC component of the differential voltage between DC voltages V dp and V dn divided by the capacitors 22 and 23. When this suppressing technology is adapted to the aforementioned dipolar modulation system (imbalance V dp < V dn is taking place in Fig. 7) to add to the fundamental wave voltage instruction e₀* a signal ΔV that corresponds to a DC component of a differential voltage (V dp - V dn ) between the DC voltages V dp and V dn, then the divided voltage instructions e op *, e on *, the positive-side voltage instruction e p * and the negative-side voltage instruction e n * undergo changes from Figs. 7(a) to 7(c) into Figs. 8(a) to 8(c). As a result, the invertor output phase voltage becomes as shown in Fig. 8(d). In this case the DC component included in the invertor output phase voltage is offset by a voltage across the output lines (e.g., across U-V) of the invertor 3 and does not appear. The DC component is not included in the current to the motor 4, either. Moreover, the switching function which expresses the condition of current flow at the neutral point N becomes as shown in Fig. 8(f). From the standpoint of positive and negative cycles of the fundamental wave voltage instruction e₀*, however, the currents are balanced during a period in which the switching function is 1. Therefore, the current at the neutral point N obtained by multiplying the switching function by the current of the motor 4 of Fig. 8(e) is balanced in the positive and negative cycles as shown in Fig. 8(g), and no DC component is included. Therefore, the DC components of DC voltages V dp and V dn remain imbalanced. That is, no suppressing effect is obtained even when the suppressing technology disclosed in the literature 2 is adapted to the dipolar modulation system. The suppressing technology disclosed in Japanese Patent Laid-Open No. 101969/1990 is a system which adjusts the amplitudes of the two modulated waves of a sinusoidal wave form and the shifting amount (bias amount) depending upon the DC component of the differential voltage between the DC voltages V dp and V dn divided by the capacitors 22 and 23. Even when this suppressing technology is adapted to the unipolar modulation system to adjust the amplitudes of the divided voltage instructions e op * and e on * as shown in Fig. 9(a) based on a signal ΔV which corresponds to the DC component of the differential voltage (V dp - V dn ) between the DC voltages V dp and V dn , the positive-side voltage instruction e p * and the negative-side voltage instruction e n * do not, after all, change since they are added up in the unipolar modulation. Therefore, equilibrium is maintained as shown in Figs. 9(b) and 9(c). In the unipolar modulation system, therefore, the suppressing technology disclosed in Japanese Patent Laid-Open No. 101969/1990 does not work to suppress the imbalance of the DC components of DC voltages V dp and V dn . In order to suppress the imbalance (e.g., V dp < V dn ) between the DC voltages V dp and V dn divided by the capacitors 22 and 23 according to the embodiment of Fig. 1, therefore, the polarity of the fundamental sinusoidal wave output by a sinusoidal wave (sin) generating means 511 is discriminated, distributed and output as 1 and 0 by polarity discrimination/distributors 542p and 542n in the voltage imbalance suppressing means 54 of the modulation means 5. These outputs and the signal ΔV (the signal here has a negative sign since V dp < V dn ) which corresponds to the DC component of the differential voltage (V dn - V dn ) between the DC voltages V dp and V dn output by a differential voltage detecting means 541, are multiplied together through multipliers 543p and 543n, and the signal ΔV is output being divided into ΔV p and ΔV n as shown in Fig. 10(b). The divided signals ΔV p and ΔV n are added to the divided voltage instructions e op * and e on * of Fig 10(a), respectively, to obtain a positive-side voltage instruction e p * shown in Fig. 10(c) and a negative-side voltage instruction e n * shown in Fig. 10(d). As a result the invertor output phase voltage becomes as shown in Fig. 10(e). That is, the positive output pulse of the invertor decreases having the same polarity as the fundamental wave voltage instruction e₀* and the negative output pulse of the invertor increases having the same polarity as the fundamental wave voltage instruction e₀*. At this moment, the neutral point period of the positive side increases and the neutral point period of the negative side decreases, and whereby the switching function which expresses the condition of current flow at the neutral point N becomes as shown in Fig. 10(g). That is, in the period corresponding to the switching function of 1, imbalance occurs from the standpoint of positive and negative cycles of the fundamental wave voltage instruction e₀*. Therefore, the current at the neutral point N including the current of the motor 4 of Fig. 10(f) superposed on the switching function becomes out of balance between the positive cycle and the negative cycle as shown in Fig. 10(h) and includes a positive DC component as indicated by a broken line. The positive DC component works to electrically charge the capacitor 22, to electrically discharge the capacitor 23, to increase the DC voltage V dp , to decrease the DC voltage V dn , and hence to suppress the imbalance (V dp < V dn ) of DC components between the DC voltages V dp and V dn . Moreover, the DC component included in the invertor output phase voltage is canceled by the voltage across the output lines (e.g., across U-V) and does not appear. The DC component is not included in the current of the motor 4, either. Fig. 10 shows the case of a power mode. In the case of a regenerative mode, the current of the motor 4 has an opposite polarity to that of Fig. 10(f). Therefore, the DC component included in the current at the neutral point N has an opposite polarity to the broken line of Fig. 10(h). Therefore, the signals ΔV p and ΔV n divided from the signal ΔV that corresponds to the DC component of the differential voltage (V dp - V dn ) between the DC voltages V dp and V dn , must be so switched as to have a polarity opposite to that of Fig. 10(b). As described above, this embodiment makes it possible to easily and effectively suppress the imbalance of DC components between the DC voltages V dp and V dn in the dipolar modulation system. According to a modified embodiment adapted to the dipolar modulation system, the same suppressing effect is obtained by subtracting ΔV p from the voltage instruction e on * and subtracting ΔV n from the voltage instruction e op * as shown in Fig. 11 in order to adjust the width of the output pulse of the invertor of an opposite polarity to the fundamental wave voltage instruction e₀* (the pulse width of the negative side is narrowed when the fundamental wave voltage instruction e₀* is positive and, on the other hand, the pulse width of the positive side is broadened when it is negative), instead of adjusting the width of the invertor output pulse having the same polarity as the fundamental wave voltage instruction e₀* by adding ΔV p to the voltage instruction e op * and adding ΔV n to the voltage instruction e on * as shown in Fig, 10. In Figs. 10 and 11, furthermore, the same suppressing effect is obtained even when the pulse width of one side only is put into action, i.e., even when ΔV p only is put into action or even when ΔV n only is put into action. Next, when shifted into the unipolar modulation system while setting the bias amount B to 0, the divided voltage instructions e op * and e on * become as shown in Fig. 12(a). Furthermore, a positive-side voltage instruction e p * and a negative-side voltage instruction e n * obtained by adding ΔV p and ΔV n of Fig. 12(b) to the above voltage instructions become as represented by thick lines in Figs. 12(c) and 12(d). Accordingly, the output phase voltage of the invertor becomes as shown in Fig. 12(e). In this case, the DC component included in the invertor output phase voltage is canceled by the voltage across the output lines (e.g., across U-V) of the invertor 3 and does not appear. Therefore, no DC component is included in the current of the motor 4, either. Moreover, the switching function that expresses the condition of current flow at the neutral point N becomes as shown in Fig. 12(g), and in the period corresponding to the switching function of 1, imbalance occurs from the standpoint of positive and negative cycles of the fundamental wave voltage instruction e₀*. Therefore, the current at the neutral point N obtained by multiplying the switching function by the current of the motor 4 of Fig. 12(f) becomes out of balance in the positive and negative cycles is shown in Fig. 12(h) and includes a positive DC component as indicated by a broken line. The positive DC component works to electrically charge the capacitor 22, to electrically discharge the capacitor 23, to increase the DC voltage V dp , to decrease the DC voltage V dn , and to suppress the imbalance (V dp < V dn ) of DC components between the DC voltages V dp and V dn . It can be further understood that the imbalance of DC components between the DC voltages V dp and V dn can be suppressed in the same manner even in the partial dipolar modulation system of Fig. 3, in the over-modulation system of Fig. 5, and in the one-pulse modulation system of Fig. 6. As described above, the embodiment of the invention improves the system for suppressing the imbalance of DC components between the DC voltages V dp and V dn in the dipolar modulation system, and can readily be adapted to other modulation systems than the dipolar modulation system. In an apparatus for controlling an electric car to which are adapted the dipolar modulation system and another modulation system, furthermore, the embodiment of the invention makes it possible to carry out the operation for suppressing the imbalance of DC components between the DC voltages V dp and V dn commonly in all of the modulation systems, contributing to simplifying the suppress control. According to this embodiment, it needs not be pointed out that the aforementioned suppressing effect is obtained even when the signal ΔV that corresponds to the DC component of a differential voltage between the DC voltages V dp and V dn output by the differential voltage detecting means 541 in the voltage imbalance suppressing means 54 in the modulation means 5 is output being divided into ΔV p and ΔV n of a half-wave sinusoidal shape as shown in Fig. 13 instead of being divided into ΔV p and ΔV n of a square wave form of Fig. 10(b). For this purpose, the polarity discrimination/distributors 542p and 542n in the voltage balancing means 54 of the embodiment of Fig. 1 should be changed into those like polarity discrimination/distributors 526p and 527p in the voltage instruction dividing means 52. The present invention can, as a matter of course, be adapted even to a dipolar modulation system different from the dipolar modulation system described in conjunction with Fig. 2. That is, the invention can be adapted even to a dipolar modulation system which forms two divided voltage instructions e op * and e on * of a half-wave sinusoidal shape as shown in Fig. 14(a), forms a positive-side voltage instruction e p * of Fig. 14(b) and a negative-side voltage instruction e n * of Fig. 14(c) from the voltage instructions e op * and e on *, and alternatingly generates positive and negative output pulses of the invertor via zero voltage as shown in Fig. 14(d) while maintaining constant the width of the output pulses that have a polarity opposite to the fundamental wave of the invertor output phase voltage. In the three-level invertor to which are adapted the dipolar modulation system and another modulation system, furthermore, it needs not be pointed out that there may be provided a means which switches the system for suppressing the imbalance of DC components between the DC voltages V dp and V dn depending upon the modulation systems (e.g., technology disclosed in Japanese Patent Laid-Open No. 101969/1990 as for the dipolar modulation system, and technology disclosed in the literature 2 as for the unipolar modulation system). Fig. 15 shows an another embodiment of the present invention and is the same construction as that in Fig. 1 except the unbalance voltage suppressing means 54 in the modulating means 5. In the embodiment shown in Fig. 1, the unbalance voltage between the capacitors is mainly suppressed in powering of the induction motor 4. On the contrary in the embodiment shown in Fig. 15, the unbalance voltage between the capacitors may be suppressed not only in powering but in braking of the induction motor 4. A polarity selecting means 544 and a multiplier 545 are added to the unbalance voltage suppressing means 54 as shown in Fig .15, and the polarities of the voltages ΔVp and ΔVn are changed. That is, the polarity selecting means 544 outputs a signal "1" when driving the motor 4 in powering and outputs a signal "-1" when driving it in braking on the basis of powering/braking order from an operator. The multiplier 545 inverts the polarity of the voltages ΔVp and ΔVn in powering and braking by reversing the output of the fundamental wave generating means depending on the output of the polarity selecting means 511. Furthermore, in stead of said powering/braking order from the operator, a polarity of an electric power obtained from output voltage and output current, or a DC voltage and a DC current may be used. In this embodiment shown in Fig. 15, the unbalance voltage is always suppressed in both of powering and braking of the motor 4. The present invention makes it possible to easy and effectively suppress the imbalance of DC components between the two DC voltages in the dipolar modulation system. In an apparatus for controlling an electric car to which are adapted the dipolar modulation system and another modulation system, furthermore, it is allowed to simplify the operation for suppressing the imbalance of DC components between the two DC voltages.

Claims: A power converter comprising capacitors (22, 23) connected in series so as to divide a DC voltage (V d ); a DC/AC converter (3) for converting said DC voltage charged on said capacitors into an AC phase voltage having positive, zero and negative levels which is supplied to a load (4); and modulation means (5) for supplying said DC/AC converter (3) with a signal so as to generate a sequence of alternating output pulses with interleaving zero-level pulses in each half cycle of the fundamental wave of the output phase voltage of the DC/AC converter; characterized by means (54) for adjusting the width of only either one of the positive and negative output pulses in the half cycle of the fundamental wave of said output phase voltage depending upon the DC component of the difference between the voltages (V dp , V dn ) on said capacitors (22, 23). The power converter of claim 1, wherein the width of only the output pulses having the same polarity as the fundamental wave of said output phase voltage is adjusted depending upon the DC component of the difference between the voltages on said capacitors. The power converter of claim 1, wherein the width of only the output pulses having a polarity opposite to the fundamental wave of said output phase voltage is adjusted depending upon the DC component of the difference between the voltages on said capacitors. The power converter of any one of claims 1 to 3, wherein the width adjusting means (54) is adjusted according to a powering or a braking state of the load (4). The power converter of any one of claims 1 to 3, wherein the width adjusting means (54) adjusts the width of said output pulses corresponding to the positive and/or negative polarities of the fundamental wave of said output phase voltage. The power converter of any one of claims 1 to 3, wherein the width adjusting means (54) is provided in said modulation means (5). The power converter of claim 6, wherein said modulation means (5) divides a fundamental wave voltage instruction formed on the basis of an amplitude instruction of a voltage and frequency instruction output to the DC/AC converter into a positive-side voltage instruction for generating negative output pulses, and then forms a signal based on these voltage instruction to turn on or off the switching elements (G1U...G4W) that constitute said DC/AC converter (3), distributes the signal corresponding to the DC components of the difference between the voltages on said capacitors (22, 23) depending upon the polarity of said fundamental wave voltage instruction, and superposes said distributed signal on said positive-side voltage instruction or on said negative-side voltage instruction. The power converter of claim 7, wherein said distributed signals are distributed depending on said polarity and either a powering or a braking state of the load (4). The power converter of claim 7, wherein said distributed signals having the same or opposite polarity as the voltage instructions are superposed on said positive-side voltage instruction or on said negative-side voltage instruction. An apparatus for controlling an electric car comprising the power converter of any one of claims 1 to 9, wherein an AC motor (4) is driven by said DC/AC converter (3); said modulation means (5) has a first modulation mode in which said DC/AC converter (3) is supplied with the signal for generating the sequence of alternating output pulses with interleaving zero-level pulses in response to a voltage instruction and a frequency instruction fed to said DC/AC converter, the sequence of pulses corresponding to half the cycle of the fundamental wave of the output phase voltage of the DC/AC converter, and a second modulation mode in which said DC/AC converter is supplied with a signal for generating a sequence of output pulses different from the sequence of output pulses of said first modulation mode; and wherein said adjusting means (54) adjusts the width of only either one of the positive and negative output pulses in the half cycle of the fundamental wave of said output phase voltage depending upon the imbalance of the DC components between said divided DC voltages in said first modulation mode and in said second modulation mode. The apparatus of claim 10, wherein said second modulation mode includes at least one of the following modes: a partial dipolar modulation mode in which a phase voltage of said DC/AC converter includes a sequence of alternating output pulses with interleaving zero-level pulses and a series of pulses having the same polarity as the fundamental wave of said output phase voltage in each half cycle of the fundamental wave of said output phase voltage; an unipolar modulation mode in which a phase voltage of said DC/AC converter includes a sequence of output pulses of the same polarity as the fundamental wave of said output phase voltage, and a plurality of output pulses are output in a half cycle of the fundamental wave of said output phase voltage; an over-modulation mode in which the number of output pulses having the same polarity as the fundamental wave of said output phase voltage and included in the half cycle of the fundamental wave of said output phase voltage is smaller than the number of said output pulses included in the half cycle of the fundamental wave of said output phase voltage in said unipolar modulation mode; and an one-pulse modulation mode in which as a phase voltage of said DC/AC converter, a sequence of output pulses from said DC/AC converter has the same polarity as the fundamental wave of said output phase voltage, and only one output pulse is outputted in each half period of said output phase voltage. The apparatus of claim 10, wherein said modulation means (5) includes means (52) which divides a fundamental wave voltage and a frequency instruction output to said DC/AC converter (3) into a positive-side voltage instruction for generating negative output pulses from said DC/AC converter; means (522) that gives a bias which changes these voltage instructions; means (53) that forms a signal based on these voltage instructions to turn on or off the switching elements (G1U...G4W) that constitute said DC/AC converter; and means (54) that distributes the signals corresponding to the DC components of the difference between said divided DC voltages depending upon the polarity of said fundamental wave voltage instruction and superposes the output of said distribution means on said divided positive-side and negative-side voltage instructions.

Inventors: NAKAMURA KIYOSHI, NAKATA KIYOSHI, TANAMACHI TOKUNOSUKE, NAKAMURA, KIYOSHI, NAKATA, KIYOSHI, TANAMACHI, TOKUNOSUKE
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1993
Main classification: H02M7
IPC codes: H02P27, B60L9, H02M7