USING D-C FEEDBACK WITH ON-CHIP FILTERING TO BALANCE I-F DRIVE TO SECOND DETECTOR IN MONOLITHIC IC

Abstract: A surface-acoustical-wave (SAW) or other lumped intermediate-frequency amplifier filter is followed by an IF amplifier chain and a second detector constructed within the confines of a monolithic integrated circuit. The IF amplifier chain includes three emitter-coupled differential amplifiers, each exhibiting up to about twentyfold voltage gain, cascaded one after the other. Provision is made for automatically controlling the voltage gain of the first two emitter-coupled differential amplifiers. Common-collector amplifiers are used to buffer the application of the balanced output signals from each of the emitter-coupled differential amplifiers to the succeeding emitter-coupled differential amplifier or second detector (DET). Balanced current responses to the direct bias potentials on which the balanced signals supplied to the second detector are respectively superposed, are extracted by lowpass filtering (LPF) that is on-chip and does not use off-chip IF bypass capacitors. These balanced current responses are fed back to the emitters of the transistors in the common-collector amplifiers (Q68, Q69) used to couple the first gain-controlled emitter-coupled differential amplifier in the IF amplifier chain to the second gain-controlled emitter-coupled differential amplifier in the IF amplifier chain. This completes a direct-coupled feedback loop for degenerating the differences between the direct bias potentials on which the balanced signals supplied to the second detector are respectively superposed.

Description: USING D-C FEEDBACK WITH ON-CHIP FILTERING TO BALANCE I-F DRIVE TO SECOND DETECTOR IN MONOLITHIC IC The invention relates to intermediate-frequency (IF) amplification and, more particularly, to inter ediate- frequency amplifier and second detector combinations as constructed in monolithic-integrated-circuit form. Background of the Invention Television receivers commonly use a type of monolithic integrated-circuit, or IC, which is constructed using bipolar transistors; is designed to follow a surface- acoustical-wave (SAW) or other lumped "block" intermediate- frequency amplifier filter; and comprises a cascade connection of three emitter-coupled differential amplifiers, each exhibiting up to about twentyfold voltage gain, followed by a second detector. Untuned, direct interstage coupling is provided by common-collector- amplifier (or emitter-follower) transistors. Provision is commonly made for automatically controlling the voltage gain of the emitter-coupled differential amplifiers. The second detector may be an envelope detector, but in recent years is more often a synchronous detector or a quasi- synchronous detector of the exalted-carrier type. In double-conversion receivers or in an IF amplifier dedicated to generating intercarrier sound, the second detector may be a second mixer for converting a first intermediate frequency to a second intermediate frequency. U.S. patent application serial No. 07/940,220 filed 8 September 1992 by Jack Rudolph Harford and Heung Bae Lee, entitled VARIABLE GAIN AMPLIFIER, describes IF amplifier circuitry modified by the inventor in making embodiments of the invention claimed hereinafter. As is the case in the present application, U. S. patent application serial No. 07/940,220 has been assigned to Samsung Electronics co., Ltd., pursuant to obligations of the inventor(s) to assign his (their) invention(s) at the time the inventions were made. The IF amplifier circuitry described by Harford and Lee meets the automatic gain control range requirements of about 66 dB for a television receiver IF amplifier chain to be met by controlling the voltage gains of first and second emitter-coupled differential amplifiers therein, and a third emitter-coupled differential amplifier therein can be operated with a fixed voltage gain. Commonly, second detectors are designed to be driven with balanced signals from the IF amplifier chain. Then, the desideratum is for reasonably good matching, at least to within 20 millivolts or so, of the direct bias potentials on which the balanced signals supplied to the second detector are superposed. In previous designs respective low-pass filters, each filter using an off-chip capacitor, extract the direct bias potentials on which these balanced signals supplied to the second detector are superposed. The responses of these low-pass filters are then differentially combined to develop an error signal fed back to the input of the IF amplifier chain, thereby to complete a direct-coupled (d-c) feedback loop for degenerating the error signal. This approach has been found to be disadvantageous. Bringing the fully amplified IF signals off-chip, even to bypass capacitors, increases the risk of undesirable regeneration in the IF amplifier chain. The high voltage gain of the full IF chain under weak- signal conditions and the changes in phase margin that may occur in different portions of the AGC range cause problems of dc feedback loop stabilization. The reliability of interfaces between the IC and its external environment tends to , be lower than the reliability of the electronic circuitry interfaced between. The number of pins required on the IC package affects its cost, and additional pins are often needed for the off-chip capacitors used in the low- pass filters. The off-chip capacitors have to be separately inventoried from the IC during television receiver production. Summary of the Invention The invention is embodied in a surface-acoustical-wave (SAW) or other lumped intermediate-frequency amplifier filter followed by an IF amplifier chain and a second detector constructed within the confines of a monolithic integrated circuit. The IF amplifier chain includes three emitter-coupled differential amplifiers, each exhibiting up to about twentyfold voltage gain, cascaded one after the other. Provision is made for automatically controlling the voltage gain of the first two emitter-coupled differential amplifiers. Common-collector amplifiers are used to buffer the application of the balanced output signals from each of the emitter-coupled differential amplifiers to the succeeding emitter-coupled differential amplifier or second detector. Balanced current responses to the direct bias potentials on which the balanced signals supplied to the second detector are respectively superposed, are extracted by lowpass filtering that is on-chip and does not use off- chip IF bypass capacitors. These balanced current responses are fed back to the emitters of the transistors in the common-collector amplifiers used to couple the first gain- controlled emitter-coupled differential amplifier in the IF amplifier chain to the second gain-controlled emitter— coupled differential amplifier in the IF amplifier chain. This completes a direct-coupled feedback loop for degenerating the differences between the direct bias potentials on which the balanced signals supplied to the second detector are respectively superposed. Brief Description of the Drawing FIGURE 1 is a schematic diagram of a gain-controlled amplifier stage that is particularly well-suited for use as the first stage of a plural-stage IF amplifier and is also disclosed by the inventor and another in U. S. patent application serial No. 07/940,220 filed 8 September 1992. FIGURE 2 is a schematic diagram of a gain-controlled amplifier stage that is particularly well-suited for use as the second stage of a plural-stage IF amplifier and is also disclosed by the inventor and another in U.S. patent application serial No. 07/940,220 filed 8 September 1992. FIGURE 3 is a schematic diagram of a cascade connection of the gain-controlled amplifier stages of FIGURES I and 2, which is also disclosed by the inventor and another in U. S. patent application serial No. 07/940,220 filed 8 September 1992. FIGURE 4 is a schematic diagram of another gain- controlled amplifier stage that is particularly well-suited for use as the input stage of a plural-stage IF amplifier and is also disclosed by the inventor and another in U. S. patent application serial No. 07/940,220 filed 8 September 1992. FIGURE 5 is a schematic diagram of a cascade connection of the gain-controlled amplifier stages of FIGURES 4 and 2, which is also disclosed by the inventor and another in U. S. patent application serial No. 07/940,220 filed 8 September 1992. FIGURE 6 is a schematic diagram of a third amplifier stage for further cascade connection after the FIGURE 3 or 5 cascade connection of gain-controlled amplifier stages, thereby completing a three-stage IF amplifier; a second detector for accepting balanced amplified IF signals superposed on respective direct bias potentials that ideally are equal to each other; and an on-chip filter for developing a balanced error current signal differentially responsive to those respective direct bias potentials, which balanced error current signal is fed back to the balanced input of the second gain-controlled amplifier stage per FIGURE 2 in the FIGURE 3 or 5 cascade connection of gain-controlled amplifier stages, in accordance with the invention. FIGURE 7 is a schematic diagram of a modification that can be made to the FIGURE I gain-controlled amplifier stage, which is also disclosed by the inventor and another in U.S. patent application serial No. 07/940,220 filed 8 September 1992. FIGURE 8 is a schematic diagram of a modification that can be made to the FIGURE 4 gain-controlled amplifier stage, which is also disclosed by the inventor and another in U.S. patent application serial No. 07/940,220 filed 8 September 1992. FIGURE 9 is a block schematic diagram of those portions of a television receiver or video tape recorder used for recovering audio-signal, video-signal and synchronizing-signal portions of a transmitted television signal, which television receiver uses intermediate- frequency amplifiers of the type shown in FIGURES 3 and 6 or in FIGURES 5 and 6. Detailed Description Within this specification the term "RF signal" shall be used in reference to signals at points in a television receiver before the down-conversion, or first detection; and the term "IF signal" shall be used in reference to signals at points in a television receiver after the down- conversion, or first detection, and before video detection, or second detection. In television receivers a down- conversion is carried out by heterodyning the incoming radio-frequency (RF) signals of different transmission channels with the oscillations of a tunable-frequency oscillator, thereby to generate lower-infrequency radio- frequency signals within an intermediate-frequency (IF) band which is selected and amplified in an intermediate- frequency (IF) amplifier. An intermediate-frequency amplifier for the video portion of a television signal is commonly termed the "PIX IF amplifier". An intermediate- frequency amplifier for the sound portion of a television signal may be completely separate from the PIX IF amplifier. Or, alternatively, a portion of the intermediate-frequency amplification for the sound portion of a television signal may be done by the PIX IF amplifier, as is the case in most TV sets of the inter sound type. A PIX IF amplifier is typically required to handle signals ranging from about 50 microvolts to about 100 millivolts RMS. This represents a dynamic range of about 66 dB. In providing an automatic gain control (AGC) function, it is desirable that certain operating conditions be met for each amplifier stage or device. Thus, the input signal level should exceed the internal noise by a predetermined factor, and the input signal level should not overload the device and thereby cause signal distortion and a bias shift. Furthermore, the AGC control signal should not itself cause undesirable bias shifts and thereby cause devices to be shifted from their intended operating points. E. g., the operating points for amplifiers and mixers are chosen to provide for low distortion in their output signals, and the operating points for mixers and detectors are chosen to provide for relatively high second-order responses. At relatively strong signal levels in the order of I millivolt or more, it is particularly important that the gain be controlled in a manner that takes into account the so-called "noise/overload window". If, on the one hand, the gain of an earlier stage of a multiple-stage amplifier is reduced too little, overload with distortion undesirably may occur in a later stage. If, on the other hand, if the gain in an earlier stage is too low, thermal noise may become noticeable. It is desirable that a substantially noise-free and undistorted picture be achievable for an input signal level corresponding to 10 millivolts or so, measured at typical impedance levels. If an amplifier exhibits an inadequate noise/overload window, it may contribute noise or overload distortion at signal levels where a low distortion, relatively noise-free picture should be possible. The development of integrated-circuit (IC) gain blocks led to the use block filtering. Recent practice has been to implement the IF filtering and gain functions in TV receivers as a gain-block IC amplifier without interstage tuning, which gain-block IC is cascaded after a block filter. A surface-acoustic-wave (SAW) , filter can provide the entire passband shape and adjacent channel attenuation required by a television receiver. Additional information on SAW filters and on block filtering and amplification may be found, for example, in Chapter 13 of the book TELEVISION ENGINEERING HANDBOOK; K. Blair Benson, Editor in Chief; McGraw-Hill Book Company, New York; 1986. While the advent of block filtering and amplification has been generally desirable in the TV receiver art, it aggravates the problem of the noise/overload window for a number of reasons. The typical SAW filter commercially available for use as a lumped filter at the input of an IF amplifier, exhibits high insertion loss and high impedance, thereby acting as a relatively high level noise source impedance. The noise margin side of the noise/overload window is accordingly reduced. Furthermore, noise signals falling within +/- 4.5 MHz of the picture carrier will be demodulated as noise that is "folded" into the 0 - 4.5 MHz video band. This arises as follows. The IF signal lies within the band of 41.25 - 45.75 MHz. With the use of lumped or block filtering at the input of an IF amplifier, the sideband noise of IF stages following the filter is not suppressed as was the case when filtering was distributed stage by stage. This is because the noise within the band of +/- 4.5 MHz centered about the (IF) picture carrier frequency of 45.75 MHz is not filtered by the lumped filter ahead of the amplifier. Another effect which tends to aggravate the noise/overload window problem in the block filtering and amplification procedure is that the typical bipolar IC amplifier utilized exhibits a transfer characteristic having a fixed overload voltage level, which restricts the overload side of the noise/overload window. Furthermore, typical modern small geometry bipolar transistors tend to exhibit a high base access resistance (rb) and hence tend to have a worse noise figure than larger, optimized devices having low rb; this aggravates the problem. The noise/overload window can be extended on the overload side by utilizing transistors of different design and, on the noise side by transforming the SAW filter output impedance to a lower value, thereby reducing its contribution as a noise source. However, impedance matching arrangements such as transformers or other matching circuits are costly, bulky, and raise the gain requirements on a system that already has high gain. The problem of the noise/overload window is further complicated by the fact that each of certain prior-art gain-controlled IF amplifiers exhibits a shift of its output bias voltage as a function of gain control. Generally, this results in a change of bias voltage on the demodulator, which is typically direct-coupled to the IF amplifier. As was mentioned above with regard to operating points, such change is undesirable. As a result of the shifting bias conditions, adequate bias voltage must be provided to accommodate the changes, thereby complicating the demodulator design and necessitating a higher supply voltage than is otherwise required for low distortion. A basic amplifier stage that is often used in IF amplifiers is the long-tailed pair or emitter-coupled differential amplifier, which includes two transistors with a "tail" connection between their emitter electrodes to which a constant current generator connects. The constant current generator may be provided by a high-resistance resistor between the tail connection and a remote direct potential; but in ICs, where there is a desire to use smaller operating potentials in order to keep dissipation within acceptable bounds, the constant current generator is generally provided by the principal conduction path of another transistor biased for constant current operation. While the long-tailed pair is oftentimes referred to as an emitter-coupled "differential" amplifier, in fact, it is often operated with a single-ended input circuit, a single- ended output circuit, or both. Gain control may be effected by the straight-forward reduction of the operating or tail current of an emitter-coupled differential amplifier, thereby reducing §itε mutual conduction in a known manner. However, there are drawbacks to the simple application of this approach. First, the noise source resistance is increased as gain decreases, thereby negating to an extent the improved signal-to-noise ratio associated with a larger signal and second, the power handing capability is reduced when it is most needed to handle a larger signal. Prior-art untuned amplifiers, constructed in IC form and used after block filtering for television-receiver IF amplification in commercially successful TV receiver designs, have used three successive gain-controlled stages in order to meet the dynamic range requirements of about 66 dB for such service. These designs have used reverse AGC, in which the transconductances of the amplifier transistors are reduced in order to effect gain reduction. The voltage gain of an undegenerated common-emitter transistor amplifier is gmRL, where gm is the transconductance of the transistor and RL is the resistance of the collector load used with the transistor. The reduction of the transconductances of the amplifier transistors raises the resistances of the noise sources presented to their collector electrodes, increasing thermal noise generated by the transistors and thus making it necessary to use three successive gain-controlled stages in order to keep the overall noise figure for the PIX IF amplifier chain low enough to meet commercial requirements. An alternative approach for reducing the gains of cascaded amplifier stages is to reduce the collector resistances used with the transistors, the well-known forward AGC being an example of this approach. If the transconductances of the transistors are not reduced, there is no attendant increase in thermal noise generated by the transistors, and reducing the collector resistances used with the transistors reduces the voltages associated with the currents generated by their thermal noise. In U.S. patent application serial No. 07/940,220 J. R. Harford and H. B. Lee describe arrangements to reduce the collector resistances used with emitter-coupled differential-amplifier transistors by shunting those collector resistances with devices having electrically controlled conductances. Each of the gain-controlled IF amplifiers J. R. Harford and H. B. Lee describe exhibits very little shift of its output bias voltage as a function of gain control. Three-stage IF amplifiers using these gain-controlled IF amplifiers in their first and second voltage-gain stages are suitable for use with direct- coupled DC feedback loops that reduce the difference between the direct bias potentials on which the balanced IF output signals are superposed, doing so in accordance with the principles of the invention herein described and claimed. Since these gain-controlled IF amplifiers exhibit very little shift of their output bias voltages as a function of gain control, the direct-coupled DC feedback loops that reduce the difference between the direct bias potentials on which the balanced IF output signals are superposed can be differential-mode in nature and need not correct the common-mode values of these direct bias potentials. Since the third voltage-gain stage has a fixed voltage gain of twentyfold or so, even when the gain of the second voltage-gain stage is reduced by AGC, sufficient differential-mode feedback loop gain is available to suppress adequately the difference between the direct bias potentials on which the balanced IF output signals are superposed, even though the differential-mode feedback loop does not include the first gain-controlled IF amplifier therewithin. As the gain of the second voltage-gain stage is reduced by AGC before the gain of the first voltage-gain stage is reduced by delayed AGC, there is a reduction in similar degree of the difference between the direct bias potentials on which the balanced IF output signals are superposed, inasfar as that difference is attributable to imbalance in the first gain-controlled IF amplifier. Furthermore, the difference between the direct bias potentials on which the balanced IF output signals are superposed that is attributable to imbalance in the second gain-controlled IF amplifier is likely to be reduced as well. As the gain of the first voltage-gain stage is reduced by delayed AGC, the difference between the direct bias potentials on which the balanced IF output signals are superposed that is attributable to imbalance in the first gain-controlled IF amplifier is likely to be further reduced. So, modest further reduction of the gain in the second gain-controlled IF amplifier during the application of delayed AGC to the first gain-controlled IF amplifier can be tolerated, inasfar as keeping the difference between the direct bias potentials on which the balanced IF output signals are superposed within acceptable limit. Including, within their respective differential-mode feedback loops for correcting direct potential imbalances in their amplified IF signals, only the second gain- controlled IF amplifiers of each of the IF amplifier chains AGC'd in parallel tends to facilitate tracking of the respective gains of these IF amplifier chains. There is no AGC delay break in the gain control characteristic of the amplifiers within either of the feedback loops, to have to take into account in determining loop behavior. Referring to FIGURE 1 , Ql is a bipolar transistor, having a base electrode for controlling conduction through a principal conduction path between emitter and collector electrodes, as is also the case with other bipolar transistors to be hereinafter referred to in the description. An NPN transistor Ql has its base and collector electrodes conductively joined so as to operate in a diode-connected mode. The emitter electrode of Ql connects to a source of a reference potential, here shown as ground. A reference current is supplied to the joined base and collector electrodes via a resistance Rl having one end thereof connected to those joined electrodes and having another end thereof connected to receive a automatic-gain-control (AGC) signal potential applied at a terminal TI. FIGURE 1 shows the AGC signal potential originating from a generator GC1 being applied at a terminal TI. NPN transistors Q2 and Q3 have their respective emitter electrodes connected to the same reference potential as the emitter electrode of Ql and their base electrodes connected to the base electrode of Ql, so as to form a current mirror arrangement with respect to the reference current supplied via Rl. The emitter electrodes of NPN transistors Q4 and Q5 are each connected to one end of respective resistances R5 and R6 whose other ends are connected together and are connected to a point at ground reference potential via a resistance R7, so that transistors Q4 and Q5 form a differential pair, with resistance R7 supplying operating current or tail current to the differential pair The base electrodes of NPN transistors Q6 and Q7 are connected to respective signal input terminals T5 and T6 for receiving a differential input signal and accompanying direct bias potential thereat. Figure I shows a battery BI with its negative terminal connected to a point of ground reference potential supplying a positive direct bias potential V at its positive terminal against which are referred balanced input signals supplied by generators SI and S2 to the base electrodes of Q6 and Q7. Transistors Q6 and Q7 are connected as common-collector amplifiers to provide voltage followers of the emitter-follower type. Their respective emitter electrodes connect to respective ones of the base electrodes of Q4 and Q5 and to one end of respective resistances R2 and R3. The other ends of R2 and R3 are connected together and to one end of a resistance R4 whose other end is connected to ground. Transistors Q6 and Q7 have their collector electrodes connected to receive a positive operating potential VB2 applied to a supply terminal T2, shown in FIGURE I as being supplied from the positive terminal of a battery B2 having its negative terminal connected to a point at reference ground potential. The collector electrodes of Q4 and Q5 are connected to supply terminal T2 via respective collector load resistances R8 and R9. The collector electrode of Q4 is further connected to the base electrode of an NPN transistor Q8, the collector electrode of which connects to T2. The emitter electrode of Q8 is connected to an output terminal T3, and a current source IS1 drains current therefrom to a point of ground reference potential. The collector electrode of transistor Q5 is further connected to the base electrode of an NPN transistor Q9, the collector electrode of which connects to T2. The emitter electrode of Q9 is connected to an output terminal T4, and a current source IS2 drains current therefrom to a point of ground reference potential. Q8 and Q9 function as voltage followers of emitter-follower type for the balanced output voltages developed by the FIGURE I controlled-gain amplifier. The collector electrode of transistor Q4 is further connected to the joined collector and base electrodes of an NPN transistor Q10 and to the emitter electrode of an NPN transistor Qll. The collector electrode of transistor Q5 is further connected to the joined collector and base electrodes of an NPN transistor Q12 and to the emitter electrode of an NPN transistor Q13. The joined emitter electrodes of transistors Q10 and Q12 are connected to the collector electrode of transistor Q3 via a resistance R12. the joined collector and base electrodes of transistors Qll and Q13 are connected to the collector electrode of a PNP transistor Q14, the emitter electrode of which is connected to supply terminal T2 via a resistance R13. The base electrode of transistor Q14 is connected to the collector electrode of Q2 and is further connected via a resistance R14 to the base and collector electrodes of a PNP transistor Q15. The emitter electrode of diode-connected transistor Q15 is connected to supply terminal T2. In operation, diode-connected transistors Q10, Qll, Q 12, and Q13, in conjunction with resistors R8 and R9, form a variable load for the collector electrodes of the emitter-coupled differential amplifier transistors Q4 and Q5. The output signal is buffered by Q8 and Q9 operating as voltage followers of the emitter-follower type. The DC through diode-connected transistors Q10, Qll, Q12, and Q13 is determined by the current mirror output current in the collector electrode of Q3 and in the equal collector current of Q2, as thereafter mirrored by the current mirror formed by PNP transistors Q14 and Q 15. When these currents are zero, as will occur when the current in resistance Rl is zero, diode-connected transistors Q10, Qll, Q12, and Q13 present high impedances. Consequently, the amplifier gain as determined by the gain of the differential pair amplifier is at a maximum, being defined by the collector resistors. When current is applied to diode-connected transistors Q10, Qll, Q12, and Q13, responsive to increasing the positive potential at terminal TI, their impedance becomes relatively low and the gain of the emitter-coupled differential amplifier comprising Q4 and Q5 is reduced. The collector electrodes of transistors Q3 and Q14 source and sink closely equal currents so that the same current enters as leaves the network comprising diode-connected transistors Q10, Qll, Q12, and Q13. Under this condition, no current is added to or removed from the collector electrode nodes of Q4 and Q5. Thus, if diode-connected transistors Q10, Qll, Q12, and Q13, and the transistors supplying current to them are well matched, there will be no disturbance of the DC conditions of operation of the amplifier as the gain is changed. Such matching is readily accomplished on a monolithic IC. Furthermore, the network comprising diode-connected transistors Q10, Qll, Q12, and Q13 is in the form of a bridge, so that the nodes where currents are supplied to the network are at AC ground, forming a "virtual ground" for RF currents. One result of this is that the PNP transistor Q14 carries only DC and its collector capacitance does not affect the frequency response of the amplifier. Another effect is that there is no signal return to ground through the diode-connected transistors Q10, Qll, Q12, and Q13. It is also noted that the gain control variable elements are in the collector circuit of the differential pair amplifier, thereby allowing design freedom in biasing the emitter circuit for large signal handling capability and so extending the overload characteristic. Furthermore, the power required to effect gain control is limited. In the FIGURE 1 amplifier stage the collector loads of the emitter-coupled differential amplifier are just the resistive loads at maximum gain, since the diodes used to shunt them are nonconducting under this condition. The use of resistances as collector loads is advantageous in that: the maximum voltage gain of each stage can be predicted, despite the construction of the gain-controlled amplifier in an IC, and this permits gain-controlled amplifier stages to be mass-produced in IC form without the need for individual adjustment of each amplifier stage in regard to maximum voltage gain. The maximum voltage gain of each amplifier stage is the product of the transconductance (gm) of an emitter-coupled differential-amplifier transistor times the resistance (RL) of its collector load. The gm of the transistor is determined by its emitter current flow, which current flow is made proportional to a applied bias voltage VBIAS (less, typically, a semiconductor junction offset voltage VBE) applied across a resistive element with resistance RBIAS included on the IC with the resistive loads and arranged to be of the same type as the resistive loads. That is, the emitter current flow of the emitter- coupled differential-amplifier transistor is made to track a bias current IBIAS = (VBIAS - VBE) /RBIAS, SO its maximum voltage gain, gmRL, is proportional to [ (VBIAS VBE) /RBIAS] RL = (VBIAS - VBE) (RL/RBIAS) . Since (RL/RBIAS) is the ratio of on-chip resistive elements, the value of this ratio is very well defined and can be accurately predicted. The few millivolt variation of VBE with temperature is usually negligible compared to (VBIAS - VBE) , a voltage which depends on the bias voltage VBIAS applied from off-chip and can be arranged to have a well- predicted value. The value of RL is normally chosen to provide a maximum voltage gain of about ten times or so for a controlled-gain amplifier stage. The first stage of a PIX IF amplifier has to accommodate the full dynamic range of differential IF input potential signal to the amplifier, the amplitude of the IF signal supplied to the later stage(s) of the PIX IF amplifier being subject to a lesser dynamic range of input signal level owing to the gain control afforded by the first stage. The first stage of a PIX IF amplifier has to have the capability of avoiding overload on the peaks of the largest differential IF input signals received during strong-signal reception, when the gain control of the preceding RF amplifier runs out of range. The FIGURE I gain-controlled amplifier is fitted for use as the first stage of a PIX IF amplifier, with the differential amplifier transistors Q4 and Q5 being emitter-coupled with substantial differential-mode resistance between their emitter electrodes. The linear differential-mode resistance provided by the resistors R5 and R6 permits the differential IF input signal potential between their base electrodes to reach as high about 100 millivolts RMS without either transistor being cut off on signal peaks. The differential-mode resistance between the emitter electrodes of transistors Q4 and Q5 can be provided in other known ways — e. g., by the resistance of the resistor R61 in the FIGURE 8 pi network replacement for the FIGURE I tee network connection of resistors R5, R6 and R7; by the resistance of a resistor corresponding to resistor R61 in another pi network that is a modification of the FIGURE 8 pi network, in which other pi network transistors biased for constant-current-source operation replace the resistors R62 and R63; and by the combined resistances of the resistors R5 and R6 in a modification of the FIGURE 1 tee network connection of resistors R5, R6 and R7 in which a transistor biased for constant-current-source operation replaces the resistor R7. In the FIGURE 2 gain-controlled amplifier, a transistor Q21 is of NPN conductivity type and has its base and collector electrodes conductively joined so as to operate in a diode-connected mode. The emitter electrode of Q21 is connected via a resistance R21 to a source of a reference potential, here shown as ground. A reference current is supplied to the joined base and collector electrodes via a resistance R22 having one end thereof connected thereto and another end thereof connected to receive a positive direct bias potential VB3 applied to a terminal T21. FIGURE 2 shows VB3 as being supplied from a battery B3. An NPN transistor Q22 has its emitter electrode connected to ground via a resistance R23 and its base electrode connected to the base electrode of transistor Q21, so as to form a current mirror arrangement with respect to the reference current supplied via R22. NPN transistors Q23 and Q24 form a differential amplifier pair, having their respective emitter electrodes connected to the collector electrode of transistor Q22. The base electrode of transistor Q23 is connected to a terminal T22 for receiving a gain control signal thereat, herein represented as being supplied by a source GC2, and the base electrode of transistor Q24 is connected to a terminal T23 for receiving a positive direct bias potential VB4 thereat, herein represented as being supplied by a battery B4. NPN transistors Q25 and Q26 form a differential amplifier pair wherein their emitter electrodes are connected to the collector electrode of transistor Q24. Their base electrodes are connected to respective input terminals T25 and T26 for receiving a balanced input signal referred to a direct bias potential. Figure 2 shows a battery B5 with its negative terminal connected to a point of ground reference potential supplying a direct bias potential VB5 at its positive terminal against which are referred balanced input signals supplied by generators S3 and S4 to the terminals T25 and T26. The collector electrodes of transistors Q25 and Q26 are connected via respective resistances R24 and R25 to a supply terminal T27 for receiving a positive operating potential VB2, shown as being supplied from the battery B2. The collector electrode of transistor Q25 is further connected to the joined collector and base electrodes of an NPN transistor Q27 and the collector electrode of transistor Q26 is further connected to the joined collector and base electrodes of an NPN transistor Q28. The joined emitter electrodes of Q27 and Q28 are connected to the collector electrode of transistor Q23 and are further connected to terminal T27 by a resistance R26. NPN transistors Q29 and Q30 are arranged as voltage followers of the emitter-follower type, which serve as output buffer stages. The base electrodes of Q29 and Q30 connect to the collector electrodes of Q26 and Q25, respectively, and the collector electrodes of Q29 and Q30 connect to supply terminal T27. The emitter electrode of transistor Q29 is connected to an output signal terminal T28 and to one end of a resistance R27 the other end of which is connected to ground. The emitter electrode of transistor Q30 is connected to an output signal terminal T29 and to one end of a resistance R28 the other end of which is connected to ground. In operation, current from the current mirror output at the collector electrode of transistor Q22 is steered by the transistor pair Q23 and Q24, between providing tail current for the differentialamplifier transistors Q25 and Q26 on the one hand, and providing bias current for diode- connected transistors Q27 and Q28, on the other hand. When the diode-connected transistors Q27 and Q28 carry no current, the gain is at its maximum value, being determined by maximum tail current and by the collector load resistances R24 and R25. When the AGC potential GC2 is made positive enough to bias transistor Q23 into conduction, the diode-connected transistors Q27 and Q28 are biased into conduction to shunt the collector resistances R24 and R25 of the transistors Q25 and Q26 to reduce their gain. At the same time the conduction of transistor Q23 reduces the current available for flow through Q24 and as tail current for the transistors Q25 and Q26, which reduced tail current operates them at reduced transconductance and thus reduces their gain further. In any event, the DC through each of resistances R24 and R25 is not disturbed by the operation of gain control. However, when more than half of the operating tail current for the differential amplifier pair is steered into the diode-connected transistors Q27 and 028, noise performance will start to degrade. This is because of the poorer noise figures of the transistors Q25 and 026 as their internal emitter resistances increase responsive to reduced current conduction by the principal conduction path of transistor Q24. Accordingly, the reduction of stage gain by the shunting of the collector load resistances R24 and R25 by diode-connected transistors Q27 and Q28 is the mechanism for gain reduction principally relied on, rather than reduction of the transconductances of Q25 and 026 through starvation of their tail current. The normal range of gain control is upward from about 0 dB, then, to 26 dB or so. The FIGURE 2 gain-controlled amplifier is not particularly well-suited for use as the initial stage of a plural-stage IF amplifier, because it will overload rather quickly on overlarge input signals. Since the FIGURE 2 gain-controlled amplifier relies more on diode shunting of the collector loads of the emitter-coupled transistors Q25 and Q26 than on reduction of their transconductances through starvation of their tail current, this shortcoming can be appreciably overcome by including emitter degeneration resistances for the transistors Q25 and Q26 in their emitter coupling. The modified stage still does not perform quite so well as the first stage of an IF amplifier as does either the FIGURE I or FIGURE 4 gain-controlled amplifier, because of the above-noted problem of noise figure being degraded as gain is cut back below 0 dB. In the later stage(s) of an IF amplifier, however, where the dynamic range of input signal to the stage(s) is reduced, the simpler construction of the FIGURE 2 gain-controlled amplifier makes it the favored choice over the FIGURE I or FIGURE 4 gain-controlled amplifier. FIGURE 3 shows a cascade connection of the FIGURE 1 and FIGURE 2 gain-controlled amplifiers. In operation, typically in television IF amplifier service, the two gain control signals at inputs TI and at T22, respectively, are arranged to cooperate such that, when gain reduction starts to be applied, the gain of the second amplifier is first reduced without reducing the gain of the first amplifier. When the gain of the second amplifier has been reduced by a predetermined amount, subsequent amounts of gain reduction reduce the gain of both first and second amplifiers in a predetermined relationship. Thus, for small amounts of gain reduction, the first amplifier stage continues to operate at its full gain while overall gain reduction is achieved by reducing the gain of the second amplifier. As is known, such a mode of operation, known as delayed gain control, is beneficial to the overall noise performance because the contribution of the second amplifier is thereby kept small for smaller signals where amplifier noise may still be significant. In practice, such a delay is readily achievable by various means not shown here such as, for example, by the introduction of a voltage delay for the signal to the first amplifier. The FIGURE 1 and FIGURE 2 amplifiers are suited for operation from a single positive operating supply, and FIGURE 3 accordingly shows the supply terminal T27 connecting from the supply terminal T2. In practice the batteries B3 and B4 are replaced by networks within the same IC as the first and second gain-controlled amplifiers, which networks are of known type for deriving bias potentials from an operating supply potential as supplied via the supply terminal T2. FIGURE 4 shows another gain-controlled amplifier that is well suited for use as the first stage in a television IF amplifier. The FIGURE 4 amplifier includes a transistor Q41 of NPN conductivity type, which has its base and collector electrodes conductively joined so as to operate in a diode-connected mode. The emitter electrode of Q41 is connected via a resistance R41 to a source of reference potential, shown as ground in FIGURE 4. A reference current is supplied to the joined base and collector electrodes via a resistance R42 having one end thereof connected to them and having another end thereof connected to receive a positive operating potential VB3 applied to a terminal T41. FIGURE 4 shows the battery B3 supplying this potential. An NPN transistor Q42 has its emitter electrode connected to ground via a resistance R43 and its base connected to the base electrode of transistor Q41, so as to form a current mirror arrangement with respect to the reference current supplied by R42. NPN transistors Q43 and Q44 form a differential amplifier pair, having their respective emitter electrodes connected to the collector electrode of transistor Q42 via respective resistances R44 and R45 and their base electrodes connected to respective input terminals T42 and T43 for receiving an input signal therebetween at an appropriate direct bias level. FIGURE 4 shows signal sources SI and S2 applying a balanced input signal to the input terminals T42 and T43, as referred to a positive direct bias potential VB1 provided from the battery Bl. The NPN transistors 'Q45 and Q46 are connected as a current splitter for the collector current of transistor Q43, with each of them having its emitter electrode connected to the collector electrode of transistor Q43. The NPN transistors Q48 and Q49 are connected as a current splitter for the collector current of transistor Q44, with each of them having its emitter electrode connected to the collector electrode of transistor Q44. The base electrodes of transistors Q45 and Q48 are connected to receive a positive direct bias potential VB6 applied to a terminal T45. FIGURE 4 represents the source of VB6 by a battery B6. The base electrodes of transistors Q46 and Q49 are connected to a terminal T44 for receiving a gain control voltage thereat, which FIGURE 4 shows as being supplied from a source of control . voltage GC4. The collector electrodes of transistors Q45 and Q48 are connected via a resistance R46 and via a resistance R47, respectively, to a supply terminal T46 to which a positive operating potential VB2 is applied from the battery B2. An electrically controllable conductance is provided between the ends of the resistances R46 and R47 remote from terminal T46. The joined collector and base electrodes of an NPN transistor Q47 and the collector electrode of transistor Q45 connect to the end of the resistance R46 remote from terminal T46. The joined collector and base electrodes of an NPN transistor Q50 and the collector electrode of transistor Q48 connect to the end of the resistance R47 remote from the supply terminal T46. The joined collector electrode and base electrodes of an NPN transistor Q47 connect to the collector electrode of transistor Q45. The emitter electrodes of transistors Q47 and Q50 and the collector electrodes of transistors Q46 and Q49 are all conductively joined and are connected to the supply terminal T46 via a resistance R48. The gain-controlled response appearing at the end of the resistance R46 remote from terminal T46 is applied to an output terminal T47 by the voltage-follower action of the NPN common-collector-amplifier transistor Q8. The gain-controlled response appearing at the end of the resistance R47 remote from terminal T46 is applied to an output terminal T48 by the voltage-follower action of the NPN common-collector-amplifier transistor Q9. In operation, the collector output current of differential-amplifier transistor Q43 constitutes the tail current of differential pair transistors Q45 and Q46, which function as a current splitter. Depending on the control signal level at terminal T44, the collector output current of differential pair amplifier transistor Q43 can be steered through transistor Q45 or through transistor Q46 and thence through diode-connected transistor Q47, or partly through each of transistors Q45 and Q46. In symmetrical fashion, the collector output current of differential pair amplifier transistor Q44 can be steered through transistor Q48 or through transistor Q49 and thence through diode-connected transistor Q50, or partly through each of transistors Q48 and Q49. The steering of currents to flow entirely through the transistors Q46 and Q49 applies the entire collector currents of transistors Q43 and Q44 including their differential variations to the node between the diode- connected transistors Q47 and Q50, where the differential signal variations cancel each other out at a "virtual ground" for AC. There are no components of Q45 and Q48 collector currents flowing through transistors Q46 and Q49, the differential variations of which can respectively flow to the load resistances R46 and R47 to cause corresponding signal voltages across them. The common-mode DC components of the collector currents of transistors Q43 and Q44 are in combined flow through the diode-connected transistors Q47 and Q50, causing their conductances to become relatively small respective to the load resistances R46 and R47, respectively. The low shunt resistances of the diode- connected transistors Q47 and Q50 determine the voltage gain of the FIGURE 4 amplifier as they ratio against resistances R46 and R47, respectively. When the combined collector currents of transistors Q43 and Q44 are steered through diode-connected transistors Q47 and Q50, the gain will be at its minimum level. The steering of currents to flow entirely through the transistors Q45 and Q48 applies the entire collector currents of the transistors Q43 and Q44 including their differential variations to the load resistances R46 and R47, respectively. The concomitant steering of currents away from the transistors Q46 and Q49 results in no current being steered through the diode-connected transistors Q47 and Q50, so their conductances are accordingly very low and do not shunt the load resistances R46 and R47 appreciably. The voltage gain of the FIGURE 4 gain-controlled amplifier- is therefore is at its maximum level. The steering of the collector currents of the emitter- coupled differential amplifier transistors Q43 and Q 4 4 partially through transistors Q45 and Q48 reduces gain by applying only a fraction of the differential variations of the collector currents to the load resistances R46 and R47, thereby reducing the corresponding signal voltages across them in a degree controlled by the gain control potential GC4. The steering of the collector currents of the emitter-coupled differential amplifier transistors Q43 and Q44 partially through transistors Q46 and Q49 at the same time further reduces gain by causing the common-mode components of the collector currents to flow through the diode-connected transistors Q47 and Q50, so their conductances shunt the load resistances R46 and R47 in a degree also controlled by the gain control potential GC4. In any case, the total current in resistance R46 remains unchanged during the gain control process, being always equal to the collector output current of transistor Q43 and likewise, the total current in resistance R47 remains unchanged during the gain control process, being always equal to the collector output current of transistor Q44. Thus, if the transistors are well matched, there will be no disturbance of the DC conditions of operation of the amplifier as the gain is changed. Similar advantages result with the FIGURE 4 gain- controlled amplifier as were described in reference to the FIGURE 1 gain-controlled amplifier. The FIGURE 4 gain- controlled amplifier is fitted for use as the first stage of a PIX IF amplifier, with the differential-amplifier transistors Q43 and Q44 being emitter-coupled with substantial differential-mode resistance between their emitter electrodes in order to avoid overload distortion at expected IF amplifier input signal levels. The linear differential-mode resistance provided by the resistors R44 and R45 permits the differential IF input signal potential between their base electrodes to reach as high as about 100 millivolts RMS without either transistor being cut off on signal- peaks. The various emitter-coupling networks described above with regard to the differential-amplifier transistors Q4 and Q5 can be used with differential- amplifier transistors Q43 and Q44 as well. FIGURE 5 shows a cascade connection of the FIGURE 4 and FIGURE 2 gain-controlled amplifiers. NPN transistors Q8 and Q9, with current sources ISl and IS2, forward biasing their emitters form emitter-follower buffer stages for the output of the first amplifier. The input signal is applied at terminals T42 and T43 and the two gain control signals are applied at terminals T44 and T22, respectively. Similar considerations to the FIGURE 3 cascade connection of gain-controlled amplifiers are applicable regarding delayed gain control or delayed automatic gain control. The FIGURE 4 and FIGURE 2 amplifiers are suited for operation from a single positive operating supply, and FIGURE 5 accordingly shows the supply terminal T27 connecting from the supply terminal T46. In a variant of FIGURE 5, the transistor Q42 receives its base potential from the joined collector and base electrodes of Q21; and elements R41, R42 and Q41 are dispensed with. FIGURE 6 shows circuitry that is included in an IC together with a cascade connection of amplifier stages, either as shown in FIGURE 3, or as shown in FIGURE 5. In FIGURE 6 a transistor Q61 is of NPN conductivity type and has its base and collector electrodes conductively joined so as to operate in a diode-connected mode. The emitter electrode of Q61 is connected via a resistance R61 to a source of a reference potential, here shown as ground. A reference current is supplied to the joined base and collector electrodes via a resistance R62 having one end thereof connected thereto and another end thereof connected to receive a positive direct bias potential VB3 applied to the terminal T21. FIGURE 6 shows VB3 as being supplied from a battery B3. NPN transistors Q62 and Q63 have their emitter electrodes connected to ground via resistances R63 and R64, respectively, and have their base electrodes connected to the base electrode of transistor Q61, so as to form a dual-output current mirror arrangement with respect to the reference current supplied via R62. NPN transistors Q64 and Q65 form a differential amplifier pair, having their respective emitter electrodes connected to the collector electrode of transistor Q62. The gain-controlled, amplified, balanced IF signals at the emitter electrodes of the-emitter-follower transistors Q29 and Q30 are applied to the base electrodes of transistors Q64 and Q65. The collector electrodes of transistors Q64 and Q65 are connected via respective resistances R64 and R66 to a supply terminal T27 for receiving a positive operating potential VB2, shown as being supplied from the battery B2. NPN transistors Q66 and Q67 are arranged as voltage followers of the emitter-follower type, which serve as output buffer stages. The base electrodes of Q66 and Q67 connect to the collector electrodes of Q64 and Q65, respectively, and the collector electrodes of Q66 and Q67 connect to supply terminal T27. The emitter electrodes of transistors Q66 and Q67 connect to ends of respective load resistances R67 and R68 the other ends of which connect to ground. The emitter electrodes of transistors Q66 and Q67 supply balanced IF output signals superposed on direct bias potentials to a second detector DET. The automatic adjustment of these direct bias potentials to eliminate any substantial difference between them is an objective of the invention herein described and claimed. The second detector DET supplies an output signal to the terminal T60 and may, as shown in FIGURE 6, supply another output signal to the terminal T61, which output signals are balanced in nature. The second detector DET is normally included in the same IC as the IF amplifier, because off-chip stray coupling back to the input of the IF amplifier of the relatively small remnant IF signals from the output of the second detector DET is not, as likely to cause undesirable undamped regeneration as the amplified IF would if brought off-chip. However, in less-preferred embodiments of the invention the second detector DET may not be in the same IC as the IF amplifier. The direct bias potentials on which the balanced IF output signals are superposed are automatically adjusted by a differential-mode direct-coupled DC feedback loop. The balanced IF output signals at the collector electrodes of transistors Q64 and Q65 are supplied to a four-terminal lowpass filter LPF, which supplies a balanced response to the base electrodes of common-collector-amplifier NPN transistors Q68 and Q69. The transistors Q68 and Q69 have respective emitter load resistors R69 and R70 connecting from their emitter electrodes to a point at ground potential. The balanced response applied to the base electrodes of transistors Q68 and Q69 essentially consists of the direct bias potentials on which the balanced IF output signals are superposed; and transistors Q68 and Q69 function as voltage followers of the emitter-follower type for applying the difference between these direct potentials between the base electrodes of NPN transistors Q70 and Q71. The transistors Q70 and Q71 are connected in emitter— coupled differential amplifier conguration. The interconnection of their emitter electrodes has the collector electrode of the NPN transistor Q63 connected thereto, and transistor Q63 withdraws a collector current from this tail connection that is proportional to the reference current flowing through the resistance R62, owing to the current mirror action of transistors Q61 and Q63. The collector electrodes of the transistors Q70 and Q71 are connected withdraw balanced currents from the emitter electrodes of the previously described emitter-follower transistors Q8 and Q9, respectively, in response to the difference between the direct potentials on which the balanced IF output signals supplied to the second detector DET are superposed. These connections close the direct- coupled, differentialmode DC feedback loop used for eliminating any substantial difference between these direct bias potentials. The lowpass filter LPF includes a resistance R71 for connecting the collector electrode of transistor Q64 to the base electrode of transistor Q68, a resistance R72 for connecting the collector electrode of transistor Q65 to the base electrode of transistor Q69, and a floating capacitance Cl connected between the base electrodes of transistors Q68 and Q69.. The lowpass filter LPF further includes two similar capacitances C2 and C3 shunting the base electrodes of transistors Q68 and 69, respectively, to a point or points of ground potential. The capacitances C2 and C3 are relatively small compared to the floating capacitance Cl and supress conunon-mode signal at the base electrodes of transistors Q68 and Q69. The capacitances Cl, C2 and C3 are typically of metal- oxide-semiconductor (MOS) construction. The floating capacitance Cl provides the equivalent filtering action of two shunt-to-ground capacitances, each twice its capacitance size. An MOS floating capacitance C 1 takes up only a quarter as much IC die area as two shunt-to-ground capacitances providing equivalent filtering action. The floating capacitance Cl may be constructed from two MOS capacitors of the same size, parallelly connected with the metal plate of each connecting to the polysilicon plate of the other. The equal capacitances of the polysilicon plates to substrate ground appear in respective ones of the capacitances C2 and C3, then, as at least portions of those capacitances. Since the feedback loop used for eliminating any substantial difference between the direct bias potentials on which balanced IF signals are superposed is around only two voltage-gain stages with a maximum voltage gain of a hundred-fold to two-hundredfold, rather than around three voltage-gain stages with a maximum voltage gain of a thousand-fold or more, the primary open-loop pole provided by the lowpass filter LPF need not be located as low in frequency in order to assure closed-loop stability. This reduces the required size of the floating capacitance Cl. The faster time constant in the feedback loop makes it less prone to "setting up" during impulse noise or start-up conditions. The use of differential-mode current feedback to the emitter electrodes of emitter-follower transistors Q9 and Q8 provides a non-linear feedback response with reduced gain for large errors. This also tends to prevent erratic behavior by the feedback loop during start-up or impulse noise conditions. FIGURE 7 shows a modification that can be made to the FIGURE I gain-controlled amplifier, in which modification the tee connection of resistors R5, R6 and R7 is replaced by an equivalent pi connection of resistors R81, R82 and R83. The resistance of R61 equals the sum of the resistances of R5 and R6; the resistance of R82 equals the sum of the resistances of R5 and R7; the resistance of R83 equals the sum of the resistances of R6 and R7. FIGURE 8 shows a modification that can be made to the FIGURE I gain-controlled amplifier, in which modification the tee connection of resistors R44, R45 and the constant current source formed by transistor Q42 and resistor R43 is replaced by an equivalent pi connection of resistor R84 and two constant current sources, one formed by transistor Q81 and resistor R85, and the other formed by transistor Q82 and resistor R86. That is, the single-output current mirror comprising elements Q41, R41, Q42 and R43 is replaced by a dual-output current mirror comprising elements Q41, R41, Q81, R85, Q82 and R86. FIGURE 9 shows those portions of a television receiver or video tape recorder used for recovering audio-signal, video-signal and synchronizing-signal portions of a transmitted television signal, which television receiver uses intermediate-frequency amplifiers of the type shown in FIGURE 3 or in FIGURE 5. FIGURE 9 is useful in understanding how delayed automatic gain control can be applied to intermediate-frequency amplifiers of the type shown in FIGURE 3 or in FIGURE 5. An intermediate-frequency amplifier used for further amplifying the inter sound signal after its detection is commonly termed a "sound IF amplifier". To avoid confusion, the following description of FIGURE 9 will use the term "video IF amplifier" only to refer to the IF amplifier used to supply input signal to the sound detector generating the inter sound signal and will use the term "PIX IF amplifier" only to refer to the IF amplifier used to supply input signal to the video detector generating a composite video signal. The term "IF amplifier" will be a generic term referring to either a "video IF amplifier" or to a "PIX IF amplifier", but not to a "sound IF amplifier". Television signals captured by an antenna 10 are supplied to a radio-frequency amplifier 12. A downconverter 14, which typically includes a mixer and one or more tunable oscillators oscillating at frequencies above those in the television signal bands, responds to the amplified television signals supplied from the radio- frequency amplifier 12 to generate IF signals with sound carrier at 41.25 MHz and picture carrier at 45.75 MHz. The downconverter 14 is sometimes referred to as the "first detector". The IF signals from this first detector are supplied to a block filter 16 that separates the sound carrier and its FM sidebands (and the picture carrier as well in inter sound receivers) for application to a cascade connection of a first video IF stage 18, a second video IF stage 20, and a third video IF stage 22. An on-chip lowpass filter 24 responds to differences in the direct bias potentials on which the balanced IF output signals of the third video IF stage 22 are superposed, to supply differential-mode feedback signals to summing elements 26 and 28. The summing elements 26 and 28 combine the differential-mode feedback signals with the balanced output signals from the first video IF stage 18 to generate corrected input signals for the second video IF stage 20. The IF signals from the first detector are also supplied to a block filter 30 that separates the vestigial picture carrier and its AM sideband for application to a cascade connection of a first PIX IF stage 32, a second PIX IF stage 34, and a third PIX IF stage 36. An on-chip lowpass filter 38 responds to differences in the direct bias potentials on which the balanced IF output signals of the third PIX IF stage 36 are superposed to supply differential-mode feedback signals to summing elements 40 and 42. The summing elements 40 and 42 combine the differential-mode feedback signals with the balanced output signals from the first PIX IF stage 32 to generate corrected input signals for the second PIX IF stage 34. A second converter 44, which can be an exalted carrier synchronous detector in a television receiver generating sound-IF signal by the inter method, receives amplified 45 MHz IF signals from the third video IF stage 22 and responds to generate a frequency-modulated 4.5 MHZ-IF signal selected by a bandpass filter 46 with a passband centered at 4.5 MHz. The bandpass filter 46 suppresses the image frequencies that would otherwise accompany the frequency-modulated 4.5 MHz sound-IF signal, as applied to a limiter 48. The limiter 48 suppresses unwanted amplitude modulation of the frequency-modulated 4.5 MHz carrier it supplies as sound-IF response to an FM sound discriminator 50, which discriminator detects the frequency-modulation of the 4.5 MHz carrier to generate the audio signal to be supplied to the remainder of the television receiver or video tape recorder. There are other known means for detecting sound-descriptive information contained in the frequency modulation of the sound-IF response, which means include means for suppressing response of said means for detecting sound-descriptive information to variations in the amplitude of the sound-IF response, such as the well- known ratio detector. A video IF overload detector 52 responds to the amplified IF signals from the third video IF stage 2 2 exceeding a level acceptable as input signal to the down converter 44, to provide an auxiliary automatic-gain- control (AGC) signal to the first video IF stage 18, augmenting during abnormal conditions a normal automatic- gain-control (AGC) signal generated responsive to PIX IF signal. Under normal conditions, however, both the video IF and the PIX IF chains are gain controlled responsive solely to the normal automatic-gain-control (AGC) signal generated responsive to PIX IF signal. To facilitate the AGC tracking between the video IF and the PIX IF chains, the video IF amplifiers 18, 20 and 22 are constructed within the confines of the same IC as the PIX IF amplifiers 32, 34 and 36. The down-converter 44, the overload detector 52, a video detector 54, an AGC detector 56 and AGC delay circuits 58 and 60 are advantageously included within the same IC as well. The video detector 54, which receives amplified IF signals from the third PIX IF stage 36, detects a composite video signal. The automatic-gain-control (AGC) detector 56 develops an automatic-gain-control (AGC) signal by detecting peaks of the synchronizing pulses included in the composite video signal. If the video detector 54 is an envelope detector, the AGC detector 56 is normally a keyed AGC detector so as to provide the AGC immunity to impulse noise. If the video detector 54 is a synchronous detector, which is the modern trend in TV receiver design, the AGC detector 56 preferably includes filtering of its input signal to suppress response to the 2 MHz or so component of the composite video signal detected by the video detector 54, which component arises from the ringing of the block filter 30 at its midband natural frequency. This filtering of the input signal of the AGC detector 56 should pass frequencies up to about 500 kHz; this is so that equalizing pulses can be peak detected and the very top of the video image is not undesirably increased in brightness respective to the remainder of the video image. The AGC detector 56 in any case includes filtering of its output signal to a noise bandwidth of 400 Hz or so. The AGC signal developed by the AGC detector 56 proceeding from the composite video signal detected by the video detector 38 is used to control gain in both the PIX IF and the video IF amplifiers as well as gain in the RF amplifier 12. Developing AGC proceeding from the composite video signal permits precise gain control of the PIX IF amplifiers, which have to amplify AM sidebands linearly. The video IF amplifiers need gain control primarily to avoid overloading the down-converter 44, gross overloading of which is forestalled in any case by the video IF overload detector 52. The linearity with which the FM sidebands of the sound carrier are amplified is not of particular concern. The bandpass filter 46 and the limiter 48 suppress the effects of any gain errors in the video IF amplifier chain and the down-converter 44 as well. So obtaining acceptable AGC tracking of the video IF amplifiers 18 and 20 to the PIX IF amplifiers 32 and 34 is practical to obtain. The AGC signal developed by the AGC detector 56 is applied in parallel, without delay, to the second stages 20 and 34 of the video IF and PIX IF amplifiers. The AGC signal developed by the AGC detector 56 is applied in parallel, with delay, to first stages 18 and 32 of the video IF and PIX IF AMPLIFIERS. Preferably, as shown in FIGURE 9, the first stages 18 and 32 of the video IF and PIX IF amplifiers. Preferably, as shown in FIGURE 9, the first stages 18 and 32 of the video IF and PIX IF amplifiers have delayed AGC applied to them via respective AGC delay circuits 58 and 60, so that only a single AGC line has to be run from the portion of the IC having the PIX IF located therein and the portion of the IC having the video IF located therein. The AGC signal developed by the AGC detector 56 is applied to the RF amplifier 12 with still further delay, as provided by tuner gain control delay circuitry 60 usually located on the IF amplifier integrated-circuit chip. Under weak-signal-reception conditions, any reduction of the gain through the RF and IF amplifier chains takes place in the second stages 20 and 34 of the video IF and PIX IF amplifiers. The RF amplifier 12 and the first stages 18 and 32 of the video IF and PIX IF amplifiers operate at full gain to secure best signal-to-noise ratios in the signals supplied to the second stages 20 and 34 of the video IF and PIX IF amplifiers. As second stages 20 and 34 of the video IF and PIX, IF amplifiers reach favorable signal levels with increase in the RF signal level from the antenna 10, the AGC delay circuits 58 and 60 apply delayed AGC to the first stages 18 and 32 of the video IF and PIX IF amplifiers to reduce their gain. Under strong-signal- reception conditions, the tuner gain control delay circuitry 62 applies AGC signal to the RF amplifier 12 to reduce its gain, thereby- to avoid overloading the down¬ converter 14 and the first stages 18 and 32 of the video IF and PIX IF amplifiers. A dashed line 70 surrounds elements that, except for large-capacitance shunt bypass capacitors, are normally constructed within a single monolithic integrated circuit (IC) . The PIX IF chain is operated with balanced signals throughout, from the input signal applied to the first IF amplifier stage 32 from the PIX IF block filter 30 to the output from the third PIX IF amplifier stage 36 to the video detector 54, and the output signal from the video detector 38 is taken single-ended from the IC, to suppress any self-oscillatory tendencies in the higher-gain portions of the PIX IF gain control range. The video IF chain is operated with single-ended input signal applied to the first IF amplifier stage 18 from the video IF block filter 16, allowing some simplification of that block filter 16, but the rest of the video IF chain is operated with balanced signals, to suppress any self-oscillatory tendencies in the higher-gain portions of the video IF gain control range. The output signal from the downconverter 44 is supplied in balanced form to the bandpass filter 46, to suppress any self-oscillatory tendencies in the higher-gain portions of the video IF gain control range. The gain-controlled amplifiers of FIGURES 2 and 4 are readily modified so that gain reduction is effected in increasing degree by an AGC voltage becoming increasingly negative, rather than by an AGC voltage becoming increasingly positive. In FIGURE 2 the terminal T22 rather than the terminal T23 is connected to receive a direct bias potential VB4, and terminal T23 receives the AGC voltage that becomes increasingly negative so that gain reduction is effected in increasing degree. In FIGURE 4 the terminal T44 rather than the terminal T46 is connected to receive a direct bias potential VB6, and terminal T46 receives the AGC voltage that becomes increasingly negative so that gain reduction is effected in increasing degree. The gain- controlled amplifier of FIGURE I can also be modified so that gain reduction is effected in increasing degree by an AGC voltage becoming increasingly negative. One way to do this is to replace the current source and sink together comprising elements R 1, Q2, Q3, R13, R14, Q14 and Q15 with: a single-output current mirror for sinking via the resistor R12 the combined emitter currents of Q10 and Q12 an output current scaled to an input current supplied to that current mirror; a dual-output current mirror having an input connection referred in potential to VB2, having a first output connection for supplying the input current of the single-input current mirror, and having a second output connection for providing a current equal to the output current of the single-input current mirror as a source current to the combined base and collector currents of Qll and Q13; and a resistor connected between terminal TI and the input connection of the dual-output current mirror to generate an input current to that current mirror directly related to the AGC potential applied to terminal TI. The present invention is herein disclosed and its principles explained by way of exemplary embodiments, but is not limited just to such embodiments. As will be apparent to one skilled in the art, various changes and modifications can be made without departing from the spirit of the invention. By way of example, the embodiments herein described utilize NPN amplifying transistors; clearly, PNP transistors can be substituted with appropriate circuit modifications as familiar to persons skilled in the art, or field effect transistors may be used instead of bipolar transistors, again with appropriate circuit modifications as are familiar to persons skilled in the art. Furthermore, other forms of current mirrors can replace the particular forms herein used by way of explanation. It is also contemplated that current steering need not be achieved by conventional differentially coupled pairs, though these have the advantage of simplicity, but it may also be performed by other circuits which can split an input current into two components having a variable ratio. These and like changes are contemplated to be within the scope of the invention as defined by the claims following.

Claims: WHAT IS CLAIMED IS: 1. A first detector and a frequency-selective filter receiving input signal from said first detector, in combination with a monolithic integrated circuit, said monolithic integrated circuit comprising: a second detector of a type receiving balanced input signal voltages superposed on respective direct bias potentials; a direct-coupled cascade connection of amplifier stages for amplifying a response from said frequency- selective filter, thereby to supply to said second detector said balanced input signal voltages superposed on respective direct bias potentials; first, second and third emitter-coupled transistor differential amplifiers included in order of their ordinal numbering in said direct-coupled cascade connection of amplifier stages, each having a respective pair of input terminals and having a respective pair of output terminals, the response of said frequency-selective filter being applied between the input terminals of said first common- collector-amplifier transistor; automatic gain control circuitry for controlling the respective voltage gains of said first and second emitter- coupled transistor differential amplifiers; differential lowpass filtering of the balanced input signal voltages superposed on respective direct bias potentials supplied from respective ones of the pair of output terminals of said third emitter-coupled transistor differential amplifier, for generating balanced direct- current feedback signals; and means combining said balanced direct-current feedback signals with balanced output signals from the respective pair of output terminals of said first emitter-coupled transistor differential amplifier for application to the respective pair of input terminals of said second emitter- coupled transistor differential amplifier. 2. A combination as set forth in Claim 1, wherein said second detector is a video detector. 3. A combination as set forth in Claim 1, wherein said second detector is a downconverter followed by a bandpass filter for selecting a desired downconversion result from its image. 4. A combination as set forth in Claim 3, further including means for detecting information contained in said desired downconversion result. 5. A combination as set forth in Claim 4, wherein said means for detecting information contained in said desired downconversion result comprises: means for detecting the variation in frequency of said desired downconversion result. 6. A combination as set forth in Claim 1, wherein said means combining said balanced direct-current feedback signals with balanced output signals from the respective pair of output terminals of said first emitter-coupled transistor differential amplifier for application to the respective pair of input terminals of said second emitter- coupled transistor differential amplifier comprises: a fourth emitter-coupled transistor differential amplifier, having a respective pair of output terminals respectively connected to respective ones of the pair of input terminals of said second emitter-coupled transistor differential amplifier, and having a respective pair of input terminals; a four-terminal lowpass filter, having a respective pair of input terminals to which respective ones of the pair of output terminals of said third emitter-coupled transistor differential amplifier respectively connect, and having a respective pair of output terminals; and means for applying a difference in potentials at the output terminals of said lowpass filter between the input terminals of said fourth emitter-coupled transistor differential amplifier. 7. A combination as set forth in Claim 6, wherein said four-terminal lowpass filter comprises: first and second resistances of similar value, each having a respective first end to which a respective one of the pair of output terminals of said third emitter-coupled transistor differential amplifier is connected, and each having a respective second end connected to a respective one of the output terminals of said lowpass filter; and a capacitance having first and second plates respectively connected to respective ones of the output terminals of said lowpass filter. 8. A combination as set forth in Claim 7, wherein said means for applying a difference in potentials at the output terminals of said lowpass filter between the input terminals of said second emitter-coupled transistor differential amplifier comprises: first and second common-collector-amplifier transistors, having respective base electrodes to which respective ones of the pair of output terminals of said lowpass filter connect, and having respective emitter electrodes connected to respective ones of the pair of input terminals of said fourth emitter-coupled transistor differential amplifier. 9. A combination as set forth in Claim 6, wherein said means for applying a difference in potentials at the output terminals of said lowpass filter between the input terminals of said second emitter-coupled transistor differential amplifier comprises: first and second common-collector-amplifier transistors, having respective base electrodes to which respective ones of the pair of output terminals of said lowpass filter connect, and having respective emitter electrodes connected to respective ones of the pair of input terminals of said fourth emitter-coupled transistor differential amplifier. 10. A first detector and a frequency-selective filter receiving input signal from said first detector, in combination with a monolithic integrated circuit, said monolithic integrated circuit comprising: a second detector of a type receiving balanced input, signal voltages superposed on respective direct bias potentials; a direct-coupled cascade connection of amplifier stages for amplifying a response from said frequency- selective filter, thereby to supply to said second detector said balanced input signal voltages superposed on respective direct bias potentials; first, second and third emitter-coupled transistor differential amplifiers included in order of their ordinal numbering in said direct-coupled cascade connection of amplifier stages, each having a respective pair of input terminals and having a respective pair of output terminals, the response of said frequency-selective filter being applied between the input terminals of said first common- collector-amplifier transistor; first and second common-collector-amplifier transistors included in said direct-coupled cascade connection of amplifier stages, having respective base electrodes to which respective ones of the pair of output terminals of said first emitter-coupled transistor differential amplifier connect, and having respective emitter electrodes connected to respective ones of the pair 5 of input terminals of said second emitter-coupled transistor differential amplifier; automatic gain control circuitry for controlling the respective voltage gains of said first and second emitter- coupled transistor differential amplifiers; and 10 differential lowpass filtering of the balanced input signal voltages superposed on respective direct bias potentials supplied from respective ones of the pair of output terminals of said third emitter-coupled transistor differential amplifier, for generating balanced direct 15 current feedback signals applied to the emitter electrodes of said first and second common-collector-amplifier transistors. 11. A combination as set forth in Claim 9, wherein said second detector is a video detector. 20 12. A combination as set forth in Claim 10, wherein said second detector is a downconverter followed by a bandpass filter for selecting a desired downconversion result from its image. 13. A combination as set forth in Claim 12, further 25 including means for detecting information contained in said desired downconversion result. 14. A combination as set forth in Claim 13, wherein said means for detecting information contained in said desired downconversion result comprises: 30 means for detecting the variation in frequency of said desired downconversion result. 15. A combination as set forth in Claim 10, wherein said differential lowpass filtering of the balanced input signal voltages superposed on respective direct bias potentials supplied from respective ones of the pair of output terminals of said third emitter-coupled transistor differential amplifier comprises: a fourth emitter-coupled transistor differential amplifier, having a respective pair of input terminals, and having a respective pair of output terminals respectively connected to the emitter electrode of said first common- collector-amplifier transistor and to the emitter electrode of said second common-collector-amplifier transistor, for applying said balanced direct current feedback signals to the emitter electrodes of said first and second common- collector-amplifier transistors; a four-terminal lowpass filter, having a respective pair of input terminals to which respective ones of the pair of output terminals of said third emitter-coupled transistor differential amplifier respectively connect, and having a respective pair of output terminals; and means for applying a difference in potentials at the output terminals of said lowpass filter between the input terminals of said fourth emitter-coupled transistor differential amplifier. 16. A combination as set forth in Claim 10, wherein said four-terminal lowpass filter comprises: first and second resistances of similar value, each having a respective first end to which a respective one of the pair of output terminals of said third emitter-coupled transistor differential amplifier is connected, and each having a respective second end connected to a respective one of the output terminals of said lowpass filter; and a capacitance having first and second plates respectively connected to respective ones of the output terminals of said lowpass filter. 17. A combination as set forth in Claim 16, wherein said means for applying a difference in potentials at the output terminals of said lowpass filter between the input terminals of said second emitter-coupled transistor differential amplifier comprises: third and fourth common-collector-amplifier transistors, having respective base electrodes to which respective ones of the pair of output terminals of said lowpass filter connect, and having respective emitter electrodes connected to respective ones of the pair of input terminals of said fourth emitter-coupled transistor differential amplifier. 18. A combination as set forth in Claim 15, wherein said means for applying a difference in potentials at the output terminals of said lowpass filter between the input terminals of said second emitter-coupled transistor differential amplifier comprises: third and fourth common-collector-amplifier transistors, having respective base electrodes to which respective ones of the pair of output terminals of said lowpass filter connect, and having respective emitter electrodes connected to respective ones of the pair of input terminals of said fourth emitter-coupled transistor differential amplifier.

Inventors: HARFORD JACK RUDOLPH, HARFORD, JACK, RUDOLPH
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1993
Main classification: H04N5
IPC codes: H03G3, H04N5