Display control unit and display control method

Abstract: The present invention provides display control unit and method for binarizing data of an image to binary data by an error spared method while taking error data generated in binarizing previous images into consideration, and spreads error data generated in binarizing the current image to subsequent images to preserve a density of the input data and prevent moire and lumbrical noise, and provides display control unit and method which spreads an binarizing error generated in binarizing an image to images to be subsequently binarized to preserve a density so that a high quality image having a high tonality and a high resolution is produced.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to display control unit and display control method, and more particularly to display control unit and display control method for quantizing input data to binary data or multi-value data and sending it to a display apparatus. Related Background Art A display apparatus is essential to an information processing apparatus for test and image such as word processor, personal computer and workstation. Recently, as the information is distributed in multi-media and a processing performance of the information processing apparatus is improved, the display apparatus is required to display more information. As a result, the display apparatus of not only monochromatic display but also gray level or full color animation display is required. On the other hand, from the standpoint of cost reduction of the apparatus due to down-sizing and technology advancement and the improvement of an office environment, the desk personalization of the information processing apparatus, that is, a trend of one unit per person is being enhanced, and from the standpoint of effective utilization of the office space, the reduction of the size and the thickness of the apparatus is desired. In the past, such a display apparatus includes a Braun tube display apparatus (CRT) and a liquid crystal display apparatus (LCD). Of those, the former one, that is, the CRT has a high display performance but it is very expensive, and the former one, that is, the LCD includes several types which are generally thin but have some problems, respectively. As a high display performance one, a TFT liquid crystal display apparatus which has a drive element for each pixel is known. Since the drive elements are mounted on a surface of a liquid crystal glass, it has a low aperture factor and a display screen is dark. Further, a yield is low and a large size and fine screen is difficult to attain, and a cost is expensive. Accordingly, the TFT liquid crystal display apparatus is not yet common as a display apparatus for the information processing apparatus. A simple matrix type STN liquid crystal apparatus which is primarily used presently is of binary display type and includes problems in the display performance such as of low contrast, cross-talk and narrow viewing angle. Of the simple matrix type apparatus, a ferroelectric liquid crystal display apparatus (FLCD) which uses ferroelectric liquid crystal cells having a memory property is known. It does not have problems of contrast, viewing angle and cross-talk, but it can make only binary display at a present stage. When an image signal to be displayed is binarized, it will be very effective from the standpoint of improving the display performance if some image processing is made to produce a quasi-gray level expression of an overall image to be displayed. An error diffusion method which is a density reservation type binarizing method is known as a method for binary expressing the gray level. The publication "An Adaptive Algorithm for Spatial Greyscale" by Robert W. Floyd and Louis Steinberg in the "Proceeding of the S.I.D.", Vol. 17/2, Second Quater 1976 describes the principles of the error diffusion method. The publication "A Survey of Electronic Techniques for Pictorial Image Reproduction" by J.C. Stoffel and J.F. Moreland in the "IEEE Transactions on Communications", Vol. COM-29, No. 12, December 1981, describes the error diffusion method in comparison with other image processing algorithms for transforming continuous tone and halftone pictorial image input into spatially encoded representations compatible with binary output processes. This publication proposes the error diffusion method as the most suitable method. However, the error diffusion method includes problems of reduction of resolution power, moire and lumbrical noise in the process of binarization. Further, since the prior art method is applied to a still image, no attention is paid to a continuously changing image such as animation, that is, an image which varies time sequentially and hence the moire and noise appear prominently. It is an object of the present invention to provide a display control unit and method for displaying a high quality animation image on a display apparatus. This object is achieved by a display control unit and method as claimed in claim 1 and 6, respectively. The above object of the present invention will be apparent from the detailed description of the present invention made in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram of a system configuration of the present invention; Fig. 2 shows a block diagram of detail of a display apparatus interface 33 of Fig. 1; Fig. 3 show a time chart of signals used in the display apparatus interface; and Fig. 4 shows a flow chart of a display operation in an embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is now explained with reference to the drawings. Fig. 1 shows a system block diagram of one embodiment of the present invention. In Fig. 1, numeral 11 denotes a processor or CPU which controls the entire system in accordance with program and information from a memory and an interface to be described later. Numeral 12 denotes a main memory and numeral 121 denote a ROM (read-only memory) which stores a program to be executed by the CPU, a control program shown in Fig. 4 and initial settings required for the processing. In addition to the program stored in the ROM, a program from an external memory interface may be written into a RAM to execute it. Numeral 122 denotes a RAM (rewritable memory) which is used as a work area to temporarily store programs to be executed by the CPU 11 and various data during the execution. Numeral 13 denote a CPU peripheral control circuit which comprises a DMAC (direct memory access controller) 131 which conducts data transfer with the main memory and between the main memory 12 and various units of the present invention without routing the CPU 11, and a peripheral control circuit 132 for controlling the main memory 12 and various interruptions. Numeral 14 denotes a keyboard for entering character information and control information, numeral 15 denotes a mouse which serves as a pointing apparatus, and numeral 16 denotes a key input interface for controlling the keyboard 14 and the mouse 15 and connecting the signals. Numeral 17 denotes a scanner for inputting a still image into the system, numeral 18 denotes a video apparatus such as a television or VTR for generating a video signal of image information such as animation or still image, and numeral 19 denotes an image input interface for controlling the scanner 17 and the video apparatus 18 and inputting the signals from those devices to the system. Numerals 20 and 21 denote a floppy disk drive and a hard disk drive, respectively, which serve as external storage, numeral 22 denotes an external storage interface for controlling the external storage apparatuses and connecting the signals thereof to the system. Numeral 23 denotes a printer apparatus such as a laser beam printer or an ink jet printer which serves as an output apparatus, and numeral 25 denotes a printer interface for controlling the printer 23 and connecting the signals therefrom to the system. Numeral 26 denotes a public communication line such as a telephone line, numeral 27 denotes a LAN (local area network) such as Eathernet, and numeral 28 denotes a communication network interface for connecting the telephone line 26 and the LAN 27 to the system. Numeral 29 denotes an other input/output apparatus, and numeral 30 denotes an I/O interface for connecting the input/output apparatus 29 to the system. Numeral 32 denotes a display apparatus such as FLCD or LCD. In the present system, it is a monochromatic binary display apparatus having P x Q pixels (P horizontal pixels and Q vertical pixels). Numeral 33 denotes a display apparatus interface for displaying the signal from the system as an image on the display 32. Ll denote a system bus comprising an address bus, a data bus and a control bus for connecting signals between the apparatuses and controlling them. The display information inputted by the display interface 33 has a data length of 8 bits per pixel to express 0 to (2 8 - 1) gray levels. Accordingly, the display interface 33 converts the 8 bits/pixel data to 1 bit/pixel binary data and sends it to the FLCD 32. The 8 bits/pixel display information is processed by the CPU 11 based on the text, image and control information from the keyboard 14, the mouse 15, the scanner 17, the video apparatus 18, the floppy disk drive 20, the hard disk drive 21, the public line 26 and the network 27, or directly by the DMAC 131 and sent to the display interface 33 through Ll as the 8 bits pixel data. Fig. 2 shows a block diagram of detail of the display interface 33. As shown, the interface comprises, in major, a display RAM 2A, a binarization control unit 2B and a display control unit 2C. Numerals 201 and 202 denote RAM's (NVRAM's), that is, NVRAMa and NVRAMb for storing one screen of 8 bits/pixel display data and they are configured as a bit map RAM which is one-to-one associated with the pixels of the display. One of the pair of NVRAM's is connected to the Ll system bus to write the display data from the system. The other NVRAM is connected to the buses L21 and L22 which are connected to the binarization control unit 2B and it is used for the transfer of the display data to the binarization control circuit. The pair of NVRAM's are appropriately switched by the control from the system bus Ll from the system, and an address and control bus control circuit 205 to be described later. Numerals 203 and 204 denote an address and control bus switching circuit and a data bus switching circuit, respectively, for selectively connecting the NVRAMa and the NVRAMb to the system bus Ll and the binarization control unit buses L21 and L22. L21 and L22 denote address control bus and data bus, respectively, in the binarization control unit 2B. The data bus L22 is an 8-bit display data bus for expressing 0 to (2 8 - 1) gray levels. Numeral 205 denotes an address and control bus control circuit (A&CC) which generates read/write addresses of an error VRAM and a l-bit VRAM to be described later, controls the switching of the buses of the binarizing control circuit and supplies timing. Numeral 206, 207 and 208 denote 8-bit length error bit map RAM's (EVRAM's), namely, EVRAMa, EVRAMb and EVRAMc for storing errors (binarization errors) created when the 8-bit display information is binarized to "1" and "0" binary information. The binarization error data is in a range of 0 and ± (2 8-1 - 1), and a negative number is expressed by a 2's complement. When a signal having a signal level of 0 ≤ u ≤ 1 is binarized to "0" or "1", an error of u or (u-l) is created. This is called a binarization error. L24, L25 and L26 denote 8-bit data buses for the EVRAMa 206, EVRAMb 207 and EVRAMc 208, respectively. Numeral 209 denotes a bus switch which rotationally switches the connection of the data buses L24, L25 and L26 with 8-bit data buses L27, L28 and L29, respectively, by a control signal from the A&CC 205. Numerals 210 and 211 also denote bus switches which switch the buses as shown in Fig. 2 by the control signal from the A&CC 205, as the bus switch 209 does. Numeral 212 denotes a bit adder which converts 8-bit display data without sign and 8-bit binarization error data with sign sent from the data switch 204 through the data bus L22 to 9-bit data with sign. Numerals 213 and 214 denotes 2-input adders, and numerals 215 and 216 denotes an edge hold type latch circuit which is controlled by a timing signal (TCK signal of Fig. 3 to be described later) supplied from the A&CC 205. It is sampled at a rising edge of the timing signal. L31 denotes 9-bit display data derived from the sum of the adder 213 through the latch 215. It is the display data for the binarization. Numeral 217 denote a comparator which compares the 9-bit display data sent from the latch 215 through the data bus L31 with a fixed value 2 8-1 , and outputs "0" if (display data) < 2 8-1 , and outputs "1" if 2 8 + 2 8-1 > (display data) ≧ 2 8-1 Numeral 218 denotes an error calculation circuit which calculates the 8-bit binarization error with sign based on the output from the latch 215 and the comparison output from the comparator 217 and supplies it to L32. Numerals 219 and 220 denote weighting circuit for 8-bit with sign which weights 1/4 and 3/4, respectively to the error data from the error calculation circuit 218. Numeral 221 denotes a bit map video RAM (lbVRAM) for storing the binarized display information. Numeral 222 denotes a VRAM control circuit (lbVRAMC) for writing the output data from the comparator 217 to the lbVRAM 221, transfers the binary display data to a display control circuit 2C to be described later, and arbitrates them. Numeral 2C denotes a display control circuit which receives a display request signal from the display 32 to read the display data from the lbVRAM 221 and transfer it to the display 32. Fig. 3 is now explained. Fig. 3 shows a timing of data signals in the address control bus L21. TCK is a basic clock for the operation of the binarization control unit 2B. Other signals and the buses are operated with reference thereto. VRAM address is one for accessing the NVRAMa 201 (or NVRAMb 202), the EVRAMa 206 to EVRAMc 208 and the lbVRAM 221. EVRAMR/W is a control signal for controlling the reading of the data from the EVRAMa 206 to EVRAMc 208 and the writing of data to the EVRAMa 206 to EVRAMc 208. It reads with a logical level "l" and writes with "0". An operation of the present invention is now explained in connection with the display interface of the present invention with reference to the address bus signal generated by A&CC and the timing signal of Fig. 3 and the flow chart of Fig. 4. After the start-up of the system and before the start of the display operation, the contents of the NVRAMa 201 to NVRAMb 202, the EVRAMa 206 to EVRAMc 208, the lbVRAM 221 and the latches 215 and 216 are initialized and cleared (to "0") by the CPU (Sl in Fig. 4). Then, the bus switching circuit 209 connects the data bus L24 with the data bus L27, the data bus L25 with the data bus L28, and the data bus L26 with the data bus L29, and throws SW 210 to the bit adder 212 and opens SW 211 (S2 in Fig. 4). As described above, the 8-bit display data of the system is sent to the display interface 33 through the system bus Ll as the 8-bit pixel data. The NVRAMa 201 and NVRAMb 202 are, on one hand, connected to the system bus Ll of the system by the control data from the system bus Ll and the A&CC 205, and on the other hand, connected to the binarization control circuit 2B, and the transferred display data is written into the NVRAMa 201 or NVRAMb 202 connected to the system bus Ll (S3 in Fig. 4). On the other hand, the A&CC monitors the system bus Ll and the binarization control bus L21 (S4 in Fig. 4), and when the system completes the writing of the display image pixels (one display screen) to the NVRAMa 201 or NVRAMb 202, it switches the connection of the NVRAMa 201 or NVRAMb 202 (S5 in Fig. 4). After the switching, new 8-bit data from the system bus Ll is written into the other NVRAM. Thus, the operation of the binarization control unit 2B is started. First, the VRAM address is set to "0", and as shown in Fig. 3, the address set in the address control bus L21 is read at the rise of TCK (S7 in Fig. 4). When TCK changes to "0" level, the 8-bit display data written in the NVRAMa 201 or NVRAMb 202 from the system is read and supplied to L22. The binarization error data is read from the EVRAMa 206 to EVRAMc 208 are read and supplied to the corresponding buses L24 to L26, respectively. The binarization error data of the EVRAMa 206 on L24 is supplied, by the bus switching circuit 209 to the bit adder 212 through L27 and SW 210. On the other hand, the binarization error data of the EVRAMb 207 on L25 is supplied, by the bus switching circuit 209, to the latch 216 through L28 (S8 in Fig. 4). The 8-bit display data on L22 and the binarization error data on L24 are supplied to the bit adder 212 where they are converted to 9-bit data and summed by the adder 213, and the sum is supplied to the latch 215 through L30 (S9 in Fig. 4). At the rise of TCK, the latch 215 latches and the sum of the 8-bit display data on L22 and the binarization error data on L24 is supplied to L31. Further, the latch 216 latches and the binarization error data of the EVRAMb 207 is supplied to the adder (S10 in Fig. 4). When TCK change to "l" level, the EVRAMR/W signal which indicates the reading and the writing of the data from and to the EVRAMa 206 to EVRAMc 208 is changed from "l" to "0" to switch the control from the reading to the writing, and the connection of L27 of SW 210 is changed from the bit adder 212 to "0", and the connection of L28 of SW 211 is changed from the open state to the output of the adder 214 (Sll in Fig. 4). At the same time, the 9-bit data on L31 is compared with the threshold 2 8-1 by the comparator 217, and it is binarized to either "0" or "l" depending on the comparison result. The error calculation circuit 218 operates based on the result to supply the binarization error data of 8 bits with sign to L32 (S12 in Fig. 4). "0" is supplied to L24 through SW 209, L27 and the bus switch 210, and it is written into the EVRAMa 206 (S13 in Fig. 4). That is, the data of the EVRAMa 206 is cleared. The output of the latch 216, that is, the binarization error signal written in the EVRAMb 207 and the binarization error data of 8 bits with sign which is weighted by a factor of 3/4 by the weighing circuit 219 are summed by the adder 214, and the sum is supplied to L25 through SW 211, L28 and the bus switch 209 and it is written into the EVRAMb 207 (S14 in Fig. 4). The binarization error data of 8 bits with sign which is weighted by a factor of 1/4 by the weighing circuit 220 is supplied to L26 through L29 and the bus switch 209, and it is written into the EVRAMc 208 (S15 in Fig. 4). On the other hand, the l-bit display data binarized by the comparator 217 is controlled by the lbVRAM 222 and written into the lbVRAM 221 and displayed on the display 32 by the display control circuit 2C (S16 in Fig. 4). The A&CC 205 monitors whether the VRAM address reached the total display pixel number, that is, whether one screen of data have been binarized and displayed (Sl7 in Fig. 4), and if it does not reach, it increments the VRAM address (Sl9 in Fig. 4) and the process returns to S8 to repeat the above steps until the VRAM address reaches the total display pixel number, when the binarization and display of one screen of display data are completed. The contents of the EVRAM's at this moment, that is at the end of the binarization of the first screen are all-"0" for the EVRAMa 206, 3/4 of the binarization error of the first screen for the EVRAMb 207, and 1/4 of the binarization error of the first screen for the EVRAMc 208. When the VRAM address reaches the total display pixel number, the A&CC 205 controls the bus switching circuit 209 to move the top EVRAMa 206 to the bottom in Fig. 2 and move up the EVRAMb 207 and EVRAMc 208. Namely, L25 is connected to L27, L26 is connected to L28, and L24 is connected to L29 (S18 in Fig. 4). Then, the process returns to S3 of Fig. 4 to write the display data of the second screen from the system to the NVRAM, and when the end of writing is detected, S4 to S19 of Fig. 4 are repeated. Since L25 is connected to L27, the display data on L31 for the binarization of the second screen is the sum of the display data of the NVRAMb 202 (or NVRAMa 201) of the second screen and the content of the EVRAMb 207 (3/4 of the binarization error of the first screen). Namely, (the display data (L31) for binarization of the second screen) = (display data of the second screen) + (binarization error data of the first screen) X 3/4 The contents of the EVRAM's at the end of the binarization of the second screen are all-"0" for the EVRAMb 207, (binarization error data of the first screen) X 1/4 + (binarization error data of the second screen) X 3/4 for the EVRAMc 208, and (binarization error data of the second screen) X 3/4 for the EVRAMa 206. When the VRAM address reaches the total display pixel number and the process for the second screen is completed, the bus switching circuit 209 switches to connect L26 to L27, L24 to L28 and L25 to L29 as it does in the switching for the first screen, and starts the binarization for the third screen. By repeating the above steps, the display data for the binarization of the M-th screen at time t M = (display data of M-th screen) + (binarization error data of (M-1)th screen) X 3/4 + (binarization error data of (M-2)th screen) X 1/4 The contents of the three EVRAM's at the end of the binarization of the M-th screen are: (1) all-"0" (2) (binarization error data of (M-1)th screen) X 1/4 + (binarization error data of M-th screen) X 3/4 (3) (binarization error data of M-th screen) X 1/4 Accordingly, when the data of the M-th screen is binarized, the binarization error data of the (M-1)th and (M-2)th screens at times t M-1 and t M-2 are spread. The binarization error generated when the data of the M-th screen is binarized at t M is spread up to the (M+l)th and (M+2)th screens at t M+1 and t M+2 . In accordance with the present invention, when data of one screen is converted to binary data by the error diffusion method, the binarization is conducted by taking the error data generated in the binarization of the previous screens into consideration, and the error data generated in the binarization of the current screen is spread to the subsequent screens. Accordingly, the density of the input data is preserved and the moire and the lumbrical noise are prevented, and high quality display image is attained. When the binarization error is corrected in one screen, the tonality is improved but the resolution power is lowered. In accordance with the present invention, however, since the binarization error spreads to a plurality of screens to be subsequently processed and the density is preserved, the tonality is excellent and the resolution is improved. While the display is LCD in the above embodiment, it may be a CRT display. While the binarization error is spread up to two ahead screens in the above embodiment, it may be spread to one ahead screen or three or more ahead screens. The weighing factors may be other than 1/4 and 3/4. While the data and the error data are simply summed in the above embodiment, they may be processed in other way. While the input data is monochrome in the above embodiment, three-color R, G, B input data may be processed respectively to attain color display. This may be attained by providing the circuit shown in Fig. 2 to each of the R, G, B input data. The LCD display apparatus is not limited to the ferroelectric liquid crystal display apparatus but it may be a TFT liquid crystal display apparatus. The gray level processing applicable to the present invention is not limited to the error diffusion method but a mean error minimizing method or mean density preservation method may be used. A method including a step of correcting an error generated when the input data is quantized may be used. While the input data is converted to the binary data in the above embodiment, where the LCD or the CRT is capable of displaying multi-level tonality of no smaller than 2, the input data may be quantized to multi-level data displayable by the LCD or the CRT and error data generated in quantizing may be spread to the data of the subsequent screens.

Claims: A display control unit comprising: quantizing means (212, 213, 215, 217) for quantizing image data of a M-th screen inputted at a first time into one of a plurality of displayable levels; calculation means (218) for calculating error data generated by the quantization of said quantizing means (212, 213, 215, 217); means for supplying the data quantized by said quantizing means (212, 213, 215, 217) to a display apparatus (32); and storage means (206, 207, 208) for storing the error data, characterized in that said quantizing means (212, 213, 215, 217) quantizes image data of a (M+1)th screen inputted at a second time by using the error data stored in said storage means (206, 207, 208). A display control unit according to Claim 1, characterized in that said quantizing means (212, 213, 215, 217) quantizes the image data to binary data or multi-level data, and said calculation means (218) calculates a difference beween the input image data and the binary data or the multi-level data. A display control unit according to Claim 1, characterized in that said storage means (206, 207, 208) include a first (206, 207, 208) memory for storing error data to be spread into the input image data of the (M+1)th screen inputted at the second time, and a second memory (206, 207, 208) for storing error data to be spread into image data of a (M+2)th screen inputted at a third time. A display control unit according to Claim 1, characterized in that said display apparatus (32) is a ferroelectric liquid crystal apparatus. A display control unit according to any of the preceeding claims, characterized in that said input image data are multi-level image data; said calculation means (218) calculates a binarization error generated in binarizing the multi-level pixel data; said storage means (206, 207, 208) stores the binarization error; and said quantizing means (212, 213, 215, 217) comprises data operation means (212, 213, 215) for operating input pixel data of M-th screen and the error data generated in binarizing at least a (M-1)th screen and stored in said storage means (206, 207, 208) and binarizing means (217) for binarizing the data from said data operation means (212, 213, 215) into two-level data. A display control method for quantizing input pixel data to multi-level or binary pixel data comprising the steps of: calculating a quantization error generated by quantizing the input pixel data; and storing the quantization error in quantization error storage means; characterised by the steps of: operating the input pixel data of M-th screen and the error data generated in quantizing at least (M-l)th screen and stored in said quantization error storage means; and quantizing the data generated in said operation step.

Inventors: SHIBAMIYA YOSHIKAZU, SHIBAMIYA, YOSHIKAZU, Shibamiya, Yoshikazu, c/o Canon Kabushiki Kaisha
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: G09G3
IPC codes: G09G3