Arithmetic apparatus

Abstract: An arithmetic apparatus in which while data read out of a memory (1) is shifted by means of a barrel shifter (3) by a shift bit number designated by data standing for an output signal of an inverter (5), data standing for an output signal of the barrel shifter (3) is inputted to a shift register (4) to thereby perform Viterbi decoding at a high speed.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an arithmetic apparatus incorporated in a digital signal processing processor adapted to perform Viterbi decoding of convolution ally coded data for error correction. Description of the Related Art In recent years, the digital signal processing processor (hereinafter abbreviated as DSP) has been highlighted as a processor used for incorporation into apparatus such as for example a portable telephone in accordance with a trend toward digitization in the mobile communication field. In data communication in mobile radio circuits, bit errors are generated frequently and an error correction processing must be carried out. One of error correction techniques uses Viterbi decoding for convolutional codes and the DSP is sometimes used for the error correction processing. The Viterbi decoding is for realizing maximum likelihood decoding of a convolutional code by repetition of simple processings of addition, comparison and selection and by trace back operation for final decoding of data. In the Viterbi decoding, each time that coded data (receiving data series) corresponding to one bit of information bits is obtained, inter-signal distances (metrics) of paths associated with individual states at that time are calculated to determine survivor paths. In a convolutional decoder having a constraint length of k, two paths representative of state transitions to a state S 2n (n being positive integer) at a certain time point from a state S n and a state (equation 1) at a one preceding time point extend as shown in Fig. 1. S n+2 (k-1) A path metric a is the sum of an inter-signal distance (branch metric) between an output symbol of each path coming into the state S 2n and the receiving data series and a path metric indicative of a total of branch metrics of survivor paths remaining until the state S n at the one preceding time point. Similarly, a path metric b is the sum of the distance (branch metric) between the output symbol of each path coming into the state S 2n and the receiving data series and a path metric indicative of a total of branch metrics of survivor paths remaining until the state (equation 1) at the one preceding time point. The path metrics a and b coming into the state S 2n are compared to select one of them, which is smaller than the other, as a survivor path. Each of the processings of path metric determining addition, path metric comparison and path selection is carried out for 2 k-1 states at each time point. Further, a history as to which path is selected in path selection needs to be left in the form of a path select signal PS[S i ], (i = 0 ∼ {2 k-1 -1}). When a suffix of a state at the one preceding time point with which a selected path is associated is smaller than suffixes of the other state at the one preceding time point, PS[S i ] = 0 is held but when not smaller, PS[S i ] = 1 is held. Upon final decoding through trace back operation, survivor paths are traced back on the basis of select signals to perform decoding of data. The path associated with the state S 2n (n being positive integer) at the certain time point is traced back until the state S n or state (equation 1) at the one preceding time point on the basis of the select signal PS[S 2n ], as shown in Fig. 2. Generally, a state at the one preceding time point can be expressed on the basis of a state Si and a path select signal PS[S i ] pursuant to equation 2. S j, j = 1 2 + PS[S i ]·2 (k-1) In that case, when a convolutional code with tail bits is used, the path select can be determined as decoded data. Fig. 3 is a block diagram showing an arithmetic apparatus incorporated in a conventional DSP for Viterbi decoding. In Fig. 3, a data memory 1 stores path metrics, path select signals and decoded data. A barrel shifter 3 shifts data read out of the data memory 1. A first bus 6 is coupled to the data memory 1 to effect supply of data and storage of operation results. A first register 7 holds the number of shift bits (a shift bit number) by which the barrel shifter 3 shifts the data. An arithmetic and logic operation unit (hereinafter simply referred to as ALOU or ALU) 8 performs arithmetic and logic operations. A first latch 9 temporarily stores a value of the left input of the ALOU 8. A second latch 10 temporarily stores a value of the. right input of the ALOU 8. A plurality of second registers 11 and 12 temporarily store operation results. A second bus 13 effects data supply from the register 11 or 12. The number of shift bits for the barrel shifter 3 is represented by the two's complement system, and right shift is carried out when the shift bit number is positive but left shift is carried out when negative. In the arithmetic apparatus constructed as above, when coded data subject to convolutional coding ending in a trail bit undergoes Viterbi decoding, trace back operation is carried out as will be described below. Conditions therefor are such that the constraint length of a convolutional code is k, the number of bits of coded information is n, and each of the data memory 1,first bus 6, second bus 13, first latch 9, second latch 10, ALOU 8 and second registers 11 and 12 has a bit width of 2 k-1 bits. Further, path select signals PS t [S i ], (t=0∼{(n-1)+(k-1)}, i=0∼{2 k-1 -1}) are packed in one word in the form of a path memory (equation 3) and stored in the data memory in the form of PM[t], (t=0∼{(n-1)+(k-1)}). PM[t] = {PS t [S 2 (k-1) -1 ], PS t [S 2 (k-1) -2 ], ... , PS t [S t ],PS t [S 0 ] Decoded data Y[i], (i=0∼{n-1}) is stored in the data memory 1 in a unit of one word for one bit. The trace back operation is divided into steps which will be described below. (1) A fixed value [0] is stored in the second latch 10. The ALOU 8 stores the value of the second latch 10 as it is in the second register 11. Thus, "The operation starts from state 0." is fulfilled.In the following steps (2) to (10), i is counted down from {(n-1)+ (k-1)} to (k-1) to repeat the operations by n. (2) The value of the second register 11 is stored in the first latch 9 through the second bus 13. The ALU determines a two's complement of the value of the first latch 9 and stores it in the second register 12. (3) The value of the second register 12 is stored in the first register 7 through the first bus 6. Thus, "This value is a shift bit number for selection of the next path select signal." is fulfilled. (4) A path memory PM[i] is read out of the data memory 1, shifted by means of the barrel shifter 3 by a shift bit number designated by the first register 7, and stored in the second latch 10. The ALOU 8 stores the value of the second latch 10 as it is in the second register 12. Thus, "A path select signal to be selected is put to the least significant bit (LSB)." is fulfilled. (5) The value of the second register 12 is stored in the first latch 9 through the second bus 13 and a fixed value [1] is stored in the second latch 10. In the ALOU 8, the values of the first and second latches 9 and 10 are ANDed and a resulting product is stored in the second register 12. Thus, "Only the LSB is extracted." is fulfilled. (6) The value of the second register 12 is stored as decoded data Y[i-(k-1)] in the data memory. Thus, "The LSB is the decoded data." is fulfilled. (7) A fixed value [k] is stored in the first register 7. (8) The value of the register 12 is stored in the first latch 9 through the second bus 13, and an output obtained by shifting the value of the second register 12, sent through the first bus 6 to the barrel shifter 3, by means of the barrel shifter by a shift bit number designated by the first register 7 is stored in the second latch 10. In the ALOU 8, the values of the first and second latches 9 and 10 are ORed and a resulting sum is stored in the second register 12. (9) A fixed value [-1] is stored in the first register 7. (10) An output obtained by shifting the value of the second register 12 by means of the barrel shifter 3 by a shift bit number designated by the first register 7is stored in the second latch 10. The ALOU 8 stores the value of the second latch 10 as it is in the register 12. Thus, "The state at the one preceding time point is calculated through steps (6) to (10)." is fulfilled. In the above conventional arithmetic apparatus, by carrying out operations by using the barrel shifter 3 and ALOU 8 in combination in this manner, the trace back operation in Viterbi decoding of n-bit information bit can be accomplished through (9n+1) steps. When the operation bit width is smaller than the state number 2 k-1 or the convolutional code does not end in the trail bit but is used continuously, trace back operation can also be carried out in a similar way. In the above conventional arithmetic apparatus, however, many operation steps are needed to determine the state at the one preceding time point and decoded data is stored in a unit of one word for one bit, raising a problem that the capacity of the data memory is increased. "Architectural design and realization of a single-chip Viterbi decoder", Biver M. et al, Integration, the VLSI Journal, October 8, 1989, Elsevier Science Publishers B.V., Amsterdam, discloses a trace back circuit for a Viterbi decoder. In said trace back circuit, a selection of a corresponding MSB of a previous state is performed by a 16:1 multiplexer. A further arithmetic apparatus is known from US-A-4,797,175. In said known apparatus, the output signal of the barrel shifter is inputted into the address input of the memory. A serial to parallel circuit receives output signals from an add-compare-select circuit and is adapted to write data into the memory. US-A-4,939,684 discloses a simplified processor for digital filter applications including 2 barrel shifters which receive shift instructions from a program memory. The present invention intends to solve the conventional problems and it is an object of the present invention to provide an excellent arithmetic apparatus which can perform operations through a reduced number of operation steps and by using a data memory of smaller capacity. According to the invention, the above object is achieved by an arithmetic apparatus according to the claim. Accordingly, in accordance with the present invention, the state at one preceding time point can be determined by merely inputting a path select signal selected by shifting a path memory read out of the data memory by means of the barrel shifter, the next shift bit number for the barrel shifter can be determined, and the path select signal stored in the shift register can be determined as decoded data, so that trace back operation in Viterbi decoding can be carried out through a reduced number of operation steps and by using the data memory of smaller capacity. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a state transition diagram (trellis diagram) showing paths of state transition in a convolutional coder in Viterbi decoding. Fig. 2 is a state transition diagram (trellis diagram) showing trace back of paths upon trace back operation in Viterbi decoding. Fig. 3 is a block diagram showing a configuration of a conventional arithmetic apparatus for Viterbi decoding. Fig. 4 is a block diagram showing a configuration of an arithmetic apparatus for Viterbi decoding according to an embodiment of the invention. Fig. 5 is a block diagram showing a configuration of an arithmetic apparatus for Viterbi decoding according to another embodiment of the invention. Fig. 6 is a block diagram showing a configuration of an arithmetic apparatus for Viterbi decoding according to still another embodiment of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 4 is a block diagram showing a configuration of an arithmetic apparatus for Viterbi decoding according to an embodiment of the invention. Referring to Fig. 4, a data memory 1 stores path metrics, path select signals and decoded data. A bus 2 is coupled to the data memory 1 to effect supply of data and storage of operation results. A barrel shifter 3 shifts data read out of the data memory 1. A shift register 4 can receive a shift input of specified one bit of an output of the barrel shifter 3 and it performs, through the bus 2, data loading from the data memory 1 or data storage into the data memory 1. An inverter 5 inverts a specified register value of the shift register 4 to produce a shift bit number applied to the barrel shifter 3. The shift bit number of the barrel shifter 3 is represented by the two's complement system, and right shift is carried out when the shift bit number is positive but left shift is carried out when negative. In the shift register 4, the most significant bit (MSB) lies on the shift input side. In the arithmetic apparatus constructed as above, when coded data subject to convolutional coding ending in a trail bit undergoes Viterbi decoding, trace back operation is carried out as will be described below. Conditions therefor are such that the constraint length of a convolutional code is k, the number of bits of coded information is n, and each of the data memory 1, bus 2 and shift register 4 has a bit width of 2 k-1 bits. The MSB of an output of the barrel shifter 3 is inputted as a shift input to the shift register 4, and the inverter 5 inverts upper (k-1) bits of the shift register 4 and adds the MSB, which is 0 (zero), to its output (k-1) bits to produce k bits which is used as a shift bit number for the barrel shifter 3. Further, path select signals PS t [S i ], (t=0∼{(n-1)+(k-1)}, i=0∼{2 k-1 -1}) are packed in one word in the form of a path memory (equation 3) and stored in the memory lin the form of PM[t], (t=0∼{(n-1)+(k-1)}). Decoded data Y[i], (i=0∼{n-1}) is packed in a unit of one word of 2 k-1 bits and stored in the data memory 1. The trace back operation is divided into steps which will be described below. (1) A fixed value [0] is stored in the shift register 4. Thus, "The operation starts from state 0." is fulfilled.In the following steps (2) and (3), i is counted down from {(n-1)+(k-1)} to (k-1) to repeat the operation by n. (2) A path memory PM[i] is readout of the data memory 1, shifted by means of the barrel shifter 3 by a shift bit number designated by the output of k bits of the inverter 5, and the MSB of the output of the barrel shifter 3 is inputted as a shift input to the shift register 4. Thus, "A path select signal to be selected is put to the MSB.", "Upper (k-1) bits after shift input indicates the state at one preceding time point." and "At the same time, inversion of the upper (k-1) bits provides the basis for the bit shift number for selection of the next select signal." are fulfilled. (3) Each time that 2 k-1 bits are decoded, the contents of the shift register 4 is stored in the data memory. Thus, "The selected path select signal is the decoded data." is fulfilled. As described above, in accordance with the present embodiment, the selection of path select signal and the calculation of the state at one preceding time point can be carried out in step (2) and therefore, the trace back operation in Viterbi decoding of n-bit information bit can be accomplished through {n+(n/2 k-1 )+1} steps. Figs. 5 and 6 are block diagrams showing configurations of arithmetic apparatus according to other embodiments of the invention. In Figs. 5 and 6, the configuration shown in Fig. 4 is added with a first register 7, an ALOU 8, a first latch 9, a second latch 10, second registers 11 and 12 and a second bus 13 which are necessary for performing other processings than the trace back operation in Viterbi decoding. When the operation bit width is smaller than the state number 2 k-1 or the convolutional code does not end in the trail bit but is used continuously, trace back operation can also be carried out in a similar way.

Claims: An arithmetic apparatus for performing the trace back operation in a Viterbi decoder, comprising: a memory (1) for storing trellis selection bits; a barrel shifter (3) arranged to be loaded with data of said memory (1); a shift register (4) with an input connected to the output of said barrel shifter (3), which provides bits to be shifted into said shift register (4); a data inverting unit (5) for inverting data output by said shift register (4) and for providing a shift amount input to said barrel shifter (3), whereas the arithmetic apparatus is arranged so that the shift operation of said barrel shifter (3) is performed while data from the barrel shifter is shifted into said shift register (4).

Inventors: ASANO NOBUO, ISHIKAWA TOSHIHIRO, OKAMOTO MINORU, UESUGI MITSURU, ASANO, NOBUO, ISHIKAWA, TOSHIHIRO, OKAMOTO, MINORU, UESUGI, MITSURU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1993
Main classification: H03M13
IPC codes: H03M13, G06F17