PERFORMANCE MONITORING AND TEST SYSTEM FOR A TELEPHONE NETWORK

Abstract: An access, monitor and test system (170) for a telephone network. The system (170) provides selective, and hitless, bit overwrite in any of the embedded channels, for example, DS1, DS0 and subrate, in a signal (134), for example, DS3. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange (252) in conjunction with the recombiner (458) of the present invention. The present invention further includes a lookahead reframer (474) for framing to the DS3 signal (134). The present invention also includes a facilities data link (FDL) handler (254, 1068) for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare (470) is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization, and also provides alarm correlation and hierarchical event filtering. A portion of the relative synchronization method is the auto-search reference select sequence (1168). A portion of the system for correlating performance monitoring and testing of a channel is the alarm correlation and filter process (1270).

Description: PERFORMANCE MONITORING AND TEST SYSTEM FOR A TELEPHONE NETWORK Background of the Invention * Field of the Invention The present invention relates to telephone networks, and * more particularly to a system and method for accessing, 10 monitoring and testing a telephone network. Description of the Related Technolocry The telephone industry has changed drastically since the divestiture of the Bell System. Today, seven regional Bell Operating Companies (RBOCs) and independent telephone 15 companies provide local telephone service within 166 Local Access Transport Areas (LATAs) . These companies are forced to rely on interexchange carriers such as AT&T, MCI and Sprint for transmission of calls from one LATA to another. The responsibility for quality and performance of the telephone 20 circuit is thus split between local telephone companies and interexchange carriers. RBOCs are under pressure for financial performance as independent companies . With rates restricted by utility commissions, and facing rising costs and new competition with 25 restrictions on transmission of calls beyond LATA boundaries, telephone companies find themselves faced with rapid introduction of new technology, smarter business customers, and antiquated network maintenance systems. Demand for information transmission increased 30 dramatically during the 1980s. At the beginning of the decade most data transmission systems interfaced a predominantly analog network through relatively low speed modems. Those desiring "high speed" transmission generally opted for the 56 kbps rate of the digital data system (DDS) . »; 35 Considerable pressure for increases in such transmission • * rates came from the desire to take advantage of the increasing capabilities and computation speeds of computers and other business systems . Improvements in transmission technology during the decade fueled the momentum of the increase in transmission rates. The replacement of copper cables with glass fiber expanded the transmission capacity of outside plants many times over. At the same time, improvements in electronics and coding algorithms yielded terminal equipment designed to take advantage of the enormous increase in bandwidth which accompanied the conversion to fiber optics. In the absence of a standard, virtually all lightwave vendors chose DS3 (44.736 Mbps) as the interface between the lightwave terminal and the network. Figure 1 illustrates the prior art North American Digital Hierarchy having a DSO (64 kbps) level 102, a DSl (1.544 Mbps) level 104, a DS2 (6.312 Mbps) level 106 and a DS3 (44.736 Mbps) level 108. This hierarchy is defined by ANSI TI.102-1987 - "Digital Hierarchy, Electrical Interfaces", The American National Standards Institute, Inc., New York, 1987. DS2 is important as a link between DSl and DS3. Even though there is little growth in DS2 as a transport medium, the DS2 level exists in every muldem (multiplexer/demultiplexer) or other network element which must interface DSl and DS3 signals. Although DSO is essentially confined to digital signals, reference to analog voice frequency signals is included in Figure 1 because of widespread interfacing of such signals to the DSl level of hierarchy by digital channel banks. The transition of telecommunications into the 1990s will thus occur with the DS3 rate used almost universally for interfaces within the network. DSl transmission between customers and operating companies is now commonplace, and an ever increasing number of customers are seeking to interface with service providers and with other end users at even higher rates. The DS2 rate, seemingly a logical intermediate step between DSl and DS3, has proved to be uneconomical for transport except in certain special cases. Thus, DS3 is proving to be the underlying building block for high bandwidth, light signals. Figure 2 is a prior art, simplified model of a lightwave network 120 showing four example network carriers (Carrier A, Carrier B, Carrier C and Carrier D) and how a DSO level line 130, a DSl level line 132, a DS3 level line 134 and a fiber optic (light) line 136 are used to interconnect a customer X 140 to a customer Y 142. The equipment at the customer premise or site 140 and 142 could be, for example, a telephone, a facsimile modem or a data modem. A multiplexer/demultiplexer or channel bank 144 is used to multiplex 24 DSO level signals on the line 130 into one DSl level signal on the line 132. In this model 120, a Ml/3 muldem 146 is used to multiplex 28 DSl level signals on the line 132 into one DS3 level signal on the line 134. The DS3 level signals on the line 134 are further combined by Carrier A using a lightwave transport multiplexer 122 into a fiber optic signal on the line 136. In this model 120, three Central Offices 152, 154 and 156 are used, with the middle Central Office 154 having three carriers cross-connected at the DS3 level by use of a cross-connect 158. A long distance call from customer X 140 to customer Y 142 involves many levels of multiplexing and many transport carrier handoffs. Carrier A is the local operating company of customer X 140, and owns Central Offices 152 and 154. Carrier B and Carrier C are long distance carriers, and Carrier D is the local operating company that owns Central Office 156 and services customer Y 142. A call from customer X 140 to customer Y 142 involves three central offices and three transport carriers . As the call traverses the network 120, it may be processed by several network elements, such as channel banks 144, Ml/3 muldems 146, 128, and lightwave transport multiplexers 122, 126 with each element having its own surveillance techniques. Maintenance and billing problems are not uncommon with this interaction. Most network elements incorporate some form of monitoring, test, and control of the data that they process. However, none of these options supports the continuous monitor or test access of DS3 and all embedded channels. Although the cost of bandwidth has plummeted to the extent that it no longer worries facility planners as it did in previous decades, the move to DS3 is not without its costs. Chief among them are the lack of convenient and economical test access to lower rate channels embedded in the DS3 bit stream and the lack of surveillance systems designed to take advantage of the performance data embedded in the DS3 formatted signal. DS3 (and to a lesser extent DSl) signals carry large amounts of data per unit time and represent a considerable financial investment on the part of the end user, for whom bandwidth is not as inexpensive as it has become for the operating company facility planner. The operating company using DS3 runs the risk of a substantial outage in the case of a crippling impairment or total failure of such high-speed digital facilities. Those who manage the DS3 facilities of both end users and service providers are thus quite interested in the performance of the digital links in their networks. They are not satisfied to let the performance information embedded in the bit streams they deal with simply pass on by without extracting data which can be quite useful in managing the network and in minimizing the costly impact of service outages. It is possible to acquire a DS3 signal at the monitor jack of a DSX-3 cross-connect panel and demultiplex from the DS3 whatever subsidiary signals are desired. Such signals may then be patched into portable test equipment or routed to test systems for analysis. There are many test sets available which will analyze signals extracted at any rate from DSO to DS3. This technique, however, requires manual access to implement the patching and allows the use of the test and/or surveillance equipment on only one DS3 at a time. Portable test arrangements of this type do not generally allow the insertion of test signals or data into outgoing channels of a DS3 bit stream without interrupting the other services carried by the same DS3. A digital cross-connect system (DCS) might be considered for use as a test access vehicle in the DS3 network. The versatile and sophisticated switching capabilities of the DCS make it a costly access. There are, in addition, impairments associated with the use of DCS which make it inadvisable to scatter such systems throughout the network at all points requiring surveillance or test access . Among the impairments introduced by a DCS are delay, a certain amount of which is necessary to synchronize incoming and outgoing frame structures, and robbed-bit writeover distortion, the latter difficulty occurring only when switching down to the DSO rate is provided. To improve service while cutting costs, RBOCs have turned from portable test equipment in the hands of field craftspeople, to permanently installed test systems connected to a central network management center or operations support system (OSS) ; and from repair actions in response to a trouble report from customers, to proactive network performance monitoring and preventative maintenance. Existing equipment available to telephone companies provides only a small portion of the functionality needed by telephone companies and is quite expensive. In a telephone network, a synchronization monitoring function compares the clock frequency of a DSl signal under test to a reference DSl signal . The reference signal can be any (embedded or direct interface) DSl in the test system or an external DSl based reference received through a test system port. Synchronization measurements are important because frequency offsets in the network can result in "slips", which are additions or deletions of a DSl subframe. If all clocks and signal delays were perfectly stable, telephone network timing would not be a problem. Only an initial calibration on the clocks would then be necessary so that they all would operate at the same rate. The telephone network would operate at the same rate indefinitely without timing faults. However, physical devices are not perfect and thus synchronization techniques are utilized. But even with presently known synchronization methods, frequency offsets may still cause problems. Thus it would be a significant advantage for a monitor function to accurately and quickly predict the occurrence of slips in the network. It would also be desirable to compare the two directions of a selected DSl signal to determine if the bi-directional paths are synchronized to each other or the external reference. Furthermore, a need exists to establish a threshold level for the allowed number of slips in a specified time period, and when the threshold is exceeded, to send an autonomous alarm message to the network management center where the appropriate action can be taken. Performance monitoring is performed on bi-directional or through DS3 circuits or channels and all of their constituent sub-circuits commonly known as DS2s and DSls. These DS3 , DS2 and DSl circuits are organized in the network in a hierarchical structure, with seven DS2s per DS3 and four DSls per DS2. Pursuant to Bellcore TR-TSY-833 and ANSI T1M1.3 91 specifications, each circuit is monitored for several network disturbance conditions. A disturbance can be a failure, which leads to a loss of service, or a defect, which leads to a degraded state. These disturbances include Loss of Signal (LOS) , Loss of Frame (LOF) , Alarm Indication Signal (AIS) , Yellow Alarm, and so forth, and are issued as autonomous events to the controlling operations support system (OSS) , typically via a 9600 baud link using Bellcore TL1 protocol. In the event of a DS3 level disturbance, the probability of a subordinate or embedded circuit failure is very high. In this scenario, a significant amount of "redundant" information from embedded DS2 and DSl circuits has the potential of being generated in the form of a flood of autonomous events towards the OSS. In essence, this constituent information is of little value, as only the highest level defect is of concern. In order to provide the OSS with the most pertinent information in identifying the fault, a hierarchical filtering mechanism that reduces the amount of redundant information issued in the event of a higher (DS3 or DS2) level fault would be of great utility. Consequently, there is a need for DS3 surveillance and testing using a system which is essentially transparent to in- service DS3 lines and paths, which provides non-intrusive surveillance and performance monitoring, which can provide intrusive test access when required and which is economical enough to install at all points requiring DS3 surveillance or test access. There is also a need for network managers to have access to comprehensive performance data embedded in the DS3 format in order to make informed decisions about the operations of their DS3 networks. Summary of the Invention The present invention provides an integrated access, performance monitoring and test system to help companies efficiently manage their high speed telecommunications network. The access system allows telephone companies to continuously monitor the performance of all circuits from their network management center, identifying degradation of service before a service-affecting outage occurs. All DS3 signals passing through the system are monitored for performance indicators specified by Bellcore transmission requirements. The presently preferred access system is essentially transparent to the DS3 network except for the injection of an absolute delay of less than 10 microseconds unless transmitting an alarm signal. The system interacts with circuits embedded in the DS3 signal by transmitting outgoing information on any such circuit without affecting transmission on the other circuits of the DS3. In one aspect of the present invention, there is a maintenance system for a signal having a plurality of embedded communication channels, the system comprising means for receiving the signal, means for simultaneously accessing any one or more of the channels, and means for performance monitoring the accessed channels. In another aspect of the invention, there is a performance monitoring system for a signal having embedded channels, the system comprising a shared resource for providing access to the embedded channels, means for continuously monitoring a channel in the signal, the channel having a plurality of multiplexed channels, and means for continuously monitoring the multiplexed channels simultaneously with the channel . In another aspect of the invention, there is a system for measuring relative synchronization between a plurality of embedded channels in one or more signals, the system comprising means for simultaneously accessing the embedded channels wherein each embedded channel comprises a plurality of bits, means for counting the bits in the accessed embedded channels, and means for comparing a bit count in one of the embedded channels with a bit count in another of the embedded channels. In another aspect of the invention, there is a method of measuring synchronization of a set of channels in a signal, the method comprising the steps of measuring the frequency of each channel, and comparing the frequency of each channel to obtain one or more relative frequency measurements. In yet another aspect of the invention, there is a method of adaptively selecting an internal reference from a set of channels in a signal, the method comprising the steps of selecting a pool of channels, choosing a reference channel from the pool so as to normalize frequency measurement results on all other channels, and measuring the frequency of each channel in the signal relative to the reference channel . In another aspect of the present invention, there is a system for correlating performance monitoring and testing of a channel having a plurality of embedded channels, comprising means for detecting a disturbance in the channel, means for detecting a disturbance in one of the embedded channels, means for correlating the disturbance in the channel with the disturbance in the embedded channel, and means for generating an alarm for the disturbance including means for blocking the alarm of the embedded channel disturbance when the embedded channel disturbance correlates to a disturbance of the channel . Brief Description of the Drawings Figure 1 is a diagram of the North American digital hierarchy used in a telephone network accessed by the present invention; Figure 2 is a block diagram of an exemplary simplified network model; Figure 3 is a block diagram of an exemplary simplified network model having a set of DS3 signal access systems of the present invention shown as Integrated Transport Access Units (ITAUs) ; Figure 4 is a functional block diagram of the presently preferred access system architecture according to the present invention; Figure 5 is a system block diagram of the access system shown in Figure 4; Figure 6 is a block diagram of the DS3 interface module shown in Figure 5; Figure 7 is an operational flowchart of the access system shown in Figures 4 and 5; Figure 8 is an input/output (I/O) diagram of the Drop and Insert (DAI) circuit shown in Figure 6; Figures 9 is a high level block diagram of the DAI circuit shown in Figure 8; Figure 10a is a detailed block diagram of the DAI circuit shown in Figure 8; Figure 10b is a block diagram of the DAI M23 Demultiplexer subcircuit shown in Figure 10a; Figure 10c is a block diagram of the DAI M12 Demultiplexer subcircuit shown in Figure 10a; Figure lOd is a block diagram of the DAI DSl Monitor subcircuit shown in Figure 10a; Figure lOe is a block diagram of the DAI Recombiner subcircuit shown in Figure 10a; Figure lOf is a block diagram of the DAI Processor Interface subcircuit shown in Figure 10a; Figure 11 is a block diagram of the pseudo DS2 insert portion of the DAI recombiner shown in Figure 10e; Figure 12 is a diagram of a DS3 Framing Format for the DS3 level shown in Figure 1; Figure 13 is a diagram of DS3 Overhead Bits for the DS3 level shown in Figure 1; Figure 14 is a diagram of DS3 C-bit Parity Overhead Bits for the DS3 level shown in Figure 1; Figure 15a is a block diagram of the lookahead framer portion of the DAI M23 Demux shown in Figure 10b and Figure 15b is a diagram associated with a pyramid shift register of Figure 15a; Figure 16 is a functional block diagram of a portion of the access system shown in Figure 4; Figure 17 is a block diagram of the Pulse Code Modulation (PCM) Highway shown in Figure 5; Figure 18 is a timing/bit format diagram of a set of PCM Highway time slots; Figure 19 is a timing/bit format diagram of the PCM Highway transmit status timing providing details of two time slots shown in Figure 18; Figure 20 is an input/output (I/O) diagram of the asynchronous Time Slot Interchange (TSI) circuit shown in Figure 6; Figure 21a is a top level block diagram of the asynchronous TSI circuit shown in Figure 20; Figure 21b is a block diagram of the TSI Facilities Data Link (FDL) subcircuit shown in Figure 21a; Figure 21c is a block diagram of the TSI Frequency Counter subcircuit shown in Figure 21a; Figure 21d is a block diagram of the TSI Subrate Handler subcircuit shown in Figure 21a; Figure 22 is a timing diagram of the interface between the TSI and DAI; Figure 23 is a block diagram of the Facilities Data Link (FDL) microcontroller interface shown in Figure 6; Figure 24 is a block diagram of the TSI FDL Handler logic shown in Figure 23; Figure 25 is a timing diagram of the FDL interface timing in reference to Figures 23 and 24; Figure 26 is a block diagram of the DS3 data paths for a pair of DS3 interface modules shown in Figure 5; Figure 27 is a block diagram of the DS3 protection of the access system, including the DS3 monitor module shown in Figure 5; Figure 28 is a block diagram of the bit for bit compare portion of the DAI circuit shown in Figure 10a; Figure 29 is a block diagram of the DS3 data path delay adjustment portion of the DS3 Linear Interface (LI) circuit shown in Figure 6; Figures 30a and 30b illustrate a TI bit sequence before and after a controlled slip; Figure 31 is a diagram of a DSl Superframe Format for the DSl level shown in Figure 1; Figure 32 is a system block diagram of the access system shown in Figure 4, including a reference clock path; Figure 33 is a flowchart of an auto search reference select sequence performed by the administration processor module shown in Figure 32; Figure 34 is a high level block diagram of an event and performance monitor hierarchical filtering process of the access system shown in Figures 4 and 5; Figure 35 is a flowchart of a per alarm scan sequence corresponding to the alarm correlation and filter process shown in Figure 34 ; and Figure 36 is a flowchart of a per circuit scan sequence corresponding to the alarm correlation and filter process shown in Figure 34. Detailed Description of the Preferred Embodiments Reference is now made to the drawings wherein like numerals refer to like parts throughout. For convenience, the following description will be outlined into the following six principal sections: System Overview, The DS3 Drop and Insert (DAI) Circuit, The Asynchronous Time Slot Interchange (TSI) Circuit, The Protect Path, Relative Synchronization, and Alarm Correlation. I. SYSTEM OVERVIEW As shown in Figure 3, the DS3 signal access, monitor and test system 170, also referred to as an Integrated Transport Access Unit (ITAU) , is installed as an integral part of the fiber optic and microwave radio transmission systems of the Regional Bell Operating Companies (RBOCs) and long distance carriers. The simplified network model 120 of Figure 2 is enhanced in Figure 3 by the addition of the DS3 signal access system 170 at several example positions in the network model 168. At Central Office 152, the DSl signals 132 are multiplexed by the Ml/3 muldem 146 into the DS3 signal 134 which becomes the input for the access system 170a. The access system 170 can accept the range from one DS3 signal up to a maximum of 96 DS3 signals as inputs, with the number of output DS3 signals being the same number as input signals. Actually, the access system 170 is bi-directional and the network itself is bi-directional in order to handle two-way voice or data communication. The access system 170a outputs, including the DS3 level line 134', are combined by Carrier A using a lightwave transport multiplexer 122 into a fiber optic signal on the line 136 or alternatively, into a microwave signal by other known means to be transmitted to Central Office 154. At Central Office 154, for example, Carrier A demultiplexes the fiber optic signal 136 into multiple DS3 level signals, via the demultiplexer 122, which are used as inputs to another access system 170b. Similarly, Carrier B and Carrier C can provide DS3 level signals to access systems 170c and 170d, respectively. The outputs of the three access systems 170b, 170c and 170d cross-connect at the point 158. A final access system 170e could be installed as shown in Central Office 156 between Carrier C and Carrier D. Interfacing at the DS3 rate, the access system 170 is capable of regeneration of DS3 data, and provides one-for-one protection, using a protection path scheme, to guarantee high reliability as will be shown hereinbelow. Delay through the access system 170 is nominal (less than 10 microseconds) so that the system can be used at multiple network locations, as shown in Figure 3, with minimal effect on the end to end DS3 path delay. The access system 170 provides continuous performance monitoring of the DS3 channel 146 and all embedded DSl circuits 132. As an embedded maintenance system, performance information is monitored and collected without invoking data disruptions. The access system 170 provides access to any embedded channel in the DS3 bit stream without causing service disruptions to the other channels, i.e., hitless access. The access system 170 supports simultaneous, hitless access to: multiple DSl signals for High Capacity Digital Service (HICAP or HCDS) testing; multiple embedded DSO and subrate channels for testing and measurement of voice frequency (VF) , digital data service (DDS) , and signalling; and DSl and DSO craftsperson interface for test access digroup (TAD) and facility access digroup (FAD) . Subrate channels are subchannels of the DSO DDS network for data applications such as a modem. Subrate DS0A can have one subcustomer, while subrate DS0B can have multiple customers, depending on the data rate used. Transport carriers, such as carriers 122, 124, 126 and 128, have the freedom to place the access system 170 anywhere in the network. Applications for the access system 170 include use at the boundary between two carriers, for special services and DDS hubs, and at manned, unmanned or remote central offices. Control center interface with the access system 170 is provided through industry standard operations support system communication protocols as will be explained below. Operations support system (OSS) is also known as operations system (OS) . Figure 4 is a functional block diagram illustrating the architecture of the presently preferred access system 170. The access system 170 of the present invention connects in- line to as many as 48 bi-directional DS3 signals or 96 one-way DS3 signals, such as, for example, the DS3 signal fed across the line 134, to provide: continuous non-intrusive performance monitoring of DS3 and embedded DSl channels; non-intrusive performance monitoring of DSO and embedded channels, on demand; hitless access to multiplexed DSl, DSO and subrate channels; intrusive or non-intrusive testing of DSl, DSO and subrate channels; and an OS interface for reporting and control. In general, the performance monitoring function stores notable events and calculates statistics such as error rates. Among others, the parameters and events monitored at the DS3 level by the access system 170 include: frame format, bipolar violations (BPV) and loss of signal (LOS) . DS3 level statistics, including, for example, frame format status, F bit error count and frame parity error count, are stored and reported to the OS. Similarly, DSl level performance monitoring and statistics, and TAD/FAD performance monitoring are stored in memory by the system 170. The access system 170 also provides hitless monitor or split access to all DSl, DSO and subrate channels in support of pre-service testing, verification or sectionalization of faults, and verification of repairs. A monitor access permits the system 170 to "listen" to the accessed channel as it passes through the system undisturbed. Establishing or tearing down a monitor access does not cause disruption to the channel or to other components of the bit stream. A split access breaks the normal through path of the channel and the received data from each direction has data inserted into the outgoing transmit channels. Lastly, the access system 170 provides non-intrusive test capabilities for extracting DSl, DSO and subrate channels from received DS3 and DSl bit streams without affecting the transmission of the same information through the system. Intrusive testing allows the writing of information into outgoing DSl, DSO and subrate channels embedded in the DS3 bit stream. For example, intrusive tests include HCDS and DDS reconfiguration commands, looping commands, test patterns and voice frequency test tones, and complex waveforms such as those required for P/AR tests. Again referring to Figure 4, the DS3 signal received on the line 134 is fed through a receiver or regenerator 172, which outputs a DS3 signal having the same digital information, then through a combiner 174, and through a transmitter or regenerator 176. A primary path relay 178, shown to be closed, allows the DS3 signal to be output from this primary path across the output line 134' . Simultaneously, the incoming DS3 signal is fed through two regenerators 172', 176', but a second relay, termed the protect path relay 178' is open thus preventing this protect path from feeding its DS3 signal to the output line 134' . The relays 178, 178' are operated cooperatively, as will be further discussed below, to apply the signal from only one of the two paths to the output line 134' thus providing fail-safe transmission of the DS3 signal through the access system 170. The performance monitoring functions of the access system, as discussed hereinabove, are conducted in the functional block indicated in Figure 4 at 180, which receives the DS3 signal from the primary path. Access and test functions are accomplished by feeding the DS3 signal from the primary path to a DS1/DS0 router 182 which selectively routes embedded channel data to one or more DSl test resources 184 or DSO test resources 186. Since DSl and DSO test systems are well-known, the function of the test resources 184, 186 will not be further discussed herein. A TAD/FAD interface line 188 for carrying a DSl signal also connects to the router 182 so that the access system 170 can be used as a remote test unit or as a local test unit for bit streams demultiplexed from incoming DS3 signals with external test equipment . Note that tests requiring bit overwrite communicate data via the router 182 to the combiner 174 where bits are selectively overwritten in " the DS3 signal. Performance monitoring, access and test are controlled by a system controller 190 via a High Level Data Link Control (HDLC) bus or link 192 connected to the performance monitor 180, DS1/DS0 router 182 and the DSl and DSO test resources 184, 186. The system controller 190 also communicates with a user interface subsystem 194 that provides communication to an OS (not shown) across a line 196 for control from remote locations. The user interface decodes messages sent in Transaction Language 1 (TL1) , generally used by modern mechanized systems, or Program Documentation System (PDS) formats. Man-Machine Language (MML) is used to interface with craft technicians. Thus, a local telephone company, e.g., Bell South, or interexchange carrier, e.g., MCI, can gain immediate access to the DS3 and embedded channels by using the access system 170 of the present invention. Figure 5 is a system block diagram of the presently preferred access system 170. The access system 170 integrates monitor, access, and test functions into one system having three shelves of hardware. A fully configured access system 170 supporting 48 DS3s would be housed in two equipment bays, each bay supporting 5 shelves; one Administration Shelf 200, eight High Speed Interface Shelves 202, and one Test Resource Shelf 204. The access system 170 is designed for operation in a central office environment. The access system 170 is modular in design, supporting the network as it expands and enabling easy integration of hardware and software capabilities. Each hardware module contains a processor complex, which will be described hereinbelow, that provides data collection, control, and communication to the central administration processor 190. Design of the access system 170 was based on the philosophy that the addition of a network maintenance element should not degrade network reliability. To achieve this goal, the access system 170 carefully monitors its circuitry and software functionality. The access system 170 is protected by redundancy to an extent that causes the system to substantially exceed industry goals for network reliability. In order to further enhance access system 170 reliability, each DS3 path is protected by a bypass repeater providing a one-to-one redundancy, which is automatically switched into service if the normal path through the access system 170 should fail to pass any of several stringent internal diagnostic tests. Administration Shelf As shown in Figure 5, the Administration Shelf 200 contains the central computing elements and memory storage resources. This shelf also provides resources for intershelf communication and communication with support and management centers or personnel. Internal communication is in multiple serial communication protocols "Electronic Industries Association (EIA) 232" and "EIA 423". External interface language formats include TL1, PDS and MML. The Administration Shelf 200 is the source of system generated office alarms including audible, visual, and telemetry, as well as displays. The Administration Shelf 200 contains four hardware modules as described below. The Administration Processor module 190 is the central system controller. It provides inter-shelf communication via the HDLC link 192 and communication with external interfaces through the Communication Processor module 194 described below. It uses serial interfaces for internal system control: a Small Computer System Interface (SCSI) interface 208 for control of peripherals such as the hard disk drive (not shown) , and a VersaModule Eurocard (VME) data bus interface 210 to communicate with other VME standard modules. The SCSI interface 208 connects the Administration Processor module 190 to a Peripheral Subsystem 212, and the VME interface connects module 190 to the Communication Processor module 194 and a Office Alarm Interface Module 214. The Peripheral Subsystem 212 has a 1.44 megabyte floppy disk drive, a 105 megabyte hard disk drive, a 60 megabyte optional tape drive, and a Peripheral Module, none of which are shown on Figure 5. These components store surveillance data and record user activity. The Communication Processor module 194 provides the communication interface 196 to external Operations System (OS) or test system control centers (not shown) . Interfaces are via TL1 or PDS. The electrical protocols are serial "EIA 232" or "EIA 423". Craft interface is MML with a user friendly overlay. Other communication 196' external to the system is done with TL1 and PDS using serial interface electrical protocols based on Consultative Committee for International Telephony and Telegraphy (CCITT) standard X.25. The Office Alarm Interface Module 214 generates audible 216a, visual 216b, and telemetry 216c alarms for critical, major, and minor office alarms. It also receives and converts a DSl based Building Integrated Timing Source (BITS) clock (not shown) , providing clock and frame for internal synchronization. The BITS clock is a clock reference for an entire Central Office. High Speed Interface Shelf Each High Speed Interface Shelf 202 supports the capability to interface up to six bidirectional DS3 signal lines 134. Up to eight shelves can be provisioned to support a total of 48 DS3s per system. Each DS3 path 134 is supplied with one-for-one protection. Continuous performance monitoring at the DS3 rate of DS3 and DSl parameters, hitless access to DSl and all embedded DSO channels, and drop and insert of DSl and DSO channels into a DS3 bit stream are provided. HCDS testing capability is provided for the proprietary formatted DSl data that is available. Formatted DSO data can be transported via a PCM Highway 220 to the Test Resource Shelf 204 for testing. The High Speed Interface Shelf 202 contains four hardware modules as described below. A set of DS3 Interface modules (two modules are shown in Figure 5) 171 and 171' interface the digital DS3 bit stream 134 and provide resources to demultiplex the DS3 into component DSl, DSO, and subrate channels. The DS3 Interface modules 171 and 171' connect to a Shelf Monitor module 232 and a DS3 Monitor module 224 via the PCM Highway 220. The DS3 Interface modules support DS3 regeneration circuity with drop and insert capability at DSl, DSO and subrate digital levels. Full framing and continuous performance monitoring information is collected and reported at DS3 and DSl levels. The module 171 contains DS3 protection and regeneration circuitry, providing one-for-one next-card protection for the DS3 bit stream on the adjacent module 171' . The Shelf Monitor module 232 interconnects the DS3 Interface modules 171 and 171' , the DS3 Monitor module 224 and the DSl Access and Test module 184 using the HDLC link 192. The Shelf Monitor module 232 serves as the intra-shelf communication interface via the HDLC link 192 to the Administration Processor 190. The module 232 also connects to a Shelf Monitor module 232' on the Test Resource Shelf 204 via the PCM Highway 220. The Shelf Monitor module 232 provides retiming, buffering, and differential to single ended conversions of data and control lines. The DS3 Monitor module 224 connects to the DS3 Interface modules 171 and 171' via Monitor bus 226 and 226', respectively. The DS3 Monitor module 224 performs fault management on the DS3 Interface modules 171 and 171' by doing a bit for bit compare . Error conditions are reported using the HDLC link 192. The DSl Access/Test module 184 connects to the DS3 interface modules 171 and 171' via a Pseudo DS2 (PDS2) Bus 230. The module 184 also connects to the DS3 Monitor 224 via the PDS2 Bus 230 (link not shown) . The DSl Access/Test module 184 provides HCDS testing to the embedded DSls. This module supports simultaneous HCDS testing of two DSl channels . DSl channels can be routed to the Test Resource Shelf 204 for testing via a Pseudo DSl (PDS1) bus 234. There is one DSl Access/Test module per High Speed Interface Shelf 202. Test Resource Shelf The Test Resource Shelf 204 supports test resource functionality for DSl, and a full range of DSO and sub-DSO testing. The TAD 188 and FAD 188' ports also provide interfaces for testing DSls and DSOs via a DSl access. The Test Resource Shelf 204 contains four modules as described below. A DSl Interface module 238 provides an access system network interface at the DSl rate that can be configured either as a TAD or FAD port. As a TAD interface 188, the DSl Interface module 238 demultiplexes an incoming DSl channel and extracts selected DSO circuits for testing. Configured as a FAD interface 188', this module 238 receives, transmits, and loops the intact DSl facility. Performance monitoring and test access supervision are also provided for HCDS testing of DSls input via the FAD. The DSl Interface module 238 connects to the DSl Access and Test modules 184 and 184', the DSO Access and Test module 186, and the Shelf Monitor module 232' . The DSl Access/Test module 184' provides HCDS testing to the embedded DSls. This module supports simultaneous HCDS testing of two DSl channels. The DSO Access/Test module 186 incorporates digital signal processing (DSP) for DDS and VF testing of DSO and subrate channels embedded in a DS3 or DSl bit stream. Each module supports up to six simultaneous tests. The Shelf Monitor module 232' serves as the intra-shelf communication interface. It provides retiming, buffering, and differential to single ended conversions of data and control lines. DS3 Interface Module Figure 6 is the block diagram for the DS3 Interface Module 171, also referred to as the DS3 Module, in the access system 170. Each DS3 Module 171 provides a complete receive and transmit interface for a single DS3 signal 134. The access system 170 provides the capacity for up to 96 DS3 Modules providing service for 48 through DS3s. A one-for-one protection scheme is implemented with each DS3 Module containing a redundant path for the adjacent DS3 Module of the DS3 Module pair 171 and 171' . The DS3 Module provides drop and insert capability at all rates from DS3 to DSOB. Specifically, up to 4 DSOB subrate channels or 24 full DSO channels can be inserted without any restrictions on which DSls or DS2s they come from. All insertion is hitless so that no other channels are affected when the insertion is initiated, during insertion, or when it is terminated. The DS3 Module also provides for the drop and insert of DS2 bits . Either an entire DS2 bit stream or any subset of the bit stream, including individual DSl channels 132, can be overwritten. The capability also exists for overwriting the DS3 control bits. All insertion takes place at the DS3 rate so that any bits that are not inserted upon simply pass through the module unaffected. In addition, the DS3 Module 171 continuously monitors the performance of the DS3 signal 134, all 7 embedded DS2s, and all 28 embedded DSls 132. A variety of frame formats are supported including C-Bit Parity at the DS3 rate; and Superframe (SF) , Extended Superframe (ESF) , TI Data Multiplexer (T1DM) , and SLC-96 at the DSl rate. The DS3 Module 171 can be broken down into the following subsystems: a DAI circuit 250, a TSI circuit 252, a FDL Handler 254, a DSl Framer 256, a Protection subsystem 258, a DS2 Handler 260, and a CPU complex 262 along with its extensions 264. Each of these subsystems is described below. Refer to the block diagram in Figure 6 for an overview of all the DS3 Module subsystems and interfaces. The main DS3 input 134 and a protection DS3 input 268 enter the DS3 module 170 at a DS3 Analog Interface block 270. Within the DS3 Analog Interface block 270 are a main DS3 Linear Interface (LI) circuit 272 and a protection DS3 LI circuit 272' . The LI circuits 272 and 272' perform analog to digital (TTL standard logic level) conversion on input signals 134 and 268, and digital to analog level conversion on output signals 134' and 268' . The DS3 Analog Interface block 270 connects to the Protection Control 258, which further connects to the Protection Control on the adjacent module 171. The block 270 also has a bidirectional connection to the DAI circuit 250 at the DS3 level . The DAI circuit 250 connects bidirectionally to the DSl Framer Subsystem 256 at the DSl level. An Alarm Indication Signal (AIS) clock source 274 feeds the DAI circuit 250. The DAI circuit 250 also has a bidirectional connection to a block of DS2 Glue Logic 276 within the DS2 Handler 260. The DS2 Glue Logic 276 connects bidirectionally to a 7 x 7 Crosspoint Array 278, also within the DS2 Handler 260, which further connects a buffer 280. The buffer 280 provides seven bidirectional DS2 links 282 that leave the DS3 module 171. The DS2 Glue Logic 276 also has a bidirectional connection to the TSI circuit 252, which then further connects to a buffer 284 at a bidirectional DSO level. The buffer 284 then connects to the bidirectional PCM Highway 220. The TSI circuit 252 has a bidirectional connection to the FDL Handler 254, which then further bidirectionally connects to the Standard CPU Complex 262. The HDLC link 192 also has a bidirectional connection to the Complex 262. The CPU Complex Extensions 264 tie in with the Complex 262 to provide additional I/O capability. The functionality of the DS3 Module subsystems will now be described below. DAI Circuit The DAI circuit 250 performs continuous performance monitoring on the DS3 as well as all embedded DS2s and DSls. In addition the DAI provides for the drop and insert of any DS2 bit via a PDS2 interface to the DS2 Handler 260. The DAI 250 also allows for the drop and insert of any DS3 control bit . A second DS3 interface is provided along with a configurable bit for bit compare circuit, which will be discussed hereinbelow, that allows for the verification of proper DS3 signal flow. At the DS3 level, the DAI 250 supports both Asynchronous Muldem DS1/DS3 (M13) and C-Bit Parity frame formats, which will be discussed below. A more detailed description of the DAI 250 is provided below under the main heading "The DS3 Drop and Insert (DAI) Circuit". Asynchronous TSI Circuit The main functions of the asynchronous TSI circuit 252 are to multiplex/demultiplex DSl signals and to perform switching and routing of asynchronous DSO signals. The TSI 252 supports the drop and insert for up to 24 DSO channels. Other functions of the TSI 252 include a frequency counter, DSOB subrate handler (4 DSOB channels) , PDS2 overwrite control for DSOs, and a Facilities Data Link (FDL) handler for ESF formatted DSls. The TSI 252 also provides support for DDS secondary channel by allowing for "bit 8" drop and insert on up to 24 DSOs. A more detailed description of the TSI 252 is provided below under the main heading "The Asynchronous Time Slot Interchange (TSI) Circuit". Facilities Data Link (FDL) Subsystem The DS3 Module 171 provides FDL support via dedicated circuitry on the TSI 252 operating in conjunction with an external microcontroller (see Figure 23) . The FDL is a 4 Kbs data stream embedded in ESF formatted DSl signals. The TSI 252 continuously extracts FDL bits from each of the 28 DSls and stores them in an internal buffer. The buffer can hold up to seven FDL bits for each DSl. To prevent buffer overflow, the FDL microcontroller (uC) 254 must poll the TSI at a frequency such that a maximum of seven FDL bits are stored between polling cycles. This can be accomplished using a nominal polling cycle of 1.7 ms since a worst case fast DSl will produce seven FDL bits in 1.7498 ms. The FDL uC 254 is an industry standard 8052 running at 20 MHz. The 8052 has 8K bytes of ROM, 256 bytes of RAM, a clock oscillator, 3 timer counters, an interrupt controller, and a 1.66 Mbs serial port. To start the data transfer from the TSI 252 to the FDL uC 254, the FDL uC asserts a FDLDIR signal and waits a minimum of 2 us. This causes the TSI 252 to move the stored FDL bits from the online buffer to the output buffer. To extract the data from the output buffer of the TSI 252, the FDL uC 254 performs 28 consecutive byte read operations from the 8052 serial port. Each byte corresponds to a DSl channel starting with #1 and ending with #28. Since all FDL channels can be running at slightly different rates the 28 FDL bytes may not have the same number of valid FDL bits. To determine the number of valid FDL bits contained in each byte, the FDL uC starts at the least significant bit and looks for the first bit position containing a zero. All remaining bits in the byte are valid. For example, if there are seven valid data bits then the least significant bit (lsb) will be zero and the remaining seven bits are interpreted as valid FDL data bits. If the least significant bit is a one and the next bit is a zero then there are six valid FDL bits. The FDL uC 254 interprets each 4 Kbs FDL bit stream it receives from the TSI 252 for both scheduled and unscheduled performance messages. For scheduled performance report messages, which occur every second, the FDL uC 254 extracts the sixteen bits (two bytes) of information associated with the current second (to) . The other thirteen bytes of the message are discarded. For unscheduled messages, only a yellow alarm is recognized, all other messages are discarded. Every ten ms, the DS3 Module 68000 processor (available from Motorola) , within the Standard CPU Complex 262, reads a sixteen bit word from the FDL uC 254. The sixteen bit words contain the extracted FDL messages along with header information to identify the DSl channel, the message type (scheduled/unscheduled) , and the 8052 internal buffer status. The 68000 can also write eight bit values to the FDL uC 254 for future applications that require configuration data. The interface between the 68000 and the 8052 is implemented with two 8-bit tri-state buffers and an 8-bit register. The 68000 within the Standard CPU Complex 262 can reset the " FDL uC 254 under program control, and a watchdog low speed clock signal is sent from the uC to the 68000 to provide an indication of sanity. DS1 Framing Subsystem The DS3 Module 171 provides support for framing on all 28 DSls in SF, ESF, T1DM, or SLC-96 formats. Framing at the DSl level is performed by an external microcontroller, within the DSl Framer Subsystem 256, operating in conjunction with the DAI. The Framer uC is the 8052 (same as FDL uC 254) running at 16 MHz. The DSl Framing Subsystem 256 operates on one DSl signal at a time. The entire DSl data stream (up to 72 frames) is loaded into a external 16 K X 1 RAM by the DAI 250. The Framer uC then examines the RAM to determine where the framing pattern is . The Framer uC then feeds an offset to the DAI to indicate where the framing pattern was found. The RAM address generator of the DAI includes a 14 bit counter which is implemented, along with some glue logic, in a small Erasable Programmable Logic Device (EPLD) , an Intel 5C60/Altera EP600. DS2 Handler Subsystem The DS2 Handler Subsystem 260 includes the circuitry that processes the DS2 level signals that flow between the DAI 250, the TSI 252 and the backplane. The interface between the DAI 250 and TSI 252 includes groups of pseudo DS2 (PDS2) signals. "Pseudo" refers to the fact that the signals run at the DS2 rate but the clock is gapped for non-DSl data bits and all DSl framing information is provided. The seven groups represent the seven DS2s that are embedded in the DS3. The DAI 250 feeds the inverted DS2 data stream directly to the TSI 252. The DAI 250 also sends out the DS2 clock along with a cycle "block" signal to indicate where the DS2 overhead bits are located. External circuitry is provided to gate the clock with the block signal thus providing a gapped DS2 clock to the TSI 252. The DAI 250 also provides signals used to locate DSl data bits and frame bits in the DS2 data stream. A two bit value is fed from the DAI 250 to the TSI 252 to indicate which DSl the current bit on the DS2 data line is associated with. A DSl multi-frame signal is also provided to the TSI to indicate when the first F-bit of a DSl multi-frame is currently active on the DS2 data line. The TSI 252 sends inverted data at the DS2 rate back to the DAI 250 along with an overwrite signal that indicates to the DAI 250 which of the bits coming from the TSI 252 should be overwritten onto the outgoing DS3 data stream. The output data and overwrite signals of the TSI 252 are processed by external circuitry so that they can be de-activated during DS2 overhead bits before being sent onto the DAI 250. A crosspoint switch array 278 is provided as the interface between the DAI 250 and the DS2 links 282 on the backplane. In this manner any of the seven DS2 signals from the DAI 250 can be connected to any of the seven DS2 links 282 on the backplane. The five signals associated with each of the seven DS2s require five 7 X 7 crosspoint arrays 278 to provide the switch function. All five crosspoint arrays 278 are configured with the same crosspoints activated since the group of signals for the specified DS2 are always routed together. After passing through the crosspoint array 278, the DS2 data coming from the DAI 250 is fed through inverting buffers 280 and out onto the backplane. Both the DS2 clock and frame signals coming from the DAI 250 are sent through 7 X 7 crosspoint arrays 278 and fed through non-inverting buffers 280' (not shown) and out to the backplane. The DS2 data coming from the backplane is inverted and sent through a 7 X 7 crosspoint array 278 before being "ORed" with the data coming from the TSI 252 and sent on to the DAI 250. The companion DS2 overwrite signal coming from the backplane is also sent through a 7 X 7 crosspoint array 278 before being "ORed" with the overwrite signal coming from the TSI 252 and sent on to the DAI 250. The crosspoint arrays 278 are implemented with 8 X 8 analog switch devices (Mitel MT8809) that are designed to handle digital signals. Since the DS2 signals are arranged in groups of seven, only the 7 X 7 portion of the devices is actually used. DS3 Protection Subsystem The access system 170 provides a one-for-one protection scheme. Each main DS3 path 134 has associated with it a protection path 268 on the adjacent DS3 Module. Failure conditions on the main path 134 cause the DS3 signal to be switched to the protection path 268. When the failure condition is removed, the signal is switched back to the main path 13 . Several conditions can cause a switch to the protection path. Under hardware control by the Protection Control 258, if there is a power loss or if the output of the DS3 LI circuit 272 has no activity, then a switch is made to the protection path 268. If the 68000 CPU complex watchdog timer times out this will also force a switch to the protection path. In addition under software control the CPU can force a protection switch. The CPU also has the capability of forcing a protection switch off of the main path on the adjacent board. Whenever any of the conditions that caused the protection switch to occur are removed then the DS3 signal is again routed through the main path 134. There are several status signals available to the CPU to aid it in determining when to invoke a software controlled protection switch. These signals include: loss of activity on main path, loss of activity on protection path for adjacent DS3, loss of signal on main path, loss of signal on protection path for adjacent DS3 signal and loss of signal on main path for adjacent board. When a protection switch is invoked, the signals are timed so that events take place in the following sequence: 1. Close protection path relay 2. Delay 15 ms 3. Simultaneously enable protection path DS3 LI 272' and disable main path DS3 LI 272 4. Open main path relay When the DS3 signal is switched back to the main path, events take place in the following sequence: 1. Close main path relay 2. Delay 15 ms 3. Simultaneously disable protection path LI 272' and enable main path LI 272 4. Open protection path relay Once a protection switch is invoked, the CPU must force the main path LI 272 output to be enabled so that the activity detector can resume functioning and allow the return to the main path 134 if activity is again detected. Once activity is again detected on the main path LI output, the CPU must relinquish control of the LI output enable (this will result in the LI output being disabled) . In order that the activity detector does not immediately flag a loss of activity and prevent switching back to the main path 134, there must be a minimum 30 ms delay in its loss of activity detect time. This allows enough time for the main path LI 272 to be enabled (15 ms after start of switch back to main path) . So that a protection switch is not again immediately invoked, the activity detector must have a maximum delay of 5 ms before declaring the presence of activity. A more detailed description of the Protect Path is provided below under the main heading "The Protect Path" . DS3 Path Delay Adjustment The DS3 signal in the access system 170 goes through the DS3 LI 272 and the DAI 250. In the protection switching scheme there are two parallel paths taken by the DS3 signal: the main path 134 and the protection path 268. A fault on one path results in the DS3 being routed through the other path. To minimize downstream disruptions to the network, the access system 170 provides hitless switching capability when switching between the two DS3 paths. Normal manufacturing tolerances result in potential delay differences between the main and protection paths that would not allow for hitless switching. To remedy this problem, the delay through all DS3 paths is adjusted to an absolute reference before the modules are placed in service. A delay adjustment circuit 1120, which is a portion of the preferred DS3 LI 272 and 272', is shown in Figure 29. The circuit 1120 contains an eight bit elastic store 1122 (a First In, First Out or FIFO structure) in the transmit direction. Input DS3 data is clocked into the elastic store 1122 using a recovered data clock 1124. The recovered data clock 1124 is extracted from the input DS3 data stream through a signal processing circuit which produces current pulses leading to a 44.736 MHz LC tank circuit in another portion of the DS3 LI circuit (not shown) . A tank circuit has inductance and capacitance, and is capable of storing electrical energy over a band of frequencies continuously distributed about a single frequency about which the circuit is said to be resonant, or tuned. Output DS3 data is clocked out using an output clock that is generated by a voltage controlled crystal oscillator (VCXO) 1126. The frequency of the VCXO 1126 is automatically adjusted until it matches the frequency of the incoming data, which has a variance of +/- 20 ppm. The automatic frequency adjustment is implemented using a phase comparator 1128 that monitors the status of the elastic store 1122 and a loop amplifier 1130. The status signals include: elastic store less than half full, elastic store more than half full, elastic store reading from last bit and elastic store reading from first bit. The phase comparator 1128, the loop amplifier 1130 and the VCXO 1126 are used together as a phase lock loop circuit. The phase comparator 1128 output is a smoothed analog, delay error signal connected to the loop amplifier 1130. The loop amplifier output is a DC control signal which provides instantaneous frequency and phase information to the VCXO 1126. The phase comparator 1128 and loop amplifier 1130 adjust the frequency of the VCXO 1126 such that the elastic store 1122 remains in the half full position nominally. In addition, the phase of the VCXO clock 1126 is manually adjusted until the delay through the entire DS3 path is exactly 980 +/- 1 nanoseconds. The VCXO offset phase adjustment is controlled by a potentiometer 1132 that is manually adjusted at the time the DS3 module 171 is manufactured to ensure that the input to output DS3 delay is approximately equal to the nominal number•of bits desired in the elastic store. Hitless protection is assured by having all DS3 modules 171 adjusted in this manner. 68000 CPU Complex Referring now again to Figure 6, the CPU complex on the DS3 Module includes the "Standard CPU Complex" 262 along with some additional circuitry 264 required by functions particular to the DS3 Module. The "Standard CPU Complex" 262, which is included in entirety on the DS3 Module, contains the following: 1. 68HC000 microprocessor with clock generator 2. 128K Bytes Electrically Programmable Read-Only Memory (EPROM) 3. 256K Bytes flash memory 4. 256K Bytes Pseudo Static RAM with auto-refresh 5. 2K Bytes Electrically Erasable PROM (EEPROM) 6. Wait state generator/bus error generator 7. Interrupt controller 8. Power on reset circuit 9. Watchdog timer 10. HDLC Serial link controller 11. Multi-function I/O port: - 4 counters Universal Asynchronous Receiver Transmitter (UART) - 8 bit I/O port There are four Light Emitting Diodes (LEDs) on the DS3 Module to indicate the following conditions : 1. Unit Fail (Red) 2. CPU in Service (Green) 3. DS3 Main Online (Green) 4. DS3 Protection Online (Amber) CPU Complex Extensions The DS3 Module requires additional I/O capability beyond that supplied by the standard CPU complex. This additional capability is provided by the CPU Complex Extensions 264. There are five I/O lines available in the standard CPU complex 262; however, additional I/O is required for the Framer microcontroller (1 status, 3 control) , the FDL microcontroller 254 (4 status, 1 control) , the DAI 250 (2 status) , the DS3 LI protection circuit (13 status, 11 control) , DS2 link tri-state enables (7 control) , and two additional LEDs. There are no additional chip select requirements beyond that provided by the standard CPU complex 262. In order to save pins, the DAI 250 requires a multiplexed address/data bus. Circuitry is provided to multiplex the lower eight bits of the 68000 address and data busses together before feeding them to the DAI 250. DS3 Module Interfaces All interfaces between the DS3 Module 171 and the rest of the access system 170 are routed over an 140 pin edge connector. The primary interfaces include: the DS3 interface 134, the PCM Highway interface 220, seven DS2 interfaces 282, and the HDLC interface 192. There are several additional interfaces that are also described below. DS3 Analog Interfaces There are two paths for DS3 signals passing through the DS3 Module: the main path 134 and the protection path 268. Full performance monitoring and drop and insert capabilities exist for the main path DS3 134 while the protection path 268 basically functions as a repeater with delay inserted to match the main path. There are three types of DS3 analog interfaces on the DS3 Module: line receivers, line transmitters, and monitor outputs. The line receivers take the input from the DS3 line 134 and convert it into a TTL level digital signal plus clock. The line transmitters take the TTL signal plus clock and convert it into an analog bipolar DS3 signal 134' . The monitor outputs are similar to the transmitter outputs and are sent over the backplane to the Monitor card. PCM Highway Interface The PCM Highway 220 provides the mechanism for routing of DSOs throughout the access system 170. With 128 time slots, the PCM Highway 220 supports transmission of up to 128 bi-directional asynchronous DSO channels. The PCM Highway 220 is arranged in a master/slave fashion, where masters, such as the DS3 Module 171, transmit onto four Tx lines each supporting 32 times slots, and receive from four Rx lines each supporting 32 time slots. The master also drives an additional transmit status line which indicates whether or not the associated time slot contains valid data or stuff data in the current frame. Stuff data and bit stuffing will be described hereinbelow. PCM Highway slave devices such as the DSP module receive from the Tx lines and transmit onto the Rx lines, while monitoring the transmit status line in order to extract DSO timing. Arbitration of the PCM Highway 220 is controlled by software via proper allocation of time slots among the various master or slave devices throughout the system. A single clock and frame sync signal are fed to all devices on the PCM Highway 220 for synchronization. In normal operation only one device is driving the PCM Highway 220 during any given time slot. However, due to clock skew and differences in driver and receiver buffer delays there can be bus contention for short periods of time (-50 ns) near the time slot transitions. To resolve this contention issue, open collector drivers (such as 74ALS1005/74ALS1035) are used for transmitting onto the PCM Highway 220. With open collector buffers, contention is not a problem since the buffers sink current in the logic "0" state and are inactive in the logic "1" state. In a case where two or more drivers are active simultaneously, they all will be attempting to bring the line to the same logic "O" level, with no backdriving taking place. Centralized pull-up resistors on the PCM Highway 220 provide default logic "1" levels on inactive lines. The DS3 Module 171 also outputs five transmit enable signals, one for each of the four Tx lines and one for the transmit status line. These signals indicate when that particular DS3 Module 171 is driving the associated line on the PCM Highway 220. Figure 7 is an operational flowchart for the presently preferred access system 170. A first portion of the system software is message driven, and so, at state 350, waits on a TL1 message at the communications processor 194 (Figure 5) . The message from the OS (not shown) , sent across the OS link 196, will contain a command function and an access identification (AID) that are validated at state 352. Proceeding to state 352, the command function is checked for whether a test command has been requested and, if it is, a decision is made at state 356 as to whether the test is a DSl or DSO level test. If a DSl level test has been requested, the test information is forwarded to the administration processor 190 which in turn communicates across the HDLC bus 192 to one of the DS3 interfaces 171 and one of the DSl test resources 184 to allocate routing and resources (states 358 and 360) . Now the access system 170 is ready to begin the DSl test. Continuing to states 362 and 364, the access system 170 sends an enable byte and security byte to the DAI circuit 250 to demultiplex the requested DSl channel from the DS3 bit stream received from the input line 134. The requested DSl channel is forwarded across the pseudo-DSl bus 234 to the allocated DSl test resource (A/T module) 184 where the test is performed at state 366. Moving to state 368, the test results are sent across the HDLC bus 192 to the administration processor 190 where the test results are stored on a disk in the peripheral subsystem 212 and, at state 370, an output message, including the test results, is created by the access system 170. A final sequence of states is necessary to forward the test results back to the OS. The administration processor 190 communicates the unformatted output message to the communications processor 194 where the message is placed in TL1 format (state 372) . The message is then queued for output (state 374) and finally, at state 376, it is transmitted to the OS across the OS link 196. The access system 170 then returns to state 376 to wait on another command message. Another branch of processing flow occurs if the decision at state 356 is that the command function requests a DSO level test. At states 377 and 378, PCM Highway slots and DSO multiplexer/demultiplexer circuits are allocated by commands sent from the administration processor 190 to the TSI circuit 252 on the DS3 interface 171. Moving to state 379, the administration processor 190 allocates the DSO subrate framer in the TSI circuit 252 (state 380) if a DDS subrate test was requested. Then, states 381-386 are carried out similarly to states 362-370, except that DSO insert must be enabled in the TSI 252 at state 383 and the DSO test resource 186 receives the DSO channel across the PCM Highway 220. From state 372, the results of the DSO test are forwarded to the OS in the same manner as the DSl test results. Returning in the discussion to decision state 354 of Figure 7, if the command function is not a test command, the communications processor 194 moves to state 387 to test whether the command requests a performance monitoring (PM) data retrieval. PM data is maintained on a continuous basis for the DS3 signal as well as all embedded DS2 and DSl channels. If the command is not a PM command, then other commands are checked and processed accordingly (not shown) . Assuming the command received from the OS is to retrieve PM statistics, a test is made at state 388 to determine whether current or history statistics were requested. A request for current PM statistics is handled by a request from the administration processor 190 to the DS3 interface 171. The DS3 interface 171 then retrieves current PM statistics from memory and forwards them back to the processor 190 (state 389) where an output message, containing current PM statistics, is constructed (state 390) and communicated back to the OS as before proceeding from state 372. On the other hand, if history PM statistics were requested, then the administration processor 190 retrieves the PM statistics from a disk that is part of the peripherals subsystem 212 (state 391) . An output message, containing history PM statistics, is constructed at state 392 and communicated back to the OS as before proceeding from state 372. The software for the access system 170 also comprises a performance monitoring (PM) process 393 which is periodically executed in the DS3 interface 171 (Figure 4) . The process 393 begins at state 394 by reading performance monitoring (PM) registers located inside of the DAI circuit 250. PM statistics are accumulated and stored in on-board semiconductor memory at state 395. Moving to state 396, the statistics are tested for whether any thresholds have been exceeded. If a threshold has been exceeded, an alarm/event message is constructed at state 397, forwarded to the administration processor 190, and sent back to the OS, as before, proceeding from state 372. If no threshold is reached, or the alarm/event message has been sent, the PM process 393 terminates. As indicated by state 398, once a PM interval expires, the PM process 393 is restarted. II. THE DS3 DROP AND INSERT (DAI) CIRCUIT A. INTERFACES Figure 8 is an Input/Output diagram for the DAI circuit 250. A description of each I/O pin group is given below. DS3 Processor Interface A DS3 Processor Interface 400 is provided to allow the DAI 250 to be configured and for the status that is generated by the DAI to be reported. DS3 Transceiver Interface A DS3 Transceiver Interface 402 is provided to allow the DAI 250 to interface to the DS3 Line Interface device which recovers the DS3 clock and converts the DS3 signal 134 into two rail Non-Return-to-Zero (NRZ) data in the receive direction and it converts the two rail NRZ data and clock from the DAI into a DS3 signal 134' in the transmit direction. Pseudo DS2 Interface A Pseudo DS2 Interface 404 is provided to allow the capability for an external device to overwrite any information bit in the DS3 signal 134. DSl Framer Interface A DSl Framer Interface 406 is provided to allow the capability for an external device to synchronize the internal DSl state counters of the DAI 250 to the 28 internally generated component DSl channels. Alternate DAI Interface An Alternate DAI Interface 408 (shown as part of a system interface 412 in Figure 8) is provided to allow the capability for the alternate DAI to insert a Far End Block Error (FEBE) in the East to West DS3 signal in response to a parity error in the West to East DS3 signal . Control Bit Interface A Control Bit Interface 410 (shown as part of the system interface 412) is provided to allow the capability for an external device to overwrite any control bit in the DS3 signal 134. System Interface The System Interface 412 is provided for miscellaneous signals such as clocks, resets, enables, power, ground and alarms. B. FUNCTIONALITY The top level block diagram of the DAI circuit 250 is shown in Figure 9. A secondary DS3 input from the DS3 Analog Interface 270 (Figure 6) goes to a bipolar with three-zero substitution (B3ZS) Decoder 420, through a fixed delay 422 and exits after encoding by a B3ZS Encoder 423. A primary DS3 input from the DS3 Analog Interface 270 goes to a B3ZS Decoder 424 and through a fixed delay 426 which has a different value than the delay 422. Connected to the delay 426 is a multiplexer 428 which is further connected to a B3ZS Encoder 429, whereupon the signal leaves the DAI circuit 250. A signal line from the output of the B3ZS Decode 424 connects to a DS3 Performance Monitor 430 and to a DS3 to DS2 demultiplexer 432. The DS3:DS2 demultiplexer 432 has seven output lines of which only the first 433 and last (seventh) 433' are shown in Figure 9. The first output line 433 connects to a DS2 Performance Monitor 434 and to a DS2 to DSl demultiplexer 436. The last output line 433' connects to a DS2 Performance Monitor 434' and to a DS2 to DSl demultiplexer 436' . The DAI circuit 250 has seven DS2 Performance Monitors, like the Monitor 434, and seven DS2:DS1 demultiplexers, like the demultiplexer 436. The DS2:DS1 demultiplexer 436 has four output signals; each output signal is connected to a DSl Performance Monitor 438a-d. The DS2:DS1 demultiplexer 436' has four output signals; each output signal is connected to a DSl Performance Monitor 438e-h. Connected to the four output signals of each of the seven DS2:DS1 demultiplexers 436 is a DSl Performance Monitor 438, for a total of 28 DSl Performance Monitors in the DAI circuit 250. The DAI circuit 250 provides performance monitoring of a single direction of a DS3 signal and its constituent channels. Frame Formats supported include M13 Asynchronous, C-Bit Parity, SF, ESF, T1DM, and SLC-96. The M13 Asynchronous format, also known as the DS3 frame format, and the DS3 C-Bit Parity format will be described below in association with Figures 12-14 The DAI circuit 250 provides for the drop and insertion of any of the 4704 information bits in the DS3 signal via the DS2 Interface 404 (Figure 8) , and any of the 56 control bits in the DS3 signal via the Control Bit Interface 412 (Figure 8) . The DAI circuit 250 provides a second digital DS3 interface along with a configurable bit for bit compare circuit (Figure 10a, 470) that allows for the verification of the operation of other DAI circuits that are configured identically or for the cycle alignment of two DS3 signals to assure a hitless switch. The detailed level functional block diagram of the DAI circuit is separated into six different subgroups of circuitry as illustrated in Figure 10a: 1. DS3 Data Path 450 - 2. M23 Demux 452 (Figure 10b) 3. M12 Demux 454 (Figure 10c) 4. DSl Monitor 456 (Figure lOd) 5. Recombiner 458 (Figure lOe) 6. Processor Interface 460 (Figure lOf) 1. DS3 Data Path The DS3 Data Path section 450 of the DAI circuit 250 contains two groups of circuitry, one for the primary path 462 and one for the secondary path 464. The primary path 462 is the path that has the ability to overwrite DS3 data and control bits, while the secondary path 464 has no overwrite capability. There are four main functions that are performed in the DS3 Data Path section: B3ZS encoding/decoding - Bit for bit compare DS3 data delay Overwrite of DS3 data and control bits. a. B3ZS Encode/Decode The zero code suppression used at the DS3 level is the bipolar with three-zero substitution (B3ZS) format, well known in telephone network technology. In the B3ZS format, each block of three consecutive zeros is removed and replaced by B0V or 00V, where B represents a pulse conforming with the bipolar rule, 0 is a zero (no pulse) and V represents a pulse violating the bipolar rule. The choice of BOV or 00V is made so that the number of B pulses between consecutive V pulses is odd. The B3ZS decoders 420 and 424 take the incoming positive rail data and the negative rail data and converts the information into a single NRZ channel. The B3ZS encoders 423 and 429 take the single NRZ channel and converts the information into two NRZ channels, positive rail and negative rail . b. Bit for Bit Compare A Bit for Bit Compare circuit 470 connects to the output of the delay 422 and to the input of the delay 426. The Bit for Bit Compare circuit 470 provides the capability to verify the functionality of the DAI 250 while in service, and to verify the alignment of the primary path 462 and secondary, or redundant, path 464 prior to making a "hitless" switch. The Bit for Bit Compare circuit 470 will be further discussed in conjunction with Figure 28. c. DS3 Data Delay The DS3 Data Delay circuitry 422 and 426 provides sufficient processing time for the M23 demultiplexer 452 and M12 demultiplexer 454 to calculate the pointers to the data in the DS3 stream that are used by the recombiner 458 in overwriting individual bits. d. 7:1 Multiplexer Block The 7:1 Multiplexer circuitry 428 provides the ability for the recombiner 458 to overwrite the DS3 data in the primary path 462 with data from any of the six sources. The select line for this multiplexer is generated by the recombiner. 2. M23 Demultiplexer Referring now to Figure 10b, the DS3 primary data path 462 is the main input to the DS3 to DS2 demultiplexer 452. The DS3 Performance Monitor 430 output, within the DS3 to DS2 demultiplexer 452, connects to the recombiner 458 (Figure lOe) , while each of the outputs of the DS2 data generator 432, also referred to as the DS3:DS2 demultiplexer in Figure 9 and 10, connects to one of the seven M12 demultiplexers 454 (Figure 10c) . Other outputs of the demultiplexer 452 connect to the DAI I/O pins as shown in Figure 10a. The DS3 to DS2 demultiplexer 452 demultiplexes the DS3 signal into its seven constituent DS2 channels along with their associated gapped clocks. Refer to Figures 12 and 13 for the M13 Asynchronous frame format and Figure 14 for the C- Bit Parity frame format. The four main functions of the DS3 to DS2 demultiplexer section include: - DS3 Framing DS2 Clock Generation DS2 Data Generation DS3 Performance Monitoring a. DS3 Framing A DS3 Framer 474 synchronizes a DS3 State Counter 472 to the incoming DS3 signal. The DS3 State Counter 472 provides a pointer that indicates which bit of the DS3 M-frame the incoming DS3 data bit is associated with. The DS3 Framer 474 and DS3 State Counter 472 will be discussed further in reference to Figure 15a and 15b. b. DS2 Clock Generation A DS2 clock generator 476 uses the timing information from the DS3 State Counter 472 to generate seven 6.312 MHz gapped clocks. The clock pulse associated with a particular data bit is deleted or gapped by several conditions dependant upon the clocks destination. c. DS2 Data Generation The DS2 data generator 432 uses the timing information from the DS3 State Counter 472 to generate seven 6.312 MHz serial data streams. The DS2 data channels are synchronous with the associated DS2 gapped clock. No bit inversion is required when demultiplexing from DS3 to DS2. d. DS3 Performance Monitoring The DAI circuit 250 monitors the performance of both the standard M13 asynchronous signal format as specified in Bellcore TR-TSY-000009 and the DS3 C-Bit Parity signal format as specified in AT&T PUB 54014. DS3 performance monitoring parameters that are continuously monitored by the monitor 430 are as follows: Bipolar Violation Count Loss Of Signal Status Loss of Line A Clock Status Loss of Line B Clock Status F Bit Error Count Out-of-Frame Status Change of Frame Alignment Status Line Parity Error Count C-bit Parity Error Count - Far End Block Errors (FEBE) Count Incoming C-Bit Parity Frame Format Status Incoming All Ones Status Incoming Yellow Alarm Status Incoming Alarm Indication Signal (AIS) Detection Status Incoming Stuck Stuffing Detection Status Incoming Idle Signal Status 3. M12 Demultiplexer There are seven DS2 to DSl demultiplexers on the DAI circuit 250, one per constituent DS2 channel. Each DS2 to DSl demultiplexer is alike, and performs the same functions. The first DS2 to DSl demultiplexer 454 and the last (seventh) DS2 to DSl demultiplexer 454' are shown in Figure 10a. As described above, each DS2 to DSl demultiplexer is driven by an output of the DS2 data generator 432 (Figure 10b) . Referring now to Figure 10c, outputs of the DS2 to DSl demultiplexer 454 are driven by the DSl data generator 436, also referred to as the DS2:DS1 demultiplexer in Figure 9 and 10, and a DSl clock generator 482. Each DSl data generator 436 is connected to four DSl Monitors 456 (Figure lOd) , and also provides four outputs that connect to a multiplexer 484 (Figure 10a) . Each DS1 clock generator 482 provides four outputs that connect to a multiplexer 486 (Figure 10a) and also connect to a multiplexer 488. Each of the multiplexers 484, 486 and 488 has twenty eight inputs from the seven DS2 to DSl demultiplexers. The DS2 to DSl demultiplexer 454 demultiplexes the DS2 channel into its four constituent DSl channels along with their associated gapped clocks. The four main functions of the DS2 to DSl demultiplexer section include: DS2 Framing DSl Clock Generation DSl Data Generation DS2 Performance Monitoring a. PS2 Framing A DS2 Framer 480 synchronizes a DS2 State Counter 478 to the incoming DS2 channel. Frame synchronization is obtained by finding a bit position in which the 010101... framing pattern is observed across nine consecutive F bits. The DS2 frame format is specified in Bellcore TR-TSY-000009. There are four subframes per DS2 frame and each subframe contains six blocks or groups of 49 bits. The first bit of each group is a control bit or overhead bit. The control bits associated with groups 3 and 6 are F bits. A serial approach which searches one bit position at a time has a maximum average reframe time (MART) of approximately 6.85 msec for the DS2 framing pattern. Maximum Average Reframe Time is the average time to reframe when the maximum number of bit positions must be examined for the framing pattern. This time must be arrived at statistically, and in the calculation it shall be assumed that the non-frame bits are ones and zeros with equal probability. The requirement for the DS2 rate is a MART of less than 7.0 msec, and consequently the serial search algorithm is used. The algorithm employed has a MART of approximately 6.85 msec. The algorithm initially assumes that the current state of the State Counter 478 is correct and tries to find the framing pattern in the bit position currently identified by the State Counter as being the F bit location. If a single bit is found that does not correlate with the framing pattern, then the state of the State Counter is retarded by one cycle. By retarding the state counter one cycle at a time and checking the validity of the bits observed, the DS2 Framer 480 will eventually synchronize to the sub-frame. The next step in the framing process is to acquire multi- frame alignment. A shift register (not shown) is used to store the values of all of the four first column (group 1) control bits. These control bits are the Ml, M2, M3, and the M4 bits. However, at this point in the framing process it is not known which bit in the shift register corresponds to which control bit. The shift register is searched for the Oil pattern of the M bits. If multiple Oil patterns are found or a Oil pattern does not exist, the framing process begins again. If a single Oil pattern is found, the State Counter is advanced or retarded the correct number of subframes to obtain M-frame alignment. b. DSl Clock Generation The DSl clock generator 482 uses the timing information from the DS2 State Counter 478 to generate four 1.544 MHz gapped clocks. The clock pulse associated with a particular data bit is deleted or gapped by several conditions dependant upon the clocks destination. c. DSl Data Generation The DSl data generator 436 uses the timing information from the DS2 State Counter 478 to generate four 1.544 MHz serial data streams. The DSl data channels are synchronous with the associated DSl gapped clock. The first and third DSl channels are inverted, while no inversion is required on channels 2 and 4. d. DS2 Performance Monitoring The DAI circuit 250 monitors the performance of the standard DS2 channel format as specified in Bellcore TR-TSY- 000009. DS2 performance monitoring parameters that are continuously monitored by the monitor 434 are as follows: - Loss of Signal Status F Bit Error Count Out-of-Frame Status Change of Frame Alignment Status Incoming Yellow Alarm Status - Incoming Alarm Indication Signal (AIS) Status 4. DSl Monitor Each DSl Monitor 456 (Figure 10a) is connected to one of the four outputs of the DSl data generator 436 (Figure 10c) . Since there are a total of seven DSl data generators in the DAI 250, there are a total of twenty eight DSl Monitors, but only the first Monitor 456 and the last (28th) Monitor 456' are shown in Figure 10a. Referring to Figure lOd, the following DSl Monitor functions are described: a. DSl State Counter A DSl State Counter 520 drives a portion of the interface 404 as described in reference to Figure 8. The DSl State Counter 520 is synchronized through the use of the external DSl Framer Subsystem 256 (Figure 6) . b. DSl Performance Monitoring The DAI circuit 250 monitors the performance of DSl channels in the Superframe format as specified in Bellcore TR- TSY-000009 and TlCl.2/87-001R3, the Extended Superframe format as specified in Bellcore TR-TSY-000194 and TlCl.2/87-001R3, the TIDM format as specified in Bellcore TA-TSY-000278 and the SLC-96 format as specified in Bellcore TR-TSY-000008. DSl performance monitoring parameters that are continuously monitored by the monitor 438 are as follows: Loss of Signal Status F Bit Error Count Out-of-Frame Status Change of Frame Alignment Status - Frame Format Status Incoming Yellow Alarm Status Incoming Alarm Indication Signal (AIS) Status Cyclic Redundancy Check Error Count 5. Recombiner Referring now to Figure lOe, the recombiner 458 provides for the insertion of data into the DS3 data stream or any constituent DS2 or DSl channel with no blocking. Several interfaces are provided to allow for a variety of methods of overwriting data. Every type of data that can be inserted into the DS3 data stream is individually enabled via software configuration. Inputs to the recombiner 458 are from the DAI input pins of the pseudo DS2 interface 404 (Figure 8) and from the M23 demultiplexer 452. A pseudo DS2 insert circuit 490, a control bit insert circuit 492, a line parity insert circuit 494, a C-bit parity insert circuit 496, a Far End Block Error circuit 498 and a Alarm Indication Signal insert circuit 500 all provide an output which connects to an input of the 7:1 Multiplexer 428 (Figure 10a) . a. Pseudo DS2 Insert The pseudo DS2 insertion circuit 490 provides the capability to overwrite any given DS3 information bit on an individual bit by bit basis. Applications for the use of this capability include the hitless overwrite of individual DSl channels, DSO channels, subrate channels, or secondary channels. The PDS2 Insert block 490 is further discussed in conjunction with Figure 11. b. Control Bit Insert The control bit insertion circuit 492 provides the capability to overwrite any of the DS3 control bits. c. Line Parity Insert The line parity insertion circuit 494 provides the capability to correct the line parity or to pass the received parity through. d. C-bit Parity Insert The C-bit parity insertion circuit 496 provides the capability to modify the C-bit parity in the event of an overwrite taking place or to pass the received parity through. e. Far End Block Error Insert The Far End Block Error (FEBE) Insert circuit 498 provides the capability of inserting a FEBE in one direction of the DS3 if in the alternate direction a parity error was detected. f . Alarm Indication Signal Insert The Alarm Indication Signal (AIS) insert circuit 500 provides the capability to insert AIS in response to certain trouble conditions detected by the DS3 performance monitoring circuitry. 6. Processor Interface Referring now to Figure lOf, the DS3 Processor Interface circuitry 460 allows for the configuration of the DAI and for the reporting of status information generated by the DAI . The interface is a general purpose design and can be used with a variety of different processor families. Two separate modes exist for the processor interface: ASYNCMD In the asynchronous mode, a peripheral generates a data transfer acknowledge signal . SECMD In the secure mode, the processor must write to the address associated with the next write enable register prior to every write. This feature allows for the filtering of invalid write attempts. a. Configuration The DAI has the capability of being configured via the DS3 processor interface. Configuration data is written to a set of specific configuration registers 510, 512 and 514. The capability exists to read the data back to verify that the correct data was written. Resetting the DAI 250 forces the configuration of the chip into the default mode with all of the overwrite capabilities disabled. b. Status The status internally generated by the DAI 250 is read by the DS3 processor via a DS3 processor interface 516. When the DS3 processor 262 (Figure 6) is reading status information generated by the DAI 250 that requires multiple words to transfer (such as certain counts) , the least significant word must be read first and then immediately thereafter the most significant word must be read. c. DSl Framing Processor Interface A DSl framing processor interface 518 connects to the DSl framing processor circuitry 256 (Figure 6) to provide the capability to synchronize the 28 internal DSl state counters, such as state counter 520, to the respective DSl channels. The DSl framing processor 256 operates autonomously by cycling through the 28 DSl channels, and synchronizing the ones that are identified by the DAI 250 as being OOF. The DS3 Processor 262 configures the DAI 250 by downloading the frame format of all constituent DSl channels via the processor interface 460. The DAI 250 continuously monitors the framing status of all DSl channels. Upon detection of an OOF condition on a particular DSl channel, a corresponding status bit is set. Figure 11 illustrates how the pseudo DS2 insert circuit 490 (Figure lOe) connects to the other circuits of the DAI circuit 250. The microprocessor in the CPU complex 262 (Figure 6) interconnects to the microprocessor interface 516 of DAI 250 to enable the configuration registers 510, 512 and 514 to be written. The outputs of the configuration registers 510, 512 and 514 connect to a compare circuit 530. From the subcircuits 452, 454 and 456 (Figure 10a) , the State Counters 472 (Figure 10b) , 478 (Figure 10c) and 520 (Figure lOd) , respectively, drive a decode circuit 532. The output of the decode 532 provides the second input to the compare circuit 530. An output of the compare circuit connects to the 7:1 multiplexer 428 (Figure 10a) as a select line input. Two of the data inputs to the multiplexer 428 are the DS3 data from the output of the delay 426 (Figure 10a) , and the PDS2 data from the PDS2 interface 404 (Figure 8) . The output of the multiplexer 428 is the overwritten DS3 data, if any input other than that from the delay circuit 426 is selected. The pseudo DS2 insertion circuitry 490 provides the capability to overwrite any given DS3 information bit on an individual bit by bit basis. Applications for the use of this capability include the hitless overwrite of individual DSl channels, DSO channels, subrate channels, or secondary channels. The recombiner 458 takes advantage of the fact that the timing of the demultiplexed channels is identical to that of the multiplexed channels. This timing relationship eliminates the need to provide a complete DSl to DS2 and DS2 to DS3 multiplexer. Each constituent DS2 and DSl channel of the DS3 has a state counter that is synchronized with the demultiplexed data. These state counters 478 and 520 are used as pointers to indicate which DS2 and which DSl channel a given bit in the DS3 data stream is associated with. The microprocessor in the CPU Complex 262 enables the DAI circuit 250 to overwrite a given DSl channel for example. The values of the state counters are decoded by the decode block 532 every DS3 cycle to determine which DSl channel the bit is associated with. When the decode of the state counters matches the value enabled via the microprocessor interface 516 by use of the compare block 530, the select line of the multiplexer 428 becomes active which enables the data from the PDS2 Interface to overwrite the particular DS3 data bit . The DAI circuit 250 provides as outputs the seven DS data channels with their respective gapped clocks . I addition a three bit wide data bus is provided with each DS to indicate the location of the DSl framing bits and which DS channel any given bit in the DS2 data stream is associate with. Given this information external circuitry can determin exactly which bits are to be overwritten for a give application. By providing seven pseudo DS2 data inputs alon with seven overwrite signals as inputs to the DAI circuit 250 , any information bit in the DS3 data stream can be overwritten. The overwrite signals are used to indicate which bits in the pseudo DS2 inputs are to be inserted into the DS3 data stream. Control Bit Insert The control bit insertion circuitry 492 (Figure lOe) provides the capability to overwrite any of the DS3 control bits. Seventeen DS3 cycles after a control bit has been clocked out of the DAI circuit 250 via the control bit drop circuitry, the same control bit in the DS3 data stream is overwritten via an externally provided control bit . This overwrite of the DS3 control bits is enabled via software configuration. Line parity Insert The line parity insertion circuitry 494 (Figure lOe) provides the capability to correct the line parity or to pass the received parity through. Three modes exist for line parity insertion: Mode A Line parity is passed through the DAI circuit 250 regardless of whether or not the parity is correct, and regardless of whether or not an insert is taking place. Mode B If the Line parity of the incoming signal is in error, then the line parity of the outgoing signal is in error even if an insert is taking place. Mode C The Line parity of the outgoing signal is correct even if the incoming parity is in error, and even if an insert is taking place. Each mode is activated via a two bit configuration word. C-bit Parity Insert The C-bit parity insertion circuitry 496 (Figure lOe) provides the capability to modify the C-bit parity in the event of an overwrite taking place or to pass the received parity through. Two modes exist for path parity insertion. Mode A C-bit Parity is passed through the DAI circuit 250 regardless of whether or not the parity is correct, and regardless of whether or not an insert is taking place. Mode B If an insert is taking place and the incoming C-bit parity is in error, then the outgoing C-bit parity is in error. If an insert is taking place and the incoming C-bit parity is correct, then the outgoing C-bit parity is correct . The mode is selected via a configuration bit . Far End Block Error Insert The Far End Block Error (FEBE) Insert circuitry 498 (Figure lOe) provides the capability of inserting a FEBE in one direction of the DS3 if in the alternate direction a parity error was detected. A parity error is defined as either an F bit error, an M bit error or a Line parity error. Refer to Bellcore T1X1.4/89-017 for more details. A FEBE is generated by setting the three C-bits in the fourth subframe of the C-bit Parity M-frame structure to all zeros. Due to the asynchronous relationship of the DS3 signals there could be up to a whole M-frame of latency between the time a parity error was detected and the time a FEBE is inserted in the opposite direction. Alarm Indication Signal Insert The Alarm Indication Signal (AIS) insert circuitry 500 (Figure lOe) provides the capability to insert AIS in response to certain trouble conditions detected by the DS3 performance monitoring circuitry. Declaration of a LOS or an OOF has the capability of optionally generating a DS3 Stuck Stuffing Alarm Indication Signal (AIS) . The DS3 AIS shall be activated after a delay of approximately 24 to 25 M-frames which is approximately 2.55 msec to 2.66 msec. The requirement is 1.5 to 2 times the maximum average reframe time. Maximum average reframe time is the average time to reframe when the maximum number of bit positions must be examined for the framing pattern. This time is arrived at statistically, and in the calculation it shall be assumed that the "non-frame" bits are ones and zeros with equal probability. The required upper limit for the maximum average reframe time for DS3 is 1.5 msec. After a LOS or an OOF, a DS3 good signal is declared when valid framing and line parity are found, and the average ones density is at least 33%. A ones density of less than 33% is measured by counting the number of BPVs in between occurrences of DS3 control bits. If the number of BPVs exceeds 8, then the ones density is determined to be less than 33%. DS3 good signal detection time does not exceed 1.5 times the maximum average reframe time. After a DS3 good signal has been identified, AIS is deactivated without delay. Note that during a LOS condition, a valid DS3 clock is supplied to the DAI 250 in order to assure proper functionality. The DS3 AIS clock rate is generated externally and supplied to the DAI as an input with a clock frequency of 44.736 Mbit/s +/- 20 ppm. Figure 12 illustrates the format of a DS3 frame, also known as a DS3 M-frame or M13 frame, having seven subframes. Each subframe has eight groups or blocks 550, wherein each block has a first OverHead (OH) bit 552 followed by 84 DS2 information bits, such as a bit 554 to represent a time slot devoted to DS2 input 1. Figure 13 is similar to Figure 12 but illustrates a set of specific overhead bits for each subframe and each block, of the subframe, of the asynchronous DS3 frame format. For example, the OverHead bit of block one 550 of the first subframe is an X-bit 552' . Figure 14 is similar to Figure 12 but illustrates a set of specific overhead bits for each subframe and each block, of the subframe, of the C-bit Parity DS3 frame format. For example, the OverHead bit of block three of the fourth subframe is a FEBE 554. Figure 15a is a block diagram of the DS3 Framer 474 and the DS3 State Counter 472, both of which are a part of the M23 Demultiplexer 452 shown in Figure 10b. The DS3 data 462 connects to a Pyramid shift register 594 and to a M-bit shift register 596 in the DS3 Framer 474. The output of the Pyramid shift register 594 connects to a compare circuit 598. The Equal output of the compare 598 connects to a counter 600 which connects to a Slip by Mxl70 Cycles block 602 driving a Group counter 604 in the DS3 State Counter 472. The output of the M-bit shift register 596 connects to a compare circuit 608. The Equal output of the compare 608 connects to a counter 610 which connects to a Slip by M Subframes block 612 to drive a Subframe counter 614 in the DS3 State Counter 472. The NotEqual output of the compare 598 and the compare 608 both interconnect a Bit counter 606 in the DS3 State Counter 472. The DS3 Framer 474 synchronizes the DS3 State Counter 472 to the incoming DS3 signal 462. The DS3 State Counter 472 provides the pointer that indicates which bit of the DS3 M- frame the incoming DS3 data bit is associated with. The synchronization process performed by the DS3 Framer 474 aligns the State Counter 472 with the DS3 M-frame structure of the data stream. Refer to Figure 13 for the Asynchronous DS3 frame format and Figure 14 for the C-bit Parity DS3 frame format. There are seven subframes per DS3 frame and each subframe contains eight blocks or groups of 85 bits. The first bit of each group is a control bit or overhead bit . The control bits associated with groups 2 and 8 are FI bits, and those associated with groups 4 and 6 are FO bits. Since FI bits are equal to 1 and FO bits are equal to 0, the framing pattern 1001... can be found by observing every 170th bit position. Synchronization to this bit pattern constitutes subframe alignment, which is the first step in total synchronization to the DS3 stream. The standard approach to subframe synchronization is a serial approach. The serial approach to framing observes one bit position until that position is determined to be valid or invalid. Upon determination that the bit position is invalid, the state counter is held constant for one clock cycle which effectively retards the state counter by one cycle or bit position. The new bit position which is adjacent to the previous position is observed for the framing pattern until it is determined to be valid or invalid. This cycle continues until the bit position is found to be valid. This serial approach which searches one bit position at a time has a maximum average reframe time (MART) of approximately 1.9 msec for the DS3 framing pattern. Maximum Average Reframe Time is the average time to reframe when the maximum number of bit positions are examined for the framing pattern. This time is arrived at statistically, and in the calculation it is assumed that the non-frame bits are ones and zeros with equal probability. The requirement for the DS3 rate is a MART of less than 1.5 msec, and consequently, the serial approach implemented does not meet the required MART. The enhanced approach to subframe synchronization that is implemented in the preferred embodiment is a serial look-ahead approach. Instead of observing a single bit position every 170 bits, N adjacent bits are stored for future use if needed, while the current position is evaluated as before. By storing the value of the adjacent bit positions prior to the time that they are needed, the Framer 474 is essentially looking ahead which reduces the MART. After every 170 bits, a decision is made as to the validity of the current bit position. In the serial approach, when the current bit position is found to be invalid, another decision can't be made for at least 3x170 bits (since 00, 01, 10, and 11 are all valid patterns in the framing pattern 1001...) ; however, in the serial look-ahead approach, another decision can possibly be made in 170 bits since two previous values of the new bit position were previously stored. Increasing the number of adjacent bits, N, that are stored for future use decreases the MART but increases the gate count of the framing circuitry. N is selected in order to optimize the circuit for either speed or size. A value of N=3 was implemented in the preferred embodiment and is used for the following illustration. This value provides a MART that meets the specification of 1.5 msec. A pyramid 580 shown in Figure 15b illustrates a form of shift register that shifts up or down based upon different criteria, and is the mechanism used to store values of the current bit position as well as bit positions adjacent to the current framing position. Each square in the pyramid represents a storage element. At any given time the Pyramid shift register 594, corresponding to the pyramid 580, contains the value of three consecutive framing bits associated with the current alignment of the State Counter 472 to the DS3 data stream. When the State Counter 472 reaches a new framing bit position, i.e., 170 cycles since the last framing bit position, Pl 584 is shifted into P2 586, P0 582 is shifted into Pl 584 and the new framing bit is shifted into P0 582. The previous framing bit position -1 which is Q0 588 is shifted into QI 590 and the current framing bit position -1 is shifted into Q0 588. The current framing bit position -2 is shifted into R0 592. At this time P0 582 is compared to P2 586. If they are different, the current position could still be a valid framing bit position (since the framing pattern is 10011001...) . After another 170 cycles, the above procedure is repeated until seven consecutive comparisons of P0 582 to P2 586 were found to be different, at which time the state of the State Counter 472 is advanced or retarded some multiple of 170 in order to align the State Counter to the groups. At this time subframe synchronization is declared and the first step to total synchronization is complete. If however, the comparison indicates that the PO and P2 bits are of the same value, the current bit position is declared as an invalid framing position and the adjacent bit position is selected as the new framing position. The State Counter 472 relationship to the DS3 data stream is modified by retarding the State Counter by one cycle. QO used to contain the value of the current framing bit position -1, but due to the adjustment made to the State Counter 472, QO actually contains the value of the current framing bit position. QO is shifted into PO, QI is shifted into Pl, and RO is shifted into QO. When the State Counter 472 reaches a new framing bit position, i.e. 170 cycles since the last framing bit position, Pl is shifted into P2, PO is shifted into Pl and the new framing bit is shifted into PO. The previous framing bit position -1 which is QO is shifted into QI and the current framing bit position -1 is shifted into QO. The current framing bit position -2 is shifted into RO. At this time PO is compared to P2. If they are different, the current position could still be a valid framing bit position. After another 170 cycles the above procedure is repeated until seven consecutive comparisons of PO to P2 were found to be different, at which time the state of the State Counter 472 is advanced or retarded some multiple of 170 in order to align the State Counter to the groups. At this time subframe synchronization is declared and the first step to total synchronization is complete. The second step of the synchronization process is to find multiframe alignment. The control bits associated with group 1 of subframe 5 and 7 are M0 bits, and the control bit associated with group 1 of subframe 6 is an Ml bit. Since the Ml bit is equal to 1 and the M0 bits are equal to 0, the framing pattern 010 can be found by observing the first control bits of each subframe. Synchronization to this bit pattern constitutes multiframe alignment, which is the second and last step in total synchronization to the DS3 stream. Multiframe alignment is performed by shifting the control bit associated with group 1 of each subframe into a M-bit shift register 596. Since there are seven subframes, the shift register 596 is seven bits long. If the multiframe framing pattern 010 associated with the M bits is found to be valid in two consecutive multiframes, the state of the State Counter 472 is advanced or retarded some multiple of 680 in order to align the State Counter to the subframes. At this time the State Counter 472 is declared as being in frame and the last step to total synchronization is complete. If an F bit error is detected or the M bit alignment pattern is found to be invalid during the multiframe alignment process, the Framer 474 retards the state of the State Counter 472 and the subframe synchronization process starts over again. III. THE ASYNCHRONOUS TIME SLOT INTERCHANGE (TSI) CIRCUIT Figure 16 illustrates a functional block diagram of an asynchronous DSO switch 1000 for switching DSO channels embedded in DS3 signals fed across lines 134, into DSO test resources 186, and out across lines 134' . In its maximum configuration the presently preferred access system 170 has access to as many as 64,512 DSO's via its 96 DS3 interface modules 171 (96 X 672 = 64,512) . In addition, there are up to 24 DSO test resources 186 in the access system 170 that are used for testing the accessed DSO channels. In order to allow for access to the shared test resources 186, the switching function 1000 is required. The switch architecture must be capable of establishing bi-directional connections between any of the 64,512 accessed DSO channels and any of the 24 DSO test resources Conventional switch architectures, such as the Time Slot Interchange implemented by AT&T, require that all accessed DSO channels be synchronous to a common reference (e.g. Stratum 1 clock) . If any of the DSO channels are not synchronous to the reference, then slips, i.e., a bit is lost, can occur and the DSO signal is distorted resulting in, for instance, an audible click or a lost data packet. Hence, a functional asynchronous switch 1000 is included in the access system 170 to accommodate asynchronous DSO channels without introducing distortion. Referring now to Figure 17, the core of the asynchronous switching function 1000 is located in the asynchronous Time Slot Interchange (TSI) circuit 252. The TSI 252 can access all 672 DSO channels within a given DS3 signal and provides switching capability for up to 24 of the 672 DSO channels with no restrictions on which DSl or DS2 channel embeds a DSO channel. All TSIs 252 in the access system 170 are connected together, along with a digital signal processor (DSP) 1001 in each DSO test resource 186, over what is referred to as the PCM Highway or PCM bus 220. The TSI 252 provides the switching function and the PCM Highway 220 provides the routing facility for handling up to 128 DSO channels within the access system 170. The PCM Highway 220 provides the mechanism for routing DSO channels throughout the access system 170. The PCM Highway 220 has an intra-shelf portion 1002 and an inter-shelf portion 1004. They are connected together through a set of buffers 1006 on the shelf monitor module 232, 232' . With 128 time slots the PCM Highway 220 supports transmission of up to 128 bi-directional asynchronous DSO channels. The PCM Highway 220 is arranged in a master/slave fashion, where masters, such as the TSI 252, transmit onto four transmit lines (not shown) each supporting 32 times slots, and receive from four receive lines (not shown) each supporting 32 time slots. Figure 18 is a timing/bit position diagram illustrating the relationship among the time slots of the PCM Highway 220. The PCM frame sync signal (PFRM) 1008 aligns the 128 slots to a single frame. Figure 18 also shows the 32 transmit time slots for each of four signals TXA 1010, TXB 1012, TXC 1014 and TXD 1016, a TXSTAT signal 1018, and the 32 receive time slots for each of four signals RXA 1020, RXB 1022, RXC 1024 and RXD 1026. Each time slot represents the 8 bits of a DSO which are transmitted serially. To handle asynchronous DSO channels, the PCM Highway 220 runs at a rate (preferably 11.16 kHz) which is higher than the rate of any incoming DSO channel (approximately 8 kHz) . Since the PCM Highway 220 is running at a rate higher than the data that is being transported, a "stuffing" method has been implemented to allow for cases where there is no valid data to transmit even though the selected time slot is available on the bus 220. The stuffing technique is accomplished by using a transmit status line (indicated by the TXSTAT signal 1018) that is used to indicate whether or not the associated time slot contains valid data or stuff data in the current frame. Arbitration of the PCM Highway 220 is controlled by software via proper allocation of time slots among the various master or slave devices throughout the access system 170. A single clock and frame sync signal are fed to all devices to synchronize the PCM Highway 220. The TSI 252 drives the transmit status line (TXSTAT signal 1018) based on an internal scanning method that is described below. PCM Highway slave devices, such as the DSP 1001 in the DSO test resource 186 (Figure 17) , receive from the lines that the TSI 252 transmits onto, and transmit onto the lines that the TSI 252 receives from. In addition, the DSP 1001 in the DSO test resource 186 monitors the transmit status signal 1018 in order to extract DSO timing. The details of a specific time slot, including the shared PCM clock signal (PCLK) , showing how the DSO bits are mapped along with the transmit status signal 1018 are shown in Figure 19. Note that the TXSTAT signal 1018 provides bit valid and frame codes in a time slot N-l 1030 prior to the time slot N 1032 containing the marked data bits. To stuff a byte such as the byte in time slot N 1032, the VA bit 1036 of TXSTAT 1018 in time slot N-l 1030 is set to "1", to indicate that the byte is not valid. The interfaces to the TSI 252 are shown in the I/O diagram of Figure 20. The TSI 252 provides the DSO switching function in the presently preferred access system 170, interfacing to 672 DSO channels on the DS3 side and 128 time slots on the PCM Highway 220 so as to provide a time slot interchange function between the DS3 signal and the PCM Highway 220. The TSI contains additional functions beyond DSO switching including relative frequency counter, DSO subrate handler, CRC generation, Facilities Data Link (FDL) handler, support for secondary channel, and support for DSl superframe alignment . Microprocessor Interface A microprocessor interface 1027 is used for passing control and status information between the TSI 252 and the microprocessor in the CPU complex 256 (Figure 6) . The microprocessor interface 1027 includes an 8 bit address bus, an 8 bit bi-directional data bus, a chip select, a read/write control signal, and an address latch enable signal. The TSI 252 asserts a data transfer acknowledge signal to notify the microprocessor that the read/write cycle can be completed. In addition, there are two mode control pins to allow for "secure" write operations and to allow for interfacing to a wide variety of standard microprocessors . PCM Highway Interface A PCM Highway interface 1029 is used to connect the TSI 252 to the PCM Highway 220 (Figure 17) . There are four lines for received data and four lines for transmit data; each pair of Tx/Rx signals connects to one of the four 32 time slot PCM Highway lines 220. The transmit status line indicates when valid data is being output. Each transmit line has an associated transmit enable signal that indicates when the PCM Highway 220 is being driven. In addition, clock and frame sync signals are sent to the TSI 252 to synchronize all TSIs 252 and DSO test resources 186 (Figure 17) on the PCM Highway 220. DAI Circuit Interface A Pseudo DS2 (PDS2) Bus interface 1031 is used to interface the TSI 252 to the DAI 250 (Figure 6) . The DAI 250 sends seven DS2 data streams to the TSI 252 along with the associated clocks and DSl sync status to allow for identification of bits at the DSl level. The TSI 252 passes DS2 data along with overwrite control back to the DAI 250. The overwrite control is used by the DAI 250 to determine which bits in the DS3 should be overwritten. FDL Microcontroller Interface A Facilities Data Link (FDL) interface 1033 is used to connect the TSI 252 to an external microcontroller 256 (Figure 6) for processing the FDL data. The microcontroller 256 drives the strobe and clock lines, while the TSI 252 shifts out FDL data bits from each of 28 ESF formatted DSl's. System Interface A System interface 1035 includes miscellaneous TSI 252 signals including a reference clock for DSl frequency counter measurements, a reset signal for TSI initialization, and a clock for overall TSI operation. Test Interface A Test interface 1037 provides controllability and observability for fault coverage. In addition, a control signal is available that can be used to disable all TSI outputs to facilitate board level testing. Power A Power interface 1039 includes pins that are used for power and ground. Figure 21a is a block diagram of the asynchronous TSI circuit 252. In the transmit direction the TSI 252 receives DSO data from the DAI circuit 250 over the Pseudo-DS2 (PDS2) interface, at an input demux 1040, and sends DSO data out onto the PCM Highway 220 (Figure 17) , at a PCM Highway transmitter 1045. In the transmit direction, the overall function of the TSI 252 is to load the incoming DSO data into the transmit sample buffer 1044 whenever it arrives, extract the DSO data out of the transmit sample buffer 1044, and place it onto the PCM Highway 220 at a previously assigned time slot. DS2 data from the DAI 250 (Figure 6) enters into the TSI 252 through the input demux 1040. Figure 22 is a timing diagram showing details of the TSI/DAI PDS2 interface. In Figure 21a, the input demux extracts the 28 DSl data streams from the seven DS2 data and clock lines, which are part of interface 1031 (Figure 20) . Two DS1NUM signals (interface 1031, Figure 20) form a two bit binary number that specifies which of the four DSl's currently has active data on the DS2 line. The TSI 252 uses these signals to demultiplex the active DS2 into individual DSl lines and feeds each of the incoming DSl signals (28) serially into a DSl input shift register 1041. Once the 8 bits of a DSO channel byte have been shifted in for a given DSl, the DSO byte is loaded into a DSO holding register 1042. There are 28 holding registers 1042, one for each DSl channel. The holding registers 1042 are 10 bits wide: 8 bits for the DSO byte, 1 bit for the multi-frame sync status associated with the "parent" DSl channel, and 1 bit that is used as a valid data flag to indicate that a new DSO byte has come in and has not yet been processed. The TSI 252 has 24 internal "channel slots" available for processing DSO channels. The channel slots provide the intermediary mechanism for establishing a connection between an incoming DSO channel and a time slot on the PCM Highway 220. The external microprocessor (uP) interface 1060 is shown in Figure 21a, controls how the 24 channel slots are allocated. The uP sets up a switched connection by making two assignments to a given channel slot. The first assignment ties a channel slot to a PCM Highway time slot; the second assignment ties a channel slot to a specific DSO channel within a specific DSl channel of a DS3 signal . The PCM Highway time slot assignment is made by a uP "write" to the time slot assignment dual port memory (128 X 8) 1059. The DSO assignment is made by two uP writes to the DSO select content addressable memory (CAM) 1049; one write for the DSl number (1-28) and one write for the DSO number (1-24) . Once the proper assignments have been made to the DSO select CAM 1049 and the time slot assignment memory 1059, no further uP action is required; the DSO channels are continually processed and the connection is maintained until the configuration is changed by the uP. After the DSO bytes are loaded into the holding registers 1042, they are scanned to determine whether they should be transferred to the transmit sample buffer 1044. The TSI 252 contains a 5 bit DSl scan counter 1048 that is used to scan each of the 28 holding registers 1042 in sequence. Associated with each of the holding registers 1042 is a DSO channel counter 1047 that stores the DSO number of the DSO channel that is currently in the holding register 1042. If there is a match between the DSl scan counter 1048/DSO scan counter 1047 and the contents of the DSO select CAM 1049, one of the CAM'S 24 DSO channel slot "match" signals activates. The match signal is encoded into a 5 bit transmit sample buffer address at the address encoder 1050. While the match is active, the DSO byte is transferred from the holding register 1042 into the transmit sample buffer 1044. If the DSO byte in the addressed holding register 1042 had already been processed, the valid data flag, provided through the multiplexer 1043, would indicate "null" data and the transfer from the holding register 1042 to the transmit sample buffer 1044 does not take place. On the PCM Highway side, the time slot counter 1058 keeps track of which time slot is currently active on the PCM Highway 220. The contents of the time slot counter 1058 are used as an address into the time slot assignment (TSA) memory 1059 which contains a location for each of the 128 time slots. If a channel slot has been assigned to a time slot, the TSA memory 1059 will output the channel slot number when that time slot comes up. The channel slot number is then used as an address into the PCM Highway side of the transmit sample buffer 1044 for retrieval of the selected DSO byte. If the associated valid data flag in the transmit sample buffer 1044 indicates valid data, the DSO byte is serially sent out onto the PCM Highway 220 through the PCM Highway transmitter registers 1045. The valid data flag itself is also sent out onto the PCM Highway 220 via a transmit status line (interface 1029, Figure 20) . Still referring to Figure 21a, the DSO data flow in the receive direction is driven by the timing derived in the transmit direction. This is due to the in-line drop and insert architecture of the access system 170. A specific TSI 252 handles transmit and receive data both of which are associated with the same DS3 signal . This architecture dictates that the receive side timing be identical to the transmit side timing since the insert takes place into the same DS3 signal that the drop was derived from. It is not possible to insert a DSO byte with different timing since there is no way to modify the associated DSl timing when only the DSO bits are being inserted into the DS3 with all other DS3 bits passing through transparently. In the receive direction, the TSI 252 receives DSO data from the PCM Highway 220 (Figure 17) and sends DSO data out to the DAI 250 (Figure 6) over the PDS2 interface. The overall function of the TSI 252 in the receive direction is to load the incoming DSO byte into the receive sample buffer 1062 during its assigned time slot, extract the DSO byte from the receive sample buffer 1062, and send it to the DAI 250 at the same time that the associated transmit DSO byte is being loaded into the TSI 252. In addition, the TSI 252 generates an overwrite signal (interface 1031, Figure 20) if so configured by the external microprocessor (not shown) . The overwrite signal is used to signal the DAI 250 that the associated data bit on the PDS2 line should be overwritten into the DS3 signal . Data flow on the receive side starts with a serial-to- parallel conversion of the data coming from the PCM Highway and going into the PCM Highway receiver registers 1061. The data is taken off the PCM Highway at the same time that data is placed onto the PCM Highway on the transmit side. From the PCM Highway receiver registers the data is loaded into the receive sample buffer 1062 at. the location specified by the TSA memory 1059 when addressed by the time slot counter 1058. The DSO data then gets loaded into the receive side DSO holding registers 1063. From the holding registers 1063 the DSO bytes are fed into the DSl output shift registers 1064 where they are passed through the output multiplexer 1067 and sent on to the DAI 250 over a set of PDS2 receive data lines (interface 1031, Figure 20) . The TSI 252 also includes three additional subcircuits: a TSI FDL handler 1068 (Figure 21b) , a frequency counter 1069 (Figure 21c) , and a subrate handler 1056 (Figure 21d) . The TSI FDL handler 1068 obtains its input from the output of the TSI demultiplexer 1040 and a clock signal from the external FDL microcontroller 254. Data is output to microcontroller 254 and to TSI shift register 1041. The frequency counter subcircuit 1069 obtains its input from the output of the TSI demultiplexer 1040 and from the TSI system interface 1035 reference clock. The subrate handler 1056 obtains its input from TSI DSO holding register 1042 and the DSO channel match signal. The output of subrate handler 1056 drives one of the inputs to AND gate 1057. DSl Facilities Data Link (FDL) Handler Figure 23 is a block diagram of the Facilities Data Link (FDL) interface between the FDL handler subcircuit 1068 of asynchronous Time Slot Interchange (TSI) circuit 252 and the FDL microcontroller (uC) 254 in the presently preferred access system 170. The three I/O pins of the TSI interface 1033 (Figure 20) that interconnect to the microcontroller 254 are FDLDIR, FDLCLK and FDLDAT. The FDL is a 4 Kbit/s data link that is embedded in Extended Super Frame (ESF) formatted DSl signals. In the access system 170, the DS3 Interface Module 171 (Figure 5) provides performance monitoring of the DS3 signal as well as all embedded DS2 and DSl signals. A portion of the performance monitoring of ESF formatted DSl channels involves interpreting messages that are being sent into the access system 170 on the FDL. On a given DS3 Interface module 171 there can be as many as 28 DSl channels passing through; each one of which can contain an independent 4 Kbit/sec FDL channel . Conventional techniques for handling FDL-like data links (e.g. HDLC) involve the use of off-the-shelf integrated circuits (ICs) that provide an interface between a microprocessor and one or two data links (e.g., USART chips, DLC chips, and the like) . In the presently preferred access system 170, this technique is not practical since the required number of ICs would not fit on a single board and the cost would be prohibitive. The present invention includes a novel approach to handling multiple asynchronous data links in the access system 170 so as to accommodate 28 4 Kbit/sec data links on a single DS3 Interface Module 171 without introducing excessive cost. The approach involves a sampling/packing subcircuit (the FDL handler 1068) in the TSI 252 that operates in conjunction with the external microcontroller (uC) 254 to provide a high level message interface to the board microprocessor (uP) in the CPU complex 262 (Figure 6) . Referring now to Figures 21c and 24, the FDL handler subcircuit 1068 of TSI 252 continuously extracts FDL bits from each of the 28 DSl channels and stores them in an internal buffer referred to as the Input Shift Register (ISR) 1070. The ISR 1070 can hold up to 7 FDL bits for each DSl channel. As each new bit is shifted in, an FDL Bit Counter 1071 is incremented. When the external uC 254 asserts the TRANSFER signal (derived from FDLDIR, Figure 23) , the FDL Flag Logic 1072 samples the FDL Bit Counter 1071 and passes the valid FDL data bits from the Input Shift Register 1070 to an Output Shift Register 1073 (only 1 of 28 shown) . The Flag Logic 1072 then determines the state of the unused bits in the Output Shift Register 1073 as described below. Since all FDL channels can be running at slightly different rates the 28 FDL bytes may not have the same number of valid FDL bits. The size of the Output Shift Register 1073 is 8 bits, however, the number of valid FDL data bits is 7 or fewer. Based on the FDL Bit Counter 1071, the Flag Logic determines the number of valid FDL bits in the output shift register 1073 and sets the next bit to a "0" and if there are any remaining unused bits they are all set to "1". The external FDL uC 254 (Figure 23) can then determine the number of valid FDL bits contained in each byte by starting at the least significant bit (LSB - Bit 0) and looking for the first bit position containing a zero. All remaining bits in the byte are valid. For example, if there are 7 valid data bits, the LSB (Bit 0) will be zero and the remaining 7 bits are interpreted as valid FDL data bits. If the least significant bit is a one, and the next bit (Bit 1) is a zero, then there are 6 valid FDL bits. The order of arrival of the FDL data bits is from least significant bit to most significant bit . This implies that the most significant bit (Bit 7) is the most recent bit to have been loaded into the TSI 252. The 28 Output Shift Registers 1073 are connected together inside the FDL handler subcircuit 1068 of TSI 252 to form a shift register 224 bits long (28 X 8) . This allows the FDL data for all 28 DSl channels to be extracted from the TSI 252 over a serial interface. Figure 25 shows the format of the FDL data as it is shifted out of the TSI 252 and into the external uC 254 (Figure 23) . To avoid buffer overflow, the FDL uC 254 must poll the TSI 252 at a frequency such that a maximum of 7 FDL bits are stored between polling cycles. This can be accomplished using a nominal polling cycle of 1.7 ms since a worst case fast DSl will produce 7 FDL bits in 1.7498 ms. IV. THE PROTECT PATH Figure 26 illustrates a normal DS3 signal path and a protect DS3 signal path in the access system 170. The DS3 channel has two primary requirements for protection. The first involves the failure of the access system 170 of the path and the second involves a craftsperson requested switch. In the first case, the DS3 path must be moved from the failed unit to a secondary protection path. Since the equipment has failed, it is assumed that a major hit on the DS3 channel will occur. The second requirement involves a protection switch due to a craftsperson request. This switch request could be required to correct some non-service affecting fault (such as an LED has burned out) on the DS3 interface module. Under this circumstance, a major hit of the DS3 channel is not allowed. It is assumed that a few bit errors, but no loss of synchronization, will occur on the down stream equipment. Both of these scenarios deal with protection of the DS3 signal that pass through the access system 170. The DS3 signal input 134 is wired to both the normal and protection path modules 171a, 171b. When the DS3 signal is transmitted from the DS3 module 171, relays 178, 178' are used in both the normal and protection output paths to guarantee that only one DS3 module 171a,b drives the line 134' at any given time. Special turn on/off sequencing is required to meet the hitless requirements. Given these requirements, the protection scheme for the access system 170 is discussed hereinbelow. The protection of a DS3 path is accomplished using a next card protection approach. As Figure 26 shows, the DS3 Interface modules 171a,b are tightly coupled into functional pairs. Each module 171 has a normal path 1080a, 1080b for a DS3 channel. In addition, the modules 171 have a second path 1082a, 1082b available that is used to protect its companion module. In other words, the "1A" module 171a has a normal path 1080a for DS3 channel 1A and a protection path 1082a for DS3 channel IB. In the same way, the "IB" module 171b has a normal path 1080b for DS3 channel IB and a protection path 1082b for DS3 channel 1A. The same coupling occurs for each of the other five pairs of DS3 modules 171 in a shelf. Thus, an alternate path is available for all DS3 channels. The difference in the two paths 1080, 1082 fall into two categories: channel statistics and overwrite capability. The normal path 1080 gathers full statistical information about the DS3 channel. A full range of DS3, DS2, and DSl statistics are taken. In addition, entire DSl and DSO channels can be extracted from the incoming DS3 channel and replaced in the outgoing channel . On the other hand, the protect path 1082 is basically a channel repeater. The DS3 signal is received, delays are matched with the normal path 1080, and the signal is retransmitted. Only a very minimum of statistics, such as loss of signal (LOS) , are detected and reported on the protection path 1082. No insertion of any kind is done. The primary purpose of the protection path 1082 is to protect the DS3 channel in the event of a failure in the module of the normal path. Referring now to Figure 27, another DS3 interface module 171c is used as a monitor of the other modules 171a,b on the DS3 shelf 202 (Figure 5) . Signals are routed from the monitor ports of the DS3 LI circuits 272a, 272a' , 272b, 272b' into the DS3 LI circuits 272c, 272c' on the monitor module 171c. The monitor outputs of the LI circuits 272 are tied to one of two wires that interface to the DS3 monitor module 171c. The DS3 RCV MON line 1084 from the LI circuits 272a, 272b on the normal path 1080a,b (Figure 26) is used as the input to the normal path of the DS3 monitor module. Two comparisons are performed as follows using module 171a as an example: 1. The input signal on the line 134a against the normal data path output on the line 134a' ; 2. The input signal on the line 134a against the protection path output on the line 1082b (Figure 26) . The sequence of events, using the DS3 "1A" module 171a as an example shows how the comparisons take place. Note that the setup and control of this test will be accomplished by the shelf monitor module 232. Sequence for Comparing the Normal Path Output to the Monitor Path 1. The shelf monitor module 232 first passes the DS0/DS1 insertion parameters of the DS3 Interface Module 171a to the DS3 Monitor module 171c. 2. The shelf monitor module 232 then commands the DS3 interface module #1A 171a to turn on its output driver for the DS3 RCV MON OUT signal on a line 1084, from the normal path LI 272a. This puts an amplified image of the DS3 1A input signal out on the line 1084. This line is wired to the normal path LI 272c on the DS3 monitor module 171c. The shelf monitor 232 also commands all other modules, e.g., 171b, to disable their drivers to the line 1084. 3. Next, the shelf monitor 232 commands DS3 interface module #1A 171a to turn on its output driver for the DS3 XMT MON OUT signal on a line 1086, from the normal path LI 272a. This puts an image of the DS3 1A output signal out on the line 1086. The line 1086 is wired to the protection path LI 272c' on the DS3 monitor module 171c. The shelf monitor 232 also commands all other modules, e.g., 171b, to disable their drivers to the line 1086. 4. Finally, the shelf monitor 232 commands DS3 interface module #1A 171a to turn on its output driver for the FEBE MON OUT signal on a line 1088. As seen from Figure 27, this signal originates from a DAI circuit 250a to the FEBE input of a DAI 250c on the DS3 monitor module 171c. The shelf monitor 232 also commands all other modules, e.g., 171b, to disable their drivers to the line 1088. 5. Now that the physical link has been established to the monitor module, the test can begin. The signal coming into the normal path LI 272c on the DS3 monitor module 171c is effectively the same input 134a that is seen by the #1A module 171a. All performance data is gathered by the DAI 250c and compared to that found on the #1A module 171a. This comparison is performed by the shelf monitor 232. If a major difference is found (i.e. frame loss, etc.) , then a failure may have been detected. 6. The DS3 monitor module 171c must first be validated to guarantee prior function by doing the same test on another module, e.g., 171b. If no problem is found with the DS3 monitor module 171c, then the shelf monitor 232 must decide whether a fault has been found and then command the #1A module 171a or #1B module 171b to perform a protection switch of the #1A module normal DS3 path 1080a (Figure 26) . 7. During DS3 processing, a Far End Bit Error (FEBE) signal is generated by the DAI 250c. This FEBE signal must be compared to the one received on the line 1088 from the #1A module 171a. If a mismatch occurs then the same procedures shown in step 6 are followed to determine if a switch is necessary. 8. The next step is to perform the same insertion of DS0/DS1 data that occurs on the #1A module 171a. Once this has been accomplished, the data signal in the DAI 250c on the normal path 1080 is the same as what is coming in on the protection path 1082. 9. Remember that the protection path 1082 of the DS3 monitor module 171c has an image of the output of the #1A module 171a on it. When the signal arrives in the DAI 250c, it has been delayed by a known number of clock cycles. An adjustment is made in the normal path 1080 of the DAI 250c on this module to match these cycles. With variations from DAI to DAI, addition clock cycles may be needed. The DAI 250c has up to 3 bits of variance allowed. 10. Once the delay variance has been compensated, a bit for bit comparison of the two signals (#1A output from line 1086 and DS3 monitor output) is done in the DAI 250c. 11. Assuming that the module #1A 171a is not in alarm, no performance failure was detected by the DS3 monitor module 171c, and the comparison fails, then one of two things is possible. Either module #1A 171a has failed or the DS3 monitor module 171c has failed. To determine if it is the monitor module 171c, the same test is run against another DS3 interface module, e.g., 171b. 12. If no failure is found in the DS3 monitor module 171c, then a failure has been detected and the shelf monitor 232 issues a command to module #1A 171a or #1B 171b to perform a protection switch of the #1A DS3 path 134a. In addition, the #1A DS3 module 171a turns on its unit failure lamp. Sequence for Comparing the Protection Path Output to the Monitor Path 1. The shelf monitor 232 commands the DS3 interface module #1A 171a to turn on its output drive of the DS3 RCV MON OUT signal on the line 1084, from the normal path LI 272a. As described previously, this puts an amplified image of the DS3 1A input signal out on the line 1084. The line 1084 is wired to the normal path LI 272c on the DS3 monitor module 171c. The shelf monitor 232 also commands all other modules, e.g., 171b, to disable their drivers to the line 1084. 2. Next, the shelf monitor 232 commands the DS3 interface module #1B 171b to turn on its output drive of the DS3 XMT MON OUT signal 1086, from the protection path LI 272b' . This puts an image of the DS3 1A protection output signal out on the line 1086. The line 1086 is wired to the protection path LI 272c' on the DS3 monitor module 171c. The shelf monitor 232 also commands all other modules, e.g., 171a, to disable their drivers to this line 1086. 3. Now that the physical link is established to the monitor module 171c, the test can begin. As in the previous test, the signal coming into the normal path LI 272c on the DS3 monitor module 171c is effectively the same input 134a that is seen by the #1A module 171a. All performance data is gathered by the DAI 250c and compared to that found on the #1A module 171a. This comparison is done by the shelf monitor 232. If a major difference is found (i.e. frame loss, etc), then a failure may have been detected. 4. The DS3 monitor module 171c must first be validated to guarantee proper function by doing the same test on another module, e.g., 171b. If no problem is found with the DS3 monitor module 171c, then the shelf monitor 232 decides whether a fault has been found and then commands the #1B module 171b to perform a protection switch of the #1A DS3 normal path 1080a (Figure 26) . 5. Since the protection path 1082b (Figure 26) does not allow any insertion of DS0/DS1 data, no insertion is needed for this test. Remember also that the protection path 1082 of the DS3 monitor module 171c has an image of the output of the #1B DS3 protection path 1082b on it. This signal is a regenerated #1A DS3 signal. When the signal arrives in the DAI 250c, it has been delayed by a known number of clock cycles. The same cycle adjustment described earlier is done again. 6. Once the delay variance has been compensated, a bit for bit comparison of the two signals (#1B protection output from line 1086 and DS3 monitor output) is done in the DAI 250c. 7. Assuming that #1B protection path is not in alarm, no performance failure was detected by the DS3 monitor module 171c, and the comparison fails, then one of two things is possible. Either module #1B 171b has failed or the DS3 monitor module 171c has failed. To determine if it is the monitor module 171c, the same test is run against another DS3 interface module, e.g., 171a. 8. If no failure is found in the DS3 monitor module 171c, then a failure has been detected in the protection path on the #1B DS3 module 171b and the shelf monitor 232 issues a command to module #1A 171a to perform a protection switch of the #1B DS3 normal path 1080b. This is required in order to isolate the #1B module 171b for removal. In addition, the #1B DS3 module 171b turns on its unit failure lamp. Figure 28 is the block diagram of the Bit for Bit Compare circuit 470 shown in the DAI block diagram (Figure 10a) and discussed above in step 10 of the Normal Path output test and step 6 of the Protection Path output test. A normal data input (input A) connects to a delay 1100 which further connects to a seven bit shift register 1102. The output of the shift register 1102 connects to a compare block 1104. A protect data input (input B) connects to a four bit shift register 1106 which then connects to the compare block 1104. The compare block 1104 then appropriately generates a compare signal which is the output of the circuit 470. The Bit for Bit Compare circuit 470 provides the capability to verify the functionality of the DAI 250 while in service and to verify the alignment of the normal and protect paths prior to making a "hitless" switch. In order to verify the functionality of the DAI 250 (Figure 26) , two identically configured DAIs are required with identical inputs on the normal input (input A) . The normal output of a first DAI 250a (after insertion) is fed into the protect input (input B) of a second DAI 250b. This input is internally compared to the normal output. The circuit can detect a comparison even if there is up to 3 cycles of latency between the two streams. To check the functionality and relative alignment between the normal path of one DAI 250a and the protect path of the second DAI 250b, a third DAI 250c is required as shown in Figure 27. Note that since insert capability does not exist on the protect path, the DAI 250a whose normal path is being checked is configured such that overwrite is not allowed. The normal output of the first DAI 250a connects into the protect path of the third DAI 250c, while the protect output of the second DAI 250b connects into the normal input of the third DAI 250c. The first and second DAI 250a,b must have the same input signal on the normal inputs. The Bit for Bit Compare circuit 470 in the third DAI 250c then compares the two streams and reports the relative alignment within 3 bits. V. RELATIVE SYNCHRONIZATION DSl Synchronization Monitoring The DSl Synchronization Monitor continuously synchronization monitors all (embedded or direct interface) DSl signals in the access system 170 (Figure 32) . Synchronization monitoring occurs by comparing the clock frequency of the DSl under test to a reference DSl signal. The reference can be any (embedded or direct interface) DSl in the presently preferred access system 170 or a DSl based reference received through a port provided in the access system 170 on the Office Alarms Interface module 214 (Figure 32) . Frequency deviations from the reference are noted and reported as the number of "slips" of an entire DSl subframe for the specified time interval. For example, using a 1.544 X 10 6 Hertz (Hz) clock rate, a one second measurement period, and an approximate 16 bits or clock cycles per second error rate yields a prediction of five slips per minute. This is the case since over one minute there will be an estimated 960 bit frequency error thus requiring five 193 bit DSl subframe slips. Controlled slips will be further discussed below in conjunction with Figures 30a and 30b. The terms clock cycle, clock pulse, and bit are used to describe a single TI clock cycle (1/1.544 MHz or 0.648 microsecond) which is the time interval of one TI bit. The cause of slips is the instability of the timing generators and path delays in the external equipment (external to the access system 170) such as the terminals (not shown) . Terminals contain memory buffers to accommodate minor frequency departures . These departures include jitter and wander. Jitter is defined as short term, abrupt, spurious variation in the frequency of successive pulses, and includes all variations above a 10 Hz rate. Wander is similar to jitter but is long term variation in the frequency of successive pulses, and includes all variations below a 10 Hz rate. There is no problem with jitter and wander in a system so as long as the variations do not exceed the capacity of the buffer. However, buffers will either overflow or underflow in response to frequency departure or excessive variation which then results in a slip. The terminal throws away or deletes a block of 192 data bits (i.e., one TI subframe less the framing bit) in its buffer during overflow, which occurs when data comes into the buffer faster than it can be removed. The buffer repeats a block of 192 data bits during underflow. The external equipment has the buffers and does the actual deletion or repetition of the data bits. The access system 170 of the present invention determines or predicts that a slip is about to happen. A TI controlled slip takes place when a TI subframe buffer overflows or underflows. All 192 data bits in one TI subframe are deleted (overflow) or repeated (underflow) when the subframe buffer slips. In other words, one byte (eight bits) is deleted or repeated from each DSO signal during the controlled slip. Figure 30a illustrates a TI bit sequence before a controlled slip is about to occur. TI subframe SI 1136 begins with a framing bit F 1137 followed by 192 data bits 1138. This pattern is repeated for the rest of the subframes (labelled F/S2, F/S3, F/S4, F/S5, ...) as will be explained below in conjunction with Figure 31. Figure 30b illustrates the TI bit sequence after a buffer overflow has occurred causing a controlled slip. In the illustrated controlled slip, all 192 data bits in the subframe S3 1139 are deleted. Referring to Figure 32, the mechanism for reporting slips is through the Transaction Language 1 (TL1) command "RTRV-PM- TI" using the Monitored Parameter Type "SLIPC" sent by a craftsperson from the operations support system (OSS) to the access system 170 via the interface 196. The Communication Processor module 194 provides the communication interface 196 to the external OSS or network management center. The TL1 command "SET-TH-T1" is used by a craftsperson at the OSS to set a threshold level for the allowed number of slips in a specified time period. When the threshold is exceeded, an autonomous message is output from the access system 170 to the OSS. DSl Relative Synchronization Monitoring As a means to identify slips, the access system 170 utilizes the DSl Superframe (SF) format or the DSl Extended Superframe (ESF) format. Figure 31 illustrates the DSl Superframe format, which is specified in Bellcore TR-TSY- 000499. There are twelve TI subframes per DSl Superframe, with each subframe having a first overhead or control bit (F- bit) followed by 192 DSO data or information bits. The 192 data bits are divided into 24 channels of eight bits each wherein the bits are in a standardized pattern to minimiz crosstalk problems. The control bits in the DSl Superfram format are one of two types of F-bits. Terminal Framing (F t ) bits are used to identify subframe boundaries. Signal Framin (F s ) bits are used to identify superframe boundaries. The DS ESF format is similar but has 24 subframes rather than the 1 subframes of the DSl SF format shown in Figure 31. In the presently preferred embodiment of the acces system 170, clock pulses of a reference DSl and a test DSl ar compared to predict the slip rate, but other ways may be use in alternate embodiments. Using clock pulses rather than F- bits allows the access system 170 to predict the slip rate 193 times faster than utilizing the F-bits. This is due to the framing (F-bit) rate being equal to the clock frequency divided by 193. Stated another way, by using clock pulses to monitor frame slips at the DSl level, the access system 170 can achieve the same accuracy in one second as another monitor function using F-bits achieves in 193 seconds. Returning now to the relative synchronization concept, a reference source used by the access system 170 may have less stability than the clocks used to generate the DSl signal received by the system 170. When such instability in the reference source occurs, a systematic frequency error can be introduced across all DSl signals. To factor out this potential error, the synchronization of multiple DSl signals with respect to the reference signal must be examined. The relative synchronization monitoring function of the present invention can also be used by a craftsperson at the OSS to compare the two directions of a selected DSl channel to determine if each direction of the bi-directional path is synchronized to the same reference. As an additional feature, the access system 170 is capable of automatically picking a reference during the use of relative synchronization when no reference source has been previously defined by the user. With reference to Figure 32, priority is given to the synchronization reference which is input to the access system 170 on line 1140, but any of the DSls (embedded or direct interface, e.g., embedded on line 134 or direct on line 188) can be selected. The reference source is chosen by an auto- search program, described hereinbelow, running on the Administration Processor module 190. Access System Capabilities Now referring generally to Figure 32, the presently preferred access system 170 has the capability of using any single (embedded or direct interface) DSl as a synchronization reference. In addition, a DSl-based reference to a Building Integrated Timing Source Clock (BITSCLK) interface can be received by the system 170 at line 1140 and the clock pulses used as the reference signal. This interface is located on the Office Alarms Interface module 214. Each DS3 Interface module 171 is capable of receiving the reference and using it to monitor any of its embedded DSls, one at a time. In Figures 21a and 21c, the frequency counter subcircuit 1069 is part of the TSI circuit 252 (Figure 6) on the DS3 module 171 and includes an 11-bit frequency counter 1054 with a sign bit. The previously selected DSl reference clock increments the frequency counter 1054 while the clock of the DSl under test, selected by a 1 of 28 clock circuit 1052, decrements the counter 1054. The resultant value over time can be converted to the frequency difference. For instance, if the reference clock is running at 1,544,000 Hz (TI specified frequency) and the DSl clock under test is running at 1,544,016 Hz, the error rate or frequency difference is 1.04 X 10 "5 , which corresponds to five slips per minute. Since the presently preferred embodiment of the access system 170 only includes one of the counter subcircuits 1069 on each DS3 Interface module 171, a quantizing algorithm is used to monitor all 28 DSl circuits for synchronization. Namely, periodically each DSl circuit drives the frequency counter 1069 for a selected time interval. This approach requires an accumulation of monitored intervals for all 28 DSl circuits to achieve meaningful statistics and takes into account Loss Of Signal (LOS) at DSl, DS2, and DS3 rates. A measurement of the frequency difference for each DSl circuit is stored in a database. In addition to each DS3 Interface module 171, the DSl Interface module 238 has the capability to perform synchronization monitoring of DSl signals it receives. The Reference Source Referring to Figure 32, the primary source for the synchronization reference is the Building Integrated Timing Source (BITS) input 1140 to the Office Alarms Interface module 214. The BITS clock signal is received at the module 214 by a DSl interface chip (not shown) that has built-in clock phase/frequency locking and smoothing. A reference clock (REFCLK) connects, via a line 1142, the Office Alarm Interface module 214 to the Shelf Monitor module 232 wherein a REFCLK interface circuit (not shown) performs a repeater function on the REFCLK. From the Shelf Monitor module 232, the REFCLK is placed on a REFCLK bus 1144 that is sent to all the DS3 Interface modules (e.g., 171,171') on the High-Speed Interface Shelf 202. Status of the primary source, i.e., BITS clock, (and secondary source) is obtained by a craftsperson at the OSS using the TL1 command "RTRV-COND" with condition types of: SFI Synchronization Failure Indication Detected SYNC Loss of Timing of Synchronization Link SYNCOOS Loss of Timing on Both Primary and Secondary Synchronization Links SYNCPRI Loss of Timing of Primary Synchronization Link SYNCSEC Loss of Timing on Secondary Synchronization Link The secondary source of the reference can be any DSl (embedded or direct interface) that is accessed by the access system 170. Each DAI circuit 250 (Figure 6) on each DS3 Interface module 171 is capable of selecting one of 28 DSl clocks (as the REFCLK) via the multiplexer circuit 486 of Figure 10a as previously described. This selected clock (REFCLK) also connects onto the REFCLK bus 1144. As previously described, the Administration Processor Module 190 selects either the BITS Clock or one of the clocks generated by the DAI 250 (Figure 10) to be the synchronization reference clock. For example, the third DSl of the DS3 controlled by the DS3 module 1171 could be selected. It should be noted that when an embedded DSl is used as the reference, the signal that is put out on the internal bus is the gapped DSl clock. A gapped clock has the right number of pulses over time, but instantaneously may not have equal pulse widths. No smoothing has occurred on this signal. Smoothing by the Administration Processor Module 190 restores the clock pulse widths from a gapped status back to normal. The presently preferred access system 170 also includes an auto search feature for finding a reference, which requires a special algorithm. The creation of a DSl or channel reference pool uses the underlying principle that a majority vote of several monitored channels in the network will indicate the best available reference timing source. All channels at a given rate (in this case, DSl) are treated as candidates to be used as the reference clock. Software for the auto search feature is, in a presently preferred embodiment, written in the "C" language. The software described herein was translated from the source code into object code using an optimizing MCC68K "C" cross- compiler, version 3.3, available from Microtec Research. Nonetheless, one skilled in the technology will recognize that the steps in the accompanying flowchart can be implemented by using a number of different languages, language translators, computers and circuitries. A flowchart of a sequence 1168 for auto selection of a channel timing reference is shown in Figure 33. A sequential DSl channel scan begins at state 1170. At a decision state 1172, each potential channel that is being measured is first checked for service state to ensure that the connected facility is "in service" or valid. Once the channel is determined to be a valid candidate, a measurement is initiated at state 1174 for a predetermined time interval, e.g., five seconds, at state 1176 and decision state 1178. After the measurement results are obtained, as determined by state 1178, the sequence 1168 moves to a decision state 1180. Measurement results are expressed as counts of bits of difference over the measurement period, where the nominal bit rate for a DSl channel is 1.544 MBits/second. At state 1180, a check is made for validity of the result, i.e., that the channel remained stable and in service during the measurement period. If a loss of signal is detected during the measurement period, the measurement results are deemed invalid and the sequence 1168 moves to state 1182, selects the next DSl channel, and continues at state 1172. If the results are valid as determined at state 1180, a one second average is used as a data point in determining the viability of the channel as a reference. This averaging method serves to cancel inherent +/-1 count uncertainty in using the frequency counter 1069 (Figure 21) to measure frequency differences between two asynchronous channels. At state 1184, this one second average is then saved along with the DSl channel number in a database for later post processing. At a decision state 1186, a determination is made whether all DSl channels in the system 170 have been measured. If not, the sequence 1168 loops back to state 1182 to select the next channel. This measurement loop is repeated for all subsequent DSl channels in the system 170. Once all channels are measured, a system-wide average is calculated at state 1188. Then, at state 1190, each channel is categorized with other channels having the same difference count. A resultant distribution or weighting is then obtained for all unique difference count results with the number of DSl channels per difference count comprising the weighting value. The aforementioned distribution is scanned on a per difference count basis. At a decision state 1192, a determination is made as to whether the difference count is within +/-7 counts of the overall average difference count. Out of all difference counts that meet this criteria, the difference count with the maximum number of conforming channels is marked as the "normalization standard" at states 1194 and 1196. A check is made at a decision state 1198 to determine if all the results have been scanned. If not, the sequence 1168 moves to state 1200, selects the next DSl channel, and continues at state 1192. When all the results have been scanned, as determined by state 1198, a reference pool is obtained at state 1202 by incorporating all channels into the pool that are conforming at the normalization standard. At state 1204, all DSl channels at an acceptable deviation (if necessary, as described hereinbelow) from the normalization standard become members of the reference pool. At a decision state 1206, a determination is made whether there are at least 10 channels in the reference pool. If less than 10 channels are obtained conforming at the normalization standard, the conformance criteria is incrementally expanded +/-1 difference count from the normalization standard by a loop of states 1206, 1208, and 1204, until a minimum of 10 channels are obtained in the pool. This reference pool selection mechanism also incorporates a selection filter at states 1210 and 1212 to prevent all channels in the pool from being embedded channels of the same higher order channel, e.g., DS3 channel. This selection filter ensures that the reference pool is not depleted if the higher order channel encounters Loss of Signal (LOS) . A valid reference pool is thus obtained at state 1214. This auto-reference pool selection is repeated periodically, e.g., nominally every hour, to ensure the long term validity of the reference pool. Once the initial reference pool is selected, conforming channels will remain in the reference pool until one of the two following situations occur: 1. When a loss of signal is detected in the conforming channel or higher order channel, the conforming channel is deleted from the pool. If the loss of signal is detected in the reference channel that was selected from the pool, that channel is removed as the reference and an arbitrary channel is selected from the reference pool. 2. A periodic re-evaluation via the aforementioned sequence 1168 determines that a conforming channel no longer falls within the new pool. This serves to filter out one-time valid reference channels which, over time, deteriorate in stability or drift. The present embodiment of the auto-search reference algorithm provides continuous synchronization monitoring of DSl channels embedded in the DS3 channels received by the access system 170. The reference source is, primarily, taken from the BITS input that is received by the Office Alarms Interface module 214 (Figure 32) . As previously discussed, due to the resource sharing of a single frequency counter 1069 (Figure 21) , a quantizing algorithm is used on the DS3 Interface module 171 although another embodiment may include multiple counters. This algorithm is performed in the CPU complex 262 (Figure 6) on each DS3 Interface module 171. In the auto-search reference algorithm, a two-level approach to measurement time is utilized. The first level requires monitoring each of the 28 DSls for a short period of time (e.g., 1 second). The second level monitors a specific DSl for a longer period of time. A cyclic method between the two levels monitors a specific DSl for a longer period of time. The cyclic method between the two levels results in data points that are correlated to a particular frequency difference, and further, to a slip rate. Table 1 shows the monitor time breakdown of DSl channels on a per minute basis . The actual sequence of channel numbers is not important, e.g., the channel numbers could be in a descending order over time. Table 1 Minute Secc Dnds I L-28 Seconds 29-43 Seconds 44-58 1 See Note 1 Channel 1 only Channel 2 only 2 See Note 1 Channel 3 only Channel 4 only 3 See Note 1 Channel 5 only Channel 6 only 4 See Note 1 Channel 7 only Channel 8 only 5 See Note 1 Channel 9 only Channel 10 only 6 See Note 1 Channel 11 only Channel 12 only 7 See Note 1 Channel 13 only Channel 14 only 8 See Note 1 Channel 15 only Channel 16 only 9 See Note 1 Channel 17 only Channel 18 only 10 See Note 1 Channel 19 only Channel 20 only 11 See Note 1 Channel 21 only Channel 22 only 12 See Note 1 Channel 23 only Channel 24 only 13 See Note 1 Channel 25 only Channel 26 only 14 See Note 1 Channel 27 only Channel 28 only 15 See Note 1 Channel 1 only Channel 2 only Note 1: DSl Channels 1 through 28 are each monitored for 1 second during this time interval. Using the rates defined in Table 1 the following monitoring times can be guaranteed for each DSl: Table 2 Time Number of Seconds Monitored per DSl 1 minute 1 second 15 minutes 30 seconds 1 hour 120 seconds 1 day 2880 seconds To determine if these time periods are enough to define the synchronization level of the DSl signal under test involves two primary components. The first is the expected accuracy of the DSl clock frequency. This parameter involves the use of Stratum clocks at the source of the DSl being monitored. As described in Bell Communications Research TA- NPL-000426 (Issue 1, November, 1986) , the accuracy of each of the stratum clocks is as follows: Table 3 Stratum Minimum Accuracy Seconds/Bit Slip 1 ± 1 X 10 -11 64767 (± 0.000015 Hz @ 1.544 Mhz) ± 1.5 x 10 "8 40 (± 0.025 Hz @ 1.544 Mhz) 3 ± 4.6 x 10 "6 .143 (± 7 Hz @ 1.544 Mhz) 4 ± 3.2 x 10 '5 .02 (± 50 Hz @ 1.544 Mhz) The second parameter that affects the synchronization level definition has to do with jitter and count value accuracy. This parameter has three subparameters: 1. The counting value accuracy is dependent upon the instantaneous reading of the counter and the phases of the two clocks. Because of the asynchronous nature of the time when the counter is read, there will always be an uncertainty of ± 1 bits in the value that is taken from the counter. Over time this discrepancy averages out to zero bits, but the use of the instantaneous value must include the uncertainty. 2. Due to the fact that uns oothed DSl clocks are used in the synchronization measurement, waiting time jitter of ± 1 bit is introduced. As with the count value discrepancy, this jitter averages out to zero over time, but the uncertainty must be included when the instantaneous count value is used. 3. The DSl signal itself is allowed to have up to ± 5 bits of peak-to-peak jitter which affects the instantaneous count value. As with the other discrepancies, this jitter averages out to zero bits over time. The accumulation of these three sources of uncertainty is: Count Value Inaccuracy ± 1 Waiting Time Jitter ± 1 DSl Peak-To-Peak Jitter + 5 ± 7 Bits of Uncertainty Therefore, any counts received in the range from +7 to -7 must be integrated over multiple time samples before any definition of frequency or slips can be made. Given the criteria just defined, the following results are possible using the quantizing algorithm: Table 4 Number of Seconds Stratum Level Time Monitored per DSl Prediction 1 minute 1 second Stratum 4 or better 1 15 minutes 30 seconds Stratum 4 or better 2 Stratum 3 or better 1 1 hour 120 seconds Stratum 3 or better 2 Stratum 2 or better 1 1 day 2880 seconds Stratum 2 or better 2 Note 1: This level can be predicted with limited accuracy. Not enough time has passed to give an accurate definition of the synchronization level. Note 2: Enough seconds have been monitored to give an accurate definition of the synchronization level. Use of Data Collected It is evident from Table 4 that the only data point available for the 1-minute reporting time is the 1-second accumulation. To calculate the slip count for the present minute, the following algorithm is used: 1 Minute Reporting ABS(# of Counts/second) * 60 seconds = # of Slips ±2 Slips 193 bits per DSl Subframe Note 1. If the fractional part of a slip is less than .5, then round down. If the fractional part of a slip is ≥ .5, then round up. Note 2. If the # of Slips -< 3, then the # of Slips = 0 Note 3. Use the absolute value of the number of counts in order that the number of slips reported is always positive. Note 4. The accuracy of the # of slips depends upon the accuracy of the # of counts which is ± 7. In determining which data points to use for the hour reporting, two sources are available. Both the 1-second data points and the 15-second data points have an accuracy of ± 7 bits. Over an hour time period, sixty 1-second samples are taken and four 15-second (i.e., 1 minute) samples are taken. Given the same amount of monitoring time for each, the 15- second samples tend to be more accurate because the uncertainty factor is accumulated over four samples versus the sixty 1-second samples. Therefore, it follows that only the 15-second samples should be used in the 1-hour calculation as well as the 1-day calculation. Due to the 15- second sampling criteria, new slip count results could only be reported every 15 minutes. Minutes 1 through 14 of the hour could report no data available or could report the average of the 1 minute samples. Reporting of Synchronization The "RTRV-PM-T1" Monitored Parameter Type used is "SLIPC" . After factoring out the uncertainty values, the count is converted to a number of slips per the time period (i.e., minute, hour, day) of the DSl subframe. This slip value is then reported to the craftsperson at the OSS in response to the TL1 command "RTRV-PM-T1" . To get autonomous responses for a specific number of slips, the TL1 command "SET-TH-T1" is used. The user can specify a threshold number of slips, in the TL1 "SLIPC" Parameter Type of "SET-TH-T1", for a defined time period and get an autonomous message output when the threshold is exceeded. VI. ALARM CORRELATION Access System Hierarchical Event and PM Filtering The access system 170 is capable of full-time performance monitoring on up to 48 bi-directional or through DS3 circuits or channels and all of their constituent DS2 and DSl sub-circuits. Each circuit is monitored by the access system 170 for several network disturbance conditions. These conditions are issued as autonomous events to the controlling operations support system (OSS) , via a 9600 baud link using Bellcore TL1 protocol in the presently preferred embodiment. In the event of a DS3 level defect or failure, the probability of a subordinate or embedded circuit failure is very high, and a significant amount of "redundant" information has the potential of being generated in the form of a flood of autonomous events towards the OSS. To provide the OSS with the most pertinent information in identifying the fault, the access system 170 has a hierarchical filtering mechanism that reduces the amount of redundant information issued in the event of a higher (DS3 or DS2) level fault. Hard failures cause loss of service while soft failures cause a degradation of service. Soft failures are categorized by the accumulation of a user specified number of data errors over a given interval of time. This detection of soft failures is done as a post process by a "STATS" subsystem which will be described hereinbelow. Referring to the high level block diagram in Figure 34, the fundamental component of the hierarchical filter of the access system 170 (Figure 5) is the hierarchical partitioning of hardware register sampling tasks 1260, 1262, 1264 on a per DS3/DS2/DS1 level basis. Registers of the DAI performance monitors 430, 434, and 438 (Figures 10b, 10c, lOd and 34) for the DS3, DS2, and DSl levels, respectively, are accessed by the tasks 1260, 1262, 1264, running on the DS3 interface 171, via the microprocessor interface 400 (Figures 8 and 10a) , and hard failure information is retrieved. (The microprocessor access corresponds to state 394 (Figure 7) of the performance monitoring process 393.) Continuing to refer to Figure 34, the DS3 level is sampled by high priority task 1260 at a rate of approximately 50 ms. The DS2 level is sampled by task 1262 of lower priority than the DS3 level, but of higher priority than the DSl level. In addition, the DS2 sampling rate is preferably set to no greater than one-half that of the DS3 rate. The DSl level is sampled by the lowest priority task 1264 at a rate of no more than that of the DS2 rate. The tasks 1260, 1262, 1264 identify hard failures. The highest priority task labelled (PM ISR) 1266 is performed by a performance monitor (PM) Interrupt Subroutine (ISR) at a rate of approximately 3 ms. The PM ISR task 1266 retrieves performance monitor data from the DS3, DS2, and DSl performance monitors 430, 434, 438 and stores the PM data in a PM elastic buffer 1268, e.g., a memory element. The PM data in the buffer 1268 is used to identify soft failures. The PM ISR task 1266 corresponds to state 395 (Figure 7) of the performance monitoring process 393. As defects or faults are detected at the DS3 or DS2 level, this information is queued to an alarm correlation and filter process 1270 by the event samplers 1260, 1262 for eventual reporting to the external OSS. In addition, a DS3 event flag 1272 or a DS2 event flag 1274, in a set of DS2 event flags 1275, is raised. The constituent level tasks, e.g., 1262 for the DS3 event flag 1272, upon reading a raised event flag, suspend event processing and squelch any existing alarm conditions. These event flags 1272, 1275 also employ a nominal amount of "off transition" hysteresis or delay, thus guaranteeing that the constituent levels have the opportunity to acknowledge the occurrence of the higher level event. Note that the event flags 1272, 1275 are used to track the event but not to report it. Both the PM elastic buffer 1268 and the event flags 1272, 1275 are maintained in the RAM memory of the CPU complex 262 (Figure 6) . For hierarchical event filtering, all performance monitor (PM) data collection is maintained such that each subordinate circuit's PM data will reflect the superordinate event condition. As a final procedure to reduce redundant autonomous alarm events and conserve access system 170 to OSS link 196 (Figure 5) bandwidth, an alarm integration state machine 1276 is implemented pursuant to the recommendations of ANSI T1M1.3. It should be noted that the alarm correlation and filter process 1270, mentioned above, and the state machine 1276 correspond functionally to the states 396 and 397 of the performance monitoring process 393 shown in Figure 7. The alarm integration state machine 1276 allows the user to specify an integrated duration, e.g., 0 - 15 seconds, for which an event is present on a per circuit basis before an external alarm report is issued. That is, the state machine 1276 is a post-process for further filtering to the process 1270 and determines how "hard" a failure is before reporting. The state machine 1276 thus only reports hard failures and ignores glitches responsible for soft failures. Referring again to Figure 34, the state machine 1276 receives feedback indicated as 1277, in the form of a failure code, from an alarm and exception reporting (AEREP) subsystem (not shown) . The failure code is received by means of detection of internal message buffer pool exhaustion using an alarm and exception reporting utility called by the state machine 1276. The buffer pool utilizes an elastic buffer (not shown) . This feedback helps throttle alarm reports and prevent loss of events. The alarm and exception reporting subsystem is part of the administration processor module 190 (Figure 5) . A per second PM quantization, correlation and filter process 1278 receives event data from the process 1270 and raw PM data from the PM elastic buffer 1268. The process 1278 then categorizes the problems into hard and soft failures, and further categorizes the hard failures hierarchically by circuit and alarm type. The process 1278 provides industry standard (Bellcore or ANSI) error counts on a per second basis. The results, indicated as 1279, are sent to the STATS subsystem, which includes a distributed database. The STATS subsystem resides primarily on the administration processor module 190 (Figure 5) but also on the DS3 Interface module 171. The OSS may then interrogate the STATS subsystem for PM statistics reports via the OSS link 196. The tasks associated with the event and PM hierarchical filtering shown in Figure 34 are preferably controlled by a real-time operating system, such as the PSOS program available from the Software Components Group of San Jose. The process 1270 and the process 1278 are executed by the CPU complex 262 (Figure 6) on the DS3 Interface module 171. As an example of a typical scenario, once the alarm integration state machine 1276 reports a hard failure to the OSS, a craftsperson will reroute the traffic on the effected circuit, along with any embedded circuits. The craftsperson then temporarily removes that circuit, along with any embedded circuits, from processing by the alarm correlation and filter process 1270. The craftsperson may then use intrusive tests to isolate the problem. The intrusive testing of the circuit at a particular level, e.g., DS3 , may continue until the cause is identified. However, the testing of the circuit is suspended or interrupted if a superordinate circuit is seen to have an intermittent or sustained hard failure. When the cause of a hard failure is identified and corrected, the effected circuit, along with any embedded circuits, is restored for handling by the process 1270. Hierarchical Event Filtering and Alarm Correlation Several sequences or functions are employed in the access system software to filter out "redundant" event issuances or information sent to the OSS in the event of a DS3 or DS2 level defect occurrence. Referring to Figures 35 and 36, the filtering functionality is partitioned into a number of Per Alarm Scan Sequences 1290 which are components of a. given Per Circuit Scan Sequence 1292, i.e., the circuit sequence 1292 is composed of several alarm sequences 1290 (one per alarm type) . Both sequences 1290, 1292 are part of the alarm correlation and filter process 1270 of Figure 34. Software for the sequences 1290, 1292 is, in a presently preferred embodiment, written in the "C" language. The software described herein was translated from the source code into object code using an optimizing MCC68K "C" cross- compiler, version 3.3, available from Microtec Research. Nonetheless, one skilled in the technology will recognize that the steps in the accompanying flowchart can be implemented by using a number of different languages, language translators, computers and circuitries. The Per Alarm Scan Sequence 1290 (Figure 35) begins at a start state 1300 and proceeds to a state 1302 wherein sample data for the circuit being processed, e.g., DS3, is read from a bit-mapped buffer. In the buffer, a given alarm type defect status, such as Loss of Signal, is indicated by an individual bit. The bit-mapped buffer contains an image of the data in the DAI performance monitor registers 430, 434, 438 (Figure 34) . Moving to a decision state 1304, the bit corresponding to a given instantiation of the alarm sequence 1290 is tested to determine if a defect is present for an alarm type. If a defect is found to be present at state 1304, the sample data buffer is cleared at state 1306, thus clearing the indication of defects for all subsequently scanned alarms for that circuit. The event flags 1272, 1275 (Figure 34) heretoforward are also known as hierarchical defect flags. One of the hierarchical defect flags, such as set by state 1349 of Figure 36, is then set at state 1308 indicating, for any embedded circuits, that a superordinate defect has been detected. Proceeding to state 1310, a corresponding hierarchical defect timer (not shown) is initialized to ensure that the defect flag remains set, allowing subordinate or embedded circuits to recognize the superordinate defect. A weighted defect integrator, which is a part of the state machine 1276 (Figure 34) is then incremented at state 1312 and, at a decision state 1314, a test is done to determine whether multiple defects have integrated to a hard failure condition. The defect integrator categorizes various disturbances and determines whether the defect is of a significance such that it needs to be reported to the OSS. If a failure condition has been reached at state 1314, a test is made at a decision state 1316 to determine if there was already a failure condition active. If a failure condition was not yet active at state 1316, an autonomous message is initiated at state 1318 to the external OSS or control port indicating that a failure condition is active. If a defect is not present at state 1304, the weighted defect integrator is decremented at state 1322. Moving to a decision state 1324, if the integrator has been decremented to zero, a test is made at a decision state 1326 to determine if a failure condition is active. If a failure condition is active at state 1326, an autonomous message is initiated at state 1328 to the external OSS indicating that the failure condition for the present alarm has cleared. Upon the completion of state 1318 or 1328, or if any of the decision states 1314, 1316, 1324, or 1326 are false, the alarm sequence 1290 finishes at state 1330 and the Per Circuit Scan Sequence 1292 scans the next alarm type during the next scan period using another instantiation of the alarm sequence 1290. Referring now to Figure 36, the Per Circuit Scan Sequence 1292 is scheduled for execution by the real-time operating system at approximately 50 ms intervals for DS3 circuits, 125 ms intervals for DS2 circuits, and 250 ms intervals for DSl circuits. The sequence 1292 begins at a start state 1340 and proceeds to a state 1342 wherein the appropriate DAI alarm status register, which is a part of the performance monitor 430, 434, or 438, for that circuit is sampled and buffered in an alarm sample buffer located in the memory of the CPU complex 262 (Figure 6) . A check is made at a decision state 1344 to see if a superordinate defect is present via a test of the associated hierarchical level defect flag. If a superordinate defect is found to be present at state 1344, the alarm sample buffer is cleared at state 1346, thus effectively initiating a failure "clear" process in the subsequent alarm sequences 1290. The alarm sequences 1290 then proceed in a defined order of precedence specified as LOS, AIS, OOF, and other alarms, at states 1348, 1350, 1352, and 1354. States 1348, 1350, and 1352 have associated states 1349, 1351, and 1353, respectively, to indicate that the hierarchical level defect flag is set. This sequence assigns a hierarchy of alarms within a specific circuit. For example, an alarm indication signal (AIS) defect will squelch an active out of frame (OOF) defect/failure and so forth. Once all alarms are scanned, at state 1356, the hierarchical level defect timer for the scanned level is decremented. Moving to a decision state 1358, a test is then made to determine if this associated defect timer has expired (equals zero) . If the defect timer has expired at state 1358, the hierarchical level defect flag associated with this scanned circuit is cleared at state 1360, and the sequence 1292 finishes at state 1362. At the appropriate time, the operating system will schedule the circuit sequence 1292 for execution on either a DS3, DS2, or DSl circuit. VII. SUMMARY The embodiments disclosed herein for the DS3 signal access system 170 can be extended to other telephone and communications networks. Although the invention has been described with reference to specific embodiments, the description is intended to be illustrative of the invention and is not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims.

Claims: WHAT IS CLAIMED IS: -98- 1. A system for measuring relative synchronization between a plurality of embedded channels in one or more signals, the system comprising: means for simultaneously accessing the embedded channels wherein each embedded channel comprises a plurality of bits; means for counting the bits in the accessed embedded channels; and means for comparing a bit count in one of the embedded channels with a bit count in another of the embedded channels. 2. The system defined in Claim 1, wherein the counting means simultaneously counts bits in the accessed embedded channels. 3. The system defined in Claim 1, wherein the comparing means includes means for generating an alarm signal when the comparison result is greater than a threshold value. 4. The system defined in Claim 1, wherein each bit comprises a clock pulse. 5. The system defined in Claim 1, wherein the bits include a framing bit. 6. A method of measuring synchronization of a set of channels in a signal, the method comprising the steps of: measuring the frequency of each channel; and comparing the frequency of each channel to obtain one or more relative frequency measurements. 7. The method of Claim 6, further comprising a step of generating an alarm signal when the comparing result is greater than a threshold value. 8. A method of adaptively selecting an internal reference from a set of channels in a signal, the method comprising the steps of: selecting a pool of channels; choosing a reference channel from the pool so as to normalize frequency measurement results on all other channels; and measuring the frequency of each channel in the signal relative to the reference channel. 9. The method of Claim 8, comprising the additional step of dynamically selecting a new reference from the reference pool if the reference channel is determined to no longer be a suitable reference. 10. A system for correlating performance monitoring and testing of a channel having a plurality of embedded channels, comprising: means for detecting a disturbance in the channel; means for detecting a disturbance in one of the embedded channels; means for correlating the disturbance in the channel with the disturbance in the embedded channel; and means for generating an alarm for the disturbance including means for blocking the alarm of the embedded channel disturbance when the embedded channel disturbance correlates to a disturbance of the channel. 11. The system defined in Claim 10, wherein testing of the embedded channel is interrupted when testing of the channel fails. 12. The system defined in Claim 10, additionally comprising means for filtering each disturbance received from the detection means, wherein the correlation means is provided filtered disturbances. 13. The system defined in Claim 10, wherein the detection means includes an event sampler. 14. The system defined in Claim 10, wherein the detection means includes an event flag. 15. The system defined in Claim 10, additionally comprising means for storing raw performance monitoring data. 16. The system defined in Claim 15, additionally comprising means for reporting performance monitoring data received from the storage means.

Inventors: ENGDAHL THOMAS L, HARTMANN PAUL R, TYBURSKI EDWARD S, ENGDAHL, THOMAS, L., HARTMANN, PAUL, R., TYBURSKI, EDWARD, S.
Applicants: APPLIED DIGITAL ACCESS INC, APPLIED DIGITAL ACCESS, INC.
Application year: 1993
Main classification: H04J3
IPC codes: H04J3, H04Q11