Chip varistor and its production method

Abstract: The varistor element 2 of the present invention has a pair of electrodes 3 and 4 accommodated on the outer surfaces of a varistor element 2. The pair of electrodes 3 and 4 are comprised of a pair of ohmic contact electrodes 5 and 6, oppositely arranged on top/bottom surfaces of the varistor element, and a pair of non-ohmic contact electrodes 7 and 8, covering both ends of the varistor element 2 so as to form terminal electrodes. The non-ohmic contact electrodes 7 and 8 are, respectively, connected to the pair of ohmic contact electrodes 5 and 6. With this structure, an electric current is not concentrated at the ends of the ohmic contact electrodes. As a result, the endurance against surge currents increased and the reliability and durability of the product is improved.

Description: Background of the Invention Field of the Invention This invention relates to a chip varistor and is particularly directed to a chip varistor having an improved structure of electrodes so as to obtain high surge current endurance. Description of the Prior Art An increase in the amount of varistors, which are non-linear resistance elements, currently in use corresponds to the increased use of electric machines and devices in recent years. In addition, chip varistors are increasingly needed due to miniaturization of devices. An important feature of chip varistors is surge current endurance. In use, chip varistors protect against both large and small current surges. Therefore, chip varistors are critical components with respect to product reliability and durability. Figure 1 shows a cross sectional view of a conventional chip varistor 20, such as it is, for instance, known from US-A-4 706 060. The chip varistor 20 is comprised of: a rectangular-parallelepiped shaped varistor element 21 which is mainly made of zinc oxide (ZnO) ; and, electrodes 22a, 22b made of a material in which boro-silicated glass frit is added to, for example, silver. The electrodes 22a, 22b are in contact with the varistor element 21. One electrode extends from one opposing surface to one end of the varistor element 21 and the other electrode extends from the other opposing surface to the other end of the varistor element 21. Application of a certain voltage to the pair of electrodes 22a, 22b and a large amount of current to the varistor element 21 causes an intensified concentration of electric current at ends of the electrodes 22a, 22b. This intensified concentration of electric current is indicated by the arrows shown in Figure 2. In addition, the sections of the varistor element 21 proximate to the ends of the electrodes 22a, 22b are also damaged, as a result of the above mentioned condition. Thus, the surge current endurance of the varistor 21 is decreased. Furthermore, gap intervals " b " between the electrodes must be larger than the thickness " a " of the varistor element, as shown in Figure 3. Therefore, this creates a dimensional limitation in producing electric poles. Hence, it is an object of the present invention to provide a new chip varistor which has a greater surge current endurance than conventional chip varistors, thereby increasing the reliability and durability of devices utilizing the new chip varistor, and an improved method of manufacturing chip varistors. Summary of the Invention The chip varistor of the present invention is comprised of a varistor element having top and bottom surfaces, opposite sides and opposite ends, a pair of non-ohmic contact electrodes accommodated on said varistor element, one said non-ohmic contact electrodes covering one of said opposite ends of said varistor element and extending over a majority portion of said top surface, and the other nonohmic contact electrode covering other end of said varistor element and extending over a majority portion of said bottom surface; a pair of ohmic contact electrodes directly arranged each of which is arranged at a center of corresponding one said top and bottom surfaces of said varistor element, each of said ohmic contact electrodes directly electrically contacting one of said surfaces and each of said pair of non-ohmic contact electrode being electrically connected to each of said pair of ohmic-contact electrodes while forming a non-ohmic contact with respect to said varistor element. Due to the particular configuration of the chip varistor, as described above, the application of a large electric current to the varistor element of the chip varistor will not damage the electrodes. The current is dispersed or flows equally through the electrodes and into the varistor element positioned between the pair of ohmic contact electrodes. This results in large endurance against the surge current. In addition, the varistor element is also protected against damage caused by the surge current, thereby improving product reliability and durability. Also a method of producing a chip varistor is described comprised of a calcined varistor element, having a non-linear voltage characteristic, and a pair of electrodes, accommodated at peripheral surfaces of the varistor element. The production method includes a step for rounding the corners of the varistor element. This is accomplished by dry polishing the corners, utilizing organic abrasives, before the calcination process. According to the above-described chip varistor production method, since the corners of the varistor element are rounded by the dry polishing method prior to the calcination process, there is no need to round the varistor element after calcination. Further, a decrease in varistor resistance on the surface layer of the varistor element, typically caused by the polishing process following the calcination process, is, subsequently, avoided. Therefore, the true electric characteristics are maintained. In addition, the dry polishing method advantageously creates irregularities on the surface of the varistor element. This prevents the varistor elements from sticking together during the calcination process, thereby resulting in improved production yields. Brief Description of the Invention Figure 1 is a cross sectional view showing a conventional chip varistor. Figure 2 is an explanatory view showing a situation where electric currents are concentrated on the conventional chip varistor. Figure 3 is a cross sectional view showing another embodiment of the conventional chip varistor. Figure 4 is a perspective view showing a preferred embodiment of the chip varistor of the present invention. Figure 5 is a cross sectional view showing the preferred embodiment of the chip varistor of the present invention. Figure 6 is a perspective view showing a production method of the chip varistor. Figure 7 is another perspective view showing the production method of the chip varistor. Figure 8 is a further perspective view showing the production method of the chip varistor. Figure 9 is a further perspective view showing the production method of the chip varistor. Figure 10 is a graph showing a relationship between an applied surge current and a variation rate of varistor voltage in the conventional chip varistor. Figure 11 is a cross sectional view showing another structure of the chip varistor of the present invention. Description of the Preferred Embodiments The preferred embodiment of the present invention is described in detail below. As shown in Figures 4 and 5, a chip varistor 1 is comprised of a varistor element 2, which is mainly made of zinc oxide (ZnO), and a pair of electrodes 3, 4, which are accommodated on the periphery of the varistor element 2. The electrode or electric pole 3 is comprised of an ohmic contact electrode 5 and a non-ohmic contact electrode 7. The ohmic contact electrode 5 is positioned at the center of the varistor element 2. The electrode 5 is made of boro-silicated glass frit, or indium (In), or gallium (Ga), or zinc (Zn), or aluminum (Al), and silver or the like (Ag, Zn, Al, Pd, Ag+Pd, or Ag+Pt). The non-ohmic contact electrode 7, which is connected to the ohmic contact electrode 5, extends to the end of the varistor element 2 so as to cover one end or terminal of the varistor element 2. Thus, the non-ohmic contact electrode forms the terminal pole. The non-ohmic contact electrode 7 is made of borosilicated glass frit and silver or the like (Ag, Pd, Ag+Pd, or Ag+Pt). The boro-silicated glass utilized in this example can be boro-silicated lead glass or boro-silicated lead zinc glass. The other electrode 4 is comprised of an ohmic contact electrode 6 and a non-ohmic contact electrode 8. The ohmic contact electrode 6 is positioned at the center of the varistor element 2, so as to correspond to the ohmic contact electrode 5. The ohmic contact electrode 6 is made of the same materials as the ohmic contact electrode 5. The non-ohmic contact electrode 8, which is connected to the ohmic contact electrode 6, extends to the end of the varistor element 2 so as to cover the other end or terminal of the varistor element 2. The non-ohmic contact electrode 8 is made of the same material as that of the non-ohmic contact electrode 7. The production method of the chip varistor is comprised of the following. First, a plurality of rectangular-parallelepiped-shaped varistor elements 2, mainly made of zinc oxide (ZnO), are placed in a tube-shaped rotatable plastic pot 13, as shown in Figures 6 and 7. Next, organic abrasive materials 14 sized between 0.5 and 10 mm, for example, are put into the rotatable pot 13. The organic abrasive materials 14 are selected from seed rice, walnut shells, corn, or synthetic materials. An advantage of utilizing organic abrasive materials in this process is the elimination of surface cracks on the varistor element. Next, the tube-like rotatable pot 13 is kept rotating from 5 minutes to 2 days so that the varistor elements 2 are dry-polished therein. The polishing time is set depending on dimensions or volumes of the varistor elements 2. By performing dry polishing, the eight corners and surfaces of the varistor element are rounded, as shown in Figure 8, and, also, small irregularities are created on the surface of the varistor elements 2. Finally, the calcination process is performed on the rounded varistor elements 2, utilizing temperatures between 1100-1400 °C, for example. Since irregularities are created on the surfaces of the varistor elements 2 during the dry polishing, the varistor elements do not stick together. Advantageously, fewer scratches are created on the surfaces of the varistor elements, since it is not necessary to separate the varistor elements. In addition, degradation of electrical characteristics caused by the scratches are, subsequently, eliminated. Hence, production proceeds without experiencing many interruptions. Furthermore, since the varistor elements 2 are first rounded by the dry polishing method utilizing the organic abrasives before the calcination process is started, as stated above, the rounding process is not necessary after the calcination process. Since the varistor element is hardened after the calcination process, performing the rounding process after the calcination process typically produces cracks or scratches on the surface of the varistor element. These cracks or scratches on the varistor surface may cause lattice defects which lower the surface resistance of the varistor element. However, due to the production method of the present invention, fewer scratches are created and, thus, decreases in surface resistance are eliminated. Therefore, the chip varistor 1 achieves the required electric characteristics. As shown in Figures 5 and 9, the ohmic contact electrodes 5 and 6 are positioned on the top and bottom surfaces of the varistor element 2. The electrodes or poles 5 and 6 are made of boro-silicated glass frit, or indium (In), or gallium (Ga), or zinc (Zn), or aluminum (Al), and silver and the like (Ag, Zn, Al, Pd, Ag+Pd, or Ag+Pt). The non-ohmic contact electrodes 7 and 8 are respectively connected to the pair of ohmic contact electrodes 5 and 6. The electrodes 7 and 8 are made of boro-silicated glass frit and silver and the like (Ag, Pd, Ag+Pd, or Ag+Pt). This structure provides the chip varistor, as shown in Figure 4, where both ends of the varistor element 2 are covered by the non-ohmic contact electrodes 7 and 8. By structuring the chip varistor 1 in this manner, intensified concentrations of electric currents at the ends of the electrodes 7 and 8 are eliminated. Thus, when a large amount of current is applied to the varistor element 2 through the non-ohmic contact electrodes 7 and 8 and the ohmic contact electrode 5 and 6 by connecting the electrodes 7 and 8 to a power supply, the current flows smoothly through the ohmic contact electrodes 5 and 6 without causing any localized concentration of the current. Therefore, the chip varistor 1 is able to withstand or endure large surge currents. Further, the varistor element is protected against damage resulting from such surge current and, thus, has improved product reliability and durability. As shown in Figure 5, a relationship between an interval " b " between the non-ohmic electric poles 7, 8 and a thickness " a " of the varistor element 2 is expressed as follows: a < b ' = {(conventional gap interval b ) - (a distance corresponding to non-ohmic voltage [electric barrier])} As a result, the interval " b '" between the non-ohmic contact electrodes 7, 8 is smaller. The value of the conventional gap interval " b " is, for example, 1 mm. The distance corresponding to the non-ohmic voltage in the above relationship usually matches with a diameter of the material used, zinc oxide in this example, and is typically 0.1 mm or less, which is about 10% of the conventional gap length. Thus, the present invention provides less restrictions in determining dimensions when forming the pair of electrodes 3 and 4. Figure 10 shows the relationship between the applied surge current and the variation rate of the varistor voltage for the chip varistor 1 of the present invention and the chip varistor 20 of conventional technology. As is apparent in the drawing, the varistor characteristic of the chip varistor 20 of conventional technology is significantly deteriorated at around 250A. In contrast, the varistor characteristic of the chip varistor 1 of the present invention deteriorates around 500A. Therefore, the present invention has a surge endurance that is twice as much as that of the conventional chip varistor. In addition, as shown in Figure 11, the present invention also provides a structure wherein additional terminal electrodes poles 9 and 10 may be accommodated at the periphery of the non-ohmic contact electrodes 7 and 8 of the chip varistor 1. The terminology, "non-ohmic contact", is defined as a contact on an electrode that does not ohmically contact the varistor element. In addition, the electrode does not electrically contact the varistor element. Such an electric isolation is realized, for example, by the diffusion process wherein a material, like natrium (Na), on the surface of the varistor element forms an insulation layer between the electrode and the varistor element.

Claims: A chip varistor comprising: a varistor element (2) having top and bottom surfaces, opposite sides and opposite ends, a pair of non-ohmic contact electrodes (7, 8) accommodated on said varistor element (2), one of said non-ohmic contact electrodes covering one of said opposite ends of said varistor element (2) and extending over a major portion of said top surface, and the other nonohmic contact electrode covering other end of said varistor element (2) and extending over a major portion of said bottom surface; a pair of ohmic contact electrodes (5, 6) each of which is arranged at a center of corresponding one said top and bottom surfaces of said varistor element (2), each of said ohmic contact electrodes (5, 6) directly electrically contacting one of said surfaces; and each of said pair of non-ohmic contact electrodes (7, 8) being electrically connected to the corresponding ohmic-contact electrode (5, 6) while forming a non-electric contact with said varistor element (2). A chip varistor as defined in claim 2, wherein said ohmic contact electrode (5, 6) is made of materials selected from a group consisting of boro-silicated glass frit, In, Ga, Zn or Al and added with materials selected from a group consisting of Ag, Zn, Al, Pd, Ag+Pd, or Ag+Pt. A chip varistor as defined in claim 1, wherein said non-ohmic contact electrode (7, 8) is made of materials selected from a group consisting of Ag, Pd, Ag+Pd, or Ag+Pt and added with boro-silicated glass frit.

Inventors: ONABUTA SHUICHI, ONABUTA, SHUICHI, ONABUTA, SHUICHI, C/O TDK CORPORATION
Applicants: TDK CORP, TDK CORPORATION
Application year: 1993
Main classification: H01C7
IPC codes: H01C7