Interface circuit between a control bus and an integrated circuit suitable for two different protocol standards

Abstract: While employing the same number of dedicated pins of an IC, a self-configurable interface circuit between a control bus and the IC recognizes whether the IC is being used in a system employing an SPI or a I2CBUS protocol for the transmission to the IC of control signals through the bus. The interface circuit employs an "inner" SPI interface standard block, to a third input of which either a true CE (chip-enable) signal coming from a third wire of the bus or a virtual CE signal that is self-generated by the interface circuit in case of operation in an I2CBUS environment, is fed. The third (ADDR) pin of the IC may be connected to the CE wire of the bus in case of an SPI application or it may be biased at the supply or ground voltage for selecting one or the other of two internal addresses of the IC, when functioning in an I2CBUS environment.

Description: In complex signal processing systems, commonly comprising a plurality of integrated circuits (ICs) containing functional signal processing circuits, the practice of controlling the operation of the system by a microprocessor is becoming more and more common. The microprocessor is capable of receiving and carrying out instructions for enabling/disabling certain functions and/or for adjusting certain operating parameters and of transmitting commands to the various integrated circuits for signal processing through a connection bus. Audio signals processing systems in TV receivers, car radios and similar apparatuses, make large use of such a microprocessor control system for selecting modes of operation for adjusting balance, tone, volume, etc.. The document EP-A-0 225 720-A2 describes an integrated circuit capable of interfacing with a four-line or with a two-line type bus to receive formatted input data and outputting data formatted in a selectable format. The decoding function in selected by means of an externally generated chip-select signal. Transmission of different control signals through the bus from the microprocessors to the various integrated circuits of the system takes place according to a certain transmission protocol. The transmission protocols more widely employed for these purposes are the so-called SPI protocol, which is widely adopted as a standard in US and the I2CBUS protocol, which is the standard most adapted in European countries. The SPI standard requires three wires for transmitting to an interface circuit of an integrated device three distinct signals that are commonly referred to by the acronyms: CL (clock), DA (data) and CE (chip-enable) and does not require the selection of an address. Viceversa the I2CBUS standard requires two wires, for transmitting the signals: CL and DA, respectively, plus the selection of an internal address (i.e. an address present within a controlled IC). Commercial ICs are specifically produced to be used with one or the other of said standard protocols. In either case, the devices are provided with three dedicated pins. In case of ICs destined to be used in an SPI environment, the IC is provided with pins CE, DA and Cl. In case of devices destined to operate in an I2CBUS environment, each IC is provided with three dedicated pins, respectively, DA, CL and ADDR. The third pin ADDR of these devices is provided for address selection. Commonly, users of these ICs require the availability within each IC of at least two addresses that may be selected through said third pin ADDR. It is evident the burden, in terms of production management by ICs manufacturers, deriving from the necessity of producing specific devices destined to work with one or the other of said two widely adopted transmission protocols for the control data of a supervising microprocessor. Also on an user, for example a manufacturer of audio apparatuses, there is a burden due to the management of different inventories of ICs for producing apparatuses according to one or the other protocol standard. It has now been found that these management burdens and drawbacks may be eliminated by providing ICs with a bus interface circuit for the transmission of commands from a supervising microprocessor to the functional circuit for signal processing integrated in the device, which is capable of automatically adapting itself to one or to the other of two transmission protocol standards without requiring any configuring command. The interface circuit of the instant invention is capable of assessing whether the type of transmission protocol being used differs from a "basic" standard protocol and consequently to simulate an operation according to said "basic" standard protocol in case the incoming control signals be transmitted according to a protocol different from said standard protocol. Such an ability of the interface circuit object of the present invention to self-adapt itself in function of the control signals that are received through three pins of the IC is attained by applying to a third one of said three dedicated pins (for example to the ADDR pin) of the integrated circuit, the signal CE (e.g. by connecting said ADDR pin to a third wire of the transmission bus), in order to permit the functioning of the interface circuit according to an SPI protocol. Alternatively, by maintaining floating or by connecting to a ground potential said third pin ADDR, thus selecting one or the other of two internal addresses, the IC may function according to an I2CBUS protocol. A correct operation of the interface circuit in either case and therefore the possibility of employing the same IC in either one or the other environment is ensured by transmitting either the CE signal that is received through the third pin ADDR in case of an SPI environment or a "virtual" CE signal that is purposely generated by the interface circuit itself in case the IC must be used in an I2CBUS environment, through a multiplexer to an inner interface block, which is substantially an SPI interface circuit. The invention will be better understood by referring to the attached drawings showing an important embodiment that is incorporated in the present description by express reference. Figure 1 shows the shape of the three signals : CL, CE and DA, used in an SPI system. Figure 2 shows the shape of the two signals CE and DA used in an I2CBUS system. Figure 3 is a functional block diagram of an interface circuit made according to the present invention. Figure 4 shows how a pseudo or virtual signal CE is self-generated by the circuit of the invention in case only two signals according to the I2CBUS standard are received. Figures 1 and 2 make a clear comparison between the different timing signals that are used according to the two different standard protocols, SPI and I2CBUS, respectively. As may be observed, in case of an I2CBUS protocol, the CE signal (chip-enable) is absent while through a third dedicated pin ADDR of the IC , either one or another of two internal addresses of the chip may be selected. An interface circuit of the invention is depicted in the block diagram of Fig. 3. An SPI type interface circuit block ( SPI interface) constitutes an "inner level" of the self-configurable interface circuit of the invention and receives through three inputs: a clock signal CL, a data signal DA and a third signal for enabling the controlled IC (chip-enable) CE. According to the present invention, this last signal CE may either be a signal coming from the external bus, i.e. from a third wire of the bus that may be connected to the ADDR pin in case of an SPI application, or a virtual CE signal that is internally generated by the circuit in case of an I2CBUS application. This last case is analysed first. In practice, the signals CL and DA, having the form shown in the diagrams of Fig. 4 , will be fed to the dedicated pins CL and DA. By contrast, according to an I2CBUS standard, the third pin ADDR of the IC may be left floating (disconnected) so as to make the output of the comparator COMP assume a high state ( VCC ) (for example this may represent the selection of a first address). Alternatively, the third pin ADDR may be connected to ground so as to cause the output of the comparator COMP to assume a low state (for example this may represent the selection of a second address). In both cases, the output of the comparator COMP that constitutes the input signal for the I2CBUS/SPI decoder block, will not undergo transitions, i.e. there won't be switchings of the signal that is fed to the input of the I2CBUS/SPI decoder, which has the function of detecting the occurrence of a switching of the input signal, by sensing an eventual falling front. Therefore in either cases, the buschoice signal that is generated by the I2CBUS/SPI decoder block will have a certain value, for example high. A high state of the buschoice signal enables the operation of a confirmation signal generating block (acknowledge generator), which detects the start signal and the stop signal that decode, after a start signal, the selected address of the IC (selection that is determined by the state of the output signal of the comparator COMP ) and which therefore generates an acknowledging signal ( 1 ) as indicated in the third diagram of Fig. 4 . The acknowledge signal ( 1 ) so generated is fed to an intput of a circuit capable of generating a virtual CE signal (false CE generator) . The diagram ( 2 ) of Fig. 4 shows how the block, false CE generator, generates a pseudo CE (chip-enable) signal ( 2 ) by deriving it from the acknowledge signal ( 1 ). Therefore, through a multiplexer, MUX , that is controlled by the buschoice signal, the false (virtual) CE signal self-generated by the circuit is fed to the CE input of the "inner", SPI type, interface block. In case of operation in an SPI mode, to the ADDR pin that, in this case will be connected to a third wire of the bus, will be fed a CE signal which, at the first transition from high to low or from low to high, will determine a change of state of the buschoice signal produced by the I2CBUS/SPI decoder block. The transition of the buschoice signal from high to low disables the operation of the acknowledge generator block. Thus the selection of an address is no longer waited for, neither the start and stop signals are interpreted as described above and the entire top portion of the block diagram of Fig. 3 is in practice disactivated. The multiplexer MUX is enabled by the new state of the buschoice signal in order to permit transmission of the "true" CE signal (contemplated by an operation according to an SPI protocol) from the ADDR pin of the IC to the respective input terminal of the "inner", SPI type interface block ( SPI interface). As may be observed, both in case of operation with an I2CBUS protocol and in case of operation with an SPI protocol, three signals ( DA, CL and CE ) are eventually fed to the respective inputs of the inner interface block, SPI interface, thus permitting to the interface circuit to function satisfactorily in either an I2CBUS or in an SPI mode.

Claims: An interface circuit between a bus for the transmission of control signals according to a certain protocol chosen between a first standard (SPI) requiring three wires for the transmission of a clock (CL), a data (DA) and a chip-enable (CE) signal respectively and a second standard (I2CBUS), requiring two wires for the transmission of a clock (CL) and a data (DA) signal respectively and the selection of an address present within a controlled integrated circuit, and the controlled integrated circuit, said interface circuit having at least a first pin connected to a clock transmission wire (CL) of said bus, a second pin connected to a data transmission wire (DA) of said bus and a third pin (ADDR), an inner interface block capable of functioning according to said first standard (SPI) and having a first input connected to said first pin (CL), a second input connected to said second pin (DA) and a third input through which a virtual or real chip-enable signal (CE) is received; decoder means capable of sensing a signal present on said third pin (ADDR) and of modifying accordingly the state of a selection signal (buschoice) generated by said decoder means, for one (SPI) or the other (I2CBUS) of said standards; characterized by comprising means for decoding an address and for generating an acknowledgement signal, enableable and disableable by said selection signal (buschoice) and having an input connected to said first pin (CL), a second input connected to said second pin (DA) and a third input to which a signal whose state depends from the potential present on said third pin (ADDR) is fed, a state of said selection signal (buschoice), corresponding to a selection of said second standard (I2CBUS), enabling said means to generate an acknowledge signal; a virtual chip-enable signal generator capable of receiving said acknowledgement signal generated by said means and to generate a virtual chip-enable signal; a multiplexer (MUX) transferring to said third input of said inner interface block a chip-enable signal fed to said third pin (ADDR) of the circuit in case of operation according to said first standard (SPI) or said generated virtual chip-enable signal in case of operation according to said second standard (I2CBUS) depending on the state of said selection signal (buschoice) fed to a control input of said multiplexer (MUX); said third pin (ADDR) receiving a chip-enable signal through a respective wire of the bus in case of operation according to said first standard (SPI) or, in case of operation according to said second standard (I2CBUS), being kept floating or connected to ground potential for selecting either a first or a second address. An interface circuit as defined in claim 1, wherein said third pin (ADDR) is connected to a noninverting input of a comparator and through an impedance to a supply node, the output of the comparator being connected to an input of said decoder means (I2CBUS/SPI decoder), to an input of said multiplexer (MUX) and to an input of said means for decoding an address and generating an acknowledge signal.

Inventors: CASSIS MARCO, PEDRAZZINI GIORGIO, CASSIS, MARCO, PEDRAZZINI, GIORGIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G06F13
IPC codes: G06F13, H04L29