Digitized image correction

Abstract: A hardware implementation of a digitized image corrector converts a colorimetric representation of an original image into a new representation based upon the colors of the original and target images, as well as user supplied artistic parameters. The digitized image corrector receives digitized Red, Green and Blue input signals that comprise a colorimetric representation of an original film scene, and generates digitized Red, Green, and Blue output signals according to the specifications of SMPTE 240 M. The digitized image corrector is comprised of four identical hardware correction modules, which are coupled to receive correction parameters from an external source. Each module has a bypass switch for entering a bypass mode, which is used for reconfiguration of the module's correction parameters without affecting the output image. Each correction module receives digitized input signals and generates digitized output signals by transforming the digitized input signals according to a set of predetermined correction parameters and a transfer function defined by a matrix of functions.

Description: This invention relates to the field of digital image processing, and more particularly to digitized image correctors and correction circuits. In image processing, image signals typically undergo various adjustments and corrections. For example, in film to video conversion for high definition television (HDTV) these adjustments and corrections may include: a) correction of color distortions due to film dye crosstalk; b) correction of the non-linear luminance transfer function of the film; c) correction for distortion due to video crosstalk; and d) conversion of linear data into SMPTE 240M representation, a predistortion of the data based upon the display gamma. Additionally, in the film to video conversion for HDTV, an operator may want to: a) adjust the color of a film derived image to match that of a video derived image for seamless intercuts; b) remove localised noise; and/or c) process layered film mattes for smooth composition. United States Patent US-A-4,794,460 discloses an apparatus for recording an image on film that is simultaneously monitored on a video display. The image data is passed in series through a gray corrector and respective colour correctors and gradation correctors in order that the image displayed on the video monitor should closely match the image recorded on the film. The Journal of Electronic Imaging, Volume 1, Number 1, 30 January 1992, Pages 35 to 45 "High Performance Digital Colour Video Camera" discloses an image processing circuit in which a lookup table can be used or bypassed depending upon whether or not the image data does or does not require logarithmic correction. European Patent Application EP-A-0,160,489 discloses a video image correction circuit that may be reprogrammed during the vertical flyback period of a video signal. Various aspects of the invention are set out in the claims. A preferred embodiment of the invention described hereinbelow provides a hardware implementation for digitized image signal correctors of an image processing system that allows an operator to dynamically change processing parameters, which enables these correctors to achieve specified output results. The preferred hardware implemented digitized image corrector converts a colorimetric representation of an original image into a new representation based upon data from the original and target images, as well as user supplied artistic parameters. This allows dynamic modification of processing parameters to convert colorimetry of a film image into that of HDTV. The preferred digitized image corrector is coupled to receive digitized Red, Green and Blue input signals that comprise a colorimetric representation of an original film scene. The digitized image corrector generates digitized Red, Green and Blue output signals according to the specifications of SMPTE 240 M. The preferred digitized image corrector comprises four hardware correction modules, which are coupled to receive correction parameters from an external source, such as an operator input subsystem. The four correction modules are chained together in a serial fashion. Each module has a bypass switch which allows a user to switch any module into a bypass mode such that the module's input is coupled directly to the module's output. At any one moment, one pair of correction modules are switched in a live data path. While a pair of modules are in the live data path, the other pair are in a bypass mode. While in bypass mode, an operator can reconfigure the modules' correction parameters without affecting the output image. After new parameters have been loaded into the bypassed modules, the user switches the bypassed pair into the live data path and the live modules into bypass mode, thereby inserting a new set of parameters into the live data path. Each correction module receives digitized input signals R in , G in , B in , and generates digitized output signals R out , G out , and B out by transforming digitized input signals R in , G in , B in according to a set of predetermined correction parameters that are received from the operator input subsystem controlled by the user. In general, a correction module performs a transformation of digitized input signals R in , G in , B in in accordance with the following arithmetic. R out = ƒ 0 [ƒ 3 (R in ) + ƒ 4 (G in ) + ƒ 5 (B in )] G out = ƒ 1 [ƒ 6 (R in ) + ƒ 7 (G in ) + ƒ 8 (B in )] B out = ƒ 2 [ƒ 9 (R in ) + ƒ 10 (G in ) + ƒ 11 (B in )] Functions ƒ 0 through ƒ 11 comprise a set of predetermined correction parameters supplied by the operator input subsystem and dynamically loaded into the correction module. The digitized image corrector generates R out , G out , and B out by transforming input signals R in , G in , B in , based upon the predetermined user supplied parameters received from the operator input subsystem. In the current embodiment of the present invention, the user supplied parameters generate digitized HDTV signals conforming to SMPTE 240M for coupling to an HDTV monitor or image storage device, in order to render a high quality HDTV video image from an original film image. The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: Figure 1 is an overall block diagram of a digital image processing system; Figure 2 is a block diagram of a digitized image corrector of the image processing system, including four correction modules. Figure 3 is a block diagram of an individual correction module, illustrating LUT circuits and adder circuits used to transform digitized input signals according to predetermined correction parameters; and Figures 4a - 4d provide a more detailed illustration of an individual correction module, including means for reading and writing transform data stored in the LUT circuits, and means for bypassing the correction module. A hardware implementation of a digitized image corrector in accordance with a preferred embodiment of the invention will now be disclosed. The image corrector converts a colorimetric representation of an original image into a new representation based upon data from the original and target images, as well as user supplied artistic parameters. In the following description, for purposes of explanation, specific circuit devices, circuit architectures, and components are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known circuits and devices are shown in schematic form in order not to obscure the present invention unnecessarily. The preferred hardware implementation of a digitized image corrector allows dynamic modification of correction parameters to achieve desired output specifications and artistic correction. The current embodiment of the present invention converts colorimetry of what was an image on film into HDTV. Additionally, digitized image correctors embodying the invention can solve a wide variety of data processing image processing problems, as will be described. Figure 1 is a block diagram of a digital image processing system that incorporates an image corrector embodying the invention. Image corrector subsystem 6 receives digitized input signals 15 from image sampling subsystem 8. Image corrector subsystem 6 also receives predefined correction parameters 17 from operator input subsystem 7. Image corrector subsystem 6 generates digitized output signals 16 which are coupled to image storage/display subsystem 9. Image sampling subsystem 8 is used for sampling physical images to generate digitized spatial samples for the images. In the current embodiment, image sampling subsystem 8 generates digitized Red, Green, and Blue video signals representing an original image on film. Image storage/display subsystem 9 receives digitized output signals 16 and stores and/or generates the output images defined by output signals 16. Image storage/display subsystem 9 is intended to represent a broad category of image storage and display devices, including HDTV monitors, video recording devices, laser disc devices and frame buffer storage mechanisms. In the current embodiment, image storage/display subsystem 9 represents devices that store and display images based on SMPTE 240M. Image corrector subsystem 6 interacts with a user through operator input subsystem 7. The user inputs commands into operator input subsystem 7 to generate correction parameters 17 for image corrector subsystem 6. The user may also input commands to retrieve correction parameters from image corrector subsystem 6. Image corrector subsystem 6 receives digitized input signals 15 and generates digitized output signals 16 based upon user defined correction parameters 17 received from operator input subsystem 7. In the current embodiment, the user defined parameters are used to convert digitized input signals 15 into digitized HDTV signals conforming to SMPTE 240M. Image corrector subsystem 6 will be described in further detail below with reference to Figure 2 . There are four correction factors required when converting an original film image into an HDTV image. They are: a) correct colorimetric distortion due to film dye crosstalk; b) correct the non-linear luminance transfer function of the film; c) correct for distortion due to video crosstalk; and d) convert this linear data into SMPTE 240M representation (i.e. predistort the data based upon the display gamma). In addition, for artistic correction a user may desire to change parameters based upon the quality of the visual image. The original correction parameters depend on the type of film used, and the final colorimetry is based upon the specifications of SMPTE 240M. Figure 2 provides a block diagram of image corrector subsystem 6. The digitized image corrector comprises four identical hardware correction modules: film A module 20, film B module 22, video A module 24, video B module 26. Modules 20, 22, 24 and 26 are coupled to receive correction parameters from CPU 40 over bus 140. The correction parameters are calculated by operator input subsystem 7 and downloaded to CPU 40 over bus 145. The digitized image corrector receives digitized input signals 15, in the current embodiment preferably comprising digitized Red 10, digitized Green 11, and digitized Blue 12 color signals representing the original film scene. The digitized image corrector generates digitized output signals 16, in the current embodiment preferably comprising digitized Red 10, digitized Green 11, and digitized Blue 12 color signals representing the original film scene. The four correction modules, film A 20, film B 22, video A 24, and video B 26 are chained together in a serial fashion so that the output of module 20 is coupled to the input of module 22, the output of module 22 is coupled to the input of module 24, and the output of module 24 is coupled to the input of module 26. Each module has a bypass switch controlled by CPU 40. This allows CPU 40 to switch any module into a bypass mode such that the input of a module is coupled directly to the module's output. When a module is not in bypass mode, it is in a live data mode wherein a transformation is performed on an input signal received by the module. During normal operation, a live data path comprises a series of digitized image signals received on signal lines 10 - 12, coupled to flow in series through signal lines 121, 122, and 123, and transmitted over signal lines 30 - 32. When a module is in bypass mode, it is removed from the live data path since its input is directly coupled to its output. At any one moment, in the current embodiment, either film A 20 and video A 24, or film B 22 and video B 26 are switched in the live data path. While film A 20 and video A 24 are in live data path, film B 22 and video B 26 are in bypass mode. Conversely, while film B 22 and video B 26 are in the live data path, film A 20 and video A 24 are in bypass mode. While a pair of modules, film A 20 and video A 24, or film B 22 and video B 26, are in bypass mode, CPU 40 can reconfigure the modules' correction parameters without affecting the digitized output signals 30 - 32. After new parameters have been loaded into the bypassed modules over bus 140, CPU 40 switches the bypassed pair into the live data mode and the live modules into bypass mode, thereby inserting a new set of parameters into the live data path. Moreover, during bypass mode, CPU 40 can read correction parameters from a module over bus 140. Film A module 20 generates digitized signals 121 by transforming Red 10, Green 11, and Blue 12 according to correction parameters preloaded into Film A module 20 by CPU 40. Similarly, film B module 22 transforms digitized signals 121 into digitized signals 122 according to correction parameters preloaded into Film B module 22 by CPU 40. Likewise, Video A module 24 transforms digitized signals 122 into digitized signals 123, and Video B module 26 transforms digitized signals 123 into digitized signal 30 - 32. As noted above, any one of modules 20, 22, 24, and 26 can be switched into a bypass mode wherein the module does not perform a transformation. With the modular approach illustrated in Figure 2 , it is possible to couple together as many hardware correction modules as required to meet the input/output specifications of the system. To perform the required image corrections to meet the system specifications, each hardware correction module 20, 22, 24, and 26 is loaded with a unique set of correction parameters set by CPU 40. These correction parameters are calculated by operator input subsystem 7 and down-loaded to CPU 40 over bus 145. In the current embodiment of the present invention, the hardware correction module parameters are generated by operator input subsystem 7 in order to convert digitized Red 10, digitized Green 11, and digitized Blue 12 color signals representing the original film scene into digitized output Red 30, Green 31, and Blue 32 according to the specifications of SMPTE 240 M. As their name suggests, film A module 20 and film B module 22 are used to perform film related corrections, and video A module 24 and video B module 26 are used to perform HDTV video related corrections. Figure 3 provides a block diagram of an individual hardware correction module, such as module 20, 22, 24, or 26. A correction module receives digitized input signals R in , G in , B in on signal lines 90, 91 and 92, respectively, and generates digitized output signals R out , G out , and B out on signal lines 95, 96, and 97, respectively. A correction module generates digitized output signals R out , G out , and B out by transforming digitized input signals R in , G in , B in according to a set of predetermined correction parameters that are received from CPU 40 over bus 140. The predetermined parameters are loaded into LUT circuits 50 - 61 while the module is in bypass mode. Thereafter, CPU 40 switches the module into live mode to perform the transformation. In the current embodiment of the present invention, the correction module of Figure 3 performs a transformation of digitized input signals R in , G in , B in in accordance with the following arithmetic. R out = ƒ 0 [ƒ 3 (R in ) + ƒ 4 (G in ) + ƒ 5 (B in )] G out = ƒ 1 [ƒ 6 (R in ) + ƒ 7 (G in ) + ƒ 8 (B in )] B out = ƒ 2 [ƒ 9 (R in ) + ƒ 10 (G in ) + ƒ 11 (B in )] where, ƒ 0 , ƒ 1 , ƒ 2 - non linear transfer functions ƒ 3 = crosstalk component of Red in Red ƒ 4 = crosstalk component of Green in Red ƒ 5 = crosstalk component of Blue in Red ƒ 6 = crosstalk component of Red in Green ƒ 7 = crosstalk component of Green in Green ƒ 8 = crosstalk component of Blue in Green ƒ 9 = crosstalk component of Red in Blue ƒ 10 = crosstalk component of Green in Blue ƒ 11 = crosstalk component of Blue in Blue Functions ƒ 0 through ƒ 11 comprise a set of predetermined correction parameters supplied by operator input subsystem 7. In the correction module of Figure 3 , functions ƒ 0 through ƒ 11 are implemented using lookup table (LUT) circuits 50 - 61, which are preloaded with transform data needed to perform functions ƒ 0 through ƒ 11 . Each LUT circuit 50 - 61 enables CPU 40 to load any predetermined function over bus 140. Each LUT circuit 50 - 61 has a programmable data path controlled by CPU 40, and an auto increment subcircuit that allows CPU 40 to quickly load transform data to perform the desired function or functions. CPU 40 may also read transform data stored in LUT circuits 50 - 61. Each LUT 50 - 61 is comprised of at least four banks of transform data, which allows CPU 40 to preload transform data for four different functions into each LUT circuit 50 - 61. Thereafter, CPU 40 can modify the function being performed by each LUT circuit 50 - 61, in real time, by switching banks of individual LUT circuits 50 - 61. The ability to switch functions in real time is useful for implementing moving mattes, doing localized color correction, doing A/B comparisons between various curves, and for doing colorimetry changes in real time at a scene change. Adder circuits 70, 71 and 72 are very fast synchronous clipping circuits capable of adding three 20 bit values in 54 nano-seconds. The inputs are formatted as signed values with three significant digits and 16 fractional bits. The output of each adder 70, 71, and 72 is a 16 bit unsigned quantity with two significant digits and 14 fractional bits. Since the sum could be acceptable, negative, or overflow the legal two significant bits, the circuit has provisions to clip the output value to all zeros or all ones, as required. In the current embodiment of the present invention, functions ƒ 0, ƒ 1, and ƒ 2 have 16 bit inputs and a 16 bit outputs. Functions ƒ 3, · ƒ 11 have 16 bit inputs and 20 bit outputs. A critical element of system performance is the precision used in implementing LUT circuits 50 - 61 and adder circuits 70 - 72. The bit widths used were chosen to result in a final error of no more than one LSB (less than .1%). To perform digitized image correction, CPU 40 preloads LUT circuit 50 with transform data necessary to implement function ƒ 7 . Similarly, CPU 40 preloads LUT circuit 51 with transform data to implement function ƒ 4 and LUT circuit 52 with transform data to implement function ƒ 10 . In a similar manner, CPU 40 preloads LUT circuits 53, 54, and 55 with transform data to implement functions ƒ 6 , ƒ 3' and ƒ 9 , respectively. Likewise, CPU 40 loads LUT circuits 56, 57 and 58 with transform data to implement functions ƒ 8 , ƒ 5 , and ƒ 11 , respectively. LUT circuits 50, 51, and 52 are coupled to receive G in 91, LUT circuits 53, 54, and 55 are coupled to receive R in 90, and LUT circuits 56, 57 and 58 are coupled to receive B in 92. During live data transformation, LUT circuit 50 generates a digitized signal equal to ƒ 7 (G in ). Likewise, LUT circuit 51 generates ƒ 4 (G in ), and LUT circuit 52 generates ƒ 10 (G in ). In a similar manner, LUT circuits 53, 54, and 55 generate ƒ 6 (R in ), ƒ 3 (R in ), and ƒ 9 (R in ), respectively. LUT circuits 56, 57 and 58 generate ƒ 8 (B in ), ƒ 5 (B in ), and ƒ 11 (B in ), respectively. By examining Figure 3 , it will be appreciated that input 150 of adder circuit 70 equals ƒ 7 (G in ). Moreover, input 151 of adder circuit 70 equals ƒ 6 (R in ), and input 152 of adder circuit 70 equals ƒ 8 (B in ). As a consequence, output 170 of adder circuit 70 equals the arithmetic sum of the foregoing terms, or ƒ 6 (R in ) + ƒ 7 (G in ) + ƒ 8 (B in ). LUT circuit 59 is preloaded by CPU 40 with transform data to implement function ƒ 1 . Therefore, digitized signal 159 equals ƒ 1 [ƒ 6 (R in ) + ƒ 7 (G in ) + ƒ 8 (B in )] as given by Eq. 2 above. Selector 80 multiplexes digitized signal 159 and G in 91 to G out 96 under control of CPU 40. Similarly, it will be appreciated that input 153 of adder circuit 71 equals ƒ 4 (G in ), input 154 of adder circuit 71 equals ƒ 3 (R in ), and input 155 of adder circuit 71 equals ƒ 5 (B in ). Thus, output 171 of adder circuit 71 equals the arithmetic sum of the foregoing terms, or ƒ 3 (R in ) + ƒ 4 (G in ) + ƒ 5 (B in ). LUT circuit 60 is preloaded by CPU 40 with transform data to implement function ƒ 0 . Therefore, digitized signal 160 equals ƒ 0 [ƒ 3 (R in ) + ƒ 4 (G in ) + ƒ 5 (B in )] as given by Eq. 1 above. Selector 81 multiplexes digitized signal 160 and R in 90 to R out 95 under control of CPU 40. Finally, input 156 of adder circuit 72 equals ƒ 10 (G in ), input 157 of adder circuit 72 equals ƒ 9 (R in ), and input 158 of adder circuit 72 equals ƒ 11 (B in ). Thus, output 172 of adder circuit 72 equals ƒ 9 (R in ) + ƒ 10 (G in ) + ƒ 11 (B in ). LUT circuit 60 is preloaded by CPU 40 with transform data to implement function ƒ 2 . Therefore, digitized signal 161 equals ƒ 2 [ƒ 9 (R in ) + ƒ 10 (G in ) + ƒ 11 (B in )] as given by Eq. 3 above. Selector 82 multiplexes digitized signal 161 and B in 92 to B out 97 under control of CPU 40. Figures 4a - 4d provide a more detailed block diagram of a correction module. Figure 4a illustrates the circuitry used to load transform data into LUT circuits 50 - 52. Multiplexer circuit 250 is coupled to receive G in 91 and CPU address signals over bus 140. During bypass mode, multiplexer circuit 250 transmits CPU address signals from bus 140 to LUT circuits 50 - 52 over signal lines 255 in order to load transform data. Transform data from CPU 40 is received by transceiver circuits 251, 252, and 253 over bus 140. Transceiver circuit 251 is coupled to transmit and receive transform data to and from LUT circuit 50. Similarly, transceiver circuit 252 is coupled to transmit and receive transform data to and from LUT circuit 51, and transceiver circuit 253 is coupled to transmit and receive transform data to and from LUT circuit 53. During live data mode, multiplexer circuit 250 transmits G in 91 to LUT circuits 50 - 52 over signal lines 255 in order to transform G in . Figure 4b illustrates the circuitry used to load transform data into LUT circuits 53 - 55. Multiplexer circuit 260 is coupled to receive R in 90 and CPU address signals over bus 140. Multiplexer circuit 260 transmits CPU address signals from bus 140 to LUT circuits 53 - 55 over signal lines 265 in order to load transform data during bypass mode. Transform data is received by transceiver circuits 261, 262, and 263 over bus 140. Transceiver circuit 261 is coupled to transfer transform data to and from LUT circuit 53, transceiver circuit 262 is coupled to transfer transform data to and from LUT circuit 54, and transceiver circuit 263 is coupled to transfer transform data to and from LUT circuit 55. Multiplexer circuit 260 transmits R in 90 to LUT circuits 53 - 55 over signal lines 265 in order to transform R in during the live data mode Figure 4c illustrates the circuitry used to load transform data into LUT circuits 56 - 58. Multiplexer circuit 270 is coupled to receive B in 92 and CPU address signals over bus 140, and to transmit CPU address signals from bus 140 to LUT circuits 56 - 58 over signal lines 275 in order to load transform data during bypass mode. Transform data is received by transceiver circuits 271, 272, and 273 over bus 140. Transceiver circuit 271 is coupled to transfer transform data to and from LUT circuit 56, transceiver circuit 272 is coupled to transfer transform data to and from LUT circuit 57, and transceiver circuit 273 is coupled to transfer transform data to and from LUT circuit 58. Multiplexer circuit 270 transmits B in 92 to LUT circuits 56 - 58 over signal lines 275 in order to transform B in during the live data mode Figure 4d illustrates circuitry used to load LUT circuits 59 - 61, and circuitry used to switch between bypass mode and live data mode under control of CPU 40. Multiplex circuits 280, 281, and 282 are coupled to receive address signals from CPU 40 over bus 140. Transceiver circuits 283, 284, and 285 are coupled to transfer data between CPU 40 and LUT circuits 59, 60, and 61, respectively. Transform data is received by transceiver circuits 283, 284, and 285 over bus 140. Transceiver circuit 283 is coupled to transfer transform data to and from LUT circuit 59, transceiver circuit 284 is coupled to transfer transform data to and from LUT circuit 60, and transceiver circuit 285 is coupled to transfer transform data to and from LUT circuit 61. Digitized signal 159, defined by Eq. 2 during live data transformation, and G in 91 are multiplexed to G out 96 by multiplexer 80 under control of CPU 40. Similarly, digitized signal 160, defined by Eq. 1 during live data transformation, and R in 90 are multiplexed to R out 95 by multiplexer 81 under control of CPU 40, and digitized signal 161, defined by Eq. 3 during live data transformation, and B in 92 are multiplexed to B out 97 by multiplexer 82 under control of CPU 40. Thus, when CPU 40 switches the correction module into bypass mode, R out = R in , G out = G in , and B out = B in . An alternative embodiment of the present invention may be employed to provide color space conversion. As discussed above, R out = ƒ 0 [ƒ 3 (R in ) + ƒ 4 (G in ) + ƒ 5 (B in )] G out = ƒ 1 [ƒ 6 (R in ) + ƒ 7 (G in ) + ƒ 8 (B in )] B out = ƒ 2 [ƒ 9 (R in ) + ƒ 10 (G in ) + ƒ 11 (B in )]. if ƒ 0 , ƒ 1 , and ƒ 2 are each set to one, then ƒ 3 through ƒ 11 can be set to convert the input signal into a new color space. Examples are RGB video to YUV video, or HIS to YIQ. This has wide application in computer graphics and video. Alternatively, if ƒ 5 , ƒ 7 , and ƒ 9 are each set to zero, and ƒ 3 , ƒ 4 , ƒ 6 , ƒ 8 , ƒ 10 , and ƒ 11 are the log function, and ƒ 0 , ƒ 1 , and ƒ 2 are the exponential function, then the correction module implements the following functions: R out = exp [log (R in ) + log (G in )] G out = exp [log (R in ) + log (B in )] B out = exp [log (G in ) + log (B in )]. Since addition in the log domain is equivalent to multiplication in the linear domain, the correction module becomes a multiplier. Thus, an alternative embodiment of the present invention provides one module which removes an offset by being configured for subtraction and a second module that multiplies by a gain by being configured for multiplication. The present invention has application for use in image processing environments and may be incorporated into a variety of data processing circuitry. Although the present invention has been described in conjunction with the embodiments illustrated in Figures 1 through 4, it is evident that numerous alternatives, modifications, variations and uses will be apparent to those skilled in the art in light of the foregoing description.

Claims: A digitized image corrector for transforming a first digitized representation (10,11,12) of an image into a second digitized representation (30,31,32) of said image in accordance with a first transformation function (f 0 to f 11 ) defined by a first set of transform data, a second transformation function defined by a second set of transform data, a third transformation function defined by a third set of transform data, and a fourth transformation function defined by a fourth set of transform data, comprising: first, second, third and fourth correction circuits for receiving a respective one of said first, second, third and fourth sets of transform data from a user and connected in series, each correction circuit having three inputs and three outputs and serving to either transform digitized signals appearing at said inputs in accordance with a respective one of said first, second, third or fourth transformation functions or sending said digitized signals directly to said outputs; and image storage means (9) for storing said second digitized representation of said image for subsequent display; wherein each of said first, second, third and fourth correction circuits comprises: first function means (50,51,52) for performing three transformations on a first digitized signal (91), said first function means coupled to receive said first digitized signal, said first function means generating a first signal (150), a second signal (153) and a third signal (156); second function means (53,54,55) for performing three transformations on a second digitized signal (90), said second function means coupled to receive said second digitized signal, said second function means generating a fourth signal (151), a fifth signal (154) and a sixth signal (157); third function means (56,57,58) for performing three transformations on a third digitized signal (92), said third function means coupled to receive said third digitized signal, said third function means generating a seventh signal (152), an eighth signal (155) and a ninth signal (158); first adder means (70) for generating a first term signal (170) equal to the arithmetic sum of said first signal (150), said fourth signal (151), and said seventh signal (152), said first adder means coupled to receive said first signal, said fourth signal, and said seventh signal; second adder means (71) for generating a second term signal (171) equal to the arithmetic sum of said second signal (153), said fifth signal (154), and said eighth signal (155), said second adder means coupled to receive said second signal, said fifth signal, and said eighth signal; third adder means (72) for generating a third term signal (172) equal to the arithmetic sum of said third signal (156), said sixth signal (157), and said ninth signal (158), said third adder means coupled to receive said third signal, said sixth signal, and said ninth signal; fourth function means (59) for transforming said first term signal (170), said fourth function means coupled to receive said first term signal, said fourth function means generating a first transformed signal (96); fifth function means (60) for transforming said second term signal (171), said fifth function means coupled to receive said second term signal, said fifth function means generating a second transformed signal (95); and sixth function means (61) for transforming said third term signal (172), said sixth function means coupled to receive said third term signal, said sixth function means generating a third transformed signal (97) said first, second and third transformed signals together forming the output of the respective correction circuit. The digitized image corrector defined by claim 1, wherein said image storage means comprises frame buffer memory means. The digitized image corrector defined by claim 1, wherein said image storage means comprises video tape storage means. The digitized image corrector defined by claim 1, wherein said image storage means comprises laser disc storage means.

Inventors: BENNETT GARY M, CAPITANT PATRICE, COLLIER DAVE, MORGAN O F, ROSSMERE DAVID, BENNETT, GARY M., CAPITANT, PATRICE, COLLIER, DAVE, MORGAN, O.F., ROSSMERE, DAVID
Applicants: SONY ELECTRONICS INC A DELAWAR, SONY ELECTRONICS INC. (A DELAWARE CORPORATION)
Application year: 1993
Main classification: H04N9
IPC codes: H04N9