Interface circuit for controlling data transfers

Abstract: To provide an interface circuit which performs data transfer surely without a wasteful waiting time with the same hardware, whether the status reading by a host is performed before or after the data transfer. The interface circuit comprises interrupt means (60) for generating an interrupt request (IRQ) to a host (12) in response to a data request (DRQ) from a peripheral device (HDD) and dropping the interrupt request if the status of the peripheral device is read by the host, mode detecting means (62) for detecting that the host operates in a post-read mode, and interrupt enable means (64) responsive to the post-read mode detect signal from the mode detecting means and the status reading by the host to enable the interrupt means to regenerate the interrupt request to the host.

Description: Field of the Invention The present invention relates to an interface circuit for controlling data transfers, and more particularly to an interface circuit for performing data transfers between a peripheral device such as a hard disk drive (HDD) and a host by an interrupt from the peripheral device to the host. Background Art In personal computer systems, the AT interface is widely used to connect a host with its peripheral devices. An HDD is a typical peripheral device. From a viewpoint of peripheral manufacturers, it is desired that communications with a host through the AT interface be standardised, but some commands allow more than one operation sequence. For example, a Read command for an HDD is executed in either one of two operation sequences depending on when a status register of the HDD is read by the host. The first operation sequence is as follows: 1. When data (usually in one sector) becomes ready to be transferred to the host, the HDD sets a data request (DRQ) bit of the status register high and at the same time asserts an interrupt request IRQ to the host. 2. Receiving the IRQ from the HDD, the host first reads the status register of the HDD (the IRQ is reset or dropped at that time. The IRQ is always reset whenever the status register is read by the host.) and then starts a data transfer. 3. When the transfer of a sector of data is completed, the HDD once again resets the DRQ bit. 4. Steps 1 to 3 are repeated for the requested number of sectors. In the above sequence, the host reads the status register before the data transfer is started, and therefore, the sequence is hereinafter referred to as "pre-read". However, some hosts handle the Read command as follows. 1. Same as Step 1 of the pre-read. 2. Receiving the IRQ from the HDD, the host first starts a data transfer which continues till the end of that sector. 3. Same as Step 3 of the pre-read. 4. The host reads the status register of the HDD (the IRQ is reset thereby). 5. Steps 1 to 4 are repeated for the requested number of sectors. In the second sequence, the host reads the status register after the transfer of a sector of data is completed, and therefore, this sequence is hereinafter referred to as "post-read". If the host operates in a post-read mode, a malfunction would occur in the case where the host attempts to read the status register of the HDD to obtain the current sector status (Step 4 of the post-read) after the next sector of data becomes ready to be transferred in the HDD (Step 1 following Step 4). In this case, an IRQ for the next sector is reset by the status register reading for the previous sector transfer, which results in an abnormal situation where the host continues to wait for the IRQ for the next sector while the HDD continues to wait for the data transfer. In fact, such abnormal situation has occurred, since the IRQ for the next sector is asserted by hardware as soon as the sector data becomes available. To avoid the abnormal situation described above, it is necessary to assert the IRQ for the next sector after the host reads the status register. However, since the above abnormal situation will not occur when the host is in the pre-read mode, a scheme to merely delay the IRQ would cause a problem that the performance of data transfer is lowered when the host is in the pre-read mode. Therefore, the prior art has adopted a method in which a switch is set according to whether the host is in the pre-read mode or the post-read mode and, in case of the post-read, the IRQ is asserted again immediately after the status register is read instead of delaying the IRQ. Thus, the performance is not lowered even in case of the post-read. However, in modern hosts, there are many cases where either one of the pre-read and post-read modes is used depending on an operating system (OS) (for example, the pre-read and post-read modes are used under OS/2 and conventional DOS, respectively) and therefore the switch must be set each time mode changes. Another method uses a microcode to entirely control the IRQ. According to the method, since the IRQ is always asserted late, both the pre-read and post-read modes function normally, while the performance is not good as compared with the hardware control. To solve the problems as described above, Japanese Patent Application No. 3-337995, which is a prior application of the present assignee, discloses an interface circuit which automatically detects whether the host is in the pre-read mode or the post-read mode. The interface circuit includes a mode detecting circuit for automatically detecting a mode of the host according to the states of a data request signal DRQ from a controller of the HDD and an interrupt request signal IRQ to be transmitted to the host, a delay circuit for delaying the DRQ by a predetermined amount of time when the host is in the post-read mode, and an interrupt request generating circuit for generating an IRQ to the host in response to an output (controlled DRQ) from the delay circuit. When the mode detecting circuit detects that the host is in the pre-read mode, the delay circuit does not operate and the DRQ is provided, without delay, to the interrupt request generating circuit as a controlled DRQ. When the above interface circuit is used, performance is improved as compared with the conventional methods for changing by swicth and for controlling by microcode, but there is a problem that an IRQ cannot be immediately generated even if the host has completed the status reading before the predetermined delay time elapses since the delay time of the DRQ is previously fixed. So, it would be desirable to provide an interface circuit which can accurately cope with both pre-read and post-read with the same hardware, and also can generate the next interrupt request immediately after the status reading is performed if the host is in the post-read mode. Disclosure of the Invention The present invention relates to an interface circuit which accurately performs data transfers irrespective of the mode of a host in a computer system in which data is transferred, based on an interrupt, between a peripheral device and the host. In such a computer system, a peripheral device generates a data request and sends an interrupt request to the host when a block of data is ready to be transferred. The host responds to the interrupt request and operates either in a first mode to start a block data transfer after reading status of the peripheral device or in a second mode to read the status of the peripheral device after completing the block data transfer. The interface circuit of the present invention comprises interrupt means for generating the interrupt request to the host in response to the data request from the peripheral device and dropping the interrupt request if the status is read by the host, mode detecting means for detecting that the host is in the second mode if the status of the peripheral device is not yet read even if the next data request is generated, and means responsive to the second mode detect signal from the mode detecting means and the status reading by the host to enable said interrupt means to regenerate the interrupt request to the host. Brief Description of the Drawings Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: FIG.1 is a block diagram showing an example of the configuration of a computer system including an interface circuit according to the present invention; FIG.2 is a block diagram showing the configuration of an input/output section for a host in the interface circuit shown in figure 1; FIG.3 is a block diagram showing the configuration of an interrupt control section in the interface circuit shown in figure 1; FIG.4 is a detailed circuit diagram of the interrupt control section shown in FIG.3. FIG.5 is a timing chart of operations in a case where the host is in the pre-read mode; and FIG.6 is a timing chart of operations in a case where the host is in the post-read mode. Detailed Description of the Invention An overall system configuration including the interface circuit of the present invention is shown in FIG. 1. Although a peripheral device is assumed to be an HDD in this embodiment, the present invention can be applied to any peripheral device having the above-mentioned problems with respect to the pre-read and post-read. In FIG. 1, an HDD 10 enclosed by broken lines is connected to a host 12 through an interface circuit 14 and a system bus (AT bus) 16. The host 12 includes a microprocessor such as i80386 or the like and forms a Personal Computer AT system of the present assignee or its compatible system together with the HDD 10 and other peripheral devices ( keyboard, display, etc.) not shown. The HDD 10 includes a microprocessor-controlled device controller 18 which controls the entire HDD. The device controller 18 has three main functions, that is, control of reading and writing by a head 20, control of a voice coil motor (VCM) 22 for moving the head 20, and control of a spindle motor 24 for rotating a disk (not shown). A sector buffer 26 and a read/write (R/W) circuit 28 are used to read or write by the head 20. The sector buffer 26 can store 64 sectors of data (32 Kbytes) in the embodiment. The R/W circuit 28 has a well-known configuration including various circuits necessary for reading and writing, that is, an amplifier, a peak detecting circuit, a variable frequency oscillator (VFO), an encoder, a decoder, a servo logic, an analog-to-digital converter, a digital-to-analog converter, etc. The VCM 22 and the spindle motor 24 are controlled through a VCM driver 30 and a spindle driver 32, respectively. Since, except for the interface circuit 14, each of the system components shown in FIG.1 may be a conventional one having a well-known configuration, details thereof are not described here. FIG.2 shows a configuration of an input/output section of the interface circuit 14. The input/output section includes plural registers selected by a register selector 40, that is, a sector count register 42, an address register 44, a command register 46, a data register 48, and a status register 50. Although the address register 44 actually consists of four registers (two cylinder address registers, one sector address register, and one drive/head address register), these registers are treated, for convenience, as a single register in the following explanation. The sector count register 42 retains the number of sectors to be read or written, the address register 44 retains a start address thereof, the command register 46 retains a command code, the data register 48 retains data to be written to the HDD 10 from the host 12 or data to be read out to the host 12 from the HDD 10, and the status register 50 contains a plurality of bits indicating status of the HDD. These registers are selected by the information provided to the register selector 40 from the host 12 through the system bus 16. At that time, the register selector 40 generates a signal Si (i=1,2,3,..) for selecting a specified register. Although FIG.2 shows only five registers necessary for the understanding of the present invention, more than five registers are actually provided. When the host 12 sends a command to the interface circuit 14, it places an address for selecting a particular register and an input/output write (-IOW) signal on a bus 16A and information to be written to the selected register on a bus 16B. The buses 16A and 16B are included in the system bus 16. Taking a Read command as an example, the host 12 first transmits signals for indicating a write to the sector count register 42, that is, an address of the sector count register 42 and an input/output write signal over the bus 16A and a sector count over the bus 16B. The register selector 40 generates a signal S1 for selecting the sector count register 42 in response to the signal on the bus 16A to load the sector count on the bus 16B into the register 42. Then the host 12 transmits signals for indicating a write to the address register 44 and a start address over the buses 16A and 16B, respectively. The register selector 40 thereby generates a signal S2 selecting the address register 44 to load the start address on the bus 16B into the register 44. Finally the host 12 transmits signals for indicating a write to the command register 46 and a Read command code over the buses 16A and 16B, respectively, and the Read command code is thus loaded into the command register 46. Upon completion of loading into the registers 42, 44, and 46, the controller 18 then performs a read operation specified by the contents thereof and writes data read from the disk (not shown) to the sector buffer 26. For a Write command, data to be written to the disk is additionally transmitted from the bus 16B to the data register 48. In the write operation, the above-mentioned problem of the pre-read and post-read does not occur, and therefore it is not described here. Data transfers from the HDD 10 to the host 12 during the read operation are performed on an interrupt basis. As described above, the HDD 10 transmits a data request signal DRQ to the interface circuit 14 when a predetermined number of sectors of data (for example, one sector of data) is written to the sector buffer 26 from the disk and thus data is ready to be transferred to the host. The interface circuit 14 responds to the DRQ and sends an interrupt to the host 12 to start data transfer from the sector buffer 26 to the host 12. An interrupt control section of the interface circuit is shown in FIG. 3, which efficiently performs the data transfer based on the interrupt whether the host 12 is in the pre-read or post-read mode. The interrupt control section of FIG.3 includes an interrupt request generating circuit 60 for generating an interrupt request IRQ to the host 12 in response to a DRQ from the controller 18. The circuit 60 drops the IRQ when the status is read by the host 12. The DRQ and IRQ are also provided to a post-read mode detecting circuit 62. The post-read mode detecting circuit 62 generates a post-read signal indicating that the host 12 is in the post-read mode if the status is not yet read by the host 12, that is, if the previous IRQ still remains generated when the next DRQ is generated. The post-read signal is provided to an interrupt enable circuit 64. The interrupt enable circuit 64 enables the interrupt request generating circuit 60 to generate a new IRQ in response to the post-read signal and the status reading by the host 12. FIG.4 shows a detailed circuit diagram of the interrupt control section. The interrupt control section includes a first flip-flop 70 operating as the interrupt request generating circuit 60 and a second flip-flop 72 operating as the post-read mode detecting circuit 62. A third flip-flop 74, a counter 76, a delay value register 78, and a comparator 80 compose the interrupt enable circuit 64 in FIG. 3. A data terminal D of the first flip-flop 70 is always kept high and its clock terminal CK receives a data request signal DRQ from the controller 18. A negative set terminal -S is connected to an output of the comparator 80 and a negative reset terminal -R is connected to an output of a NOR gate 82. Both of two inputs of the NOR gate 82 are inverted ones and receive the output of a NAND gate 84 and a negative reset signal -RST generated at the time of initial reset such as power-on, respectively. One input of the NAND gate 84 receives a signal S5 from the register selector 40 in FIG.2 and the other input receives an input/output read signal -IOR from the host 12. A Q output of the first flip-flop 70 is connected not only to a data terminal D of the second flip-flop 72, but also to a bus line to the host 12 through a bus driver (not shown). A clock terminal CK of the second flip-flop 72 also receives the DRQ. A Q output of the second flip-flop 72 is connected to a data terminal D of the third flip-flop 74 and its negative reset terminal -R is connected to an output of a NOR gate 86. The NOR gate 86 receives the above reset signal -RST and the output of the comparator 80. A clock terminal CK of the third flip-flop 74 whose data terminal D is connected to the Q output of the second flip-flop 72 is connected to an output of the NAND gate 84, its negative reset terminal -R is connected to the output of the NOR gate 86, and its Q output is connected to a negative reset terminal -R of the counter 76. The counter 76 is released from the reset state by a negative input to the negative reset terminal - R so that it starts counting in response to a clock. A count value of the counter 76 is provided to a first input A of the comparator 80. Provided to a second input B of the comparator 80 is a delay value retained in the delay value register 78. A predetermined delay value is loaded into the delay value register 78 from a microprocessor (not shown) of the controller 18 at each power-on time. An inverted output of the comparator 80 is connected to the negative set terminal -S of the first flip-flop 70 and one of inverted inputs of the NOR gate 86. It is assumed that each of the flip-flops 70, 72, and 74 in the embodiment of FIG.4 is set to the state of it data terminal D in response to a positive transition at its clock terminal CK and is reset when its reset terminal -R becomes low. The flip-flop 70 is set when the set terminal S becomes low. However, as far as the present invention is concerned, each flip-flop may be a negative transition response type, and also be a type which is set and reset by a high level signal. Further, with respect to the logic, it is also possible to use the positive logic of AND and OR instead of the negative logic of NAND and NOR. Next, the operations of the interface circuit according to the present invention are described in detail with reference to FIG.5 showing a time chart for the pre-read and FIG.6 showing a time chart for the post-read. 1. Pre-read As described above, a Read command includes a sector count which specifies the number of sectors to be read, a start address, and a command code. When they are received by the registers 42, 44, and 46 in FIG.2, respectively, the controller 18 starts to read data from the disk to the sector buffer 26. When a sector of data is written to the sector buffer 26, the controller 18 generates a data request signal DRQ and sends it to the interrupt control section (FIG.3) of the interface circuit 14. The DRQ is applied to the clock terminal CK of the flip-flops 70 and 72. Since the data terminal D of the first flip-flop 70 is always kept high, the flip-flop 70 is set by the positive transition of the DRQ so that its Q output or an interrupt request IRQ becomes high to interrupt the host 12. Although the DRQ is applied also to the clock terminal CK of the second flip-flop 72, the flip-flop 72 remains reset since the Q output of the first flip-flop 70 does not yet become high when the DRQ is changed from low to high. The host 12 in the pre-read mode reads the status register 50 in the interface circuit 14 in response to the interrupt request IRQ from the HDD 10 to know the status of the HDD 10 before starting data transfer. To this end, the host 12 transmits signals indicating read of the status register 50, that is, an address of the status register 50 and an input/output read signal -IOR over the bus 16A. In response to the signals, the register selector 40 generates a signal S5 for selecting the status register 50 to cause its contents to be gated to the bus 16B. The status register 50 contains not only the DRQ bit described above, but also a plurality of status bits representing the status of the HDD 10 such as a busy bit indicating that the HDD 10 is busy, an error bit indicating that an error has occurred during the command execution, etc. The status register selecting signal S5 is applied also to a first input of the NAND gate 84. Applied to a second input of the NAND gate 84 is an input/output read signal -IOR from the host 12. This signal indicates reading of various I/O registers (refer to FIG.2) in the interface circuit 14 and is defined, in the AT interface, as active low. The NAND gate 84 is conditioned by the active S5 and -IOR to set the output - STATRD indicating the status reading by the host 12 to low. This output -STATRD is provided, through the NOR gate 82, to the negative reset terminal -R of the first flip-flop 70 to reset the flip-flop 70. Thus the interrupt request IRQ to the host 12 is dropped (refer to a waveform of the IRQ shown in FIG.5). Although the output -STATRD is applied also to the clock terminal CK of the third flip-flop 74, the flip-flop 74 remains reset even if the -STATRD is changed from low to high since the data terminal D (Q output of the flip-flop 72) is kept low at that time. To read data written to the sector buffer 26, the host 12 transmits signals for reading the data register 48 over the bus 16A after reading the status register 50. If it is assumed that a bit width of the data register 48 is 16 bits and one sector is 512 bytes, then the host 12 must read the data register 48 256 times for each sector. The data register 48 may be either a latch type or a gate type. If the data register 48 is a latch type, the controller 18 generates a data request signal DRQ after loading the first 16 bit-word from the sector buffer 26 into the data register 48, and thereafter, sequentially reads a 16 bit-word from the sector buffer 26 and loads it into the data register 48 each time the host 12 reads the data register 48. If the data register 48 is a gate type, the controller 18 generates a DRQ at the time when a sector of data is written into the sector buffer 26 and, thereafter, sequentially reads a 16 bit-word from the sector buffer 26 and gates it to the bus 16B each time the host 12 directs a read of the data register 48. In either case, the controller 18 counts the read signals -IOR's from the host 12 and drops the DRQ when the count reaches 256. Thereafter, when the next sector of data is ready to be transferred, the controller 18 sets the DRQ high again and repeats the above operation. In this connection, if the next sector data is read from the disk and written to the sector buffer 26 after the host 12 reads the first sector data, it would take a longer time to complete the Read command. Therefore, it is preferable that a read from the sector buffer 26 to the host 12 and a write from the disk to the sector buffer 26 are performed in parallel. In this case, data from the disk is written to the sector buffer 26 while data read from the sector buffer 26 is transferred to the host 12, that is, a read operation of the sector buffer 26 is not performed. The same is true of the post-read mode described below. When the number of sector data transferred to the host 12 reaches the sector count loaded into the sector count register 42, the execution of the Read command is completed. 2. Post-read Operations in the case where the host 12 is in the post-read mode are the same as in the pre-read mode until an interrupt request IRQ is generated. In the post-read mode, the host 12 starts data transfer from the sector buffer 26 to the host 12 by first directing a read of the data register 48 in response to the interrupt request IRQ. After reading a sector of data, the host 12 directs a read of the status register 50. In the interface circuit 14, likewise the pre-read, a DRQ becomes low when the host 12 has read 512 bytes of sector data. However, as shown in FIG.6, at the time when the DRQ becomes low, the status register 50 is not yet read so that the flip-flop 70 is not reset and the interrupt request IRQ remains high. In this condition, when the next sector data is ready to be transferred and the DRQ becomes high again, the second flip-flop 72 is also set a high Q output since the first flip-flop 70 has already been set. This indicates that the host 12 is in the post-read mode. When the host 12 reads the status register 50 with the flip-flop 72 being set, a negative pulse appears at the output (-STATRD) of the NAND gate 84, the third flip-flop 74 is set and the first flip-flop 70 is reset through the NOR gate 82 to thereby make the IRQ low. The high Q output of the flip-flop 74 releases the reset state of the counter 76. So far as the flip-flop 74 is reset and the negative reset terminal -R of the counter 76 is kept low, the counter 76 remains reset. When the counter 76 is released from the reset state, it starts counting and increments by one each time a clock pulse is applied. The contents of the counter 76 are provided to the comparator 80 to compare with the contents of the delay value register 78. The delay value register 78 retains a predetermined delay value loaded from a microprocessor (not shown) of the controller 18 during the power-on operation. The delay value is programmable and previously set so as not to hinder the interrupt response of the host 12. Generally, the delay value loaded into the register 78 depends on a host to which the HDD 10 is connected and, for example, may be set to 1 if the host allows a situation in which an IRQ may become high at any time after the status reading, that is, the host can issue the next command (in this case, a data register read command) immediately after the status register read command. If the delay value is 0, the flip-flop 70 cannot be successfully set since the output of the comparator 80 is always active (low) as far as the counter 76 is reset. In any case, the delay value should be set in consideration of an amount of time required until the host can respond (issue a command) after the IRQ once became low. If so set, the IRQ can be set high immediately after the host is ready to respond so that wasteful waiting time is eliminated. When a count value of the counter 76 becomes equal to the contents of the delay value register 78, the output of the comparator 80 becomes low to thereby set the flip-flop 70, and to reset the flip-flops 72 and 74 through the NOR gate 86. When the flip-flop 70 is set, the IRQ becomes high again to request an interrupt to the host 12. Thus, according to the present invention, even if an IRQ is not yet reset when a DRQ rises in each of second and subsequent sector data transfers, an IRQ for the next sector data transfer can be surely generated without a waiting time. When a specified number of sector data is read by the host 12, the execution of a Read command is completed. Some hosts, which operate in the post-read mode, perform the status reading a plurality of times for one sector data transfer. The circuit of FIG.4 preferably operates also for such hosts. However, in that case, the delay value set to the delay value register 78 should be determined to be equal to, at least, an amount of time from the first status reading to the last status reading plus an amount of time required until a host is ready to respond after the last status reading. The operations of the circuit of FIG.4 are the same as in the above description with the exception that the generation of equal output from the comparator 80 and accordingly the rise of an IRQ and the reset of the flip-flop 72 are delayed as compared with those of FIG.6. Although the first status reading resets the flip-flop 70, the second and subsequent status readings have no effect on the circuit of FIG.4. Although the preferred embodiments have been described, the present invention is not limited thereto and allows various modifications. For example, in the embodiments, the DRQ and IRQ were controlled based on the 512-byte sector as a unit block. However, it is appreciated that the length of the unit block is not limited to 512 bytes and may be determined arbitrarily within a suitable range. Further, as described above, each flip-flop in the circuit of FIG.4 may be a negative transition response type, and it is also possible to use positive logic such as AND and OR as basic logic. The present invention can accurately cope with any host with the same hardware whether the host is in the pre-read mode or the post-read mode, and can send an interrupt request to the host practically without waiting time if the host is in the post-read mode.

Claims: An interface circuit (14) for controlling data transfers for use in a computer system in which a peripheral device generates a data request to send an interrupt request to a host (12) when a block of data is ready to be transferred, and the host responds to said interrupt request and operates either in a first mode to start a block data transfer after reading status of said peripheral device or in a second mode to read said status after completing said block data transfer, the interface circuit comprising: interrupt means (60) for generating said interrupt request in response to said data request and dropping said interrupt request in response to said status reading; mode detecting means (62) for detecting that said host operates in said second mode; and interrupt enable means (64) responsive to a second mode detect signal from said mode detecting means and said status reading to enable said interrupt means to regenerate said interrupt request. An interface circuit (14) as claimed in claim 1, wherein said data request is dropped at the completion of reading said block of data and regenerated when the next block of data is ready to be transferred. An interface circuit (14) as claimed in claim 2, wherein said interrupt means (60) includes a first flip-flop which is set in response to the generation of said data request and the output of said flip-flop becomes said interrupt request. An interface circuit (14) as claimed in claim 3, wherein said mode detecting means (62) includes a second flip-flop (72) which is set to the same condition as said first flip-flop (70) in response to said data request. An interface circuit (14) as claimed in claim 4, wherein said interrupt enable means (64) includes a third flip-flop (74) which is set to the same condition as said second flip-flop (72) in response to said status reading, a counter (76) which starts counting in response to the setting of said third flip-flop (74), a register (78) into which a predetermined delay value is loaded, and a comparator (80) which compares the contents of said counter and said register and, when they are equal to each other, sets said first flip-flop and resets said second flip-flop and said third flip-flop. An interface circuit as claimed in claim 5, wherein said delay value is set so that said interrupt request can be generated when said host is ready to respond.

Inventors: ASANO HIDEO, MURAKAMI MASAYUKI, ASANO, HIDEO, MURAKAMI, MASAYUKI
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1993
Main classification: G06F13
IPC codes: G06F13, G06F3