Semiconductor device with reduced floating inductance and method of fabricating same

Abstract: A first composite substrate (5) including an insulating substrate, a copper pattern deposited on the upper surface thereof, and a copper layer deposited on the lower surface thereof is mounted on a metal base plate (1). A second composite substrate (9) and semiconductor chips (11, 12) are mounted on the first composite substrate (5), and wire bonding is performed. The paths of currents flowing in aluminum wires (13) and in a copper pattern region (8a) of the second composite substrate (9) are parallel to the paths of currents flowing in respective corresponding portions of the first composite substrate (5), and the former currents flow in the direction reverse to the latter currents. A semiconductor device is achieved wherein an increasing switching frequency being used in power modules does not increase a surge voltage generated in ON and OFF switching operation because of its small inductance so that semiconductor chips are not broken down.

Description: The present invention relates to a semiconductor device and a method of fabricating the Same. More particularly, the invention relates to a semiconductor device having a reduced floating inductance and a method of fabricating the same. Fig. 15 shows a conventional composite substrate 50 with thick copper foil for a power module in top plan view, in cross section and in bottom plan view. The composite substrate 50 includes a ceramic insulating substrate 51, a circuit pattern 52 deposited on one surface of the ceramic insulating substrate 51, and a back pattern 53 deposited on the other surface thereof. In Fig. 16, there is shown, in perspective, a conventional semiconductor device 60 including the composite substrate 50. The semiconductor device 60 comprises a copper base plate 1, the composite substrate 50, a power semiconductor element 12, aluminum wires 13, main electrode terminals 62, a control electrode terminal 63, and a case 61. Fig. 17 shows a main current path 64 of the semiconductor device 60 in practical use. It will be apparent from the comparison between Figs. 16 and 17 that the main current path 64 from one of the main electrode terminals 62 leads to the semiconductor chips 12, and then runs through the wires 13 and part of the circuit pattern 52 to exit at another main electrode terminal 62. Such semiconductor device is used as a power switching device while repeating ON/OFF operation. As MOS power devices have been recently put to practical use, the switching time is very rapid, commonly in the range of 20 to 30 KHz. The switching frequency is expected to increase acceleratedly. As the switching time becomes short, the rate of current change per time di/dt rises in ON-to-OFF and OFF-to-ON operation. This causes a surge voltage V = L·dildt in ON-to-OFF operation due to a floating inductance L present in the main current path 64. Increase in floating inductance L results in increase in surge voltage. When the increasing surge voltage exceeds the rating of the power semiconductor elements 12, the power semiconductor elements 12 break down. EP-A-0 427 143 discloses a semiconductor power device wherein a ceramic substrate is coated with a metallic coating. A first metallic layer is provided on the metallic coating and is divided into an auxiliary emitter area and a positive terminal area (figure 3). A further ceramic isolating layer is arranged on the auxiliary emitter area and carries a gate area. Further, an isolating layer is arranged on the positive terminal area and is covered with a tap connection layer. A plurality of transistor chips is provided on the tap connection area which furthermore carries a negative terminal connection layer on which further isolating and electrically conducting layers are provided. Bonding wires provide the necessary internal connection between the components. EP-A-0 277 546 discloses a semiconductor device including at least one semiconductor chip wherein the terminal connectors are arranged side by side in close proximity and at least partially parallel to each other. The terminal connectors are connected with metallic connectors arranged on an isolating substrate. The connectors include portions extending at right angles to each other, and are connected, via bonding wires, to the respective electrodes of the semiconductor chips provided on metallic layers on the substrate. An object of the present invention is to provide a semiconductor device wherein a surge voltage produced in ON-to-OFF operation is not increased with an increase in switching frequency being used so that a semiconductor element is not broken down. Another object of the invention is to provide a method of fabricating the above-mentioned semiconductor device. These objects are achieved by the features stated in the independent Claims. In the semiconductor device, the input and output currents flow in the first and second conductive layers in antiparallel with each other, so that the respective magnetic fields generated by the input and output currents cancel each other. As a result, a floating inductance decreases, and a high surge voltage is not produced. When the at least one semiconductor chip includes a plurality of semiconductor chips spaced in the first direction, it is preferable that there is provided a slit substantially parallel to the second direction in a portion corresponding to the spacing in the second region. In the semiconductor device the second region of the second conductive layer on which the semiconductor chip is disposed is of peninsular configuration. The input or output current flows in the second direction in which the peninsula extends. The input current, by way of example, flowing in the first region in the first direction maintains its flowing direction up to the boundary between the first region and the second peninsular region. The input current changes its flowing direction to the second direction at the boundary, and then flows into the semiconductor chip in the second direction. The output current from the semiconductor chip reaches the fourth conductive layer from the second peninsular region and flows in the fourth conductive layer in the third direction which is antiparallel to the first direction of the input current. If the second region is not peninsular in configuration, the input current has a component which flows in the first region at a finite angle with respect to the first direction. Since the maximum effect to reduced the floating inductance is achieved when the input and output currents are completely antiparallel to each other, the peninsular shape of the second region enables the inductance reduction effect to be particularly enhanced. The slit is formed in the portion corresponding to the spacing between the semiconductor chips, if in plurality, in the second region. This enhances the effect to cause the output or input current in the second region to flow in the third direction. The semiconductor device according to the present invention is not broken down if the switching frequency being used is increased. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Fig. 1 is a cross-sectional view, with portions broken away, of a semiconductor device of a preferred embodiment according to the present invention: Fig. 2 is a partial plan view of a power module included in the semiconductor device of Fig. 1; Fig. 3 is a cross-sectional view of the power module taken along the line A-A of Fig. 2; Fig. 4 is a partial plan view of a first composite substrate of the power module of Fig. 2; Fig. 5 is a partial plan view of a second composite substrate of the power module of Fig. 2; Fig. 6 is a circuit diagram of the power module of Fig. 2; Fig. 7 shows a current path in the power module of Fig. 2; Fig. 8 shows a current path in the semiconductor device of Fig. 1; Fig. 9 shows a comparable example of the power module of Fig. 2; Fig. 10 is a cross-sectional view showing a fabrication process of the power module of Fig. 2; Fig. 11 is a cross-sectional view showing another fabrication process of the power module of Fig. 2; Fig. 12 is a partial plan view of a power module included in a semiconductor device of another preferred embodiment according to the present invention; Fig. 13 is a cross-sectional view of the power module taken along the line B-B of Fig. 12; Fig. 14 shows a current path in the power module of Fig. 12; Fig. 15 shows a composite substrate with thick copper foil for use in a conventional semiconductor device; Fig. 16 is a perspective view, with portions broken away, of the conventional semiconductor device; and Fig. 17 shows a current path in the semiconductor device of Fig. 16. <Whole Structure> Fig. 1 is a perspective view, with portions broken away for clarity, of a semiconductor device 30 of a preferred embodiment according to the present invention. Fig. 2 is a plan view showing a quarter of a power module 10 included in the semiconductor device 30. A portion shown in Fig. 2 is equivalent to a unit module 10a. The power module 10 of Fig. 1 includes four unit modules 10a to 10d. Referring to Fig. 1, the power module 10 is fixed on a copper base plate 1. Main electrode terminals 32 (32a, 32b) and a control electrode terminal 33 are mounted upright on the upper surface of the power module 10. The power module 10 is located in the bottom of the semiconductor device 30, and is housed in a case 31. The case 31 may be an insert case or an outsert case. The "insert case" means a case to which the electrode terminals 32, 33 have been previously attached, and the "outsert case" means a case to which the electrode terminals 32, 33 are attached as the case 31 is mounted to the copper base plate 1. The case 31 has the shape of an open-bottomed box, the lower end thereof being soldered to the peripheral portion of the metal base plate 1. Resin is introduced into the case 31 through a hole 34 formed on the top of the case 31, and is heated to harden, whereby the power module 10 and the electrode terminals 32, 33 are sealed. <Structure of Power Module 10> Fig. 3 is a cross-sectional view taken along the line A-A of Fig. 2. Referring to Figs. 2 and 3, the power module 10 includes a first composite substrate (laminate) 5 disposed on the upper major surface of the metal base plate 1. The first composite substrate 5 includes a ceramic insulating substrate 3 made principally of Al 2 O 3 or AlN, a copper pattern 4 deposited on the upper major surface of the ceramic insulating substrate 3, and a copper layer 2 deposited almost over the lower major surface of the ceramic insulating substrate 3. Fig. 4 shows only the first composite substrate 5 on the metal base plate 1 in plan view. As shown in Fig. 4, the copper pattern 4 is roughly divided into four regions 4a to 4e. The broken line of Fig. 4 is a phantom line conceptually showing the boundary between the region 4a and the regions 4b to 4d. In practice, the region 4a is continuous with the regions 4b to 4d. The first region 4a is a strip-shaped region extending in a direction X parallel to the upper major surface of the metal base plate 1. The second regions 4b, 4c are of peninsular configuration extending from a side face of the first region 4a in a direction Y substantially perpendicular to the direction X. A slit 70 is formed between the second regions 4b and 4c. The slit 70 extends in the Y direction, and the deepest portion thereof reaches the side face of the first region 4a. The third region 4d extends from an end of the first region 4a in the Y direction. A slit 71 is formed between the third region 4d and the second region 4b. The fourth region 4e is provided in a position isolated from the first to third regions 4a to 4d. Referring again to Figs. 2 and 3, a second composite substrate 9 is provided on the upper major surface of the first region 4a (Fig. 4) of the conductive pattern 4 of the first composite substrate 5. The second composite substrate 9 includes a ceramic insulating substrate 7 made principally of Al 2 O 3 or AlN, a copper pattern 8 deposited almost over the upper major surface of the ceramic insulating substrate 7, and a copper layer 6 deposited almost over the lower major surface of the ceramic insulating substrate 7. The plan size of the second composite substrate 9 is smaller than that of the first composite substrate 5 and is generally equivalent to that of the first region 4a (Fig. 4) of the conductive pattern 4. Fig. 5 is a plan view of the second composite substrate 9. The copper layer 8 is a copper strip extending in the X direction. The copper layer 6 not shown in Fig. 5 on the lower major surface of the ceramic insulating substrate 7 is also a copper strip extending in the X direction. Preferably, the thickness of the copper patterns 4, 8 and the copper layers 2, 6 is selected from the range of 0.1 to 0.5 mm, respectively. The spacing between the copper pattern 4 and the copper layer 2 and the spacing between the copper pattern 8 and the copper layer 6 are preferably selected from the range of 0.5 to 1.5 mm. This is achieved by selecting the thickness of the respective ceramic insulating substrates 3, 6 from the range of 0.5 to 1.5 mm. Referring again to Figs. 2 and 3, a plurality of power semiconductor chips 12 and a plurality of flywheel diode chips 11 are soldered onto the second regions 4b, 4c of the copper pattern. The power semiconductor chips 12 are IGBTs (insulated gate bipolar transistors) each of which has emitter and gate exposed on the upper major surface thereof and a collector exposed on the lower major surface thereof. Each of the flywheel diode chips 11 has a cathode exposed on the upper major surface thereof and an anode exposed on the lower major surface thereof. One power semiconductor chip 12 and two flywheel diode chips 11 make one set, and a plurality of sets of chips 12, 11 are spaced in the X direction. Aluminum wires 13 extending substantially in the Y direction are laid between the copper pattern 8 of the second composite substrate 9 and the upper major surface (cathode) of the flywheel diode chips 11, between the copper pattern 8 and the emitter on the upper major surface of the power semiconductor chips 12, and between the fourth region 4e of the copper pattern 4 and the gate on the upper major surface of the power semiconductor chips 12. The aluminum wires associated with the semiconductor chips 11, 12 illustrated on the upper side of Fig. 2 are not shown in Fig. 2. Fig. 6 is an equivalent circuit diagram of the unit module 10a of the present preferred embodiment having such wiring. Referring to Fig. 2, an area 14a is defined in a (+X)-side end portion of the copper pattern 8. The main electrode terminal 32a of Fig. 1 is connected to the area 14a. An area 14b is defined in the third region 4d of the copper pattern 4. The main electrode terminal 32b of Fig. 1 is connected to the area 14b. The lower structure of the main electrode terminal 32b is not shown in Fig. 1. An area 14c is defined in a (+X)-side portion of the fourth region 4e of the copper pattern 4 of Fig. 2. The control electrode terminal 32a of Fig. 1 is connected electrically to the area 14c. The other unit modules 4b to 4d of Fig. 1 have the same structure as the unit module 4a. <Operation and Characteristics> A positive voltage is applied to the main electrode terminal 32b of Fig. 1, and a negative voltage is applied to the main electrode terminal 32a. A control voltage which is positive to the main electrode terminal 32a is applied to the control electrode terminal 33. Then the power semiconductor chips 12 turn on. A current flow at this time will be described hereinafter. Fig. 7 is a plan view, with portions of the upper structure of Fig. 2 broken away. Fig. 8 shows a current flow of Fig. 1. The arrows 15 and 16 of Figs. 7 and 8 indicate the paths of input and output currents, respectively, when the power semiconductor chips 12 conduct in the forward direction. The input current flowing from the main electrode terminal 32b is directed from the area 14b of Fig. 2 to the third region 4d of the conductive pattern 4, and then reaches the first region 4a. The input current entering the first region 4a flows in the first region 4a in the (-X) direction. Since the copper layer 6 (Fig. 3) on the reverse side of the second composite substrate is soldered to the first region 4a, the input current flows in the copper layer 6 in the (-X) direction. The input current changes its direction to the (+Y) direction as it reaches the boundary between the first region 4a and the second regions 4b, 4c, to flow into the second regions 4b, 4c. The input current flowing in the second regions 4b, 4c in the (+Y) direction flows into the lower major surface or the collector of the power semiconductor chips 12. Such input current path is shown as the path 15. On the other hand, the output current flowing out of the emitter on the upper major surface of the power semiconductor chips 12 is directed through the aluminum wires 13 to the copper pattern 8. Since the aluminum wires 13 extend substantially in the Y direction, the output current is antiparallel to the input current flowing in the second regions 4b, 4c. It is well known in the art of electromagnetism that the floating inductance of go and return parallel conductor is in general low. For this reason, the current path formed by the second regions 4b, 4c and the aluminum wires 13 serves as a small path of floating inductance. The output current changes its direction to the (+X) direction as it reaches the copper pattern 8 through the aluminum wires 13. The output current flows to the area 14a in the (+X) direction, and then flows to the exterior from the area 14a through the main electrode terminal 32a. The direction of the input current flowing in the first region 4a of the copper pattern 4 is antiparallel to that of the output current flowing in the copper pattern 8. That is, the input current flows in the (-X) direction and the output current flows in the (+X) direction in these portions. This provides for a small inductance of the main current path in these portions. In particular, since the copper pattern 8 is disposed just above the first region 4a, great effects to reduce the floating inductance are provided. The aluminum wires 13 and the second peninsular regions 4b, 4c enable the reduction in floating inductance by the antiparallel combination of "lines" (wires 13) and "planes" (regions 4b, 4c). The first region 4a of the copper pattern 4 and the copper pattern 8 enable the reduction in floating inductance by the antiparallel combination of a "plane" (copper pattern 8) and a "plane" (region 4a). The use of both combinations affords remarkable effects to reduce the floating inductance in the semiconductor device 30 of the present invention. The semiconductor device 30 that has a low floating inductance of the main current path for the above-mentioned reasons has a small surge voltage V=L·di/dt if the rate of current change di/dt rises in ON-to-OFF and OFF-to-ON operations due to increasing switching frequency being used. Thus the power semiconductor chips 12 are effectively prevented from being broken down. <Slits 70, 71> The reason for provision of the slits 70, 71 in the structure of Figs. 2 and 7 will be discussed hereinafter. The slit 70 is located between two pairs of semiconductor chips, and the slit 71 is located between the second region 4b and the third region 4d of the copper pattern 4. For explanation of the functions of the slits 70, 71, it is assumed that the slits 70, 71 are absent. Fig. 9 shows a structure wherein the slits 70, 71 are absent. In Fig. 9, a copper pattern 4m is of rectangular configuration, and the area 14b to be connected to the main electrode terminal 32b of Fig. 1 is defined in an end portion of the copper pattern 4m. Regions 12a represent positions in which the semiconductor chips 12 and the like are to be mounted. In the case of Fig. 9, the current path 15 of the input current does not run just under the copper pattern 8 of the second composite substrate 9. In addition, the current path 15 runs in oblique directions. Thus the input and output currents are not completely antiparallel to each other, and the distance between the input and output currents is long, resulting in less effective reduction in floating inductance. The semiconductor device of the present preferred embodiment of Fig. 2 having the slits 70, 71, however, is capable of forcing the input current path 15 to run in the (-X) direction (Fig. 7) and then to change its direction to the (+Y) direction so as to provide an L-shaped path. Furthermore, the input current path 15 runs adjacent the output current path 16, providing great effects to cancel the magnetic fields mutually. <Fabrication Method> The semiconductor device 30 is fabricated, for example, in a manner to be described hereinafter. First prepared is the first composite substrate 5 including the insulating substrate 3, the copper pattern 4 deposited on the upper major surface of the insulating substrate 3, and the copper layer 2 deposited on the lower major surface of the insulating substrate 3. Also prepared is the second composite substrate 9 including the insulating substrate 7, the copper pattern 8 deposited on the upper major surface of the insulating substrate 7, and the copper layer 6 deposited on the lower major surface of the insulating substrate 7. The size of the second composite substrate 9 is determined in accordance with the size of the first region 4a of the copper pattern 4 of the first composite substrate 5. The first composite substrate 5 is joined to the upper major surface of the metal base plate 1 such that the copper layer 2 is positioned in face-to-face relation to the upper major surface of the metal base plate 1. The second composite substrate 9 is joined onto the first region 4a of the copper pattern 4 of the first composite substrate 5. The junction may be made by means of direct-connect process or activated metal process. Specifically, the junction is achieved by high-temperature brazing using hard solder or by using, as junction layers, copper oxide provided by heating the copper layers 2, 4, 6, 8 in an atmosphere of oxygen. Fig. 10 shows the power module after the junction. The metal base plate 1, the first laminate 5, and the second laminate 9 are joined together with junction layers 18, 17. The flywheel diode chips 11 and the power semiconductor chips 12 are soldered onto the second regions 4b, 4c of the copper pattern 4. The wires 13 are laid between the semiconductor chips 11, 12 and the copper patterns 8, 4e to bond the ends of the wires 13 to the semiconductor chips 11, 12 and the copper patterns 8, 4e. The power module provided in the foregoing manner is housed in the case 31 (Fig. 1). Almost simultaneously, the electrode terminals 32, 33 (Fig. 1) are joined to the corresponding areas 14a to 14d (Fig. 2). Resin is introduced into the case 31 through the hole 34 formed in the upper surface of the case 31, and is then heated to harden. The semiconductor chips 11, 12, the wires 13 and their vicinities may be protected with silicon gel or the like. <Other Preferred Embodiments> (1) A laminate including two insulating substrates may be deposited on the metal base plate 1 in place of the two composite substrates 5, 9 of the foregoing preferred embodiment. The present invention may be accomplished, for example, by joining a laminate 19 including three copper patterns 2, 4, 8 and two insulating substrates 3, 7 to the metal base plate 1 with solder 18, as shown in Fig. 11. In this case, it is preferable that the thickness of the respective metal patterns 2, 4, 8 is selected from the range of 0.1 to 0.5 mm. The spacing between the copper patterns 4, 8 is preferably selected from the range of 0.5 to 1.5 mm. (2) Although the input current path is on the lower side and the output current path is on the upper side in the power module 10 of the above-mentioned preferred embodiment, the input current path may be on the upper side whereas the output current path is on the lower side. Fig. 12 is a plan view of a power module 40 in such case, and Fig. 13 is a cross-sectional view taken along the line B-B of Fig. 12. Fig. 14 shows current paths in the power module 40, with portions of the upper structure of Fig. 12 broken away. The copper pattern 4 formed on the upper major surface of the first composite substrate 5 includes, as shown in Fig. 14, the first region 4a extending in the X direction, the second peninsular regions 4b, 4c extending from the first region 4a in the (+Y) direction, and the third region 4d in which the area 14c (Fig. 12) for connection of the terminal is defined. Slits 72 are formed between the regions 4b, 4c, 4d. The second composite substrate 9 having a plan size smaller than the first composite substrate 5 is joined onto the first composite substrate 5. The copper pattern 6 formed on the lower major surface of the second composite substrate 9 is adapted to fit the copper pattern 4. The copper pattern 8 is formed on the upper major surface of the second composite substrate 9. The copper pattern 8 includes a region 8a (Fig. 14) extending in the X direction, regions 8b, 8c of peninsular configuration extending from the region 8a in the Y direction, a region 8d extending parallel to the region 8b, and a region 8e isolated from the regions 8a to 8d. Slits 73 are formed between the regions 8b, 8c, 8d. The semiconductor chips 11, 12 (Fig. 12) are joined onto the regions 8b, 8c. The wires 13 extending in the Y direction connect the semiconductor chips 11, 12 to the copper patterns 8e, 4b, 4c. The other structures of the power module 40 are identical with those of the power module 10 of Fig. 2. In the power module 40 of Figs. 12 to 14, an input current 41 from the area 14b (Fig. 12) flows in the region 8d (Fig. 14) in the (-Y) direction, and then flows in the region 8a in the (-X) direction. The input current changes its direction to the (+Y) direction at the boundary between the region 8a and the regions 8b, 8d, and then reaches the lower major surface of the power semiconductor chips 12 through the regions 8b, 8c. The output current from the upper major surface of the power semiconductor chips 12 flows through the wires 13 to the copper pattern regions 4b, 4c of the first composite substrate 5. The output current further flows in the copper pattern regions 4b, 4c in the (-Y) direction as illustrated as a path 42 in dotted lines. The output current changes its direction to the (+X) direction, and flows in the copper pattern region 4a of the first composite substrate 5 just under the copper pattern region 8a of the second composite substrate 9 in the (+X) direction. The output current changes its direction to the (+Y) direction as it reaches the copper pattern region 4d to flow out from the area 14c (Fig. 12) to the main electrode terminal. In the power module 40, the input and output current paths 41 and 42 are antiparallel to each other. This provides for a small floating inductance and effective prevention of the breakdown due to the surge voltage in high-speed switching operation. The slits 72, 73 are provided for the same reason as in the power module 10 of Fig. 2. (3) Although the above-mentioned preferred embodiments employ the power module including two insulating substrates, more insulating substrates and copper patterns may be used. In such case, the input and output current paths may be adapted to be antiparallel to each other. The copper patterns may be replaced with other conductive patterns such as aluminum patterns. While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention as defined by the appended claims.

Claims: A semiconductor device for controlling an input current by a semiconductor chip to provide an output current, comprising: (a) a metal base plate (1) having a major surface; (b) a first insulating substrate (3) disposed on said major surface of said metal base plate; (c) a first conductive layer (4) provided on said first insulating substrate and having (c-1) a first region (4a) for conducting one of said input and output currents in a first direction (X) parallel to said major surface, and (c-2) a second peninsular region (4b, 4c) continuous with said first region and protruding therefrom in a second direction (Y) different from said first direction (X) on said major surface; (d) a second insulating substrate (7) provided on said first conductive layer (4) except at least an end portion of said second region (4b, 4c); (e) a second conductive layer (8) provided on said second insulating substrate (7) and having a third region (8a) for conducting the other current in a third direction antiparallel to said first direction, said third region (8a) overlaying said first region (4a) of said first conductive layer (4); and (f) at least one semiconductor chip (12) provided on said second region (4b, 4c) or said second conductive layer (8) and connected electrically to said second region (4b, 4c) and said second conductive layer. The semiconductor device of claim 1, wherein (f-1) a plurality of semiconductor chips (12) are provided on said second region (4b, 4c) and spaced in said first direction, and there is provided a slit (70) substantially parallel to said second direction in a portion corresponding to said spacing in said second region. The semiconductor chip of claim 2, further comprising: (g) a first electrode (32b) connected electrically to an end of said first region (4a); and (h) a second electrode (32a) connected electrically to an end of said second conductive layer located on the same side as said end of said first region. The semiconductor device of anyone of the preceding claims, further comprising: (i) a third conductive layer (2) provided between said metal base plate (1) and said first insulating substrate (3). The semiconductor device of anyone of the preceding claims, wherein the respective thickness of said first and second conductive layers (4, 8) is selected from the range of 0.1 to 0.5 mm. The semiconductor device of any of claims 1 to 4, wherein a spacing between said first and second conductive layers (4, 8) is selected from the range of 0.5 to 1.5 mm. The semiconductor device of anyone of the preceding claims, wherein said first and second conductive layers (4, 8) are formed substantially of copper. The semiconductor device of anyone of the preceding claims, further comprising: (g) at least one wire (13) electrically connecting each upper surface of said at least one semiconductor chip (12) and one of said second region (4b, 4c) and said second conductive layer (8) to conduct one of said input and output currents, and extending substantially in said second direction. The semiconductor device of claim 8, wherein said at least one first semiconductor chip (12) includes: (f-1) at least one first chip (12) provided on said second region (4b, 4c); and (f-2) at least one second chip (12) provided on said second conductive layer (8); and each one of said at least one wire (13) includes: (g-1) a first end connected electrically to one of upper surfaces of said at least one first chip (12); and (g-2) a second end connected electrically to one upper surfaces of said at least one second chip (12). The semiconductor device of anyone of the preceding claims, wherein said second conductive layer (8) further includes: (e-1) a fourth peninsular region (8b, 8c) continuous with said third region (8a) and protruding in said second direction (Y) to overlay said second region (4b, 4c) except said end portion thereof, said at least one semiconductor chip (12) includes: (f-1) a plurality of semiconductor chips provided on said fourth peninsular region and spaced in said third direction, and there is provided a slit (73) substantially parallel to said third direction in a portion corresponding to said spacing in said fourth peninsular region. A method of fabricating a semiconductor device for controlling an input current by a semiconductor chip to provide an output current, said method comprising the steps of: (a) providing a laminate (19) including a first insulating substrate (3), a first conductive layer (4), a second insulating substrate (7) and a second conductive layer (8) joined together in this order, said first and second conductive layers (4, 8) being at least partially exposed, respectively; (b) fixing said laminate (19) on a major surface of a metal base plate (1); and (c) fixing a semiconductor chip (12) on an upper surface of said exposed first or second conductive layer (4, 8) of said laminate, said first conductive layer (4) including a first region (4a) for conducting one of said input and output currents in a first direction (X) parallel to said major surface, and a second peninsular region (4b, 4c) continuous with said first region and protruding in a second direction (Y) different from said first direction on said major surface, said second insulating substrate (7) being provided on said first conductive layer (4) except at least an end portion of said second region (4b, 4c), said second conductive layer (8) being provided on said second insulating substrate (7) and having a portion for conducting the other current in a third direction antiparallel to said first direction (X), said portion overlaying said first region (4a) of said first conductive layer (4). The method of claim 11, wherein said step (a) includes the steps of: (a-1) providing said first insulating substrate (3); (a-2) selectively providing said first conductive layer (4) on said first insulating substrate (3); (a-3) selectively providing said second insulating substrate (7) on said first conductive layer (4); and (a-4) providing said second conductive layer (8) on said second insulating substrate, and said step (a-4) includes the steps of: (a-4-1) providing a conductive strip smaller in plan size than said first conductive layer (4); and (a-4-2) fixing said conductive strip on said second insulating substrate (7), with the length of said conductive strip directed in said second direction (Y), to provide said second conductive layer (8). The method of claim 12, further comprising the steps of: (d) providing a first electrode (32b) to electrically connect an end of said first conductive layer (4) to said first electrode; and (e) providing a second electrode (32a) to electrically connect an end of said second conductive layer (8) located on the same side as said end of said first conductive layer to said second electrode. The method of claim 13, wherein said step (a-2) includes the step of: (a-2-1) providing a metal layer having a thickness selected from the range of 0.1 to 0.5 mm to provide said first conductive layer (4), and said step (a-4-1) includes the step of: (a-4-1-1) providing a metal layer having a thickness selected from the range of 0.1 to 0.5 mm to provide said conductive strip. The method of claim 12, 13 or 14, wherein said step (a-3) includes the step of: (a-3-1) fixing said second insulating layer (7) on said first conductive layer (4) such that a spacing between said first and second conductive layers (4, 8) is a value selected from the range of 0.5 to 1,5 mm. A method of fabricating a semiconductor device for controlling an input current by a semiconductor chip to provide an output current, said method comprising the steps of: (a) providing a first laminate (5) including a first insulating substrate (3) and first and second conductive layers (2, 4) deposited on first and second major surfaces of said first insulating substrate (3), respectively, and a second laminate (9) including a second insulating substrate (7) and third and fourth conductive layers (6, 8) deposited on first and second major surfaces of said second insulating substrate (7), respectively; (b) fixing said first laminate (5) on a major surface of a metal base plate (1) such that said first conductive layer (2) is positioned in face-to-face relation to said major surface of said metal base plate; (c) fixing said second laminate (9) on said first laminate (5) such that said third conductive layer (6) is positioned in face-to-face relation to said second conductive layer (4) and such that a portion of a major surface of said second conductive layer (4) is exposed; and (d) fixing said semiconductor chip (12) on said portion of said major surface of said second conductive layer (4) or on said fourth conductive layer (8), said second conductive layer (4) including a first region (4a) for conducting one of said input and output currents in a first direction (X) parallel to said major surface of said metal base plate (1), and a second peninsular region (4b, 4c) continuous with said first region (4a) and protruding in a second direction different from said first direction on said major surface of said metal base plate (1), said second insulating substrate (7) being provided on said second conductive layer (4) except at least an end portion of said second region (4b, 4c), said fourth conductive layer (8) having a portion for conducting the other current in a third direction antiparallel to said first direction, said portion overlaying said first region (4a) of said second conductive layer (4). The method of claim 16, wherein said step (a) includes the step of: (a-1) providing said second laminate (9) so that said second laminate is smaller in plan size than said second conductive layer (4) and is of elongated configuration, and said step (b) includes the step of: (b-1) fixing said second laminate (9) on said first laminate (5), with the length of said second laminate directed in said second direction (Y). The method of claim 17, further comprising the steps of: (d) electrically connecting a first electrode (32b) to a first end of said second conductive layer (4); and (e) electrically connecting a second electrode (32a) to a second end of said fourth conductive layer (8) located on the same side as said first end of said second conductive layer. The method of claim 18, wherein said step (a-1) includes the steps of: (a-1-1) fixing first and second metal layers each having a thickness selected from the range of 0.1 to 0.5 mm on said first and second major surfaces of said first insulating substrate (3) to provide said first and second conductive layers (2, 4) of said first laminate (5); and (a-1-2) fixing third and fourth metal layers each having a thickness selected from the range of 0.1 to 0.5 mm on said first and second major surfaces of said second insulating substrate (7) to provide said third and fourth conductive layers (6, 8) of said second laminate. The method of claim 19, wherein said step (a-1) further includes the steps of: (a-1-3) producing said first laminate (5) such that a spacing between said first and second conductive layers (2, 4) is a value selected from the range of 0.5 to 1.5 mm; and (a-1-4) producing said second laminate (9) such that a spacing between said third and fourth conductive layers (6, 8) is a value selected from the range of 0.5 to 1.5 mm.

Inventors: ARAI KIYOSHI, TAKAGI YOSHIO, ARAI, KIYOSHI,, TAKAGI, YOSHIO, Arai, Kiyoshi, c/o Mitsubhishi Denki K.K., Fukuoka, Takagi, Yoshio, c/o Mitsubhishi Denki KK, Fukuoka
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: H01L23
IPC codes: H01L23, H01L25