Apparatus for multiplying integers of many figures

Abstract: A multiplier apparatus designed to multiply integers of many figures with a small circuit scale in such a manner that an input value is partitioned and multiplication is performed by taking account of carries. With respect to partitioned input values, partial multiplications are repeatedly performed in parallel with each other, and results of the partial multiplications are added by a plurality of adders. A carry occurring at each adder is added in the same adder or in an upper adder in the next cycle of addition. A circuit for this operation may be formed as a systolic array of identical processing elements to perform the operation in a pipe line processing manner.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a multiplier apparatus for multiplying integers and, more particularly, to a multiplier apparatus which is suitable for a cryptographic scheme using a cryptographic system such as the RSA cryptosystem, and which multiplies integers of many figures by utilizing multiplication of a small number of figures. Description of the Related Art Recently, with the rapid development of information communication systems using computer networks, the importance of cryptographic schemes for data protection has increased. There are two kinds of cryptosystems: public-key cryptosystems and common-key cryptosystems. Unlike common-key cryptosystems, public-key cryptosystems are advantageous in that key management is easy and digital signature is possible. In the RSA cryptosystem, which is typical of public-key cryptosystems, a cryptogram is calculated by a modular exponentiation: C = M e mod N (C, M, N, e: integers). The modular exponentiation is realized by repeating a modular multiplication: D = A·B mod N (A, B, D: integers). To ensure security against cryptanalysis, 512 bits or more are required for the values N and e. In such a case, the computational complexity is very high. To directly execute the above-described calculation, a multiplier and a divider having many places are required. In gate array design or board design, a multiplier for multiplying integers of a small number of figures can be easily arranged because suitable cell libraries, transistor-transistor logic (TTL) devices and the like are available. However, there have been provided no ROMs and no cell libraries for realizing a multiplier and a divider of many places. It has been difficult to design a multiplier or a divider of many places in accordance with one's need, because the circuit configuration is very complicated if the configuration of a multiplier or a divider of a small number of places is simply extended. Then, a multiplication may be performed by partitioning an input value with respect to a predetermined number of bits. In a calculation system such as a Galois field using no carry, a multiplication can be executed by a circuit such as that shown in Fig. 2. The circuit shown in Fig. 2 has (m × m)-bit multipliers ×Bi on a Galois field having m-bit values Bi(i = 1, ..., n-1) as multiplier factors, m-bit EXOR devices EX, and m-bit registers r. In the case of an ordinary multiplication of integers performed by separate operations of such a circuit, however, a carry occurs when each separate operation is performed. It is therefore difficult to form an efficient multiplication apparatus by using this circuit. SUMMARY OF THE INVENTION In view of the above-described problems, an object of the present invention is to provide a multiplier apparatus capable of efficiently multiplying integers of many figures with a small-scale circuit. Another object of the present invention is to provide a multiplier apparatus for multiplying integers of many figures by utilizing multiplication of integers of a small number of figures. Still another object of the present invention is to provide a multiplier apparatus for efficiently performing a multiplication by taking account of carries in a case where integers of many figures are multiplied by partitioning an input value. A further object of the present invention is to provide a multiplier apparatus for multiplying integers of many figures which is formed of a plurality of identical processing elements, and which can be suitably formed as an integrated circuit. The present invention is defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1, 3, 4, 7 to 10, and 12 are diagrams of examples of multiplier circuits in accordance with embodiments of the present invention; Fig. 2 is a diagram of an example of a conventional multiplier circuit on a Galois field; Fig. 6, 11, 14, 15, 17, and 18 are examples of circuit arrangements of processing elements (PE) for effecting multiplication; and Figs. 5, 13, 16, and 19 are diagrams of examples of multiplier circuits using the PEs. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. [Embodiment 1] Let m, A, and B be a small integer, an integer of n bits, and an integer of h·m bits, respectively. For ease of explanation, h = n is assumed in the following. The generality is not lost by this limitation. Practice of an operation: A·B = C will be discussed. As is well known, a multiplier for executing multiplication of an integer a of one bit and an integer b of m bits, i.e., a·b = c , can be realized by using AND circuits or the like. Integers A and B can be expressed as shown below by being partitioned with respect 1 bit and m bits, respectively. A = A n-1 ·2 n-1 + A n-2 ·2 n-2 + ... + A 1 ·2 + A 0 B = B n-1 ·X n-1 + B n-2 ·X n-2 + ... + B 1 ·X + B 0 X = 2 m-1 Partitioned n terms in the equation of A form a bit series A n-1 , A n-2 , ..., A 0 from an upper place to a lower place. B is also expressed in the same manner. In this case, A and B are regarded as polynominals and A·B can therefore be expressed as shown below. A·B = A n-1 ·B·2 n-1 + A n-2 ·B·2 n-2 + ... + A 1 ·B·2 + A 0 ·B A case where n = 4 will be discussed. The generality is not lost by this limitation. A·B = A 3 ·(B 3 ·X 3 + B 2 ·X 2 + B 1 ·X + B 0 )·2 3 + A 2 ·(B 3 ·X 3 + B 2 ·X 2 + B 1 ·X + B 0 )·2 2 + A 1 ·(B 3 ·X 3 + B 2 ·X 2 + B 1 ·X + B 0 )·2 + A 0 ·(B 3 ·X 3 + B 2 ·X 2 + B 1 ·X + B 0 ) To execute this operation, a multiplier circuit such as that shown in Fig. 1 is formed. The arrangement of the multiplier circuit shown in Fig. 1 corresponds to a case where A i (i = n - 1, ..., 0) represents 1-bit units while B i represents m-bit units. The circuit shown in Fig. 1 is formed of four (1 × m)-bit multipliers (×B 0 to ×B 3 ), four m-bit full adders with a 2-bit carry (+ 1 to + 4 ), and four (m + 2)-bit registers (R 0 to R 3 ). In the initial state, the content of each register in the circuit shown in Fig. 1 is "0". Also, the values of B i are set in the multipliers (×B i ) prior to inputting Ai. When A 3 is input by a first clock pulse, the coefficient A 3 ·B i (i = 3, ..., 0) of each sub-term in the term (1) is output from the corresponding multiplier and is stored in the corresponding register through the full adder. When A 2 is input by the next clock pulse, the coefficient A 2 ·B i (i = 3, ..., 0) of each sub-term in the term (2) is output from the corresponding multiplier. Since the term (1) is greater than the term (2) one place in binary notation, the values stored in the registers are shifted up one bit, and the shifted values and the outputs from the multipliers representing the coefficients of the terms (2) are added to each other. Accordingly, lower m - 1 bits in each register are shifted up one bit and feedback-input to the adder, and the mth bit in each register is input to the least significant bit of the adjacent adder on the right side. In each adder, therefore, two groups of m bits are added to each other. If there is a carry, m + 1 bits are output and stored in the register again. The same operation as that performed when A 2 is input is also performed when A 1 is input by the next clock pulse. At this time, however, a carry bit as the (m + 1)th bit in each register is input as a carry to the second place in the adjacent adder on the right side. That is, the (m + 1)th bit in each register has the same place as the least significant bit in the adjacent register on the right side and, therefore, needs to be treated as a second-place carry bit instead of a lowermost-place carry bit in the adder. Accordingly, m + 2 bits are output from each adder and stored in the register again. Thus, the coefficients of the sub-terms in the terms (1) to (3) are added. When A 0 is finally input by the next clock pulse, the coefficients of the sub-terms in the terms (1) to (4) are added by the same operation, thus performing the multiplication A·B. Subsequently, inputting clock pulses may be continued to output the multiplication result A·B successively from the upper place, from the upper bit of the uppermost-place register, or the content of each register may be read out to form the final multiplication result A·B. In this manner, the operation A·B is performed efficiently as partitioned values of A are input. It is apparent that the full adders having carries in the arrangement shown in Fig. 1 can be realized by a combination of a plurality of two-input full adders and half adders. It is also apparent that a multiplier circuit for achieving the same effect can also be formed by removing the right-end register or by further annexing a full adder and a register. The arrangement of the same processing elements each consisting of a multiplier (×B j ), a full adder (+ j ) and a registers (R j ), such as those shown in Fig. 1, is also advantageous in that a large-scale circuit such as a VLSI can be easily realized thereby. It is also apparent that the same operational result can be obtained by using a memory having a plurality of regions R j and by performing operations corresponding to the above-described processing elements successively or parallel to each other on the basis of a software process. [Embodiment 2] With respect to the following embodiments, examples of multiplier circuits in which A is also partitioned with respect to m bits will be described. Let m, A, and B be a small integer, an integer of n bits, and an integer of h·m bits, respectively. For ease of explanation, h = n is assumed in the following. The generality is not lost by this limitation. Practice of an operation: A·B = C will be discussed. A multiplier for executing multiplication of an integer a of one bit and an integer b of m bits, i.e., a·b = c , can be easily realized by using a cell library, a transistor-transistor logic or the like. Integers A and B can be expressed as shown below by being partitioned with respect m bits. A = A n-1 ·X n-1 + A n-2 ·X n-2 + ... + A 1 ·X + A 0 B = B n-1 ·X n-1 + B n-2 ·X n-2 + ... + B 1 ·X + B 0 X = 2 m-1 Partitioned n terms in the equation of A form a bit series A n-1 , A n-2 , ..., A 0 from an upper place to a lower place. B is also expressed in the same manner. In this case, A and B are regarded as polynominals and A·B can therefore be expressed as shown below. To execute this operation, the multiplier circuit may be arranged as shown in Fig. 3. That is, the multiplier circuit is formed of n multipliers (×B 0 to ×B n-1 ) for executing multiplication a·b = c of groups of m bits, n - 1 2m-bit adders with a carry (+ 1 to + n-1 , hereinafter referred to as full adders), n - 1 2m-bit registers (R 0 to R n-2 ), and carry lines each of which connects adders + i and + i+2 by jumping one adder placed therebetween. In the initial state, the content of each register in the circuit shown in Fig. 3 is "0". When A n-1 is input by a first clock pulse, the coefficient C 2n-2 (= A n-1 ·B n-1 ) of X 2n-2 designating the uppermost place is output from the full adder (+ n-1 ), and A n-1 ·B i (i = n - 2, ..., 0) is stored in each register. When A n-2 is input by a first clock pulse, the sum of the output A n-1 ·B n-2 from the right-end register (R n-2 ) and the output A n-2 ·B n-1 from the multiplier ×B n-1 , i.e., C 2n-3 (= A n-1 ·B n-2 + A n-2 ·B n-1 ) is output from the full adder (+ n-1 ) of the circuit shown in Fig. 3. This output corresponds to the coefficient of X 2n-3 designating the next place. Simultaneously, a carry from each full adder to the next but one full adder on the right side is calculated. In the arrangement shown in Fig. 3, a carry from the second nearest full adder on the left side is added to the least significant bit. That is, with respect to A i and B i of m bits, the output (A n-1 ·B n-2 + A n-2 ·B n-1 ) represents a 2m-bit unit corresponding to X 2 , while one clock cycle corresponds to a unit of X. A carry is therefore made by jumping one full adder. In each register, (A n-1 ·B i-1 + A n-2 ·B i ) which is the sum of the output from the subordinate register and the output from the multiplier is stored. It can be understood that the multiplication result through the places to X n-1 is output if the above-described operational steps are repeated by n clock pulses until A 0 is input. Thereafter, the same operational steps are repeated while "0" is input by n clock pulses. The values in the registers are thereby successively output until the multiplication result is entirely output. In this manner, the operation A·B of integers A and B is performed efficiently as partitioned values of A are input. The values n and m are determined by considering a balance between the operational speed of the multiplier circuit and the complexity of the circuit. If m is greater, the number of clock pulses is smaller and the operational speed is higher, but the circuit is complicated. Also, it can be understood that the circuit formed by arranging processor elements (PE) each consisting of a multiplier (×B i ), a full adder (+ i ) and a register (R i ) in accordance with this embodiment can be realized by annexing a full adder (+ 0 ) corresponding to the multiplier (×B 0 ) and a register (R n-1 ) for storing the output from the full adder (+ n-1 ) to the circuit shown in Fig. 3. It has been explained that a multiplier circuit of n·m bits can be realized efficiently by using multipliers of m x m bits in a case where an input value is supplied by being partitioned into n values with respect to m bits. It is apparent that a multiplication can also be executed with the same circuit even when h ≠ n . However, the output from the multiplier circuit in accordance with this embodiment, inclusive of carries, has a (2m + 2)-bit form. It is natural that such carries are added to the forward output, but there is no problem if the multiplication result is processed by being partitioned with respect to several bits in a subsequent circuit, and if the output from the main circuit is used by recognizing this condition. On the contrary, the scale of the subsequent circuit arrangement can be reduced since a many-figure number can be processed part by part. [Embodiment 3] An example of a multiplier circuit in which no carry is made and in which each of full adders is provided with a buffer which feeds a value back to the full adder will be described below. As shown in Fig. 4, the multiplier circuit is formed of n multipliers (×B i ; i = n - 1, ..., 0) for executing m-bit multiplication a·b = c , n - 1 2m-bit adders with a carry (full adders) (+ i ; i = n - 2, ..., 0), n - 1 2m-bit registers (R i ; i = n - 1, ..., 1), and 2n - 1 buffers (BF i ; i = n - 2, ..., 0) for delaying a carry by 2 clock cycles. When A 0 is input by a first clock pulse in the circuit shown in Fig. 4, C 0 (= A 0 ·B 0 ) corresponding to the lowermost place is output, and A 0 ·Bi (i = n, ..., n - 2) is stored in each register. The content of each register in the initial state is "0". When A 1 is input by the next clock pulse, the sum of the output A 0 ·B 1 from the right-end register and the output A 1 ·B 0 from the right-end multiplier, i.e., C 1 (= A 0 ·B 1 + A 1 ·B 0 ) is output. This output corresponds to the coefficient of X designating the next place. A carry of A 0 ·B 1 + A 1 ·B 0 is stored in the 2-bit buffer BF 0 at the right end and used as a carry in an addition after two clock pulses. That is, the carry is calculated with a delay corresponding to two clock cycles because the output from the circuit shown in Fig. 4 becomes higher in place by X per clock pulse while A 0 ·B 1 + A 1 ·B 0 represents a 2m-bit value, i.e., a value corresponding to X 2 . In each register R i and buffer BF i , (A 0 ·B i + A 1 ·B i ) which is the sum of the output from the register R i+1 at the preceding stage and the output from the corresponding multiplier is stored together with its carry. It can be understood that the multiplication result through the places to X n-1 is output if the above-described operational steps are repeated by n clock pulses until A n-1 is input. Thereafter, the same operational steps are repeated while "0" is input by n clock pulses. The values in the registers are thereby successively output until the multiplication result is entirely output. Also, processing elements (PE) each consisting of a multiplier B i , a full adder + i , a buffer BF i and a register R i arranged as shown in Fig. 6 may be used. It is apparent that this embodiment can also be realized by parallel processing using such PEs as shown in Fig. 5. Thus, the operation A·B is performed efficiently as partitioned values of A are successively input. It has been explained that a multiplier circuit of n·m bits can be realized efficiently by using multipliers of m × m bits in a case where an input value is supplied by being partitioned into n values with respect to m bits. It is apparent that a multiplication can also be executed with the same circuit even when h ≠ n . In this system, a circuit portion for making a carry with a full adder forms a closed loop by a feedback using a buffer, and the problem of a delay relating to a carry, encountered in multiplication of integers, can therefore be avoided. It is also apparent that the output from the circuit shown in Fig. 4 or 5, which represents a 2m-bit unit, can be formed as an m-bit output by using such a full adder with a buffer. That is, the arrangement may be such that upper m bits in a series of 2m bits are input to an m-bit register and are then input to an m-bit full adder, lower m bits are directly input to the full adder, and a carry is fed back to the full adder with a 1-bit delay. The arrangement of the same processing elements, such as those shown in Fig. 5 or 6, is also advantageous in that a large-scale circuit such as a VLSI can be easily realized thereby. [Embodiment 4] A multiplier circuit arranged to directly add 2m-bit outputs for the purpose of simplifying the circuit arrangement will be described below. For ease of explanation, a case where n = 4 in the equation (5) will be discussed. The generality is not lost by this limitation. As shown in Fig. 7, the multiplier circuit arranged to execute this operation is formed of four multipliers (×B 0 to ×B 3 ) for executing multiplication a·b = c of m × m bits, four 2m-bit full adders with a carry (+ 1 to + 4 ), and four (2m + 1)-bit registers (R 0 to R 3 ). In the initial state, the content of each register in the circuit shown in Fig. 7 is "0". When A 3 is input by a first clock pulse, the coefficients A 3 ·B i (i = 3, ..., 0) of the sub-terms in the term (6) are output from the multipliers and stored in the registers (R 0 to R 3 ) through the full adders (+ 0 to + 3 ). When A 2 is input by the next clock pulse, the coefficient C 6 (= A 3 ·B 3 ) of X 6 designating the uppermost place of A·B is output from the right-end register R 3 through the full adder + 4 . Simultaneously, in each of the other full adders (+ 0 to + 3 ), the sum of the output A 3 ·B i-1 (i = 3 ... 0) from the adjacent register on the left-hand side and the output A 2 ·B i (i = 3, ..., 0) from the multiplier, i.e., (A 3 ·B i-1 + A 2 ·B i ) (i = 3, ..., 0) is calculated. The output from the full adder is input to the adjacent register on the right side. This means the calculation of the sum of the coefficients of X 5 , X 4 , and X 3 in the terms (6) and (7) of the above equation. B i (i = -1, ..., -n) is assumed to be always "0". The output from each full adder has 2m + 1 bits if there is a carry, since each of A 3 ·B i-1 and A 2 ·B i represents a 2m-bit value. Each register therefore requires 2m + 1 bits. Each bit in each register designates a place, and the most significant bit in one register corresponds to 2 2m = X 2 th place from the least significant bit. However, since each register R i stores operation result with respect to the X places, the most significant bit in each register R i has the same place as the least significant bit in the next but one register R i+2 on the right side. When A 1 is input by the next clock pulse, C 5 (= A 3 ·B 2 + A 2 ·B 3 ) corresponding to the coefficient of X 5 is output from the full adder (+ 4 ) at the right end as viewed in Fig. 7. At this time, the most significant bit in the second-nearest register R 2 on the left side, having the same place as the least significant bit of C 5 , and the most significant bit in the adjacent register R 3 on the left side, having the same place as the place X of C 5 , are also added and output. At this time, in each of the other full adders (+ 1 to + 3 ), the most significant bit in the third-nearest register on the left side, i.e., a carry output from the same, is added as a carry along with the 2m-bit output from the adjacent register on the left side and the 2m-bit output from the multiplier, and a (2m + 1)-bit output is thereby formed. Thus, the coefficients of the sub-terms in the terms (6) to (8) are added. Similarly, when final input A 0 is input by the next clock pulse, C 4 , which is the coefficient of X 4 , is output from the right-end full adder (+ 4 ), and the multipliers output the coefficients A 0 ·B i (i = 3 ... 0) of the sub-terms in the term (9). By receiving these outputs, the full adders successively output coefficients C 3 to C 0 with respect to X 3 to X 0 , thereby entirely outputting the multiplication result. Thus, the operation A·B is performed efficiently as partitioned values of A are successively input. It has been explained that a multiplier circuit of n·m bits can be realized efficiently by using multipliers of m × m bits in a case where an input value is supplied by being partitioned into n values with respect to m bits. It is apparent that a multiplication can also be executed with the same circuit even when h ≠ n . It is also apparent that a multiplier circuit for achieving the same effect can also be formed by removing the full adder and the register at the right end or by further annexing a full adder and a register. The arrangement of the same processing elements as shown in Fig. 7 is also advantageous in that a large-scale circuit such as a VLSI can be easily realized thereby. The same effect can also be achieved by providing a full adder (+ 0 ) between the multiplier (×B 0 ) and the register R 0 in the circuit shown in Fig. 7. The operation in accordance with this embodiment can also be practiced by using a pipe line system designed by considering a group of a multiplier (×B i ), a full adder (+ i ) and a register (R i ) as one processing element (PE). Also, it may be practiced by using a multiplier (×B i ), a full adder (+ i )a and a memory having a plurality of areas and by performing programmed sequential or parallel processing. [Embodiment 5] A multiplier circuit arranged to partition a 2m-bit output into upper m bits and lower m bits for the purpose of reducing the necessary register size so that the circuit scale is smaller will be described below. From the equation (10), A·B = C 7 'X 7 + C 6 'X 6 + C 5 'X 5 + C 4 'X 4 + C 3 'X 3 + C 2 'X 2 + C 1 'X + C 0 ' C i ' = up (C i-1 ) + down (C i ) As shown in Fig. 8, the multiplier circuit arranged for this operation is formed of four multipliers (×B 10 to ×B 13 ) for executing multiplication a·b = c of m × m bits, four 3-input m-bit full adders with a carry (+ 10 to + 13 ), and four (m + 1)-bit registers (R 10 to R 13 ). When A 3 is input by a first clock pulse, the coefficient A 3 ·B i (i = 3, ..., 0) of each of the sub-terms in the term (6) is output from the corresponding multiplier. Since A 3 ·B i output from the multipliers is an 2m-bit output (corresponding to 2 2m = X 2 places), the lower m bits of the right multiplier (B 1i ) and the upper m bits of the left multiplier (B 1i-1 ) have the same places. In each full adder (+ 1i-1 ) shown in Fig. 8, therefore, the upper m bits and the lower m bits of the left and right multipliers are simultaneously added to each other, the addition result is input to the register (R 1i ) and the operation result with respect to X places is stored. The upper m bits and the lower m bits are expressed as up(C i-1 ) and down(C i ), as in the equation (12). Accordingly, the coefficient C 7 ' of X 7 designating the uppermost place of A·B shown in the equation (11) is output through the right-end full adder (+ 13 ). At this time, if there is a carry from the sum of the upper and lower m bits, the (m + 1)th bit in the corresponding register is stored as a carry bit. The (m + 1)th bit representing a carry has the same place as the least significant bit in the adjacent register on the right side. When A 2 is input by the next clock pulse, the upper m bits of A 2 ·B 3 output from the right-end multiplier and the output from the register R 13 on the left side are added in the full adder (+ 13 ) at the right end as viewed in Fig. 8, and the coefficient C 6 ' of X 6 in the equation (11) is output. Simultaneously, in each of the full adders (+ 10 to + 12 ), the sum of the upper/lower m bit outputs from the left and right multipliers and the lower m bit output from the adjacent register on the left side of the full adder is calculated and the output is input to the adjacent register on the right side. Further, the (m + 1)th bit in the second-nearest register on the left side is added as a carry to the full adder. The sums of the coefficients of the sub-terms in the terms (6) and (7) are thus calculated. Since the output from each of the registers and the multipliers has m bits, a two-place carry may occur, and the number of bits of each register for storing the output from the corresponding full adder must be m + 2. When A 1 is input by the next clock pulse, the coefficient C 5 ' of X 5 is output from the right-end full adder (+ 13 ). At this time, to each full adder, the upper two bits in the second-nearest register on the left side having the same place as the lower two bits of the adjacent register on the left side are input as a carry. The full adder executes addition and output m + 2 bits. When final input A 0 is input by the next clock pulse, the coefficient C 4 ' of X 4 is output from the right-end full adder (+ 13 ). In the other full adders, the coefficients C 3 ' to C 0 ' are calculated with respect to X 3 to X 0 . The calculated values are stored in the registers. Thereafter, the same operational steps are repeated while "0" is input by 4 clock pulses. The values C 3 ' to C 0 ' in the registers are thereby output successively from the right-end full adder (+ 13 ) until the multiplication result is entirely output. Thus, the operation A·B is performed efficiently as partitioned values of A are input. [Embodiment 6] A multiplier circuit is formed as shown in Fig. 9. The arrangement shown in Fig. 1 corresponds to a case where each of A i and Bi (i = n - 1, ..., 0) represents 1-bit units. The multiplier circuit shown in Fig. 9 is formed of four (1 × 1)-bit multipliers (×B 20 to ×B 23 ), four 1-bit full adders with a carry (+ 20 to + 23 ), and four 2-bit registers (R 20 to R 23 ). In the initial state, the content of each register in the circuit shown in Fig. 9 is "0". When A 3 is input by a first clock pulse, the coefficient A 3 ·B i (i = 3, ..., 0) of each of the sub-terms in the term (6) is output from the corresponding multiplier and is stored in the register through the full adder. When A 2 is input by the next clock pulse, the coefficient C6 (= A 3 ·B 3 ) of X 6 representing the uppermost place of A·B is output from the right-end register R 23 through the full adder (+ 23 ). Simultaneously, in each of the other full adders (+ 20 to + 22 ), the sum of the output A 3 ·B i-1 (i = 3, ..., 0) from the adjacent register on the left-hand side and the output A 2 ·B i (i = 3, ..., 0) from the multiplier, i.e., (A 3 ·B i-1 + A 2 ·B i ) (i = 3, ..., 0) is calculated. The output from the full adder is input to the adjacent register on the right side. This means the calculation of the sum of the coefficients of the sub-terms in the terms (6) and (7). B i (i = -1, ..., -n) is assumed to be always "0". The output from each full adder has a 2-bit form if there is a carry, since each of A 3 ·B i-1 and A 2 ·B i is 1 bit. Each register therefore requires 2 bits. Each bit in each register designates a place, and the upper bit in each register has the same bit as the lower bit in the adjacent register on the right side. When A 1 is input by the next clock pulse, C 5 (= A 3 ·B 2 + A 2 ·B 3 ) corresponding to the coefficient of X 5 is output from the right-end full adder (+ 4 ) in the circuit shown in Fig. 9. At this time, the most significant bit in the second-nearest register R 22 on the left side, having the same place as the least significant bit of C 5 is also added and output. At this time, in each of the other full adders, the most significant bit in the third-nearest register on the left side, i.e., a carry output from the same, is added as a carry along with the 1-bit output from the adjacent register on the left side and the 1-bit output from the multiplier, and a 2-bit output is thereby formed. Thus, the coefficients of the sub-terms in the terms (6) to (8) are added. When final input A 0 is input by the next clock pulse, C4, which is the coefficient of X 4 , is output from the right-end full adder (+ 23 ), and the multipliers output the coefficients A 0 ·B i (i = 3, ..., 0) of the sub-terms in the term (9). By receiving these outputs, the full adders (+ 23 to + 20 ) successively output coefficients C 3 to C 0 with respect to X 3 to X 0 . The coefficients are stored in the registers. Thereafter, the same operational steps are repeated while "0 is input by 4 clock pulses. The values C 3 to C 0 in the registers are thereby output successively from the right-end full adder (+ 23 ) until the multiplication result is entirely output. Thus, the operation A·B is performed efficiently as partitioned values of A are successively input. It has been explained that a multiplier circuit of n·m bits can be realized efficiently by using multipliers of m × m bits in a case where an input value is supplied by being partitioned into n values with respect to m bits. It is apparent that a multiplication can also be executed with the same circuit even when h ≠ n . It is also apparent that the 3-input m-bit full adder having a carry can be realized by a combination of a plurality of 2-input full adders and half adders. Further, it is apparent that a multiplier circuit for achieving the same effect can also be formed by removing the full adder and the register at the right end or by further annexing a full adder and a register in the circuit shown in Fig. 8 or 9. Since the circuit shown in Fig. 9 is arranged for 1 × 1 multiplication, it is free from reduplication of places from the multiplier outputs and may have a simpler circuit configuration in comparison with the circuit shown in Fig. 8. The arrangement of the same processing elements as shown in Fig. 8 or 9 is also advantageous in that a large-scale circuit such as a VLSI can be easily realized thereby. [Embodiment 7] If the multiplier circuit shown in Fig. 2 is used for an integer operation, carries from lower places cannot be taken into account because the operation is performed from an upper place. Further, at least n clock pulses are required to successively input and calculate Ai (i = n-1, ..., 0) . Therefore, a system for speeding the processing may be arranged in which inputting is effected from a lower place and a plurality of Ai values are input simultaneously. A multiplier circuit for performing a multiplication with n/2 clock pulses will be described below as an example. Such a multiplier circuit may be formed as shown in Fig. 10. The multiplier circuit shown in Fig. 10 is formed of a pair of circuits illustrated in upper and lower sections of Fig. 10. The upper circuit serves to obtain Ck (k = 0, 2, ..., n -2) while the lower circuit serves to obtain C k (k = 1, 3, ..., n - 1). These circuits are formed of 2n multipliers (×B 0 to ×B n-1 ) for executing multiplication a·b = c of m bits with multiplication factors Bj (j = 0, ..., n - 1), n 3-input 2m-bit full adders (BA 0 to BA n-1 ) with a buffer for delaying a carry two clock cycles, and n - 1 2m-bit registers (R 2 to R n-1 ). In the circuit shown in the lower section of Fig. 10, A 0 and A 1 are input through an upper line and a lower line, respectively, by a first clock pulse. Then, C 0 (= A 0 ·B 0 ) corresponding to the lowermost place is output from the right-end buffered adder BA 0 , and A 0 ·B j + A 1 ·B j-1 (j = 2, 4, ..., n - 1) is stored in each register. The content of each register in the initial state is "0". When A 2 and A 3 are input by the next clock pulse, the sum of the output (A 0 ·B 2 + A 1 ·B 1 ) from the right-end register R 2 and the output A 2 ·B 0 from the multiplier (×B 0 ), i.e., C 2 (= A 0 ·B 2 + A 1 ·B 1 + A 2 ·B 0 ) is output from the buffered adder BA 0 . This output value corresponds to the coefficient of X 2 in the equation (5). A carry of (A 0 ·B 2 + A 1 ·B 1 ) is stored in the buffer of the buffered adder BA 0 and is used as a carry in the addition effected by the next clock pulse. In the register and the buffer at each stage, a value which is the sum of the output from the register at the preceding stage and the output from the two multipliers is stored. It can be understood that if the above-described operational steps are repeated by n/2 clock pulses until A n-2 , A n-1 are input, the even-number terms of the equation (5) operation result are calculated. Thereafter, the same operational steps may be repeated while "0" is input so that the operation result is entirely output. The contents of the registers may be collectively shifted into other registers. Accordingly, it is considered that the number of processing clock pulses is substantially n/2. Similarly, in the circuit shown in the upper section of Fig. 10, A 1 and A 0 are input through an upper line and a lower line, respectively, by the first clock pulse. Then, C 1 (= A 0 ·B 1 + A 1 ·B 0 ) which is the coefficient of the Xth place of the equation (5) is output from the buffered adder BA 1 , and A 0 ·B j + A 1 ·B j-1 (j = 3, 5, ..., n - 2) is stored in each register. When A 3 and A 2 are input by the next clock pulse, the sum of the output (A 0 ·B 3 + A 1 ·B 2 ) from the right-end register R 3 and the output from the multiplier (×B 0 , ×B 1 ), i.e., C 3 (= A 0 ·B 3 + A 1 ·B 2 + A 2 ·B 1 + A 3 ·B 0 ) is output from the buffered adder BA 1 . This output value corresponds to the coefficient of X 3 in the equation (5). At this time, a carry is stored in the buffer of the buffered adder BA and is used as a carry in the addition effected by the next clock pulse, as in the case of the lower circuit. It can be understood that the equation (5) operation result is obtained in such a manner that two lower-place values are simultaneously calculated and output at a time. Accordingly, the number of processing clock pulses necessary for the multiplication of the equation (5) is substantially n/2. Thus, the operation A·B is performed efficiently as partitioned values of A are successively input. The circuit shown in Fig. 10 can be formed by arranging the same processing elements each formed as shown in Fig. 11 and is advantageous in that a large-scale circuit such as a VLSI can be easily realized thereby It has been explained that a multiplier circuit of n·m bits can be realized efficiently by using multipliers of m × m bits in a case where an input value is supplied by being partitioned into n values with respect to m bits. It is apparent that a multiplication can also be executed with the same circuit even when h ≠ n . In the illustrated embodiment, a multiplication is executed on the basis of n/2 clock pulses by a pair of circuits. However, it is apparent that a multiplication can be executed on the basis of n/p clock pulses by a set of p circuits in which p signals of A i are simultaneously input to multiplier devices having a series of multiplier factors B j+k (j = 0, p - 1, ...) with k shifted with respect to the input signals. Accordingly, a multiplier circuit whose operating speed can be increased as desired by the selection of p can be formed. Fig. 12 shows an example of a circuit in such a multiplier with respect to P = 4, which outputs C 0 , C 4 , C 8 , ···. If the circuit shown in Fig. 12 can be simplified if each of adders BA is a 5-input full adder. In a case where p = 2 as in this embodiment, a circuit portion for making a carry with each full adder is closed by a feedback using a buffer, and the problem of a delay relating to a carry, encountered in multiplication of integers, can therefore be avoided. It is also apparent that the output from the circuit shown in Fig. 10, which represents a 2m-bit unit, can be formed as an m-bit output by using such a buffered full adder. That is, the arrangement may be such that upper m bits in a series of 2m bits are input to an m-bit register, an output from the register is input to an m-bit full adder, lower m bits are directly input to the full adder, and a carry is fed back to the full adder with a 1-bit delay. This circuit configuration can also be used as a high-speed multiplier circuit in a calculation system such as a Galois field using no carry. In such a case, adders may be EXOR circuits. [Embodiment 8] A multiplier circuit for performing repeated operations as parallel processing on the basis of a pipe line processing will be described below. The multiplier circuit is formed as shown in Fig. 13 and has an overall configuration called a systolic array. In a systolic array, an operation is executed by a pipe line processing using small blocks having the same functions and each called a processing element (PE). As shown in Fig. 14, each PE is formed of a multiplier for executing a multiplication a·b = c of m bits (A j × B j in this embodiment), m-bit registers (R 1 to R 4 ), a 3-input m-bit adder, and a flip flop FF which latches a carry output from the adder and which returns the carry output as a carry input to the adder with a delay corresponding to one clock cycle. A i (i = 0, ..., n - 1) is the above-described partitioned values of integer A and is previously set in each PE as shown in Fig. 13. Referring to Fig. 13, B j is input in the order of B 0 , B 1 ... B n-1 , and a preceding stage input S j to PE 0 is always "0". In the first processing element PE 0 (when A i is A 0 ), 2m-bit outputs A 0 ·B 0 , A 0 ·B 1 ..., A 0 ·B n-1 are output from the multiplier. Lower m bits of each output from the multiplier is directly input to the adder, but upper m bits are input to the adder after being delayed one clock cycle by the register R 1 . This is because, since each output from the multiplier has a 2m-bit form such that the outputs from the multiplier overlap every m bits with respect to the m-bit division designated by X in the term (1), the output is to be sent in the same m-bit form as the input. Since this addition is performed from a lower place to an upper place, an output carry is delayed one clock cycle by the flip flop to be used as a carry at the time of the upper place operation performed in the next clock cycle. The result of the operation S j ← A 0 ·B j is thereby output from the first processing element PE 0 . The same operation is performed in the second processing element PE 1 in the circuit shown in Fig. 13 (when A i = A 1 ). However, operation A 1 ·B j (j = 0, ..., n - 1) is treated as operation A 1 ·B j ·X one place above S j , because B j is input after being delayed one clock cycle by the two registers R 3 and R 4 . Accordingly, the output from the adder is successively output as S j ← A 1 ·B j-1 + S j . It can be understood that the output from the systolic array PE n-1 shown in Fig. 13 becomes C k (k = 0, ..., 2n - 2) representing every m bits from the lower place of A.B as the same processing is thereafter repeated to the final processing element PE n-1 (A i = A n-1 ). The same operation can also be performed in such a manner that, with respect to the internal construction of the PE, the 2m-bit output from the multiplier is directly input to the adder to output 2m-bit S j , as shown in Fig. 15. A block r in Fig. 15 represents a 2m-bit register, and a block BF represents a 2-bit buffer for delaying a carry from the adder two clock cycles. These are required to supply the output from the multiplier not in the m-bit unit form but in a 2m-bit unit form, as mentioned above. It has been explained that a multiplier circuit of n·m bits can be realized efficiently by using multipliers of m × m bits in a case where an input value is supplied by being partitioned into n values with respect to m bits. It is apparent that a multiplication can also be executed with the same circuit even when h ≠ n . Thus, the operation A·B is performed efficiently as partitioned values of integer A are successively input. A systolic array can be formed of a regular arrangement of simple identical PEs and can easily be formed as a large scale circuit such as a VLSI. Also, a multiplier circuit using such a systolic array can be realized very easily, because the PEs can be controlled by the same control system and because data can be supplied in synchronization with each other by the same clock. If the number of figures of A or B is greatly increased, PEs may be annexed to perform the necessary operation. This type of multiplier circuit therefore has high extendability. Also, in this system, a carry is calculated in one PE and no carry is output to other PEs, and the problem a delay relating to a carry, encountered in multiplication of integers, can therefore be avoided. [Embodiment 9] PEs in accordance with the above embodiment may be arranged two-dimensionally for further parallelized operation, and a multiplier circuit such as that shown in Fig. 16 may be formed. The operation of the circuit shown in Fig. 16 is also executed by a pipe line processing. The same values of A i (i = 0, ..., n - 1) are previously set in PE (i, 0) to PE (i, n-1) arranged in a vertical direction. In the arrangement shown in Fig. 16, each PE outputs Bj (j = 0, ..., n - 1) to the PE on the right side with a delay corresponding to one clock cycle, as shown in Fig. 17. Then, S j is received from the PE located diagonally to the upper left, and S j ← A i ·B j +S j is calculated. The calculation result Sj is output to the PE located diagonally to the lower right, and a carry cr output by this calculation is output to the second-nearest PE on the right side. Data input/output at each PE varies depending upon the arrangement of PEs, but the functions of PE are equivalent. The PE shown in Fig. 17 is formed as shown in Fig. 18. That is, the PE is formed of a multiplier for executing a multiplication a·b = c of m bits (A j × B j in this embodiment), m-bit registers (R 1 to R 4 ), two 2m-bit registers R 1 , and R 2 , a 2-input m-bit adder, and a flip flop FF which latches carry or from the adder. Referring back to Fig. 16, values B 0 to B n-1 are simultaneously output to corresponding ones of n PEs at the left end (in the left end column), i.e., PE (0, 0) to PE (0, n-1) . "0" is input, as S j input, to each of the PEs in the left end column and the PEs in the upper end row from diagonally upper left positions. In the n PEs in the left end column, i.e., PE (0, 0) to PE (0, n-1), A 0 ·B 0 , A 0 ·B 1 , ..., A 0 ·B n-1 of 2m bits are calculated by the multipliers. The calculation results are output as S j = A 0 ·B 0 to the PEs located diagonally to the lower right. In synchronization with this output, B j is output to the PEs on the right side. At this time, C 0 (= A 0 ·B 0 ) representing the lowermost place is output from the PE (0, 0) at the lower end of the left end column. In the n PEs in the second column from the left end, i.e., PE (1, 0) to PE (1, n-1), A 0 ·B j + A 1 ·B j-1 is calculated from the output S j from the left end PEs one row above (diagonally to the upper left), and the calculation results are output newly as S j to the third row PEs one row below (diagonally to the lower right), while carry cr output from each adder is latched by the flip flop and is output to the fourth PE in the same row. At this time, C 1 (= A 0 ·B 1 + A 1 ·B 0 ) , i.e., the next-place output is output from the lower end PE (1, 0) in the second column. The multiplication result A i ·B j in each PE is a 2m-bit value in contrast with m-bit A i , B i , and has places corresponding to X 2 . However, since the place shift by the calculation effected in each PE is X, the carry is output as a carry signal the next but one PE. It can be understood that, by repeating the same processing to the n PEs (n-1, 0) to PE (n-1, n-1) in the right end column, multiplication results, i.e., values of A·B in X n-1 places are output from the lower end PEs (0, 0) to (n-1, 0) while multiplication results of A·B and carries above the X n-1 th place are output from the PEs (n-1, 0) to (n-1, n-1) in the right end column. To obtain multiplication results including results of addition of carries, two columns of n PEs (n, 0) to (n, n-1) and n PEs (n+1, 0) to (n+1, n-1) may be annexed or n adders for performing only carry addition operation may be annexed. It has been explained that a multiplier circuit of n·m bits capable of operating at a high speed in a pipe line processing manner can be realized by using multipliers of m bits in a case where an input value is supplied by being partitioned into n values with respect to m bits. It is apparent that a multiplication can also be executed with the same circuit even when h ≠ n . Thus, the operation A·B is performed efficiently as partitioned values of A are successively input. In the circuit of this embodiment a large number of PEs can be realized by regularly arranging simple and identical PEs. Therefore it can be easily formed as a VLSI or the like. Also it can be realized very easily because the PEs can be controlled by the same control system and because data can be supplied in synchronization with each other by the same clock. Even if the number of figures of A or B is greatly increased, PEs may be annexed to perform the necessary operation. This type of multiplier circuit therefore has high extendability. Also, in this system, a carry from each PE is supplied to the next but one E in synchronization with clock, and the problem a delay relating to a carry, encountered in multiplication of integers, can therefore be avoided. The present invention may be applied to any system or apparatus, e.g., a system formed of a plurality of units or an apparatus formed of one unit. Needless to say, the present invention can also be applied to a processing program supplied to a system or an apparatus. The present invention makes it possible to provide an efficient, high-speed and extendible integer multiplier circuit which uses small-place multipliers while considering carries in a case where an operation is performed by partitioning an input value of many figures.

Claims: A multiplier apparatus for multiplying (n x q)-bit first data representing a first integer (A) and (n x m)-bit second data representing a second integer (B), said apparatus comprising: input means for successively inputting the first data q bits at a time; a plurality of multiplication means (xB0, ..., xB3; xB0, ..., xBn-1) each for multiplying input q bits of data with a different one of a group of m bits of the second data; a plurality of addition means (+1, ..., +4; +1 ..., + n-1 ), and a plurality of memory means (R0, ..., R3; R0, ..., Rn-2) each for storing a result of operation by respective one of said plurality of multiplication means or addition means; the apparatus being characterised in that: said plurality of addition means includes a plurality of first addition means (+1, ..., +3; +1, ..., + n-2 ) arranged to add a respective output from at least one of said plurality of multiplication means (xB1, ..., xB3; xB1, ..., xBn-2) and a result without carry bits of a first respective preceding operation stored in a first respective one (R0, ..., R2; R0, ..., Rn-3) of said plurality of memory means and to output the results to a second respective one of said memory means (R1, ..., R3; R1, ..., Rn-2), at least one (+3; + n-3 , + n-2 ) of said plurality of first addition means being arranged further to add carry bits of a second respective preceding operation with the respective output from at least one of said plurality of multiplication means and the result without carry bits of the first respective preceding operation. An apparatus according to claim 1, wherein q is equal to 1, said input means is arranged to input the first data bit by bit starting with the most significant bit and said plurality of addition means includes a second addition means (+4) arranged to add a result with carry bits of a third preceding operation stored in a third one (R3) of said plurality of memory means and carry bits of at least one of fourth preceding operation stored in at least a fourth one (R1, R2) of said plurality of memory means. An apparatus according to claim 2, wherein each of said plurality of memory means (R0, ..., R3) is arranged to store a value of m+2 bits. An apparatus according to claim 1, wherein q is equal to m and said input means is arranged to input the first data m bits at a time starting with the most significant bit. An apparatus according to claim 4, wherein each of said plurality of memory means (R0, ..., Rn-2) is arranged to store a value of 2m bits. An apparatus according to claim 1, wherein q is equal to m and said input means is arranged to input the first data m bits at a time starting with the least significant bit and said apparatus further comprises a plurality of buffer memory means (BF 0 , BF 1 , BF n-2 ) each for storing carry bits output from respective one of said plurality of addition means (+0, +1, +n-2) and for feeding back the carry bits to said respective one of said plurality of addition means at the time of a subsequent addition. An apparatus according to claim 6, comprising n identical processing elements (PE) connected one-dimensionally, each of said processing elements including one of said plurality of multiplication means (Bi) for multiplying each of the groups of m bits of the second data successively received and the corresponding one of the groups of m bits of the first data, one of said plurality of addition means (+i) for adding the product of the multiplication to the result of the operation of the preceding processing element, one of said plurality of buffer memory means (BFi) for storing a carry of the addition and for feeding back the carry to one of said plurality of addition means at the time of a subsequent addition, and one of said plurality of memory means (Ri) for storing the result of the addition and outputting the result to the succeeding processing element, the apparatus being such that in use each of the groups of m bits of the second data is input in succession to said n processing elements (PE), the second data being successively input to the uppermost processing element, each processing element (PE) being arranged to receive successive results of an addition by the processing element at the preceding stage and the groups of m bits of the first data from the preceding processing element, and to successively output a result of an addition by said processing element and the groups of m bits of the successively received second data to the succeeding processing element, the result of the multiplication of the first and the second data being output from the lowermost processing element. An apparatus according to claim 1, wherein q is equal to m and said input means is arranged to input the first data m bits at a time starting with the most significant bit and that said second one (R0, R1, R2, R3) of said plurality of memory means is identical with said first one (R0, R1, R2, R3) of said plurality of memory means. An apparatus according to claim 1, wherein q is equal to m and said input means is arranged to input the first data m bits at a time starting with the most significant bit and that each of said plurality of first addition means (+10, +11, +12) is connected to two of said plurality of multiplication means (B10, B11, B12, B13) and arranged to add, respectively, m bits of an output from a first one (B10, B11, B12) of said plurality of multiplication means including the most significant bit, m bits of an output from a second one (B11, B12, B13) of said plurality of multiplication means including the least significant bit, and less than all the bits of a value stored in said first one (R10, R11, R12) of said plurality of memory means including the least significant bit, and at least one (+11, +12) of said plurality of first addition means further adding less than all the bits of a value stored in said second one (R10, R11) of said plurality of memory means including the most significant bit. A cryptographic system including means for calculating a cryptogram by modular exponentiation using a multiplier apparatus according to at least one of claims 1 to 9 arranged to perform repeated modular multiplication. A computer program product programmed with machine readable instructions for causing a processing system to operate as a multiplier apparatus according to at least one of claims 1 to 9.

Inventors: IWAMURA KEIICHI, IWAMURA, KEIICHI, IWAMURA, KEIICHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: G06F7
IPC codes: G06F7