Mounting for a high frequency integrated circuit

Abstract: An integrated circuit packaging system with an integrated circuit die (300) mounted onto a substrate (302) having a top side ground plane (308) between the integrated circuit and the substrate, a bottom side ground plane (306) and short high frequency connections (304) between the two ground planes. The top side ground plane decreases signal degradation due to reflections by providing high frequency ground access close to the die and by providing a transmission line for bond wires. A grid of conductive vias through the substrate improves thermal conductivity and provides the short high frequency current path for the top side ground plane. The die is separated from the top side ground plane by a dielectric layer (310) which also has a conductive layer (312) next the die to provide a back bias voltage.

Description: FIELD OF INVENTION This invention relates to microelectronics packaging and more particularly to mechanical, thermal and electrical attachment of a high frequency integrated circuit die to a ceramic substrate. BACKGROUND OF THE INVENTION Integrated circuit dice are typically attached to a substrate that provides heat transfer and electrical connections. For high frequency circuits, heat transfer becomes especially important. In addition, for high frequency circuits, signal degradation die to reflections may limit the useful frequency range. Therefore, transmission line geometry becomes especially important. A common method of electrically connecting the die to the substrate is wire bonding (or tape-automated bonding). Wire bonding consists of attaching wires to bonding pads on the die and to traces on the substrate. Flexible wire bonds provide strain relief to allow for differences in thermal expansion between the die and the substrate. High frequency signals on an integrated circuit die and on the substrate are typically routed by microstrips or other transmission lines. Bonding wires between a substrate and a die form a discontinuity in the transmission line. This discontinuity causes signal degradation due to reflections. For high frequency circuits, the substrate is typically a material with good tliermal conductivity such as aluminum oxide or other ceramic material. The die is typically back bonded to the ceramic for thermal conduction through the back of the die. The present invention improves substrate thermal conductivity and reduces signal degradation relative to prior art die mounting methods. SUMMARY OF THE INVENTION According to the invention, there is provided an integrated circuit structure as specified in claim 1. The insulation means may comprise a layer of ceramic or glass ceramic. A preferred embodiment improves heat conductivity by providing a grid of metal coated or metal filled vias through a ceramic substrate to a heat conductive backplane. The vias are isolated from the integrated circuit die by a dielectric layer. A metallic layer on the die side of the dielectric provides a back bias conductor for the integrated circuit die. A metallic layer on the substrate side of the dielectric, electrically connected to the grid of vias, minimizes signal degradation from transmission line discontinuities due to bonding wires by providing an additional span of microstrip and by minimizing the distance between die pads and electrical ground. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 (prior art) illustrates a mechanical top view of a portion of an integrated circuit wire bonded to a substrate. Figure 2 (prior art) is a mechanical cross section of the integrated circuit assembly of figure 1. Figure 3 is a mechanical top view of an exemplary circuit mounting and interconnection system in accordance with the present invention. Figure 4 is a mechanical cross section of the integrated circuit mounting and interconnection system illustrated in figure 3. Figures 1 and 2 illustrate a typical prior art system. Figure 1 illustrates a top view of a corner of an integrated circuit wire bonded to traces on a substrate. Figure 2 illustrates a cross section through the assembly illustrated in figure 1. In figures 1 and 2, an integrated circuit 100 is wire bonded to traces (102 and 104) on a substrate 106. Trace 102 represents the top portion of a signal microstrip. A ground plane 112 on the bottom side of the substrate 106 forms the other conductor in the microstrip. Trace 104 represents a ground connection to the integrated circuit 100. A plated via 110 connects the ground trace 104 to the ground plane 112 on the bottom of the substrate. In general, traces leading to the integrated circuit 100 are so crowded that via 110 cannot be placed close to the integrated circuit 100. For high frequency signals (for example signals in the GigaHertz range), trace 102 and the ground plane 112 comprise an effective transmission line. However, at the wire bond 108, there is a discontinuity in the microstrip geometry. At that point, there is no longer a transmission line. Instead of confined electric field lines between the trace 102 and the ground plane 112 below, there is a longer circuit through the integrated circuit requiring current flow through the plated via 110. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION Figure 3 illustrates a mechanical top view of the present invention. Figure 4 illustrates a cross section through the system illustrated in figure 3. In figures 3 and 4, an integrated circuit 300 is mounted to a substrate 302. The substrate 302 has a grid of vias 304 connecting a conductive lower ground plane 306 to a conductive upper ground plane 308. The integrated circuit 300 is electrically isolated from the upper ground plane 308 by a dielectric layer 310. The dielectric layer 310 has a conductive layer 312 which electrically contacts the back of integrated circuit 300. The conductive layer 312 has a bonding wire 314 to a back bias voltage 316 (V EE ). The integrated circuit 300 has a bonding wire 324 to the upper ground plane 308. The integrated circuit 300 has a bonding wire 318 to a signal trace 322. The integrated circuit 300 is attached to conductive layer 312 by a suitable high temperature adhesive. Likewise, dielectric layer 310 may be attached to the upper ground plane 308 with an adhesive. In the preferred embodiment of the present invention, the substrate 302 is aluminum oxide. The vias 304 are preferably metal filled to maximize the thermal conductivity but alternatively may be just metal plated. If the vias 304 are solid filled then the dielectric 310 is preferably a screen printed glass ceramic. A suitable material is a .002 inch (1inch=2.54cm) layer of insulating glass such as DuPont 5704M. If the vias 304 are merely plated, the ends of the vias are open and a screen printed dielectric cannot cover the open ends. Therefore, for plated vias, a mechanically rigid dielectric is needed. For plated vias, a tliin sheet of thermally conductive substrate such as aluminum nitride or beryllium oxide is preferable. The rigid substrate must be thin for thermal transmission but thick enough to conveniently process. Aluminum nitride with a thickness in the range of .010-.025 inches is suitable. In the preferred embodiment, the upper and lower ground planes (306 and 308) are Palladium-Silver. The vias 304 are plated with gold. The vias 304 are tlien filled with gold that contains a small amount of glass filler. The glass filler improves adhesion and also minimizes the thermal expansion mismatch between the gold and the surrounding substrate material. In the preferred embodiment, the vias 304 are laser drilled using a CO 2 laser. The distance between vias 304 is approximately the same as the thickness of the substrate (302). Figures 3 and 4 also illustrate the improvement in transmission line geometry. The signal bond wire 318 has the upper ground plane 308 underneath for much of the distance to the integrated circuit 300, effectively forming a microstrip. In addition, the ground bond wire 324 provides a very short path from the same upper ground plane 308 to the integrated circuit. The grid of conductive vias 304 provides a very low impedance path between the upper and lower ground planes. While there is still some transmission line discontinuity at the signal bond 320, there is much less of a discontinuity than the prior art as illustrated in Figure 1.

Claims: An integrated circuit structure comprising: an integrated circuit die (300) having a back surface and having a plurality of bonding pads arranged on the top surface; a first plurality of wires (324) for electrical ground and a second plurality of wires (318) for electrical signals, wherein each wire from the first plurality of wires and the second plurality of wires is bonded to a corresponding pad in the plurality of bonding pads; a substrate (302) having top and bottom surfaces; a bottom ground plane (306) substantially covering the substrate (302) bottom surface; a top ground plane (308), located on the substrate (302) top surface; a plurality of vias (304) passing through the substrate (302) from the substrate top surface to the substrate bottom surface and connecting said top and bottom ground planes, the vias (304) being electrically and thermally conductive, the vias thereby providing heat transfer from the substrate top surface to the substrate bottom surface and high frequency electrical conductivity from the top ground plane (308) to the bottom ground plane (306); insulation means (310) for insulating the back surface of the integrated circuit die (300) from the top ground plane (308), the insulation means (310) located between the back surface of the integrated circuit die (300) and the top ground plane (308) and being attached to the top ground plane (308); and, wherein the top ground plane (308) extends beyond the bottom surface of the integrated circuit die (300), wherein each wire in the first plurality of wires (324) is bonded to the top ground plane (308), thereby providing a short high frequency ground path for each wire in the first plurality of wires (324), and wherein each wire in the second plurality of wires (318) is bonded to signal traces (322) arranged on the substrate top surface beyond the top ground plane, the wires in the second plurality of wires thus passing near the top ground plane (308), thereby forming a plurality of separate microstrips each composed of a wire in the second plurality of wires (318) in conjunction with the top ground plane (308). An integrated circuit structure as in claim 1 wherein the insulation means (310) comprises a layer of ceramic and a conductive layer (312) is sandwiched between the ceramic and the integrated circuit die (300). An integrated circuit structure as in claim 2 comprising: a bias voltage (316) electrically connected to the conductive layer (312). An integrated circuit structure as in claim 3 wherein the conductive vias (304) are filled with a metal. An integrated circuit structure as in claim 1 wherein the insulation means (310) comprises a layer of glass ceramic and a conductive layer (312) is sandwiched between the glass ceramic layer and the integrated circuit die (300). An integrated circuit structure as in claim 5 comprising: a bias voltage (316) electrically connected to the conductive layer (312). An integrated circuit structure as in claim 6 wherein the conductive vias (304) are filled with a metal.

Inventors: WALZ DALE D, WALZ, DALE D.
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1993
Main classification: H01L23
IPC codes: H01L21, H01P5, H01L23