Method for the automatic generation of test sequences

Abstract: Method for the automatic generation, from a system or protocol specified as an FSM, of unique test sequences in order to establish whether or not the implementation is in a particular state. On the basis of the FSM a table comprising legal possibilities is generated for each state, as well as a series of tables comprising legal impossibilities for the remaining states. Unique test sequences are found by selecting those IO sequences which occur in the "possibilities table" and in all the "impossibilities tables". If required, the shortest UIO sequence can be selected therefrom.

Description: A. BACKGROUND OF THE INVENTION The invention relates to a method for the automatic generation, from a system or protocol specified as an FSM, of sequences of input signals, which are to be supplied to a system to be tested, together with the associated output signals which are to be received from the system to be tested and which serve to establish whether or not the implementation is in a particular state. A useful introduction to the problems addressed by the present invention is provided in the US Patent No. 4692921 of AT&T, where it is stated that there has always been a need for the functioning of electronic systems to be tested and verified against the intended functioning. In the past, tests intended for this purpose were devised by the system designers who, in doing so, depended on their knowledge of the system design and the likely behaviour thereof. As VLSI (Very Large Scale Integration) progressed, this became more difficult. One of the causes is that there are no internal test points which can be approached to isolate faults. Another reason is that, in general, there are no repair possibilities. A further reason is that the design philosophy has changed from designs which attempt to limit the number of transistors to designs which intend to reduce the "real estate" and the input/output complexity. The number of active elements in an integrated circuit (IC) amounts to hundreds of thousands, and is still increasing. The masks with which these ICs are produced are very expensive and it is therefore extremely important that the ICs fabricated therewith function according to their specifications. Another point is that during fabrication no defects must be introduced, such as active elements which stick on the value 1 or 0. Even more importantly, it must be possible for ICs containing such defects to be detected quickly and simply. Hereinbelow, as in the said US Patent, use will be made of the possibility to describe digital systems as "finite state machines" (FSM) which, in response to certain sequences of input signals, emit certain sequences of output signals. These are called finite state machines because, in contrast to analog systems, they can adopt only a limited number of internal states and jump from one state to another state ("state transition" or "edge") in response to one or more input signals. An FSM can therefore also be regarded as having been specified by its reaction to input signals (in the form of output signals). An FSM can be represented both in the form of a diagram and in the form of tables. Said US Patent discloses a method for developing test sequences for evaluating the design or the functioning of a digital system presented as an FSM. According to the method disclosed, the entire FSM is run through, and all the state transitions are tested. For each state transition, a test is developed which comprises a three-part test sequence. The first part is a sequence which puts the FSM into a first state. The second part, by supplying an input signal, causes a state transition from the first state to a second state. The third part is formed by a sequence which is unique for the second state and whose purpose is to check whether the implemented FSM has indeed reached the state desired (in accordance with the specified FSM). This part is therefore formed by a sequence of input signals together with the associated output signals, which is unique with respect to all the other states of the FSM and can serve as a "signature", as it were, for that state. The invention is in the field of the automatic generation, from a system or protocol specified as an FSM, of sequences of input signals, which are to be supplied to a system to be tested, together with the associated output signals which are to be received from the system to be tested and which serve to establish whether or not the implementation is in a particular state, in other words the generation of unique input/output sequences (UIO sequences), and is comparable to process step 1 in the said patent. According to the known method for generating this type of sequences, the UIO sequences are generated via three intermediate steps. In the first intermediate step, a table is generated containing the "labels" of all state transitions and a designation of the "head" and the "tail" state(s) of each of those labels. In the second intermediate step, all the state transitions having a "null" input are identified, as well as all the state transitions whose tail state is identical to a head state of a state transition having a null input. Consecutive state transitions of this type then form a "meta" state transition. The meta state transitions and the remaining (non-null input) state transitions are incorporated in a second table. As a third step, this table is sorted according to state transition labels, and the labels which occur only once are marked. The labels are then sorted according to head state. The marked labels are unique. Finally, in a fourth step, the third step is repeated a number of times, resulting, generally, in a unique UIO sequence. Generating UIO sequences in this manner has a number of drawbacks. Notably, the known method results in only one UIO sequence for a particular state. Furthermore, when carrying out the said fourth step of the known method, there is the risk that this ends up in an "infinite loop", namely if no UIO sequence can be found. The method according to the present invention, in contrast, generates all the UIO sequences which are possible for a particular state (from which, incidentally, the shortest is preferably selected). B. SUMMARY OF THE INVENTION The invention therefore relates to a method for the automatic generation, from a system or protocol specified as an FSM, of sequences of input signals, which are to be supplied to a system to be tested, together with the associated output signals which are to be received from the system to be tested and which serve to establish whether or not the implementation is in a particular state. The invention is characterised by a first step in which the FSM is converted into a first table containing input-output signals and associated start and end states; a second step in which, for a particular state, a second table is generated by copying the first table and, in doing so, marking that state as a start state and all the other states as a valid end state; a third step in which for each of the other states a third table is generated by copying the first or the second table, adding thereto at least one escape state and, in those third tables, in each case marking that other state as a start state and that escape state as a valid end state for all invalid input-output signals; a fourth step in which a fourth table is generated by logically combining the second table with all the third tables to give combination states which occur both in the second and in all the third tables, that combination state being marked as a start state which is marked as a start state in both the second and in all the third tables, and all those combination states being marked as an end state which are marked as an end state in both the second and in all the third tables; a fifth step in which each sequence of input-output signals from the fourth table, starting from a combination state marked as a start state and ending in a combination state marked as an end state, is selected as one of the desired test sequences and is stored in a fifth table. To put it more simply, the method according to the invention successively comprises a conversion of the FSM - stored, for example, in a computer file - into a "base table" from which, for example for each state, two types of tables are generated. First - for that state - a table is produced in which, starting from that state as a start state, all the (according to the FSM) legal end states which are possible from that start state are indicated; this table could be called "possibilities table". This table thus comprises all the legal IO sequences which are possible from that start state. Thereafter - or at the same time - a table is produced for all the other states, in which table, starting from that "other" state as a start state, all nonlegal IO sequences are registered. A "virtual" end state for those nonlegal IO sequences is introduced in the form of an "escape state". In other words, if a nonlegal IO sequence is supplied in a particular state, the system always ends up in such an escape state. Thus one table has now been generated for the initial state, comprising legal IO sequences from that state, the "possibilities table" and a series of tables - "impossibilities tables" - comprising all nonlegal IO sequences from the other states. In order to establish that a system at a given time is in a particular state, it is sufficient to establish that an IO sequence from that state is legal, whereas that IO sequence from all the other states is nonlegal and results in an escape state. In that case, therefore, a UIO sequence is involved. All the UIO sequences for a particular state can thus be found by, starting from that state, logically combining its "possibilities table" with the "impossibilities tables" of all the other states; these sequences therefore must occur in the "possibilities table" AND in all those "impossibilities tables". The IO sequences satisfying this condition are UIO sequences for that state to be tested. The above method can be carried out for only one state, for example the start state of the FSM, or - successively or simultaneously - for more or even all the states. The method can then preferably be carried out simultaneously for all states, in which case in the second step a second table is generated for all states by copying the first table and, in doing so, marking those various states as a start state in the various second tables, and all the other states as a valid end state; in the third step a third table is generated for all the states by copying the first or the second table, adding thereto at least one escape state and in each case marking those various states as a start state in those various third tables and that escape state as a valid end state for all invalid input-output signals; a fourth step in which a fourth table is generated by logically combining the second tables with the third tables as indicated, resulting in combination states which occur both in the second and in all the third tables, those combination states being marked as a start state which are marked as a start state in both the second and in the third tables, and all those combination states being marked as an end state which are marked as an end state in both the second and in the third tables; a fifth step in which the sequences of input-output signals which start with a combination state marked as a start state and end in a combination state marked as an end state are selected as a desired test sequence and are stored in the fifth table. By calculating the UIO sequences for all the states simultaneously, the method can thus work very efficiently. To put it simply, in doing so, a "possibilities table" is generated for all states as well as an "impossibilities table" for all states. Subsequently, for each state, the "possibilities table" of that state is logically combined with the "impossibilities tables" of the remaining states, resulting in UIO sequences for each state, by means of which those states can therefore be identified. Figure 1 shows an illustration of the generation of the UIO sequences according to a first prior art teaching Figure 2 shows an illustration of the generation of the UIO sequences according to a second prior art teaching. C. ILLUSTRATIVE EMBODIMENTS An example will be given below of the generation of the UIO sequences for state 0 in the FSM of Figure 1, the same FSM as is shown in US Patent 4692921. In doing so, the steps will be followed which are specified in the main claim. I. In the first step, the FSM is converted into a first table containing input-output signals and start and end states associated therewith; see TABLE 1. II. In the second step, a second table is generated for a particular initial state - in this case state 0 - by copying the first table and, in doing so, marking that state as a start state, and all the other states as valid end states; see TABLE 2. III. In the third step, a third table is generated for each state other than the initial state by copying the first or the second table, adding thereto an escape state, and in each case marking, in those third tables, that other state as a start state and that escape state as a valid end state for all invalid input-output signals (hereinafter, a,b,c,... indicate the various escape states); see TABLE 3. IV. In the fourth step, a fourth table is generated by logically combining ('^') the second table (the "possibilities table") see TABLE 2, with all the third tables (the "impossibilities tables") see TABLE 3 to give combination states which occur both in the second and in all the third tables, that combination state being marked as a start state which is marked in both the third table and in all the third tables as a start state, and all those combination states being marked as an end state which are marked as an end state both in the second table and in all the third tables. First of all, the generation of the logical combination ('^') of all "impossibilities tables" of the states ≠ state 0 is demonstrated; see TABLE 4. Then the "possibilities table" of state 0 is logically combined with the "impossibilities tables" of the states ≠ 0; see TABLE 5. V. In the fifth step, the sequences of input-output signals which start with a combination state marked as a start state ('S') and which end in a combination state marked as an end state ('E') are selected as one of the desired test sequences and are stored in a fifth table. This works as follows (see TABLE 5): Starting from the start state, it is ascertained which "paths" lead to an end state. The following sequences are produced: 01234567S (1) → A/N → 1abc5efg (2) → D/X → 2abcdefg (3) End state 01234567s (1) → A/N → 1abc5efg (2) → D/X → 2abcdefg (3) → N/Y → 3abcdefg (4) End state 01234567S (1) → A/N → 1abc5efg (2) → D/X → 2abcdefg (3) → N/Y → 3abcdefg (4) → R/N → 0abcdefg (5) End state 01234567S (1) → A/N → 1abc5efg (2) → D/X → 2abcdefg (3) → N/Y → 3abcdefg (4) → R/N → 0abcdefg (5) → A/N → 1abcdefg (6) End state Etcetera The UIO sequences are therefore A/N → D/X A/N → D/X → N/Y A/N → D/X → N/Y → R/N A/N → D/X → N/Y → R/N → A/N Etcetera As all the sequences start with the same sequence A/N → D/X, the remaining sequences in fact do not add anything. The only relevant UIO sequence is therefore the UIO sequence A/N → D/X, which is suitable as a "signature" for state 0. In the same way, UIO sequences can be generated for the other FSM states, such as for state 7; see TABLE 6. Two (independent) IO sequences are produced from this system, which can both be used as a UIO sequence, viz. D/N (which effects the transition from state (1) to (2)); B/N → N/Z (which successively effects the transition from state (3) to (4) and then from (4) to (5)). Finally, the elaboration is also given for an FSM which is shown in Figure 2 and which is taken from US Patent 4991176 (AT & T), specifically for the state of that FSM 1; see TABLE 7. The result was obtained in the same manner as described hereinabove, in this case even as many as five UIO sequences: (A/X A/X) (A/X C/Y A/X) (A/X C/Y B/Z) (C/Y A/X) (C/Y B/Z) According to Dijkstra's known shortest-path method, it can be calculated that (A/X A/X) is the shortest of these UIO sequences. For the sake of completeness, TABLE 8 shows the source code of the computer program with which the method according to the invention can be carried out, which program was also used to produce the above illustrative examples. D. REFERENCES US 4692921 (AT&T)

Claims: Method for the automatic generation, from a system or protocol specified as an FSM, of sequences of input signals, which are to be supplied to a system to be tested, together with the associated output signals which are to be received from the system to be tested and which serve to establish whether or not the implementation is in a particular state, CHARACTERISED BY a first step in which the FSM is converted into a first table containing input-output signals and associated start and end states; a second step in which, for a particular state, a second table is generated by copying the first table and, in doing so, marking that state as a start state and all the other states as a valid end state; a third step in which for each of the other states a third table is generated by copying the first or the second table, adding thereto at least one escape state and, in those third tables, in each case marking that other state as a start state and that escape state as a valid end state for all invalid input-output signals; a fourth step in which a fourth table is generated by logically combining the second table with all the third tables to give combination states which occur both in the second and in all the third tables, that combination state being marked as a start state which is marked as a start state in both the second and in all the third tables, and all those combination states being marked as an end state which are marked as an end state in both the second and in all the third tables; a fifth step in which each sequence of input-output signals from the fourth table, starting from a combination state marked as a start state and ending in a combination state marked as an end state, is selected as one of the desired test sequences and is stored in a fifth table. Method according to Claim 1, CHARACTERISED IN THAT the second and subsequent steps are carried out for only one state of the FSM. Method according to Claim 2, CHARACTERISED IN THAT said second and subsequent steps are carried out only for the start state of the FSM. Method according to Claim 1, CHARACTERISED IN THAT the second and subsequent steps are carried out for all the states of the FSM. Method according to Claim 4, CHARACTERISED IN THAT in the second step for all states a second table is generated by copying the first table and, in doing so, marking those various states as a start state in the various second tables, and all the other states as a valid end state; in the third step a third table is generated for all the states by copying the first or the second table, adding thereto at least one escape state and in each case marking those various states as a start state in those various third tables and that escape state as a valid end state for all invalid input-output signals; a fourth step, in which a fourth table is generated by logically combining the second tables with the third tables as indicated, resulting in combination states which occur both in the second and in all the third tables, those combination states being marked as a start state which are marked as a start state in both the second and in the third tables, and all those combination states being marked as an end state which are marked as an end state in both the second and in the third tables; a fifth step in which the sequences of input-output signals which start with a combination state marked as a start state and end in a combination state marked as an end state are selected as a desired test sequence and are stored in the fifth table.

Inventors: VAN DE BURGT STEPHANUS PIETER, VAN DE BURGT, STEPHANUS PIETER
Applicants: NEDERLAND PTT, KONINKLIJKE PTT NEDERLAND N.V.
Application year: 1993
Main classification: G06F11
IPC codes: G01R31