Apparatus and method for controlling communication within a computing system

Abstract: An apparatus for managing communication within a computing system which includes a processing unit and a plurality of peripheral units. The processing unit receives information from a plurality of loci within the computing system and determines an enablement profile in response to such information according to predetermined criteria. The processing unit responds to the enablement profile to selectively enable specified peripheral units. The apparatus comprises a monitoring circuit for monitoring the enablement profile; a logic circuit for logically treating the enablement profile and generating a feedback signal representative of the enablement profile; and a transmission circuit for communicating the feedback signal from the logic circuit to the processing unit. The processing unit responds to the feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until the non-enabled unit is enabled. The invention further comprises a method for managing communications within such a computing system comprising the steps of monitoring the enablement profile; generating a feedback signal representative of the enablement profile; communicating the feedback signal to the processing unit; and configuring the processing unit to respond to the feedback signal to determine whether to employ a transfer trapping discipline.

Description: In certain computing system configurations, especially in those configurations where conservation of supply power is of importance (e.g., battery-powered computers), the processing unit of the computing system receives information from various loci within the computing system to monitor employment of various associated peripherals and determine whether the system is on battery power or external power (AC power). The processing unit evaluates the various information thus received and, according to predetermined criteria, disables selected peripheral devices within the computing system. For example, a failure to enter any keystroke entries on the keyboard for a predetermined time interval may result in disabling the display (e.g., the screen) until the display is further required. In such situations, any input/output (IO) transfer associated with a disabled peripheral device, cannot be sent to that disabled device until the device has been enabled and is able to receive the IO transfer. Such power preserving computing systems may employ what is known as an "IO trapping" discipline whereby an IO transfer destined for a disabled peripheral device is "trapped" (i.e., stored or otherwise held) until the system can effect re-enablement of the affected peripheral unit, and then releasing the IO transfer for delivery to the newly-enabled peripheral unit. There is an inherent performance degradation in operation of such a system since time must be taken to check whether a given peripheral unit is enabled -- a check which must be made no later than the end of a cycle period. Thus, even when all peripheral devices are enabled, an IO trapping discipline imposes inefficiencies in the response of the system. It would be advantageous to limit application of an IO trapping discipline to only those situations or configurations in which it is necessary that such a discipline be imposed. For example, when all peripheral devices are enabled or when power is derived from an AC source, no IO trapping discipline is required or desired. SUMMARY OF THE INVENTION According to the present invention there is provided an apparatus for controlling communication within a computing system; said computing system including a processing unit and a plurality of peripheral units; said processing unit being adapted to receive information from a plurality of loci within said computing system and to disable selected said peripheral units in response to said information according to predetermined criteria; said apparatus being characterised by comprising: an enabling unit operatively connected with said processing unit and with said plurality of peripheral units, said enabling unit adapted to respond to an enablement profile to selectively enable specified peripheral units of said plurality of peripheral units, said enablement profile being determined by said processing unit in response to said information according to said predetermined criteria; a monitoring means for monitoring said enablement profile; a logic means operatively connected with said monitoring means for logically treating said enablement profile, said logic means adapted to generate a feedback signal representative of said enablement profile; and a transmission means for communicating said feedback signal from said logic means to said processing unit; wherein said processing unit is adapted to respond to said feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until said non-enabled unit is enabled. According to the invention there is also provided a method which corresponds to the above defined apparatus and which is defined in claim 9 appended to this description. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of an embodiment of the present invention. Fig. 2 is a schematic diagram of the preferred embodiment of the present invention. Fig. 3 is a flow diagram illustrating the method of the present invention. DETAILED DESCRIPTION OF THE INVENTION Fig. 1 is a schematic diagram of an embodiment of the present invention. In Fig. 1, a computing system 10 is illustrated including a processing unit 12, an enabling unit 14, and a logic unit 16. Processing unit 12 conveys information to enabling unit 14 via a transfer bus 18. Such information as is conveyed via transfer bus 18 preferably includes information regarding an enablement profile for a plurality of peripheral units 20 a , 20 b , 20 c , ..., 20 n , in appropriate detail to facilitate generation by enabling unit 14 of appropriate signals on enabling lines 22 a , 22 b , 22 c , ..., 22 n to enable or disable peripheral units 20 according to the enablement profile conveyed via transfer bus 18. The enablement profile is established by the processing unit based upon a variety of information received by the processing unit from various loci (not shown) within computing system 10, according to predetermined criteria. Logic unit 16 monitors the enablement profile conveyed from processing unit 12 to enabling unit 14 via transfer bus 18 by monitoring lines 24 a , 24 b , 24 c , ... 24 n , and generates a feedback signal at an output 26; output 26 is operatively connected with processing unit 12. The feedback signal at output 26 of logic unit 16 is representative of the enablement profile conveyed via transfer bus 18. In the particular embodiment of the present invention illustrated in Fig. 1, logic unit 16 is an AND gate so that if any of the monitoring lines 24 a , 24 b , 24 c , ..., 24 n indicates that its respective peripheral unit 20 a , 20 b , 20 c , ... 20 n is not enabled, then the feedback signal at output 26 of logic unit 16 will indicate that not all peripheral units 20 are enabled. In such a situation, processing unit 12 will respond to the feedback signal at output 26 of logic unit 16 by invoking a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until that non-enabled unit is enabled. When the feedback signal indicates that all peripheral units are enabled, then no transfer trapping discipline is imposed. As discussed above, such a transfer trapping discipline involves a predetermined "overhead" in terms of delay time thereby slowing operation of computing system 10 whenever the transfer trapping discipline is invoked. An advantage of the apparatus of the present invention in its employment with computing system 10 is to preclude employment of a transfer trapping discipline when all peripheral units 20 are enabled, thereby allowing speedier operation of computing system 10 at least during some periods of its operation (i.e., when all peripheral units 20 are enabled). An additional input to processing unit 12 from enabling unit 14 (or from elsewhere within computing system 10) may be conveyed via a line 28 to indicate whether computing system 10 is powered by battery power or by external AC (alternating current) power. Such an input to processing unit 12 is preferable in employing the apparatus of the present invention with computing system 10 so that processing unit 12 may respond to an indication that computing system 10 is operating on AC power to independently preclude employment of a transfer trapping discipline. This is so because, when AC power is employed as a power source for computing system 10, no considerations regarding power conservation need impinge upon operation of computing system 10 so that there is no need for processing unit 12 to selectively disable peripheral units 20. That is, no transfer trapping discipline need be employed (and no inherent "overhead" time delay need be incurred) when AC power is employed. Fig. 2 is a schematic diagram of the preferred embodiment of the apparatus of the present invention. In Fig. 2, a computing system 30 is illustrated including a processing unit 32, an enabling unit 34, a logic unit 36, and a monitoring unit 38. Enabling unit 34 provides enabling signals to peripheral units 40 a , 40 b , 40 c , 40 d , ... 40 n via enabling lines 42 a , 42 b , 42 c , 42 d , ... 40 n . Information about an enablement profile appropriate to facilitate operation of enabling unit 34 to selectively enable peripheral units 40 is conveyed from processing unit 42 to enabling unit 34 via a transfer bus 44. Processing unit 32 establishes the enablement profile according to predetermined criteria based upon information received from various loci (not shown) within computing system 30. Monitoring unit 38 receives information about the enablement profile via an enablement bus 46; monitoring unit 38 preferably comprises a storage device appropriate to store information regarding each of peripheral devices 40. As will be recognized by one skilled in the art, monitoring unit 38, shown as a separate unit in Fig. 2, may be employed as a sub-unit of enabling unit 34, receiving enablement profile information via transfer bus 44 or may be an integral portion of processing unit 32. Enablement profile information is conveyed from monitoring unit 38 to logic unit 36 via a monitoring bus 48, and logic unit 36 generates a feedback signal on a feedback line 50. The feedback signal is representative of the enablement profile conveyed from monitoring unit 38 via monitoring bus 48 to logic unit 36. Processing unit 32 responds to the feedback signal conveyed via feedback line 50 to determine whether to employ a transfer trapping discipline. The feedback signal conveyed via feedback line 50 may include battery/AC power source information or a separate input (not shown) may convey an override feedback signal regarding such power source information to processing unit 32 in a manner similar to the provision of such a separate override feedback signal to processing unit 12 (see line 28 in Fig. 1). Fig. 3 is a flow diagram illustrating the method of the present invention. In Fig. 3, the method starts with a start block 60 and, according to block 62, the enablement profile established by information received from a plurality of loci within the computing system is monitored. As indicated by block 64, the monitored enablement profile is employed to generate a feedback signal which is conveyed to the processing unit, as indicated by block 66. On receiving the feedback signal, the processing unit decides whether to employ a transfer trapping discipline according to predetermined criteria, as indicated by block 68. As one skilled in the art will recognize, the method must return to start, as indicated by block 70, in order that the information from the various loci within the computing system may constantly be monitored so that the enablement profile may be constantly updated, and the decision whether to employ a transfer trapping discipline may be constantly re-evaluated in order that the most efficient employment of a transfer trapping discipline (with its inherent "overhead" time delays) may be appropriately effected.

Claims: An apparatus for controlling communication within a computing system (10,30); said computing system including a processing unit (12,32) and a plurality of peripheral units (20a..n,40a..n); said processing unit being adapted to receive information from a plurality of loci within said computing system and to disable selected said peripheral units in response to said information according to predetermined criteria; said apparatus being characterised by comprising: an enabling unit (14,34) operatively connected (18,44) with said processing unit and with said plurality of peripheral units, said enabling unit adapted to respond to an enablement profile to selectively enable specified peripheral units of said plurality of peripheral units, said enablement profile being determined by said processing unit in response to said information according to said predetermined criteria; a monitoring means (24a..n,38) for monitoring said enablement profile; a logic means (16,36) operatively connected with said monitoring means for logically treating said enablement profile, said logic means adapted to generate a feedback signal representative of said enablement profile; and a transmission means (26,50) for communicating said feedback signal from said logic means to said processing unit; wherein said processing unit is adapted to respond to said feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until said non-enabled unit is enabled. An apparatus for controlling communication within a computing system as claimed in claim 1 wherein said monitoring means (24a..n) is operatively connected with said processing unit (12) via said enabling unit (14). An apparatus for controlling communication within a computing system as claimed in claim 2 wherein said enabling unit is operatively connected with said plurality of peripheral units by a plurality of enabling transmission lines (22a..n), and wherein said monitoring means comprises a plurality of monitoring transmission lines (24a..n) operatively connecting said plurality of enabling transmission lines with said logic means. An apparatus for controlling communication within a computing system as claimed in claim 3 wherein said logic means (16) comprises an AND gate. An apparatus for controlling communication within a computing system as claimed in claim 1 wherein said monitoring means (38) comprises a storage means for storing said enablement profile. An apparatus for controlling communication within a computing system as claimed in claim 5 wherein said monitoring means (38) is operatively connected between said processing unit (32) and said logic means (36). An apparatus for controlling communication within a computing system as claimed in claim 6 wherein said monitoring means (38) is a sub-unit of said enabling unit (34). An apparatus for controlling communication within a computing system as claimed in any preceding claim, wherein said processing unit is further adapted to respond to a power source information signal such that when the computing system employs AC power as said power source then said transfer trapping discipline is precluded independently of said enablement profile. A method for controlling communication within a computing system (10,30); said computing system including a processing unit (12,32) and a plurality of peripheral units (20a..n,40a..n); said processing unit receiving information from a plurality of loci within said computing system and disabling selected said peripheral units in response to said information according to predetermined criteria; said method being characterised by comprising the steps of: employing an enabling unit (14,34) which is operatively connected with said processing unit and with said plurality of peripheral units and responds to an enablement profile to selectively enable specified peripheral units of said plurality of peripheral units, said enablement profile being determined by said processing unit in response to said information according to said predetermined criteria; monitoring (62) said enablement profile; employing a logic circuit (16,36) for generating (64) a feedback signal representative of said enablement profile; communicating (66) said feedback signal from said logic circuit to said processing unit; and said processing unit responding (68) to said feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until said non-enabled unit is enabled. A method for controlling communication within a computing system as claimed in claim 9 wherein said logic circuit (16) comprises an AND gate.

Inventors: GEPHARDT DOUGLAS D, MCBRIDE ANDREW, GEPHARDT, DOUGLAS D., MCBRIDE, ANDREW
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1993
Main classification: G06F13
IPC codes: G06F13