Method for formation of contact vias in integrated circuits

Abstract: A method for forming contact vias (34,36) in a integrated circuit (10) which do not have planarizing material nearby. After a first insulating layer (16) is deposited over the integrated circuit, a planarizing layer (18) is deposited over the first insulating layer. The planarizing layer (18) is etched back and portions of the planarizing layer (18) may remain in the lower topographical regions of the first insulating layer (16) to planarize the surface of the integrated circuit. A first masking layer (20) is then formed over the surface of the integrated circuit (10). The openings (22,24) created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer (16) is partially etched into so that portions of the planarizing layer (18) near the locations of the contact vias (22,24) are removed. The first masking layer (20) is then removed, and a second insulating layer (26) is deposited over the integrated circuit (10). A second masking layer (28) having openings (30,32) which define the locations of the contact vias (34,36) to be created is then formed over the second insulating layer (26). The size of the openings (30,32) in the second masking layer (28) are smaller than the size of the openings (22,24) in the first masking layer (20). The contact vias (34,36) are then formed through the first and second insulating layers (26,18).

Description: The present invention relates generally to the fabrication of integrated circuits, and more particularly to a method for forming contact vias in integrated circuits. By increasing the density of components in an integrated circuit, it has become necessary to fabricate multilevel metal interconnect and contacts between the layers. To maintain the integrity of the layers of metal interconnect and contacts, insulating layers must be formed between each metal interconnect layer. Fabricating multiple layers, however, results in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to maintain constant cross sections when crossing over uneven topography. This can lead to portions of the metal interconnect lines having a higher current density or voids in the lines themselves. These defects can cause electromigration or other related device failure mechanisms. Various techniques are used during the fabrication process to planarize the surface of the integrated circuit. One method involves depositing a layer of spin on glass over an insulating layer. The spin on glass is then etched back so that portions of the spin on glass remain in the lower topographical regions of the insulating layer. This planarizes the surface of the integrated circuit. A problem arises, however, when forming contact vias between metal interconnect lines. When forming a metal contact within the contact via, the spin on glass can contaminate the metal contact. This can cause step coverage problems or increased resistivity in the contact. EP 0388862 relates to the fabrication of a multilevel interconnection structure. A silicon oxide film is deposited on the entire surface of the device, which includes a first layer conductor pattern. A layer of SOG is formed on the silicon oxide film. The SOG layer is uniformly etched by dry etching until the silicon oxide film is exposed, and the SOG layer is planarized. A PSG layer is provided on the planarized SOG layer. A contact hole is formed through the PSG layer and the silicon oxide film underneath, until the first conductor pattern is exposed. A second conductor layer is deposited on the PSG layer and fills the contact hole. The second conductor layer is patterned to form a second layer conductor pattern. The interlevel contact therefore has PSG in its sidewalls. BE-A-901 350 discloses a method of forming a contact opening to an underlying semiconductor structure. P-silox is deposited over a first oxide layer. Windows are made in the P-silox layer. The P-silox is reflowed. A second oxide layer is deposited over the device. A window is etched to the underlying semiconductor structure, this window being situated in the previous window. EP-A-0488546 is a document falling within the terms of Article 54(3) EPC. It discloses a method for forming a contact in a semiconductor integrated circuit which comprises the formation of dielectric sidewall spacers within the via. It would be desirable to provide a method for fabricating contact vias in integrated circuits that do not have planarizing material therein. It is also desirable that such a method not significantly increase the complexity of the manufacturing process. According to the present invention, a method is provided for forming contact vias in integrated circuits which do not have planarizing material therein. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit. A second masking layer having openings which define the locations of the contact vias to be created is then formed over the second insulating layer. The size of the openings in the second masking layer are smaller than the size of the openings in the first masking layer. The contact vias are then formed through the first and second insulating layers. According to one aspect of the present invention there is provided a method for forming a contact via in an integrated circuit, comprising the steps of: forming a first insulating layer with planarizing material on the upper surface thereof, over an underlying region in the integrated circuit; etching, to remove the planarizing material above the first insulating layer at the location of the contact via to be formed, the etching being effected to a depth below an upper surface of the first insulating layer thereby forming an opening with planarizing material remaining at the sides of the opening; forming a second insulating layer over the integrated circuit and within said opening; and forming the contact via through the first and second insulating layers to expose a portion of the underlying region without exposing the planarizing material, the contact via being of less width than and within said opening. The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Figures 1 - 8 are sectional views of an integrated circuit illustrating a preferred method for forming contact vias in an integrated circuit according to the present invention. The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. Referring to Figure 1 , conductive elements 12 , 14 are formed on an underlying region 10 in an integrated circuit. The underlying region 10 can be either a semiconductor substrate or an interlevel insulating layer. The conductive elements are preferably metal interconnect signal lines, but can also be polycrystalline silicon interconnect signal lines. A first insulating layer 16 is then deposited over the integrated circuit, followed by a planarizing layer 18 . The first insulating layer 16 is preferably made of oxide, and the planarizing layer 18 is preferably made of spin on glass. Other insulating and planarizing materials, however, can be used. Figure 2 illustrates the integrated circuit after an anisotropic etch is performed leaving portions of the planarizing layer 18 in the lower topographical regions of the first insulating layer 16 . As known in the art, this planarizes the surface of the integrated circuit. Referring to Figure 3 , a first masking layer 20 is deposited and patterned on the surface of the integrated circuit using techniques known in the art. The first masking layer 20 is typically a photoresist mask. Openings 22 , 24 in the first masking layer 20 are made larger than the contact vias to be formed later. The purpose for making the size of the openings 22, 24 in the masking layer 20 larger is illustrated in Figure 4 . Those portions of the first insulating layer 16 which are exposed in the openings 22, 24 are anisotropically etched partway through. Portions of the planarizing layer 18 which are located near the contact vias to be formed are also removed. This is done so that when the contact vias are formed, there will not be any planarizing material nearby to contaminate the contacts. Referring to Figure 5, the first masking layer 20 is removed and a second insulating layer 26 is deposited over the integrated circuit. The second insulating layer 26 is preferably made of oxide, but can be made of other insulating materials. Figure 6 illustrates the integrated circuit after a second masking layer 28 is deposited over the second insulating layer 26. The masking layer 28 is patterned using techniques known in the art to form openings 30, 32 which define the locations of the contact vias to be formed. The masking layer 28 typically is a photoresist mask. The sizes of the openings 30, 32 are smaller than the openings 22, 24 made in the first masking layer 20. Referring to Figure 7, contact vias 34, 36 are formed by performing an anisotropic etch through the first 16 and second 26 insulating layers to expose the conductive elements 12, 14 . The second masking layer 28 is then removed. As can be seen, the planarizing material in the planarizing layer 18 is not exposed in the contact vias 34, 36. The contact vias 34, 36 are surrounded by the materials in the first 16 and second 26 insulating layers. Those skilled in the art will recognize that this prevents the planarizing material from migrating into the contact vias 34, 36 and contaminating the metal used for the contacts or causing step coverage problems later on in the fabrication process. Referring to Figure 8, a conductive layer 38 is deposited and patterned over portions of the second insulating layer 26 and extends into the contact vias 34, 36 to make electrical contact with the conductive elements 12, 14. The conductive layer 38 is preferably made of aluminum, but other conducting materials can be used. The integrated circuit is now ready for further processing steps. As described above, the present invention provides a method for forming contact vias which are free from highly doped planarizing materials along the sidewalls. This prevents the planarizing material from outgassing or contaminating the contacts or causing step coverage problems later on in the fabrication process. Furthermore, the present invention does not significantly increase the complexity of the fabrication process. The present invention may provide a method wherein the step of forming the second insulating layer comprises depositing a layer of oxide over the integrated circuit. The present invention may provide a method, wherein an interconnect layer comprises a metal interconnect. The present invention may provide a method wherein the step of forming the first insulating layer comprises depositing a layer of oxide over the integrated circuit. The present invention may provide a method wherein the step of forming the planarizing layer comprises depositing a layer of spin on glass over the dielectric layer. The present invention may provide a method wherein the step of forming a first masking layer comprises depositing a photoresist layer over the integrated circuit. The present invention may provide a method wherein the step of forming a second masking layer comprises depositing a photoresist layer over the insulating layer.

Claims: A method for forming a contact via (34) in an integrated circuit, comprising the steps of: forming a first insulating layer (16) with planarizing material (18) on the upper surface thereof, over an underlying region (10, 12) in the integrated circuit; etching, to remove the planarizing material above the first insulating layer (16) at the location of the contact via to be formed, the etching being effected to a depth below said upper surface of the first insulating layer (16) thereby forming an opening with planarizing material (18) remaining at the sides of the opening; forming a second insulating layer (26) over the integrated circuit and within said opening; and forming the contact via (34) through the first (16) and second (26) insulating layers to expose a portion (12) of the underlying region (10,12) without exposing the planarizing material (18), the contact via being of less width than and within said opening. The method of claim 1, further comprising the steps of depositing and patterning a conductive layer (38) over portions of the second insulating layer (26), wherein the conductive layer extends into the contact via (34) to make electrical contact with a portion of the underlying region (12). The method of any preceding claim, wherein said step of forming the first insulating layer (16) with planarizing material (18) comprises the steps of: depositing a layer of oxide (16) over the integrated circuit; depositing a layer of spin on glass (18) over the layer of oxide; and anisotropically etching the spin on glass (18). The method of any preceding claim, wherein said step of etching into the first insulating layer (16) comprises anisotropically etching the layer. The method of any preceding claim, wherein said step of forming the contact via (34) comprises anisotropically etching through the first (16) and second (26) insulating layers. The method of any preceding claim, wherein said underlying region comprises an interconnect layer (12) formed on a semiconductor substrate (10). The method according to claim 1, further comprising the step of: forming conductive elements (12,14) on an underlying region in the integrated circuit, prior to said step of forming the first insulating layer. The method according to claim 7, wherein said step of forming a first insulating layer containing planarizing material on the upper surface thereof comprises: forming a first insulating layer (16) over the integrated circuit; and forming a planarizing layer (18) over the first insulating layer. The method according to claim 8, wherein said step of partially etching into the first insulating layer comprises: forming a first masking layer (20) over the integrated circuit; patterning the first masking layer to define an opening, wherein the size of the opening is larger than the size of the contact via (34) to be formed; removing any remaining portions of the planarizing layer (18) within the opening and a portion of the first insulating layer (16); and removing the first masking layer (20). The method according to claim 9, wherein said step of forming a contact via through the first and second insulating layers comprises: forming a second masking layer (28) over the second insulating layer (26); patterning the second masking layer to form an opening (30) which defines the location of the contact via to be formed, wherein the size of opening (30) in the second masking layer is smaller than the size of the opening (22) made in the first masking layer (20); and forming the contact via (34) through the first (16) and second (26) insulating layers to expose a portion of the conductive elements (12,14). The method of claim 7 or any preceding claim dependent on claim 7, wherein said step of forming conductive elements on the underlying region comprises depositing a layer of metal and patterning it to define metal interconnect. The method of claim 9 or any preceding claim dependent on claim 9, wherein prior to forming the first masking layer (20) the planarizing layer (18) is etched in order to make the planarizing layer thinner. The method of claim 12, wherein the planarizing layer (18) is anisotropically etched. The method of claim 9 or any preceding claim dependent on claim 9, wherein said step of removing a portion of the first insulating layer (16) and any remaining portions of the planarizing layer (18) comprises anisotropically etching said layers (16,18). The method of claim 10 or any preceding claim dependent on claim 10, wherein said step of forming the contact via comprises anisotropically etching the first (16) and second (26) insulating layers to expose a portion of the conductive elements. The method of any of claims 7 to 15, further comprising the steps of: removing the second masking layer (28) ; and depositing and patterning a conductive layer (38) over a portion of the second insulating layer (26), wherein the conductive layer extends into the contact via (34) to make electrical contact with a portion (12) of the conductive elements. The method of claim 8 or any preceding claim when dependent on claim 8, wherein said step of forming the first insulating layer (16) comprises depositing a layer of oxide over the integrated circuit. The method of claim 8 or any preceding claim which is dependent on claim 8, wherein said step of forming the planarizing layer (26) comprises depositing a layer of spin on glass over the first insulating layer. The method of claim 9 or any preceding claim when dependent on claim 9, wherein the step of forming a first masking layer (20) comprises depositing a photoresist layer over the integrated circuit. The method of any preceding claim, wherein said step of forming the second insulating layer (26) comprises depositing a layer of oxide over the integrated circuit. The method of claim 10 or any preceding claim when dependent on claim 10, wherein said step of forming a second masking layer (28) comprises depositing a photoresist layer over the integrated circuit.

Inventors: HUANG KUEI-WU, HUANG, KUEI-WU
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L23