Integrated structure protection device for the protection of logic-level power MOS devices against electro static discharges

Abstract: An integrated structure protection device suitable for protecting a power MOS device from electro static discharges comprises a junction diode (9) comprising a first electrode made of a highly doped region (12) of a first conductivity type surrounded by a body region (11) of a second conductivity type and representing a second electrode of the junction diode (9), which in turn is surrounded by a highly doped deep body region (10) of said second conductivity type. The highly doped region (12) is connected to a polysilicon gate layer (7) representing the gate of the power MOS device, while the deep body region (10) is connected to a source region (6) of the power MOS.

Description: The present invention relates to an integrated structure protection device for the protection of logic-level power MOS (MOSFET, IGBT and so on) devices against electro static discharges. MOS devices are more and more employed in power electronics thanks to the simplicity of the circuits necessary for their driving operation and to their switching performances. Among power MOS devices, those which can be directly driven by logic-level signal (called logic-level power MOS) hold a significant market share. In their most common use, logic-level power MOS can be directly driven by a microprocessor. Since it is known that most logic families have logic-level voltage values compatible with those of the TTL technology, it follows that logic-level power MOS must have threshold voltage values ranging from 1V to 2V: in fact, they shall remain in the "off" state for gate driving voltages between 0V and 0.8V (corresponding to the "0" logic level), while they shall drain the nominal current when the gate voltage is higher than 2.4V (corresponding instead to the "1" logic level). Due to the low value of the threshold voltage, these devices are labeled with the letters LT (Low Threshold). In order to achieve said threshold voltage values, it is necessary for logic-level MOS power devices to have a gate oxide layer that is rather thin, with thickness typically ranging from 30 nm to 80 nm. Such a thin layer can be permanently damaged if a voltage higher than a few tens of volts is applied to the gate of the device. For this reason logic-level power MOS are particularly affected by Electro Static Discharges (ESD) problems. To prevent ESD failures, manufacturers of logic-level power MOS devices provide said devices with integrated structure protections, usually made up of diodes. Such protections, however, set two opposing kind of limits: the first is represented by the breakdown voltage of each of said diodes, while the second deals with the series resistance introduced by the diodes. Each diode should have a breakdown voltage higher than the maximum driving voltage of the power MOS device, in order to prevent it from draining current from the driving circuit of the power MOS device. Since diodes obtained from p + /n + junctions exhibit low breakdown voltages (with values even below 5V), it is necessary to connect a plurality of such diodes in series. Another possibility is represented by the use of p/n + junction diodes, which generally have breakdown voltages of the order of 10V. If, however, the series resistance introduced by the protection structure is not negligible, during an electro static discharge it can give rise to a voltage drop able to damage the protected power device. Pat. Abs. Jap. vol. 10 No. 359(E-460) and corresponding JP-A-61156856 discloses a protection diode for a MOSFET in a VLSI integrated circuit. US-A-3999212 discloses a clamp diode for a MOSFET; the diode comprises an anode region formed directly in a semiconductor substrate, and a cathode region made of a heavily doped ring surrounding the anode region and deeper than the latter. US-A-4890143 discloses a protection diode for a DMOS cell of a MOS-gated device. The diode comprises an anode region formed in a semiconductor substrate, a cathode region formed therein; the anode region is merged at an end with a base region of a DMOS cell. Pat. Abs. Jap. vol. 7 No. 99 (E-172) discloses an IGFET and a bidirectional diode inserted in series between the gate and source of the IGFET. The bidirectional diode comprises two cathode region respectively connected to the gate and to the source of the IGFET, formed inside a common anode region in turn formed in a semiconductor substrate. In view of the state of art described, the object of the present invention is to provide an integrated structure protection device suitable for protecting logic-level power MOS devices during electro static discharges, which is not affected by the abovementioned problems. According to the present invention, such object is attained by means of an integrated structure protection device comprising a junction diode as claimed in claim 1. In a first embodiment of the present invention said deep body region is phisically set apart from said source regions of the power MOS device, and the connection to them is carried out by means of a superimposed conductive layer coincident with a source electrode. In a second embodiment of the present invention said source region of the power MOS device is obtained inside said deep body region of the junction diode. Thanks to the structure according to the present invention, particularly to the deep body region surrounding the anode of the junction diode, it is possible to obtain an integrated structure protection diode having a breakdown voltage in the range of 1OV, and with low series resistance. Moreover, the area occupied by this protection device is very small, particularly when the second embodiment is utilized. The two abovementioned solutions will now be described in detail with reference to the annexed drawings, wherein: Figure 1 shows in section an integrated structure protection device not forming part of the claimed invention; Figure 2 is a top view of the integrated structure protection device shown in Figure 1; Figure 3 shows in section an integrated structure protection device according to the present invention; Figure 4 is a top view of the integrated structure protection device shown in Figure 3; Figures 5-10 shows sectional views representing intermediate steps of the fabrication process of the integrated structure protection device according to the present invention; Figure 11 is an equivalent electrical diagram of the integrated structures shown in Figures 1 and 3. With reference to the drawings, a known power MOS (MOSFET-type) device is made up of a plurality of cells 1 obtained on a substrate 2 of a semiconductor material, for example of the n + type, with superimposed an epitaxial layer 3 of the n - type. Each cell 1 comprises a deep p + type region 4 contacting at least one lateral p type channel region 5, and at least one n + type source region 6. A polysilicon gate layer 7, isolated from the top surface of the substrate 2 by a thin gate oxide layer 8, is superimposed over said p type channel region 5 and extends over said n + type source region 6. A superimposed conductive layer 15, for example of aluminium, represents a source electrode S and contacts the substrate 2 top surface in correspondence with said deep p + type region 4 and said n + type source region 5. A drain electrode D (not shown) contacts a bottom surface of the substrate 2. As shown in Figures 1 and 2, a first embodiment provides for the fabrication of a p/n + junction diode 9, phisically set apart from all the cells 1. The diode 9 comprises an annular p + type deep body region 10, extending from the surface of the substrate 2 into the epitaxial layer 3 and completely surrounding a p type body region 11 representing an anode of the diode 9. Within the p type body region 11 an n + type cathode region 12 is obtained. A gate electrode 13, for example of aluminium, contacts both the polysilicon gate layer 7 and the n + type cathode region 12, and extends to a gate contact pad G, not shown in Figure 2. One side of the deep body region 10 is contacted by the source electrode S, so that the n+ type source regions 6 and the deep p+ type region 4 are electrically connected to said deep body region 10. In the present invention, shown in Figures 3 and 4, the annular p + type deep body region 10 is merged with the deep p + type region 4 of one of the cells 1 of the power MOS device, and includes a portion of the n + type source region 6. The diode series resistance is thus further reduced, as well as the occupied area. As shown in Figures 5-10, a typical process for the fabrication of a power MOSFET device featuring the integrated structure protection device of the present invention, as shown in Figures 3 and 4, provides for the growth of the n - epitaxial layer 3 over the n + type substrate 2, the growth of a field oxide layer 14, and the masked implant and subsequent diffusion of a p type dopant to form a plurality of said deep p + type regions 4 and the annular p + type deep body region 10 of the junction diode 9 (Fig. 5). After a masking step suitable for defining active area regions on the surface of the substrate 2, the gate oxide layer 8 is grown (Fig. 6); the polysilicon gate layer 7 is then deposited and doped (Fig. 7), and is subsequently etched to form gate regions 17. A low concentration of p type dopant is then diffused within the boundary defined by said annular p + type deep body region 10 and under said gate regions, to form a plurality of p type channel regions 5 and the p type body region 11 representing the anode of the diode 9 (Fig. 8). A high concentration of n type dopant is then diffused at the sides of said gate regions and inside the p type body region 11, in order to form the n + type source regions 6 of the plurality of cells 1 and the n + type cathode region 12 of the diode 9. An insulating dielectric layer 16, for example of phosphosilicate glass, is then deposited on the surface (Fig. 9), and, after the definition of contact areas, a conductive layer, for example of aluminium, is deposited over the surface, in order to form the gate electrode 13 and the source electrode S. It appears that no additional steps, with respect to a known process for the fabrication of a power MOS device, are required in order to obtain the integrated structure protection device of the present invention. Since the junction diode 9 is obtained from a p/n + junction, it shows a breakdown voltage value of about 10 V; the p + type deep body region 10, which surrounds the p type body region 11 representing the anode of the diode 9, reduces the series resistance of the diode 9. It also enhances the ruggedness of the overall devices, since it prevents the formation of inversion layers (its doping is much higher than that of the region 11). The region 10 is used as contact region for the anode of the diode 9. Also, the invention applies to p-channel devices; in this case it is necessary to substitute p-type regions for n-type regions and viceversa, and to reverse the diode connection to the source and gate electrodes. Experimental results have proved that the present structure is suitable for protecting the power MOS device from electro static discharges up to 16 KVolts.

Claims: An integrated structure protection device for the protection of a power MOS device, comprising a junction diode (9) formed in a substrate (2,3) of a semiconductor material of a first conductivity type in which the power MOS device is also formed, said junction diode (9) comprising a first electrode made of a first, highly doped region (12) of a first conductivity type connected to a gate layer (7) of said power MOS device and extending from a top surface of the substrate (3) within a second doped body region (11) of a second opposite conductivity type, which forms a second electrode of said junction diode (9) and extends into the substrate (3) from said top surface, and a third highly doped annular deep body region (10) of said second conductivity type more heavily doped than and provided around said second doped region (11), the third highly doped region connected to source regions (6) of said power MOS device, the power MOS device made up of a plurality of cells (1) each comprising a fourth, deep highly doped region (4) of said second conductivity type, at least one lateral channel region (5) of said second conductivity type less doped than the fourth doped region (4), at least one highly doped source region (6) of said first conductivity type inside said fourth doped region and extending into said lateral channel region (5), and said gate layer (7) which is isolated from the surface of the substrate (3) by a thin gate oxide layer (8) superimposed over said channel region (5) and extends over said source region (6), said third highly doped annular body region (10) of the junction diode (9) being merged with the fourth highly doped region (4) of at least one of said cells (1) of the power MOS device, and containing the source region (6) of said cell (1). An integrated structure protection device according to claim 1, characterized in that said first conductivity type regions (3, 6, 12) are semiconductor regions doped with donor impurities, while said second conductivity type regions (4, 5, 10, 11) are semiconductor regions doped with acceptor impurities. An integrated structure protection device according to claim 2, characterized in that said first highly doped region (12) is an n + type region of semiconductor material. An integrated structure protection device according to claim 2, characterized in that said second doped region (11) is a p type region of semiconductor material. An integrated structure protection device according to claim 2, characterized in that said third doped region (10) is a p + type region of semiconductor material. An integrated structure protection device according to claim 1, characterized in that said first conductivity type regions (3, 6, 12) are semiconductor regions doped with acceptor impurities, while said second conductivity type regions (4, 5, 10, 11) are semiconductor regions doped with donor impurities. An integrated structure protection device according to claim 6, characterized in that said first highly doped region (12) is a p + type region of semiconductor material. An integrated structure protection device according to claim 6, characterized in that said second doped region (11) is an n type region of semiconductor material. An integrated structure protection device according to claim 6, characterized in that said third doped region (10) is an n + type region of semiconductor material. An integrated structure protection device according to any one of the preceding claims 2-5, characterized in that said substrate (2) is of semiconductor material doped with donor impurities. An integrated structure protection device according to any one of claims 6 to 9, characterized in that said substrate (2) is of semiconductor material doped with acceptor impurities. A process of manufacturing a power MOS device with an integrated structure protection diode, as claimed in claim 1 and comprising the following steps : a) forming in a semiconductor layer (3) of a first conductivity type at least one power MOS cell (1) comprising a highly doped region (4) of a second conductivity type, at least one adjoining lateral channel region (5) and more lightly doped than the highly doped region, at least a highly doped source region (6) of the first conductivity type inside the highly doped region and extending into the channel region, and an insulated gate layer (7) over the channel region, b) forming a first diode electrode region (11) of the second conductivity type in the semiconductor layer, forming a highly doped second diode electrode region (12) of the first conductivity type inside the first diode electrode region, and c) forming, simultaneously with the highly doped region (4) of the at least one power MOS cell (1), a highly doped annular region of the second conductivity type around said first diode electrode region, d) connecting the first diode electrode region electrically to the source region and connecting the second diode electrode region electrically to the gate layer of the power MOS device. A process according to claim 12, characterized in that said first diode electrode region (11) is formed simultaneously with the lateral channel region (5) of the power MOS cell (1). A process according to claim 13, characterized in that said second diode electrode region (12) is formed simultaneously with the source region (6) of the power MOS cell (1).

Inventors: ZAMBRANO RAFFAELE, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1993
Main classification: H01L27
IPC codes: H01L29, H01L27