Control, reduction and equalization of delays in a low-side driver stage

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Description: The present invention relates to a control circuit for an output power transistor (low-side driver) having means for reducing and controlling switching delays and which permits to make substantially identical the turn-off and the turn-on delays of the output signal. Many power ICs are required to drive external loads connected to a supply line (low-side driver). The power switch that is commonly employed in these ICs, whenever the fabrication technology will permit it, is an integrated DMOS transistor, because it offers numerous advantages as compared with a bipolar transistor of similar power rating. By driving the gate of the DMOS, its drain voltage, i.e. the voltage (signal) on the output node of the low-side driver stage, varies between Vds=Rdson*Id and Vds=H.V., wherein Id is the current flowing through the power transistor and H.V. is the supply voltage of the external load. In order to minimize the power dissipated through the power transistor when it is conducting, it is necessary to minimize its Rdson. This is obtained by imposing to the gate a voltage higher than the grounded source potential of the power transistor by a well defined quantity, equal to about 10V (overdrive voltage). Most often in practice, the supply voltage Vcc of the integrated circuit is applied to the gate of the output power transistor during a conduction phase. The document JP-A-1183214 discloses a control circuit for an output power transistor including a first controlled current generator for charging a control node of the power transistor and second and third current generators for discharging the driving node capacitance of the power transistor, whereby the third current generator helps in discharging the driving node capacitance until the power transistor reaches a near saturation condition. A control circuit that is normally used for driving an output power DMOS transistor is schematically depicted in Fig. 1. The current generators I 1 and I 2 , driven by the switching signals S 1 and S 2 in phase opposition to each other, have the function of charging and discharging, respectively, the capacitance of the driving node (gate) of the power DMOS. Fig. 2 shows the time-diagram of the gate and drain voltages of the power transistor during a turn-on phase and during a turn-off phase. Three distinct operating regions of the characteristics may be observed in both phases. During a turn-on, in a first zone I of the characteristic, the gate voltage rises from Vgs=0V to Vgs=Vth. In this region of the characteristic, there isn't any flow of current through the power transistor and the current I 1 charges the gate capacitance: Cgs+Cgd. In a second region II of the characteristic, the output power transistor starts to conduct, its drain voltage drops from Vds=H.V. to Vds=Von=Rdson*Id while the current I 1 continues to charge the gate capacitance which in this phase is given by Cgs+Cgd(Δvds/Δvgs), where the term: Cgd(ΔVds/ΔVgs) is due to the so-called Miller effect. In this zone of the characteristic, also referred to as the saturation zone, the gate voltage does not change much because the contribution to the input capacitance due to the Miller effect is preponderant in respect to the physical capacitance Cgs between gate and source of the transistor. In a third zone III, also known as the "triode operation" zone, the output power transistor is fully on, its input capacitance having been charged completely, up to the maximum driving voltage (Vcc). In this region, the drain voltage Vds does not change much. Vcc represents the overdrive voltage that serves to minimize the Rdson of the power transistor. The interval of time, during which the transistor functions in the second zone II of the characteristic curve, determines the so-called fall time (Tf) of the output signal, present on the drain node of the output transistor while the interval of time, during which the transistor functions in the zone I of the characteristics curve, defines the so-called turn-on delay time (Tphl) as referred to an input signal. The behaviour of the output DMOS in a "turn-off" phase is similar to its behaviour during a "turn-on" phase. That is, the gate capacitance discharges through three distinct phases. From a qualitative analysis of the switching phases of the power DMOS, it may be concluded that the rise time is equal to the fall time if I 1 =I 2 , while the turn-off and turn-on delays, as referred to a driving (input) signal, are different from each other. This is due to the fact that, in order to bring the DMOS to an off state (at the start of the saturation zone II) the variation of the gate voltage will be: ΔVgs 1 =Vth, while in order to pass from the so-called "triode" operation zone to the zone where the Miller effect occurs, the variation of the gate voltage will be: ΔVgs 2 =(Vcc-Vgson), where Vgson is the gate voltage at which the DMOS may be considered to be fully on. If the generators I 1 and I 2 have the same value, by being ΔVgs 2 >ΔVgs 1 , the turn-off delay time results greater than the turn-on delay time. In many practical applications of the circuit, it is often required that the output signal, i.e. the drain voltage (Vds) of the output power transistor, have a "length" identical to the "length2 of the driving signal. This requires concurrence of both conditions: Tr=Tf and Tphl=Tplh. The main aim of the present invention is to provide a driving circuit for an output power transistor, which will permit to control switching delays as well as rise and fall times. The invention is directed especially to minimize and make symmetric the delay times. These objects are fully met by the circuit of the present invention, which is characterized by the fact that an auxiliary third current generator, driven by a third signal is employed in order to provide an additional discharge current of the driving node capacitance of the output power transistor, during a first phase of the discharge process and until the output power transistor is near to reach a state of saturation. In this way, while retaining control and desirably leaving unaltered and identical to each other the rise time and the fall time (by employing for this purpose identical current generators: I 1 =I 2 ), through the action (limited in time) of a third or auxiliary current generator, the turn-off delay (Tplh) may be effectively controlled and eventually made identical to the turn-on delay time (Tphl). Figure 1 is a functional diagram of a driving circuit according to a prior art, as already described above. Figure 2 is a time diagram of the drain/source and of the gate/source voltages of the output power transistor during a turn-on phase and during a turn-off, phase in the case of a driving circuit as the one depicted in Fig. 1. Figure 3 is a functional diagram of a driving circuit made according to the present invention. Figure 4 is a time diagram of the drain/source and of the gate/source voltages of the output power transistor, that may be obtained with a driving circuit of the invention. Figure 5 is the diagram of a driving circuit according to a first embodiment of the present invention. Figure 6 is the circuit diagram of a second embodiment of a driving circuit of the present invention. A basic diagram of a driving circuit made according to the present invention is schematically depicted in Fig. 3. According to the invention, the driving circuit is provided with a third constant current generator I 3 that is controlled by a third switching signal S 3 . Basically, the invention rests on the fact that, in a turn-off phase, the current generator I 2 and I 3 are activated at the same instant, by S 2 and S 3 , for discharging the gate capacitance of the power DMOS in a certain desired time (Tplh). When the DMOS enters saturation (zone II), the third current generator I 3 is disasctivated by S 3 . Thereafter the gate capacitance continues to discharge only through the current imposed by the I 2 generator. In this way, the rise time remains defined solely by the current I 2 and therefore may be kept identical to the fall time, by making I 1 =I 2 . Conversely, the turn-off delay (Tplh) is determined by the sum of the I 2 and I 3 currents (I 2 +I 3 ), thus permitting, through an appropriate dimensioning of the "additional" discharge current I 3 , to make it identical to the turn-on delay time (Tphl) that would otherwise be shorter, for the reasons set forth before. The time-base diagrams of the gate and drain voltages of the output power DMOS transistor are shown in Fig. 4. A practical embodiment of the driving circuit of the invention may be as shown in Fig. 5. According to this embodiment, the "disactivation" of the third (auxiliary) constant current generator I 3 that provides an additional discharge current, during a first phase of a turn-off process, takes place automatically due to the drop of the gate voltage of the output power transistor (POWER DMOS) during a turn-off phase, when the power transistor ceases to function as a "triode" and enters saturation. According to this preferred embodiment, it is no longer necessary to generate a dedicated control signal S 3 , as will be better described below. The discharge of the gate capacitance of the power DMOS takes place through an amplifying stage that may be constituted by a transistor Q. The amplifying stage, that is the transistor Q, should preferably have a gain that is reasonably independent of process spread and temperature. The transistor Q is driven by a second constant current generator I' 2 , controlled by the S 2 signal. The S 2 signal may be complementary to a signal S 1 , which controls the charge of the gate capacitance during a turn-on phase, according to a known functional diagram. This second current generator I' 2 may deliver a current whose contribution to the driving node capacitance discharge current I discharge , given by β Q ·I' 2 , is equal to the current produced by the current generator I 1 . According to the present invention, to the driving current of the amplifying transistor Q, an "overdrive" current I 4 is added (which is fully injected into the base of the transistor Q because the current that flows through the resistance R can be neglected). According to the embodiment shown, such an "overdrive" current I 4 may be generated by the use of a third constant current generator I' 3 , which may be controlled by the same signal S 2 that controls the second current generator I' 2 . The third current generator I' 3 drives a current mirror that may have a certain mirroring ratio (N) and be constituted by the pair of transistors M1 and M2. In practice, the output current of the M1-M2 current mirror is entirely injected into the base of Q, because the current flowing through the resistance R is negligeable. By implementing a large mirror ratio, the current I' 3 , generated by the third constant current generator, may have a negligeable value as compared with other contributions to the discharge current (I discahrge ) of the driving node (gate) of the output power transistor (POWER DMOS). Interruption of the additional driving current I 4 to the discharge transistor Q, just before the power DMOS comes out of a "triode" operation zone (in order not to influence the rise time of the output signal), is achieved by employing a transistor M3. Preferably, the M3 transistor should have a structure similar to the power transistor used in the low-side driver stage. In this way, the transistor M3 will substantially have the same characteristics of variation of its threshold voltage due to process spread and temperature as the power transistor. In the example shown, both are DMOS transistors. During a turn-off phase, the driving node (gate) capacitance fo the power DMOS transistor will discharge initially with a current equal to the sum of the multiple contributions: I discharge =β Q I' 2 +β Q I 4 +I' 3 +I 4 +I' 2 where β Q is the current gain of the discharge transistor Q, which is assumed to be independent from process spread and temperature, and the current I 4 is given by I' 3 times the ratio of the current mirror formed by the transistors M1 and M2. Therefore, in the equation (1), the term β Q (I' 2 +I 4 ), is preponderant as compared to the other terms which may be neglected in a first approximation. The gate/source voltage present on the driving node of the power DMOS transistor will be given by: Vgs(DMOS)=Rdson(M2)*I 4 -Vgs(M3)+Vbe When Vgs(M3) equals the threshold voltage Vth(M3), the M3 transistor ceases to conduct. The Vgs(DMOS) voltage at which this occurs may be in practice around a voltage at which the power DMOS transistor may be considered as having already reached saturation. This fact may marginally influence the rise time. Nevertheless, by suitably adjusting the current I' 3 , it is possible to "accelerate" the discharge process in order to make the turn-off delay equal to the turn-on delay (Tphl=Tplh). According to an alternative embodiment of the circuit of the invention, shown in Fig. 6, it is also possible to ensure also a precise control (equalization) of the signal fronts. The problem of ensuring a turn-off of the M3 transistor at a slightly higher voltage which would coincide with a definitely occurred exit from the "triode" operation zone by the power DMOS, though not yet entered in a saturation zone, may be effectively resolved by introducing an additional transistor M4, having a size appropriate to divert to ground the current I 4 . By referring to Fig. 6, through the additional transistor M4 normally would not flow current because its source voltage is less than its gate voltage. In fact, the voltages on the node A and B of the circuit are given by the following equations: V(A)=Vgs(M3)+Vbe(Q) V(B)=Vgs(DMOS)-Vgs(M2) As the voltage on the driving node (gate) of the power DMOS transistor decreases, also the V(B) voltage decreases, while the V(A) voltage remains constant because the current I 4 is constant. When the following condition occurs: V(B)≤V(A)-Vth the transistor M4 turns-on, thus diverting part of the I 4 current that flows through the M3 transistor. The voltage at which the transistor M4 is fully on and therefore capable of drawing the whole current I 4 , by diverting it directly to ground, is given by the following relation: (Vgs(M4)-Vth(M4))= I 4 /(k*W/L) = =Vgs(M3)+Vbe(Q)-[Vgs(DMOS)-Vgs(M1)] By knowing the value of the gate voltage of the power DMOS transistor that corresponds to the exit from the "triode" operation zone, and having established the Vgs(M1) from the value of the current I' 3 , and having designed a certain area ratio between M1 and M2, it is possible to determine the so-called "aspect ratio" (W/L) (width/length of the channel) of the transistor M4 from the above equation. A correct dimensioning of the M4 transistor will ensure a precise cut-off instant of the M3 transistor, just before the power DMOS enters saturation, during a turn-off phase. In practice, the driving circuit of the invention permits to separately set the charge and discharge current levels of the gate of the power transistor in order to obtain controlled rise and fall times, as well as to adjust the turn-off delay time and eventually make it equal to the turn-on delay time, by suitably adjusting the current I' 3 .

Claims: A control circuit for switching toward ground a load through a power transistor comprising a first current generator (I 1 ) controlled by a first switching signal (S 1 ) producing a current for charging the capacitance of the driving node of said power transistor, a second current generator, controlled by a complementary signal (S 2 ) of that first switching signal (S 1 ), and producing a current for discharging the driving node capacitance of said power transistor, a third current generator, controlled by a third switching signal (S 3 ), and capable of producing an additional current for discharging said capacitance during a first phase of a turn-off process, until said power transistor has reached a near saturation condition, characterized by comprising further: a capacitance discharge current amplifier (Q) functionally connected between the driving node of said power transistor and a ground node of the circuit and driven by a current that is the sum of a first current (I' 2 ), produced by said second current generator controlled by said second signal (S 2 ), and of an additional driving current (I 4 ) that is produced through an output branch of a current mirror (M1, M2), functionally connected between said driving node of the power transistor and ground and driven by said third current generator (I' 3 ), which is controlled by said third switching signal (S 3 ) being a replica of said second signal (S 2 ) and means (M3) capable of interrupting said additional driving current (I 4 ) of said capacitance discharge current amplifier (Q) when the voltage on said driving node of the power transistor drops to a value close to that of saturation of the power transistor. A circuit as defined in claim 1, characterized by the fact that said means capable of interrupting said additional current are constituted by a diode configured transistor (M3) connected to the output branch of said current mirror (M1, M2). A circuit according to claim 2, wherein said power transistor and said diode-configured transistor (M3) are both DMOS transistors. A control circuit according to claim 2, characterized by comprising a transistor (M4) functionally connected between an output node of said current mirror (M1, M2) and ground and having a control terminal which is connected in common with the control terminals of a pair of transistors (M1, M2) that form said current mirror, said transistor (M4) having a size as to turn-on when the voltage on the driving node of the power transistor drops to a preset value, thus diverting to ground the output current (I 4 ) of said current mirror (M1, M2).

Inventors: ALZATI ANGELO, BONTEMPO GREGORIO, MILAZZO PATRIZIA, ALZATI, ANGELO, BONTEMPO, GREGORIO, MILAZZO, PATRIZIA
Applicants: CONS RIC MICROELETTRONICA, ST MICROELECTRONICS SRL, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H03K17
IPC codes: H03K17