A pipeline computer with scoreboard

Abstract: A pipeline computer having functions of scoreboard control includes: a dependency detection unit provided in the scoreboard for detecting dependency of data between a preceding instruction and a following instruction, the preceding instruction being an instruction which executes precedingly, and the following instruction being an instruction which executes followingly; and an ensuring unit for the dependency of data detected by the detection unit based on an interlock operation at pipeline processes when an interruption occurs; wherein, an interruption instruction waits for completion of an instruction which already starts to execute prior to the interruption instruction, and all register bits on the scoreboard indicating the in use state are reset to the not used state to ensure the dependency of data.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline computer, and more particularly, it relates to a control method for a scoreboard in a pipeline computer. 2. Description of the Related Art In a pipeline computer, a scoreboard (or SCB) is known as a method for managing and controlling the mutual dependency of operands which are used in a calculation. As one example, the scoreboard is used for an interference detection in the general registers as explained in detail below. That is, a scoreboard storage means is provided for indicating in use or not used state of each general register. When executing an instruction which writes data into a general register (i. e., write instruction), a bit in the scoreboard corresponding to the number of the register is set to the setting state to indicate that a write operation is being executed. Further, when an instruction writes a result of calculation into a general register, a bit in the scoreboard corresponding to the number of the register, is set to the reset state to indicate that the write operation has been completed. In this case, in order to confirm whether or not the rewriting of the bit has been executed by an instruction which a source operand executes precedingly, an instruction which follows the preceding instruction (below, following instruction) reads the bit corresponding to the register number which indicates the source operand. If the bit is set, since it shows that the rewriting based on the preceding instruction is not completed, the following instruction waits for the start of a calculation. If the bit on the scoreboard is reset, since the preceding instruction does not rewrite the source operand, the following instruction can start the calculation. Motorola Technical Developments, vol 8, no. 1, October 1988, Schaumburg IL US, pages 43-44, Talgam, "Shadow Scoreboard and Implementation" discloses a pipeline computer according to the preamble of claim 1. According to this prior art, when context is switched to the exception or interrupt handler context, no instructions of the current context may complete, so the scoreboard seen by the new context must indicate all-ready. JP-A-3206962 by the present applicant discloses that when an access exception occurs, an access error signal is outputted from an error signal output means and the contents of the register scoreboard are cleared. According to the present invention, there is provided a pipeline computer comprising: a plurality of registers for use by instructions executed in pipeline processes of the pipeline computer; and a scoreboard for monitoring use of the registers and having a plurality of scoreboard bits, each of which can be set or reset to indicate an in-use state or a not-used state of one of said registers, respectively; characterised by: a data dependency detection means provided in the scoreboard for detecting a data dependency between a preceding instruction and a following instruction; an interruption control means for ensuring the data dependency detected by the detection means based on an interlock operation of the pipeline processes, by executing an interruption program after an interruption has occurred; and means for performing a non-serialized process composed of non-serialized instructions in which, when an instruction has already started to execute prior to the interruption instruction, the interruption instruction starts to execute without waiting for completion of a preceding instruction; wherein, when an interruption is detected, execution of the interruption program waits for completion of all instructions except for said non-serialized instructions, and execution of said non-serialized instructions is continued; all scoreboard bits are reset to indicate the not-used state; and after the scoreboard bits are reset to the not-used state, all scoreboard bits corresponding to registers used by said non-serialized instructions to execute write operations are set to the in-use state. An embodiment of the present invention can provide a pipeline computer enabling correct setting/resetting of bits in a scoreboard when an interruption occurs during the execution of a preceding instruction, and enabling an improvement of the register interference control without reducing the response characteristics of the interruption. In the drawings: Figure 1 is an essential structural view of a pipe line computer using a scoreboard of the present invention; Figure 2 shows one example of a scoreboard according to the present invention; Figure 3 is a block diagram of a pipeline control circuit according to the present invention; Figure 4 is a block diagram of a scoreboard having all bits resetting function; Figure 5 shows one example of an address alignment exception detection circuit according to the present invention; Figure 6 shows one example of a calculation block and a register file according to the present invention; Figure 7 shows one example of a state transient circuit according to the present invention; Figure 8 shows one example of a scoreboard correction circuit according to the present invention; Figure 9 shows another example of a calculation block and a register file according to the present invention; Figure 10 is an essential structural view of a pipe line computer using a scoreboard of another aspect of the present invention; Figure 11 shows one example of a cache block according to the present invention; Figure 12 shows another example of a scoreboard correction circuit according to the present invention; Figure 13 shows another example of a scoreboard according to the present invention; Figure 14 shows another example of a state transient circuit according to the present invention; Figure 15 shows still another example of a calculation block and a register file according to the present invention; Figure 16 is an explanatory view for preceding/following instructions; Figure 17 is an explanatory view for preceding/following instructions when the following instruction does not wait for completion of the preceding instruction; Figure 18 is an explanatory view of an erroneous scoreboard caused by an interruption; and Figure 19 is an explanatory view of a pipeline computer not using an asynchronous execution. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 16 is an explanatory view of preceding/following instructions. This is in the case that the following instruction waits for the completion of the preceding instruction. According to this example, the following instruction can read correct data. In order to confirm whether or not the rewriting of the bit is executed by the instruction which a write operand executes precedingly, the following instruction reads the bit corresponding to the register number indicating the read operand. If the bit is set, since it shows that the rewriting is not completed by the preceding instruction, the following instruction waits to the start the calculation. If the bit on the scoreboard is reset, since the instruction which executes precedingly does not rewrite the write operand, the following instruction can start the execution of the calculation. Figure 17 is an explanatory view of another example of the preceding/following instruction. This is in the case that the following instruction does not wait for the completion of the preceding instruction. This drawing explains that, if the following instruction does not wait for completion of the writing, the order of writing may be not ensured and the mutual relationship between data may be not processed correctly. In this example, although the third ADD instruction expects to read the result of the second ADD instruction, the result of the LOAD instruction written into the same register is read after completion of the write by the second ADD instruction. This process results in an error. The setting of the bit in the scoreboard means that a value of the register cannot be read (or, cannot be written). In the case of almost all basic instructions, for example, an adding instruction, the E-stage is completed during one cycle (1τ), and the following instruction can read the result of the E-stage as the source operand based on a bypass function. Further, an instruction in which the E-stage is completed within 1τ, has no possibility of an erroneous operation such as the following instruction passes the preceding instruction as shown in Fig. 17. Accordingly, for the basic instruction, such as the adding instruction (i. e., the instruction having the shortest execution time, such that it can be executed during one cycle and the E-stage is executed during 1τ.), the mutual interference of data can be avoided without setting/resetting of the scoreboard. This is the reason that the values of the scoreboard are not changed in the adding instructions in Figs. 16 and 17. The process of the scoreboard when an interruption occurs will be explained in detail below. In the example shown in Fig. 17, the explanation will be given of the case that, in the ADD instruction, an overflow interruption is generated at the E-stage during execution of the LOAD instruction. Since this interruption is executed after the result is written into the register (i. e., after completion of the instruction), the preceding LOAD instruction is completed and the execution result must be ensured. For example, there are two methods, i. e., (1) an interruption program is executed after completion of the LOAD instruction, (2) the interruption program is executed without waiting for completion of the LOAD instruction. When accessing (reading/writing) the register which is rewritten by the LOAD instruction, the register is accessed by the method using the scoreboard after completion of the LOAD instruction. However, there are problems in above two methods (1) and (2) in that correct operations cannot be ensured as explained in detail below. Figure 18 shows the case that the scoreboard becomes incorrect due to the interruption. In Fig. 18, a memory address of the LOAD instruction generates an address alignment exception (this means that, for example, although the read data is formed of four bytes, the address cannot be divided by four bytes, i. e., the address is not formed from an integer times the data size). As explained above, since the scoreboard is set at the front half of the E-stage, the scoreboard is set although the instruction is canceled due to the interruption. In this state, when the gr4 is accessed, the access enters the state which waits for the write into the register so that the system enters a hang-up state. That is, a contradiction occurs in the scoreboard due to the interruption so that it is impossible to correctly control register interference. The object of the present invention lies in a pipeline computer in which a scoreboard can set correctly even if an interruption occurs so that it is possible to realize normal register interference, and in which the response characteristics of the interruption is not reduced when a lot of time is required for the write into the register. The present invention will be explained in detail hereinafter, following a discussion of First and Second Solution Methods (not according to the invention) by way of background explanation. First Solution Method In a first solution, all bits on scoreboard are reset when the interruption occurs, the scoreboard which is set in error is reset, and the execution of next instruction (i. e., execution of the interruption program) is started after all instructions of which the execution is started prior to the interruption are completed. Second Solution Method All register numbers which set the scoreboard in error are held, the scoreboard which is set in error when the interruption occurs is reset, and the execution of next instruction (interruption program) is started after all instructions in which the execution is started prior to the interruption are completed. In this case, the following is the reason for waiting for completion of all instruction which the execution is started prior to the interruption. That is, even if a privilege/user mode of the processor is changed in the interruption, although it is necessary that the operation is the same as that of an original mode, for example, the result of the instruction issued by the user mode must be written into the register of the user mode. However, if it is in the case which does not wait for completion of all instructions which the execution is started prior to the interruption, the control for the above process becomes complicated. New problems and guides for solution thereof will be explained in detail below. The processes of the scoreboard when the interruption occurs, as explained in the first solution, are to wait for completion of all instructions which execute the write operation, and then to reset all bits of the scoreboard so that it is possible to perform the control without contradiction. Only the process is to wait for completion of all instructions, the scoreboard is kept to "set" based on the instruction which is canceled by the interruption or the instruction in which the write is inhibited by the interruption. Accordingly, all bits of the scoreboard are reset. Further, if the process is to wait for completion of all instructions which perform the write operation when the interruption occurs, the response characteristics of the interruption become worse in the following cases. That is, this is in the case of the structure connecting a co-processor which executes a vector process. When the instructions are filled in an instruction queue of the co-processor, and when an instruction for rewriting the general register is filled in the end queue, it is possible to start the interruption after execution of several instructions of the vector processes which necessitate a lot of execution time. For example, if a length of the vector is 500, and if five instructions are stored in the queue, the interruption process is started after about 2500τ. As explained above, since the response characteristics of the interruption become worse, in the co-processor which executes the vector process, it is necessary to execute the interruption without waiting for the write operation to the register. However, in order to ensure the mutual dependency for data, it is necessary to control so as to access the register after completion of the instruction by the co-processor co-processor when the register which is rewritten by the instruction is accessed (read/written). Accordingly, it is necessary that the register which is rewritten by the co-processor is not used in the interruption (and not used in a save) to realize the high speed interruption. Third Solution of the Present Invention In the second solution explained above, the control is performed so as to ensure the normality of the scoreboard without a reset operation of all scoreboards when the interruption occurs. That is, the number of the register which sets the erroneous scoreboard, the scoreboard which is set in error when the interruption occurs is reset, and the execution of next instruction (interruption program) is started after completion of all instructions except for the instruction to the co-processor which starts prior to the interruption. Accordingly, there is no new problem in the second solution, such as a lot of waiting time for the vector instruction is required. On the contrary, in the first solution, although it is necessary to take countermeasures against a lot of waiting time for the vector instruction, this can be solved by a marker means. The preferred embodiments are explained in detail below along with the operation of each stage. (Instruction Decode Stage) First, an instruction is decoded to confirm that it is an instruction which necessitates update of the scoreboard except for read from the register. Further, the cause of the interruption is detected by decoding the instruction. The result of decode, i. e., the cause of the interruption is held in a pipeline-tag to use in the following stage. Next, the bits in the scoreboard corresponding to the write register number are detected. If the bits are set on the scoreboard, the instructions are interlocked in a decode stage. Further, the bits on the scoreboard corresponding to the read register number are detected. (Calculation Stage) First, an instruction, which executes the calculation stage, indicates the instruction which necessitates the update of the scoreboard except for execution of the calculation, the bits corresponding to the write register number are set. The cause of the interruption is detected from the result of the calculation. When there are any interruption causes, the start of the interruption of a hardware is instructed to the interruption control circuit. In the case of the interruption which must stop the execution, for example, the interruption of a priviledge instruction offence, the control is performed as the register write signal is inhibited, and as the value of the register is not changed. (Write Stage) Except for the write process which writes the result of the calculation stage into the register, when the instruction which executes the write stage indicates the instruction which necessitates the update of the scoreboard, the bits on the scoreboard corresponding to the write register number are reset. The Operation of the Data Processing Apparatus Figure 6 is a block diagram of a register file and a calculation block. The block includes an ALU which executes arithmetic calculation and a logical calculation; an integer-multiplyer; a memory access unit, and a data cache block for a load-store instruction. This block executes the read of the source operand of the calculation, and the write of the result of the calculation. In this case, although clocks are not input in a part of the registers to simplify the drawing, in actuality, the clocks are input to all registers, and this block is formed of the complete synchronous circuit based on clocks. When executing the instruction which is calculated in the ALU, the result is obtained in one calculation stage. The selection circuit before the register file selects the output of the ALU (see, the upper most signal in Fig. 6), the result of the ALU is written into the register file in accordance with a write register address and a write control signal which are held in the pipeline resister E-W-ADR and E-W-E. When executing an integer multiplication instruction, the result is obtained in a plurality of calculation stages. Accordingly, the write operation to the register file is controlled by the integer multiplication after completion of the calculation. A selection circuit selects the output of the integer multiplication circuit and the integer multiplication control circuit, and the result of the integer multiplication is written into the register file in accordance with the write register address and the write control signal which are generated in the integer multiplication control circuit. When executing a memory access instruction, it is necessary to execute a data transfer from an external main memory when mis-hit occurs in the cache in the execution of a load instruction. Accordingly, the write operation to the register file is controlled when a hit to the cache is confirmed, or when the data transfer from the external main memory is completed. The selection circuit selects the output of the cache block (see, the lower most signal in the drawing), and the result of the load instruction is written into the register file in accordance with the write register address and the write control signal which are generated in the cache control circuit. When the instruction which is calculated in the ALU executes in the E-stage, and an interruption having a inhibition type is detected, the signal PIPE-CANCEL is asserted and the write operation is inhibited. In this case, since the instruction which executes prior to the interruption is not inhibited, the preceding instruction in not dependent on the signal PIPE-CANCEL. When executing an integer multiplication instruction and the memory access instruction, and a interruption having inhibition type is detected, the signal PIPE-CANCEL is asserted and the write operation is inhibited in each control circuit. The operation of the scoreboard will be explained for the pipeline processing apparatus (data processing apparatus) shown in Fig. 1. The scoreboard is read in accordance with the result of the decode of the instruction so that an operand register number (SRC-REG-ADR0, SRC-REG-ADR1) and a write operand register number (DIST-REG-ADR) can be obtained. The signals SRC-REG-ADR0 and SRC-REG-ADR1 are input to the read register address of the register file GR to read the source operand. The source operand which is read from the general register is held in the operand register OP1 and OP2 (see, Fig. 6). The output of the operand register is input to the calculator ALU to execute the calculation. The result of the calculation, the write register number, and the write control number (DIST-REG-WE) are controlled in accordance with the kind of the calculation including LOAD instruction, and the result of the calculation are written into the general resister GR. When there is no mutual interference of the data, the above operations are executed. When there is the mutual interference, the operations are as follows. Figure 2 is a structural view of the scoreboard according to an embodiment of the present invention. Figure 3 is one example of a pipeline control circuit. The read operand register number (SRC-REG-ADR0, SRC-REG-ADR1), the write operand register number (DIST-REG-ADR) are input to the write register detection ports (RD0-CHK, RD1-CHK, and WR-CHK). The above detection ports (RD0-CHK, RD1-CHK, and WR-CHK) are used as selection signals which select the registers indicating the in use or the not used state within the scoreboard. The selected signals (SRC0-REG-BUSY, SRC1-REG-BUSY, and WRITE-REG-BUSY) are input to the pipeline control circuit (see, Fig. 3), and used for determining whether or not the decode stage is interlocked. If any one of signals (SRC0-REG-BUSY, SRC1-REG-BUSY and WRITE-REG-BUSY) indicate an in use state, the signal D-STAGE-RELEASE is inhibited. The signal D-STAGE-RELEASE is the control signal indicating completion of the decode stage and progress to the execution stage. Accordingly, if any one of signals (SRC0-REG-BUSY, SRC1-REG-BUSY and WRITE-REG-BUSY) indicate an in use state, these signals are interlocked in the decode stage, and the process waits for the release of the register which will be used next. When interlocking in the above state, the scoreboard register indicating an in use or a not used state is reset (indicates "not used") when the preceding instruction is completed. When the register number coincides with the register number which intends to use next, the signals (SRC0-REG-BUSY, SRC1-REG-BUSY and WRITE-REG-BUSY) are negated, and the inhibition of the signal D-STAGE-RELEASE is released and shifted to the execution stage. As explained above, the source operand waits for the rewriting by the preceding instruction, and it is possible to realize the read of the most recent data. Further, an order of the write is ensured by executing after completion of the write by the preceding instruction. The setting to the scoreboard is executed to the bit of the scoreboard which is indicated by the write operand register number DIST-REG-ADR when the mutual interference is solved (the signal D-STAGE-RELEASE is asserted). The resetting of the scoreboard is executed to the bit of the scoreboard of the same register in the same timing as the write control of the general register GR of the calculation block. The Operation When the Interruption Occurs in the First Method In the first method, all scoreboards are reset when the interruption occurs so that it is possible to clear the scoreboard which is set in error. Further, the next execution for the instruction (interruption program) is started after completion of all instructions in which the execution is started prior to the interruption. Figure 4 is a block diagram of the scoreboard having an all reset function according to the present invention. This embodiment shows the scoreboard circuit enabling resetting of all bits of the scoreboard. Since the signals SCB-RESET-ALL are processed by an OR operation regarding the reset inputs of all scoreboards, when the signals SCB-RESET-ALL "1", all bits of the scoreboard are reset. The schematic block diagram of the interruption detection circuit is shown in Fig. 1. In this circuit, the detection of a non-definition instruction is executed by an instruction decoder, the timing of the execution is matched by the resister, the cause of the interruption is detected by the OR operation with the cause of the interruption which is detected in the E-stage. In this example, since all interruptions inhibit the instruction, the interruption detection signal is used as an inhibition signal PIPE-CANCEL which inhibits a write control signal of the register. When the calculation enters an overflow/underflow state, the write operation to the register is not inhibited since the instruction is a completion type. Figure 5 is one example of an address alignment exception detection circuit. It is obvious that the detection of the non-definition instruction can be formed of an OR circuit which executes OR operation regarding patterns of all non-definition codes. One example of the cause of the interruption which is detected in the E-stage is a detection circuit of the address alignment exception for the memory access instruction. Figure 7 is one example of a state transient circuit which waits for completion of all instructions of which execution is started prior to the interruption when the interruption occurs. In an initial state, the register having the state S0 is set to 1, and others are set to "0". That is, this is called the state S0 (S0-STATE). When the interruption occurs, the signal D-E-EXCP becomes "1", the register is shifted from the state S0 to S1. As shown in Fig. 3, the signal D-STAGE-RELEASE is not asserted except for the state S0, and the execution of the instruction is inhibited. In the state S1, both signals IMLT-SEQ indicating execution of the multiplication instruction and the signal NEW-SEQ indicating execution of the instruction of the memory/cache operation, for example, LOAD/STORE instruction, are input to the OR circuit. The state S1 is held until these signals indicate completion of execution, and the register is shifted to the state S2 after completion. In the state S2, the value in a program counter PC is transferred to an interruption save register OPC so as to allow the instruction which is interrupted to be retracted. In the state S3, the address of the destination of the interruption is transferred to the program counter, and the restart of the fetch instruction is instructed in the state S4. The register is shifted to the state S0 after the state S4 is completed, and the execution of the interruption program is started when the instruction fetch circuit completes the fetch of the instruction. All bits on the scoreboard can be reset at any time except for the state S0. In this example, the signal SCB-RESET-ALL is set to "1" in the state S4, and all bits of the scoreboard are reset. The Operation When the Interruption Occurs in the Second Method In the second method, the scoreboard which is set in error when the interruption occurs is reset, and the execution of the next instruction of the interruption program is started after completion of all instructions which started execution prior to the interruption. Figure 8 is one example of a scoreboard correction circuit. This circuit includes a register to hold the locations of the scoreboard which are set in error, and a selector circuit before the scoreboard resetting port. Further, this circuit includes a register SCB-SET-ADR-REG to hold the register number which is set in error, and a register SCB-SET-CANCELED to hold erroneous bits which are set in error due to canceling of the instruction. These registers hold the set address and the scoreboard setting signal D-WE in the same timing as the scoreboard setting. If there is no interruption having the inhibition type, the signal D-STAGE-RELEASE is asserted based on the pipeline control circuit. That is, it is clarified that the scoreboard is not set in error. Accordingly, the signal SCB-SET-CANCELED is reset by the signal E-STAGE-RELEASE. In the pipeline computer, although the setting and resetting operation occur simultaneously, the setting operation is set preferentially. When an interruption of the inhibition type occurs, the signal E-STAGE-RELEASE is negated. Accordingly, since the signal SCB-SET-CANCELED is not reset, it is possible to recognise that the scoreboard which is set in the last stage is in error. When the interruption of the completion type occurs, even if the scoreboard is set, the scoreboard is set correctly since it is completed by rewriting the general register. As explained above, it is possible to solve the problem in the case that the instruction which sets the scoreboard is canceled in the E-stage. However, in the LOAD/STORE instruction, the following cases may occur that the interruption occurs after execution in the E-stage, and the instruction is canceled. This is explained with reference to Fig. 16. The operand address is calculated in the E-stage, and the cache, the cache tag and the TLB are searched in the C1 stage. Further, the TLB may be checked and a "page invalid exception" may be detected in the C2 stage. In this case, since the signal SCB-SET-CANCELED is reset by the signal E-STAGE-RELEASE, it is impossible to reset the scoreboard by using the signal SCB-SET-CANCELED. The scoreboard is reset based on the register write information in which the cache block holds. The cache block holds the register write information so as to be able to execute the following instruction by the LOAD instruction. Figure 9 shows another example of the calculation block and register file, and Figure 10 shows an essential structural view of the pipeline processing apparatus. When the interruption does not occur, the rewriting of the general register and the reset of the scoreboard are simultaneously executed in accordance with the register write information. When the interruption occurs, only the reset of the scoreboard is executed in accordance with the register write information. Accordingly, although the write control signal to the general register is the same signal as the reset signal to the scoreboard in the conventional art, these signals necessitate separately in the present invention. Figure 9 shows a signal SCB-WE, and Figure 10 shows that the signal SCB-WE controls the reset of the scoreboard. The signal SCB-WE is generated by a cache block, and one example of the cache block is shown in Fig. 11. In Fig. 9, the selector which is provided before the signal SCB-WE executes the same operation as explained previously. In this case, when the selector selects the ALU, this selector can output any value. This is because, since the instruction using the ALU does not set the scoreboard, there is no problem in the fact that the value "0" is output and the the reset is not performed. In this example, when the integer calculator is selected, the same signal as the write signal of the general register is output. This is because the circuit is designed as the interruption after the E-stage, such as load instruction, is not contained in this example. Figure 11 shows one example of a cache block. When a signal TLB-HIT is set to "1" (i. e., a logical address registered in a TLB coincides with a signal E-OP-ADR); when a page invalid signal CHE-HIT is set to "1" (i. e., a physical address registered in the CHE-TAG coincide with the physical address registered in the TLB); when a page invalid (PI) bit of the TLB is set to "0" (i. e., this indicates that a page does not exist in an actual memory); and when the instruction is the LOAD instruction, the LOAD instruction is hitted to the cache and the data is written from the cache to the general register GR. In this case, the signal CHE-GR-WE is set to "1" and the signal CHE-SCB-WE is also set to "1", further, the reset of the scoreboard is executed with the write of data to the general register. When the signal TLB-HIT is set to "1" (i. e., the logical address registered in the TLB coincides with the signal E-OP-ADR); when the PI bit of the TLB is set to "1" (i. e., this indicates that the page does not exist in the actual memory); and when the instruction is the LOAD instruction, an exception of absence of the page occurs. In this case, since the LOAD instruction must be inhibited, the signal CHE-GR-WE is set to "1" in order not to write data from the cache to the general register GR. However, the signal CHE-SCB-WE is set to "1" in order to release the scoreboard when the register is in use. Figure 7 shows one example of a state transition circuit. This circuit waits for completion of all instructions in which the execution is started prior to the interruption when the interruption occurs (i. e., the same as the first solution). In the initial state, only the register of the state S0 is "1" and the others are "0". This is called the S0 state. When the interruption occurs, the signal D-E-EXCP becomes "1" and the state is changed from the S0 to S1. The signal D-STAGE-RELEASE is not asserted except for the state S0, and the execution of the instruction is inhibited. In the state S1, two signals, i. e., the signal (IMLT-SEQ) indicating the execution of the multiplication instruction, and the signal (MEM-SEQ) indicating the execution of the instruction for the memory/cache, for example, LOAD/STORE instruction, are input to the OR gate. This circuit holds the state S1 until these signals indicate completion of the execution, and the state is shifted to the state S2 after completion of the execution. In the state S2, the value of the program counter PC is transferred to the interruption save register OPC so as to restart the process of the instruction which is interrupted. In the state S3, the address of the destination of the interruption is transferred to the program counter PC, and in the state S4, restart of the fetch of the instruction is instructed. The state is shifted to the state S0 after the state S4. When the instruction fetch circuit completes the fetch of the instruction, the execution of the interruption program is started. Further, it is necessary to provide reset ports which are used for the resetting of the scoreboard bit which is set in error. The reset port may be provided independently, or may wait for completion of all instructions which started the execution prior to the interruption before reset operation. Accordingly, since the reset port of the scoreboard is not used after the above process, the selector is provided before stage of the port in order to reset the scoreboard which is set in error. The selector is controlled by the signal SCB-MODIFY which is previously explained. When the signal SCB-MODIFY is set to "1", the signals SCB-SET-ADR-REG and SCB-SET-CANCELED are selected. The reset of the bits of the scoreboard which are set in error can be executed at any time after the state S2. In this example, in the state S4, the signal SCB-MODIFY is set to "1" in order to reset the scoreboard bits which are set in error. Further, at the same time, the signal SCB-SET-CANCELED is reset by the signal SCB-MODIFY in order to indicate that there is a scoreboard which is set in error. Although this example shows the cache block, when a co-processor interface generates an exception at a late timing, it is possible to provide a method of using the register write information in which a co-processor interface holds and of resetting the scoreboard. Figure 19 shows a pipeline without an asynchronous execution. The pipeline structure in which the following instruction does not start the execution (i. e., asynchronous execution) during execution of the LOAD instruction is explained using a model R3000 of MIPS. This pipeline always uses the C-stage in the case of the instruction, such as an ADD instruction, which the cache access stage is not necessary. In the above example, when the first LOAD instruction detects the exception in the C-stage, two scoreboard "bit" are set in error. Accordingly, two sets of the registers are necessary for storing the scoreboard in error. Figure 12 shows one example of this circuit. A and B denote the register SCB-SET-ADR-REG, and C and D denote the register SCB-SET-CANCELED. The register A stores the location which is finally set in the scoreboard, and the register B stores the location just before the above in the scoreboard. The register C holds whether or not the instruction executing the E-stage sets the scoreboard. Accordingly, the register C is set when there is the write operation to the general register, and the register C is reset when the E-stage is completed. Further, when the scoreboard is reset by an interruption (see, the signal S3-STAGE), at the same time, the register C is reset. The register D holds whether or not the instruction executing the C-stage sets the scoreboard. Accordingly, when the instruction which executes in the E-stage is the instruction which sets the scoreboard, and when the instruction completes the E-stage, the register D is set and it is reset when the C-stage is completed. Further, when the scoreboard is reset in the interruption (see, the signal SCB-MODIFY of Fig. 7), and at the same time, the register C is reset. In order to return from the scoreboard having maximum two errors to the original scoreboard, the selector which is provided before the scoreboard has three inputs, selects the registers CB-SEY-ADR-REG (A) and SDB-SET-CANCELED (C), and resets the scoreboard which contradicts because the instruction executing the E-stage sets the scoreboard and this instruction is canceled. Further, the selector selects the registers CB-SEY-ADR-REG (B) and SCB-SET-CANCELED (D) by using the signals SCB-MODIFY to reset the scoreboard which contradicts based on the same reason as above. Figure 15 shows another example of the calculation block and register file. This drawing shows the calculation block and register file substituting the integer multiplication control circuit of Fig. 9 for the co-processor control circuit. In Fig. 15, the data cache block executes the load/store instruction for memory access. The co-processor is physically mounted on a board as a different LSI from the calculation block. The register file reads the source operand, such as calculation, and writes the result of the calculation. When executing the instruction which calculates in the ALU, the result of the calculation is generated in one calculation stage. In this calculation stage, the selection circuit which is provided before the register file selects the output of the ALU, the result of the ALU is written into the register file in the write stage by using the write register address which is held in the pipeline register (E-W-ADR, E-WE) and the write control signal. When executing the instruction for the co-processor, the result of the instruction is generated after plural calculation stages. The co-processor which writes data into the register file is controlled by the co-processor control unit after completion of the calculation. The selecting circuit selects the output between the co-processor and the co-processor control circuit, the result of the calculation of the co-processor writes into the register file by using write register address which is held in the co-processor control circuit and the write control signal which is generated by decoding the co-processor instruction. When a write register address holding circuit is shared with another calculator, and when the co-processor instruction which executes the write to the register operates (or, is entered into a queue of the co-processor instructions), the write register address holding circuit (not shown) is provided independently in the co-processor control unit since the following instruction cannot be executed. When executing the memory access instruction, and when the cache is mis-hitted in the execution of the load-instruction, it is necessary to perform data transfer from the main storage. Accordingly, the write operation to the register file is controlled after confirmation of a cache hit or completion of data transfer from the main storage. The selecting circuit selects the output of the cache block (lower portion of the drawing), the result of the load instruction is written into the register file in accordance with the write register address and the write control signal which are generated by the cache control circuit. When the interruption having an inhibit type is detected when the instruction which calculates in the ALU executes in the E-stage, the signal PIPE-CANCEL is asserted and the write operation is inhibited. In this case, since the instruction which executes prior to the interruption is not inhibited, this instruction is not dependent on the signal PIPE-CANCEL. When the memory access instruction detects an interruption having the inhibit type during execution of the instruction for the memory access, the signal PIPE-CANCEL is asserted and the write by the following instruction is inhibited. Further, the write by the memory access instruction itself is inhibited in the memory access control circuit. Figure 13 shows a structural view of another example of a scoreboard. The read operand register number (SRC-REG-ADR0, SRC-REG-ADR1) and the write operand register number (DIST-REG-ADR) are input to the read/write register detection port (RD0-CHK, RD1-CHK, WR-CHK). Further, the explanation is given to another example of the operation when the interruption occurs. By resetting all scoreboards when the interruption occurs, the scoreboard which is set in error is reset, and the execution of the next instruction (i. e., interruption program) is started after completion of all instructions except for the co-processor which starts the execution prior to the interruption. In the scoreboard circuit of Fig. 13, it is possible to reset all bits of the scoreboard. The signal SCB-ALL-RESET is input to the OR circuit, and the output of the OR circuit is input to the scoreboard register. Accordingly, when the signal SLB-ALL-RESET is set to "1", all bits of the scoreboard are reset. The instruction decoder performs detection of non-definition instruction. The decoder obtains the timing by matching with the register, and detects the cause of the interruption by performing OR operation with the cause of the interruption detected in the E-stage. In this example, since all interruptions inhibit the instruction, the interruption detection signal is used as the inhibition signal PIPE-CANCEL which inhibits the write control signal to the register. In the case of the overflow/underflow state of the calculation, the write to the register is not inhibited since it is a completion type interruption (it is the type having the function for writing the result of the overflow into the register). As explained above, it is obvious that the detection circuit for non-definition instructions can be structured by OR circuits which perform an OR operation on the code of the non-definition instructions. As one example of the cause of the interruption which is detected in the E-stage, the alignment exception detection circuit for the memory access instruction is shown in Fig. 5. Figure 14 shows another example of the state transient circuit. This circuit has the function to wait for completion of all instructions except for a co-processor instruction which starts executing prior to the interruption. In the initial state, only the register of the state S0 is "1", and any other is "0". When the interruption occurs, the signal D-E-EXCP becomes "1", the register changes from the state S0 to the state S1. As shown in Fig. 5, the signal D-STAGE-RELEASE is not asserted except at the state S0, and the execution of the instruction is inhibited. In the state S1, the register receives the signal IMT-SEQ indicating the on execution of the multiplication instruction and the signal MEM-SEQ indicating on execution of the instruction of the memory/cache operation, such as the LOAD/STORE instruction, holds the state S1 until these signals indicate completion of the execution, and shifts to the state S2 after completion of the execution. In the state S1, the signal SCB-ALL-RESET is "1" so that all bits of the scoreboard are reset. In the state S2, the contents of the program counter PC are transferred to the interruption save register OPC so as to restart the instruction which is interrupted. Further, the scoreboard is set by using the write address and the write control signal which are held in the processor control unit. In this embodiment, the same signal lines as the normal write are used for the write address and the write control signal. Further, the selector switches between the signal WR-SET and the write address signal WR-RES and between the signals D-WE and the signal W-WE. Since the signal SCB-RESTORE is asserted in the state S2, the selector SEL can set itself by using the write address and the write control signal which are sent from the co-processor control unit. At that time, in order not to simultaneously reset these signals, either the set/reset register is structured so as to have "priority to setting" (i.e., priority is given to the setting operation), or the signal inverted from the SCB-RESTORE and the output of the decoder are gated by the AND circuit so as not to assert the output of the decoder (4 to 16) of the reset side. In the state S3, the address of the destination of the interruption is transferred to the program counter PC, and in the state S4, the restart of the fetch of the instruction is instructed. The register shifts to the state S0 after the state S4, and when the instruction fetch circuit completes the fetch of the instruction, the execution of the instruction of the interruption program is started. It is necessary to perform the resetting of the scoreboard in correspondence to the number of the write register. In this example, although only one write register is provided, when two registers are provided for reserving the write operation, the state S3 is used and the register address and the write control signal are transferred in the state S3. Further, by using the selector for switching the state S3, the resetting of the scoreboard is performed.

Claims: A pipeline computer comprising: a plurality of registers (GR, OP1, OP2) for use by instructions executed in pipeline processes of the pipeline computer; and a scoreboard (SCB) for monitoring use of the registers and having a plurality of scoreboard bits, each of which can be set or reset to indicate an in-use state or a not-used state of one of said registers, respectively; a data dependency detection means provided in the scoreboard (SCB) for detecting a data dependency between a preceding instruction and a following instruction; an interruption control means for ensuring the data dependency detected by the detection means based on an interlock operation of the pipeline processes, by executing an interruption program after an interruption has occurred; characterized by: means (ALU) for performing a non-serialized process composed of non-serialized instructions in which, when an instruction has already started to execute prior to the interruption instruction, the interruption instruction starts to execute without waiting for completion of a preceding instruction; wherein, when an interruption is detected, execution of the interruption program waits for completion of all instructions except for said non-serialized instructions, and execution of said non-serialized instructions is continued; all scoreboard bits are reset to indicate the not-used state; and after the scoreboard bits are reset to the not-used state, all scoreboard bits corresponding to registers used by said non-serialized instructions to execute write operations are set to the in-use state. A pipeline computer as claimed in claim 1, further comprising: a scoreboard setting information selecting means for selecting a set signal or a reset signal for the scoreboard; wherein, after the scoreboard bits corresponding to registers used by said non-serialized instructions are set again to the in-use state, scoreboard resetting information is sent using the same signal line used for resetting the scoreboard bits; and the scoreboard setting information selection means selects the reset signal to reset the scoreboard (SCB) based on the scoreboard resetting information.

Inventors: NAKADA TATSUMI, OHSHIMA TOSHIHARU, NAKADA, TATSUMI, OHSHIMA, TOSHIHARU, NAKADA, TATSUMI, C/O FUJITSU LIMITED, OHSHIMA, TOSHIHARU, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1993
Main classification: G06F9
IPC codes: G06F9