DIGITAL SIGNAL PROCESSOR ARCHITECTURE

Abstract: Processor architecture comprising a central processing unit CPU (2, 4), a program memory (1) and a data memory (3), the central processing unit being functionally composed of a program execution portion (1, 2) and a data processing portion (4), characterised in that, in order to reduce the number of components participating in the constitution of the processor, at least one element (6, 11, 12) of the program execution portion (1, 2) is disposed in the data processing portion (4).

Description: DIGITAL SIGNAL PROCESSOR ARCHITECTURE The present invention concerns processors, and it relates more particularly to a processor especially adapted to applications cf digital telephony. A certain number of applications of digital telephony use a complete standard, ADPCM G721 for voice encoding/decoding. .-. digital signal processor, DSP, Standard, such as TMS320C25 requires 1300 cycles for sampling at 8 kHz (10.4 Mips). The invention envisions creating a new architecture, 3BSF, for a broadband signal processor, optimized to reduce, or. the one hand, the number cf cycies to below 1000 and energy consumption on the other. The list of operations to be performed in the G721 standard are shown in Table I. FUNCTIONS NUMBER Add/subtract 122 AND . 65 Preshift, right 53 Preshift, left 46 Test bit 37 2-complement 24 Dynamic shift 22 Normalization 12 XOR 11 MPY 6*6 8 Post-shift 11 MPY 13*7 1 Shift unit: the preshift, postshift, and normalization functions represent 144 operations out of 415. The shift value varies from 1 to 15 bits to the right or left. Immediate or calculated values are used at the time. Test bit: The G721 standard is characterized by a number of indications of conditional inclusion access, where the result of the test defines execution of one or more groups of actions. Multiplier: The G721 standard requires a multiplication function. The TMS320C25, likewise with a multiplier, is not acceptable from the point of view of economy. The Booth algorithm, with the technique of shifting and addition, is more suitable, and only reduces processor performance by 3%. ALU: a 16-bit ALU arithmetic and logic unit is necessary. Command: A subroutine of G721 requires specific functionality in order to reduce the cycle count and the dissipation of energy, such as a block of repetitive instructions, retarded ramification and return,• a normalization block, and others. The structures of existing processors do not have these capacities and cannot perform efficiently: shifts, normalization, conditional execution, low-cost multiplication in a 16-bit data path. The broadband signal processor (BBSP) uses a Harvard architecture, modified to improve speed and flexibility. In a Harvard architecture, the program and data memories are located in two separate places, permitting total recovery from the call and execution of instructions. The invention envisions creating a processor architecture that has the performance indicated above while staying at a moderate cost price. It therefore has as its object a processor architecture comprising a CPU central processing unit, a program memory, and a data memory, the central processing unit consisting functionally of a program-execution part and a data-processing part, characterized by the fact that in order to reduce the number of components entering into construction of the processor, at least one element of the program-execution part is placed in the data- processing part. It also has as an object a processor architecture of the type defined above, in which the program-execution part contains a program counter, with which an incrementing device and an addressing device are associated, a controller, and the program memory addressed by the program counter, characterized by the fact that the program counter and its incrementing and addressing devices are placed in the data-processing part. The invention will be understood better with the aid of the following description, given only by way of example, and referring to the attached diagrams, in which: - Figure 1 is an overall scheme of the architecture of a broadband signal processor or BBSP; - Figure 2 is a scheme of the program-execution part of the central processing unit of the BBSP of Figure ~ X; - Figure 3 is a scheme of the data-processing part of the central processing unit; - Figure 4 is a partial schematic view of an LMO block of operation registers, one the leftmost in the central processing unit; - Figure 5 is a partial schematic view of a program-counter block that is likewise a part or the CPU registers; - Figure 6 is a partial schematic view of the X and B registers of the central processing unit; - Figure 7 is a partial schematic view of a' block comprising register M and the shift register used to execute the Booth algorithm; - Figure 8 is a partial schematic view of the status and control register of the central processing unit; - Figure 9 is a scheme showing the contents of the program- counter register of Figure 5; - Figure 10 is a partial schematic view of the arithmetic and logic unit and of the shift unit of the architecture of Figure 1; - Figure 11 is a scheme showing the functioning of the shift unit in immediate shifting; - Figure 12 is a scheme showing the functioning of the shift unit in dynamic shifting; - Figs. 13a and 13b are partial schematic views illustrating the functioning of certain registers of the CPU, the shift unit, and the arithmetic and logic unit, respectively with one the leftmost and in dynamic shifting; - Figure 14 shows the memory field of the BBSP according to the invention; - Figure 15 is a scheme showing operand addressing in direct and indirect modes; - Figure 16 illustrates the functioning in pipeline mode of the BBSP architecture according to the invention; - Figure 17 is a representation of the instruction format decoded in the control part of the core of the BBSP; and - Figure 18 shows the instruction codes used in the architecture according to the invention. As shown in Figure 1, the architecture of the BBSP broadband signal processor comprises principally three blocks. The core of the BBSP consists of the CPU central processing unit 2 and 4, a program memory 1, and a data memory 3. The CPU is a 16-bit processor, which is divided functionally into two parts: - a program-execution part 1 and 2, - a data-processing part 4. The program-execu ion part shown in Figure 2 comprises a 14- bit program counter 6, and controller 8, and the program memory 1, which is a ROM. The program counter 6 addresses the program-memory ROM 1 via a 14-bit program-address bus 9. The controller 8 receives instructions from memory 1 via a 24-bit instruction bus 10, and decoding is assured in a decoder functioning in pipeline mode. The controller block 8 includes a 6-bit RPTC command- repetition-counter circuit (Figure 2) for repeating the instructions in a block and an up-and-down counter of memory- stack address for stacking the pointers used to save the context during the course of interruptions or the execution of subroutines. The progra counter 6 is associated with an incrementing device II and an addressing dsvics 12. In order to reduce the silicon surface used and to improve performance and programming flexibility, the program counter 6, the incrementing device 11, and the addressing device 12 of the program counter are placed in the data-processing part 4. In each cycle, the program counter 6 generates the PAB address and calls an instruction in the ROM program memory 1. Normally, the program counter 6 is incremented by 1 by the incrementing device 11. When there is a branch, an interrupt, or a loading of the program counter 6, the status of this counter is modified by a PMA value of a program-memory address transmitted to the counter 6 by a 14-bit bus 13 coming from an instruction decoder or from the arithmetic and logic unit found in the data-processing part. Part 4 of the data-processing part will now be described with reference to Figure 3. It consists of a stack of 16-bit registers 15, a shift unit 16, and a 16-bit ALU arithmetic and logic unit 17. The data-processing part is connected to the data-memory block 3 (Figure 1) by a 16-bit data bus 18 and by a 15-bit address bus 19. The arithmetic and logic unit 17 performs operations on 16- bit words from register to register and direct or indirect memory operations to a register in one instruction. One instruction is executed during each machine cycle. In addition to the usual arithmetic instruction, the ALU 17 can assure operations providing the bit-manipulation capacity required of a high-speed ccncroil r. The shift unit 16 situated at the input of the ALU 17 permits logic or arithmetic shifting to the left or to the right of the contents of a register by 0 to 15 bits, to take place before the execution by the ALU 17 of an operation on the contents. Input A of the ALU receives a 16-bit word from the register stack 15, from the data-memory 3 (Figure 1), or from the controller 8. Input B of the ALU is connected only to the register stack 15 through the shift unit 16. The output of the ALU 17 is connected to the registers 15 and to the data memory 3. The operations of the ALU 17 with the shift unit 16 permit extraction in two instructions (and 2 CPU cycles) of the mantissa and the exponent of a number. A multiplication operation is executed in multiple instructions of one cycle each (MPY/MPY1) . The multiplication instructions use the Booth algorithm with a shifting and addition process. The CPU central processing unit of the BBSP contains eight internal 16-bit registers, which can be used as universal registers or a specialized registers with a dedicated function. Registers X and B can be used for indirect addressing, with a possibility of postincrementing. Register 6 is used as a program counter. 8 Register M is used for multiplication with a shift of 2 bits to the right. Register A2 is the destination register for normalization of instructions. SW is the status register. The organization of the CPU and of the BBSP memory will now be described. The functional diagram of Figure 1 shows the principal data blocks and paths in the BBSP. The CPU of the BBSP contains eight internal registers, which are the following: Register X is a 16-bit register or an indirect register. Register B is a 16-bit register or an indirect register. Register A0 is a 16-bit register. Register Al is a 16-bit register. Register A2 is a 16-bit register. Register M is a 16-bit register or a Booth shift register. Register SW is a status or command register. Register PC 6 is a 14-bit program counter. All these registers can be source and/or destination operands of an instruction executed by the ALU. These registers and their use will be described later. All the internal registers are universal registers. They can be used as source and/or destination operands. To improve the performance of the central processing unit CPU for applications of digital telephony using compression algorithms of the ADPCM type, certain universal registers have specific functions that are directed by a code of instructions. Th registers with specific functions work in parallel with the AL arithmetic and logic unit 17. Register A2 and LMO block 1 with leftmost one are shown i Figure 4 at 20 and 21 respectively. When an LMO code of instructions of with leftmost 1 i specified, the result of the leftmost 1 operation is placed i register A2 20. The result of this operation is the number of contiguou zeros co ing from the most significant bit of the source. Th purpose is normalization of a positive number. The program counter 6 is a 14-bit register that contains th program-memory address of the next instruction to be executed. The BBSP reads the instruction coming from the program memory location addressed by the program counter 6 and increment the program counter for calling the next instruction. The program counter 6 is initialized to zero after th device has been powered on. Bits 14 and 15 of the progra counter are not used for addressing; an operation that read these bits gives bit N and bit Z for bits 15 and 14. A write operation on these bits will have no action, and and Z are not modified. The value of the program counter 6 can be modified b branching, jumping to a subroutine, return, and an operatio where the program counter 6 is used as a destination register. This last possibility is used for a calculated branch Calculated branches are retarded, which means that th 10 instructions following the calculated branch are executed before u e effective branching. For example: LD (X) , PC; calculated branch ST X, AO; executed instruction ADD AO, Al; non-executed instruction "ST X, AO" is executed before the branch, "ADD AO, Al" is executed. A repetition instruction of the instruction block permits creation of a loop without loss of CPU cycle time. This function has been implemented by creating an RPTB instruction, which specifies the number of loops as a parameter, and a condition (?EOL) , which specifies the next-to-last instruction of the loop. The RPTB instruction transfers the starting address of the loop into a register 23 that starts the program counter 6. It also stores in the repetition counter 22 of the control block 8 (Figure 2) the number of the loop to be executed. The next-to-last instruction should be conditional, with the condition ?EOL. This condition alone means that the program counter will be loaded with the starting address after the next instruction. The indirect registers B and X 24 and 25 shown in Figure 6, are both connected to a corresponding incrementing device 26,27, which functions in parallel with the ALU. Indirect addressing is specified within the instruction code, and uses either register X or register B as an address register. 11 They can be autoincremented after instruction execution, i that is specified. MPY is a phase of the Booth multiplication algorithm. Th operation is determined by the two least significant bits of register M 28 and the preceding 1 bit of M in the previous MPY o MPYl operation. MPYl is the first phase of the Booth algorithm. MPY and MPYl are shown in the table below: MPYl d+(s shifted) d-2*(s shifted) d-(s shifted) Register M 28 is logically shifted 2 bits to the right afte the operations MPY and MPYl. The start of a multiplication should be MPYl. A multiplication of 2n bits with sign should be MPY followed by n-1 MPY's. A multiplication of 2n-l bits without sign should by MPY followed by n-1 MPY's. When an interruption is produced, the M(t-l)th bit is not saved, which means that if the interrupt subroutine uses MPY o MPYl, it can modify the result of a multiplication performed i 12 the interrupted subroutine. The status register 30 is shown in Figure 8. It contains status bits, flags, and command bits. All conditional instructions use these status bits t determine the flow of a program. The notations and definition of the bits of the status register are the following: * bit 0 U user bit established or re-establishe by the user; this bit is used in th condition ?U. user bit has been established or re established by the user. selection mode for reading/writing o the data memory. Interrupts with global authorization. This bit authorizes/inhibits maskabl interrupts of the BBSP. 0 = inhibition of the maskable globa interrupt request. 1 = authorization of the maskable globa interrupt request. * bit 4 Ell Interrupt of authorization 1:1 authorized interrupt, 0 = inhibite interrupt. * bit 9 C Carry: this status bit is establishe by arithmetic instructions when th operation gives a carry. 13 A subtraction A - B is considered as a addition A + (-B) , and the carry i established in consequence (inverse o remainder) . C = 0 if A < B; C = 1.if A > B. The operation A NEG A is performed as a addition of !A + 1, and a carry i established in consequence. * bits 10-12 D10-12 Page number for direct addressing. * bit 13 PZ Preceding zero: PZ is a one-level stac for bit Z. PZ is loaded with Z when th status update has been requested. * bit 14 Z Zero: set to one by the CPU if th result of the preceding operation was ϋ otherwise erased. *bit 15 N Negative: the CPU sets this bit to th value of the most significant (sign) bi of the result of the previous operation The condition bits, N, Z, PZ, C, indicate the result of th previous instruction. They are updated each time a status updat (US) is requested by the instruction. When the BBSP recognizes an interruption, • a jump subroutin (JSR) is executed, and condition bits N, Z of the status registe (SW) are automatically pushed onto the stack. These conditio bits are combined with the 14 least significant bits of th program counter 6 and then pushed onto the same word in th stack. 14 The normal exit out of the subroutine is assured by th instruction to return rom tne subroutine, RTS. When the BBS executes the RTS instruction to return from the subroutine, i automatically resets the contents of the program counter with an unstacking operation. The two status bits, N, Z, are not stored, and remain in th state they had before the RTS instruction (Figure 9) . Normal exit from an interrupt is effected with the RT instruction to return from a program interrupt. When the BBS executes an RTI instruction, it automatically resets the content of the program counter with an unstacking operation. The tw status bits, N, Z, are reset, starting from the stack. The SP stack pointers will now be considered. The stack functions as a circular read/write memory, las in, first out. The stack is of the kind typically used fo storing the return address in subroutine calls or o interruptions and condition flags of the status registers 30 The SP stack pointer is a 4-bit counter, which points to th first 16 words in the data memory, starting with the address 0x0 15 through OxlE (16 words of 16 bits) . This counter cannot be accessed directly by the programmer. The SP pointer points only to a word, never to a byte, even if the instruction is an instruction in the form of a byte. The stack pointer is used by the instructions JSR, RTS, RTI, when one enters an interruption subroutine and when the stack pointer is used for indirect addressing. Pushing the stack (JSR and interrupt) is storing an address defined by the stack pointer and an incrementing of the stack pointer, in this order (postincrementing the SP) . Popping the stack (RTS and RTI) is provided by a decrement of the stack pointer (predecrementing the SP) . Therefore, this is a reading of the address defined by the new value in the SP. The shift unit 16 and the arithmetic and logic unit 17 will now be described with reference to Figure 10. The shift unit 16 receives the contents of source/destination register RB, which can be shifted in a logical or arithmetic manner to the left or to the right by 0 to 15 bits. The output of the shift unit is connected directly to the B input of the arithmetic and logic unit 17. This unit performs an operation between A and B. Input A receives a file [sic] from register RA, a constant K, or data from a memory and input B, but only the output of shift unit 16. The shift value is defined in the instruction code for an immediate shift operation or in register A2 for a dynamic shift. 16 Immediate shift: The instruction operand defines: - a shift value from 0 to 15, - a direction to the left or to the right, - a logical or arithmetic shift. Examples of sifts are given below. 1. AND AO, Al, L » 15; AND AO & Al, shif logically by 15 units the right, result sa in Al. 2. AND AO, A; AND AO S- Al, result sa in Al. 3. AND AO, Al, L « 1; AND AO £ Al, shif logically 1 bit to right, result saved Al. 4. AND AO, Al, A » 1; AND AO S. Al, shif arithmetically by 1 to the right, res saved in Al. 5. AND AO, Al, A » 15; AND AO S- Al, shif arithme ically by 15 b to the right, res saved in Al. The codes for shifts cf Examples 1 through 5 given below shown in Figure 11, which shows an immediate shift. The dynamic shift shown in Figure 12 is a shift to the le 1 7 the number of bits to be shifted being a value with sig contained in register A2. This mode has the possibility o shifting RB from 32 to 31. Normally, a leftmost 1 operation precedes a dynamic shift. The result of the LMO operation is the number of contiguou zeros, starting with the most significant bit of the sourc register. The result is placed in register A2 20. The dynamic shif operation places the first of the source register in a positio of most significant bit. During execution of the LMO instructio (Figure 13a), the exponent of AO is placed in A2. The normalization instruction (Figure 13b) sifts AO by value defined in A2. The result of the operation between Al (i requested) and A2 is shifted on returning to A2. The organization of the memory of the BBSP will now b described with reference to Figure 14. The BBSP makes use of a Harvard architecture with the dat memory and program memory located in separate places. The BBSP provides two separate address spaces for th program memory and the data memory. Figure 14 shows the arrangements of the memory regions in BBSP. In the program space 30, the 14 bits of the program counte 6 of the BBSP can address 16-bit words 24 of program memor (Figure 1) . The upper part of the memory contains the origin o the address vectors for an interrupt and a return to the initia state 2.2.2. 18 The data space contains a RAM, a ROM, and an input-output set, I/O; the address space 31 is contained between 0 and 7FFFh. It is organized in bytes (octets) . All the addresses are byt addresses. With an indirect-addressing mode, one can access 32 kilobytes of data space. The B or X registers contain a effective address of 15 bits. In the direct-addressing mode, one can only reach the first 8 K bytes. The "DMA" instruction field contains an address shifted by 10 bits, and the status registers contain a pag address of 3 bits. The two most significant bits are set to zero, as shown i Figure 15, which shows a scheme of operand addressing. It will be noted that the I/O space of inputs and outputs 32 is a 32-word space placed at the end of the data pages. The BBSP uses a modified Harvard architecture, in which th data memory and the program memory are located in two separat spaces, which permits a complete overlapping of the calling an execution of the instructions. This overlapping is possible because of the two-level pipeline architecture adopted for the BBSP, as shown in Figur 16. The pipeline architecture is the best compromise in terms o performance with respect to the number of transistors necessar and the energy consumed. The pipeline of prefetching/decoding/execution i practically invisible to the user. 19 In the functioning of the pipeline, the operations of prefetching, decoding, and execution are independent, as is shown by the groups of arrows in Figure 16. First pipeline level. 1. The program counter 6 generates the next instruction address. 2. Instruction fetch. 3. Updating the program address. 4. Decoding the instruction Second pipeline level. 5. Generation of an operand address. 6. Reading of the operands. 7. Updating the addresses of the operands (if the addressing is indirect with postmcrementing) . 8. Execution and saving of the result in a destination register or in memory. The BBSP instruction set will now be examined. The BBSP has four instruction formats. Instructions from register to register, which define an operation between two registers, Ra and Rb. Indirect register instructions, concerning operations between a data-memory address, defined in register Ra, and register Rb. Instructions from register to memory, concerning operations between a data-memory address, defined in the instruction field, and register Rb. Command instructions, assuring control of the flow of 20 program execution. The instruction format will now be described with reference to Figure 17, which shows the four instruction formats listed above in the form of four lines. The register-to-register, indirect-register, and register- to-memory instructions are integer instructions. The last format is the command instruction. The format of the instruction is chosen in field 3.0. All the instructions have a length of 24 bits in order to reduce the complexity of decoding and the dissipation of energy; the fields for instruction format 3.0, opcode 3.1 or 3.2 of the condition code 3.3 are identical. For integer instructions, the updating status 3.4 and the source/destination register 3.5 are common. The other fields depend on the format. The type of instruction is decoded in the control part 8 of the core of the BBSP (Figure 1) . The instruction codes are shown in detail in Figure 18. The opcodes (operation codes) of the integer instructions are divided into four categories. - operations with shif ing of the operand 3.15. - operations without shifting 3.16. - operations of multiplications 3.17. - byte transfer 3.18. 21 The instructions with destination shifting are: Addition ADD Addition/subtraction conditioned on A ASCA Addition/subtraction conditioned on B ASCB Subtraction A SUBA Subtraction B SUBB ET AND OU OR Exclusive OR XOR The instructions with source shifting are: Storage ST Conditional storage STNC Multiplication MPY Multiplication 1 MPYl Conditional byte storage STB The instructions without shifting are: Loading LD Left-most one LMO Negation NEG The opcode command instructions presented in [3.2] of Figure 18 are divided into three categories. - Instructions without operand 3.19. - Instructions with program-memory address 3.20, 3.22. - Instructions with repetition value 3.21. The opcode instructions direct the functioning of the arithmetic and logic unit 17. 22 The condition codes are represented by field 3.3 in Figur 17. They select the execution condition for an instruction. T various conditions are presented in 3.3 of Figure 18. The condition chosen is compared with the contents of t current status. If the condition is true, the destinatio operand is modified by the result of the execution of the curren operation. If the condition is not true, the destination is no modified. The status update is shown by field 3.4 in Figure 17. If the US status update bit is a 1, the status is update with the result of the execution of the current operation in th ALU 17. In word mode, the status is set to the 16-bit result o the ALU. In byte mode, B = 1, the status is set to the 8-bi result of the ALU. If the US bit is not selected, the status is not modified. Source and destination registers: The Rb field selects the source/destination register. The contents of the Rb register are connected to input B o the ALU 17 through the shift unit 16. Source or indirect-addressing register: In the register-to-register format, Ra 3.6, one selects t source register that is connected to input A of the ALU 17. In indirect addressing, the indirect field, Ra 3.23, 3.24 selects a register that contains the address of the data in t memory. The register can be autoincremented after execution o an instruction. 23 All the instructions other that the control instructions ca have only the format of a byte or of a word. These instructions are: Addition ADD AND operation AND Addition/subtraction conditioned on A ASCA Addition/subtraction conditioned on B ASCB Loading LD Left most one LMO Multiplication 1 MPYl Multiplication MPY Negation NEG OR operation OR Storage ST Conditional storage STNC Subtraction A SUBA Subtraction B SUBB Exclusive-OR operation XOR The default value is the word format ("ADD AO, B"); b adding a .b afterwards, the mnemonic instruction becomes a byt instruction ("ADD.B, AO, B"). This element of modification ca have the following consequences: - if status updating is used, the status word will b updated with the least significant 8 bits of the result. - in the indirect-addressing mode with auto-incrementing the index will be incremented by 1 (instead of 2) . - the high-order byte of the 16 bits sent to the arithmeti 24 and logic unit is set to 0, if the data come from the da memory. It will be understood that in the byte mode, the arithmet and logic unit (with the exception of the flag) functions in t 16-bit mode. This means that the result placed in the destinati register is a 16-bit result. The data coming from the sour register are also 16-bit data. This means that a shift to the right should be used wi attention to the fact that the shift unit also functions int 16-bit mode. When the data come from memory, the high-order by is set to zero and is not modified when the data come from t register. This means of byte identification could only be used f addressing from register to register or indirect addressing. It cannot be used in direct addressing and immedia addressing. It cannot be used in control instructions, either. Three other byte instructions have been added: LDB load byte STB store byte CBB compare byte and brancn LDB and STB can only be used with direct addressing. They are not usable with register-to-register addressing a indirect addressing. The register-to-register and indirect-register instructio contain a shift operand 3.S, which selects arithmetic or log 25 shifts, and a 5-bit field 3.9, which selects the shifting to the left cr right and the value of the shift. The DMA direct-memory-address field 3.10 shown in Figure 17 selects the address of the source operand connected to input A of the arithmetic and logic unit 17 when the condition codes 3.3 7 or 15 are selected. This field is a constant with sign 3.11, which is used as a source operand connected to input A of the ALU 17. The ALU operation is executed between Rb and K. The result is in destination register Rb. The PMA field 3.12 contains the program address that modifies the program counter with control instructions. The repetition value is loaded into the repetition counter 22 (Figure 2) with an RPTB block-repetition instruction. The RPTB releases an instruction-repetition block which ends when the repetition counter is at zero and when the condition code EOL has been selected. At each loop, the repetition counter is decremented by 1. 26

Claims: WE CLAIM: —1. processor architecture comprising a central processing unit CPU, (2, 4), a program memory (1) and a data memory (3), the central processing unit being functionally composed of a program execution portion (1, 2) and a data processing portion (4), characterised in that, in order to reduce the number of components participating in the constitution of the processor, at least one element (6, 11, 12) of the program execution portion (1, 2) is disposed in the data processing portion (4).-- --2. Processor architecture according to Claim 1, in which, the program execution portion (1, 2) includes a program counter (6) with which there are associated an incrementing device (11) and an addressing device (12), a controller (8) and the program memory (1) addressed by the program counter (6), wherein the program counter (6) and its incrementing and addressing devices (12) are disposed in the data processing portion (4).-- —3. Processor architecture according to claim 1 or claim 2, in which the data processing portion (4) includes a stack of registers (15) and an arithmetic and logic unit (17) , the data processing portion (4) being connected to the data memory (3) by a data bus (18) and an address bus (19, wherein the program counter (6), its incrementing device and its addressing device form part of the stack of registers (15) of the data processing portion (4) .-- —4. Processor architecture according to Claim 3, wherein the data processing portion (4) further includes a shift unit (16) connected between the stack of registers (15) and the 27 arithmetic and logic unit (17) and permitting a logic or arithmetic shift to the left or the right of a register content to be positioned before the execution of an operation on this content by the arithmetic and logic unit (17).-- —5. Processor architecture according to one of Claims 1 to 4, wherein the program counter (6) is further connected to the arithmetic and logic unit (17) or to an instruction decoder of the data processing portion (4) by a bus (13) for transmission of a signal (PMA) for modification of the condition of the program counter (6) on the occasion of a connection, of an interruption or of a loading of the program counter (6).-- --6. Processor architecture according to one of Claims 1 to 5, wherein the data processing portion (4) of the central processing unit includes a plurality of internal registers (X, B, AO, Al, A2, M, SW, PC) which may be utilised as universal registers or as specialised registers with a dedicated function.- —7. Processor architecture according to Claim 6, characterised in that said registers which may be utilised as universal registers or as specialised registers comprise registers (X, B) connected to an incrementing device which functions in parallel with the arithmetic and logic unit (17) and utilised as address registers on the occasion of an indirect addressing, a register (20) to receive the result of a leftmost one operation, associated with a leftmost one operating block (21), a Booth shift multiplication register (M) (21), a status or command register (SW) and a register (PC) constituting the 28 program counter (6).— --8. Processor architecture according to Claim 7, characterised in that the multiplication by means of the Booth shift register is executed by a series of addition/shift instructions (MPY) , the first one (MPYl) of which permits the initialisation of the multiplication sequence.-- 29

Inventors: CHAUVEL GERARD, CIROUX JEAN, DENT PETER, LAURENTI GILBERT, WENZINGER YVES, CHAUVEL, GERARD, CIROUX, JEAN, DENT, PETER, LAURENTI, GILBERT, WENZINGER, YVES
Applicants: CHAUVEL GERARD, CIROUX JEAN, DENT PETER, LAURENTI GILBERT, TEXAS INSTRUMENTS FRANCE, TEXAS INSTRUMENTS INC, WENZINGER YVES, TEXAS INSTRUMENTS INCORPORATED
Application year: 1993
Main classification: G06F9
IPC codes: G06F9, G06F15, H04B14