Field programmable gate array

Abstract: A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.

Description: BACKGROUND OF THE INVENTION The present invention relates to FPGAs (field programmable gate arrays). Figure 12 shows a general configuration of an FPGA. In the figure, the circuit blocks 810 and 811 each including logic circuits are arranged. These circuit blocks 810 and 811 are connectable to each other through interconnection 831. Further, these circuit blocks 810 and 811 are also connectable to external terminals (which are not shown in this figure) through the interconnection 831, respectively. In addition, connecting means 821 are arranged between the interconnection 831 and each of the circuit blocks 810 and 811, respectively. Each of these connecting means 821 are programmed/not programmed from a turned-on state to a turned-off state or vice versa in accordance with a program prepared by a user after the FPGA has been shipped. In other words, it is possible to obtain an apparatus providing with desired functions by connecting the interconnection 831 and the circuit blocks 810 and 811 freely in accordance with the programmed connecting means 821. Figure 13 shows another FPGA in which a plurality of circuit blocks 910 and 911 is arranged in the first row ROW 0 and circuit blocks 920 and 921 in the second row ROW 1, respectively. Further, interconnection 951 is provided to programmably connect the circuit blocks 910, 911, 920 and 921 to each other or to programmably connect the circuit blocks 910 to 921 with external terminals, respectively. Programmable connecting means 941 are arranged between the circuit blocks 910 to 921 and the interconnection 951, respectively and further other connecting means 931 are arranged on interconnection 951, respectively. Using the FPGA, it is possible to obtain desired functions by programming the connecting means 931 and 941, respectively. In the above-mentioned FPGAs, however, there exists a problem as follows: since users would use any part of the prepared circuit blocks, connecting means and interconnection, all the interconnections and all the connecting means must be perfect or non-defective. In other words, if any one of a plurality of the circuit blocks will not function or only one of a plurality of interconnections is disconnected or any one of a plurality of the connecting means cannot be programmed, the desired functions could not be obtained. Recently, the capacity of FPGAs has been increasing, and it causes a low production yield and a high chip cost of FPGAs. US-A-4 608 668 discloses a semiconductor device that replaces a normal circuit block, if defective, with a spare circuit block. Said spare circuit block is used by being connected to another circuit block through a first conductor means and the normal block is used by being connected to said other circuit block through a second conductor means. EP-A-0 351 983 discloses a programmable logic device including a plurality of word lines and a plurality of bit lines each of which being interconnectable to at least one of the word lines, and further including at least one spare word line and/or bit line for use in the event that one of the regular lines of the same kind is defective. When the spare line is to be used, the device is preprogrammed to automatically redirect all signals intended for the bad line to another line, thereby putting the spare line into use. SUMMARY OF THE INVENTION It is an object of the present invention to provide a field programmable gate array which has a comparatively high production yield and a low manufacturing cost thereof. This object is achieved by providing a field programmable gate array having the features of claim 1. Further improvements thereof are specified in the claims 2 to 10 being dependent on claim 1. Preferred embodiments of the present invention are described hereinbelow with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of a comparative example of a field programmable gate array ; Fig. 2 is a block diagram for assistance in explaining the operation when the field programmable gate array shown in Fig. 1 is defective partially; Fig. 3 is a block diagram showing the configuration of a first embodiment of the field programmable gate array according to the present invention; Fig. 4 is a block diagram for assistance in explaining the operation when the field programmable gate array shown in Fig. 3 is defective partially; Fig. 5 is a block diagram showing the configuration of a second embodiment of the field programmable gate array according to the present invention; Fig. 6 is a block diagram for assistance in explaining the operation when the field programmable gate array shown in Fig. 5 is defective partially; Fig. 7 is a set of interconnecting segments of a conventional field programmable gate array; Fig. 8 is a set of interconnecting segments in the second embodiment of the field programmable gate array according to the present invention; Fig. 9, is a block diagram showing the configuration of a third embodiment of the field programmable gate array according to the present invention; Fig. 10 is a block diagram for assistance in explaining the operation when the field programmable gate array shown in Fig. 9 is defective partially; Fig. 11 is a cross-sectional view showing an anti-fuse structure which is available as the connecting means of the first to third embodiments of the present invention; Fig. 12 is a block diagram showing the configuration of a conventional field programmable gate array; and Fig. 13 is a block diagram showing the configuration of another conventional field programmable gate array. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the field programmable gate array (FPGA) according to the present invention will be described hereinbelow with reference to the attached drawings. Figure 1 is a block diagram showing a comparative example of a field programmable gate array. The FPGA comprises a plurality of regular circuit blocks 110 and 111, a spare circuit block 112, a plurality of sets of connecting means 131 and 132, a set of spare connecting means 133, an interconnection 121, and control means 141. In each of the regular circuit blocks 110 and 111, logic circuits are formed. The configuration of the spare circuit block 112 is electrically equivalent to that of the regular circuit blocks 110 and 111. The set of connecting means 131 consists of programmable switches 131a and 131b for connecting the regular circuit block 110 and the interconnection 121; the set of connecting means 132 consists of programmable switches 132a and 132b for connecting the circuit block 111 and the interconnection 121; and a spare set of connecting means 133 consists of spare programmable switches 133a and 133b for connecting the spare circuit block 112 and the interconnection 121, respectively. Further, the interconnection 121 can be connected to an external terminal (not shown). The control means 141 controls the programming of each set of the connecting means 131 and 132 and the spare set of connecting means group 133. If the circuit blocks 110, 111 and the interconnection 121 are not defective, the spare set of connecting means 133 cannot be programmed by the control means 141 after shipping. In this case users can customise the FPGA by programming the sets of connecting means 131, 132. Assuming the programmable switches are antifuses, the set of connecting means 133 holds turn off state permanently. The structure of an anti-fuse will be explained later with reference to Pig. 11. As described above, under normal case, the control means 141 can control the state of only the set of connecting means 131 and 132, but cannot control the state of spare set of connecting means 133. Figure 2 shows a case when the block circuit 111 of the same FPGA shown in Fig. 1 is defective. In this case the spare set of connecting means 133 can be programmed by the control means 141, while the set of connecting means 132 cannot be programmed by the control means 141 after shipping. Accordingly, the regular circuit block 110 and the spare circuit block 112 can be connected through the interconnection 121, by programming the set of connecting means 131 and the spare set of connecting means 133. Here, the regular circuit blocks 110 and 111 are electrically equivalent to the spare circuit block 112, respectively and further the sets of regular connecting means 131 and 132 are also electrically equivalent to the spare set of connecting means 133, respectively. Therefore, users can customise the FPGA quite the same manner as in the case of the circuit block 111 is non-defective. As described above, in case there exists a defect in the regular circuit blocks 110 or 111 or the interconnection 121 between the regular circuit blocks 110 and 111, it is possible to recover the entire FPGA from the defect by replacing the defective circuit block by the spare circuit block 112. It results in improving the production yield thereof and reducing the manufacturing cost thereof. Figure 3 shows a first embodiment of the FPGA according to the present invention. In the example shown in Fig. 1, a plurality of the regular circuit blocks 110 and 111 are arranged for one row, and further the interconnection 121 is provided to connect the regular circuit blocks 110 and 111 and the spare circuit block 112, respectively. In comparison with said example, in this first embodiment, the regular circuit blocks 210 to 222 are arranged in a matrix pattern of two rows and three columns. In addition, a plurality of the spare circuit blocks 230 to 232 are arranged in the spare row (one for each column, respectively). The regular circuit block 210 can be connected to two interconnections 261 and 262 using two connecting means 271 and 272, respectively. The other remaining regular circuit blocks 211, 212, 220, 221 and 222 can be connected to interconnections 261, 262, 263 and 264 using connecting means in the same way as above. The interconnections 261 and 262 provided for the regular row 0 can be connected to the interconnection 267 (for connecting the regular circuit blocks 210 to 222) via sets of connecting means 241 which consists of programmable switches 241a and 241b. In the same way as above, the interconnections 263 and 264 provided for the regular row 1 can be connected to the interconnection 267 (for connecting the regular circuit blocks 210 to 222) using set of connecting means 242. The spare row is configured similarly to the regular rows 0 and 1. In more detail, the spare circuit blocks 230 to 232 and the interconnections 265 and 266 can be connected by spare connecting means 273 and 274. Further, the interconnections 265 and 266 and the interconnection 267 can be connected using a set of connecting means 243. The control means 251 controls the programming of sets of the connecting means 241 and 242 in the regular rows 0 and 1 and the spare set of connecting means 243 in the spare row. If the circuit blocks 210, 211, 212, 220, 221 and 222, and interconnections 261, 262, 263 and 264 are not defective, the spare set of connecting means 243 cannot be programmed by the control means 251 after shipping. In this case users can customise the FPGA by programming the sets of connecting means 241 and 242. Figure 4 shows a case when the interconnection 263 in the regular row 1 is defective. In this case the spare set of connecting means 243 can be programmed by the control means 251, while the set of connecting means 242 cannot be programmed by the control means 251 after shipping. As described above, in any case where any one of the regular circuit blocks, the interconnections and the set of connecting means arranged in the regular rows is defective, the defective row can be replaced by the spare row. And it improves the production yield of the FPGA and reduces the cost of the FPGA thereof. Figure 5 shows the configuration of the second embodiment of the present invention, in which regular circuit blocks 310 to 317 in each of which logic circuits are formed are arranged in the regular rows from 0 to 7, respectively. Further, a spare circuit block 318 is arranged in a spare row. Each logic block including the spare row has programmable switches, which are not depicted in Fig. 5, and the switches can be programmed by the signal from the row decoder 341. To connect the each decoded signal to the appropriate row the selector 331 is used. The non-volatile storing means 321 has the position data of the defective row, which is stored by the manufacturer of the chip, and controls the selector 331 to connect the each of the decoded signals to the appropriate row. Before explaining replacement principle of a defective row with the spare row, the modification interconnections connecting a plurality of rows will be explained. Figure 7 shows an FPGA without the redundancy scheme. In this figure the circuit blocks 510 to 517 are arranged in rows. The interconnections 521 to 529 represent interconnecting segments which can connect a plurality of rows by programming the programmable switch 530 to 545. Although the explanation will be done for two row length interconnecting segments, the modification manner is same for the other length interconnections. The rows 0 and 1 in Fig. 7 can be connected by the interconnection 521; the rows 1 and 2 can be connected by the interconnection 526; the rows 2 and 3 can be connected by the interconnection 522, and so on. In this case, if the circuit block 513 arranged in the row 3 is defective and replaced with the row 4 for instance, since there are no interconnections for connecting the row 2 and the row 4, the connection between the circuit blocks will be restricted. To eliminate this problem, in the FPGA with the redundancy scheme the length of interconnection for connecting rows must be extended by one row length. Consequently, the length of the interconnecting segments for connecting two adjacent rows in the second embodiment must be replaced with the three row length segments as shown in Fig. 8. The extended portion can be used only if there is a defective row. In other words, the interconnecting segments in Fig. 8 which has three row length are used as the two row length segments logically. For example, the interconnection 621 in Fig. 8 can connect the row 0 and the row 1 and cannot connect the row 2 if the both of the row 0 and row 1 is not defective. When the row 1 is defective, it is replaced by the row 2 and the interconnection 621 can connect the row 0 and the row 2. The usable portions of the interconnections are defined by connecting the each signal from the row decoder 341 to the appropriate row. Next the replacement of the defective row will be explained using Fig. 5, Fig. 6 and Fig. 8. Figure 5 corresponds to the case there is no defective row. In this case, because no signal from the row decoder 341 is connected to the spare row after shipping, users customise the FPGA without using the spare row. As is mentioned before the interconnection 621 is used to connect the row 0 and the row 1, and not used to connect the row 2; the interconnection 622 is used to connect the row 3 and the row 4, and not used to connect the row 5, and so on. Figure 6 shows the case the row 3 is defective. In this case, the signal for the row 3 is shifted down by one row and connected to the row 4; the signal for the row 4 is shifted down by one row and connected to the row 5; and so on. The control for the shifting is done by the control circuit 321. Because no signal from the decoder is connected to the row 3, users customise the FPGA without using the row 3. The interconnection 621 is used to connect the row 0 and the row 1, and not used to connect the row 2; the interconnection 625 is used to connect the row 1 and the row 2 and not used to connect the row 3; the interconnection 622 is used to connect the row 4 and the row 5 and not used to connect the row 3, the interconnection 626 is used to connect the row 5 and the row 6, and not used to connect the row 4; the interconnection 623 is used to connect the row 7 and the spare row, and not used to connect the row 6. Thus the modification to the interconnecting segments, which span the plurality of the rows, offers the equivalent interconnecting resources to the user even after the defective row is replaced, and it results in eliminating a change in customising the FPGA. Figure 9 shows the third embodiment of the FPGA according to the present invention. In the second embodiment, the spare circuit blocks are arranged in only one row. In this third embodiment, however, the spare circuit blocks 411 are arranged in both row and column, which is hatched in Fig. 9. The third embodiment comprises regular circuit blocks 410 which is arranged in matrix pattern, the spare circuit blocks 411 which are arranged in a row and a column, the row programming decoder 461, the column programming decoder 421, the selectors 451 and 441, the non-volatile storing means 431 which has the position data of the defective row, which is stored by the manufacturer of the chip and controls the selectors 451 and 441. When there exist defective circuit blocks, the row which contains the defective circuit block/blocks and the column which contains the defective circuit block/blocks are replaced with another row and another column by shifting down the row and shifting left the column as shown in Fig. 10. This figure corresponds to the case the row 3 in Fig. 9 and the column 6 in Fig. 9 have the defective circuit blocks. Of course the defective row and the defective column can not be programmed by users because no signal from the row programming decoder 461 and the column programming decoder 421 as is explained in the second embodiment. In the above-mentioned first to third embodiments, the programmable switches are provided for connecting the circuit blocks. As the programmable switches, any means can be used, as far as it changes its state from turn-on or turn-off by applying control bit or bits. For instance, it is possible to use an anti-fuse which is shown in Fig. 11 as the programmable switch. In the anti-fuse shown in Pig. 11, a metallic wire 702 made of aluminum or a high melting point metal is formed on a semiconductor substrate 701, and an insulating film 703 such as a silicon oxide film is formed on the surface of the metallic wire 702. Further, a connection hole is formed in this insulating film 703, and a thin insulating film 704 is formed so as to cover the formed connection hole. Further, a metallic wire 705 is formed on the insulating film 704 extending in a direction perpendicular to the paper. In this anti-fuse, the two metallic wires 702 and 705 are insulated from each other before applying the programming voltage. On the other hand, when the programming voltage is applied between the two metallic wires 702 and 705, the thin insulating film 704 is broken down, and the anti-fuse turns on. As described above, the anti-fuse type programmable switch, keeps a turned-off state before programming but changed to a turned-on state after programming. However, it is of course possible to use a fuse type programmable switch. In this case, the programmable switch keeps a turned-on state before programming, but changed to a turned-off state after programming.

Claims: A field programmable gate array, comprising a plurality of regular circuit blocks (210-222; 310-317; 410) each having logic circuits, arranged in rows and/or columns; at least one spare circuit block (230-232; 318; 411) having logic circuits, arranged in a spare row and/or spare column; interconnections to connect the regular circuit rows and/or regular circuit columns and spare interconnections to eventually connect the spare circuit row and/or spare circuit column; connecting means (241, 242; 331; 441; 451) and spare connecting means (243; 331; 441 ; 451) which are located between the different interconnections and which turn their state to a turned-on state or a turned-off state when programmed, that are not field programmable and that are controlled in such a way that, when the circuit blocks, said connecting means and said set of interconnections are not defective, said connecting means is set to being programmable and said spare connecting means is set to being non-programmable; and, when any one of the circuit blocks, said connecting means or said set of interconnections is defective, said connecting means corresponding to the defective position is set to being non-programmable and said spare connecting means is set to being programmable; and control means (251; 321; 431) to control the connecting means and spare connecting means. The field programmable gate array according to claim 1, wherein said regular circuit blocks and said at least one spare circuit block are electrically equivalent to each other in configuration. The field programmable gate array according to claim 1 or 2, wherein said connecting means is an anti-fuse kept in the turned-off status before being programmed, but switched to the turned-on status after being programmed. The field programmable gate array according to any of the preceding claims, wherein said connecting means and spare connecting means are electrically equivalent to each other in configuration. The field programmable gate array according to any of the preceding claims, wherein said interconnections comprise: a first wire group including at least one wire disposed in the vicinity of said circuit blocks and said spare circuit block; a second wire group (261-264) including a plurality of wires for connecting said circuit blocks and said first wire group, respectively, in parallel to each other so as to be programmable; and a third wire group (265-266) including at least one wire for connecting said spare circuit block and said first wire group, respectively, in parallel to each other so as to be programmable. The field programmable gate array according to claim 5, wherein said second wire group and said third wire group are electrically equivalent to each other in configuration. A field programmable gate array according to any of the preceding claims, wherein said regular circuit blocks are arranged in a matrix, and said spare part blocks are arranged in at least one row and/or one column. The field programmable gate array according to claim 7, wherein said regular circuit blocks and the spare circuit block each are connectable to two or more other regular ciruit blocks or spare circuit blocks, respectively. A field programmable gate array according to any of claims 1 to 4, wherein said plurality of regular circuit blocks are arranged in groups of at last three circuit blocks (210, 211, 212, 220, 221, 222; 310-317; 410) arranged in each of a plurality of rows or columns; said interconnections include a wire group including first wires for programmably connecting two of the three adjacent regular circuit blocks and second wires for programmably connecting two of three adjacent blocks of said spare circuit blocks; and said connecting means comprise at least one first connecting means (241, 242: 331: 451) to programmably connect said regular circuit blocks through the first wires of said wire group, and at least one second connecting means (242; 331; 451) to programmably connect two of three adjacent circuit blocks including at least one spare ciruit block through the second wires of said wire group. A field programmable gate array according to any of claims 1 to 4, wherein said plurality of regular circuit blocks (210-222; 310-317; 410) are arranged in n rows, with n being an integer, and said spare circuit block (230, 231, 232; 318; 411) is arranged in a row; said interconnections include interconnecting segments, at least one interconnecting segment spanning a plurality of rows; said connecting means are set to programmably connect said interconnecting segment and said logic blocks under normal conditions; said spare connecting means are set to programmably connect said interconnecting segments, said logic circuit blocks and said spare circuit block if at least one of said circuit blocks, said interconnecting segments, or the connecting means is defective; and said at least one interconnecting segment spanning the rows is logically regarded as an interconnection spanning n-1 rows, when users customize the field programmable gate array.

Inventors: HATORI FUMITOSHI, NOGAMI KAZUTAKA, SAKURAI TAKAYASU, HATORI, FUMITOSHI, NOGAMI, KAZUTAKA, SAKURAI, TAKAYASU
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: G06F11
IPC codes: H01L27, H01L21, G06F11