Switched capacitor amplifier circuit

Abstract: In a switched capacitor amplifier circuit of an offset cancellation type, a capacitor (12) is arranged between a reverse input terminal of an operational amplifier (8) of an OTA type and a reference voltage. Only in a offset cancelling operation in which a first group of switches are on, the capacitor functions as a load of the amplifier. The capacitor hence does not exert any influence upon transfer of charge. With provision of the circuit, the phenomenon of oscillation is suppressed in the operation to cancel the offset voltage.

Description: The present invention relates to an amplifier circuit, and in particular, to a switched capacitor amplifier circuit capable of automatically compensating for an offset voltage. In an operational amplifier, due to a characteristic of a pair of transistors in a first stage, there appears a direct-current (dc) offset voltage, which possibly causes an output error. Heretofore, to overcome this difficulty, a switched capacitor amplifier circuit includes a circuit to automatically compensate for the offset voltage. Fig. 1 shows an example of the conventional amplifier circuit achieving compensation for offset voltage. The constitution of Fig. 1 includes switches 3 to 5 each being turned on or off by a clock signal A and switches 6 and 7 each being set to an on or off state in response to a clock signal B. The clocks A and B are shifted from each other by half a period thereof and are not overlapped with each other. In consequence, when the switches 3 to 5 are on, the switches 6 and 7 are off in any case and vice versa. Fig. 2A shows a sample state for an offset cancellation in which the switches 3 to 5 are on due to the clock signal A; whereas, Fig. 2B shows a hold state with an amplifying operation in which the switches 6 and 7 are on in response to the clock signal B. In this configuration, when the switches 3 to 5 and capacitors 10 and 11 having capacitances αC and C, respectively, are on, an operational amplifier 8 functions as an amplifier developing a gain "1". Resultantly, the capacitors 10 and 11 are respectively charged up to Vos - Vin and Vos, thereby producing an output voltage Vos. Assume next that when the switches 6 and 7 are on, there is developed an output voltage Vout as shown in Fig. 2B. In this situation, the capacitors 10 and 11 are respectively charged up to Vos and Vos - Vout. Since the quantity of electric charge at a reverse input terminal of the amplifier 8 is fixed, αC(Vos - Vin) + CVos = αCVos + C(Vos - Vout) holds. Consequently, there is obtained. Vout =αVin. This means that the offset voltage is cancelled out and hence does not exercise any influence upon the output voltage. According to the conventional switched capacitor amplifier circuit of the offset cancellation type, when the switches 3 to 5 are on, the operational amplifier serves as a unity gain buffer. In a case where the amplifier belongs to a type of operational-transconductance amplifiers (0TAs), there has been a problem that the amplifier easily initiates a signal oscillation. EP-A-0 078 601 and US-A-4 656 871 disclose a switched capacitor amplifier achieving cancellation of an offset voltage without using a loading capacitor. It is therefore an object of the present invention to provide a switched capacitor amplifier circuit in which a load is imposed on an output of an operational amplifier thereof only when cancelling an offset voltage thereof, thereby suppressing a phenomenon of signal oscillation. In accordance with the present invention, there is provided a switched capacitor amplifier circuit including an operational amplifier having a non-reverse input terminal connected to a reference voltage, and a first capacitor connected between a reverse input terminal of the operational amplifier and the reference voltage. The first capacitor serves as a load of the operational amplifier only when the circuit achieves cancellation of an offset voltage. The objects and features of the present invention will become more apparent from the consideration of the following detailed description taken in conjunction with the accompanying drawings in which: Fig. 1 is a schematic diagram showing the configuration of a switched capacitor amplifier circuit in the prior art; Fig. 2A is a circuit diagram showing a state of the circuit in which switches of Fig. 1 are on; Fig. 2B is a diagram showing a circuit state in which switches of Fig. 1 are on; Fig. 3 is a diagram schematically showing the constitution of an embodiment of a switched capacitor amplifier circuit in accordance with the present invention; Fig. 4A is a circuit diagram showing a state of the circuit in which switches of Fig. 3 are on; and Fig. 4B is a diagram showing a circuit state in which switches of Fig. 3 are on. Referring now to the accompanying drawings, description will be given of an embodiment in accordance with the present invention. Fig. 3 shows the structure of an embodiment of a switched capacitor amplifier circuit in accordance with the present invention. The circuit construction includes a signal input terminal connected via a switch 3 and a capacitor 10 to a reverse input terminal of an operational amplifier 8. The amplifier has a non-reverse input terminal linked with a reference voltage source 9. A connecting point between the switch 3 and the capacitor 10 is connected to the reference voltage source 9 via a switch 6. The reverse input terminal of the amplifier 8 is also coupled with the voltage supply 9 via a capacitor 12 having a capacitance C L . Moreover. the reverse input terminal is connected via a switch 4 to an output terminal 2 of the amplifier 8 as well as via a switch 7 and a capacitor 11 to the output terminal 2 of the amplifier 8. A connection point between the switch 7 and the capacitor 11 is coupled with the voltage source 9 via a switch 5. Designated at reference character 13 is an offset-representative voltage source (see Fig 4). The circuit constitution of Fig. 3 differs from that of the conventional example shown in Fig. 1 in that the capacitor 12 having the capacitance C L is disposed between the reverse input terminal of the amplifier 8 and the reference voltage source 9. Fig. 4A shows a sample state for an offset cancellation in which the switches 3 to 5 of Fig. 3 are on; whereas, Fig. 4B shows a hold state with an amplifying operation in which the switches 6 and 7 of Fig. 3 are on. In the state where the switches 3 to 5 are on, the operational amplifier 8 functions as a voltage follower circuit like in the conventional example of Fig. 2A such that the capacitors 10 and 11 are charged up to voltages Vos - Vin and Vos, respectively. Moreover, the capacitor 12 additionally disposed in the circuit structure is charged up to Vos so as to serve as a load of the operational amplifier 8 in this circuit system. In the conventional example of Fig. 2A, only the capacitor 11 functions as the load. In comparison therewith, in the circuit in accordance with the present invention, the capacitor 12 also functions as the load. Namely, the total load is increased to C + C L . Subsequently, when the switches 6 and 7 are on, also like in the conventional example of Fig. 2B, the capacitors 10 and 11 are charged up to voltages Vos and Vos - Vout, respectively. Under this condition, the capacitor 12 is kept at Vos, namely, in the charged state thereof developed when the switches 3 to 5 are on, which hence is not related to signal transfer at all. In consequence, the capacitor 12 of the circuit does not exert any influence upon signal transfer, i.e., transfer of charge at all. Namely, only when the operational amplifier 8 functions as a unity gain buffer, the capacitor 12 serves as the load. Consequently, the phenomenon of oscillation is suppressed. As described above, in accordance with the present invention. the switched capacitor amplifier circuit of the offset cancellation type includes a capacitor between a reverse input terminal of an OTA-type operational amplifier and a reference voltage source. Consequently, a load is imposed on an output from the operational amplifier only when there is conducted an operation to cancel the offset voltage, which leads to an advantageous effect of suppression of the phenomenon of oscillation.

Claims: A switched capacitor amplifier circuit in which an offset voltage is cancellable, said circuit including an operational amplifier (8) provided with a reverse input terminal (-) for receiving an input voltage (Vin) and a non-reverse input terminal (+) connected to a reference voltage (9), said operational amplifier (8) amplifying a voltage difference between the input voltage (Vin) and the reference voltage (9) to provide an output voltage (Vout) to an output terminal (2) of said circuit, so that said circuit has at the output terminal (2) thereof the offset voltage due to the voltage difference, characterized by: a capacitor (12) added to said operational amplifier (8) and connected between the reverse input terminal (-) and the reference voltage (9) so that said capacitor (12) serves as a load for said operational amplifier (8) only when the offset voltage is cancelled in said circuit. The circuit as claimed in claim 1, further comprising: another capacitor (10) connected between the reverse input terminal (-) of said operational amplifier (8) and a signal input terminal (1) of said circuit: a first switch (3) interconnected between said another capacitor (10) and the signal input terminal (1) of said circuit; a second switch (6) connected between an interconnection between said another capacitor (10) and said first switch (3), and the reference voltage (9): still another capacitor (11) connected between the reverse input terminal (-) of said operational amplifier (8) and the output terminal (2) of said circuit: a third switch (4) connected between the reverse input terminal (-) of said operational amplifier (8) and the output terminal (2) of said circuit: a fourth switch (7) interconnected between said still another capacitor (11) and the reverse input terminal (-) of said operational amplifier (8); a fifth switch (5) connected between an interconnection between said fourth switch (7) and said still another capacitor (11), and the reference voltage (9): a first switch group (3, 4, 5) including said first (3), said third (4), and said fifth switch (5); and a second switch group (6, 7) including said second (6) and said fourth switch (7), said first (3, 4, 5) and said second switch group (6, 7) being either operative to turn on and off in accordance with both of a first clock signal (A) and a second clock signal (B) that are separated from each other and shifted from each other by half a period thereof. The circuit as claimed in claim 1 or 2, wherein said operational amplifier (8) comprises an operational-transconductance amplifier. A switched capacitor amplifier circuit including: an operational-transconductance amplifier (8) having a reverse input terminal (-), and a non-reverse input terminal (+) connected to a reference voltage (9); a first capacitor (10) connected to the reverse input terminal (-) of the amplifier (8); a first switch (3) connected between the first capacitor (10) and a signal input terminal (1) of said circuit; a second switch (6) connected between the first capacitor (10) and the reference voltage (9); a third switch (4) connected between the reverse input terminal (-) of the amplifier (8) and an output terminal (2) of said circuit; a fourth switch (7) and a second capacitor (11) serially connected between the reverse input terminal (-) of the amplifier (8) and the output terminal (2) of said circuit in parallel with the third switch (4); a fifth switch (5) connected between an interconnection between the fourth switch (7) and the second capacitor (11), and the reference voltage (9), a first switch group (3, 4, 5) including the first (3), the third (4), and the fifth switch (5); and a second switch group (6, 7) including the second (6) and the fourth switch (7), the first (3, 4, 5) and the second switch group (6, 7) being operative to turn on and off in response to a first clock signal (A) and a second clock signal (B), respectively, the first (A) and the second clock signal (B) being shifted from each other by half a period thereof and being separated from each other. wherein said circiut is characterized by a third capacitor (12) connected between the reverse input terminal (-) of the amplifier (8) and the reference voltage (9) so that the third capacitor (12) serves as a load of the amplifier (8) only when said circuit achieves cancellation of an offset voltage.

Inventors: TATSUMI SATOSHI, TATSUMI, SATOSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H03F3
IPC codes: H03F3, H03H19, G11C27