System for monitoring and controlling motor vehicle running condition

Abstract: A system for monitoring and controlling a running condition of a motor vehicle such as a motorcycle has a wheel speed sensor (16,16a) and first (62) and second (64) CPUs. The first (62) and second (64) CPUs effect in a first mode, i.e., when an anti-lock brake control mode is not effected, the same calculations to produce calculated data to monitor the running condition of the motor vehicle, and compare the calculated data from each other to check the effected calculations. In a second mode, i.e., when the anti-lock brake control mode is effected, the first CPU (62) continues the calculations to produce calculated data to monitor the running condition of the motor vehicle, and the second CPU (64) performs an auxiliary controlling function for controlling the running condition of the motor vehicle by controlling a brake mechanism in the anti-lock brake control mode.

Description: The present invention relates to an anti-lock braking control system for monitoring and controlling a running condition of a motor vehicle as stated in the precharacterizing part of claim 1. Such systems for use with motor vehicles such as motorcycles, for example, determine an estimated vehicle speed, an estimated vehicle deceleration, wheel acceleration and deceleration, and a slip rate from a wheel speed detected by a vehicle speed sensor for monitoring a motor vehicle running condition. The motor vehicle running condition monitoring systems have two CPUs for carrying out the same operation, and the two CPUs produce output signals that are compared with each other to check their operation for errors. The output signals from the two CPUs are always compared with each other only for the purpose of confirming the monitoring operation. Another controlling function, such as a brake controlling operation, that needs a shorter loop time than the loop time for monitoring a motor vehicle running condition is required to be carried out by another CPU than those for monitoring the motor vehicle running condition. Therefore, the number of CPUs installed on the motor vehicle is increased. Such a motor vehicle running condition monitoring system is disclosed in Japanese laid-open patent publication No. 3-217364, for example. From EP-A-0 496 509 an anti-lock braking control system is known which has speed sensors for detecting the speed of the vehicle wheels and two control processors for calculating, in a first mode during which anti-lock braking control is not effected, parameters which allow a decision as to whether an anti-lock braking control should be performed. Both control processors perform the same calculations. In order to monitor the possible occurrence of a system failure the calculated parameters are transmitted to an additional processor which compares the calculation results of the control processors for discrepancies. In the anti-lock braking control mode both control processors operate in an identical manner. It is the object of the present invention to provide an anti-lock braking control system for monitoring and controlling a running condition of a motor vehicle, which system is of simple construction and provides high processing speed. According to the present invention this object is achieved by an anti-lock braking control system for monitoring and controlling a running condition of a motor vehicle as defined in claim 1. Particularly advantageous embodiments of the present invention are stated in the subclaims. The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate a preferred embodiment of the present invention by way of example. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a motor vehicle running condition monitoring system according to the present invention; FIG. 2 is a schematic view of a brake controlling device that is controlled by the motor vehicle running condition monitoring system; FIG. 3 is a flowchart of a control sequence of the motor vehicle running condition monitoring system; FIG. 4 is a flowchart of a main routine of the control sequence shown in FIG. 3; and FIG. 5 is a diagram showing the manner in which the motor vehicle running condition monitoring system operates. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The principles of the present invention will be described below as being incorporated in a motor vehicle running condition monitoring system for controlling an anti-lock brake controlling device on a motorcycle. As shown in FIG. 2, a brake controlling device 10 has a control unit 12 for controlling a pressure modulator 14 to control a braking hydraulic pressure for applying an optimum braking force to a motorcycle wheel. The control unit 12 is supplied with pulse signals representing wheel speeds Vw from a front wheel speed sensor 16 and a rear wheel speed sensor 16a that are positioned in the vicinity of a front wheel Wf and a rear wheel Wr, respectively, of the motorcycle. The control unit 12 has various calculating and deciding functions for performing desired calculations and decisions. A brake mechanism 18 comprises a brake lever 22 mounted on a steering handle 20, a master cylinder 24 actuatable by the brake lever 22 for producing a hydraulic pressure, and a caliper cylinder 26 for braking the front wheel Wf based on the hydraulic pressure produced by the master cylinder 24. The master cylinder 24 and the caliper cylinder 26 are hydraulically connected to each other by the pressure modulator 14. The master cylinder 24 regulates the hydraulic pressure under the control of the brake lever 22, and transmits the regulated hydraulic pressure to a cut-off valve 54. The caliper cylinder 26 applies a braking force to a disk plate 28 coupled to the front wheel Wf based on the hydraulic pressure that is controlled by the cut-off valve 54. The pressure modulator 14 for the front wheel Wf has a front motor driver 32 for energizing a front motor 30 in the form of a DC motor. The front motor driver 32 is electrically connected to the control unit 12 and supplied with an electric signal therefrom. The front motor 30 has a drive shaft to which there is connected a pinion 34 that is held in mesh with a gear 36. The gear 36 is fixedly mounted on a crankshaft 38 having one end connected through a crank arm 40 to one end of a crankpin 42. The other end of the crankpin 42 is connected to a crank arm 44 which is coupled to a potentiometer 46 for detecting the angular displacement of the crankpin 42. A cam bearing 48 and a bearing 49 are rotatably mounted on the crankpin 42 coaxially with each other. The cam bearing 48 is normally urged to move upwardly by a return spring 50 that acts on the bearing 49. The cam bearing 48 has an upper surface held against a lower end of an expander piston 52 which can be vertically moved by the cam bearing 48. The cut-off valve 54 is connected to the expander piston 52 and can be opened and closed as the expander piston 52 is lifted and lowered. The cut-off valve 54 has an upper input port 58 held in communication with the master cylinder 24, and a valve casing 56 joined at its lower end to the expander piston 52. The cut-off valve 54 also has a lower output port 60 defined between the valve casing 56 and the expander piston 52 and held in communication with the caliper cylinder 26. The input port 58 and the output port 60 communicate with each other through a communication hole 61 defined around a valve body of the cut-off valve 54. The rear wheel Wr is associated with a pressure modulator 14a hydraulically connected between a master cylinder 24a coupled to a brake pedal 23 and a caliper cylinder 26a connected to a disk plate 28a that is coupled to the rear wheel Wr. The pressure modulator 14a is structurally and functionally identical to the pressure modulator 14, and will not be described in detail below. As shown in FIG. 1, the control unit 12 comprises a first CPU 62 and a second CPU 64 each connected to a fail-safe relay 66 and an indicator 68. The fail-safe relay 66 cuts off electric energy supplied from a power supply 65 to the front motor drivers 32, 32a when the front wheel speed sensor 16, the rear wheel speed sensor 16a, the front motor driver 32, the rear motor driver 32a, the potentiometer 46, the potentiometer 46a, the CPU 62, or the CPU 64 suffers an operation error. A control process carried out by the brake controlling device 10 will be described below with reference to FIGS. 3 and 4. As shown in FIG. 3, when the power supply 65 is turned on, the first CPU 62 and the second CPU 64 are initialized in a step S1. Then, a flag is set to cause one of the CPUs 62, 64 to be recognized as a main CPU and the other as an auxiliary CPU in a step S2. In this embodiment, the CPU 62 is recognized as a main CPU and the CPU 64 as an auxiliary CPU. Then, a step 3 determines whether an initial diagnostic process such as for checking a battery voltage is to be carried out. If the initial diagnostic process is carried out, a step S4 confirms that the fail-safe relay 66 is turned off. If normal, i.e., if the fail-safe relay 66 is turned off, then it is turned on in a step S5. Then, front and rear wheel speeds Vw are read from the front and rear wheel speed sensors 16, 16a into the first and second CPUs 16, 16a in a step S6. When each of the front and rear wheel speeds Vw becomes equal to or higher than a predetermined speed Vs in a step S7, a step S8 determineS whether the front motor 30, the rear motor 30a, the potentiometer 46, the potentiometer 46a, the front motor driver 32, and the rear motor driver 32a operate normally or not. Crankpin angular displacements ϑ are detected by the potentiometers 46, 46a and transmitted to the other potentiometers 46a, 46 in mutual communications for zero setting in a step S9. After the above initial diagnostic process, control goes to a main routine in a step S10. The main routine in the step S10 will be described below with reference to FIG. 4. In the main routine, it is assumed that the CPU 62 operates as a main CPU and the CPU 64 as an auxiliary CPU. In a step S21, the CPUs 62, 64 confirm that they are main and auxiliary CPUs, respectively, based on the flag set in the step S2. Subsequently, the CPU 62 operates as a main CPU and the CPU 64 as an auxiliary CPU. The CPUs 62, 64 communicate flags (described below) with each other in a step S22. If a fail flag is set in a step S23, then a fail-safe process is carried out in a step S24. For example, if the system is in an anti-lock brake control mode, then the fail-safe relay 66 turns off the electric energy supplied from the power supply 65 to the front and rear motor drivers 32, 32a, switching the brake control from the anti-lock brake control mode effected by the pressure modulators 14, 14a to the canceling of the anti-lock brake control mode. If the fail flag is not set, then a step S25 determines whether a main flag is set or not. If the main flag is set, then the first CPU 62 determines in a step S26 whether a modulator control (MC) flag is set or not, i.e., the anti-lock brake control mode is to be effected by the pressure modulators 14, 14a or the anti-lock brake control mode is to be canceled. If the anti-lock brake control mode is to be canceled, then the first CPU 62 as the main CPU calculates an estimated vehicle speed, an estimated vehicle deceleration, wheel acceleration and deceleration, and a slip rate from the wheel speeds Vw detected by the front and rear wheel speed sensors 16, 16a, and, if it determines based on the slip rate that the anti-lock brake control mode is to be effected, the first CPU 62 set the MC flag and carries out main calculations to calculate a target crankpin angular displacement (target angle T) in a step S27. At this time, the second CPU 64 as the auxiliary CPU operates substantially in the same manner. Thereafter, the first and second CPUs 62, 64 communicate data including the slip rate, the estimated vehicle speed, etc. with each other to determine whether the data are different from each other or not, i.e., some failure has occurred or not, in a step S28. The step S28 also determines whether the front motor 30 and the potentiometer 46 of the pressure modulator 14 have failed or not. If some failure is confirmed, then the fail flag is set in the step S28. After elapse of a predetermined loop time t1 set by a timer 1 in a step S29 (Timer 1 = t1), a reset signal is applied to reset a watchdog timer in a step S30. Thereafter, control returns to the step S21. If the main flag is not set in the step S25, then the second CPU 64 determines in a step S31 whether the MC flag is set or not, i.e., the anti-lock brake control mode is to be effected or canceled. If the anti-lock brake control mode is to be canceled, then the second CPU 64 executes the steps S27 through S30 in the same manner as the first CPU 62. Therefore, insofar as the anti-lock brake control mode is canceled, the first and second CPUs 62, 64 operate in the same manner as each other, and communicate calculated data with each other in the step S28 to effect a diagnostic process at all times for checking the operation of the CPUs 62, 64 for errors. If the anti-lock brake control mode is to be effected, i.e., if the MC flag is set in the steps S26, 31, then the CPUs 62, 64 operate as follows: The first CPU 62 outputs the target angular displacement T for the crankpin 42, which has been determined in the step S27 in the preceding cycle, to the second CPU 64 in a step S32. The second CPU 64 then executes the steps S27 through S30 as is the case when the anti-lock brake control mode is canceled. The second CPU 64 reads the target angular displacement T from the first CPU 62 in a step S33. Then, the second CPU 64 energizes the front motor 30 based on the target angular displacement T and the angular displacement  read from the potentiometer 46 according to a proportional plus integral plus derivative (PID) control process in a step S34. More specifically, the front motor driver 32 energizes the front motor 30, which causes the pinion 34 and the gear 36 to rotate the crankshaft 38, thereby angularly displacing the crankpin 42 and the cam bearing 48. The return spring 50 is compressed against its own resiliency, lowering the expander piston 52 to enable the cut-off valve 54 to close the communication hole 61. The master cylinder 24 and the caliper cylinder 26 are now brought out of communication with each other. The front motor 30 is further energized to lower the expander piston 52 to increase the volume of the output port 60, thereby lowering the hydraulic pressure transmitted to the caliper cylinder 26 to obtain a suitable braking force. The pressure modulator 14a and the caliper cylinder 26a are controlled in the same manner as described above. After elapse of a predetermined loop time t2 set by a timer 2 in a step S35 (Timer 2 = t2), the steps 34, 35 are repeated until the loop time t1 set by the timer 1 elapses in a step S36 for thereby synchronizing the first and second CPUs 62, 64. In this embodiment, the loop time t1 is selected to be four times the loop time t2 (t1 = 4 x t2). Therefore, the second CPU 62 repeats the motor control step S34 four times according to the PID control process while the first CPU 62 loops through the steps S27 through S29 (see FIG. 5) to effecting its own monitoring process. Thereafter, a reset signal is outputted to the watchdog timer in the step S30, causing the first and second CPUs 62, 64 to execute the parallel processing from the step S21. As described above, when the anti-lock brake control mode is canceled, the first and second CPUs 62, 64 operate in the same manner as each other, and they communicate their calculated data with each other for checking their operation for errors. When the anti-lock brake control mode is to be effected in the step S31, the first and second CPUs 62, 64 operate differently from each other. That is, the first CPU 62 outputs the target angular displacement T to the second CPU 64, which effects a PID control process to control the front motor 30 to produce an optimum braking force based on the supplied target angular displacement T and the crankpin angular displacement  that is read in each cycle. Since the loop time t2 of the second CPU 64 is shorter than the loop time t1 of the first CPU 62 (t1 = 4 x t2), the second CPU 64 can control the motor 30 with high accuracy. Inasmuch as the first and second CPUs 62, 64 are assigned to the data calculation and the motor control, respectively, no other CPU is required to be added. The loop times of the first and second CPUs 62, 64 are monitored by the watchdog timer. While the first CPU 62 is used as the main CPU and the second CPU 64 as the auxiliary CPU, the first CPU 62 may be used as the auxiliary CPU and the second CPU 64 as the main CPU. Although a certain preferred embodiment of the present invention has been shown and described in detail, it should be understood that various changes and modifications may be made therein without departing from the scope of the appended claims.

Claims: An anti-lock braking control system (10) for monitoring and controlling a running condition of a motor vehicle, comprising: detecting means (16, 16a) for detecting the running condition of the motor vehicle; first and second processing means (62, 64) switchable between a first mode during which anti-lock braking control is not effected, and a second mode during which anti-lock braking control is effected, said first and second processing means (62, 64) performing in said first mode the same calculations to produce calculated data on the basis of the detected running condition to monitor the running condition of the motor vehicle, characterized in that said first and second processing means (62, 64) are further adapted to compare the calculated data produced by the first processing means (62) and the calculated data produced by the second processing means (64) in order to confirm said calculations; and in that the anti-lock braking control system (10) further comprises function distributing means (MAIN flag, MC flag) for switching the first and second processing means (62, 64) to the second mode, said first processing means (62) performing, in said second mode, said calculations to produce calculated data of the detected running condition to monitor the running condition of the motor vehicle, and said second processing means (64) performing, in said second mode, an auxiliary controlling function to control the running condition of the motor vehicle, said function distributing means (MAIN flag, MC flag) being enabled to switch said first and second processing means (62, 64) to said second mode when said calculations are confirmed by said first and second processing means (62, 64). The anti-lock braking control system (10) according to claim 1, characterized in that said motor vehicle is a motorcycle. The anti-lock braking control system (10) according to claim 2, characterized in that, in said first mode, each of said first and second processing means (62, 64) calculates an estimated vehicle speed, an estimated vehicle deceleration, wheel acceleration and deceleration and a slip rate, based on rotational speeds of front (Wf) and rear (Wr) wheels of the motorcycle detected by said detecting means (16, 16a), and in that, in said second mode, said second processing means (64) calculates a target crankpin angular displacement (T), based on the slip rate, for an anti-lock brake controlling device (32, 30). The anti-lock braking control system (10) according to claim 3, characterized in that said auxiliary controlling function is to control a front motor (30) in the anti-lock brake controlling device (32) to produce a suitable braking force through a proportional, integral and derivative (PID) control scheme based on said target crankpin angular displacement (T) and a detected crankpin angular displacement (). The anti-lock braking control system (10) according to claim 1, characterized in that, in said second mode, one (64) of said first and second processing means (62, 64) has a loop time which is a multiple of the loop time of the other (62) of said first and second processing means (62, 64), and that, in said first mode, said first and second processing means (62, 64) have the same loop time.

Inventors: AKAI AKINORI, HAYASHI TATSUO, MATSUTO TAKUSHI, OTA ATSUO, AKAI, AKINORI, HAYASHI,TATSUO, MATSUTO, TAKUSHI, OTA, ATSUO, Akai, Akinori, c/o NEC Home Electronics Ltd., Hayashi,Tatsuo, c/o Honda Gijyutsu Kenkyusho, Matsuto, Takushi, c/o Honda Gijyutsu Kenkyusho, Ota, Atsuo, c/o Honda Gijyutsu Kenkyusho
Applicants: HONDA MOTOR CO LTD, NIPPON DENKI HOME ELECTRONICS, HONDA GIKEN KOGYO KABUSHIKI KAISHA, NEC HOME ELECTRONICS, LTD.
Application year: 1993
Main classification: B60T8
IPC codes: B60T8