Semiconductor memory device

Abstract: The semiconductor memory device is improved by forming a capacitance being necessary for allowing a high-speed operation without the problem of generated noise by arranging a main supply voltage section of a first supply voltage line (Vcc) and a main supply voltage section of a second supply voltage line (Vss) in parallel to each other and sub-supply voltage sections extending from the first and second supply voltage sections, respectively, so as to be engaged with each other.

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device suitable for high speed access. BACKGROUND OF THE INVENTION Conventionally, a semiconductor memory device such as a DRAM has been widely used as a main memory for a personal computer or a mini-computer. The DRAM is generally controlled on the basis of various control signals such as CAS (column address select) signal obtained by processing a clock supplied to operate a CPU. In other words, the clock signal used for the CPU cannot be used as it is; that is, the clock for operating the CPU has been so far processed for controlling the memory device. With the advance of the semiconductor technology, however, the operating frequency of the CPU has recently become higher than that of the DRAM. Therefore, in order to prevent the operating speed of the CPU from being affected by the operating speed of the DRAM, there has been required such complex memory control as using a plurality of assembled DRAMs interleaved therebetween. In the case of a relatively small-scale system such as a mini-computer, work station, etc., however, when a number of memory devices are used under interleaved condition, there exists such a disadvantage that the control system of the memory device becomes complicated and therefore the system cost increases. In addition, since the operating frequency of the CPU has been increased up to 50 MHz and further to 100 MHz, it is necessary to construct the memory device hierarchically, thus raising a problem in that the control of the memory system becomes increasingly complicated and thereby the system load has been increased. Further, there exists the problem that in high-speed operation noise generated at the supply voltage line and the ground line will deteriorate the device performance. Thus, conventionally a capacitor is formed between the supply voltage and the ground line to absorb noise. In the conventional method, the capacitor is additionally provided inside the chip so that the dead space in the chip increases with increasing capacitance of the chip. US-A-4 980 799 discloses a bank or block divided semiconductor memory device. The memory device comprises usual features of a bank divided semiconductor memory like memory banks, address designating means, I/O buffer means, address and I/O control means and first and second supply voltage lines. In addition, the first and second supply voltage lines are arranged in respective main supply voltage sections in parallel to each other and supply voltage sections extending from the main supply voltage sections are arranged so as to be engaged with each other. As it is known from Fig. 9 of US-A-4 980 799, it will be necessary to provide an additional capacitor area. EP-A-0 481 437 relates to bank divided memories with interleaving operated memory banks. SUMMARY OF THE INVENTION It is the object of the present invention to provide a semiconductor memory device having supply voltage lines arranged in such a way that noise absorption capacitance can be easily provided. This object is solved by a semiconductor memory device as described in claim 1. Claims 2 to 4 show advantageous further developments of the semiconductor memory device of claim 1. According to the semiconductor memory device of the present invention it is possible to obtain capacitors without concentrating the capacitor in the circuit blocks and without providing an additional capacitor area. The semiconductor memory device of the present invention is simple in configuration and can well cope with a high speed CPU, by allowing the CPU and the memory device (e.g., DRAM) to be controllable by only a single clock. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention; Fig. 2 is a floor map for assistance in explaining the arrangement of the respective circuit systems; Fig. 3 is an illustration for assistance in explaining the conventional noise countermeasures; Fig. 4 is a diagram showing an arrangement of the circuit blocks for noise countermeasures according to the present invention; and Fig. 5 is a diagram showing an arrangement of the capacitors connected between the voltage supply line Vcc and the ground line Vss. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The embodiment of the present invention will be described hereinbelow with reference to the attached drawings. Prior to the detailed description of the embodiments of the present invention, the gist thereof will be summarized as follows: The object of the embodiments is to provide a high operating speed memory device usable with a high operating speed CPU. The method of realizing the above-mentioned gist is to reduce supply voltage noise at high speed operation, the supply voltage lines are arranged in such a way that noise absorption capacitance can be easily provided between two supply voltages. Fig. 1 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention. In Fig. 1, the column system of the memory cell is divided into two of a memory cell array 17 and a memory cell array 18. On the other hand, a clock CLK the same as supplied to a CPU is supplied to a control circuit 1. In addition to the clock CLK, a chip enable signal CE, a read write latch signal RWL, a clock mask signal CM, and a read/write status signal R/W are inputted from the CPU to the control circuit 1. Further, an address A0 to A9 including a row address and a column address, and an inversion signal of an output enable signal OE are both inputted from the CPU to the column system of the memory cell. The output enable signal OE is inputted to the control circuit 1 as an inversion signal of a signal BM and/or an inversion signal of a refresh signal RFSH. Two row address circuits 5 and 6 are both operative in response to the control signal applied from the control circuit 1. The row address circuit 5 or 6 acquires a row address from the address A0 to A9 and further controls the row address of the memory cell array 17 or 18, respectively. A row address decoder 3 or 4 decodes the row address applied from the row address circuit 5 or 6, and designates the row address of the memory cell array 17 or 18, respectively. On the other hand, a column address serial control circuit 7 or 8 is operative in response to the control signal applied from the control circuit 1, and acquires a column address from the address A0 to A9 and controls the column address of the memory cell array 17 or 18, respectively. A column address counter 9 or 10 shifts the column address forward in sequence by determining the column address acquired by a column address serial control circuit 7 or 8 as the head address, respectively. A column address decoder 11 or 12 decodes the column address generated by the column address counter 9 or 10 and designates the column address of the memory cell array 17 or 8, respectively. Data are inputted and outputted via an input and output circuit 2 to and from the cell designated by the row address and the column address of the memory cell array 17 or 18. The input and output circuit 2 is provided with input and output buffers 13, 14, 15 and 16 each for temporarily storing the input and output data, and connected to external circuits via input and output sections I/O1 to 4, respectively. Further, the inversion signal of the output enable signal OE and the control signals from the control circuit 1 are inputted to the input and output circuit 2. Fig. 2 is a floor map on which various circuit systems described above are arranged, in which the entire circuit arrangement is shown. The middle portion is a row system circuit group, which activates the cell arrays selectively and controls the operation for amplifying and latching the cell data on the bit lines. On both sides thereof, symmetrically interleaved serial systems are arranged. The output circuits, the input circuits and the input and output control circuits are arranged on both the side at which the I/O pins and the control pins are concentrated. Further, the DQ buffers are arranged on both sides. The bit lines, the precharge voltage generating circuit, the cell plate voltage generating circuit and the substrate voltage generating circuit are arranged on one short side of the chip. Further, the bonding pads are arranged on the outer periphery of the chip. By arranging the various circuits as described above, it is possible to simplify the control of the serial system signals by the row system signals. This is because no special wiring is required to transmit the signals from the row system to the serial system. Further, the serial counters and the column partial decoders can be controlled by the serial system circuits without arranging special bus wiring, thus enabling a high speed operation. Further, the signals can be transmitted directly without use of any bus wiring. Therefore, the bus wiring can be eliminated and thereby the chip area can be reduced. Further, it is possible to satisfy the diversified package requirements by providing pad areas for bonding pads. The problem involved in the high speed operation is related to noise generated at the supply voltage line and the ground line, which will deteriorate the device performance. The above-mentioned problem tends to be generated when noise is superimposed upon the voltage supply line and the ground line in different way. In more detail, when noise is superimposed upon the voltage supply line and the ground line is stable against noise at a low supply voltage, the effective voltage applied to the circuit is a voltage obtained by subtracting the noise form the supply voltage. In this case, since the circuit is to be operated by a low voltage, the operational speed is reduced. To overcome the above-mentioned problem, conventionally a capacitor is formed between the supply voltage line and the ground line to absorb noise as shown in Fig. 3. In the conventional method, however, since an area for providing the capacitor area must be additionally provided inside the chip, the dead space in the chip increases with increasing capacitance of the capacitor, thus causing an increase in chip area. To overcome the problem involved in the conventional noise countermeasures as described above, in the semiconductor memory device according to the present invention, the circuit blocks are arranged as shown in Fig. 4. That is, the respective middle portions of the floor map as shown in Fig. 2 are arranged as circuit blocks as shown in Fig. 4, and the supply voltage Vcc and the ground line Vss for the respective blocks are arranged as shown in Fig. 4. Further, capacitors are formed between the supply voltage line Vcc and the ground line Vss as shown in Fig. 5. In this circuit arrangement as shown in Fig. 5, it is possible to obtain capacitors formed between the supply voltage and the ground and distributed uniformly, without concentrating the capacitor in the circuit blocks and without providing an additional capacitor area. In the semiconductor memory device according to the present invention, since the capacitors are formed in the supply voltage area and ground area, the chip area is not increased by forming the capacitors. Further, the distribution and the capacitance of the capacitors can be adjusted easily by cutting off one electrode of the capacitor and further shorting the other electrode thereof. The semiconductor memory device is provided with at least first and second supply voltage lines. The first and second supply voltage lines of the first and second primary supply voltages are arranged in parallel with each other. Further, the secondary supply voltages extending from the respective primary supply voltages are arranged alternately. Capacitance is formed between the primary and secondary supply voltages. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor memory device, comprising: a memory cell array divided into at least two banks (17, 18) with respect to column system; row address designating means (4, 5) for designating a row address to each of said banks (17, 18); column address designating means (11, 12) for designating a column address to each of the banks in serial order; input and output buffer means (13 to 16) for holding input and output data to and from each of said banks (17, 18); address control means (1) for applying a group of input address signals (ROW, COLUMN) to said row address designating means (4, 5) and said column address designating means (11, 12) and for interleaving said memory cell arrays in operation; input and output control means (1) for operating said input and output buffer means (13 to 16) in accompaniment with the operation of said address control means; and at least a first supply voltage line (Vcc) and a second supply voltage line (Vss), wherein a main supply voltage section of the first supply voltage line (Vcc) and a main supply voltage section of the second supply voltage line (Vss) are arranged in parallel to each other; sub-supply voltage sections extending from the first and second supply voltage sections, respectively are arranged so as to be engaged with each other; characterized in that two types of wells are arranged between and alternately along the lines of the first supply voltage line (Vcc) and the second supply voltage line (Vss), on which wells the first sub-supply voltage sections and the second sub-supply voltage sections are formed; and the sub-supply voltage sections of the first supply voltage (Vcc) section are arranged on one of the two types of wells (n-wells) and the sub-supply voltage sections of the second supply voltage (Vss) section are arranged on the other of the two types of wells (p-wells). The semiconductor memory device according to claim 1, wherein the two type of wells comprise n-type wells and p-type wells. The semiconductor memory device according to claim 1 or 2, wherein said respective means are operated by a high supply voltage (Vcc) connected to said first supply voltage line and a low supply voltage (Vss) connected to said second supply voltage line, and the first and second supply voltage lines are formed into a comb-shape, respectively and arranged in such a way that the comb-shaped portions thereof are engaged with respect to each other. The semiconductor memory device according to any of the preceding claims, wherein a capacitance is formed between the two sub-supply voltage (Vcc, Vss) sections, respectively, so that capacitors of one type are formed in one of the two types of wells (n-wells) under the sub-supply voltage sections of the first supply voltage (Vcc) and so that capacitors of another type are formed in the other of the two types of wells (p-wells) under the sub-supply voltage sections of the second supply voltage (Vss).

Inventors: WATANABE YUJI, WATANABE, YUJI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: G11C5
IPC codes: G11C5