Office environment level electrostatic discharge protection

Abstract: An electrostatic discharge protection (ESD) device for a connector associated with an integrated circuit chip, particularly one associated with a thermal ink-jet printhead. A MOS field effect device (60) extends along at least one edge of the connector (32) on the chip. A bipolar transistor (66-70), parasitic to the field effect device (60), conducts current from the connector (32) to ground (52) in response to a voltage between the connector (32) and ground (52) in excess of a predetermined threshold. A zone (90) of a predetermined electrical resistance is operatively disposed between the bipolar transistor (66-70) and ground (52). The zone (90) may substantially encircle (Fig 4) the bonding pad (32) of the connector to evenly distribute local incidences of high voltage. The invention enables integrated circuits to pass ESD requirements of office products, which is 15kV by Human Body Model testing.

Description: The present invention relates to electrostatic discharge protection of electrical components to a level sufficient for handling in an office environment. More specifically, the present invention relates to a technique of emitter ballasting for avoiding a common type of failure in the vicinity of a bonding pad of a thermal ink-jet printhead. Electrostatic discharge (ESD) protection is a common and important requirement for many types of electrical equipment. The familiar "electric shock" experienced by a person touching an object, for example, on a day of low humidity, is just the type of electrostatic discharge which can cause malfunction or damage in any apparatus with sensitive electrical circuitry. A typical discharge caused by touching can be in the range of 10,000 volts, and result in current flow of several amperes for about 1 µsec or less. Such a high voltage applied anywhere to an electrical apparatus designed to be sensitive to small voltages is likely to damage, or at least cause a malfunction of, such an apparatus. One type of electrical apparatus that is sensitive to electrostatic discharges is a thermal ink-jet (TIJ) printhead. Advanced TIJ printers operate by using logic level voltage signals to operate a large number of very small heating elements, which are used to vaporize liquid ink in a corresponding number of small channels or passageways. Thermal ink jet printers are typically designed to have customer-replaceable printheads or print cartridges; ESD protection is necessary to prevent these items from being damaged during handling and machine insertion. In the circuitry for operating an ink-jet printhead, MOS (metal oxide on silicon) technology is often used. Such printhead designs are described, for example, in US-A-5,010,355. A typical resolution of an ink-jet printer is 300 channels or nozzles per inch (11.8 per mm), each nozzle having a voltage-actuable heating element associated therewith. Experimental printheads with much higher resolution have also been made. It is thus clear that such an apparatus will be sensitive to the relatively large voltages which may be externally created by a typical electrostatic discharge. It has been found that a common type of failure associated with electrostatic discharges into a thermal ink-jet printhead occurs around the area of a "bonding pad," through which the printhead is connected to an external electronic device. In a printhead using MOS technology, the inputs of the integrated circuit devices are capacitors whose two electrodes are the MOS transistor device channel and the gate electrode material, usually polysilicon. The two capacitor electrodes are separated by silicon dioxide, which is usually grown on the device channel by high temperature oxidation processes. The MOS transistors use a thin silicon dioxide gate insulator to achieve high performance, and this thin oxide is susceptible to catastrophic, irreversible breakdown if the voltage across the dielectric is raised above 20 to 100 volts, depending on device fabrication details. Numerous conventional systems are known for ESD protection of semiconductor and MOS devices. In general, such circuits use monolithically integrated protective transistors built into the semiconductor circuit to protect the gates of the devices. These protective transistors are arranged to allow a high voltage static discharge transient to pass to ground prior to reaching the protected circuit. For example, US-A 4,990,984 to Misu discloses a conventional protective transistor ESD protection device for an integrated circuit. Such systems have a disadvantage which prevents them from being applied as protection of thermal ink jet printhead input terminals. The conventional protective transistor for the circuit has only a small current carrying capacity, so that ESD surges which are encountered in the office environment will overwhelm the protective transistor, allowing a part of the ESD surge to reach the protected circuit or causing failure of the ESD protection circuit itself. When a typical electrostatic discharge protection device (which would typically be in the form of a transistor circuit adapted to short out excessive voltages at the pad) is employed around the edges of the bonding pad, the excess voltage tends not to be distributed evenly when it discharges from the pad, but rather tends to concentrate in localized "hot spots" at various points around the edge of the bonding pad, where the high voltages associated with electrostatic discharge pass through one very small area. The hot spot occurs because current conduction increases with temperature so that local fluctuations in device conductivity become greatly amplified. The resulting concentration of current in a small portion of the device causes heating and alloying or "spiking" of the aluminum metallization through the silicon/diffused surface region. There is therefore a need for a device which avoids this specific type of electrostatic discharge failure. EP-A-161,446 discloses a protective MOS transistor (Q1) having a parasitic bipolar transistor for discharging to the ground (Vss) an electric charge generated in the semiconductor substrate (19) by application of a surge voltage to a high voltage power supply terminal (18) provided between the ground (Vss) and the high voltage power supply terminal (18) of a semiconductor integrated circuit (16) including a MOS transistor with an LDD structure. The protective MOS transistor (Q1) is formed on the same semiconductor substrate (19) as the semiconductor integrated circuit (16). JP-A-62-36867 discloses an input protection circuit in which a channel region of a field effect transistor of the circuit is formed in a shape which surrounds a pad, so as to form a FET having a large channel. In accordance with the present invention, there is provided an electrostatic discharge protection device bearing the features set out in claim 1. According to another aspect of the present invention, there is provided an improved ink jet printhead having the features set out in claim 7. In the drawings: Figure 1 is a plan view of a bonding pad on a printhead chip, incorporating the features of the present invention therein; Figure 2A is an enlarged sectional elevational view of a field-oxide device according to the present invention, taken along the line 2A-2A in Figure 1 in the direction of the arrows; Figure 2B is a schematic diagram showing the elements of the field-oxide device of Figure 2A; Figures 3A and 3B are schematic approximations of a resistance associated with a field-oxide device according to the present invention; and Figure 4 is a plan view of a bonding pad incorporating a preferred embodiment of the present invention; and In the Figures, like reference numerals indicate like elements, whether in physical views or schematic diagrams. The electrostatic discharge protection device according to the invention is advantageously employed in an ink-jet printhead. US-A-5 010 355, A shows, an enlarged sectional elevational view of an ink-jet printhead 10 incorporating MOS technology. It should be understood that the above description of a thermal ink-jet printing apparatus is given to demonstrate one possible context for the ESD protection device of the present invention, and that other contexts in which the device of the present invention is useful will be apparent in any type of apparatus in which ESD protection is desirable. The present invention is especially valuable for protection of microelectronic devices which are incorporated into customer or field replaceable units of any kind. ESD events typically occur when a person's body becomes highly charged and the individual then touches a grounded object and discharges. The discharge is very similar to the discharge of a capacitor. One commonly-used paradigm for ESD events is called the "Human Body Model," or HBM. An HBM ESD event is simulated by discharging a 100 pF capacitor through 1.5 kΩ resistance, and the time constant for discharge is about 150 nsec. Therefore, the ESD event is of short duration and high current flow. ESD testing of a device would typically consist of charging up the capacitor to increasingly higher voltages and discharging it through the device until the device fails. It has been found that a common location for experiencing the effects of electrostatic discharge on a MOS-type printhead is in the area around the bonding pad 32 at the site of the connection to external circuitry by wire bond 11, although other sites within any apparatus where ESD protection would be advisable will be apparent to one skilled in the art. A high voltage experienced at this point is capable of heating the aluminum electrode material of bonding pad 32, and causing an electrical short to the substrate. In order to avoid damage to the printhead, it is necessary to avoid such high-voltage potentials at the bonding pad 32, or else to re-route the current caused by an external electrostatic discharge so that the voltage will not build up on the pad, but rather be safely grounded away form the printhead circuitry, such as into lower substrate 28 and then to ground metallization elsewhere on the surface of the chip. In particular, it is necessary to avoid "hot spots," or localized areas of high current flow, which cause localized overheating and damage in the chip. Figure 1 shows the bonding pad 32, by which the circuitry of the printhead is connected to an external device, as viewed on the surface of a printhead chip. On a typical printhead chip, there may be a large plurality of such bonding pads 32 for external connections. A bonding pad 32 will typically include a lead such as electrode 33 extending therefrom to connect with circuitry as needed in the printhead. A typical dimension of such a bonding pad 32 would be a square of 100 micrometers on a side. The bonding pad 32 is, in a typical MOS arrangement, in the form of a layer of aluminum, etched and situated on oxide grown on a silicon substrate, which is shown in Figure 1 as the area marked generally as surface 30. In normal operation, external voltage signals entered on bonding pad 32 will be conducted to further circuitry in the printhead through electrode 33. Electrode 33 may be formed on the surface of the chip, as shown, or may connect to further circuitry on the surface of the silicon itself; i.e., as viewed in Figure 1, by a connection under the bonding pad 32 into the page. Also on the printhead chip, typically generally around the bonding pads 32, is a ground area indicated as 52. Ground 52, etched into the surface 30, will include one or more ground contacts, shown as 54, which connect to ground, in the form of, for example, heater plate 28, from which the silicon layer surface 30 is disposed. One purpose of the present invention is to prevent any externally-produced discharge voltages, such as from a typical "static shock" from a human finger, from affecting or damaging any circuitry in the printhead. External high voltages appear as the area around bonding pad 32. The apparatus of the present invention thus protects the circuitry of the printhead, including the bonding pad 32 itself, by restricting the voltage at the bonding pad 32 to be at or below a predetermined amount. If the voltage exceeds the predetermined level, the pads becomes highly conductive and discharges directly to ground thereby limiting the voltage applied to the circuitry through the addressing electrode 33. In order to accomplish this discharge protection, means defining a MOS field-effect device are provided around the perimeter of the bonding pad 32 and a ground surface 52. The existence of parasitic bipolar transistors with MOS devices is well-known. More significantly, the MOS field-effect device will have associated therewith a "parasitic bipolar" which functions as a highly conductive path to ground once the voltage applied to the input pad exceeds a value fixed by the design and process sequence. This parasitic transistor is so configured that, in response to a voltage at the bonding pad 32 in excess of a predetermined amount, the transistor will create a connection between bonding pad 32 and ground 52 so that the excess voltage is redirected to ground and not into the circuitry associated with the printhead (or with any other type of apparatus to be protected). As can be seen in Figure 1, when the structure of the present invention is viewed from above, as through a microscope, the structure of the transistor appears as the elongated ovals shown generally as 60, which are the field oxide devices. The structure corresponding to these ovals is important to one aspect of the invention, and the preferred configuration of a transistor according to the present invention is to at least extend an appreciable distance along an edge (or many edges) of the bonding pad 32. Figure 2A is a sectional, elevational view along the line 2A-2A in the direction of the arrows in Figure 1, showing the structure of the MOS field-oxide device and associated lateral parasitic bipolar transistor, disposed between the bonding pad 32 and the ground surface 52, along at least one edge of bonding pad 32. As viewed in the cross section of Figure 2A, the field oxide device generally indicated as 60 includes a number of layers, which shall be described from top to bottom: the top layer comprises the conductive portions of bonding pad 32 and ground surface 52, which in the preferred embodiment are made of aluminum. A gap 62 exists between the bonding pad 32 and ground surface 52 so that there will not be any direct connection therebetween, which would of course short out the bonding pad 32. Beneath the top conductive layer is an oxide layer 64. This layer 64, typically made of silicon dioxide, is at least several 100nm thick as shown, in the region of the field oxide device for reasons which will be explained below. Underneath the oxide 64 are some important elements of the field oxide device 60; such as a drain 66, a source 68, and a channel 70, in the form of a p doped "channel stop implant." When parasitic bipolar conduction is excited, the drain 66 also serves as a collector of electrons, and source 68 serves as an emitter of electrons, while the bipolar base is the p-type substrate and associated, more heavily doped channel stop near surface region. In the embodiment shown, the collector 66 is created by an area of silicon that is n' doped, adjacent the bonding pad 32; and the emitter is created by an n' doped area adjacent the surface ground 52. The base of the transistor is a p doped area directly underneath the thick portion of the oxide, shown as 64, formed from the channel stop. In order to complete the connections to the transistor from bonding pad 32 to ground metallization 52, a via 72 is provided to connect the bonding pad 32 to collector 66, and another via 74 is provided to connect the emitter 68 to ground surface 52. Resistance zone 90, shown as a shaded area in Figure 2A, is an addition to the field effect device 60, and will be described in detail below. The ESD protection device of the present invention for bonding pad 32 is properly understood as a "parasitic bipolar" in association with the field oxide device 60. In any MOS device such as field oxide device 60, a lateral bipolar transistor is present in the substrate. In the preferred embodiment of the present invention, the bipolar transistor is exploited for ESD protection. Figure 2B is a schematic diagram in which the field oxide device generally shown as 60 is shown separate from and parallel to the parasitic bipolar transistor. In Figures 2A and 2B, like reference numerals indicate like elements. As can be seen in Figure 2B, the collector 66, base 70, and emitter 68 of the bipolar form a transistor parallel with the field oxide device 60. The emitter 68 of the bipolar is the same as the source of the MOSFET; the collector 66 of the bipolar is the same as the drain of the MOSFET; and the base 70 of the bipolar is the substrate on which the field oxide device 60 is formed. Thus, for purposes of the present invention, the characteristics of the field oxide device 60 itself is less important than the characteristics of the bipolar which is parasitic thereto. The goal is for a large ESD event on bonding pad 32 to be discharged through the parasitic bipolar, and not damage the circuit so as to interfere with the subsequent signals passing through bonding pad 32 for purposes of operating the printhead. A second goal is to limit the voltage seen on pad 32 to be less than about 30V so as to prevent rupture of gate oxide in circuits connected to pad 32. It is well known that bipolar devices are capable of conducting far larger currents than MOSFET's, especially MOSFET's with thick gate oxides such as layer 64. In fact, the input protection circuit 60 will operate equally well when the pad 32 is not present over oxide layer 64, in which case there is no MOSFET conduction whatsoever. The biploar parasitic transistor of the present invention will permit conduction from bonding pad 32 to ground metallization 52 when there is a sufficiently high voltage at bonding pad 32. This connection will be made from bonding pad 32 through via 72, collector 66, base 70, emitter 68, and via 74, to surface ground 52. Ordinarily, when there is not a high potential on the bonding pad 32, signals applied to the bonding pad 32 will be sent, as intended, through electrode 33 in Figure 1 to control in the desired way, the circuitry of the printhead. When a high voltage appears on bonding pad 32, such as a result of an external electrostatic discharge, a significant charge (here shown as a positive charge) will appear as a concentration of positive charge at the area immediately above oxide 64, as shown by the plus symbols in Figure 1. This charge on bonding pad 32 in turn creates a concentration of mobile channel electrons in the channel 70, on the opposite side of oxide 64. As is known in the art of MOS technology, this concentration of electrons in the p doped region 70 will cause the MOSFET to become conductive. The arrows 80 shown passing through the channel 70 represent the passage of electrons from source 68 to drain 66. Thus, the connection is formed from bonding pad 32 through transistor 60 to ground surface 52 when a sufficiently high potential is created at bonding pad 32. The large positive charge on bonding pad 32 causes a channel electron current in the channel 70, on the opposite side of oxide 64. This channel current 70 encounters a high electric field region at the junction between the channel and the drain and the electrons undergo impact ionization to create a hole current flow, indicated in Figure 2A as drain junction 67. The hole current flow can also be initiated by avalanche breakdown of the drain to substrate junction 67. As the bias on the drain continues to increase, the hole current flow increases due to the higher rate of impact ionization. The hole current must travel to a point distant from the generation point 67 to be collected. As a result of hole current flow through the resistive substrate, the potential in the vicinity of the device increases until the substrate 70 becomes forward biased with respect to the source 68. Electrons in the source (emitter) 70 begin to flow toward the drain (collector) 66. The flow of electrons due to bipolar transistor action generates further holes at the drain junction high field region 67, and these excess holes flow to ground through the substrate 65. The flow of electrons out of the drain junction thus creates a cyclical effect, whereby the holes created by the flow of electrons from the source 68 serve to continue to keep base 70 forward biased. For a more detailed description of the function of the field oxide device 60 and the parasitic bipolar, reference is made to European Patent Application EP 0 569 219 A falling under Art. 54(3) EPC. The parameters of the field oxide device 60, such as the physical thickness of oxide layer 64, or the concentration and dimension of the dopants in the substrate 65, are chosen for particular desired characteristics. One important characteristic is the voltage that is required to activate the field oxide device 60; that is, the threshold at which the bonding pad 32 becomes clamped and is prevented from damaging the circuitry of the printhead. In typical applications of a thermal ink jet printhead, this threshold is usually between 5 and 24 volts. The specific parameters of the field oxide device 60 are thus chosen accordingly. An important design consideration for a transistor of the present invention is the maximum possible ESD current surge that may be passed through the field oxide device 60 before failure thereof. As mentioned above, the dominant failure associated with high voltages, such as would result from external electrostatic discharges, are "hot spots" causing physical damage at points along the edges of the bonding pad 32. The "hot spot" failure is generally the result of aluminum metallization alloying and junction spiking between the pad metallization 32 and diffusion 66 at the via contact 72. Spiking occurs when the aluminum metallization migrates through the diffusion region 66 and contacts the substrate 70, thereby shorting the pad to ground. Spiking is driven by high temperatures. In a practical embodiment of bonding pad 32, the via 72 is a long contact extending substantially the length of each edge of the bonding pad (i.e., extending out of the page in the cross-section of Figure 2A). The aluminum-to-silicon contact between conductor 72 and the diffusion on collector 66 has been known to be a common source of physical failures, such as alloying and spiking between conductor 72 and the diffusion on collector 66. Bipolar conduction processes are liable to cause very localized points of high temperature along the edge of bonding pad 32, which in turn are likely to result in junction alloying and spiking. Generally, it has been found that a key determinant of failure voltage in a field oxide device such as 60 is the distance between via 72 and the drain junction 67, the distance marked d in Figure 2A. Within certain practical ranges, the greater the distance d , the higher the failure voltage allowable by the field oxide device 60. When the via 72 is near the avalanche breakdown region, the via is heated and alloying results. When the via is moved far away from the breakdown region, the contact resistance of the via itself can be the cause for heating and alloying between the metal and diffusion region of the silicon. In one test, the failure voltage of a field oxide device increased substantially linearly from about 7,000 volts to 12,000 volts (HBM) as d increased from 4.5 to 10 micrometers. One disadvantage of a large d , however, is that significant capacitance is created between the diffusion 66 and the substrate 80. This capacitance may have the effect of acting as a low pass filter for signals entering the printhead circuitry through bonding pad 32. An important function of the present invention is to ensure the even distribution of current flow along the field oxide device 60 through the elongated via 72, so as to avoid these failure causing current hot spots. This type of failure is addressed by the emitter ballasting feature of the present invention. A second method of avoiding failures will be discussed later. To illustrate the concept of emitter ballasting in the context of the present invention, attention is directed to Figures 3A and 3B, which are schematic diagrams illustrating the parasitic bipolar as a number of discrete transistors arranged in parallel with the collectors thereof commonly connected to the bonding pad 32 (shown schematically in Figure 3A) and the emitters thereof commonly connected to the surface ground 52. The channel stop implant 70 shown in Figure 2A is shown schematically as a common base of the transistors in Figure 3A. The plurality of discrete transistors are shown to simulate the effect of the continuously-elongated field oxide device 60, as shown in Figure 1 along one edge of bonding pad 32 and ground metallization 52. When an ESD event occurs on bonding pad 32, the localized hot spot can be understood an excess current flow and resultant failure of a single discrete transistor as shown in Figure 3A. In both the schematic circuit and in the actual field oxide device 60, a failure at any single location along the field oxide device 60 will effectively destroy the entire device. Bipolar devices exhibit thermal run away. The thermal run away process occurs because heating of a bipolar device causes further conduction. Therefore, as more current flows through one of the several devices in the discrete example or in a small section of the ESD device in the continuous example, the device will heat and become more conductive. This phenomenon is also referred to as "current hogging." Figure 3B shows the same conception of the field oxide device 60 as in Figure 3A, but with the addition of emitter ballasting, in the form of additional resistances, marked R e , associated with the emitter of each discrete transistor and connecting to the surface ground 52. In a physical manifestation of the emitter ballasting, the discrete resistances R e are in the form of a continuous zone of resistance 90 extending parallel to the edge of bonding pad 32. The purpose of the resistance zone is to ensure a uniform current gain of the parasitic bipolar along the length of the field oxide device 60, and thus create a more even spatial distribution of current along the edge of bonding pad 32. The resistances associated with each discrete transistor, as conceived in Figure 3B, effectively act as a current limit at that particular location (each particular location symbolized by an individual transistor in Figure 3B) along a field effect device 60 between an edge of bonding pad 32 and surface ground 52. The resistance on the emitter is very effective in reducing thermal runaway because as current increases, the voltage drop across the resistor increases and the voltage between the base and the emitter decreases. The base-emitter voltage controls the current flow from emitter to collector, so the emitter ballast resistor acts as a negative feedback loop. Because no particular spot along a field effect device 60 will be able to reach a high current, no hot spot along any particular point of the field effect device 60 will be created, and thus the chance of failure of the device as a whole is lowered. Using the MOS technology of the preferred embodiment of the present invention, there are two preferred ways of creating the necessary resistance R e in the area of the field effect device 60 between the channel stop implant forming base 70 and via 74. One possible technique is simply to increase the distance between the end of base 70 and via 74, thereby increasing the resistance in this area; however, the extension of this resistance has the disadvantages of increasing the necessary "real estate" on a chip. A more effective way of increasing the ballast resistance R e is to include an n- doped area as a high resistance zone at some point between the base 70 and the via 74, as shown by the shaded area marked 90 in Figure 2. The added resistance 90 may be included as a doped area within the small n' doped area of emitter 68, or alternatively may be placed between the edge of base 70 and emitter 68. In experiments with damaged ESD protection devices wherein the failures are caused by the presence of hot spots which are the result of spiking along the length of one edge of the bonding pad 32, it is found that the area of damage caused by the hot spot is often seen in the same place along the oxide devices and while the location of damage is reproducible, it can also be moved around by device design modifications. In some cases, the hot spot, the area of damage to the field oxide device 60, is in the center of the elongated oxide device; that is, toward the center of the elongated ovals shown in Figure 1. In this case, there is evidence that the creation of holes in a discharge event tends to create a flow of holes not only from drain 66 to source 68, but also laterally within the field oxide device 60, such as in the top view of Figure 1 where a flow of holes will be created from the center of each elongated field oxide device towards two ends thereof. This lateral flow of hole current out of the field oxide device is encouraged by the fact that the bulk of hole current flow is along the surface of the chip because the channel stop implant 70 reduces the resistivity by a factor of about 30-40 in the surface region. For this reason, the major path to ground of excess holes within the elongated field oxide device 60 is, in effect, out the ends of the field oxide device 60. Consequently, the highest gain of the parasitic bipolar is in the center of an elongated field oxide device, because of the hole bleed from the ends of the elongated structure, and therefore the failure will consistently occur in the center of the field oxide device. In other cases, when the various parameters of the field oxide device are slightly different, the failures will consistently appear at the ends of the field oxide device, probably caused by the concentration of electric fields at the end of an elongated field oxide device such as that shown by elongated ovals in Figure 1. The actual mechanisms by which failure of a type of device consistently occur in one location or another are not perfectly understood, but suffice to say that certain design parameters tend to result in consistent types of failures. Figure 4 is a plan view of a preferred embodiment of a second aspect of the present invention, wherein the field oxide device 60 not only extends along one dimension of an edge of the bonding pad, but is, in effect, brought around on itself so that the field-oxide-device extends in a single member around as much as possible of the perimeters of the bonding pad 32. Because lead 33 is typically necessary to connect bonding pad 32 to circuitry, it is usually impossible to provide ground metallization and ground via 74 field oxide device 60 which completely encloses the bonding pad 32; but it is possible to extend via 72 in a complete circle because both via 72 and lead 33 are connected to bonding pad 32. As the inner via 72 is the site of maximum impact ionization and is the terminal which cannot be shorted to the substrate as a result of parasitic bipolar discharge, the effects of hole bleed along the field oxide device 60 are substantially obviated even though via 74 may not form a complete enclosure. It is also advisable that the field oxide device is formed with rounded corners, as shown; sharp corners could be sites of unwanted field concentration. It is further preferable that the edges of the bonding pad 32 form a circle, to further evenly distribute current; however, round bonding pads may take up undue amounts of real estate on the chip. When the bonding pad 32 is substantially encircled as shown, lateral flow of excess holes in an ESD discharge is less likely to cause a hot spot which could result in damage to the device, because with a continuous ESD protection device extending entirely around the bonding pad 32, excess holes cannot escape the field effect device and thereby cause hot spots of high energy or temperature.

Claims: An electrostatic discharge protection device for a connector (32,30) disposed on a surface associated with an apparatus, comprising: a MOS field oxide device (60) operatively disposed between the connector (32,30) and ground (52); a bipolar transistor (66-70), parasitic to the field oxide device (60), having a collector (66), an emitter (68), and a base (70), and adapted to conduct current through the collector (66) and emitter (68) in response to a voltage between the connector (32,30) and ground (52) in excess of a predetermined threshold; characterized by a negative feedback resistance formed by a semiconductor region (90) of a substantial electrical resistance operatively disposed, at the emitter side, between the base (68) of the bipolar transistor (66-70) and ground (52), the semiconductor region (90) extending along at least one edge of the connector along the surface of the apparatus, whereby the resistance acts as a negative feedback loop controlling the current flow from the emitter to the collector of the bipolar transistor along the edge of the connector. A electrostatic discharge protection device as in claim 1, wherein the connector comprises a substrate (30) and a bonding pad (32) mounted on the substrate, the bonding pad (32) defining at least one edge substantially on the surface of the substrate (30). A electrostatic discharge protection device as in claim 2, wherein the field oxide device (60) and/or transistor (66-70) is operatively disposed continuously along an edge of the bonding pad (32); and/or wherein the field oxide device (60) and/or transistor (66-70) substantially encircles the bonding pad (32). A electrostatic discharge protection device as in claim 2 or 3, wherein the collector (66) of the transistor is connected to the bonding pad (32) with the emitter (68) being connected to ground (52); and preferably wherein the base (70) of the transistor comprises a channel-stop implant in the substrate (30). A electrostatic discharge protection device as in any of claims 2 to 4, wherein the substrate (30) is electrically grounded. A electrostatic discharge protection device as in any of the preceding claims, wherein the semiconductor region (90) comprises a doped area on the substrate (30), and preferably wherein a first area on the substrate (30) is doped, and the semiconductor region (90) comprises an area doped oppositely from the first mentioned area on the substrate and is adjacent thereto. An ink jet printer including an ink channel having a nozzle and in communication with an ink supply, a heating element associated with the channel, and a connector (30,32) connecting a semiconductor chip to the heating element so as to control the heating element to heat the ink in the channel and eject an ink droplet from the nozzle in response thereto, characterised by comprising an electrostatic discharge protection device (60) according to any of the preceding claims, coupled to the connector, to prevent failure of the semiconductor chip and the connector due to electrostatic discharges. The electrostatic discharge protection device of any of the preceding claims, wherein the MOS field oxide device (60) defines a drain, a gate and a source, and further includes a short between the drain and the gate of the field oxide device (60).

Inventors: BURKE CATHIE J, HAWKINS WILLIAM G, TELLIER THOMAS A, VANDEROEK SOPHIE, WATROBSKI THOMAS E, BURKE, CATHIE J., HAWKINS, WILLIAM G., TELLIER, THOMAS A., VANDEROEK, SOPHIE, WATROBSKI, THOMAS E.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1993
Main classification: H01L27
IPC codes: H01L27, H01L21