Frequency deviation measuring apparatus

Abstract: Based on a desired center frequency and a frequency resolution for a signal to be measured which are entered via an operator section (11), a micro-CPU (12) calculates the frequency dividing number (k), a preset value (M+P) and a center value (Nc) for the signal to be measured. The frequency dividing number is set in a frequency divider (15), which frequency divides the signal to be measured and provides the frequency-divided output to a continuous period-to-voltage converter (10). The continuous period-to-voltage converter counts clock pulses occurring in each frequency-divided period, measures the difference between fractions of time from both the beginning and the end of the frequency-divided period to the generation of the next clock pulses, respectively, and outputs, as a voltage corresponding to the frequency-divided period, the sum of a voltage corresponding to a predetermined number of consecutive low-order bits of a binary value, obtained by adding the preset value to the pulse count value, and the fractional time difference. A subtractor (19) is supplied with a voltage corresponding to the frequency-divided period and a voltage corresponding to the center value and outputs the voltage difference as a frequency-divided period deviation, and the micro-CPU calculates a frequency deviation of the measured signal from the center frequency on the basis of the frequency-divided period deviation.

Description: BACKGROUND OF THE INVENTION The present invention relates to a frequency deviation measuring apparatus and, more particularly, to a frequency deviation measuring apparatus whereby the deviation between a preset frequency (hereinafter referred to as a center frequency) and a measured frequency is displayed with a preset resolution. For evaluating the revolution performance of a motor which drives a rotary member used in a video tape recorder (VTR), a compact disk player (CD), a digital audio tape recorder (DAT), or similar electronic equipment, there has been proposed an effective method according to which an output obtained by superimposing an external disturbance on the output of an oscillator which drives the motor is used to drive the motor and a variation in the frequency generator output proportional to the rotating speed of the motor is measured by means of, for example, a delta F (ΔF) measuring apparatus. Yet the delta F measuring apparatus is not commercially available and its measured data lacks objectivity unless its rating is defined. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a high-resolution delta F measuring apparatus which is free from the above-mentioned problem and can be used for general purposes. The frequency deviation measuring apparatus according to the present invention includes: operation means for entering a desired center frequency and a frequency resolution with respect to a signal to be measured; calculation control means for calculating a frequency dividing number, a preset value and a center value with respect to the signal to be measured, on the basis of the center frequency and the resolution provided from the operation means; clock generating means for generating clock pulses of a predetermined period; frequency dividing means having set therein the frequency dividing number, for frequency dividing and outputting the signal to be measured; continuous period-to-voltage converting means which is supplied with the frequency divided output, counts the clock pulses in each period, measures the difference between fractions of time from both ends of the frequency divided period to the next clock pulse, and outputs, as a voltage corresponding to the frequency divided period, the sum of a voltage corresponding to a plurality of predetermined consecutive low-order bits of a binary value obtained by adding the preset value to the pulse count value and the fractional time difference; and deviation calculating means which is supplied with the voltage corresponding to the frequency divided period and a voltage corresponding to the center value and outputs the difference between the voltages as a period deviation. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a frequency deviation measuring apparatus according to the present invention; Fig. 2 is a block diagram of a continuous period-to-voltage converter for use in the present invention; and Fig. 3 is a diagram showing the display screen of a display. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to Fig. 1, an embodiment of the present invention will be described. Reference numeral 11 denotes an operation part, which enters a center frequency Fc and a resolution ΔF into an apparatus. On the basis of these values input through the operation part 11, a micro CPU 12 calculates a frequency dividing number k (where k is an integer equal to or greater than 1), a preset value M+P (where M and P are integers equal to or greater than 0) and a center value Nc (where Nc is an integer equal to or greater than 0), and these values are latched in latches 14A, 14B and 14C and, at the same time, they are displayed on a display 13. A l/k frequency divider 15, set to the frequency dividing number k, frequency-divides a signal of a cycle period Px (frequency Fx = l/Px), that is to be measured, down to l/k and the frequency-divided output of a period kPx is applied to a continuous period-to-voltage converter (hereinafter referred to as a continuous P-V converter) 10. Reference numeral 16 denotes a clock generator and 18 a digital-to-analog converter (hereinafter referred to as a D-A converter) for converting the above-mentioned center value Nc to a center voltage Vc. A difference voltage between a voltage signal Vx corresponding to the cycle period Px of the signal to be measured, available from the continuous P-V converter 10, and a center voltage Vc corresponding to the period of the pre-entered center frequency Fc is obtained as a period deviation voltage output ΔVx by means of a subtractor 19. That is, according to the present invention, the deviation of the actually measured frequency from the center frequency Fc is obtained on the assumption that the center frequency Fc as an expected frequency (or design frequency, or a frequency which is a required specification) of the signal to be measured is preknown. The continuous P-V converter 10 has such a construction as shown in Fig. 2, which is substantially identical with the construction disclosed in U.S. Patent No. 4,769,798 but the latch 14B and the clock generator 16 are included in the continuous P-V converter in the U.S. patent. As described later in detail, the value to be set in the latch 14B and its meaning according to the present invention are not the same as in the U.S. patent. Moreover, in the present invention only a predetermined number of low-order bits of the count value of a presettable counter 108 are provided to a D-A converter 109, whereas in the U.S. patent all bits of the count value of the presettable counter 108 are provided to the D-A converter 109. Despite these differences the principle of fundamental operation for period measurements by the converter depicted in Fig. 2 is the same as the principle of operation in the U.S. patent, and hence no detailed description will be given of its operation but a brief description will be made of the function of its respective part. The leading edge of an input frequency-divided pulse, which is applied to an input terminal 101, is detected by a signal detector 102. In response to the detection outputs Q and Q of mutually opposite logic from the signal detector 102, first and second fractional time-to-voltage converters (hereinafter referred to as fractional T-V converters) 103 and 104 start integration alternately with each other and upon arrival of a predetermined number of clock pulses after the start of their integration, they stop integration and alternately convert fractional times ΔT 2m-1 and ΔT 2m from the detection of an input pulse (its rise, for instance) to the generation of a predetermined equal number of clock pulses, into voltage signals ΔV 2m-1 and ΔV 2m . The suffixes 2m-1 and 2m, ... indicate the numbers of the input frequency-divided pulses, and m = 1, 2, ... The voltage signals ΔV 2m-1 and ΔV 2m , which are output from the fractional T-V converters 103 and 104 alternately with each other, are provided onto signal lines 113 and 114 via a change-over switch 105. In this case, the voltage signals ΔV 2m-1 and ΔV 2m are provided as a voltage signal ▵V n on the signal line 113 and as a voltage signal ΔV n+1 on the signal line 114 in the order in which they are updated. The suffix n represents the number of the measurement period and is 1, 2, ... An analog subtractor 106 subtracts the voltage signal ΔV n+1 from the voltage signal ΔV n to obtain a difference voltage signal δ n . A gate 107 extracts clock pulses which are present in the period of the input frequency-divided pulse corresponding to each period kPx, and the thus extracted clock pulses are counted by a presettable counter 108. The count value of the counter 108 is converted by a D-A converter 109 to an analog voltage, which is provided to an adder 111 and added therein to the difference voltage signal δ n from the analog subtractor 106. Thus a voltage Vn corresponding to the period kPx is obtained for each frequency divided period. Consequently, a series of periods of an input pulse train at the terminal 101 are sequentially converted and the converted voltages Vx are provided via a sample-hold circuit 112 to a terminal 133. The constant M which provides the value M+P to be preset in the counter 108 is to preset its value in the counter 108 so that at the end of the period kPx correct clock pulses in the period are all obtained as the count value of the counter 108, because the continuous P-V converter 10 has a construction wherein the counter 108 does not start counting the clock pulses CK simultaneously with the start of the period kPx but instead the gate 107 is enabled after counting M clock pulses CK by a frequency divider 129, as described in the afore-mentioned U.S. patent. In the present invention, however, the sum of the value M and an integral value P dependent on the center frequency Fc is preset in the counter 108 as described later in detail. Moreover, according to the present invention, at the end of each period kPx a value Ln of the two lowest-order bits of the count value of the counter 108 is input into the two highest-order bits of the D-A converter 109 and converted to an analog voltage LnVo. In the following description the fraction of time at the start of measurement for each frequency divided period kPx, corresponding to the voltage signal ΔV n , is identified by ΔT 1 and the fraction of time at the end of measurement, corresponding to the voltage signal ΔV n+1 , as ΔT 2 . With the continuous P-V converter 10 shown in Fig. 2, by measuring the number Nx of clock pulses included in the frequency divided period kPx of the input pulse (the count value of the counter 108 when P = 0) and the fractional times ΔT 1 and ΔT 2 from the start and the end of the frequency divided period kPx to the generation of predetermined numbers of clock pulses as in the U.S. patent, the frequency divided period kPx is obtained from the following expression: kPx = T 0 Nx + ΔT 1 - ΔT 2 = T 0 Nx + Δt where T 0 is the clock period. Δt = ΔT 1 - ΔT 2 will hereinafter be referred to as a fractional time difference. Yet what is intended to obtain with the apparatus of the present invention is the deviation of the frequency-divided period kPx from the center frequency-divided period, as a measure corresponding to the deviation of the frequency Fx of the signal to be measured from the center frequency Fc, and the deviation is very small as compared with the center frequency-divided period or the frequency-divided period to be measured (as small as several clocks, if converted into the number of clocks). To measure the deviation with a high degree of accuracy, according to the present invention, a desired amount of offset is removed from each of the frequency-divided period kPx and the center frequency-divided period with a view to make the most use of the maximum conversion range of each of the D-A converter 18 in Fig. 1 and the D-A converter 109 in Fig. 2. Even if a desired amount of offset is thus removed from each of the frequency-divided period kPx and the center frequency-divided period, the amounts of offset cancel each other and deviation can be measured with accuracy, because the difference between the both periods is obtained by the subtractor 19. Next, a description will be given of conditions which are set for measurement according to the present invention. (a) The present invention is intended to measure a frequency deviation but, basically, measures a period deviation. The reason for this is that since the frequency of the signal to be measured is as low as 100 kHz or below in many cases, it is advantageous to obtain a high resolution to measure the period deviation rather than the frequency deviation. (b) Since it is preferable to obtain a measurement resolution of around 100 ps and continuously measure the period, the present invention employs, as the continuous P-V converter 10, for example, the continuous period-to-voltage converter disclosed in the afore-mentioned U.S. patent and shown in Fig. 2. (c) In the continuous P-V converter 10 depicted in Fig. 2, the period T 0 of the clock pulse CK available from the clock generator 16 is set to 100 ns and the converted output voltage from each of the converters 103, 104 and 109, corresponding to one clock, is set to 1 V. The maximum output voltage of the D-A converter 109 is set to 4.000 V, for instance, and by providing the value Ln of the two low-order bits (i.e. digits 2 0 and 2 1 ) of the presettable counter 108 to its input of two high-order bits, the D-A converter 109 outputs any one of 0.000 V, 2.000 V and 3.000 V in accordance with the value Ln. Hence the maximum value of Ln is 3 and the output difference voltage δ n from the analog subtractor 106, corresponding to the fractional time difference Δt comes within the range of ±1 V. If the converted output voltage Vx available at the output terminal 133 is limited to the positive, the voltage range of the converted output voltage Vx is between 0 and +4 V. Converted output voltage regions of the continuous P-V converter 10, obtained by dividing the above-mentioned maximum voltage range with the voltage width corresponding to the clock period T 0 , and the corresponding measurement time regions are such as given below in Table 1. Now, assuming that the period of the input signal to the continuous P-V converter 10 is kPx = 12.3456 µs, the converted output voltage Vx is given by the remainder resulting from the division of the signal period by 400.0 ns corresponding to the maximum range. In this case, 100 ps which is the measurement resolution is used as the minimum unit. That is, 123456 + 4000 = 30, the remainder 3456. Since 345.6 ns is the remainder, the converted output voltage Vx is 3.456 V. The above division is expressed as follows: 3456 = 123456 mod 4000. In general, kPx is given by the following expression as referred to above. kPx = NxT 0 + ΔT 1 - ΔT 2 = NxT 0 + Δt Since kPx and T 0 (clock) are asynchronous with each other, 0 ≦ ΔT 1 ≦ T 0 , 0 ≦ ΔT 2 ≦ T 0 After all, the fractional time difference, Δt = ΔT 1 - ΔT 2 , in the case of measuring each frequency-divided period kPx with the clock period T 0 used as the unit therefor comes within the following range: -T 0 ≦ ΔT 1 - ΔT 2 ≦ T 0 That is, the fractional time difference Δt may take either of positive (including zero) and negative values. For example, if the converted output voltage Vx at the output terminal 133 is 1.250 V, this voltage belongs to the region II, and as shown in Table 2 there are two kinds of combination of the value of the fractional time difference Δt and the value Ln of the last two figures of the count value of the counter 108 which provides such an output voltage. Ln LnV 0 Δt δ n Δt ≧ 0 1 1.000 V 25.0 ns 0.250 V Δt < 0 2 2.000 V -75.0 ns -0.750 V Similarly, Table 3 shows the relationships between the sign of the fractional time t and the value Ln which provide the converted output voltage Vx belonging to each of the regions I to IV in Table 1. Region Δt ≧ 0 Δt < 0 Ln Ln IV 3 0 III 2 3 II 1 2 I 0 1 In the case of Δt < 0 in the region IV, the value Ln ought to be 4, but the value Ln is the last two-bit output of the counter 108 and hence is zero -- this is an incorrect measurement. In view of this, according to the present invention, a value obtained by adding a proper value P to the constant M is preset in the counter 108 to ensure that the P-V converted output shifts out of the region IV. That is, the latch 14B in Fig. 1 is connected to the presettable counter 108 in Fig. 2 to set its preset value P+M. The continuous P-V converter 10 is adapted so that in the case where the preset value is equal to the frequency dividing number M of the frequency divider 129 (that is, when P = 0), even though the counting of clock pulses is started M clock pulses after the start of the frequency-divided period kPx, a count value just equal to the total number of clock pulses, Nx, in the frequency-divided period kPx is obtained at the end of the counting period defined by the gate 107, irrespective of the value M. Accordingly, in this instance, if a value M+1 (P = 1) is preset in the presettable counter 108, the converted output voltages which appear in the regions I, II and III in Table 1 are shifted up by 1.000 V (= 10.0 ns) and appear in the regions II, III and IV, respectively, and the voltage which appears in the region IV is shifted to the region I. If the preset value is M+3 (P = 3), the converted output voltage in the region III appears in the region II. In this way, the converted output voltage in any region can be shifted to other regions by changing the preset value M+P. It is possible to predict the region in which the converted output voltage in the frequency-divided period kPx when P = 0, by detecting, through calculations described later on, the region to which the converted output voltage in a preknown center frequency-divided period predicted to be very close to the above period kPx would belong. In this embodiment the value M+P is chosen such that the converted output voltage would shift from the predicted region to the region II. The reason for which the region II is selected is that even if the predicted region is erroneous, the converted output voltage is very likely to be shifted to the region I or III and is not likely to be shifted to the region IV unless a frequency variation of the signal to be measured becomes abnormally larger than expected. The shift of the converted output voltage is independent of the value M and is controlled by the value P. That is, what is important is to add the value P to the total number Nx of the clock pulses in the frequency-divided period kPx, and that the value of, for example, the least significant two bits of the added value is used. Next, a description will be given of how determine the frequency dividing number k, the preset value P+M and the center value Nc which are set in the latches 14A, 14B and 14C in the frequency deviation measuring apparatus of the present invention shown in Fig. 1. The micro-CPU 12 determines these values through the operation described below. By actuating the operation part 11, the center frequency Fc of the signal to be measured and the required frequency resolution ΔF are entered into the micro-CPU 12. Now, suppose, for example, Fc = 1/Pc = 1.234567 MHz and ΔF = 1 Hz. In the above, Pc is the center period. Assume that the resolution for period measurement is about 100 ps. At first, the frequency dividing number k of the l/k frequency divider (binary) is determined on the basis of the following expression: ΔF = Fc × 100 ps + (kPc) = Fc × 100 ps/(k/Fc) = (100 ps/k) × Fc 2 That is, k = (100 ps/ΔF) × Fc 2 = (10 -10 ÷ ΔF) × Fc 2 Substitution of numerical values of Fc and ΔF into the above gives k = (10 -10 /1) × (1.234567 × 10 6 ) 2 = 152.4 Assuming that the frequency divider 15 is binary and that the frequency dividing number k which is actually set in the frequency divider 15 is a binary value of the minimum value of a power of 2 which is equal to or greater than the value given by the expression (5), k = 256 is selected from 2 7 = 128 < 152.4 < 2 8 = 256. At this time, the actual frequency resolution becomes around 0.6 Hz. Thus the frequency dividing number k is automatically determined by the micro-CPU 12. Next, the preset value M+P and the center value Nc are determined. The first step for the determination of the preset value M+P is to obtain the region in which the converted output voltage will appear on the assumption that the center frequency-divided period kPc (= k/Fc) corresponding to the center frequency Fc has been converted by the continuous P-V converter 10 as described previously. That is, an integral multiple of the time (400.0 ns) corresponding to the maximum range (4.000 V) of the converted output voltage is subtracted, as an offset, from the center frequency-divided period, and a provisional center value Nc' is determined by the following division so that the remainder of the above subtraction, converted to voltage, comes within the maximum range of 4.000 V. In this case, the minimum unit for the division is 100 ps (corresponding to 1 mV) as described previously. Nc' = (k/Fc) × (1/Fc) mod 400.0 ns = k/Fc mod 400.0 ns Substituting k = 256 and Fc = 1.234567 × 10 6 into the expression (7), we have Nc' = 1601 (= 1.601 V or 160.1 ns). That is, the region to which the converted output voltage of the frequency-divided period kPx (the region to which the provisional center value Nc' belongs), which is predicted on the basis of the center frequency-divided period k/Fc in the case of P = 0, is the region II in Table 1. Accordingly, since the converted output voltage need not be shifted to other regions in this case, P = 0, that is, the preset value is M and the center value Nc = Nc'. Table 4 shows the relationship between the regions to which the provisional center value Nc' belongs and the corresponding preset value M+P to be selected. Region Nc' M+P Range of Center Value IV 3000 ∼ 3999 M+2 1000 ∼ 1999 III 2000 ∼ 2999 M+3 1000 ∼ 1999 II 1000 ∼ 1999 M 1000 ∼ 1999 I 0000 ∼ 0999 M+1 1000 ∼ 1999 In each case the provisional center value can be transferred to the region II in Table 1, and even in the case of the minimum deviation measuring range, it is possible to secure 100.0 ns at either of lower and upper limits, converted in time (respectively corresponding to 600 Hz in the above example). Next, a shift amount P × 1000 is added to the provisional center value Nc' so that it belongs to the region II, and the center value Nc is obtained by the following expression: Nc = Nc' + P × 1000 The center value Nc thus obtained is set in the latch 14C and then converted by the D-A converter 18 to the center voltage Vc, which is applied to the subtractor 19. The output range of the D-A converter 18 is +1.000 V to 1.999 V and a 1mV resolution suffices. In the above example the center voltage Vc available from the D-A converter 18 is +1.601 V. With the A-D converter 17 in Fig. 1, the following frequency-divided period deviation voltage is measured in digital form. ΔVx = Vx - Vc Letting the frequency deviation to be ultimately obtained be represented by Δf, the following expression holds: Δf/Fc = -ΔVx × 100 ps/kPc Therefore, the frequency deviation Δf is given by the following expression: Δf = -ΔVx × 100 ps Fc 2 /k = -0.59537 ×ΔVx Hz The micro-CPU 12 in Fig. 1 performs the control and calculations described above. A display is provided, for example, as shown in Fig. 3, in accordance with the result of the calculation of the expression (10). The display shown in Fig. 3 is -4 Hz. Provision is made so that the range ±500 times larger than the resolution may be displayed on the display screen. In Fig. 1 the output of the frequency deviation measuring apparatus is shown to be the period deviation voltage output. The reason for this is that it is desirable to connect external equipment, such as a general-purpose FFT analyzer, to the apparatus so as to permit a spectrum analysis of frequency variations. Since the above embodiment has been described to employ the continuous period-to-voltage converter disclosed in U.S. Patent No. 4,769,798, the frequency dividing number M of the frequency divider 129 is set in the counter 108 after being added to the preset value. The point is to set in the counter 108 the value that P has been added to the total number of clock pulses present in each frequency-divided period, and the principle of the present invention has nothing to do with the value of the constant M. In the above embodiment the value Ln of the least significant two bits of the presettable counter 108 is provided as the input of the most significant two bits of the D-A converter 109 to select any one of 0 V, 1 V, 2 V and 3 V as the output of the D-A converter 109 and, in the case of P = 0, the output Vn of the adder 111 (and consequently the converted output voltage Vx) comes into any one of the regions 0 to 1 V, 1 to 2 V, 2 to 3 V and 3 to 4 V, accordingly. In this instance, however, the value Ln need not be limited specifically to the value of the least significant two bits but may also be a value of three or more bits. In general, in the case where the least significant W bits (where W is an integer equal to or greater than 2) are provided as the input of the most significant W bits of the D-A converter 109, the D-A converter selectively outputs, in accordance with the value Ln, any one of 2 W voltages into which a voltage range from 0 V to the maximum output voltage of the D-A converter is divided with equally spaced-apart steps. In this case, the conversion coefficients of the fractional T-V converters 103 and 104 are determined so that the converted output voltage of the continuous P-V converter 10, corresponding to the clock pulse period T 0 , may be equal to the step width. While the measurement of a frequency deviation has been described, a period deviation can also be measured by exactly the same procedure as described above (in which case the calculations involved are simpler than in the above). As described above, according to the present invention, the frequency deviation can be measured with a high resolution only by setting the minimum amount of information such as the center frequency and resolution. Moreover, the frequency deviation measuring apparatus of the present invention is general-purpose but simple in construction, and hence is inexpensive. Thus the present invention greatly contributes to the development in the technical fields to which the frequency deviation measuring apparatus of this kind belongs. It will be apparent that many modifications and variations may be effected without departing from the scope of the claims of the present invention.

Claims: A frequency deviation measuring apparatus comprising: operation means (11) for entering a desired center frequency and a frequency resolution for a signal to be measured; calculation control means (12) for calculating a frequency dividing number, a preset value and a center value for said signal to be measured, on the basis of said center frequency and said resolution, provided from said operation means (11), clock generating means (16) for generating clock pulses of a predetermined period; frequency dividing means (15) which has set therein said frequency dividing number, frequency divides said signal to be measured and provides the frequency-divided output; continuous period-to-voltage converting means (10) which is supplied with said frequency-divided output and the clock generating means output and outputs a voltage corresponding to each of a series of frequency-divided periods, said continuous period-to-voltage converting means (10) including clock counting means (108) which has preset therein said preset value and counts said clock pulses in said each frequency division period, fractional time difference measuring means (103) which measures the difference between fractional times from the beginning and end of said each frequency-divided period to the respective points of time of the completion of generation of a predetermined number of said clock pulses thereafter and outputs the measured difference as a fractional time difference voltage, D-A converter means (109) which is supplied with a predetermined number of consecutive low-order bits of said pulse count value and converts them into the corresponding voltage, and adder means (111) for outputting the sum of said fractional time difference voltage and said output voltage of said D-A converter means (109) as a voltage corresponding to said frequency divided period; and subtractor means (19) which is supplied with said voltage corresponding to said frequency-divided period and a voltage corresponding to said center value and outputs their difference as a frequency-divided period deviation. The apparatus of claim 1 which further comprises A-D converter means (17) for converting said frequency-divided period deviation from said subtractor means (19) into a digital value and in which said calculation control means (12) includes means whereby a frequency deviation of said signal to be measured from said center frequency is calculated from said frequency-divided period deviation provided as said digital value. The apparatus of claim 2 which further comprises display means (13) for displaying said calculated frequency deviation. The apparatus of claim 1 wherein said calculation control means (12) includes means for determining said preset value, depending on which region of a predetermined maximum range of said converted output voltage the remainder of a division of said center frequency by a time corresponding to said predetermined maximum range of said converted output voltage belongs to. The apparatus of claim 4 wherein said plurality of low-order bits are the last two bits. The apparatus of claim 5 wherein said preset value is selected so that said center value enters into said region which is the second lowest.

Inventors: CHINODA KAZUYOSHI, HAYASHI MISHIO, CHINODA, KAZUYOSHI, HAYASHI, MISHIO
Applicants: ADVANTEST CORP, ADVANTEST CORPORATION
Application year: 1993
Main classification: G01R23
IPC codes: G01R23