Moving picture decoding system

Abstract: An adder restores an image data by adding an output of a reverse DCT portion and an output of a predicted value calculating portion to output to a macro-block buffer. Data temporarily stored in the macro-block buffer is written in a predicting dynamic memory per a unit of data of one word consisted of 2 x 2 blocks of luminance component (Y), 1 x 2 blocks of Cr component and 1 x 2 blocks of Cb components, via a memory data bus. A prediction reference block of the preceding frame stored in the predicting dynamic memory is output to a reference block buffer via the memory data bus. A restored image data of the preceding frame in the predicting dynamic memory is output to a line buffer via the memory data bus.

Description: BACKGROUND OF THE INVENTION The present invention relates to a moving picture decoding system. More specifically, the invention relate to a moving picture decoding integrated circuit and a system thereof for decoding a moving picture data coded by an interframe predictive coding method. Conventional compressive coding method is primarily a coding method adaptively switching an intraframe coding method, a forward predictive coding method, bidirectional predictive coding method. On the other hand, there is a coding method, in which only intraframe coding method and the forward predictive coding method are switched instead of employing the bidirectional predictive coding method. Here, the intraframe coding method performs coding with only information from own frame. The forward predictive coding method performs coding with reference to the information of the former frame. On the other hand, the bidirectional predictive coding method performs coding with reference to the information of the former and backward frames. In order to decode the data coded by the foregoing methods, it is required a predicting frame memory for temporarily storing the former and backward frames. Among decoding methods for decoding data coded through the foregoing methods, there is a system illustrated in Fig. 4 , which is a moving picture decoding system not employing the bidirectional predictive coding method, for example. In the shown moving picture decoding system, a code to be decoded is input to a variable length code decoding portion 1 . The variable length code decoding portion 1 restores a quantized discrete cosine transformation (DCT) coefficient to output the quantized DCT coefficient to a reverse quantizing portion 2 . In conjunction therewith, the variable length code decoding portion 1 restores a prediction mode and a motion vector information to output the prediction mode and the motion vector information to a predicted value calculating portion 5 and a memory control portion 33 . The reverse quantizing portion 2 restores a DCT coefficient from the quantized DCT coefficient to feed the DCT coefficient to a reverse DCT portion 3 . The reverse DCT portion restores an interframe difference data or an image data by performing reverse DCT to feed the interframe difference data or the image data to an adder 4 . A predicting memory 32 has a data capacity for two frames for reading and writing and is controlled by an address and a control signal from the memory control portion 33 . The memory control portion 33 performs a prediction reference block read control, a restored image data write control, a read control for raster scanning transformation of the restored image data in time sharing manner. During the prediction reference block read control by the memory control portion 33 , with respect to a current position (x, y) of a current frame, a block at a position(x + Δx, y + Δy) corrected with a motion vector of a reference frame is read out. The read out block is output to a reference block buffer 34 . On the other hand, during write control of the restored image data by the memory control portion 33 , the data output from the adder 4 is written in the predicting memory 32 when horizontal eight samples are accumulated in a latch 31 . Also, during read control of the restored image data by the memory control portion 33 , the restored image data of the preceding frame in the predicting memory 32 is read out and transferred to a line buffer 38 . The reference block buffer 34 temporarily stores a predicting reference block input from the predicting memory 32 and outputs to a multiplexer 36 per one word. The multiplexer 36 extracts one 8 bit sample data from the predicting reference block per one word and feeds the sample data to the predicted value calculating portion 5 . The predicted value calculating portion 5 is responsive to input of the one sample data from the multiplexer 36 to calculate a predicted value for a position corresponding to the output of the reverse DCT portion 3 according to a prediction mode and a motion vector information from the variable length code decoding portion 1 . The predicted value calculating portion 5 outputs the predicted value to the adder 4 . The adder 4 restores the image data by adding the output of the reverse DCT portion 3 and the output of the predicted value calculating portion 5 . The restored image data is output to the latch 31 . When data for horizontal eight samples are accumulated in the latch 31 , the accumulated data is written in the predicting memory 32 under the control of the memory control portion 33 . A scanning transformation control portion 39 outputs a control signal to a line buffer 38 for controlling writing of the restored image data from the predicting memory 32 and reading out of the restored image in an order of raster scanning. The line buffer 38 has two banks of buffers for one line for each color component for writing and reading. Namely, when respective one line of respective color components of the restored image data from the predicting memory 32 is written in one of the bank of the line buffer 38 , data is read out in the order of raster scanning from the other bank. It should be noted that the latch 31 , the reference block buffer 34 , the line buffer 38 are respectively connected to the predicting memory 32 via a memory data bus 101 . The memory data bus 101 has a width of 64 bits. In the moving picture decoding system operating as set forth above, discussion will be given for necessary access speed performance when the memory control portion 33 accesses the predicting memory 32 . The access speed performance is most importantly required in the case of the forward direction predictive coding frame. Namely, the access speed performance is required for read control of the predicting reference block, write control of the restored image data and raster scanning transformation of the restored image data by the memory control portion 33 . Here, respective functional block of the moving picture decoding system has blocks of 8 pixels x 8 pixels as a minimum unit. Namely, 8 pixels x 8 pixels block becomes the minimum unit in reverse quantizing by the reverse quantizing portion 2 and in reverse DCT by the reverse DCT portion 3 . Also, in the following discussion, a block constituted of 2 x 2 blocks of luminance components (Y) and respectively 1 x 2 blocks of two chrominance components (Cr, Cb) will be referred to as macro-block. In case that the memory control portion 33 performs write control of the restored image data, the restored data is written in the predicting memory through eight times of access per one block. On the other hand, when the memory control portion 33 performs read control for the prediction reference block, 8 samples x 8 samples of prediction reference block is required if the motion vector makes reference to the integer pixel positions for one block. If the motion vector makes reference to intermediate pixel positions (half pel), 9 samples x 9 samples of prediction reference block is required for one block. However, in case of the word construction taking horizontal 8 samples as one word, 9 samples x 9 samples of prediction reference block cannot be directly read out. Therefore, it is required to perform access for horizontal two words (16 samples) for nine times. Furthermore, when the memory control portion 33 performs read control for raster scanning transformation of the restored image data, data of one horizontal line is output to the line buffer 38 per each chrominance component. 525 line system in the digital television stadio standard CCIR601 is a pixel rate of 720 x 480 pixel of a frame size and 30 frames/sec of a frame rate. In the above-mentioned standard, a sampling frequency is 13.5 MHz. According to this standard, it is required to output per 858 cycles for one line so that a process at 13728 (858 x 16) cycles per 16 lines is required. Next, discussion will be given for the case where the pixel rate of the 525 line system under the CCIR601 standard will be realized by the above-mentioned moving picture decoding system. At first, number of word access per 16 lines of the foregoing moving picture decoding system is concerned; reading of the prediction reference block: 2 words x 9 times x 8 blocks x 45 macro-blocks = 6480 writing of the restored image data 1 word x 8 times x 8 blocks x 45 macro-blocks = 2880 reading of restored image data (1/8) word x (720 + 2 x 360) samples x 16 lines = 2880 and thus 12240 times in total of word access becomes necessary. Here, the number of macro-blocks in one horizontal line component is 45 blocks. On the other hand, an operational clock of LSI is set at integral multiple of a sampling clock of the image. In case of the 525 line system of the CCIR601, since the sampling frequency is 15.5 MHz, one cycle becomes 74 ns. When a SRAM (static random-access-memory) having an access time less than or equal to 74 ns is employed as the predicting memory 32 , one word access of the SRAM can be done in one cycle, the access cycle becomes 12240 cycles which falls with in the necessary access rate of 13728 cycles as required in the 525 line system of the CCIR601 to satisfy the condition. On the other hand, when SRAM having an access time less than or equal to 37 ns is used at 27 MHz, the condition can be satisfied even with the memory data bus 101 of 32 bit width. Conversely, when DRAMs (dynamic random-access memory) having an access time of 70 ns as the predicting memory 32 , necessary access times for accessing the DRAMs become as follow. Page mode access of the DRAMs become as illustrated in Fig. 3(a) , in which, upon initiation of access, after two cycles, i.e. pre-charge cycle of an RAS signal and a CAS signal and row address cycle R, access is performed by inputting column addresses C0, C1, ..... Since two word access in reading of the prediction reference block can be done by sequentially column addressing for two time, number of cycles becomes four. Since column addresses are not in sequence in one word access in writing of the restored image data, one word access in page mode access can be done substantially in one cycle. Accordingly, when DRAMs are used, necessary number of cycles per 16 lines becomes: read of prediction reference block: 4 cycles x 9 times x 8 blocks x 45 macro-blocks = 12960 write of restored image data 3 cycles x 8 times x 8 blocks x 45 macro-blocks = 8640 read of restored image data (1/8) cycles x (720 + 2 x 360) sample x 16 lines = 2880 and thus 24480 cycles in total. Here, number of macro-blocks in one horizontal line is 45. Accordingly, when DRAMs are employed, the condition of less than or equal to 13728 cycles required for the pixel rate in the 525 line system of the CCIR601, cannot be satisfied. If DRAMs product having approximately 40 ns of access time, it may be possible to perform access for one word in one cycle as in the SRAM having access time less than or equal to 74 ns. However, such DRAM product is currently not available. In this circumstance, in the moving picture decoding system of the pixel rate higher than or equal to the 525 line system of CCIR601, SRAM is employed, or, in the alternative, DRAM is employed with reduced access times by widening the data bus number to be greater than or equal to 128 bits. Among the conventional systems for decoding coded data, there is a moving picture decoding system for the moving picture coded signal coded by adaptively switching the intraframe forward predictive coding and bidirectional predictive coding as illustrated in Fig. 5 . The moving picture decoding system of Fig. 5 is differentiated from the system of Fig. 4 in the following points. Namely, in the moving picture decoding system of Fig. 4 , only one reference block buffer 34 is provided. In contrast to this, the moving picture decoding system of Fig. 5 employs two reference block buffers, i.e. a forward reference block buffer 44 and a backward reference block buffer 45. It should be appreciated that the forward prediction reference blocks temporarily stored in the forward reference block buffer 44 and a backward prediction reference block temporarily stored in the backward reference block buffer 45 are output to the predicted value calculating portion 5 via a multiplexers 46 and 47. On the other hand, for a memory control portion 43 of the moving picture decoding system of Fig. 5 is established by adding a control for a bidirectional predictively coded frame for the controls in the memory control portion 33 of Fig. 4 . The bidirectional predictively coded frame requires read control for the forward prediction reference block and read control for the backward prediction reference block. The restored image data output of the bidirectional predictive coding frame performed by writing in a scan transforming memory 48 from the latch 31 via a multiplexer 40 by control of a scan transforming control portion 49 not via the memory data bus 101. Furthermore, in the moving picture decoding system of Fig. 4, the order of output of data at read control of the restored image data is per respective chrominance components and per one line. In contrast to this, in the moving picture decoding system of Fig. 5 , the order of output of data is per macro-block similarly to that of inputting of the restored image data from the latch 31 adapting to the output of restored image data of the bidirectional predictive coding frame. Namely, the restored image data from the latch 31 is written in the scan transforming memory 48 via the multiplexer 40. For the scan transforming memory 48 of the moving picture decoding system of Fig. 5, two banks of buffers for storing macro-blocks for one horizontal lines must be provided for reading and writing for inputting restored image data per macro-block. Therefore, the memory capacity therefor becomes 360 Kbits. The scan transforming control portion 49 of the moving picture decoding system of Fig. 5 outputs a control signal to the scan transforming memory 48 for controlling writing of the restored image data input per macro-block, and outputting of the restored image data in an order of raster scanning. When the pixel rate of the 525 line system of CCIR601 is realized in the above-mentioned moving picture decoding system, the times of word access per 16 lines in the memory control portion 43 becomes 12240 times similar to the word access times of the moving picture decoding system of Fig. 4, in case of forward predictive coding. In contrast to this, in case of the bidirectional predictive coding, the word access times becomes: read of forward reference block: 2 words x 9 times x 8 blocks x 45 macro-blocks = 6480 read of backward reference block: 2 words x 9 times x 8 blocks x 45 macro-blocks = 6480 and thus in total 12960 times. Here, number of macro-blocks in one horizontal line is 45. When SRAM is employed as the predicting memory 32 , the condition of the access rate less than or equal to 13728 cycles necessary for 525 line system of CCIR601 can be satisfied by employing SRAM having access time less than or equal to 74 ns. On the other hand, by employing SRAM having access time less than or equal to 37 ns, the foregoing condition can be satisfied even with the memory data bus 101 of 32 bit width. Furthermore, when DRAMs are employed as the predicting memory 32 , similarly to the moving picture decoding system of Fig. 4, the condition of the access rate less than or equal to 13728 cycles required in 525 line system of CCIR601 cannot be satisfied. As can be appreciated, in the conventional moving picture decoding system, it has been required to employ SRAM as the predicting frame memory for decoding the moving picture requiring the pixel rate of 525 line system of CCIR601 and inexpensive DRAM cannot be used. Also, when DRAM is employed with widening the width of the data bus to be greater than or equal to 128 bits, number of terminals of LSI in forming the integrated circuit is increased to prevent downsizing of the LSI. Furthermore, in order to achieve the 128 bit bus width with employing DRAMs of the currently available maximum width of x 16 bits construction, DRAMs must be increased per 8. Therefore, when eight 4-Mbit DRAMs are employed for necessary capacity of [(720 + 360) samples x 480 lines x 8 bits x 2 frames = 10.546 Mbits] as the predicting frame memory in 525 line system of CCIR601, non-used region of DRAMs become large. When 1-Mbit DRAMs are used in view of memory capacity efficiency, 16 DRAMs become necessary to make the installation area of the predicting frame memory large. In case of the moving picture decoding system for the bidirectional predictively coded signal, the output of the restored image data of the bidirectional predictive coded frame is directly written in the scan transforming memory from the latch not via the memory data bus. This is because that large portion of the memory data bus is used for accessing the predicting memory so that cycles (8 cycles x 8 times x 45 macro-blocks = 2880 cycles) per 16 lines necessary for writing in the scan transforming memory cannot be certainly attained. Therefore, when an external memory is used as the scan transforming memory in integration of the system, 64 extra terminals are required for the data bus of the scan transforming memory to prevent downsizing of the LSI. EP-A-0,503,956 discloses a method and an apparatus for the decompression of a video signal. A method and a structure are provided to decode intra-frame and interframe coded compressed video data. In one embodiment of the invention, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure in accordance with the invention communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor in the decompression structure of the invention provides overall control to the decoder, IDCT and motion compensation coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the decoder, the IDCT and the motion compensation coprocessors. The 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a macroblock of pixels to be stored in one DRAM memory page, so that an access to a macroblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of four pixels can be obtained at one time in one of 2 pixel X 2 pixel "quad pixel" configuration, or in a 4 pixel X 1 pixel horizontal "scan" configuration. A structure including four of the decompression structures and a method are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, each decompression structure decodes a 480 X 1088-pixel picture area with access to up to two additional 240 X 1088-pixel picture area. A method using a divide-by-15 divisor is provided in the HDTV decompression structure to map the display space into the external DRAM with efficient use of the DRAM physical address space. A decoder logic unit having a plurality of decode tables and a method are provided in the decoder coprocessor to decode coded video data. Each coded datum to be decoded is provided to all of the decode tables. The decoded datum is selected by a finite-state machine from among the output data of all the decoded tables. The processor of the decompression structure is provided with a structure and a method for reducing the computation of a product into the computation of a sum, using temary arithmetic and either zeroing, negating or leaving unchanged the operands of the sum. A block memory structure and a method are provided for receiving 8 X 8-pixel blocks column by column in a 16 X 16-pixel picture area, such that the 16 X 16-pixel picture area can be output column by column simultaneously as the 8 X 8-pixel blocks are received, without double-buffering. A motion compensation structure and a method are provided for interpolating interframe coded video data using motion vectors. The motion compensation structure comprises a filter for resampling the pixel data in both vertical and horizontal directions, a prediction memory structure and a weighted adder structure. In one embodiment of the present invention, a weighted adder structure and a method are provided for performing bilinear interpolation of two values using multiplexers and an multiple-input adder. A structure and a method are provided for accessing a 16 X 16-pixel picture area in two parts, in order that the number of DRAM page boundary crossed during access of the 16 X 16-pixel picture area is minimized, thereby increasing the efficiency of memory access by reducing the overhead cost of initial accesses under page mode access to DRAMs. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a moving picture decoding system which permits to employ inexpensive DRAMs as a predicting memory and to make installation area of the predicting memory small to contribute for downsizing of an LSI. In order to accomplish the above-mentioned and other objects, the present invention provides a moving picture decoding system as defined in independent claim 1. This dependent claims define particular embodiments of the invention. Preferably, access for the storage means is performed by a page mode access of a dynamic memory. Also, the moving picture decoding system may further comprise reading means for reading out the image data from the storage means in an order of raster scanning with taking the luminance components and chrominance components of a plurality of pixels as a unit, and video signal restoring means for restoring a video signal in the order of raster scanning from the image data read out by the reading means. The holding means may be provided for forward prediction and for backward prediction, respectively. In the further preferred construction, the moving picture decoding system further comprises video signal restoring means for restoring the video signal on the basis of the result of calculation by the calculating means, and control means for controlling such a manner that the result of calculation is output to the video signal restoring means via the memory data bus in conjunction with writing of the result of calculation to the storage means. The calculating means may include second memory means for temporarily storing the output of the restoring means per block and restoring means for restoring the image data consisted of the luminance components and chrominance components of a plurality of pixels by calculating the output of the second memory means and the result of calculation by the calculating means. The moving picture decoding system further comprises means for temporarily storing the result of calculation by the calculating means and writing means for writing the temporarily stored result of calculation to the storage means via the memory data bus. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the invention but are for explanation and understanding only. In the drawings: Fig. 1 is a block diagram of one embodiment of a moving picture decoding system according to the present invention; Fig. 2 is a block diagram of another embodiment of a moving picture decoding system according to the present invention; Fig. 3(a) is an illustration showing a page mode access cycle of DRAM; Fig. 3(b ) is an illustration of a write access cycle of a restored image data; Fig. 3(c) is an illustration showing a read access cycle of a predicting reference block out of a page boundary; Fig. 3(d) is an illustration of a read access cycle of a prediction reference block on the page boundary; Fig. 4 is a block diagram of the conventional construction of the moving picture decoding system; and Fig. 5 is a block diagram of another conventional construction of the moving picture decoding system. DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will be discussed with reference to the drawings. Fig. 1 shows one embodiment of a moving picture decoding system according to the present invention, which system is adapted for decoding image data coded without using bidirectional predictive coding. When a code to be decoded is input to a variable length code decoding portion 1 , the variable length code decoding portion 1 restores a quantized discrete cosine transformation (DCT) coefficient to output the quantized DCT coefficient to a reverse quantizing portion 2. In conjunction therewith, the variable length code decoding portion 1 restores a prediction mode and a motion vector information to output the prediction mode and the motion vector information to a predicted value calculating portion 5 and a memory control portion 13. The reverse quantizing portion 2 restores a DCT coefficient from the quantized DCT coefficient to feed the DCT coefficient to a reverse DCT portion 3. The reverse DCT portion 3 restores an interframe difference data or an image data by performing reverse DCT to feed the interframe difference data or the image data to an adder 4. A predicting dynamic memory 12 has a data capacity for two frames for reading and writing and is controlled by an address and a control signal from the memory control portion 13. The memory control portion 13 performs a prediction reference block read control, a restored image data write control, a read control for raster scanning transformation of the restored image data in time sharing manner. During the prediction reference block read control by the memory control portion 13 , a prediction reference block for a preceding frame stored in the predicting dynamic memory 12 is read out according to a prediction mode and a motion vector. The read out prediction reference block is output to a reference block buffer 14. On the other hand, during write control of the restored image data by the memory control portion 13 , data for one macro-block is written in the predicting dynamic memory 12 when data for one macro-block is accumulated in a macro-block buffer 11 . Also, during read control of the restored image data by the memory control portion 13 , the restored image data of the preceding frame in the predicting dynamic memory 12 is read out and output to a line buffer 18 . The reference block buffer 14 temporarily stores the prediction reference block input from the predicting dynamic memory 12 and outputs the prediction reference block to a multiplexer 16 per one word. The multiplexer 16 extracts one sample data of 8 bits from the prediction reference block of the one word unit input from the reference block buffer 14 to output the sample data to the predicted value calculating portion 5 . The predicted value calculating portion 5 is responsive to one sample data input from the multiplexer 16 , to calculate a predicted value at a position corresponding to the output of the reverse DCT portion 3 to output the predicted value to the adder 4 . The adder adds the output of the reverse DCT portion 3 and the output of the predicted value calculating portion 5 to restore the image data. The restored image data is output to the macro-block buffer 11 . When data for one macro-block is accumulated in the macro-block buffer 11 , the data is written in the predicting dynamic memory 12 under the control by the memory control portion 13 . In this case, one word of the restored image data consisted of 2 x 2 samples of luminance component (Y), 1 x 2 samples of Cr component and 1 x 2 samples of Cb component, is written per each address. On the other hand, a memory data bus 100 connecting the macro-block buffer 11 and the predicting dynamic memory 12 performs transfer per one word image data consisted of 2 x 2 samples of luminance component (Y), 1 x 2 samples of Cr component and 1 x 2 samples of Cb component. Accordingly, writing of the restored image data from the macro-block buffer 11 to the predicting dynamic memory 12 is performed per one word of the restored image data consisted of 2 x 2 samples of luminance component (Y), 1 x 2 samples of Cr component and 1 x 2 samples of Cb component. By this, for each address of the predicting dynamic memory, one word of the restored image data is written respectively. The line buffer 18 has two banks of buffers for two lines for respective chrominance components for reading and writing in order to input one word of the restored image data consisted of 2 x 2 samples of luminance component (Y), 1 x 2 samples of Cr component and 1 x 2 samples of Cb component from the predicting dynamic memory 12 via the memory data bus 100 . Namely, when respective two lines of chrominance components of the restored image data from the predicting dynamic memory 12 is written in one of the bank of the line buffer 18 , data is read out in the order to raster scanning from the other bank. Accordingly, the memory capacity of the line buffer 18 is required to be 8 samples x (2 x 2 + 1 x 2 + 1 x 2) blocks x 45 macro-blocks x 2 banks = 45 Kbits. A scanning transformation control portion 19 outputs a control signal to the line buffer 18 to control writing of the restored image data from the predicting dynamic memory 12 and reading of the restored data in the order of raster scanning. It should be appreciated that the macro-block buffer 11 , the reference block buffer 14 and the line buffer 18 are respectively connected to the predicting dynamic memory 12 via the memory data bus 100. The memory data bus 100 has a width of 64 bits to transfer the image data consisted of 2 x 2 samples of luminance component (Y), 1 x 2 samples of Cr component and 1 x 2 samples of Cb component. Next, discussion will be given for access of the predicting dynamic memory by the memory control portion 13 . As access of the predicting dynamic memory 12 by the memory control portion 13 , there are read control of the prediction reference block, write control for the restored image data, read control for raster scanning transformation of the restored image data. When the memory control portion 13 performs write control of the restored image data, the restored image data is written in the predicting dynamic memory 12 by word access for 8 words x 8 times per macro-block. On the other hand, when read control of the prediction reference block is to be performed by the memory control portion 13 , the prediction reference block for one macro-block is required 16 x 16 samples of luminance component (Y) and 8 x 16 samples of the chrominance components if the motion vector makes reference to integer pixel positions. However, when the motion vector makes reference to the intermediate pixel positions (half pel), the prediction reference block is required 17 x 17 samples of the luminance components (Y) and 9 x 17 samples of the chrominance component. Accordingly, in case of the word construction of the shown embodiment, in which one word is consisted of 2 x 2 samples of luminance component (Y), 1 x 2 samples of Cr component and 1 x 2 samples of Cb component, reading of the prediction reference block from the predicting dynamic memory 12 is performed by access of the 9 x 9 words. Furthermore, when read control for raster scanning transformation of the restored image data by the memory control portion 13 , output to the line buffer 18 is performed per word in the horizontal direction instead of outputting per macro-block. Hereinafter, discussion will be given for the case where the pixel rate of 525 line system of CCIR601 by the shown embodiment. At first, considering word access times per 16 lines in the shown embodiment, read of prediction reference block: 9 words x 9 times x 45 macro-blocks = 3645 write of restored image data: 8 words x 8 times x 45 macro-block = 2880 read of restored image data: 360 words x 8 horizontal lines = 2880 and thus 9405 times in total are required. Here, one horizontal line is consisted of 45 macro-blocks. When DRAM (dynamic random-access-memory) is used as the predicting dynamic memory, number of cycles necessary for accessing DRAMs become as follow. Page mode access of the DRAMs become as illustrated in Fig. 3(a) , in which, upon initiation of access, after two cycles, i.e. pre-charge cycle of an RAS signal and a CAS signal and row address cycle R, access is performed by inputting column addresses C0, C1, ..... 8 word access during write control of the restored data by the memory control portion 13 , will not access a page boundary, and thus performed by 10 cycles as shown in Fig. 3(b) . On the other hand, 9 word access in the read control of the prediction reference block by the memory control portion 13 without accessing the page boundary, is performed by 11 cycles as shown in Fig. 3(c) . On the other hand, if access is made to the page boundary, the 9 word access in read control of the prediction reference block by the memory control portion 13 is performed by 13 cycles as shown in Fig. 3(d). Furthermore, in case of access in read control of the restored image data by the memory control portion 13 , page boundary will be included only several times so that pre-charge cycle P and row address cycle R can be ignored. Therefore, one word access can be taken place in approximately one cycle. Accordingly, when DRAMs are used, necessary cycles per 16 lines will be: read of prediction reference block: 13 cycles x 9 times x 45 macro-blocks = 5265 write of restored image data: 10 cycles x 8 times x 45 macro-blocks = 3600 read of restored image data: 360 cycles x 8 horizontal lines = 2880 and thus 11745 cycles in total. Here, number of macro-blocks in one horizontal line is 45. Accordingly, when DRAMs are used, the condition of less than or equal to 13728 cycles per 16 lines necessary for the pixel rate of 525 line system of CCIR601 can be satisfied. In the above-mentioned one embodiment of the invention, by writing the restored image data on the memory data bus in the line buffer 18 in conjunction with writing of the restored image data from the macro-block buffer 11 to the predicting dynamic block 12 , a frame delay which otherwise cased upon transforming into a video signal, can be resolved. It should be appreciated that, in this case, as a capacity of the line buffer 18 , a larger capacity then 2 lines x 2 banks becomes necessary. Fig. 2 is a block diagram showing another embodiment of the moving picture decoding system according to the present invention. In Fig. 2 , the shown embodiment of the moving picture decoding system is adapted to coding adaptively switching intraframe coding, forward predictive coding and bidirectional predictive coding. The shown embodiment of the system is differentiated from the system of Fig. 1 in the following points. Namely, while the former embodiment of the moving picture decoding system employs only one macro buffer 14 for forward prediction, the shown embodiment of the system employs a forward reference macro-block buffer 24 and a backward reference macro-block buffer 25 . It should be noted that the forward prediction reference block and the backward prediction reference block temporarily stored in the forward reference macro-block buffer 24 and the backward prediction reference block 25 respectively are output to the prediction value calculating portion 5 via multiplexers 26 and 27 . Also, a memory control portion 23 of the shown embodiment of the moving picture decoding system is provided a control for a bidirectional predictively coded frame in addition to the control of the memory control portion 13 in the former embodiment. For the bidirectional predictively coded frame requires read control for the forward prediction reference macro-block and read control for the backward prediction reference macro-block. Output of the restored image data of the bidirectional predictively coded frame is performed by writing the restored image data output from the macro-block buffer 11 under the control of a scan transformation control portion 29 to a scanning transforming memory 28 via the memory data bus 100 . Furthermore, in the former embodiment of the invention, the order of data output during read control of the restored image data is per each chrominance component and per one line. In contrast to this, the shown embodiment, the order of data output is per macro-block similarly to inputting of the restored image data from the macro-block buffer 11 adapting to output of data of the restored image data of the bidirectional predictively coded frame. The scanning transforming control portion 29 of the shown embodiment outputs the control signal to the scanning transforming memory 28 to control writing in the input restored image data per macro-block and outputting of the restored image data in the order of raster scanning. In case that the pixel rate of 525 line system of CCIR601 is to be realized by the shown embodiment of the moving picture decoding system of the invention, considering the word access times of the predicting dynamic memory per 16 lines by the memory control portion 23 , the word access times becomes 9405 times similarly to the former embodiment in case of the forward predictive coding is concerned. On the other hand, in case of the bidirectional predictive coding, read of forward prediction reference block: 9 words x 9 times x 45 macro-blocks = 3645 read of backward prediction reference block: 9 words x 9 times x 45 macro-blocks = 3645 and thus in total 7290 times. Here, the number of macro-blocks in one horizontal line is 45. When DRAMs are used as the predicting dynamic memory as in the former embodiment, necessary cycles per 16 lines will be: read of prediction reference block: 13 cycles x 9 times x 45 macro-blocks = 5265 write of restored image data: 10 cycles x 8 times x 45 macro-blocks = 3600 read of restored image data: 10 cycles x 8 times x 45 macro-blocks = 3600 and thus in total 12465 cycles. Here, the number of macro-blocks in one horizontal line is 45. On the other hand, in case of the bidirectional predictive coding, in addition of access of the predicting dynamic memory 12 , it becomes necessary to include the number of cycles for writing of the output data of the macro-block buffer 11 in the scanning transforming memory 28 since the memory data bus 100 is also used therefor. Accordingly, the necessary number of cycles becomes: read of forward prediction reference block: 13 cycles x 9 times x 45 macro-blocks = 5265 read of backward prediction reference block: 13 cycles x 9 times x 45 macro-blocks = 5265 output to scanning transforming memory 28 : 8 cycles x 8 times x 45 macro-blocks = 2880 and thus 13410 in total. Here, the number of macro-blocks in one horizontal line is 45. Therefore, with the shown embodiment, the condition of less than or equal to 13728 cycles necessary for the access rate of 525 line system of CCIR601 can be satisfied. Therefore, the shown embodiment of the system can be adapted to 525 line system of CCIR601. In the foregoing embodiments, discussion has been given for the case the macro-block is consisted of 2 x 2 blocks of luminance component (Y), 1 x 2 blocks of Cr component and 1 x 2 blocks of Cb components according to the sampling ratio of the luminance component and the chrominance components 4:2:2 in 525 line system of CCIR601. However, it is possible to use DRAM as the predicting frame memory, even when the macro-block is consisted of 2 x 2 blocks of luminance component (Y), 1 x 1 blocks of Cr component and 1 x 1 blocks of Cb components according to the sampling ratio of the luminance component and the chrominance components 4:1:1 by setting the bus width of the predicting dynamic memory 12 to 43 bits and making 2 x 2 blocks of luminance component (Y), 1 x 1 blocks of Cr component and 1 x 1 blocks of Cb components as one word. Also, in the foregoing embodiments, as a means for forming the image data with taking 2 x 2 blocks of luminance component (Y), 1 x 2 blocks of Cr component and 1 x 2 blocks of Cb components as one word, the macro-block buffer 11 is provided at later stage of the adder 4 . However, the access method for the predicting dynamic memory 12 in the foregoing embodiments may be applicable by providing means for re-ordering data of one word consisted of 2 x 2 blocks of luminance component (Y), 1 x 2 blocks of Cr component and 1 x 2 blocks of Cb components at the stage of the adder 4 and a latch for accumulating the outputs of the adder 4 for 8 samples at the later stage of the adder 4 . When the above-mentioned system is realized by an integrated circuit, in the first-mentioned embodiment, the portion excluding the predicting dynamic memory 12 may be realized by LSI or a set of several chips. On the other hand, in case of the later-mentioned embodiment, the portion excluding the predicting dynamic memory 12 or excluding the predicting dynamic memory 12 and the scanning transforming memory 28 may be realized by LSI or a set of several chips. As set forth, when the restored image data which is restored by the adder 4 per block is temporarily stored in the macro-block buffer 11 , by re-ordering the data into one word consisted of 2 x 2 blocks of luminance component (Y), 1 x 2 blocks of Cr component and 1 x 2 blocks of Cb components, and by outputting the data per one word to the predicting dynamic memory 12 , reference macro-block buffer 14 or the forward reference macro-block buffer 24 and the backward reference macro-block buffer 25 , and the line buffer 13 or the scanning transforming memory 28 , the predicting dynamic memory 12 can be accessed by page mode access of DRAM. Therefore, inexpensive DRAMs can be used as the predicting dynamic memory. On the other hand, by providing 64 bit width for the memory data bus 100 , the predicting frame memory can be constituted with four DRAMs when x 16 bit construction of 4-Mbit DRAMs are used. Therefore, in comparison with conventional 128 bit bus, installation area can be reduced. Furthermore, since four 4-Mbit DRAMs are employed for necessary capacity of the predicting frame memory of [(720 + 360 x 2) samples x 480 lines x 8 bits x 2 frame = 10.546... Mbits] for 525 line system of CCIR601, non-used area will never been increased. In addition, even when the external memory is used as the scanning transforming memory in integration of the system, it becomes unnecessary to add 64 terminals as terminals for the data bus of the scanning transforming memory and can contribute for down-sizing of the LSI. Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above.

Claims: A moving picture decoding system comprising: restoring means (1,2,3) for restoring an image data on the basis of a discrete cosine transformation coefficient restored from an input code; predicted value generating means (5) for generating a predicted value at a position corresponding to said image data on the basis of a motion vector restored from the input code and a predicting sample data comprising image data read from a storage means (12); calculation means (4) for restoring the image data including a luminance component and a chrominance component by performing a calculation using the output of said restoring means and the predicted value of said predicted value generating means; a memory (100) data bus for transferring said image data produced by said calculation means (4) in units of a plurality of pixels of said luminance components and said chrominance components; storage means (12) for storing said image data in said units per each address via said memory data bus; holding means (14) for holding the image data read from said storage means (12) via said memory data bus per block consisted of m x n pixels, which m and n are positive integers; and means (16) for outputting said image data held by said holding means to said generating means in a multiplexed manner, characterized in that the system further comprises: memory means (11) for temporarily storing the results of calculation of said calculation means for a block unit of image data consist comprising said luminance components and said chrominance components of a plurality of pixels, per address; and writing means for writing the result of calculation held in said memory means in said storage means via said memory data bus (100). A moving picture decoding system as set forth in claim 1, wherein access for said storage means (12) is performed by a page mode access of a dynamic memory. A moving picture decoding system as set forth in claim 2, which further comprises reading means (18) for reading out said image data from said storage means (12) in an order of raster scanning with taking the luminance components and chrominance components of a plurality of pixels as a unit, and video signal restoring means for restoring a video signal in the order of raster scanning from the image data read out by said reading means. A moving picture decoding system as set forth in claim 3, wherein said holding means (24,25) are provided for forward prediction and for backward prediction, respectively. A moving picture decoding system as set forth in claim 4, wherein said video signal restoring means restores the video signal on the basis of the result of calculation by said calculating means (4), and further comprising control means (19) for controlling in such a manner that the result of calculation is output to said video signal restoring means (18) via said memory data bus (100) in conjunction with writing of the result of calculation to said storage means (12).

Inventors: KITSUKI TOSHIAKI, SAWADA AKIRA, KITSUKI, TOSHIAKI, SAWADA, AKIRA, KITSUKI, TOSHIAKI, C/O NEC CORPORATION, SAWADA, AKIRA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H04N7
IPC codes: H04N7, H04N5, G06T9, H03M7