Voltage regulator for non-volatile semiconductor memory devices

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

Description: Field of the invention The present invention relates to an electrically programmable non-volatile semiconductor memory device. More specifically the present invention relates to an electrically programmable non-volatile semiconductor memory device comprising at least one regular memory cell and one dummy memory cell, each memory cell being provided with a first floating gate semiconductor layer and a second superimposed control gate semiconductor layer, said memory device further comprising a voltage regulator with a gain stage supplied by a programming voltage and having an input terminal connected to a divider of said programming voltage and an output terminal connected to a programming line of said at least one regular memory cell. As known an individual non-volatile memory cell comprises an MOS transistor in which the gate electrode located over the channel region is floating, i.e. displays high continuous impedance to all the other terminals of the same cell and of the circuit in which the cell is inserted. The cell also includes a second electrode, called control gate, which is piloted through appropriate command voltages. The other electrodes of the transistor are the usual drain, source and body terminals. By applying appropriate voltages to the cell terminals it is possible to change the charge quantity present in the floating gate, e.g. using known Fowler-Nordheim Tunnelling and/or Channel Hot Electron Injection phenomena. This allows placing the transistor in two logic stages: a first state with "high" threshold voltage and a second state with "low" threshold voltage. If at the control gate is applied a voltage intermediate between these two values it is possible to "read" the state of the transistor since it displays between the drain and source terminals a low or high impedance depending on the threshold voltage value. Therefore said transistor can be considered a logic memory element. Since the floating gate presents a high impedance toward any other cell terminal, the charge stored therein can persist for an indeterminate time even if supply is removed from the circuit in which it is inserted. The cell therefore displays non-volatile memory characteristics. The operation by which the charge is stored in the floating gate is termed "programming" while the operation by which the charge is removed from the floating gate is termed "erasure". Generally a non-volatile memory circuit integrated on a semiconductor comprises a multiplicity of cells of the above type organised in lines called 'word lines', and columns called 'bit lines'. The cells belonging to the same word line have in common the electric line which pilots the respective control gates while the cells belonging to the same bit line have in common the drain terminals. It is also known that non-volatile memory cells and in particular the FLASH type require accurate control of drain voltage Vd during the programming phase, i.e. the voltage applied on the bit line. Said drain voltage must indeed satisfy divers conditions listed below: It must be high enough to allow fast cell programming, it must be at the same time low enough to avoid the so-called 'soft-erasing' phenomenon, which consists of partial erasure of the cell or degradation of the characteristics of the cell with use, and for reliability reasons it must always be such as to avoid setting off the phenomenon known as 'bipolar-parasite'. The optimal interval for such a voltage is in general rather small and typically between 5 and 6 volts. It is noted also that the conditions indicated above are variable depending on the production process and in particular depending on the length of the memory cell. The production processes indeed lead to variations in the dimensions of the cells and in particular of the polysilicon layers and this represents one of the critical parameters in production. Taken all together the above observations lead to the conclusion that it is necessary to equip the memory circuit with a particularly refined and accurate voltage regulator to supply the correct voltage to the bit line in the programming phase. The known art already proposes some solutions to meet this requirement. In general since the voltages supplied from the outside to the memory circuit are substantially two and in particular a 5V supply voltage Vcc and a 12V programming voltage Vpp, control of drain voltage is normally achieved by division of the programming voltage Vpp. In this manner there is achieved a drain voltage relatively stable as concerns temperature and the circuit production process parameters and variable by ± 5 % with the programming voltage Vpp. Prior art In the annexed FIG. 1 is shown diagramatically a first circuit solution of known type provided by using division of the programming voltage. The voltage regulator shown in FIG. 1 comprises a resistive divider consisting of three resistances R 1 , R 2 , R 3 connected between the programming voltage line Vpp and ground. In parallel with said resistances is a group of four MOS transistors connected in series with each other through their respective source and drain terminals. The gate terminals of the first transistor M1 and fourth transistor M4 are connected between the first and second resistances and between the second and third resistances. The voltage applied to the bit line is taken on the gate terminal of the second transistor M2 which is inserted in the circuit in diode configuration with gate and drain short-circuited. Said voltage is actually applied to the bit line unless there is a negative translation of level due to the presence of a first selection transistor M6 and a second selection transistor M7 for writing. Although advantageous from certain viewpoints, this solution is not entirely effective and displays some shortcomings. As already mentioned, the programming current absorbed by the memory cell can vary from one integrated circuit to another because of the inevitable variations inherent in the production process. It can undergo variations also because of the surrounding conditions in which the circuit is made to operate. If the current passing through the bit line and hence the output stage of the regulator is actually different from the one called for by the design it follows that the voltage on the bit line will also be wrong or different from that desired. In addition, since during programming the threshold voltage of the cell tends to rise progressively it follows that the current absorbed by the cell decreases in time. Since with the circuit described above voltage regulation is based on an average programming current, it will not give good results steadily. A second solution of the known art is shown in FIG. 2 and provides that the drain voltage be supplied by a so-called source-follower piloted by an appropriately fedback operational amplifier. Even this solution is not free of shortcomings. In particular, this circuit proved to be slow in the reading phase because it seems to increase the capacitance of the bit line. In addition, it has been observed that with the decrease in the cell dimensions and in particular their actual length, ever closer limits are imposed on drain voltage variation interval and this compromises the reliability and performance of the entire memory circuit. A voltage regulator for a transistor, comprising impedance means to set up the output voltage level with high accuracy, is disclosed in the European Patent Application No. EP-A-0 145 254 in the name of FUJITZU Limited. The technical problem underlying the present invention is to conceive a voltage regulator which would supply the bit line constantly at the output with a voltage such as to pursue optimally production process variations. In other terms, the purpose of the present invention is to conceive a voltage regulator capable of adapting to the actual length of the memory cell, avoiding the introduction of additional circuitry and overcoming the limits of the present solutions. Summary of the invention The solution idea underlying the present invention, as defined by claim 1, is to insert in the regulator a voltage divider varying with the actual length L of the memory cell by utilising the resistivity of the material making up the cell gates. On the basis of this solution idea the technical problem is solved by a voltage regulator of the type set forth above and defined in the characterising part of the annexed claims. The characteristics and advantages of the voltage regulation circuit in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of nonlimiting example with reference to the annexed drawings. Brief description of the drawings In the drawings: FIG. 1 shows a diagram of a programming circuit incorporating a voltage regulator provided in accordance with the known art, FIG. 2 shows another diagram of a programming circuit incorporating another voltage regulator of known type, FIG. 3 shows diagramatically a first embodiment of a regulator in accordance with the present invention, FIG. 4 shows diagramatically a detail of the regulator in accordance with FIG. 3, FIG. 5 shows a diagram of a detail of the embodiment of FIG. 4, FIG. 5A shows diagramatically an embodiment of the detail of FIG. 5, FIGS. 6 to 8 show schematic vertical cross section and enlarged scale views of a portion of an integrated semiconductor memory circuit in which is provided a detail of the regulator of FIG. 3, and FIGS. 9 to 11 show diagrams of additional embodiments of the regulator in accordance with the present invention. Detailed description With reference to the figures 1 designates as a whole and diagramatically a programming circuit for at least one electrically programmable non-volatile memory cell 2, e.g. a FLASH cell. The cell 2 together with other cells of the same type is provided by means of an MOS transistor with floating gate G equipped with another gate CG termed control gate. The cells 2 are organised in columns with the respective source terminals S all connected to the same reference voltage, e.g. a signal ground GND, and with the respective drain terminals D connected together on a so-called bit line 5. The bit line 5 also comprises a pair of MOS transistors MB and MW connected in series together for selection of the bit line 5. The circuit 1 comprises a voltage regulator 3 designed in accordance with the present invention to regulate the drain voltage of the cell 2 during programming thereof and designated below by Vd. For this purpose the regulator 3 comprises a gain stage provided by an operational amplifier Av, e.g. with unit gain, in cascade with which is connected a source-follower stage. The follower stage comprises an MOS transistor Mout polarised by a constant current generator Ib. The amplifier Av has a non-reversing input on which is applied a voltage Vref to be repeated on an output of the regulator 3 to supply the load consisting of the bit line 5. The output U is connected in feedback on another reversing input of the amplifier Av. The above said voltage Vref is achieved by division of a programming voltage Vpp performed by a resistive divider 6 comprising a series of resistors R 1 , R 2 and R 3 . Said resistors R 1 , R 2 and R 3 are inserted between a voltage terminal Vpp and the signal ground. Advantageously in accordance with the present invention the regulator comprises at least one circuit element allowing adaptation of the output voltage to the electrical length L of the memory cell. In the embodiment described here by way of non-limiting example said element is the divider 6 with resistors R 1 , R 2 and R 3 having resistivity varying with the length L of the memory cells 2. In accordance with the present invention the divider 6 is advantageously provided by using portions of the same material of which are made the gate terminals of the memory cell and thus utilising the internal resistivity of said material. These gate terminals consist typically of n+ doped polysilicon, or silicide, but the idea can be extended to any other technology for embodiment of gates, e.g. utilisation of p+ doped polysilicon. The more general form of the variable divider 6 is given in FIG. 4 in which said divider 6 comprises N resistances R 1 , R 2 , ..., R N , each of which is in turn obtained as the parallel of M resistances r N1 , r N2 , ..., r NM , where the value of M is chosen on the basis of the value of N. Every resistance r NM is provided by means of a section of n+ doped polysilicon having length L NM and width W NM . The value of said resistances r NM varies with the width W N of the material portion. The width W N can be greater or less than the design dimensions in accordance with an appropriately set quantity which can be designated by D. Said quantity D is linked to process differences such as over- or under- lithographic exposure, variation of the slope of the attack profile, etc. Consequently, even the value of resistance Rn depends on the difference D between the dimension obtained in the embodiment and the design dimension. To illuminate said dependence let us use the notation r NM (D) and R NM (D). The simplest embodiment of this variable divider 6 is obtained with a series of only two resistances R NM where N=2 and each of which is provided by a single resistance r NM where M=1. This embodiment is shown diagramatically in FIG. 5 by way of non-limiting example as concerns the invention. Therein a variable reference voltage V(D) is taken in the node N1 intermediate between a first resistance R 1 (D) and a second resistance R 2 (D) varying with the actual length L of the cell. These resistances R NM can be achieved in practice in various ways. The non-volatile memory cell 2 is the so-called double polysilicon level type. Basically, the heart of the cell comprises an MOS transistor with the floating gate G provided by means of a polycrystalline silicon layer S1. Over the floating gate G is provided the control gate electrode CG provided by means of a superimposed polysilicon and silicide layer S2. The control gate CG is coupled capacitively with the floating gate G by means of an intermediate dielectric layer S3. The control gate electrode CG is in common with all the cells making up the same line or word line. To provide the variable resistances it is thus possible to use the conductor layers which constitute the gates of the word line cells of the memory matrix. Advantageously there are used appropriately word lines purposely introduced and termed hereinafter dummy word lines. These are lines of overabundant cells purposely inserted in the memory structure and analogous for example to the so-called redundant lines provided for safety reasons. The dummy word lines used must have appropriate relative widths and lengths W 1 and W 2 . The variable resistances R 1 , ..., R NM are provided by means of the polysilicon and silicide conductor layer S2 of the control gate G of the dummy word line cells as shown in FIG. 6. Similarly it is possible to use the polysilicon conductor layer S1 making up the cell floating gates CG as shown in FIG. 7. In this case the structure of the first polycrystalline silicon layer S1 underlying the dummy word lines used must be unbroken. This solution, as it can make use of a construction process capable of providing a contact with the first polycrystalline silicon layer S1, is the one that ensures the least current absorption. Indeed, said first polycrystalline silicon layer S1 has typically an intrinsic resistance much higher than that of the second polysilicon and silicide layer S2. In this configuration it is also easier to connect in series with the divider 6 an MOS transistor having negligible resistance compared with that of the divider and which is used to break the path between the programming voltage (Vpp) and the ground reference voltage (GND) in those cases where the overall absorption of the memory chip must be minimal, e.g. in stand-by or deep power down situations. A third embodiment variation consists of using the two solutions proposed above short-circuiting the first polycrystalline silicon layer S1 and the second polycrystalline silicon layer S2 of the dummy word lines and providing the resistances R 1 , ..., R NM by means of both layers as shown in FIG. 8. These solutions can be provided by using the dummy word lines in the matrix of memory cells of the device. This approach is advantageous in terms of space because it utilises a limited number of dummy word lines. As an alternative, said dummy word lines can also be provided outside the cell matrix in an area purposely dedicated to reception thereof. Whatever the method of embodiment with which the variable resistive divider 6 is achieved, there are no limitations on its use in the voltage regulator 1, which uses a fixed voltage division (typically Vpp) to generate one or more reference voltages. The structure of the regulator 1 of a programming voltage Vd of at least one cell in a non-volatile memory device proposed in FIG. 3 can be modified within the scope of the present invention. Said regulator 1 must however include a gain stage supplied with a fixed programming voltage Vpp and having an input terminal connected to the variable divider 6 of said programming voltage and an output terminal connected to the programming line Vd of at least one memory cell. FIGS. 9 to 11 show by way of example and not exhaustively other embodiments of a voltage regulator in accordance with the present invention. The use of dummy gates as variable resistances in accordance with the present invention ensures the most complete correspondence of cell gate dimension variations with the resistances of the divider 6 to overcome the problems of the known art solution. Indeed, the resistances R NM (D) are achieved by means of the parallel of resistances r NM (D) provided with the same material in such a manner that a variation in the intrinsic resistance of the polysilicon does not alter the potential at the intermediate nodes. Furthermore, the sizing of the regulator in accordance with the present invention is very easy because the regulator comprises a purely resistive divider 6 and does not require the precautions necessary in sizing any added circuit structure. Concretely, having on the drain terminal of the cell 2 a drain voltage varying with the actual length of the cell means being able to operate with cells having an actual length which can vary in a broader range, thus improving the performance, feasibility and reliability of the memory circuit. In conclusion the main advantage of the voltage regulator in accordance with the present invention is to supply at output a voltage whose value is constantly and appropriately adapted to the dimensions of the cell. Said regulator is therefore particularly suited to supplying power to the bit line of an electrically programmable non-volatile memory.

Claims: Electrically programmable non-volatile semiconductor memory device comprising at least one regular memory cell (2) and one dummy memory cell, each memory cell being provided with a first floating gate semiconductor layer (S1) and a second superimposed control gate semiconductor layer (S2), said memory device further comprising a voltage regulator with a gain stage (3) supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of said at least one regular memory cell (2) characterised in that the divider (6) comprises a series circuit of a plurality of resistors (R 1 , R 2 , ..., R NM ) at least one of which comprises said first or second semiconductor layer (S1, S2) of the dummy cell, whereby the resistance of said at least one resistor is correlated with the length (L) of the regular memory cell (2). Memory device in accordance with claim 1 characterised in that said resistors (R 1 , R 2 , ..., R NM ) are provided in the second control gate semiconductor layer (S2) of polysilicon and silicide. Memory device in accordance with claim 1 characterised in that said resistors (R 1 , R 2 , ..., R NM ) are provided in the first floating gate semiconductor layer (S1) of polycrystalline silicon. Memory device in accordance with claim 3, characterised in that the structure of said first semiconductor layer (S1) is unbroken. Memory device in accordance with claim 1 characterised in that said first semiconductor layer (S1) and second semiconductor layer (S2) are mutually short-circuited. Memory device in accordance with claim 5 characterised in that said resistors (R 1 , R 2 , ..., R NM ) are provided in the mutually short-circuited first and second semiconductor layers (S1, S2) Memory device in accordance with any of claims 1 to 6 in which the memory device comprises a cell matrix characterised in that said resistors are provided in dummy word lines incorporated in the memory device inside the cell matrix. Memory device in accordance with any of claims 1 to 6 in which the memory device comprises a cell matrix characterised in that said resistors are provided in dummy word lines incorporated in the memory device outside the cell matrix.

Inventors: CAMERLENGHI EMILIO, CASAGRANDE GIULIO, CAMERLENGHI, EMILIO, CASAGRANDE, GIULIO,, CASAGRANDE, GIULIO, C/O SGS-THOMSON MICR.SRL
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C16
IPC codes: G11C16, G11C5, G11C17