Method and apparatus for detecting a frame sync signal

Abstract: A frame sync detecting apparatus comprises a frame sync detector (21), a pseudo sync detector (22), a frame sync protector (23) and an AND gate (24). The frame sync detector (21) produces a frame sync detect signal (D SYNC ) in response to an input signal (MAC DATA). The pseudo sync detector (22) counts horizontal lines of a video signal and outputs a pseudo sync detect signal (P SYNC ) corresponding to the expected location of a sync signal. The frame sync protector (23) compares the frame sync detect signal (D SYNC ) and the pseudo frame sync detect signal (P SYNC ) and controls the output of the AND gate 24 to be either the frame sync detect signal (D SYNC ) or the pseudo frame sync detect signal (P SYNC ). The output from the AND gate 24 is fedback to reset the pseudo sync detector (22).

Description: The present invention relates to a frame sync signal detecting apparatus for a raster scan video system comprising a frame sync detector for detecting a frame sync pattern in an input video signal to produce a frame sync detect signal and a method of detecting a frame sync signal in a raster scan video signal, comprising the step of detecting a frame sync signal to produce a frame sync detect signal. The present invention has particular, although not exclusive, application to the D2 MAC system. The frame sync signal of a D2 MAC signal comprises a 64-bit code in line 625. Figure 1 illustrates the structure of a frame of a D2 MAC signal. One frame in the D2 MAC signal consists of 625 lines, lines 1 to 624 each having a period of 64 microseconds and containing video, audio and information data. Line 625 differs from the other lines and comprises an initial 6 bits containing line sync data, 32 bits of clock data (555 555 HEX), a 64-bit frame sync signal (65AE F315 3F41 C246 HEX) and other service data. Conventionally, the frame sync signal is detected by comparing data in an input D2 MAC signal with a 64-bit reference code. Since a plurality of registers is required to enable comparison of the full 64-bit pattern, the known system is undesirably complex and is sensitive to errors in the received sync signal. It is an aim of the present invention to overcome the above-mentioned disadvantages of the prior art. An apparatus according to the present invention is characterised by the frame sync detector being responsive to a predetermined portion of the frame sync pattern to generate the frame sync detect signal and a pseudo frame sync detector for generating a pseudo frame sync detect signal at a predicted frame sync pattern timing, and frame sync signal generating means for selectively outputting the frame sync detect signal or the pseudo frame sync detect signal in dependence on the degree of temporal agreement therebetween during a predetermined number of frames. Preferably, the frame sync signal generating means outputs the frame sync detect signal in response to a mismatch occurring between the frame sync detect signal and the pseudo frame sync detect signal during a predetermined number of successive frames. More preferably, the predetermined number is 7. Preferably, the frame sync signal generating means outputs the pseudo frame sync detect signal in response to a match occurring between the frame sync detect signal and the pseudo frame sync detect signal during a further predetermined number of successive frames. More preferably, further predetermined number is 3. Preferably, the pseudo frame sync detector includes a first counter for counting horizontal sync signals and a second counter for counting a predetermined number of bit periods within a horizontal line identified by the first counter. Preferably, the frame sync detector comprises a comparator for comparing an input data signal with a reference code. Advantageously, the reference code corresponds to a predetermined portion of a frame sync pattern, for instance the last 16-bits thereof. A method according to the present invention is characterised by the steps of: generating a pseudo frame sync detect signal at a predicted frame sync pattern timing; and selectively outputting the frame sync detect signal or the pseudo frame sync detect signal in dependence on the degree of temporal agreement therebetween during a predetermined number of frames. Preferably, the frame detect signal is output in response to a mismatch occurring between the frame sync detect signal and the pseudo frame sync detect signal during a predetermined number of successive frames. More preferably, the predetermined number is 7. Preferably, the pseudo frame detect signal is output in response to a match occurring between the frame sync detect signal and the pseudo frame sync detect signal during a further predetermined number of successive frames. More preferably, said further predetermined number is 3. Preferably, the psuedo frame sync detect signal is generated by counting a predetermined number of horizontal lines and then counting a predetermined number of bit periods in a horizontal line. Preferably, the frame sync detect signal is generated by comparing an input data signal with a reference code. Advantageously, the reference code corresponds to a predetermined portion of a frame sync pattern, for instance the last 16 bits thereof. An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a conceptual diagram showing a frame of a D2 MAC signal; Figure 2 is a block diagram showing a preferred embodiment of the present invention; Figure 3 is a waveform diagram for a part of the device of Figure 2; Figure 4 is a block diagram of a part of the device of Figure 2; Figure 5 is a block diagram of a part of the device of Figure 2; and Figure 6 is a block diagram of a part of the device of Figure 2. Referring to Figure 2, the apparatus comprises a frame sync detector 21 for detecting the frame sync patterns in an input MAC signal and outputting a sync pattern detect signal (D SYNC ); a pseudo sync detector 22 for receiving input line horizontal sync data (H SYNC ) and a fedback frame sync detecting signal (F SYNC ) and outputting a pseudo sync detect signal (P SYNC ); a frame sync protector 23 for receiving the sync pattern detect signal (D SYNC ) and the pseudo sync detect signal (P SYNC ) and outputting a final decision signal (S T ) and a sync detect error signal (E SYNC ); and an AND gate 24 for receiving the final decision signal (S T ) and the pseudo sync detecting signal (P SYNC ) and outputting the frame sync detecting signal (F SYNC ). MAC data at 10.125 Mbits/sec and a clock (CLK) at 10.125 MHz are respectively input into the frame sync detector 21. The frame sync detector 21 generates the sync pattern detect signal in the form of a low going pulse when the final "6 HEX" of the 64-bit frame sync data ("625AE F315 3F41 C245 HEX") which is included in the 625th line, has been input. Figure 3 shows the waveform of the sync pattern detect signal (D SYNC ). The pseudo sync detector 22 receives the horizontal sync data (H SYNC ) of each line and the 10.125 MHz clock and outputs the pseudo sync detect signal (P SYNC ) as a low-going pulse at the end point of the frame sync data of the 625th line. The frame sync protector 23 receives the sync pattern detect signal (D SYNC ), output by the frame sync detector 21, and the pseudo sync detect signal (P SYNC ), provided from the pseudo sync detector 22, and outputs the result after deciding whether the pulse positions of the two signals are in accord by comparing the two signals. If the sync pattern detecting signal (D SYNC ) is not in agreement with the pseudo sync detect signal (P SYNC ), the frame sync protector 23 outputs the sync detect error signal (E SYNC ) as a high level signal and outputs simultaneously the sync pattern detect signal (D SYNC ) as the final decision signal (S T ). While if the two signals are in agreement, the frame sync protector 23 outputs the sync detect error signal (E SYNC ) as a low level signal and outputs simultaneously a high level constant signal as the final decision signal (S T ). When a high level final decision signal (S T ) is applied to the AND gate 24, the pseudo sync detect signal (P SYNC ) is output as the frame sync detect signal (F SYNC ) and the frame sync detect signal (F SYNC ) is fed back to the pseudo sync detector 22, to reset the pseudo sync detector 22. The form and operation of each block in Figure 2 will be given in detail below. Referring to Figure 4, the D2 MAC data, which is input in series, is converted into 16-bit parallel data in accordance with the clock (CLK) in a serial/parallel converter 41. A sync pattern generator 42 outputs C246 (HEX) corresponding to the last 16 bits of the frame sync data. A comparator 43 compares the 16 bit parallel MAC data, which is input from the serial/parallel coverter 41, with the 16 bit data (C246 HEX) which is input from the sync pattern generator 42. When the two data words are in agreement, the comparator 43 generates the sync pattern detect signal (D SYNC ) as a low going pulse as shown in Figure 3. Referring to Figure 5, a line counter 51 counts the input horizontal sync data (H SYNC ), and outputs a 625 line detect signal (D 625 ) as high level signal as soon as it counts the horizontal sync data of the 625th line. The 625 line detecting signal (D 625 ) enables a bit-counter 52. The bit-counter 52 starts counting in accordance with the clock. The bit-counter 52 counts up to 96 bits and generates the pseudo sync detect signal (P SYNC ) as a low-going pulse at the 96th bit. Thus, the pseudo sync detecting signal (P SYNC ) corresponds with the end position of the frame sync data which is in the 625th line. The count values of the line counter 51 are reset by the fedback frame sync detecting signal (F SYNC ). Referring to Figure 6, a comparator 61 compares the sync pattern detecting signal (D SYNC ), which is supplied from the frame sync detector, with the pseudo sync detecting signal (P SYNC ), which is supplied from the pseudo sync detector, and determines whether the two signals are in agreement. When the two signals (D SYNC , P SYNC ) are in agreement, the comparator 61 generates a corresponding sync signal (S1) as a high level signal. The corresponding sync signal (S1) is input to the clock terminal of the corresponding sync counter 62. For example, in the case that the corresponding sync counter 62 is a modulo-3 counter, when a high level corresponding sync signal (S1) from the comparator 62 is input 3 times, that is, the sync pattern detecting signal (D SYNC ) continuously corresponds with the pseudo sync detecting signal (P SYNC ) for three frames, the corresponding sync counter 62 generates a designated reset signal (RST). The reset signal (RST) resets an uncorresponding sync counter 63. When the sync pattern detect signal (D SYNC ) does not correspond with the pseudo sync detecting signal (P SYNC ) in the comparator 61, the comparator 61 generates a uncorresponding sync signal (S2) as a high level signal and inputs it to the clock terminal of the uncorresponding sync counter 63. For instance, in the case that the uncorresponding sync counter 63 is a modulo-7 counter, when a high level uncorresponding sync signal (S2), generated by the comparator 61, is input 7 times, that is, the sync pattern detect signal (D SYNC ) continuously does not agree with the pseudo sync detecting signal (P SYNC ) for seven frames, the uncorresponding sync counter 63 generates the sync detect error signal (E SYNC ) as a high level signal. The sync detect error signal (E SYNC ) is input to a selecting terminal of multiplexer 64. An input terminal (H) of the multiplexer 64 receives the sync pattern detect signal (D SYNC ) and another terminal (L) is connected to a constant DC voltage (Vcc). The multiplexer 64 outputs one of the input signals as the final decision signal (S T ) in response to the state of sync detect error signal (E SYNC ) applied to a selection terminal (SEL). In the case where the sync detect error signal (E SYNC ) is a high level signal, the multiplexer 64 outputs the sync pattern detecting signal (D SYNC ) as the final decision signal (S T ). While in the case that the sync detect error signal (E SYNC ) is a low level signal, the multipliexer 64 outputs the constant voltage signal (Vcc) as the final decision signal (S T ). Referring again to Figure 2, the final decision signal (S T ), generated by the frame sync protector 23, is input to one input terminal of the AND gate 24, and the pseudo sync detecting signal (P SYNC ) is provided to the other terminal. In the case that errors are generated beyond the predetermined limit, that is, errors are generated in seven successive frames, the sync pattern detect signal (D SYNC ) is input to the AND gate 25 as the final decision signal (S T ). Then, the AND gate 24 logically AND-operates the sync pattern detect signal (D SYNC ) and the pseudo sync detect signal (P SYNC ) and outputs the appropriate frame sync detect signal (F SYNC ). The frame sync detect signal F( SYNC ) is fedback to the psuedo sync detector 22 to reset the line counter 51. Since the frame sync detect signal (F SYNC ) is equal to the sync pattern detect signal (D SYNC ), the frame sync detect signal (F SYNC ) has a low-going pulse at the end position of the frame sync data. The line counter 51 counts the first line of the frame when an input signal changes state from low to high. In the case where there are no errors within a predetermined limit, the constant voltage signal (Vcc) is input to the AND gate 24 as the final decision signal (S T ). Then, the AND gate 24 logically AND-operates the constant voltage signal (Vcc) and the pseudo sync detect signal (P SYNC ) and outputs the appropriate frame sync detect signal (F SYNC ). The frame sync detect signal (F SYNC ) is fedback to the pseudo sync detector 22 to reset the line counter 51. As described above, a system for detecting the frame sync data of the D2 MAC signal in accordance with the present invention is simple in structure because it examines only whether errors exist the last 16 bits (C245 HEX) of the 64-bit frame sync data. Though there are some errors due to transmission, the system disregards minor errors and outputs the frame detect signal as long as there are no errors within a predetermined number of successive frames. Accordingly, the system has the effect of protecting the frame sync data. In the case where there are errors in a predetermined number of successive frames, it generates the error signal on determining an error state, thereby preventing frame sync errors.

Claims: A frame sync signal detecting apparatus for a raster scan video system comprising a frame sync detector (21) for detecting a frame sync pattern in an input video signal (MAC DATA) to produce a frame sync detect signal (D SYNC ), characterised by the frame sync detector being responsive to a predetermined portion of the frame sync pattern to generate the frame sync detect signal, a pseudo frame sync detector (22) for generating a pseudo frame sync detect signal (P SYNC ) at a predicted frame sync pattern timing, and frame sync signal generating means (23, 24) for selectively outputting the frame sync detect signal (D SYNC ) or the pseudo frame sync detect signal (P SYNC ) in dependence on the degree of temporal agreement therebetween during a predetermined number of frames. Apparatus according to claim 1, wherein the frame sync signal generating means (23, 24) outputs the frame sync detect signal (F SYNC ) in response to a mismatch occurring between the frame sync detect signal (D SYNC ) and the pseudo frame sync detect signal (P SYNC ) during a predetermined number of successive frames. Apparatus according to claim 2, wherein said predetermined number is 7. An apparatus according to claim 1, 2 or 3, wherein the frame sync signal generating means (23, 24) outputs the pseudo frame sync detect signal (P SYNC ) in response to a match occurring between the frame sync detect signal (D SYNC ) and the pseudo frame sync detect signal (D SYNC ) during a further predetermined number of successive frames. An apparatus according to claim 4, wherein said further predetermined number is 3. An apparatus according to any preceding claim, wherein the pseudo frame sync detector (22, 23) includes a first counter (51) for counting horizontal sync signals (H SYNC ) and a second counter (52) for counting a predetermined number of bit periods within a horizontal line identified by the first counter (51). An apparatus according to any preceding claim, wherein the frame sync detector (21) comprises a comparator (43) for comparing an input data signal (MAC DATA) with a reference code. An apparatus according to claim 7, wherein the reference code corresponds to said predetermined portion of the frame sync pattern. An apparatus according to claim 8, wherein the reference code comprises the last 16 bits of a frame sync pattern. An apparatus according to any preceding claim, wherein the frame sync detector (21) is arranged to detect a D2 MAC frame sync pattern. A method of detecting a frame sync signal in a raster scan video signal, comprising the step of: (a) detecting a frame sync signal to produce a frame sync detect signal (D SYNC ), characterised by the steps of: (b) generating a pseudo frame sync detect signal (P SYNC ) at a predicted frame sync pattern timing; and (c) selectively outputting the frame sync detect signal (D SYNC ) or the pseudo frame sync detect signal (P SYNC ) in dependence on the degree of temporal agreement therebetween during a predetermined number of frames. A method according to claim 11, wherein the frame detect signal (D SYNC ) is output in step (c) in response to a mismatch occurring between the frame sync detect signal (D SYNC ) and the pseudo frame sync detect signal (P SYNC ) during a predetermined number of successive frames. A method according to claim 12, wherein said predetermined number is 7. A method according to claim 11, 12 or 13, wherein the pseudo frame detect signal (P SYNC ) is output in step (c) in response to a match occurring between the frame sync detect signal (D SYNC ) and the pseudo frame sync detect signal (P SYNC ) during a further predetermined number of successive frames. A method according to claim 14, wherein said further predetermined number is 3. A method according to any one of claims 11 to 15, wherein step (b) comprises counting a predetermined number of horizontal lines and then counting a predetermined number of bit periods in a horizontal line. A method according to any one of claims 11 to 16, wherein step (a) comprises comparing an input data signal with a reference code. A method according to claim 17, wherein the reference code corresponds to a predetermined portion of a frame sync pattern. A method according to claim 18, wherein the reference code comprises the last 16 bits of a frame sync pattern. A method according to any one of claims 11 to 19, wherein the raster scan video signal is a D2 MAC signal.

Inventors: HAN HONGSOO, HAN, HONGSOO
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1993
Main classification: H04N5
IPC codes: H04N5, H04N7