Process for the manufacturing of integrated circuits, particularly of intelligent power semiconductor devices

Abstract: A process for the manufacturing of integrated ciruits comprises the steps of: forming an oxide layer (5,6) on at least one surface of two respective semiconductor material wafers (1,2); obtaining a single semiconductor material wafer with a first layer (3,9) and a second layer (2) of semiconductor material and a buried oxide layer (8) interposed therebetween starting from said two semiconductor material wafers (1,2) by direct bonding of the oxide layers (5,6) previously grown; submitting the single wafer to a controlled reduction of the thickness of the first layer (3,9) of semiconductor material; lapping a top surface of the first layer (3,9) of semiconductor material; selectively introducing dopant impurities into selected regions (12,13,14) of the first layer (3,9) of semiconductor material to form the desired integrated components; forming trenches (18) laterally delimiting respective portions of the first layer (3,9) of semiconductor material wherein integrated components are present which are to be electrically isolated from other integrated components; filling the trenches (18) with an insulating material (20).

Description: The present invention relates to a process for the manufacturing of integrated circuits, particularly of intelligent power semiconductor devices. In the manufacturing of integrated circuits the problem exists of obtaining chip regions which are electrically insulated from one another. For example, in power semiconductor devices provided with on-chip driving circuitry (also called intelligent power semiconductor devices), the power device must be electrically insulated from the driving circuitry. The most common technique is PN junction isolation. Such technique however gives rise to some problems, expecially related to the introduction of parasitic components. Considering for example a Vertical Intelligent Power semiconductor device (VIP), such as an NPN power bipolar transistor constituted by an N++ emitter region diffused into a P-type base region which is in turn diffused into an N-type epitaxial layer representing the collector of the transistor, the driving circuitry is obtained inside a P-type well which is diffused into the N-type epitaxial layer and connected to the lowest voltage among those utilized in the chip, to keep the P-type well / N-type epitaxial layer junction reverse biased; inside the P-type well, vertical NPN transistors and lateral PNP transistors are generally obtained. In such structure, a number of parasitic bipolar transistors are present, both NPN and PNP, having base, emitter and collector represented by the various P-type or N-type regions inside the P-type well, the P-type well itself and the N-type epitaxial layer; another PNP parasitic transistor has emitter, base and collector respectively represented by the P-type base region of the power transistor, the N-type epitaxial layer and the P-type well. All such parasitic components limit the VIP performances. Nakagawa et al. disclosed in the proceedings of the 19th Annual IEEE Power Electronics Specialists Conference (Kyoto, Japan, 11-14 April 1988), pages 1325 to 1329, a process for forming low and high power devices in a SOI substrate obtained by bonding. The process requires to form the SOI substrate, remove the thin silicon down to the insulating oxide and epitaxially refill with silicon where the high power devices are to be formed. Another process is known from WO-A-87 06 060. After forming the SOI substrate, the thin silicon layer is partially removed, and low power devices are formed on the remaining thin SOI layer while high power devices are formed where the thin SOI layer has been removed. In view of the state of art described, object of the present invention is to realize a process for the manufacturing of an intelligent power semiconductor device, allowing to obtain devices wherein the electrical insulation between various semiconductor regions does not give rise to parasitic components. According to the present invention, such object is attained by means of a process as set forth in claim 1. It is thus possible to fabricate intelligent power semiconductor devices with an integrated driving circuitry, which are not affected by the presence of parasitic devices since the electrical isolation between the power devices and the driving circuitry and between the various components of the driving circuitry is not accomplished by means of junction isolation, but by means of dielectric isolation. The features of the present invention will be made more evident by the following detailed description of its preferred embodiment, illustrated as a non-limiting example in the annexed drawings, wherein: Figures 1 to 7 are cross-sectional views of a part of an integrated circuit taken at intermediate steps of a manufacturing process according to the preferred embodiment of the invention. A manufacturing process according to the invention starts from two distinct silicon wafers 1 and 2, generally doped with donors impurities: a first wafer 1 comprises an N-type semiconductor bulk 9 and an N+ heavily doped silicon layer 3 at its bottom surface; the second wafer 2 has resistivity and thickness values depending on the particular power device that is to be obtained. The two silicon wafers 1 and 2 are then submitted to a thermal oxidation process, to grow on the bottom surface of the first wafer 1 and on the top surface of the second wafer 2 respective thermal oxide layers 5 and 6; during this step, thermal oxide layers 4 and 7 are also grown on the top surface of the first wafer 1 and the bottom surface of the second wafer 2, respectively (Fig. 1). The two wafers 1 and 2 are then bonded together by means of the so-called "Silicon Direct Bonding" (SDB) technique, known per-se and described for example in the European Patent Application EP-A-0 366 208. According to such technique, after this step a single silicon wafer is obtained from the two silicon wafers 1 and 2, the bottom oxide layer 5 of the first wafer 1 and the top oxide layer 6 of the second wafer 2 constituting a single oxide layer 8 sandwiched between the second wafer 2 and the N+ layer 3 of the first wafer 1, and thus buried under the first wafer 1 (Fig. 2). Among the various Silicon On Insulator (SOI) techniques, the SDB technique allows to obtain buried oxide layers of better quality. The top oxide layer 4 of the first wafer 1 and the bottom oxide layer 7 of the second wafer 2 are then removed, and the N-type semiconductor bulk 9 of the first wafer 1 is submitted to a controlled reduction of its thickness. The top surface of the N-type semiconductor bulk 9 of the first wafer 1 is then polished by means of a precision lapping and polishing machine (with a thikness tolerance of about 0.1 µm). The top surface of N-type semiconductor bulk 9 of the first wafer 1, at the end of these steps, represents the top side of the single silicon wafer composed by the two bonded silicon wafers 1 and 2 (Fig. 3). When the integrated device to be fabricated is a Vertical Intellingent Power (VIP) device, such as a bipolar power transistor, the N-type semiconductor bulk 9 and the N+ layer 3 of the first wafer 1 are selectively etched and removed down to the single oxide layer 8: at the end of this step, in all the regions 10 of the single silicon wafer wherein power devices are to be fabricated the buried oxide layer 8 is uncovered, while in all the regions 11 reserved to the driving circuitries for the power devices the oxide layer 8 is still buried under the N-type semiconductor bulk 9 and the N+ layer 3 (Fig. 4). It is important to note that the etching angle α should be as small as possible, to avoid the creation of high steps so that the following depositions of the various layers (such as vapox, aluminium, nitride, etc.) is facilitated. After this step, a thermal oxide is grown over the entire top surface of the wafer, i.e. over the top surface of the N-type silicon bulk 9 (in the wafer regions 11) and over the uncovered oxide layer 8 (in the wafer regions 10). From now on, the power devices and their driving circuitries are fabricated into the respective wafer regions 10 and 11 according to a standard and per-se known manufacturing process; it is to be noted that if the depth of field of the photolitographic apparatus employed in the manufacturing process is lower than the difference in height between the wafer regions 11 and 10, all the photolitographic steps in the wafer regions 10 reserved to the power devices are to be performed separately from those in the wafer regions 11 reserved to the driving circuitries. Figure 5 shows in an enlarged scale a part of a wafer region 11 wherein a vertical NPN transistor is present: as known to anyone skilled in the art, the transistor comprises a P-type base region 12 diffused into the N-type semiconductor bulk 9, and an N+ emitter region 13 diffused into said base region 12; the collector region is represented by a portion of the N-type semiconductor bulk 9 which is located under the emitter region 13; when the transistor is biased in the forward active region, electrons are injected from the emitter region 13 into the base region 12 wherefrom they diffuse into the collector region; the N+ layer 3 represents a buried layer offering a low resistive path for the electrons to an N+ collector contact region 14. To electrically insulate the transistor shown in Figure 5 from other integrated components defined in the same wafer region 11, the process according to the invention provides for the realization of vertical trenches. To obtain said trenches, a per-se known technique is used providing for the deposition over the top surface of the N-type silicon bulk 9 of an insulating material layer generally composed by three layers: from bottom up, a thin thermal oxide layer 15, a nitride layer 16 and a vapour-deposited oxide layer ("vapox") 17 (Fig. 5). Successively, the three layers 15, 16 and 17, together with the N-type semiconductor bulk 9 and the N+ layer 3, are selectively etched down to the buried oxide layer 8, to form a trench 18 around the lateral transistor shown, as well as around all the other elements of the driving circuitry in the wafer region 11 which are to be electrically isolated from one another (Fig. 6). The trench 18 must then be filled with an insulation material. According to the known technique, the walls of the trench 18 are preliminary covered by an oxide layer 19, and the trench 18 is filled with amorphous silicon 20. In this way the wafer region 11 is divided into portions which are electrically insulated from one another laterally by means of the trench 18, and at the bottom by means of the buried oxide layer 8. The top surface of the N-type silicon bulk 9 is then planarized, the three layers 15, 16 and 17 are removed from the surface of the N-type bulk 9, and a thermal oxide layer 21 is grown over the entire surface; said oxide layer 21 is then selectively etched to form contact areas 22 (Figure 7), and an aluminium layer (not shown) is deposited over the thermal oxide layer 21 and selectively etched to form the desired pattern of interconnection lines between the various components. The process according to the invention is suitable for the manufacturing of integrated circuits in general, and not only of VIP devices.

Claims: Process for the manufacturing of an intelligent power semiconductor device comprising at least one vertical power device and an integrated driving circuitry, characterized by comprising the following steps: a) forming an oxide layer (5,6) on at least one surface of two respective silicon wafers (1,2); b) obtaining a single silicon wafer with a first layer (3,9) and a second layer (2) of silicon and a buried oxide layer (8) interposed there between starting from said two silicon wafers (1,2) by direct bonding of the oxide layers (5,6) previously grown; c) submitting the single silicon wafer to a controlled reduction of the thickness of the first layer (3,9) of silicon; d) lapping a top surface of the first layer (3,9) of silicon; e) selectively etching the first silicon layer (3,9) down to the buried oxide layer (8) to obtain a vertical power device portion (10) of the single silicon wafer (2) wherein the buried oxide layer (8) is uncovered and a circuitry portion (11) of the single silicon wafer (1) wherein the buried oxide layer (8) is covered by the first silicon layer (3,9); f) selectively introducing dopant impurities into selected regions of the second layer (2) of silicon in said vertical power device portion (10) to form the desired vertical power device; g) selectively introducing dopant impurities into selected regions (12,13,14) of the first layer (3,9) of silicon, placed at a different height with respect to said second layer (2), in said circuitry portion (11) to form the desired integrated driving circuitry; h) forming an insulating material layer (15,16,17) over the top surface of the first layer (3,9) of semiconductor material; i) selectively etching the insulating material layer (15,16,17) and the first silicon layer (3,9) down to the buried oxide layer (8) to form trenches (18) laterally delimiting respective portions of the first silicon layer (3,9), defined in the same circuitry portion (11), wherein integrated components of the integrated driving circuitry are present which are to be electrically isolated from other integrated components; l) filling the trenches (18) with an insulating material (20). An intelligent power semiconductor device chip comprising at least one vertical power device and an integrated driving circuitry, fabricated by means of a manufacturing process according to claim 1, characterized by comprising at least one first chip portion (11) wherein a first layer (3,9) of silicon is superimposed over a buried oxide layer (8) sandwiched between said first layer (3,9) of silicon and a second layer (2) of silicon, the first layer (3,9) of silicon being divided into electrically isolated portions defined by respective trenches (18) extending from a top surface to the buried oxide layer (8) and filled with amorphous semiconductor material (20), each of said portions containing doped silicon regions (12,13,14) forming respective integrated devices of the integrated driving circuitry which are to be electrically isolated from integrated devices obtained in other portions of said at least one first chip portion (11), and at least one second chip portion (10) formed on said second layer (2) of silicon, containing doped silicon regions forming a vertical power device, placed at a different height with respect to said first layer (1), wherein the first layer (3,9) of silicon is absent.

Inventors: RONSISVALLE CESARE, RONSISVALLE, CESARE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L27