Semiconductor integrated circuit with layer for isolating elements in substrate

Abstract: By reverse biasing the PN junction formed around a semiconductor element (10), the semiconductor element (10) is isolated from other elements (10) The PN junction around the semiconductor element (10) is a junction between a layer (26) surrounding the semiconductor element (10) and a layer (28) disposed outside the layer (26). Jointly with the layer constituting the semiconductor (10), the layer (26) surrounding the semiconductor element (10) forms a parasitic diode (54). The potential of the layer (18) on the semiconductor element (10) to be connected to the layer (26) surrounding the semiconductor element (10) is detected, and based on this potential, the voltage to be applied to the parasitic diode (54) is controlled so as to be constant. When the voltage to be applied to the parasitic diode (54) is lower than a threshold, the parasitic diode (54) will be in cutoff status.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: This invention relates to a semiconductor integrated circuit (hereinafter also called "IC"), and more particularly to a concept of reducing the possibility of a parasitic diode in an IC having an element isolating structure. 2. Description of the Related Art: FIG. 5 of the accompanying drawings is a cross-sectional view showing a typical IC. The IC has a PNP bipolar transistor 10 formed in a P substrate 12. In the P substrate 12, an N + implanted layer 16 is formed by, for example, ion implantation. Formed over the N + implanted layer 16 is a P + layer 18 on which an N epitaxial layer 20 is formed. An N + layer 22 and a P layer 24 are formed in the N epitaxial layer 20. The PNP transistor 10 consists of the P + layer 18, the N epitaxial layer 20 and the P layer 24 as the collector layer, base layer and emitter layer, respectively. The N + layer 22 is the base contact layer of the PNP transistor 10. The PNP transistor 10, around which an N epitaxial layer 26 is formed, is contiguous to other elements ( such as transistors and diodes) via a diffusion layer 28. Only parts (N epitaxial layers 30 and 32) of the other elements contiguous to the PNP transistor 10 are illustrated in FIG. 5. The diffusion layer 28 is a so-called element-isolating layer for electrically isolating the PNP transistor 10 from the other elements horizontally in FIG. 5 and may be extensively used in circuit-isolation. In the manufacture of the IC of FIG. 5, the foregoing layers 16 through 32 are formed in the P substrate 12, and then an insulating film 34 is formed in a predetermined pattern on the surface of the P substrate 12. If silicon is used as the substance of the P substrate 12, the insulating film 34 is usually formed by a surface oxidation process. The insulating film 34 to be obtained by the surface oxidation process is a silicon oxide film. Upon forming the silicon oxide film 34, a conductive layer is formed in a predetermined pattern on the top surface of the P substrate 12. The substance of the conductive layer is usually metal. Part of the conductive layer pattern is used as a collector electrode 36, a base electrode 38 or an emitter electrode 40 of the PNP transistor 10. The collector electrode 36, the base electrode 38 and the emitter electrode 40 are formed respectively on the collector layer 18, the base layer 20 via the base contact layer 22, and the emitter layer 24. A collector terminal 42, a base terminal 44 and an emitter terminal 46 are connected to the collector electrode 36, the base electrode 38 and emitter electrode 40, respectively. Part of the conductive layer pattern is used in applying a supply voltage to the N epitaxial layer 26 and connecting the element-isolating layer 28 to ground; that is, a positive d.c. voltage from a battery 50 is applied to the conductive layer 48 formed on the N epitaxial layer 26, and on the other hand, a conductive layer 52 formed on the element-isolating layer 28 is grounded. Therefore the junction between the N epitaxial layer 26 and the element-isolating layer 28 is reverse biased. The N + implanted layer 16 has the same potential as that of the conductive layer 52; therefore the junction between the N+ implanted layer 16 and the P substrate 12 is reverse biased. As a result, a current will stop flowing through these PN junctions; that is, as the result that these PNP junctions become insulate, the PNP transistor 10 will be electrically isolated from the elements contiguous to it. Usually a positive d.c. voltage is also applied to the N epitaxial layer 30, 32. In the case of a double-power-source-driven IC, the reverse biasing may be performed by either the positive power source or the negative power source. Thus the N layer 26 around the PNP transistor 10 is essential to element isolation using the element-isolating layer 28, but the junction between the N epitaxial layer 26 and the collector layer 18 functions as a parasitic diode. FIG. 6 shows a parasitic diode 54 formed by this junction. As shown in FIG. 6, the junction between the N epitaxial layer 26 and the collector layer 18 forms a PN diode (i.e., the parasitic diode 54) connected to the collector of the PNP transistor 10. The parasitic diode 54 functions as an electrostatic capacity between the collector of the PNP transistor 10 and the battery 50. This electrostatic capacity would generally affect the frequency characteristic of the circuit. In fact the junction between the N epitaxial layer 26 and the element-isolating layer 28 also functions as a parasitic diode, but this diode does not contribute to circuit operation; therefore this diode is omitted in FIG. 6 and the following description. "The diode does not contribute to" means that it does not appear on an equivalent circuit showing the connections between the individual elements formed in the P substrate 12. EP-A-0 449 093 discloses a circuital arrangement for preventing latch-up phenomena in vertical pnp transistors with insulated collector which includes a semiconductor element around which a pn junction is formed. Means for reverse biasing the pn junction are provided and a voltage is applied to the parasitic diode which is controlled according to the switching state of the isolated semiconductor element in such a manner that the breakdown voltage of the semiconductor element is not limited due to the breakdown of the parasitic diode. For this reason, an auxiliary transistor is provided which opens when the semiconductor element is in the off state, thereby limiting the reverse voltage applied to the parasitic diode. In US-A-5,051,612, a method for preventing forward biasing of pn junctions in junction isolated devices to prevent parasitic transistor action is disclosed including a biasing element which is connected to the substrate/isolation regions to switch the regions to a low potential. It is an object of this invention to provide a semiconductor integrated circuit which can realize isolation between elements or circuits, without forming a parasitic diode affective to the frequency characteristic of the circuit. The object is solved by the features of claim 1. With the inventive arrangement, the PN junction between the first and second layers is reverse biased and a current flowing through the junction is cutoff. Then, the isolation object element is isolated from other elements. With these arrangements, at least part of the isolation object element is connected to the first layer in a PN junction. The potential change at this part is detected for adjusting the potential of the first layer; that is, when the potential change at the junction is detected, the potential of the first layer is adjusted so as to cancel the detected potential change, thus keeping a constant voltage to be applied to the PN junction between the part and the first layer. Meanwhile the PN junction between the part and the first layer functions as the parasitic diode connected to the isolation object element. Given that the voltage to be applied to the PN junction between the part and the first layer is kept at a constant value, the voltage to be applied to opposite ends of the parasitic diode will become constant. If this voltage is lower than a threshold of the parasitic diode in the reverse direction, the parasitic diode assumes a cutoff status all the time so that its junction capacity will not affect the frequency characteristic of the circuit. This invention may be realized in various kinds of embodiments. For example, the PN junction in connection with the isolation of elements may be reverse biased by a d.c. power source such as a battery. At that time, for keeping the parasitic diode permanently in a cutoff state, the potential to be applied to the parasitic diode from the d.c. power source should be varied in common mode with the detected potential of the first layer. The methods of varying the potential to be applied to the parasitic diode from the d.c. power source can be divided chiefly into the following two: shifting the potential to be outputted from the d.c. power source; and dropping the potential to be outputted from the d.c. power source by any means. The former method may be realized by a circuit structure, for example, in which the potential at one terminal, out of the two terminals of the d.c. power source, opposite to the terminal to be connected with the d.c. power source and the first layer is kept floating, whereupon this floating potential is varied in common mode with the detected potential change. In this case detection of a potential change can be performed by a voltage follower whose gain is +1. The latter method may be realized by a circuit structure, for example, in which a resistor is inserted between the d.c. power source and the first layer, and a voltage drop is caused to occur at the resistor. In this case a current to flow in the resistor must have such a value as to vary in common mode with the value of the detected potential change. The means for varying a current, which is to flow into the resistor, in conformity with the value of the detected potential change is exemplified by an element, such as a transistor, which can adjust the output current value responsive to the input potential. The individual layers constituting the IC of this invention may be formed by the conventional process. For example, the first layer may be formed as an epitaxial layer. The IC may include an implanted layer for isolating the isolation object element from the semiconductor substrate. Further the isolation object element may be a transistor, a diode, a capacitor, etc. The semiconductor substrate may be either a P substrate or an N substrate. If the semiconductor substrate is a P substrate, the first layer should be an N layer, the second layer a P layer, and the part of the isolation object element to be connected to the first layer as a PN junction is a P layer; the reverse biasing means applies to the first layer a potential lower than the potential at the second layer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a circuit structure according to a first embodiment of this invention; FIG. 2 is a circuit diagram showing a circuit structure according to a second embodiment; FIG. 3 is a circuit diagram showing a circuit structure according to a third embodiment; FIG. 4 is a circuit diagram showing a circuit structure according to a fourth embodiment; FIG. 5 is a cross-sectional diagram showing a PNP transistor which is electrically isolated from adjacent elements by reverse biasing the PN junctions around the PNP transistor; and FIG. 6 is a circuit diagram showing a circuit structure in which an N layer connected to an element-isolating P layer forms a parasitic diode between the element-isolating P layer and a collector layer. DETAILED DESCRIPTION Various preferred embodiments of this invention will now be described with reference to the accompanying drawings. Each embodiment is generally similar in element structure and element-isolating structure to the semiconductor integrated circuit of FIG. 5, having a parasitic diode in the form as shown in FIG. 6. In the following description, like reference numerals designate parts or elements similar to those of FIGS. 5 and 6, and equivalent circuit diagrams are used for convenience of comparison with FIG. 6. Repetition of the description in connection with FIGS. 5 and 6 is omitted here for clarity. FIG. 1 shows a partial semiconductor integrated circuit according to a first embodiment of this invention. In this embodiment a battery 50 is used differently from FIG. 5. The battery 50 applies a voltage between the conductive layers 48, 52 to reversely biasing the junction between the element-isolating layer 28 and the N epitaxial layer 26. Like FIG. 5, the potential of the P substrate 12 and the potential of the conductive layer 52 are also grounded. In this embodiment, one end of the battery 50 is floating from the grounded potential, unlike FIG. 6, and is connected to the collector terminal 42 via the voltage follower 56. The voltage follower 56 is a d.c. amplifier whose gain is +1, and which has a function of detecting the potential of the collector terminal 42 and varying the potential at the one end of the battery 50. More specifically, the collector potential of the PNP transistor 10 is detected by the voltage follower 56. Since the gain of the voltage follower 56 is +1, the output potential of the voltage follower will vary in response to the potential change of the collector of the PNP transistor 10. The output terminal of the voltage follower 56 is connected to the one end of the battery 50. In this embodiment, since the connecting point between the voltage follower 56 and the battery 50 is a negative terminal of the battery 50, the potential at a positive terminal of the battery 50 varies in common mode with the collector potential of the PNP transistor 10. "Common mode" means a state in which when the collector potential of the PNP transistor 10 rises, the potential at the positive terminal of the battery 50 will rise similarly, and when the collector potential of the PNP transistor 10 is lowered, the potential at of the positive terminal of the battery 50 will be lowered similarly. The positive terminal of the battery 50 is connected to the N epitaxial layer 26 via the conductive layer 48 as shown in FIG. 5 so that the potential at the positive terminal of the battery 50 will be applied to the N epitaxial layer 26. Since the N expitaxial layer 26 is a cathode of the parasitic diode 54 resulting from the junction between the N epitaxial layer 26 and the collector layer 18, the voltage to be applied to the parasitic diode 54 will be a potential difference between the collector of the PNP transistor 10 and the positive terminal of the battery 50. The potential at the positive terminal of the battery 50 varies in common mode with the collector potential of the PNP transistor 10 so that the voltage to be applied to the parasitic diode 54 will be constant. If this voltage is lower than a reverse threshold voltage of the parasitic diode 54, the parasitic diode 54 will be permanently in a cutoff state so that no current will flow through the parasitic diode 54. In this status, the parasitic diode 54 will not affect the circuit operation at all and hence the frequency characteristic of the circuit is also unaffected. Thus according to this embodiment, since the collector potential of the PNP transistor 10 is detected to vary the cathode potential of the parasitic diode 54 in common mode with the detected collector potential, it is possible to keep the voltage, which is to be applied to the parasitic diode 54, at a constant value. Assuming that the voltage to be applied to the parasitic diode 54 is lower than a threshold voltage, it is possible to keep the parasitic diode 54 in a cutoff state, thus guaranteeing the frequency characteristic of the circuit as designed. FIG. 2 shows a partial semiconductor integrated circuit according to a second embodiment. In this embodiment, the potential at the negative terminal of the battery 51 is not floating but is fixed to the ground. The positive-terminal of the battery 51 is connected to the conductive layer 48 via a resistor 58 so that the potential of the cathode (N epitaxial layer 26) of the parasitic diode 54 will correspond to a dropped potential across the resistor 58 from the potential of the positive terminal of battery 51. The resistor 58 may be either a diffusion resistor obtained by diffusing impurities into the P substrate 12 or a resistor formed from polycrystalline silicon. In this embodiment, another PNP transistor 60 is used in addition to the PNP transistor 10. The PNP transistor 60 may be either formed, likewise the PNP transistor 10, in the P substrate 12 or formed as a parasitic transistor in the P substrate 12. The base of the PNP transistor 60 is connected to the collector of the PNP transistor 10. Since the collector of the PNP transistor 10 has the conductive layer 42 as an electrode, this connection is realized as the connection between the conductive layer 42 and the base electrode of the PNP transistor 60. The base electrode of the PNP transistor 60 may be formed in the same method as the base electrode 44 of the PNP transistor 10. The emitter of the PNP transistor 60 is connected to one end of the resistor 58. Specifically, the emitter electrode of the PNP transistor 60 is connected to the conductive layer 48 and may be formed in the same method as the emitter electrode 46 of the PNP transistor 10. Further the collector of the PNP transistor 60 is grounded; specifically the collector electrode of the PNP transistor 60 is connected to the conductor layer 52 and may be formed in the same method as the collector electrode 42 of the PNP transistor 52. This embodiment can give the same results as the first embodiment. For example, when the collector potential of the PNP transistor 10 is lowered, the current flowing between the emitter and collector of the PNP transistor 60 is increased. The voltage drop due to the resistor 58 will thereby be increased so that the cathode potential of the parasitic diode 54 will be lowered by the amount of the voltage drop due to the resistor 58. Therefore the voltage to be applied to the opposite ends of the parasitic diode 54 will not vary, irrespective of the lowering of the collector potential of the PNP transistor 10. FIG. 3 shows a partial semiconductor integrated circuit according to a third embodiment. In this embodiment, the object element to be isolated from adjacent elements is a capacitor 62 rather than the PNP transistor 10. For forming the capacitor 62, an element-isolating structure is formed in the same method as the case shown in FIG. 5, and then a dielectric layer is formed on the surface of the element-isolating structure by the known method such as surface nitrization. One electrode of the capacitor 62 is a P layer, and the epitaxial layer to which the positive potential from the battery 51 is to be applied makes a PN junction with this P layer. Therefore as represented in an equivalent circuit, the parasitic diode 54 will be formed between the one electrode of the capacitor 62 and the positive terminal of the battery 51. This invention can be adopted also in this case if an emitter follower having the PNP transistor 60 and the resistor 58 is provided between the parasitic diode 54 and the battery 51, likewise in the second embodiment. FIG. 4 shows a partial semiconductor integrated circuit according to a fourth embodiment. In this embodiment, the object element to be isolated from adjacent elements is a diode 64 rather than the PNP transistor 10. The anode of the diode 64 is a P layer, and the epitaxial layer to which the positive potential from the battery 51 is to be applied makes a PN junction with this P layer. Therefore as represented in an equivalent circuit, a parasitic diode 54 is formed between the anode of the diode 64 and the positive terminal of the battery 51. This invention can be adopted also in this case if an emitter follower having the PNP transistor 60 and the resistor 58 is provided between the parasitic diode 54 and the battery 51, likewise in the second embodiment. The object element to be isolated may be an NPN transistor. As mentioned above, according to this invention, since the voltage to be applied to the parasitic diode is kept constant so that the parasitic diode will assume a cutoff state permanently, it is possible to prevent the diode from affecting the frequency characteristic of the circuit.

Claims: Electronic circuit comprising; a semiconductor element (10, 62, 64) around which a PN junction is formed in a semiconductor substrate; means (50) for reverse biasing the PN junction around said semiconductor element (10, 62, 64) to isolate said semiconductor element from other elements; and means (56, 58, 60) for keeping a parasitic diode (54), which is adapted to be located between a first layer (26) around said semiconductor element (10, 62, 64), thereby constituting a PN junction and a second layer (18) constituting said semiconductor element (10), permanently in cutoff state, a third layer (28) arranged so as to be connected to said first layer (26) to form a PN junction; characterized by said means (50, 51) for reverse biasing being effective on the PN junction of said first and third layers (26, 28); means (56, 60) for detecting a potential change at the PN junction between said semiconductor element (10, 62, 64) and said first layer (26); and means (56, 58, 60) for adjusting the potential of said first layer (26) so as to cancel said detected potential change; said means (56, 60) for detecting a potential change and said means (56, 58,60) for adjusting the potential being connected to the parasitic diode (54) and forming said cutoff state keeping means (56, 58, 60) being operable to keep a voltage, which is applied across said parasitic diode (54), at constant value less than a threshold of said parasitic diode (54). Electronic circuit according to claim 1, characterized by a semiconductor substrate (12), said semiconductor element (10, 62, 64) being formed in said semiconductor substrate (12) and adapted to be isolated from other elements formed in said semiconductor substrate (12); and said first layer (26) and third layer (28) also being formed in said semiconductor substrate (12). Electronic circuit according to claim 1 or 2, characterized in that said reverse biasing means is a dc power source (50) connected at one end to said first layer (26), said potential adjusting means (56) being operable for increasing or decreasing the potential at the other end of said dc power source (50) with an increase or decrease of said detected potential change. Electronic circuit according to claim 3, characterizing in that said potential change detecting means includes a voltage follower (56) with a gain of +1 connected to the PN junction of said semiconductor element (10, 62, 64) with said first layer (26). Electronic circuit according to claim 1 or 2, characterized in that said reverse biasing means is a dc power source (51) connected between said first and third layers (26, 28), said potential adjusting means is a resistor (58) located between said dc power source (51) and said first layer (26) for causing a voltage drop according to the detected potential change. Electronic circuit according to claim 5, characterized in that said potential change detecting means includes an element (60) whose output current may vary according to the potential at the junction of said semiconductor element (10, 62, 64) and said first layer (26). Electronic circuit according to any of claims 1 to 6, characterized in that said first layer (26) is an epitaxial layer formed in said semiconductor substrate (12). Electronic circuit according to any of claims 1 to 7, characterized by an implanted layer (16) for isolating said semiconductor element (10, 62, 64) from said semiconductor substrate (12). Electronic circuit according to any of claims 1 to 8, characterized in that said semiconductor element is any of a transistor (10), a diode (62) and a capacitor (64). Electronic circuit according to any of claims 1 to 9, characterized in that said semiconductor substrate (12) is a P substrate, said first layer (26) is an N layer, said third layer (28) is a P layer, a PN junction is formed between a P layer of said semiconductor element (10, 62, 64) and said first layer (26), and said reverse biasing means (50, 51) being operable to apply to said first layer (26) a lower potential than that applied to said third layer (28).

Inventors: FUJII NOBUO, MITSUHASHI YASUO, MIZUKAWA YOSUKE, FUJII, NOBUO, MITSUHASHI, YASUO, MIZUKAWA, YOSUKE, MITSUHASHI, YASUO, C/O MITSUBISHI DENKI ENG. K.K., MIZUKAWA, YOSUKE, C/O MITSUBISHI DENKI ENG. K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: H01L27
IPC codes: H01L27