Data recording method and data recording apparatus

Abstract: A method of recording data in a recording medium is performed by using an RLL (Run Length Limited) Code represented by (d,k,m,n) = (1,7,2,3). A one-byte resync signal with a pattern represented by "X01000000001" is periodically inserted into the data, X being an indeterminate bit which is determined by the data. Then, the data into which the resync signal is inserted is recorded on the recording medium. A method of recording data in a recording medium in accordance with NRZI (Non Return to Zero Inverted) recording is performed by using an RLL code represented by (d,k,m,n) = (1,7,2,3). One of one-byte resync signals represented by patterns "X01000000001" and "X01000000101" is selected such that a DSV (Digital Sum Value) of a coded signal is decreased, X being an indeterminate bit which is determined by the data. The selected resync signal is periodically inserted into the data. Then, the data into which the resync signal is inserted is recorded on the recording medium.

Description: The present invention relates to a data recording method and a data recording apparatus for coding data by using a so-called (1,7) code and recording the data into a recording medium. Fig. 1 shows a coding table of the most common (1,7) code. In this code, (d,k,m,n) = (1,7,2,3), i.e., the number of "0"s present between "1"s is a minimum of one and a maximum of seven, and the conversion bit ratio is 2 : 3. In this table, X represents an indeterminate bit which is determined by the pattern before this bit. Fig. 2 illustrates a sector format proposed as a standard of a rewritable 300-mm optical disk, as an example of a sector format using this (1,7) code. Referring to Fig. 2, a 67-byte portion as a header field is an area in which address information is already recorded on a disk, and a 1,293-byte portion as a recording field is an area in which new information is recorded. Fig. 3 explains in detail a 3-byte DS portion and a 1,249-byte data field portion in that area. The data field shown in Fig. 3 contains a data sync pattern SB1-3 which indicates the start position of data, user data D1 to D1024, address data A1 and A2, CRC parities (error-detecting codes) C1 to C4, ECC parities (error-correcting codes) E1,1 to E10,14, and resync (resynchronization) patterns RS1 to RS59. These patterns, data, and parities are coded and recorded by the (1,7) code described above. The purpose of the resync pattern is to record a predetermined pattern at a fixed period. That is, if a large omission of data takes place in a reproduction signal during reproduction, this shifts the phase of a reproduction phase locked loop (PLL) clock, making byte synchronization of reproduction information impossible. Even if this synchronization difference propagates, it is possible to perform resynchronization by detecting the resync pattern and thereby minimize the damage. The one-byte resync pattern proposed in this standard is a pattern "X01000001000" which is obtained by converting "C5" into the (1,7) code in hexadecimal notation. It is desirable that the resync pattern be a pattern which does not appear in user data. If the same pattern as the resync pattern appears in user data, a resync pattern detection circuit erroneously detects the resync pattern, producing a large error in reproduction data. To prevent this, windows for detecting the resync pattern can be provided in intervals before and after a point at which the resync pattern is expected to be detected, thereby making it impossible to detect the resync pattern in a data area. Fig. 4 is a timing chart for explaining the function of such a resync detection window. Referring to Fig. 4, RS represents a true resync signal, UD represents user data, WS represents a false resync signal in the user data, and T represents a fixed time. Assume that the window is narrowed so as not to erroneously detect the false resync pattern in the user data area. In this case, if an omission of data occurs in a reproduction signal, the resync pattern may fall outside the window due to an error in the frequency of the reproduction signal and therefore may no longer be detected. If, in contrast, the window is widened so as not to miss the true resync pattern, the false resync pattern in the user data area may be erroneously detected. For this reason, the standard of a rewritable optical disk using a (2,7) code, for example, makes use of a pattern, which satisfies a (2,7) limitation, i.e., "0010000000100100," and does not appear in a data area written by the (2,7) code, as the resync pattern. The above-mentioned resync pattern of the (1,7) code, however, is a pattern that appears in the user data area. A pattern indicated by "1000000010000001," therefore, which satisfies the dk limitation of (1,7) is used. Such a pattern in which an 8-t period is followed by a 7-t period meets the condition (d,k) = (1,7) and does not appear in the (1,7)-code coding table mentioned earlier. The use of this pattern as the resync pattern can solve the above problem. If, however, this pattern is used, the resync pattern consists of at least two bytes. In Fig. 3, a resync pattern of one byte is added every 20 bytes of user data. The efficiency of recording capacity decreases if a resync pattern of two bytes must be added every 20 bytes of user data. Another problem on which the present invention has focused attention is a problem of DC free of a coded signal. Assuming that symbol 1 is +1 point and symbol 0 is -1 point in a recording waveform column, the sum of points in a given waveform column is termed a digital sum value (DSV). A code in which a DSV in a certain predetermined interval is 0 or has a finite value does not have a DC component in its waveform column and hence is called a DC free code. When this DC free code is used, a binary circuit of a reproducing apparatus can be simplified because no DC component is contained in a reproduction signal. This effectively reduces jitters produced by binary errors. Examples of the DC free code are PE modulation, FM modulation, a Miller 2 (Miller square) code, and an EFM code. These codes, however, have their respective drawbacks, such as a low recording density, a small window margin, and complexity in a coding circuit. On the other hand, it is also possible to perform mark-edge recording for a run length limited (RLL) code, such as the (1,7) code or the (2,7) code, which is often used in mark-position recording, for the purpose of increasing the recording density. That is, as shown in Fig. 5, it is possible to convert the RLL code into a non return to zero inverted (NRZI) code, thereby using it as a (1,7) NRZI code or a (2,7) NRZI code. There is conventionally known method for converting these non DC free codes into DC free codes by providing a DC free control bit at a predetermined period. That is, by properly selecting the DC free control bit provided at the fixed period, a DSV value as a whole can be so controlled as not to be greater than a predetermined value. It is known from EP-A-0420179 to insert a resync signal in the form of a pattern which does not exist in the conversion rule of the RLL code. The invention is specified in the appended claims. The preamble of claims 1, 2, 6, 7, 11, 12 is based on EP-A-0 420 179. According to one aspect of the pesent invention there is disclosed a method of recording data in a recording medium in accordance with NRZI (Non Return to Zero inverted) recording by using an RLL code represented by (d,k,m,n) = (1,7,2,3), comprising the steps of: periodically inserting a resync signal into the data; and recording the data into which the resync signal is inserted into said recording medium; characterised in that the resync signal is obtained by selecting one of resync signals represented by patterns "X01000000001" and "X01000000101", assuming that X is an indeterminate bit which is determined by the data, such that a DSV (Digital Sum Value) of a coded signal is decreased. According to a further aspect of the present invention there is disclosed a method of recording data in a recording medium in accordance with NRZI (Non Return to Zero Inverted) recording by using an RLL code represented by (d,k,m,n) = (1,7,2,3), comprising the steps of: periodically inserting the selected resync signal into the data; and recording the data into which the resync signal is inserted into said recording medium; characterised in that the resync signal is obtained by selecting one of resync signals represented by patterns "X01000000001" and "X01010000001", assuming that X is an indeterminate bit which is determined by the data, such that a DSV (Digital Sum Value) of a coded signal is decreased. Fig.1 is a view showing a coding table for a (1,7) code; Fig. 2 is a view showing an example of a sector format; Fig. 3 is a view showing the arrangement of a data field in the sector format shown in Fig. 2; Fig. 4 is a timing chart for explaining the function of a resync detection window; Fig. 5 is a timing chart for explaining NRZI recording using the (1,7) code; Fig. 6 is a block diagram showing an embodiment of a resync signal generation unit of a data recording apparatus according to the present invention; Fig. 7 is a timing chart for explaining how to obtain a digital sum value; Fig. 8 is a view for explaining the function of a DSV determination circuit shown in Fig. 6; Fig. 9 is a view showing an output table for explaining an output from the DSV determination circuit shown in Fig. 6; Fig. 10 is a circuit diagram showing an example of the arrangement of a resync signal detection circuit in a reproducing apparatus; Fig. 11 is a circuit diagram showing an example of the arrangement of a bit control circuit shown in Fig. 6; and Fig. 12 is a block diagram showing another embodiment of the resync signal generation unit of the data recording apparatus according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 6 is a block diagram showing one embodiment of a resync signal generation unit of a data recording apparatus according to the present invention. Referring to Fig. 6, this resync signal generation unit includes a resync byte inserting circuit 1, a (1,7) encoder 2, an NRZI coding circuit 3, a delay circuit 4, a resync 10th bit control circuit 5, and a DSV determination circuit 6. In Fig. 6, a resync signal at a point A is "11001011," resync signals at points B and C are "X01000000101," and a resync signal at a point D is "X01000000101" or "X01000000001." Input recording data shown in Fig. 6 is data illustrated in a portion inside double lines in Fig. 3, i.e., data added with error-correcting codes and error-detecting codes. The resync byte inserting circuit 1 adds a portion from RS1 to RS59 shown in Fig. 3. According to the present invention, hexadecimal data corresponding to a resync byte is "CB," and this one-byte data "CB" is inserted every 20 bytes-of input data. The (1,7) encoder 2 performs (1,7) coding for recording data in accordance with the rule determined in Fig. 1. The resulting output resync signal has a pattern "X01000000101." The output from the encoder 2 is converted into an NRZI signal by the NRZI coding circuit 3. That is, the output from the encoder is converted into a signal in which the polarity is inverted at a portion of "1" and remains unchanged at a portion of "0." The DSV determination circuit 6 counts the DSV of the NRZI waveform column. As shown in Fig. 7, assuming that an interval corresponding to "1" of the NRZI signal is +1 point and an interval corresponding to "0" of the signal is -1 point, this count is obtained by calculating the sum total of these points. Of one byte of the resync signal, i.e., of 12 channel bits of the signal, the 10th bit is used as a DC free control bit. Assume that a DSV from a recording start point to a given DC free control bit Z n is DSV 0→n , and that a DSV in an interval from Z n to n+1 is DSV n+1 . If DSV 0→n = 5 and DSV n+1 = 3 for Z n , as shown in Fig. 8, the total DSV is increased if the two DSVs are connected directly since both the DSVs are positive. In this case, therefore, it is preferable to invert the polarity at the bit Z n to obtain -3 as DSV n+1 . For this reason, the polarity is inverted by setting "1" as Z n . For Z n+1 , it is assumed that DSV 0→n+1 = 2 and DSV n+2 = -4. In this case, the polarity of DSV n+2 is preferably not inverted, so Z n+1 = "0" is set. The DSV determination circuit 6 performs these determinations. Fig. 9 shows an I/O table of the DSV determination circuit 6. If the polarities of DSV o→n and DSV n+1 are the same, the DSV determination circuit 6 outputs Z n = "1"; if these polarities are different, the DSV determination circuit 6 outputs Z n = "0." The delay circuit 4 is necessary to cause a modulation signal to wait until the DSV determination circuit 6 outputs the determination result. The delay circuit 4 delays an input signal by a predetermined time by using a FIFO memory or the like and outputs the delayed signal. The resync 10th bit control circuit 5 is arranged, for example, as shown in Fig. 11. Referring to Fig. 11, this bit control circuit includes a resync 10th bit timing generating circuit 12, flip-flop circuits 13 and 14, and an exclusive-OR gate 15. The bit control circuit 5 performs control such that, when the output from the DSV determination circuit 6 is "1," the polarity is inverted at the timing of the 10th bit of a resync signal; when the output from the DSV determination circuit 6 is "0," the polarity is not inverted. When a resync pattern is recorded by using the above means, this resync signal can be recorded as a DC free signal since the maximum value of the sum total of DSVs of a waveform column to be recorded does not exceed the maximum value of DSV in one block. Fig. 10 illustrates an example of the arrangement of a resync pattern detection circuit in a reproducing apparatus. Referring to Fig. 10, this detection circuit includes AND gates 7, 8, and 9, a NOR gate 10, and a 12-bit shift register 11. The resync pattern detection circuit with the above arrangement performs pattern matching for an input reproduction signal to the shift register 11. Since the 10th bit of this shift register does not take part in this pattern matching, it is possible to detect a pattern of either "X01000000001" or "X01000000101." In addition, in order to prevent detection of a false resync pattern in a user data area, a resync pattern detection window is opened only in the vicinity of a portion where a resync pattern is expected to be detected. Consequently, the AND gate 7 can extract only a true resync pattern. In mark-position recording or in mark-edge recording requiring no DC free recording, the resync pattern need only be one type, "X01000000001." In this case, the resync signal generation unit is constituted as shown in Fig. 12. Referring to Fig. 12, a resync 10th bit conversion circuit 16 for converting the 10th bit of a resync signal from "1" to "0" is provided in place of the delay circuit 4, the bit control circuit 5, and the DSV determination circuit 6 shown in Fig. 6. That is, this embodiment makes it unnecessary to use the means for inverting the polarity in a resync portion such as in the embodiment shown in Fig. 6. Instead, after (1,7) coding is performed by inserting a resync byte "CB"hex, it is required to replace "1," the 10th bit of the resync, with "0." Since this resync pattern does not appear in the (1,7) code, it advantageously decreases the possibility of erroneous detection of the resync pattern in a data area. It will be understood from the above description that the following patterns also can be used as other embodiments. That is, as the resync pattern to be used in combination with "X01000000001," five patterns of (b) "X01010000001" (c) "X01001000001" (d) "X01000100001" (e) "X01000010001" (f) "X01000001001" can be used instead of (a) "X01000000101" mentioned earlier. Although any of the above patterns can achieve the object of the present invention, a comparison of these patterns will be made below. The pattern (b) has performance as a resync pattern equivalent to that of the pattern (a). That is, when the width of a detection window is set at ±6 channel bits in the resync detection circuit, as shown in Fig. 10, no resync pattern erroneous detection occurs even if one channel bit error takes place. When the pattern (c) or (f) is to be used, the width of a detection window must be set at ±5 channel bits in order that no resync pattern erroneous detection takes place even if one channel bit error occurs. When the pattern (d) or (e) is to be used, the width of a detection window must be set at ±4 channel bits under the same conditions. As described above, when the width of a resync detection window is narrowed, a detection omission becomes more likely to occur with respect to variations in reproducing rate. When this fact is taken into consideration, the use of the pattern (a) or (b) is desirable. As has been described above, according to the data recording method and the data recording apparatus of the present invention, a resync pattern of one byte can be set in the (1,7) code, and this improves the efficiency of recording density compared to a two-byte resync pattern. In addition, since recording can be performed in a DC free waveform column, a reproducing apparatus can be designed easily, and jitters upon binarization are also reduced. Furthermore, when a pattern "X01000001000" of the conventional example, which is obtained by performing (1,7) coding for hexadecimal "C5" is detected by using the resync pattern detection circuit, as shown in Fig. 10, one channel bit error may result in erroneous detection of a false resync signal if a detection window is set at ±6 channel bits. In the present invention, however, even if the detection window is set at ±6 channel bits, erroneous detection of a false resync signal is never caused by one channel bit error. As described above, the data recording method and the data recording apparatus of the present invention can perform recording and reproduction with a higher reliability.

Claims: A method of recording data in a recording medium in accordance with NRZI (Non Return to Zero inverted) recording by using an RLL code represented by (d,k,m,n) = (1,7,2,3), comprising the steps of: periodically inserting a resync signal into the data; and recording the data into which the resync signal is inserted into said recording medium; characterised in that the resync signal is obtained by selecting one of resync signals represented by patterns "X01000000001" and "X01000000101", assuming that X is an indeterminate bit which is determined by the data, such that a DSV (Digital Sum Value) of a coded signal is decreased. A method of recording data in a recording medium in accordance with NRZI (Non Return to Zero Inverted) recording by using an RLL code represented by (d,k,m,n) = (1,7,2,3), comprising the steps of: periodically inserting the selected resync signal into the data; and recording the data into which the resync signal is inserted into said recording medium; characterised in that the resync signal is obtained by selecting one of resync signals represented by patterns "X01000000001", and "X01010000001", assuming that X is an indeterminate bit which is determined by the data, such that a DSV (Digital Sum Value) of a coded signal is decreased. A method as claimed in any preceding claim comprising the steps of; inserting a first resync signal into an input signal representative of data to be recorded; encoding the input signal including the first resync signal using an RLL encoding method followed by a NRZI encoding method to form an encoded signal; determining the DSV (Digital Sum Value) of the encoded signal in which the first resync signal is encoded to form a second resync signal; and modifying the second resync signal corresponding to the encoded first resync signal to correspond to the selected resync signal. A method as claimed in claim 3 wherein the first resync signal is 11001011. A method as claimed in any of claims 3 and 4 including the step of delaying the encoded signal before the step of modifying the second resync signal. An apparatus for recording data in a recording medium in accordance with NRZI (Non Return to Zero Inverted) recording by using an RLL code represented by (d,k,m,n) = (1,7,2,3), comprising: means (1,5,6) for periodically inserting a resync signal into the data; and means for recording the data into which the resync signal is inserted into said recording medium; characterised by further comprising means (5,6) for selecting said resync signal to be one of resync signals represented by patterns "X01000000001" and "X01000000101", assuming that X is an indeterminate bit which is determined by the data, such that a DSV (Digital Sum Value) of a coded signal is decreased,. An apparatus for recording data in a recording medium in accordance with NRZI (Non Return to Zero Inverted) recording by using an RLL code represented by (d,k,m,n) =(1,7,2,3), comprising: means (1,5,6) for periodically inserting the selected resync signal into the data; and means for recording the data into which the resync signal is inserted into said recording medium; characterised by further comprising means (5,6) for selecting said resync signal to be one of resync signals represented by patterns "X01000000001" and "X01010000001", assuming that X is an indeterminate bit which is determined by the data, such that a DSV (Digital Sum Value) of a coded signal is decreased. Apparatus as claimed in any of claims 6 and 7 comprising; inserting means (1) operable to insert a first resync signal into an input signal representative of data to be recorded; encoding means (2) operable to encode the input signal including the first resync signal using an RLL encoding method followed by a NRZI encoding method to form an encoded signal in which the first resync signal is encoded to form a second resync signal; determining means (6) operable to determine the DSV (Digital Sum Value) of the encoded signal; and modifying means (5) operable to modify the second resync signal corresponding to the encoded first resync signal to correspond to the selected resync signal. Apparatus as claimed in claim 8 wherein the first resync signal is 11001011. Apparatus as claimed in any of claims 8 and 9 delaying means (4) operable to delay the encoded signal before the second resync signal is modified. An apparatus for reproducing data recorded on a recording medium in accordance with NRZI (Non Return to Zero inverted) by using an RLL code represented by (d,k,m,n) = (1,7,2,3), comprising; a resync pattern detection circuit having pattern matching means; characterised in that the pattern matching means is operable to detect a resync pattern of either X01000000001 or X01000000101, where X is an indeterminate bit which is determined by the data. An apparatus for reproducing data recorded on a recording medium in accordance with NRZI (Non Return to Zero inverted) by using an RLL code represented by (d,k,m,n) = (1,7,2,3), comprising; a resync pattern detection circuit having pattern matching means; characterised in that the pattern matching means is operable to detect a resync pattern of either X01000000001 or X0101000001, where X is an indeterminate bit which is determined by the data.

Inventors: SATOMURA SEIICHIRO, SATOMURA, SEIICHIRO, SATOMURA, SEIICHIRO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: G11B20
IPC codes: G11B20, G11B27, H03M7, H03M5