Bus monitor circuit for switching system and method of monitoring

Abstract: In a switching system, a data bus which interconnects circuit modules, a switching network module and a control module for transporting packets between the interconnected modules. A bus interface ( 16 ) is connected to the data bus ( 13 ) for receiving a copy of every packet on the data bus. An error detector ( 18 ) determines whether the received packet contains an error, and produces an error detect signal and an error check result if the received packet is determined as having an error. In response to the error detect signal, the received packet, the error check result and time-of-day data are stored into a register ( 19 ) and transferred to one of the storage locations of a memory ( 20 ) to keep a list of error records. A maintenance station ( 22 ) reads stored error records from the memory for identifying the source of errors.

Description: The present invention relates generally to a bus monitor circuit for a switching system, and to a method of monitoring a packet on the data bus of a switching system. The invention also relates to a switching system including the bus monitor circuit, and more specifically to a maintenance system for keeping error records of a switching system. In conventional switching systems, functional modules are interconnected by a data bus and packets are transported between the modules over the data bus. When an abnormal condition occurs in the system, a logic analyzer is brought into the system and hand-wired to the data bus for monitoring the packets transported along the bus. However, the use of the logic analyzer requires a special team of experts. Additionally, the logic analyzer is not provided with a sufficient amount of memory for storing records to be analyzed to allow identification of the fault. IBM Technical Disclosure Bulletin, Vol. 34, No. 2, July 1991, New York, USA, XP210584, 'High-Speed Network Adapter Error Trace Mechanism', describes a method and hardware for finding causes of data link framing errors when data is received over a high-speed link. A T1 communications adapter, consisting of two digital signal processors using common memory and protocol assist logic, is utilized. Incoming T1 bytes are stored raw in a circular trace buffer, and are also stored in a host buffer after being processed by protocol assist hardware. Both buffers are frozen after an error condition is detected, and a RAM dump is initiated. R.J. Prufer, 'Network Advisor Protocol Analysis: Decodes', in Hewlett-Packard Journal, Vol. 43, No. 5, October 1992, Palo Alto, USA, pages 34-40, XP349772 describes a protocol analyzer which uses the receive time of a packet in an internet protocol context. The present invention therefore seeks to provide a bus monitor circuit for monitoring packets on the data bus of a switching system and keeping error records for maintenance purposes. According to the present invention, there is provided a bus monitor circuit for a switching system comprising a plurality of circuit modules, a switching network module, a control module for controlling said circuit modules and said switching module, and a data bus interconnecting said circuit modules, said switching network module and said control module for transporting a packet between the intercon-nected modules, the bus monitor circuit comprising: time-keeping-means for generating time-of-day data; means connected to said data bus for receiving a copy of the packet therefrom; means for determining whether the received copy of said packet contains an error, and producing an error detect signal and an error check result if the copy of the packet is determined as having an error; a memory having a plurality of storage locations for storing the copy of the packet, the error check result and the time-of-day data into one of the storage locations in response to said error detect signal; and a maintenance station for reading stored contents of said memory. The invention also provides a method of monitoring a packet on the data bus of a switching system, said switching system comprising a plurality of circuit modules, a switching network module, a control module for controlling said circuit modules and said switching module, and a data bus interconnecting said circuit modules, said switching network module and said control module for transporting a packet between the interconnected modules, the method comprising: generating time-of-day data; receiving a copy of the packet from the data bus; determining whether the received copy of said packet contains an error, and producing an error detects signal and an error check result if the copy of the packet is determined as having an error; storing in memory the copy of the packet, the error check result and the time-of-day data in response to said error detect signal; and reading stored contents of said memory. The present invention will be described in further detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows in block form a switching system embodying a bus monitor of the present invention; and, Figure 2 shows the structure of signals transported on the data bus of Figure 1. Referring now to Figure 1, there is shown a switching system according to a preferred embodiment of the present invention. The switching system, inter-office trunks or transmission lines are terminated at a trunk circuit module 11 which controls the inter-office trunks in response to a command signal from a control module 10. Subscriber lines are terminated at a line circuit module 12 which controls the subscriber lines in response to a command signal from the control module 10. Both of circuit modules 11 and 12 are connected to a data bus 13 to transfer data and speech signals to a switching network module 14 where these signals are switched between lines and trunks by way of the data bus under control of the control module 10 in a manner known in the art. The control module 10 further provides an overall control of the system including maintenance and administrative tasks of the system. As shown in Figure 2, the signal transported on the data bus 13 comprises a data signal 30 and a delimiter 31 which indicates the effective area of the data signal. The data signal is transmitted in packet format which begins with a destination address field (DA) followed by a source address field (SA), a data length field (LEN), a data field (DATA) and a frame check sequence field (FCS) for detecting error bits. According to the preferred embodiment of the present invention, a bus monitor 15 is provided which comprises a bus interface 16 connected to the data bus 13 for receiving every packet transported on the data bus using a delimiter 31 as a gate pulse and supplying the DA, SA, LEN and DATA fields of a copy of the received packet to a register 19 and the FCS field of the packet to a known FCS check circuit 18 as illustrated. A calendar and time-of-day clock source 17 is provided for generating date and time-of-day data. If an error is detected as a result of an FCS check, the FCS check circuit 18 produces an error detect signal and applies it to the register 19 as an enable pulse to store the DA, SA, LEN and DATA fields of the copy of the packet to corresponding storage areas of register 19 and the result of the FCS check into a result area "R" of the register. At the same time, the date and time-of-day data are supplied to a "DATE & TIME" area of the register. When register 19 is filled, all the stored error-containing data are transferred from the register to a memory 20 as a first error record. When a subsequent packet is received from the data bus, a similar process is repeated and stored into the memory 20 with an FCS check result and date and time-of-day data as a second error record if the subsequent packet is determined as containing an error. If no error is detected by the FCS check circuit 18, no record is stored in memory 20 . As the process continues, the memory 20 will be filled with a plurality of error records as system diagnostic data. At an appropriate time, all the stored error records are read from the memory 20 by way of an interface 21 into a maintenance station or video display terminal 22 to provide a display of a list of error records on a video screen. The displayed error records may be analyzed by maintenance personnel to locate the source of the trouble. In summary, the preferred embodiment of switching system according to the present invention includes a data bus which interconnects circuit modules, a switching network module and a control module for transporting packets between the interconnected modules. A bus interface is connected to the data bus for receiving a copy of every packet on the data bus. An error detector determines whether the received packet contains an error, and produces an error detect signal and an error check result if the received packet is determined as having an error. In response to the error detect signal, the received packet, the error check result and time-of-day data are stored into a register and transferred to one of the storage locations of a memory to keep a list of error records. A maintenance station reads stored error records from the memory for identifying the source of errors. It will be understood that the present invention has been described above purely by way of example, and modifications of detail can be made within the scope of the invention.

Claims: A bus monitor circuit (15) for a switching system comprising a plurality of circuit modules (11, 12), a switching network module (14), a control module (10) for controlling said circuit modules and said switching module, and a data bus (13) interconnecting said circuit modules, said switching network module and said control module for transporting a packet between the intercon-nected modules, the bus monitor circuit (15) comprising: time-keeping means (17) for generating time-of-day data; means (16) connected to said data bus for receiving a copy of the packet therefrom; means (18) for determining whether the received copy of said packet contains an error, and producing an error detect signal and an error check result if the copy of the packet is determined as having an error; a memory (20) having a plurality of storage locations for storing the copy of the packet, the error check result and the time-of-day data into one of the storage locations in response to said error detect signal; and a maintenance station (22) for reading stored contents of said memory. A bus monitor circuit according to claim 1, wherein the receiving means (16) is adapted to receive a copy of a subsequent packet from the data bus; the determining means (18) is adapted to determine whether the received copy of said subsequent packet contains an error, and producing a further error detect signal and a further error check result if the copy of the subsequent packet is determined as having an error; and the memory (20) is adapted to store the copy of the subsequent packet, the further error check result and further time-of-day data into one of the storage locations in response to said further error detect signal. A bus monitor circuit as claimed in claim 1 or claim 2, wherein said packet comprises a destination address, a source address, a data field and a frame check sequence FCS, and wherein the means (16) connected to said data bus for receiving a copy of the packet therefrom comprises an interface; and the determining means (18) includes an FCS check means for receiving the frame check sequence of the copy of said packet and determining whether the packet contains an error, and producing an error detect signal and an error check result if said packet is determined as having an error; and wherein the bus monitor circuit includes register means for storing the destination address, the source address and the data field of the copy of the packet, said error check result and the time-of-day data to produce an error record A bus monitor circuit as claimed in any preceding claim, wherein the time-keeping means (17) further generates a calendar date signal which is stored into said storage location of the memory (20) in response to said error detect signal. A method of monitoring a packet on a data bus (13) of a switching system, said switching system comprising a plurality of circuit modules (11,12), a switching network module (14), a control module (10) for controlling said circuit modules and said switching module, and a data bus (13) interconnecting said circuit modules, said switching network module and said control module for transporting a packet between the interconnected modules, the method comprising: generating time-of-day data; receiving a copy of the packet from the data bus (13) ; determining whether the received copy of said packet contains an error, and producing an error detect signal and an error check result if the copy of the packet is determined as having an error; storing in memory (20) the copy of the packet, the error check result and the time-of-day data in response to said error detect signal; and reading stored contents of said memory. A method according to claim 5, wherein said packet comprises a destination address, a source address, a data field and a frame check sequence, the method comprising; receiving the frame check sequence of the copy of said packet; storing in a register means the destination address, the source address and the data field of the copy of the packet together with said error check result and the time-of-day data to produce an error record; and storing in the memory said error record in response to said error detect signal.

Inventors: OJIMA SAWAKO, OJIMA, SAWAKO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H04L12
IPC codes: H04M3, G06F11, H04L12