DATA-PROCESSING SYSTEM WITH A DEVICE FOR HANDLING PROGRAM LOOPS

Abstract: The invention concerns a data-processing system of the microprocessor type, with two pipeline levels comprising a device of executing an instruction sequence in a repetitive manner, comprising a program counter (74), and a program-address-start register (76) to record the number of the first instruction of the instruction sequence and a repeat counter (70) initialized at the time the first instruction of the instruction sequence is executed. The next-to-last instruction of the instruction sequence to be repeated contains an end-of-loop (EOL) code, which, when the last instruction of the loop is executed, directs that the contents of the program-address-start register (76) be loaded into the program counter (74) as long as the repeat counter is not at zero. The end-of-loop (EOL) code permits an important reduction in the circuits used and an increase in the speed of handling loops.

Description: DATA-PROCESSING SYSTEM WITH A DEVICE FOR HANDLING PROGRAM LOOPS The present invention concerns data-processing systems of the microprocessor type, and in particular a data-processing system comprising an improved device for handling program loops of the type comprising a program-address-start register to record the number of the first instruction of the loop and a repeat counter initialized at the time the first instruction is executed with the number of repetitions to be made; the repeat counter is decremented at the end of each loop, and execution of the loop is repeated until it reaches zero. In another aspect, the data- processing system may include a status register containing status parameters that are a function of the results of arithmetic and logic operations and the updating of which depends on the program. The command program of the data-processing system may include instructions depending on parameters of the status register determined by the result of arithmetic and logic operations. In yet another aspect, a device for selectively reading/writing data, byte by byte, in the data-processing system is provided and comprises a data memory in which the memory locations each contain a predetermined number of bytes. During the past decade, informatics has invaded industrial technology. Data-processing systems now perform functions more rapidly and more precisely than humans. The advent of the microprocessor or, in general, the possibility of integrating a data-processing system on a single tiny chip, has permitted most of the equipment in any field to be automated and made more efficient. SUBSTITUTESHEET These considerable steps in progress have been made possible thanks to the technology of manufacturing the elementary circuits that make up data-processing systems. This progress has permitted more and more intensive miniaturization, resulting in an enormous increase in the speed of instruction processing, even greater processing power, and a reduction in manufacturing costs from the use of identical elementary circuits, generally transistors, and a reduced consumption of the basic material of the circuits, silicon. In parallel with these improvements, mainly due to semiconductor technology, attempts have been made to improve data-processing systems by other means, such as a reduction of the logic circuits used for execution of instructions or a reduction of the operations necessary to execute the program. This is precisely a purpose of the present invention. Thus, a program of instructions for running a data- processing system such as a microprocessor often consists of an instruction sequence to be executed many times in order to achieve a given result. This is what is commonly called a loop. The classical technique for handling loops consists of recording the number of repetitions of the instruction sequence or loops to be performed in a counter and recording the number of the last instruction in the loop in a register. At each instruction, a comparison is made between the number of the instruction to be executed, given by a program counter, and the number of the last instruction recorded. When the comparison is positive, the repeat counter is decremented and the value of the program counter is replaced by the value of the first instruction of the loop, which is recorded in a program-address-start register, this being done as long as the repeat counter has not reached zero. SUBSTITUTESHEET This comparison requires functional elements such as a register for recording the number of the last instruction of the loop and a comparator, as well as a comparison operation performed at each instruction. Loop handling is therefore performed at the cost of logic circuits, which evidently consume silicon and a significant amount of time. One purpose of the invention is therefore to realize a data- processing system such as a microprocessor, of which the device for handling loops consists of a reduced number of logic circuits and permits a substantial gain in processing speed. An instruction set for directing a classical data-processing system such as a microprocessor or a digital-signal processor (DSP) consists of instructions of the arithmetic and logic type and instructions for breaking the instruction sequence, such as conditional or unconditional branching or skipping instructions. Instructions of the arithmetic and logic type direct arithmetic and logic operations performed by the arithmetic and logic unit (ALU) . The result of an operation of this type is that a certain number of parameters, called status parameters, which are generally stored in a status register, are modified. These parameters are, among others, parameters indicating that the results of the operation is zero (Z) , or negative (N) , or that the operation has generated a carry (C) . At each instruction of the arithmetic and logic type, the status parameters in the status register are therefore updated by the results provided by the arithmetic and logic unit. However, this automatic updating has the inconvenience that the programmer does not control the contents of the status register, since it is modified at each instruction. But most of all, in the case of a test that conditions a branching, it is not possible to insert instructions SUBSTITUTESHEET of the arithmetic and logic type between the instruction whose result should be used (that is, the status parameters) and the branching instruction, because this latter could be conditioned in an erroneous manner by status parameters modified by intervening instructions, since updating of these parameters occurs automatically. Another purpose of this invention is therefore to realize a data-processing system in which the status parameters, resulting from arithmetic and logic operations, are not updated automatically. A program of instructions for directing a data-processing system such as a microprocessor often includes instructions to be executed differently according to the results of preceding instructions. For example, this can be common in a specialized data-processing system such as a digital signal processor (DSP) . In this type of processor, the result of a comparison determines whether an addition or subtraction is to be performed. According to the result of the comparison, the program flows in sequence if addition is involved or makes a branch consisting of a skipping one or more instructions if subtraction is involved. Of course, it is necessary to again envision a skipping of the instructions if subtraction is involved. A double set of instructions (addition and subtraction) must therefore be included in the program, and branching and skipping instructions must also be provided. This substantially increases the number of program instructions, and most of all, it consumes time, to the detriment of the processing speed of the set of operations. Another purpose of the invention is therefore to realize a data-processing system such as a microprocessor comprising a SUBSTITUTESHEET reduced number of instructions depending on the results of previous operations. Another purpose of the invention is to realize a data- processing system including a single instruction in place of several alternative instructions, depending on the results of previous operations. One of the consequences of the increase in processing power is the processing by the processing unit of larger and larger data words. Thus,' processing that was done by 8-bit words a few years ago is done by 16-bit words in commercial microprocessors. There now exist processors where processing is done on 32-bit words, and we envisage processing by 64-bit words from now on. In spite of this increase in the length of data words that can be processed in present processors, the elementary- addressable unit in memory remains the byte, that is, the 8-bit word. When one speaks about the capacity of the main memory of a data-processing system, of a hard disk, or a diskette, this capacity is always expressed in bytes. This comes from the fact that the group of 8 bits remains the most adequate unit of information for representing a character of alphanumeric data. 16-bit processors have the possibility of reading (or writing) 8-bit words or 16-bit words in memory. When 16-bit words are involved, there are two ways of reading. When reading is done in order of increasing addresses, it starts either from the high-order 8-bit portion of the 16-bit word or from the low- order 8-bit portion. This can be of great importance in numerous applications, and in particular in telecommunications, which requires transmission of data in blocks formed by series of bytes. In fact, these transmissions can be made by sending the most significant bit first (MSB mode) or by sending the least TUTESHEET significant bit first (LSB mode) ; it is necessary to determine which of the two parts of the 16-bit word should be read first. This type of application, in which a chain of 8-bit bytes is transmitted, mostly uses indirect addressing. That is, the instructions that direct the transfer of information have access to one of the general registers of the processor in which the memory address of the word in memory is located. Each instruction contains a group of two bits which directs incrementing of the address located in the register, or decrementing it, or neither of those. Incrementing is used when one desires to read a series of bytes in memory in the direction of increasing addresses. Decrementing is used when one desires to read a series of bytes in memory in the direction of decreasing addresses. And of course, neither of these commands is made when either the transmission operation is terminated or the address loaded into the register is done by an operation that is neither incrementing nor decrementing. Consequently, two instruction bits must be available in order to provide for these three cases above. It will be seen therefore that this type of operation requires the use of two bits in each instruction and the use of an incrementer-decrementer, therefore a relatively complex logic circuit requiring numerous transistors. Another purpose of the invention is therefore to realize a device for reading/writing in the memory of a data-processing system that requires only one incrementer (or decrementer) for the operations of addressing a series of bytes in memory and not the incrementer-decrementer combination used in the systems of prior technology. SUBSTITUTESHEET One object of the invention is a data-processing system in which of the last instructions of the instruction sequence to be executed several times, in which the departure from the last instruction of the instruction sequence depends on the pipeline number of the system, containing a code at the end of the loop, which directs that when the last instruction of the loop is executed, the program counter to be loaded from the program- address-start register as long as the repeat counter is not at zero, so that the instruction sequence is repeated a number of times equal to the value contained in the repeat counter. An object of the invention is a data-processing system of the type stated above, in which the arithmetic and logic instructions include an updating field and the status parameters stored in the status register are updated only when the updating field contains a predetermined value. Another object of the invention is a data-processing system of the type comprising an arithmetic and logic unit for performing arithmetic and logic operations by the operation code of the instructions of a program and a status register containing status parameters, the value of which depends on arithmetic or logic operations performed by the arithmetic and logic unit, and including a circuit for decoding the parameters contained in the status register for modifying the operation code of an instruction transmitted to the arithmetic and logic unit as a function of the status parameters, so as to provide several operation codes equivalent to several alternative instructions, the execution of which depends on the status parameters. Another object of the invention is a device for reading data byte by byte in a system of data comprising a data memory, of which the memory locations each contain a predetermined number of SUBSTITUTESHEET bytes, the read device comprising a selection means that determines the end of each memory location from which the first byte of the predetermined number of bytes should be read first in response to a selection bit located in the status register of the system. Another object of the invention is a device for writing data byte by byte in a system of data comprising a data memory, of which the memory locations each contain a predetermined number of bytes, the write device comprising a selection means that determines the end of each memory location into which the first byte of the predetermined number of bytes should be written first in response to a selection bit located in the status register of the system. The invention will be understood better through reading the following with reference to the drawings, in which: - Figure 1 shows the overall scheme of a data-processing system in which the invention has been applied; Figure 2 shows the overall scheme of a device for repetitive execution of an instruction sequence according to the prior technology; Figure 3 shows the overall scheme of a device for repetitive execution of an instruction sequence according to a preferred implementation mode of the invention; - Figures 4A-4D show diagrams illustrating the operation sequence performed when the device shown in Figure 3 is applied to various steps of the repetitive execution of the instruction sequence; - Figure 5 is the overall scheme of a preferred application of the invention; SUBSTITUTESHEET - Figure 6 schematically illustrates a device applying the aspect of the invention, wherein the command program includes instructions depending on parameters of a status register; Figure 7 is an overall scheme of a preferred implementation of the aspect of the invention shown in Figure 6; - Figure 8 shows an overall scheme of a preferred embodiment of a device for reading data in memory according to another aspect of the invention; - Figure 9 shows an overall scheme of a preferred embodiment of the device for writing data in memory in accordance with the aspect of the invention also illustrated in Figure 8; and Figures 10A and 10B show embodiments of the ones- complement circuit used in the read/write devices illustrated in Figures 8 and 9. Figure 1 shows the organization of a data-processing system incorporating the invention. A preferred data-processing system for applying the invention is a data processor of the digital- signal type or a microprocessor as described below. The program instructions, sometimes called microinstructions when the data-processing system is a microprocessor, are recorded in a program memory 10. The program memory 10 is generally a permanent memory or a read-only memory (ROM) of the programmable type (PROM) or erasable (EPROM) type. However, memory 10 can also be a read-write memory (RAM) . Memory 10 communicates via the bus 12 with a decoding and control unit 14, which contains the essentials of the system logic, with the task of decoding the instructions coming from the program memory 10 and of controlling the progress of the decoded information in the instructions. This information can be used either to access data or for arithmetic and logic operations. To SUBSTITUTESHEET do this, the decoding and control unit 14 is connected to the address bus 16. Bus 16 is connected, on the one hand, to a block of processing registers 18, which contain the general registers used for instruction processing. These registers are designed to contain the operands contained in the instructions or coming from the data memory, or they can serve as index registers for indirect addressing. But these processing registers can have other functions assigned most of the time to the decoding and control unit. Thus, the block of processing registers 18 can contain the program counter (PC) , incrementation registers, shift registers, used mostly in operations of multiplication and division, such as a Booth shift register, or else a status register, which contains a number of parameters determined after execution of an arithmetic or logic instruction with result zero, result negative, or with a carry. Most of the registers of block 18 are addressable by means of the address bus 16. The address bus 16 is likewise an input to an address- decoding unit 20, the function of which is to decode the addresses resulting from decoding to the instructions by the decoding and control unit 14 in order to access data stored in a data memory 22. The data memory is generally a read-write memory (RAM) , but it could also be a permanent memory or any other kind of memory. It will be noted that the block of processing registers 18 is connected to the address bus 16 in such a way that the contents of certain registers of block 18 can be transmitted to the address-decoding unit 20 when this content is an address for accessing the data memory 22. In order to perform the arithmetic and logic operations ordered by the content of the program instructions, an arithmetic and logic unit (ALU) 24 is connected to the output of the block 10 SUBSTITUTESHEET of processing registers 18. The output of the arithmetic and logic unit 24 is either a storage of data in the data memory 22 by the data bus 26 or a new address from one of the registers of the block of processing registers 18 via the results bus 28. The data coming from the data memory 22, the address of which has been provided by the address-decoding unit 20, are transmitted to the input of the arithmetic and logic unit 24 by means of the memory-reading bus 30. Finally, the block of processing registers 18 is connected to the control unit for peripheral devices 32 by means of the input/output bus 34. The data-processing system that has just been described is of the Harvard type, that is, the memory 10 containing the instructions is completely separate from the memory 22 containing the data. But the invention could likewise by applied in data- processing systems of another type. Similarly, the data- processing system can be a microprocessor of universal application, but equally a specialized microprocessor such as a digital signal processor (DSP) used in devices for data transmission, and in particular a cellular radio device (GSM, DECT, or equivalent) . The instructions comprising the command program of a data- processing system such as that described above are generally processed in sequence, a program counter (PC) being incremented at each of the instructions. But it happens that an instruction sequence should be repeated a certain number of times in order to perform repetitive operations as well. In the classical manner, this repetition of an instruction sequence, called a loop, is applied in the manner described below. 11 SUBSTITUTESHEET Suppose that an instruction sequence 1, 2, ... N should be executed n times. The instruction sequence to be applied is shown in an illustrative manner in Table I. Table I program counter -1 0 1 N-l N function of instruction load RPTC load PAER arithmetic or logic operation + load PASR arithmetic or logic operation arithmetic or logic operation + load RPTC An overall scheme of a device of the above kind, permitting execution of the instruction sequence of Table I is shown in Figure 2. At instruction -1, the number n - 1 is loaded into a repeat counter (RPTC) 40. At instruction 0, the 12 SUBSTITUTESHEET instruction number of the end of the loop, that is, N, is loaded into a program-address-end register (PAER) 42. These two loading operations are performed by means of the data bus 44. At instruction 1, by more than one arithmetic or logic operation, the number 1 given by the program counter (PC) 46 is loaded into a program-address-start register (PASR) 48 by means of bus 50 on command of an initialization signal on line 51. The instructions from 2 to N - 1 are executed in sequence, the program counter 46 is incremented at each instruction, thanks to the incrementer 52 and by means of the multiplexer 54, of which the active input is the bus 56, as will be seen. At each incrementation of the program counter 46, its contents are compared to the contents of the PAER register 42 by the comparator 58. If the contents are different, a 0 bit is transmitted to the AND circuit 60 by its input 62. Consequently, the AND circuit has its output 64 at zero, which will activate the input 56 (incrementation of the program counter) of the multiplexer 54. When the program counter 46 shows N, corresponding to the contents of register 42, the comparator 58 transmits a 1 bit on line 62. As the other input line 66 of the AND circuit 60 is at 1, because the RPTC counter 40 is not equal to zero, the AND circuit 60 becomes passable, and a high signal is transmitted on its output line 64 to the multiplexer 54. The latter is activated on its second input, and the contents of the PASR register 48 are loaded into the PC program counter 46. That is, the value N is replaced by the value 1. At instruction N, in more than one arithmetic or logic operation, the value of the RPTC counter 40 is decremented by means of the decrementer 68. 13 SUBSTITUTESHEET The instruction sequence 1 through N is thus repeated until the RPTC counter is decremented to zero, in which case the 0 signal on line 66 blocks the AND circuit 60 and the value of the PC program counter 46 (at occurrence N) is not replaced by the contents of the PASR register 48. Since the multiplexer 54 is no longer activated on its second input, it is the incremented value of the contents of the program counter that are loaded into the program counter. Because this decrementing of the RPTC counter 40 ordered by instruction N, only takes place at instruction 1, the loop is executed n times when the number n - l has been loaded into the RPTC counter 40. It should be noted that in a data-processing system where the functioning is of the pipeline type, execution of the instructions takes place one, two, or more instruction cycles after the call of the instructions, according to whether the functioning of the pipeline is at one, two, or more levels. Thus, in the above example, loading of RPTC, PAER, and PASR does not take place during instructions -1, 0, and 1, if the pipeline system with two levels is used, but, respectively, during instructions 0, 1, and 2. As has already been stated, the purpose of the invention is to reduce the number of operations to be performed and the number of circuits used. Such a goal is realized by using the device illustrated by the overall scheme of Figure 3 in place of the device of Figure 2. Supposing that one wishes to execute the same loops as before, the instruction sequence is then shown in the following manner: 14 SUBSTITUTESHEET Table II program counter 0 1 N - l N function of instruction load RPTC arithmetic or logic operation + load PASR arithmetic or logic operation + end of loop (?EOL) arithmetic or logic operation + decrement RPTC At instruction 0, the number n - 1 is loaded into an RPTC repeat counter by means of the data bus 72. At instruction 1, in more than one arithmetic or logic operation, the number 1, given by the program counter (PC) 74, is loaded into a program-address- start register (PASR) 76 by means of bus 78 under the command of an initialization signal on line 79. Instructions 2 through 15 SUBSTITUTESHEET N - l are then executed in sequence, the program counter 74 being incremented at each instruction thanks to an incrementer 80 and by means of a multiplexer 82, of which the active input is the bus 84, as will be explained below. The RPTC counter 70 being positive (its contents were set at n - 1), its output 86 is at 1. Line 86 is an input to an AND circuit 90, of which the other input 88 is the EOL signal. This input is low, that is, the EOL signal is at zero, during the whole execution of instructions 1 through N - 2, thus blocking the AND circuit 90, of which the output 92 activates the multiplexer 82 in the manner that has been conditioned by the input 84 of the value previously incremented by the incrementer 80. At the time of execution of instruction N - l, the end-of- loop code EOL is decoded, and line 88 becomes high, which has the effect of unblocking the AND circuit 90, and a 1 signal is transmitted to the multiplexer 82. The active input of the multiplexer 82 then becomes the output of the PASR register 76, the contents of which (1 in fact) are loaded into the program counter 74, replacing the value it previously contained. At instruction N, in more than one arithmetic or logic operation, the value of the RPTC counter 70 is decremented by means of the decrementer 94. The instruction sequence 1 through N is thus repeated until the RPTC counter 70 has been decremented to zero, in which case the output signal 0 on line 86 blocks the AND circuit 90, and the value of the program counter PC 74 (or N) is not replaced by the contents of the PASR register 76 as during the preceding loops, but is incremented to the value N + 1. As before, because this decrementing of the RPTC counter 70 ordered by instruction N, does not take place until instruction 1, the loop is executed n 16 BSTITUTESHEET times when the number n - l has been loaded into the RPTC counter 70. It will be seen, therefore, that the essential characteristic of the invention consists of incorporating into the next-to-last instruction of the loop a coding indicating the end of the loop to permit realization of a reduced device with respect to the classical device, fulfilling the same function. Thus the device illustrated in Figure 3 no longer includes the program-address-end register (PAER) or a comparator for the purpose of comparing the contents of the program-address-end register with the program counter at each instruction. The EOL code indicating the end of the loop is, in the preferred implementation mode of the invention, one of the instruction bits. When this bit is at 1 in an instruction, this means that the next instruction is the last instruction of an instruction sequence, and, as has been seen before, this 1 bit permits the number of the first instruction of the instruction sequence in the loop to be transferred to the program counter. However, one can envision that the EOL code may have a particular value in the instruction field and not just a single bit, in which case a decoding will be necessary. It should be noted that the device according to the invention illustrated in Figure 3 has been applied in a data- processing system or a microprocessor of which the functioning is of the pipeline type with two levels. That is, access and decoding of an instruction take place in the same cycle as execution of the preceding instruction. Figures 4A-4D, showing diagrams which illustrate the progress of the operations applied in the device of the invention, will permit a better understanding of these particular points. 17 SUBSTITUTESHE In the diagram of Figure 4A, the first loop is initialized. As the microprocessor considered is of the pipeline type with two levels, instruction 0, which orders charging of the RPTC is not executed until the computer's program cycle PC = 1, and the value n - 1 is loaded into the RPTC counter at cycle PC = 2. At cycle PC = 1, an initialization signal is present on line 79 (see Figure 3) , which involves loading the PASR register with the value of the program counter, 1 in this example, at cycle PC = 2. Diagram 4B schematically illustrates the end of the first loop. At cycle PC = N - 1, decoding of instruction N - l encounters the EOL condition, which induces a high signal on line 88 (see Figure 3) at the next cycle, PC = N. The contents of the PASR register are then transferred into the program counter, which changes from PC = N to PC = 1 at the next cycle. At cycle PC = N, corresponding to the last instruction of the loop, decoding of instruction N indicates that the RPTC counter should be decremented. The RPTC counter therefore changes from the value n - 1 to the value n - 2 at cycle PC = 1, which follows the cycle PC = N. The end of the n - l loop is illustrated schematically in Figure 4C. At cycle PC = N - 1, decoding of instruction N - l makes the EOL condition appear, which induces a high signal on line 88 (of Figure 3) at cycle PC = N. The contents of the PASR register are then transferred to the program counter, which changes from PC = N to PC = 1 at the next cycle. At cycle PC = N, corresponding to the last instruction of the loop, decoding of instruction N indicates that the RPTC counter should be decremented. The RPTC counter therefore changes from the value 1 to the value 0 at cycle PC = 1, which follows cycle PC = N, that 18 SUBSTITUTESHEET is, after the value PASR = 1 has been loaded into the program counter which initializes the nth loop. As illustrated in the diagram of Figure 4D, decoding of instruction N - 1 at cycle PC = N - 1 results in a high signal on line 88 (of Figure 3) at cycle PC = N. But, in contrast to the preceding loops, the RPTC counter is at zero, and consequently the contents of the PASR register are not transferred to the program counter. Because of this fact, the PC program counter continues to increment to N + 1, N + 2, ..., without starting over at the value 1. Thanks to the diagrams of Figures 4A-4D, it can therefore be seen that in a machine of the pipeline type with two levels, application of the contents of the instruction is made at the cycle following execution of the instruction. Thus, in order that the EOL condition be able to fulfill its function on the last instruction of the loop (N in the example) , it should be contained in the next-to-last instruction. If no pipeline is being used, that is, access, decoding, and execution take place in the same cycle, the condition should be found in the last instruction of the cycle. Conversely, in a machine of the pipeline type with three levels, that is, access, decoding, and execution are made in three consecutive cycles, the EOL condition should be found in the instruction before the next-to-last instruction, N - 2 in the example. An inherent advantage in the invention is that a precaution, which is taught to every beginning programmer, is no longer needed, that is, having to avoid conditional branches into the inte r ior of a loop. In systems of the prior art, branches are delicate to manipulate within a loop, because it is not always easy to return to the loop when several branches intervene, and 19 SUBSTITUTESHEET it is therefore imperative to terminate at the end of the loop to the extent that the value at the end of the loop stored in a PAER register (see Figure 2) conditions this end. The invention permits this obligation to be eliminated, because the programmer can incorporate one or more instructions involving the EOL code into his program without problem. He could thus also include branches to the interior of the instruction sequence without having the problems that programmers using the previous technology have. The device that applies the invention, illustrated in Figure 3, includes a certain number of elements (program counter, incrementer, repeat counter, multiplexer, etc.) that are found typically incorporated into the decoding and control unit. However, in a preferred implementation of the invention, the program counter, the program-address-start register, the incrementer, and the multiplexer are registers in the block of processing registers. Such an integration of registers having the same structure permits a gain in speed as well as in cost. But it is clear that one can envision such a device in which some of the elements are found in the decoding and control unit and others are in the block of registers, without leaving the scope of the invention. The invention that has just been described permits a reduction in the number of elements in the device employed (absence of the PAER register and the comparator) . This advantage appears concretely in a reduction in elementary circuits (of transistors) . Thus, in a 16-bit microprocessor, the invention leads to a gain of 600 transistors or a gain of 10% in the whole microprocessor. But a gain in speed is equally possible, especially for short loops, since there is an economy 20 SUBSTITUTESHEET of instructions (instruction -1 of Table I) serving to initially load the program-address-end register (PAER) . The block of data-processing registers includes a register with the role of storing the status parameters that result from arithmetic and logic operations performed by the arithmetic and logic unit (ALU) . In prior data-processing system, the status register is a particular register that is not part of the general processing registers; its content is automatically updated at each arithmetic and logic operation by status parameters coming _ from operations performed by the ALU, even if these parameters are not modified from one operation to the next. Automatic updating of the status register at each arithmetic instruction has the inconvenience for the programmer of not having total control of the status register. This has at least two awkward consequences. The first is that a test of the status register must immediately follow the instructio on which it depends, without the possibility of inserting arithmetic and logic instructions that could modify the contents of the status register between this instruction and the test. The second awkward consequence in a classical data- processing system is the impossibility of having a status register available for operations depending on the programmer. Because of this, in data-processing systems applying the invention, the status register is a general register of the same kind as the other general registers that are part of the block of processing registers, and it therefore remains under control of the programmer. But in contrast to prior systems, the status register is only updated by results coming from the arithmetic and logic unit in execution of an instruction specifically directing this updating. 21 SUBSTITUTESHEET Figure 5 schematically shows the device that applies this invention. In the figure, only status register 140 in the block of processing registers has been shown. Status register 140 contains the status parameters N, indicating a negative operation result, Z, a zero result, and C, an operation with a carry. These three parameters are, in the preferred realization, those which are updated by the results of an arithmetic and logic operation performed by the ALU 24 using the device of Figure 5. But it is evident that this choice is not limiting, and that a greater number of status parameters could be updated. Each program instruction contains, in the classical manner, a field 142 affected by an operation code or OPCODE and a condition-code field 144. Moreover, the instruction includes a field US 146 for updating the parameters N, Z, and C. In the preferred implementation of Figure 5, the US field is a single bit, but this is in no way limiting, and the US field could contain several bits without leaving the scope of the invention. Bit 146 serves as an input to an AND circuit 148, the other input of which is the write signal, W, which functions in the classical way at each instruction cycle. When bit 146 is at 1, the AND circuit becomes passable, and the write signal, W, directs loading of new status parameters, N, Z, and C, by means of lines 150 coming from the arithmetic and logic unit 24 into status register 140. In the absence of the invention, the status parameters of status register 140 would be updated automatically by means of the lines 150 at each instruction when signal W has been activated. The circuit that permits this updating has not been modified (it is part of the AND circuit 148); it is classical, and its description is not necessary for understanding this invention. 22 SUBSTITUTESHEE It will therefore be seen that updating of the status register takes place only when the US bit 146 is at 1. This updating therefore remains under the control of the programmer. Application of the invention accomplishes its full purpose when it is used in combination with conditional instructions. The principal of conditional instructions, as it has been described in French Patent Application No. FR-A-9,107,985, consists of envisioning a condition-code field on which execution of the instruction will depend. Thus, as has been explained in the application cited above, it is not necessary to modify the destination register by the result of a subtraction, if this subtraction is performed for the purpose of a comparison. In this case, it is the condition code that indicates that there has been no loading of the results into the destination register. The following example will permit better understanding of the whole purpose of the invention in connection with conditional instructions. The following instruction sequence is classical in a prior data-processing system: 1st instruction subtract a - b 2nd instruction if N = 0 continue, else branch to L 3rd instruction operation X L 4th instruction operation Y The first instruction is a comparison instruction, the result of which conditions the flow of the program. If the result is negative, N = 0, instruction 3 is executed. Otherwise, the program skips instruction 3 and continues starting from instruction 4. This type of branching, in which only one instruction is skipped over when a condition is not fulfilled, is very frequent in processors used in the transmission of data, such as digital- 23 SUBSTITUTESHEET signal processors (DSP) , where the program conforms to a given protocol. Using conditional instructions such as the instruction to update the status register as envisioned by the invention, the instruction sequence becomes: 1st instruction subtract a - b, update status register 2nd instruction operation X if N = 0 _ 3rd instruction operation Y The first instruction directs updating of the status register in addition to performing subtraction. Instruction 2 includes an operation-code field that directs execution of an operation X, but also a condition code that permits execution of the operation X determined by the operation code only if N = 0. Generally, branching instructions such as those shown in the above example require several cycles, either 2, 3, or 4 cycles. It will therefore be seen that the time consumed in the above example without application of the invention, that is, with the branching instruction, is 4, 5, or 6 cycles in the most favorable case. In contrast, when the invention is applied, only 3 cycles are necessary, since the branching instruction that uses several cycles has disappeared. The following example illustrates a sequence of instructions that could be encountered in a program executed in a data- processing system applying the invention. 24 SUBSTITUTESHEET 1st instruction subtract a - b, update status register 2nd instruction operation 01 involving the status register 6th instruction operation 02 if condition Cl is realized 7th instruction operation 03 involving the status register 14th instruction operation 04 involving the status register 15th instruction operation 05 if condition C2 is realized 16th instruction operation 06 involving the status register 19th instruction operation 07 if condition C3 is realized 23rd instruction operation 08 involving the status register 27th instruction operation 09 if condition C4 is realized 36th instruction subtract a - b, update status register In the above sequence of 36 instructions , there are 4 instructions that involve conditions, namely instructions 6 , 15 , 19 , and 27. Without combining the use of conditional instructions and directed updating of the status register, it would have been necessary to envision 4 conditional-branching instructions, requiring consumption of a significant number of cycles . Updating the status register only occurs at instruction 1 and instruction 36. This permits the programmer to control the flow of the program perfectly. It is thus possible to envision placing a conditional instruction that takes the values N, Z, and C into account (condition Cl) as the 6th instruction. This would not have been possible in a prior data-processing system, because the intermediate instructions would update the status register automatically. In contrast, to the extent that the programmer himself determines, at which instructions, updating of the status 25 SUBSTITUTE SHEET registers will occur, he used the status register as a processing register in instructions 2, 7, 14, 16, and 23, which would not, of course, have been possible in the prior technology. It will therefore be seen that application of the invention permits the programmer to retain control of the status register and to make use of it like any other processing register. Moreover, in combination with the use of conditional instructions, the invention permits avoiding numerous branches that consume many cycles. These two advantages contribute to a substantial reduction in the number of program instructions. In practice, application of the invention can permit a reduction of about 2 million instructions out of a total of about 10 million instructions required by programs of the ADPCM type used in a voice encoder-decoder, which represents an improvement in the performance of the processor on the order of 20%. The general principle of an aspect of the invention is to envision instructions in which the operation code is variable according to the system's status parameters. This principle will now be described with reference to Figure 6, which represents a general implementation method of the invention. As illustrated in Figure 6, each instruction 240 contains a field 242 containing the operation code (OPCODE) of the instruction. This operation code, which is decoded by the decoding and control unit 14 (already illustrated in Figure 1) , is the code that directs the type of operation to be performed, such as Addition, Subtraction, Comparison, etc. In response to the decoding, the signals on the output lines 244 then direct either addressing of processing registers or addressing of data in memory, as has been seen previously with reference to Figure 1. A group 246 of output lines, which can, moreover, be reduced to a single line as will be seen later, is connected to a decoding circuit 248. These lines 246 provide the signals produced by decoding the instructions used to apply the invention, while, for all the other instructions, the decoding signals are provided by lines 244. The information provided on lines 246 for decoding the operation code of an instruction depending on the status parameters are used by the decoding circuit 248 in combination with certain status parameters found in the status register 250 of the block of processing registers 18. The status parameters of status register 250 used within the framework of the invention are: N: bit at 1 when the sign bit (MSB) of the preceding operation is at 1, indicating that the result of this operation is negative, Z: bit at 1 when the result of the preceding operation is zero, C: carry bit at 1 when the operation generates a carry. According to the value of the status parameters N, Z, or C, the decoding circuit 248 provides a command code on lines 252 in response to the signals received on lines 246 coming from decoding of the operation code of an instruction depending on the status parameters. This command code is transmitted directly to the arithmetic and logic unit 24, the operation of which will be different according to the code. In Figure 6, three lines 252 are shown, because eight different command codes can be provided in response to the eight possible combinations of the parameters N, Z, and C. But it goes without saying that the number of lines can be less than or greater than three without violating the principle of the invention. Figure 7 illustrates a preferred implementation method of this aspect of the invention, which permits giving evidence, thanks to a real example, of the reduction in the number of instructions made possible by application of the invention. The example illustrated in connection with Figure 7 concerns an instruction sequence in which the operation to be performed is either addition or subtraction, the choice depending on a previous comparison. In a classical data-processing system, the instruction sequence appears in the following manner (for clarity, AO, Al, X, and B are registers in the block of processing registers) : 1st instruction compare AO and Al 2nd instruction branch to Ll if N = 1 3rd instruction add X + B, result in B 4th instruction continue at L2 Ll 5th instruction subtract B - X, result in B L2 6th instruction In this implementation of the invention only status parameter N of status register 250 is used. The value of N is used as the first input of an EXCLUSIVE-OR circuit 260 (corresponding to the decoding circuit of Figure 6) . The second input of circuit 260 is an operation-code bit of an instruction depending on status parameters, of which there are four in the case illustrated. According to whether N has the value 0 or the value 1, depending on the result of the preceding comparison, this operation-code bit will or will not be inverted. The output signal from the EXCLUSIVE-OR circuit 260 on line 262 is therefore the same as the bit of the input code when N = 0 and the inverse when N = 1. This bit on line 262 is sent to the arithmetic and logic unit 24, which performs addition when N = 0 and subtraction 28 SUBSTITUTESHEET when N = 1. It should be noted that at the same time the ALU unit 24 is conditioned by other bits of the operation code (three in the present case) to perform either addition or subtraction. Thanks to the device illustrated in Figure 7, the instruction sequence to be executed is the following: 1st instruction compare AO and Al 2nd instruction add B + X if N = 0 and subtract B - X if N = 1, result in B It will therefore be seen that, thanks to this aspect of the invention, the instruction sequence only requires two instructions in place of five with a classical data-processing system. In practice, application of this aspect of the invention permits a substantial gain of about 500,000 instructions out of the total of 8 million instructions necessary for a program of the ADPCM type used in a voice encoder-decoder, which represents an increase in the speed of the processor on the order of 6-7%. Even though this aspect of the invention has been applied in practice in the implementation illustrated in Figure 7, in which only the parameter N has been used, one can easily imagine an implementation in which the two status parameters N and Z are used. In this case, the input code to the decoding circuit will comprise two bits, and the decoding circuit itself should comprise two EXCLUSIVE-OR circuits in series. The four possible outputs of the decoding circuit could be used to direct the arithmetic and logic unit to perform one of four operations, such as addition, subtraction, setting to zero, and setting to one. Block 27, between bus 26 and the memory 22 in the system as shown in Figure 1, represents the device for writing byte by byte in memory, according to another aspect of the invention, as will 29 ET be explained in the following. The data coming from the data memory 22, the address of which has been provided by a the address-decoding unit 20, is transmitted to the input of the arithmetic and logic unit 24 by means of address bus 30. Block 29 represents the device for reading byte by byte in memory according to this aspect of the invention, as will be explained in the following. As illustrated in Figure 8, which shows an overall scheme of a preferred embodiment of the read device according to this aspect of the invention, the address-bus lines 16 are divided into two parts. The lines corresponding to the high-order bits 342 are decoded by an address-decoding unit 340 to access memory locations in the data memory 22. If each memory location 344 comprises two bytes, bus 342 comprises all the address-bus lines 16 except line A Q , corresponding to the lowest-order bit. If each memory location comprises 4 bytes, bus 342 comprises all the lines of the address bus 16 except lines A Q and A^, corresponding to the two lowest-order bits of the address. And so forth. In the implementation example described here, the data bytes considered are octets, or 8 bits. This means that a memory location containing two bytes corresponds to 16 bits, a memory location containing four bytes corresponds to 32 bits, etc. However, it must be well understood that even though processors currently use 8-bit words or bytes as units of elementary information, the invention can be applied likewise to bytes containing more or less than 8 bits. Here it is good to explain how data is arranged in memory. There are two methods for memory arrangement. The highest-order byte of the memory word may be the leftmost byte 344-1 in memory location 344; in this case the low-order byte is at the right in 30 SUBSTITUTESHEET 344-2. Or else the lowest-order byte is the leftmost byte in 344-1; in this case the highest order bit is at the right end of the memory location, or part 344-2. When one proceeds with reading the memory location 344, byte by byte, if we start by reading the highest-order byte in the leftmost part of the memory location, or part 344-1, we are accustomed to saying that the reading is being done in the "big endian" mode. On the other hand, if we start by reading the lowest-order byte in the rightmost part 344-2 of the memory location, we are accustomed to saying that the reading is being done in the "little endian" mode. Thus, with memory locations containing 16 bits, the "little endian" mode corresponds to reading bits 7-0 first in 344-2. As has been explained above, one of the characteristics of the invention is requiring one incrementer (or decrementer) when proceeding with indirect addressing in memory. Each instruction therefore has a bit which, when it is 1, directs incrementing of the contents of the register containing the address, for example register X of the register block 18 (see Figure 1) by the incrementer INC of the register block 18. If the processor works in the mode called "little endian, " the lowest-order byte should be received before the highest-order byte, and conversely, if the processor works in the "big endian" mode. The invention is characterized by the possibility of the processor being able to operate equally well in the "little endian" and the "big endian" modes, while still only having one incrementer. Returning to Figure 8, the lines corresponding to low-order bits of the address of the address bus 16, or A Q , A^, etc., are connected to the input of a ones-complement circuit 346. Another input line 348 of circuit 346 comes from a 31 SUBSTITUTESHEET selection bit B/L of the status register STAT of the register block 18. The ones-complement circuit 346 has the effect of inverting each of the bits in the lines A Q , A]_, etc., if the value of the B/L bit is equal to 1 (and likewise has the effect of inverting the order of reading bytes in a memory location) and of having no action in the inverse case. Lines A' Q , A'^, etc., at the output of circuit 346 are connected to the command input of a multiplexer 350. The multiplexer 350 receives as inputs the bytes contained in the memory location 344 addressed by the high- order bits on the lines comprising bus 342. It delivers to its output the entire contents of memory location 344, byte by byte, starting with the byte contained in part 344-2 of the memory location if the B/L bit is 0 ("little endian" mode) or starting with the byte contained in part 344-1 of the memory location if the B/L bit is 1 ("big endian" mode). Only the inputs of multiplexer 350 coming from bytes located at the two ends of memory location 344 have been shown in Figure 8. But it is evident that each of the bytes in memory location 344 is likewise connected to an input of the multiplexer 350, so that the bytes are read one after another, starting either from the leftmost byte or from the rightmost byte. Even though in the preceding description the selection bit B/L is located in the status register STAT, it is clear that such a bit could be positioned in any other register. It will therefore be seen that the principle idea of the invention is a selection of the memory reading mode ("little endian" or "big endian" mode) thanks to a dynamic modification of low-order address bits, and which only requires one incrementer, instead of having two possible addressing modes requiring a decrementer at the same time as an incrementer. This choice of 32 SUBSTITUTESHEET architecture permits an optimization (incrementing or decrementing) of resources in the case where the two addressing modes are not indispensable, because realization of two addressing modes has a higher cost than implementation of the invention. Even though the embodiment that has just been described makes an appeal to a single incrementer, it is easy for an expert in the field to understand that the device of Figure 8 could accommodate a single decrementer (instead of the incrementer) without leaving.the scope of the invention. Of course, if only decrementing is performed in the addressing mode, the reading modes are inverted, the "little endian" reading mode corresponding to the highest-order byte being read first and the "big endian" mode corresponding to the lowest-order byte being read first. Figure 9, which shows an overall scheme of a preferred embodiment of the write device according to this aspect of the invention, contains certain parts in common with Figure 8. Thus, the address-bus lines are likewise divided into two parts. The lines corresponding to high-order bits 342 of the address bus 16 are decoded by the address-decoding unit 340 for accessing memory locations in the data memory 22. In the same way, bus 342 comprises all the address-bus lines 16 except line A Q , corresponding to the lowest-order bit if each memory location 354 comprises two bytes, bus 342 comprises all the lines of bus 16 except lines A Q and ^, corresponding to the two lowest-order bits of the address if each memory location comprises 4 bytes, and so forth. To simplify, memory 22 being the same as in Figure 8, each memory location is composed of a predetermined number of bytes, 33 SUBSTITUTESHEET and has therefore a capacity of a multiple of 8 bits. There too, it is good to explain that this aspect of the invention can be applied to bytes or words containing more or less than 8 bits. As has been previously seen, this aspect of the invention is characterized by the possibility of the processor being able to work both in the "little endian" and the "big endian" mode, while still having only one incrementer. The bus lines 16 corresponding to low-order bits of the address, or AQ, AJ_, etc., are connected to the input of a ones-complement circuit 356. Another input line 358 of circuit 356 comes from the B/L selection bit of the STAT status register of the register block 18. The ones-complement circuit 356 has the effect of inverting each of the bits on lines AQ, A^, etc., if the value of the bit is equal to 1 and of having no action in the inverse case. Lines A' Q , 'I, etc., at the output of circuit 356 are connected to the input of a demultiplexer or address decoder 360. The demultiplexer 360 contains as output as many lines as there are bytes contained in memory location 354. The two output lines 362 and 364 of the demultiplexer 360 affect respectively two AND circuits, 366 and 368. The other input to the AND circuits 366 and 368 is a write line 370, which is active when data should be stored in memory 22 and the memory location is designated by the address located on bus 16. The demultiplexer 360 therefore makes line 362 or 364 active according to the value of the B/L bit in the STAT status register and the value of the A Q bit. When line 362 is active, AND circuit 366 is passing if the write signal is high on line 370, which permits storage of the byte present on data bus 26 in the left part 354-1 of memory location 354. This byte being the highest-order byte of the word, the memory arrangement corresponds to the "big endian" mode. The memory 34 SUBSTITUTESHEET arrangement corresponds to the "little endian" mode if the byte is arranged in part 354-2. Even though only two output lines of the demultiplexer 360, two AND circuits, and two parts (each containing one byte) of the memory location have been shown in Figure 9, it is easy to conceive that there exist as many output lines for the multiplexer and the AND circuits as there are bytes contained in memory location 354. In the same manner as for reading, the B/L selection bit could be stored in another register than the STAT status register. As for the read device shown in Figure 8, the write device represented in Figure 9 permits avoiding simultaneous utilization of an incrementer and a decrementer. We shall make the choice of an incrementer, as is the case for the processor represented in Figure 1, or a decrementer. Of course, if it is the decrementer that is chosen in the addressing mode, the write modes described above are inverted, that is, the "little endian" mode then corresponds to the highest-order byte being written first and the "big endian mode" to the lowest-order byte being written first. Figures 10A and 10B show implementation examples of the ones-complement circuit used in this aspect of the invention. Figure 10A corresponds to a memory in which each location contains 16 bits, consisting of a high-order byte and a low-order byte. In this case, the ones-complement circuit is a simple EXCLUSIVE-OR circuit that has for the first input the B/L bit of the status register and for the second input the line of the low- order bit AQ of the address bus. The output A' Q is the input A Q when the B/L bit is equal to 0 and is the inverse of A Q when the B/L is equal to 1. 35 SUBSTITUTESHEET The circuit shown in Figure 10B corresponds to memory locations containing 32 bits or 4 bytes of 8 bits. In this case, the ones-complement circuit is formed by two EXCLUSIVE-OR circuits having as first inputs the B/L bit located in the status register and as asrolSaiiH inputs line A Q or A^ corresponding respectively to lines of the lowest-order bits of the address bus. Output lines A' Q and A' -_ are identical to inputs AQ and A^ when the B/L bit is equal to 0 and are the inverses of inputs AQ and Ai when the B/L is equal to 1. The aspect of the invention that has just been described therefore permits using only one incrementer (or decrementer) instead of the incrementer-decrementer indispensable in prior-art systems. This permits a non-negligible economy of circuits, since it represents about 400 transistors at least out of a total of about 8000 transistors comprising a processor of the DSP type, or an economy of about 5% in the silicon surface. Moreover, since each instruction only has one bit instead of two for defining incrementing in indirect addressing, the bit saved can be used judiciously for another purpose, which will increase the efficiency of the system still further. 36 SUBSTITUTESHEET

Claims: Claims 1. A data-processing system, of which the functioning is directed by execution of a program composed of an instruction sequence, including a device for executing in a repetitive manner an instruction sequence within said instruction sequence, said device comprising a program counter 74 giving the number of the next instruction of the said instruction sequence, incremented at each of the instructions, a program-address-start register 76 for recording the number of the present instruction of the said instruction sequence, and a repeat counter 70, initialized at the time of the execution of the first instruction of the said instruction sequence with the number of times that execution of said instruction sequence is to be repeated, said repeat counter being decremented at the end of said instruction sequence and the execution of said sequence ending when said repeat counter is at zero; wherein one of the last instructions of said instruction sequence, the distance of which, from the last instruction, depends on the number of pipeline levels of said system, contains an end-of-loop (EOL) code, which directs that when the last instruction of said instruction sequence is executed, the contents of said program-address-start register 76 be loaded into said program counter 74, as long as said repeat counter is not at zero, in such a manner as to repeat execution of said instruction sequence a number of times equal to the contents of said repeat counter 70. 2. A system according to Claim 1, in which said end-of- loop (EOL) code is a bit in each instruction, having the binary value 1 in said one of the last instructions to direct loading of said program-address-start register 76 into said program counter 37 SUBSTITUTESHEET 74 at the time of the execution of the last instruction in said instruction sequence to be repeated. 3. A system according to Claim 1 or 2, in which a two-level pipeline processor is used in such a way that the end-of-loop (EOL) code is the next-to-last instruction of said instruction sequence to be repeated. 4. A system according to any of Claims 1, 2, or 3, including, an AND circuit 90 with two inputs, the first being connected to said repeat counter 70 to provide a 1 signal when said repeat counter is not at 0, the second input being provided by said end-of-loop (EOL) code and the output of the said AND circuit directing a change of a multiplexer 82 connected between said program-address-start register 76 and the program counter 74, so as to transfer the contents of said program counter at the time of execution of the last instruction of said instruction sequence after detection of the end-of-loop (EOL) code and when said repeat counter is not at zero. 5. A system according to any of the preceding claims, in which a branching instruction before the said one of the last instructions permits branching of the program to another instruction sequence terminating with detection of an end-of-loop (EOL) code in such a way that execution of the program is returned to the first instruction of said instruction sequence to be repeated, of which the number was transferred into said program counter when the said EOL code was detected. 6. A system according to Claim 4 or 5, in which said program counter 74, said program-address-start register 76, said repeat counter 70 and said multiplexer are registers in the said block of processing registers 18. 38 SUBSTITUTESHEET 7. A data-processing system, in which the function is directed by the flow of a program consisting of an instruction sequence comprising an arithmetic and logic unit 24 for executing operations determined by arithmetic and logic instructions and a status register 140 containing status parameters, the value of which depends on results of said operations performed by said arithmetic and logic unit; wherein said arithmetic and logic instructions include an updating field 146 and at least some of the status parameters N,Z,C of said status register 140 are updated only when said updating field 146 has a predetermined value. 8. A system according to Claim 7, in which said updating field 146 of each arithmetic and logic unit includes a single bit US, the value of which is set to 1 in an instruction to direct updating of said status register at the time said instruction is executed. 9. A system according to Claim 8, also including an AND circuit 148, of which the first input is provided by said bit US in the updating field 146 and a second input is a write signal W in said status register 140, this latter being updated when said bit US has the value 1, by status parameters resulting from an arithmetic and logic operation performed by the arithmetic and logic unit 24. 10. A system according to any one of Claims 7 to 9, in which said status parameters, updated when the bit US of said updating field is at 1, are an N bit indicating a negative result, a Z bit indicating a zero result, and a C bit indicating a carry. 11. A system according to any of Claims 7 to 10, in which the status register 140 is included in the system's block of 39 SUBSTITUTESHEET processing registers 18 and is used as a processing register by the program. 12. A data-processing system, the functioning of which is directed by the flow of a program composed of an instruction sequence, including an arithmetic and logic unit 24 for performing arithmetic and logic operations directed by the operation code of the instructions of said instruction sequence and a status register 250, containing status parameters, the value of which depends on operations performed by said arithmetic and logic unit; wherein the system includes a decoding circuit 14 of status parameters contained in said status register for modifying the operation code 242 of an instruction transmitted to the arithmetic and logic unit, depending on status parameters as a function of said parameters so as to provide a number of command codes equivalent to several alternative instructions, the execution of which depends on said status parameters, one of said command codes depending -on the value of said status parameters being transmitted to said arithmetic and logic unit in order for it to execute an arithmetic or logic operation associated with said command code. 13. A data-processing system according to Claim 12, wherein said status parameters used to modify the operation code (242) of an instruction depending on status parameters are N, which is at 1 when the result of the preceding operation is negative, Z when the result of the preceding operation is zero, and C, which is at 1 when the preceding operation has generated a carry. 14. A data-processing system according to Claim 13, wherein said decoding circuit is an EXCLUSIVE-OR circuit 260, of which the first input is provided by the status parameter N and the second input by one of the bits of the operation code of an 40 SUBSTITUTESHEET instruction depending on status parameters, the output of said EXCLUSIVE-OR circuit directing execution by said arithmetic and logic unit 24 of one of two possible operations determined by the value of said parameter N. 15. A data-processing system acording to Claim 14, wherein the two possible operations, the choice of which is determined by the value of said status parameter N, are addition and subtraction. 16. A device for reading data byte by byte in a data- processing system of the type comprising a selection register STAT, an address bus 16, and a data memory 22, of which the locations addressed by means of an address bus each contain a predetermined number of bytes; characterized by the fact that it includes a selection means 346, 350 which determines the end of each of said locations 344 at which the first byte of said predetermined number of bytes located in said selection register should be read in response to said selection bit B/L. 17. A read device according to Claim 16, in which said selection means includes a ones-complement circuit 346 connected as input to low-order lines AQ, A^ of said address bus, the other lines of which determine the address of said memory location 344, said ones-complement circuit inverting said low-order lines when said selection bit B/L is 1, and a multiplexer 350 determining at which part, the left end or right end of said memory location, the first byte of data should be read. 18. A read device according to Claim 17, in which each of said memory locations 344 contains 2 bytes, and said ones- complement circuit 346 is an EXCLUSIVE-OR circuit, one entry of which is said selection bit B/L and the other input is the low- order line AQ of the address bus 16, the output A' Q of said 41 SUBSTITUTESHEET EXCLUSIVE-OR circuit being inverted when said selection bit is equal to 1 and unchanged when said selection bit is equal to 0. 19. A read device according to Claim 17, in which each of said memory locations 344 contains 4 bytes and said ones- complement circuit 346 is formed by two EXCLUSIVE-OR circuits, of which one of the two inputs is one of the low-order lines A'Q, A'I of said address bus 16, and the second input is said selection bit B/L, the output A'Q, A'I of each of said EXCLUSIVE- OR circuits being inverted when said selection bit is equal to 1 and unchanged when said selection bit is equal to 0. 20. A data-processing system including a read device according to any of Claims 16-19 and also including an incrementer INC for incrementing the address of an index register X in the case of indirect addressing, the reading of data in memory being possible either in the mode starting with the high- order byte or in the mode starting with the low-order byte, due to said read device. 21. A device for writing data byte by byte in a data- processing system of the type comprising a selection register STAT, an address bus 16, a data bus 26, and a data memory 22, the locations of which addressed by means of an address bus each contain a predetermined number of bytes; characterized by the fact that it includes a selection means 356, 360 which determines the end of each of said locations 354 at which the first byte of said predetermined number of bytes, provided on said data bus 26 should be written in response to said selection bit B/L. 22. A write device according to Claim 21, in which said selection means includes a ones-complement circuit 356 connected as input to low-order lines AQ, A^ of said address bus 16, the other lines of which determine the address of said memory 42 SUBSTITUTESHEET location, said ones-complement circuit inverting said low-order lines when said selection bit is 1, and a demultiplexer 360 determining at which part, the left end or right end of said memory location 354, the first byte of data should be written in response to the output lines A Q , A^ of said ones-complement circuit. 23. A write device according to Claim 22, in which each of said memory locations 354 contains two bytes, and said ones- complement circuit 356 is an EXCLUSIVE-OR circuit, one entry of which is said selection bit B/L and the other input is the low- order line A Q of the address bus 16, the output A'Q of said EXCLUSIVE-OR circuit being inverted when said selection bit is equal to 1 and unchanged when said selection bit is equal to 0. 24. A write device according to Claim 22, in which each of said memory locations 354 contains 4 bytes and said ones- complement circuit 356 is formed by two EXCLUSIVE-OR circuits, of which one of the two inputs is one of the low-order lines AQ, A]_ of said address bus 16, and the second input is said selection bit B/L, the output A ' Q , A'χ of each of said EXCLUSIVE-OR circuits being inverted when said selection bit is equal to 1 and unchanged when said selection bit is equal to 0. 25. A data-processing system including a write device according to any of Claims 21-24 and also including an incrementer INC for incrementing the address of an index register X in the case of indirect addressing, the writing of data in memory can be done either in the mode starting with the high- order byte or in the mode starting with the low-order byte, thanks to said write device. 43 SUBSTITUTESHEET

Inventors: CHAUVEL GERARD, DENT PETER, WENZINGER YVES, CHAUVEL, GERARD, DENT, PETER, WENZINGER, YVES
Applicants: CHAUVEL GERARD, DENT PETER, TEXAS INSTRUMENTS FRANCE, TEXAS INSTRUMENTS INC, WENZINGER YVES, TEXAS INSTRUMENTS INCORPORATED
Application year: 1993
Main classification: G06F9
IPC codes: G06F9, G06F12, G06F15, G11C7, G11C8