Non-volatile memory cell with double polisilicon level

Abstract: Non-volatile memory cell with double level of polycrystalline silicon comprising a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

Description: Field of the invention The present invention relates to non-volatile memory cells with double level of polycrystalline silicon and in particular an electrically erasable non-volatile memory cell (FLASH EEPROM) designed for use in analog computing devices in the charge domain. Said devices are designed to process input signals in analog form to supply output signals again in analog form and are used in associative memories for pattern recognition systems, in associative memories for correction of digital data transmission errors, in D/A converters and neural networks. Prior art In the prior art said devices are provided by means of digital circuits. The use of digital circuits however requires converting the analog input signals into digital signals, processing the signals in digital form and reconverting said signals in analog form. The considerable circuit complexity of said devices is in contrast with the present tendency toward integrating an ever greater number of circuits on the same chip to obtain higher computing powers with low consumption and low power dissipation. The technical problem underlying the present invention is to make available to those skilled in the art a capacitive element with non-linear characteristic, programmable in analog mode, of very small size, such as to make possible the provision of analog computing devices with very high density occupying a particularly small integration area. A first example of a non volatile memory cell having a modified channel region is disclosed in IBM TECHNICAL DISCLOSURE BULLETTIN vol. 23, no. 4, 4 September 1980, NEW YORK US. To maximise current flow and electron heating, a programmable field effect transistor memory cell uses different channel widths between the source and drain, with parallel channel walls near source and drain assuring alignment insensitivity. The use of a staggered channel in an electronically programmable read only memory (EPROM) or an electronically alterable read only memory (EAROM) reduces the voltage required for programming because current crowding at the drain enhances the space charge of the mobile electrons. For a given drain voltage, the electric field that heats channel electrons increases as this space charge increases. Alternatively, the same electric field strength can be produces by lower drain voltage for increasing space charge. A second example of a modified non volatile memory cell is disclosed in Patent Abstracts of Japan, vol. 8, 181 and JP-A-59 074 679 (Mitsubishi Denki K.K.) 27 April 1984. The purpose of that application is to contrive to improve the write efficiency by enhancing the injection efficiency of hot electrons by enlarging a channel width on the drain side. Summary of the invention This problem is solved by a non-volatile memory cell with double level of polycrystalline silicon of the type described above and defined in the characterising part of the claims which follow this description. The characteristics and advantages of the device in question are set forth in the description of a preferred embodiment thereof given below by way of nonlimiting example with reference to the annexed drawings. Brief description of the drawings In the drawings: FIG. 1 shows the ideal characteristic curve between the control gate voltage (Vg) and the charge (Q) accumulated in the control gate of a hypothetical FLASH EEPROM cell designed for use in analog computing devices in the charge domain, FIG. 2 shows the real characteristic curve between the control gate voltage (Vg) and the charge (Q) accumulated in the control gate of a FLASH EEPROM cell, FIG. 3 shows the real characteristic curve between the control gate voltage (Vg) and the charge (Q) accumulated in the control gate of a standard FLASH EEPROM cell in accordance with the present invention, FIG. 4 shows a cross section of the conventional structure of a FLASH EEPROM memory cell showing the principal capacitances present, FIGS. 5 and 6 show a plan view and a cross section view respectively of a standard FLASH EPROM memory cell, and FIGS. 7 and 8 show a plan view and a cross section view respectively of a FLASH EEPROM memory cell in accordance with the present invention. Detailed description With reference to FIGS. 5 and 6 showing a FLASH EEPROM memory cell of known type and designated as a whole by 20 there can be distinguished a source region 28 and a drain region 21 formed in a substrate of semiconductor material and which define a channel region 24 between them. 25 designates the contact of the drain region 21. Over the channel zone 24 is a floating gate 23 which is separated from the substrate by a thin dielectric layer 26. Over the floating gate 23 is a control gate 22 separated from the gate 23 by a second dielectric layer 27. The channel region 24 termed also active area between the source region 28 and drain 21 region displays over the threshold a capacitance Cch toward the floating gate designated symbolically in FIG. 4 where are shown the principal capacitances of a generic FLASH EEPROM cell. FIG. 4 also shows two so-called "overlap" capacitances Cfs and Cfd between the floating gate 23 and the source region 28 and between the floating gate and the drain region 21 respectively. FIGS. 7 and 8 show a FLASH EEPROM memory cell in accordance with the present invention designated as a whole by 30. A source region 38 and a drain region 31 whose contacts are designated by 35 and 39 are defined in the substrate of semiconductor material. The principal difference between the cell 20 and the cell 30 lies in the configuration of the channel region 34 which extends not only into the zone directly between the source region 38 and drain region 31 but also in two lateral zones adjacent to said zone and, like it, beneath the floating gate 33 and the control gate 32. The two gates 32, 33 have greater dimensions than those of the cell 20 because they must guarantee cover of the active channel region 34 widened in accordance with the present invention. In addition, to hold unchanged the values of the two overlapping capacitances between floating gate and source region and between floating gate and drain region, increasing the channel capacitance value, the active channel region 34 displays a cross configuration in the preferred embodiment. Consequently even the length L' of the channel 34 can be greater than the length L of the channel 24 of the cell 20. But this does not compromise the normal programmability of the cell. The channel region is defined in the substrate by thick oxide regions in conformity with lithographic techniques known to those skilled in the art. In the analog computing devices in the charge domain which use non-volatile memory cells said cells are used as condensers with non-linear characteristics by measuring the quantity of charge accumulated by a cell when it is subjected to a certain potential difference. These non-linear characteristics of the cell derive from the same MOS field effect transistor structure of the memory cell. In MOS devices the charge accumulated in the channel is almost null when the gate voltage (Vg) is lower than the threshold voltage (Vt) of the device and, in a first approximation, is linear in (Vg-Vt) when the gate voltage (Vg) is greater than the threshold voltage (Vt). FIG. 1 shows the ideal curve of the characteristic between the gate voltage (Vg) and the accumulated charge (Q). The real characteristic shown in FIG. 2 of a known non-volatile memory cell of the FLASH EEPROM type differs from the ideal one by the presence of some parasitic capacitances. FIG. 4 shows schematically the conventional structure of a FLASH EEPROM cell with accentuation, as mentioned above, of the principal capacitances present. It can be seen that the channel capacitance (Cch) which represents the "signal" of the system, when the source region (28) and drain region (21) are equipotential, is in parallel with the two "overlap" capacitances between floating gate and source (Cfs) and between floating gate and drain (Cfd). In this manner the induced charges on Cfs and Cfd represent an "error" signal for the system. The fourth capacitance present (Cgf) between control gate (22) and floating gate (28) is in series with the other three capacitances. In a normal FLASH EEPROM cell the channel capacitance (Cch) is of the same order of magnitude as the parallel of the two overlapping capacitances and, as may be seen from the real characteristic curve in FIG. 2, this causes considerable shifting of the resulting characteristic curve from the ideal characteristic of FIG. 1. Since it is not possible to lower the capacitance values of the two overlap zones without compromising cell operation, the solution of the problem in accordance with the present invention consists of increasing the capacitance of the channel region and consequently increasing the ratio of the channel region capacitance (signal) to the overlap parasitic capacitance of source and drain (error). In accordance with the present invention the capacitance of the channel region is increased as shown in FIG. 7 and FIG. 8 by extending the channel region area perpendicularly to the source-drain direction in two side zones also extending under the floating gate and the control gate, which are widened. This solution permits achieving a characteristic curve between control gate voltage (Vg) and charge accumulated in the control gate (Q) of the type shown in FIG. 3 which approximates the ideal characteristic curve of FIG. 1. As in the other memory cells of the same type, by varying the quantity of charge accumulated in the floating gate in the cell programming phase it is possible to vary continously the threshold voltage (Vt) and hence the characteristic curve of the cell. It is clear that modification, integration and replacement of elements can be made to the embodiment described above by way of nonlimiting example without thereby going beyond the protective scope of the following claims.

Claims: Non-volatile memory cell with double level of polycrystalline silicon integrated monolithically in a substrate of semiconductor material and comprising a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) defined in said levels of polycrystalline silicon and separated by at least one layer of dielectric material (37) and both extending at least on the channel region which is covered by a thin layer of dielectric material (36) and characterised in that the width of the channel region is in at least one part greater than any of the parts of the channel region adjoining the source and drain regions. Memory cell in accordance with claim 1 characterised in that the width of the channel region is not less in some part than the width of the parts of the channel region adjoining the source and drain regions. Memory cell in accordance with claim 1 characterised in that the area of the channel region is greater than that of a substrate region between the source and drain regions whose width is at all points equal to that of the two parts of the channel region adjoining the source and drain regions. Memory cell in accordance with claim 1 characterised in that the area of the channel region is greater than that of a substrate region between the source and drain regions whose width changes in a constant and uniform manner between the two parts of the channel region adjoining the source and drain regions.

Inventors: KRAMER ALAN, SABATINI MARCO, KRAMER, ALAN, SABATINI, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H01L29
IPC codes: H01L29, H01L21