Semiconductor integrated circuit and IC card using the same

Abstract: A semiconductor integrated circuit comprises a writable non-volatile memory 35; a writing voltage-generating circuit for generating a writing voltage and supplying it to the non-volatile memory; an oscillating circuit 16 generating a first clock signal and supplying it to the writing voltage-generating circuit; a timer 12 measuring a time required for applying the writing voltage to the non-volatile memory; a control circuit 11 controlling the writing to the non-volatile memory; and a switching device 18 for selecting either the first clock signal generated in the oscillating circuit, or a second clock signal to be input externally in accordance with a control signal from the control circuit, and supplying the selected signal to the timer and the control circuit as a clock.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to an IC card connected to an external device for executing data processing and a semiconductor integrated circuit used for the same. DESCRIPTION OF THE RELATED ART The construction of a conventional IC card 20 is shown in Fig. 6. A ROM 24, an EEPROM 25 and a RAM 26 are connected via a system bus 22 to a CPU 21 executing calculation and controlling operations required for data processing. The ROM 24 stores a program for executing various functions used by a card user. The EEPROM 25 writes individual information, or the like, of a card user. The RAM 26 temporarily stores the data required for data processing. An input/output (I/O) circuit 27 executing data I/O processing to communicate with an external unit is also connected to the system bus 22. The conventional IC card also includes terminals such as a positive-power supply input terminal P1, a negative-power supply ground terminal P2, a reset terminal P3 for receiving a reset signal to initialize the CPU 21, a clock terminal P4 for receiving an external clock signal Xin, and an I/O terminal P5 for executing data I/O processing. A block diagram of the EEPROM 25 is shown in Fig. 7. A memory array 1 has a plurality of word lines 1a from an X decoder 2 to a plurality of program voltage switches (VppSWs)7 and a plurality of bit lines 1b from a Y gate 3 to a plurality of program voltage switches (VppSWs)8. Each of memory cells 1c is connected at the intersection of the word line 1a and the bit line 1b. The control circuit 11 is a sequential circuit having four states such as READY, LATCH, ERASE and WRITE by using an internal clock signal  1 of a machine cycle of the CPU 21 as a clock. The READY state is not a writing state of the control circuit 11. The control circuit 11 outputs a latch signal, an erase signal and a write signal in the states of LATCH, ERASE and WRITE, respectively. Detecting that writing is to be executed from the CPU 21 into the EEPROM 25, the control circuit 11 goes into the LATCH period and sequentially stores the data supplied from the CPU 21 into a column latch 9. The control circuit 11 also goes into the ERASE period in response to a write instruction from the CPU 21, and then, to the WRITE period, and is finally completed. In accordance with the internal clock signal  1 generated by the CPU 21, the timer 12 measures the time required from latching the previous data to the following data and the time required from latching the data to inputting a write instruction. When the measured time exceeds a predetermined time out, the control circuit 11 determines it is abnormal, thus nullifying and completing the previous operation. When the control circuit 11 generates an erase signal and a write signal, it also outputs a Vpp generating signal to the charge pump 10. When the Vpp generating signal is input into the charge pump 10 from the control circuit 11, the charge pump 10 raises the Vcc power supply voltage by an external clock signal Xin which is input via the clock terminal P4 and generates the high voltage Vpp for the use of the writing so as to supply it to the VppSWs 7 and 8. According to an address signal stored in an address latch 13, the X decoder 2 and the Y decoder 4 select the word line 1a and the Y gate 3, respectively. A signal from the CPU 21 is input into the selected Y gate 3 via a data bus and a driver 5. The signal from the Y gate 3 is connected to the data bus via a sense amplifier 6. The VppSW 7 supplies the high voltage Vpp for the use of the writing supplied from the charge pump 10 to the word line 1a selected by the X decoder 2. The VppSW 8 supplies the high voltage Vpp to the respective bit lines 1b on the basis of information stored in the column latch 9. The writing data from the driver 5 is stored in the column latch 9 by way of the selected bit line 1b and the VppSW 8. In general, since an EEPROM requires a long write time, a plurality of pieces of data to be written are stored in the column latch 9 and written in the memory cells 1c on the selected word lines 1a, simultaneously, thereby effectively reducing the write time. A gate 15 generates a signal for selecting an EEPROM in accordance with the address signal from the CPU 21. A rise control circuit 14 for raising the high voltage Vpp slowly operates in accordance with the internal clock signal  1 generated from the CPU 21 and outputs a rise control signal to the charge pump 10. The above-described prior art can be found in Japanese Patent Laid Open No. 64-52298 filed on August 21, 1987; Japanese Patent Laid Open No. 64-53400 filed on August 25, 1987; Japanese Patent Laid Open No. 1-192099 filed on January 27, 1988; and Japanese Patent Laid Open No. 3-181096 filed on December 8, 1989. However, the conventional EEPROM has the following problems. As stated above, the external clock signal Xin which is input via the clock terminal P4 for the operation of the CPU 21 and supplied to the CPU 21 is also used as a clock of the charge pump 10 of the EEPROM 25. Hence, when the frequency of the external clock signal Xin is lowered in order to vary the operation speed of the CPU 21, the high voltage Vpp for the use of the writing generated from the charge pump 10 is also lowered, thus inhibiting a correct operation. Also, the frequency of the internal clock signal  1 generated in the CPU 21 is changed as the frequency of the external clock signal Xin is changed. Further, the write time determined by the timer 12 operating according to the internal clock signal  1 is inevitably changed, thus making it difficult to ensure the optimal write time for guaranteeing the reliability of the memory cell 1c and for executing sufficient writing. European Patent Publication No. EP 0374936 discloses the features of the preamble of claim 1, i.e. a non-volatile semiconductor memory system which uses two clocks. A selector switches between an internally generated clock and an externally generated clock. Both of these clocks operate at the same frequency. SUMMARY OF THE INVENTION Accordingly, in order to overcome the above drawbacks, an object of the present invention is to provide a semiconductor integrated circuit which is capable of ensuring a correct operation and an optimal write time regardless of the frequency of a clock signal input from an external unit and to provide an IC card using the same. In order to achieve the above objects, according to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a writable non-volatile memory; a writing voltage-generating circuit for generating a writing voltage and supplying it to said non-volatile memory; an oscillating circuit generating a first clock signal and supplying it to said writing voltage-generating circuit; a timer for controlling a time required for applying the writing voltage generated in said writing voltage-generating circuit to said non-volatile memory; a control circuit controlling the writing to said non-volatile memory; and switching means for selecting either of the first clock signal generated in said oscillating circuit and a second clock signal to be input externally in response to a control signal from said control circuit, thereby supplying the selected signal to said timer and said control circuit as a clock, characterized in that said control circuit outputs a first control signal or a second control signal to said switching means, the first control signal being generated when the writing voltage is supplied to said non-volatile memory by said writing voltage-generating circuit and the second control signal being generated when the writing voltage is not supplied to said non-volatile memory and wherein said switching means selects the first clock signal and supplies it to said timer and said control circuit when the first control signal is input from said control circuit to said switching means, and said switching means selects the second clock signal and supplies it to said timer and said control circuit when the second control signal is input into said switching means. According to a second aspect of the present invention, there is provided an IC card comprising: a CPU operating according to a second clock signal and executing data processing; a ROM storing a program for operating the CPU; a RAM temporarily storing data; an input/output circuit executing data input/output processing to communicate with an external unit; and a writable non-volatile memory according to the first aspect of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an IC card of one embodiment according to the present invention; Fig. 2 is a block diagram showing the construction of an EEPROM used for the IC card shown in Fig. 1; Fig. 3 is a timing chart indicating the operation of the EEPROM shown in Fig. 2; Fig. 4 shows the state transition of a control circuit used for the EEPROM shown in Fig. 2; Fig. 5 is a block diagram showing an EEPROM according to another embodiment; Fig. 6 is a block diagram showing a conventional IC card; and Fig. 7 is a block diagram showing the construction of an EEPROM used for the IC card shown in Fig. 6. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the accompanying drawings. Reference will first be made to an IC card shown in Fig. 1. A ROM 24, an EEPROM 35 and a RAM 26 are connected via a system bus 22 to a CPU 21 executing calculation and controlling operations required for data processing. An input/output (I/O) circuit 27 executing data I/O processing to communicate with an external unit is also connected to the system bus 22. The IC card of the present invention includes terminals such as a positive-power supply input terminal P1, a negative-power supply ground terminal P2, a reset terminal P3 for receiving a reset signal to initialize the CPU 21, a clock terminal P4 for receiving an external clock signal Xin, and an I/O terminal P5 for executing data I/O processing. A block diagram of an EEPROM 35 is shown in Fig. 2. A memory array 1, an X decoder 2, a Y gate 3, a Y decoder 4, a driver 5, a sense amplifier 6, VppSWs 7 and 8, a column latch 9, a charge pump 10, a control circuit 11, a timer 12, an address latch 13 and a rise control circuit 14 are similar components to those shown in Fig. 7 having the same reference numerals. The charge pump 10 and a clock signal-generating circuit 17 are connected to an oscillating circuit 16 which is further connected to the control circuit 11. The control circuit 11 and the timer 12 are connected to the clock signal-generating circuit 17 via a switching circuit 18. The rise control circuit 14 is also connected to the clock signal-generating circuit 17. The oscillating circuit 16 oscillates an OSC signal according to an oscillating control signal generated from the control circuit 11 and supplies it to the charge pump 10 and the clock signal-generating circuit 17 which generates a clock signal  2 according to the OSC signal generated from the oscillating circuit 16. The switching circuit 18 selects either of the internal clock signal  1 generated by the CPU 21 and the clock signal  2 generated by the clock signal-generating circuit 17 according to the oscillating control signal generated from the control circuit 11 and supplies the selected signal to the control circuit 11 and the timer 12. A gate 19 generating a selection signal so as to access the EEPROM 35 inputs address signals A13 - A15 and an SYNC signal which is generated by the CPU 21 when it reads an instruction word. In this embodiment, when an SYNC signal is generated, a selection signal is not generated from the gate 19, and thus, an instruction word cannot be read from the EEPROM 35, thereby inhibiting the EEPROM 35 from storing a program. The operation of this embodiment will now be explained with reference to a timing chart in Fig. 3 and the state transition shown in Fig. 4. The control circuit 11 outputs a high-level oscillation control signal when it is in either of the states of ERASE or WRITE. Then, an OSC signal is generated from the oscillating circuit 16 and the switching circuit 18 selects the clock signal  2 generated by the clock signal-generating circuit 17 and supplies it to the control circuit 11 and the timer 12. When the CPU 21 writes into the EEPROM 35 in the READY state of the control circuit 11, a high-level selection signal is generated from the gate 19, thereby changing the state of the control circuit 11 from READY into LATCH. At this time, the CPU 21 executes writing for the number of times required for the same page. The address and date to be written are latched in the address latch 13 and in the column latch 9, respectively. The timer 12 is cleared every time the CPU 21 writes a new address or data. When a predetermined time required for executing the following writing by the CPU 21, that is, for latching the following data in the column latch 9, reaches, for example, 0.4ms, the state of the control circuit 11 is changed into READY and the data latched by the previous writing is nullified. Or the control circuit 11 may be adapted to change into the ERASE state. A writing instruction signal for instructing the execution of writing is input into the control circuit 11 from the CPU 21, thereby changing the state of the control circuit 11 into ERASE and raising an oscillation control signal, a Vpp generating signal and an erase signal to a higher level. Due to such a high-level oscillation control signal, an OSC signal is generated from the oscillating circuit 16 and the switching circuit 18 selects the clock signal  2 generated by the clock signal-generating circuit 17 and supplies it to the control circuit 11 and the timer 12. The clock signal  2 is supplied to the rise control circuit 14 from which a rise control signal is output to the charge pump 10. The OSC signal from the oscillating circuit 16 and the high-level Vpp generating signal from the control circuit 11 are input into the charge pump 10, thereby generating a high voltage Vpp used for writing according to the rise control signal. The control circuit 11 starts to count the erase time by the timer 12, and after a lapse of a predetermined time, for example, 5ms, it is changed into the WRITE state, thus dropping the erase signal to a lower level and raising the write signal to a higher level. The control circuit 11 further starts to count the write time by the timer 12, and after a lapse of a predetermined time, for example, 5ms, it is then changed into the READY state, thereby dropping the write signal into a lower level. Likewise, the oscillation control signal and the Vpp generating signal are dropped to a lower level, whereby the oscillating circuit 16 stops oscillating and the switching circuit 18 selects the internal clock signal  1 generated by the CPU 21 and supplies it to the control circuit 11 and the timer 12. When the oscillating circuit 16 is actuated, and thus, the control circuit 11 is operated by the clock signal  2 from the clock signal-generating circuit 17, a clock signal may be inhibited from being input into the clock terminal P4 from the external unit, thereby halting the CPU 21 and further achieving power-saving. The present invention may be modified as follows. As illustrated in Fig. 5, instead of the control circuit 11, a control register 31 may be arranged to be able to be directly set/reset by the CPU 21, thereby outputting an oscillation control signal and a Vpp generating signal to the oscillating circuit 16 and the charge pump 10, respectively. In this case, the timer 12 is also directly controlled by the CPU 21. Thus, since the control register 31 and the timer 12 are directly controlled by the CPU 21, the switching circuit 18 shown in Fig. 2 is not required. In the above embodiments, although an EEPROM is used as a memory, another kind of writable non-volatile memory may be used.

Claims: A semiconductor integrated circuit comprising: a writable non-volatile memory (1); a writing voltage-generating circuit (10) for generating a writing voltage and supplying it to said non-volatile memory; an oscillating circuit (16) generating a first clock signal and supplying it to said writing voltage-generating circuit; a timer (12) for controlling a time required for applying the writing voltage generated in said writing voltage-generating circuit to said non-volatile memory; a control circuit (11) controlling the writing to said non-volatile memory; and switching means (18) for selecting either of the first clock signal generated in said oscillating circuit and a second clock signal (1) to be input externally in response to a control signal from said control circuit, thereby supplying the selected signal to said timer and said control circuit as a clock, characterized in that said control circuit outputs a first control signal or a second control signal to said switching means, the first control signal being generated when the writing voltage is supplied to said non-volatile memory by said writing voltage-generating circuit and the second control signal being generated when the writing voltage is not supplied to said non-volatile memory and wherein said switching means selects the first clock signal and supplies it to said timer and said control circuit when the first control signal is input from said control circuit to said switching means, and said switching means selects the second clock signal and supplies it to said timer and said control circuit when the second control signal is input into said switching means. A semiconductor integrated circuit according to claim 1 further comprising a latch circuit (9) temporarily latching and storing a plurality of pieces of data in order to write said plurality of pieces of data at the same time in a plurality of memory cells (1c) connected to a corresponding word line of said non-volatile memory, said timer measuring the time interval for which pieces of data are stored by said latch circuit, said control circuit nullifying the previous data stored in said latch circuit when the time interval of the data latch measured by said timer exceeds a predetermined value. A semiconductor circuit according to claim 1 wherein said non-volatile memory is a memory array of an EEPROM. An IC card comprising: a CPU (21) operating according to a second clock signal and executing data processing; a ROM (24) storing a program for operating said CPU; a RAM temporarily storing data; an input/output circuit (27) executing data input/output processing to communicate with an external unit; and a semiconductor integrated circuit as claimed in any one of the claims 1 to 3. An IC card according to claim 4 wherein said CPU inhibits the input of the second clock signal from the external of said IC card when said switching means selects the first clock signal generated in said oscillating circuit and the first clock signal is supplied to said timer and said control circuit.

Inventors: YAMAGUCHI ATSUO, YAMAGUCHI, ATSUO, YAMAGUCHI, ATSUO, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: G06F15
IPC codes: G11C16, G06K19, G06F15