Trenched DMOS transistor fabrication using six masks

Abstract: A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a method for fabricating a trenched DMOS transistor using six masking steps, resulting in a transistor having narrow trenches, shallow diffusions, and formed using relatively few process steps. Description Of The Prior Art DMOS transistors are well known as a type of MOSFET (metal on semiconductor field effect transistor) using diffusions to form the transistor regions, with a typical application being as a power transistor. Such devices enjoy widespread use in such applications as automobile electrical systems, power supplies, and power management applications. Many different processes have been used for the fabrication of power MOSFET devices over the years; these are generally deep diffusion processes. It is also well known to form such transistors having a trench in the substrate, the trench being lined with a thin oxide layer and filled with a conductive polysilicon to form the transistor gate structure. Prior art trenched DMOS transistors have the shortcoming that typically it takes a fairly large number (such as eight or nine) fabrication masking steps to define the various transistor regions, including the tubs in which the active transistor regions are formed, the body region of the transistor, the source region of the transistor, the body contact regions, each of which are separate diffusions, and the termination structures, i.e. field plates and field rings. Additional masking steps are used to define the oxide layers and polysilicon portions of the transistor. Each additional masking step requires a mask alignment and thus results in the possibility of alignment error, undesirably reducing yield. Additionally, the many process steps which include temperature cycles tend to result in unwanted diffusion of certain of the implanted ions, thus undesirably altering the lateral extent and/or depth of various of the diffused regions. Thus there is a need for transistor fabrication processes using relatively few masks. It is also desirable in fabrication of such a device to eliminate the polysilicon ("poly") stringer problem. Polysilicon stringers are typically formed when a layer of polycrystalline silicon ("polysilicon") is deposited over for instance an oxide layer which includes a step structure. Subsequent etching down of the polysilicon layer results in a portion of the polysilicon remaining adjadcent to the step, since the polysilicon layer is thickest at that point. This "stringer" portion causes significant performance problems in the resulting transistor. French Patent Application No. 2,647,596 is directed to a trenched MOS transistor of a conventional type. A publication "Optimum Low-Voltage Silicon Power Switches Fabricated Using Scaled Trench MOS Technologies" by K. Shenai International Electron Devices Meeting, IEDM 1990, pages 793-797 is directed to a vertical scaled trench power MOSFET. Optimized trench etching and trench sidewall cleaning processes and a novel trench polysilicon planarization process are disclosed. SUMMARY OF THE INVENTION In accordance with the invention, a trenched DMOS transistor is formed having relatively narrow and relatively shallow trenches in one embodiment. The associated transistor active regions are relatively shallow diffusions. Only six masking steps are required because one mask is used to define both the deep body and the active areas of the transistor, i.e. establish the location of the tubs, and also to determine where local oxidation is to take place defining the field oxide portions of the transistor. Thus both the prior art first mask which is typically used to define the tub region and the prior art second mask which is used to define the field oxidation regions are combined into one local oxidation of silicon (LOCOS) masking step. Additionally, the fabrication process is simplified by eliminating any dedicated photoresist masking step for definition of both the body region and the source regions of the transistor. Instead, these regions are defined by the earlier active region mask which is patterned to define portions of the body regions and source regions and further by implanting and diffusing the body regions and source regions subsequent to gate trench formation, thus using the gate trench sidewalls partly to define the lateral extent of the source regions and body regions. This is in contrast to the prior art which instead uses a dedicated photoresist mask layer for defining both the body regions and the source regions. Implanting of the body and source regions after formation of the trenches advantageously provides better control of the channel length of the completed transistors. Forming the body regions relatively late in the process advantageously exposes the body regions to fewer temperature cycles during fabrication and hence allows more accurate definition of the depth of the body diffusions. Additionally, formation of the trench prior to formation of the body regions advantageously allows easier repair of etch damage to the trench sidewalls. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1a through 1j show in cross section a sequence of steps to form a transistor in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION The present invention is to be understood in the context of a copending and commonly owned patent application, namely U.S. Patent Application Serial No. 07/881,589 filed May 12, 1992, issued April 19, 1994 as U.S. Patent No. 5,304,831, entitled "Low On-Resistance Power MOS Technology", inventors Hamza Yilmaz et al., which describes inter alia a method for fabricating a DMOS transistor using five masking steps. Advantageously, the structure and method in accordance with the invention eliminate masking steps required in prior art processes, and may dispense with formation of a thick gate oxide, and yet still in one embodiment achieves breakdown voltage far in excess of that of the active cell transistor portion of the transistor. These characteristics are especially beneficial when high breakdown voltages are required and shallow junctions are required in accordance with high cell density. The active transistor cells are square or any other convenient geometry. A process in accordance with the invention and using six masking steps is described hereinafter. In Figure 1a an N-channel process in accordance with the invention uses an N- doped epitaxial layer 100 having a resistivity of for example 0.85 to 1 ohm-cm formed on an N+ doped silicon substrate having a resistivity of for example 0.001 to 0.005 ohm-cm and which is 5 to 10 microns (micrometers) thick (not shown). The substrate is about 500 µm thick. A thin layer of silicon dioxide 102 30 nm (300Å) to 50 nm (500Å) thick is thermally grown on the principal surface of the epitaxial layer 100 and a mask layer of silicon nitride 104 is deposited thereon. Mask layer 104 is conventionally patterned and etched. Then boron is predeposited by using the boron nitride process or by implanting boron at an energy of 40 to 60 KeV and a dose of 2 x 10 13 to 1 x 10 16 /cm 2 through the mask layer 104 and driven in to form P+ deep body regions 106, 108 which are about 2 to 3 microns deep and having a final concentration at the principal surface of 1 x 10 16 to 2 x 10 19 /cm 3 , and similar P+ field rings (termination structures) 110, 112, 114. Then local oxidation (LOCOS) 118 of silicon to a thickness of 500-800 nm (5,000 to 8,000Å) in Figure 1b is followed by stripping of the nitride mask layer 104 to define both the active transistor cells and the device termination portion. (It is to be understood that in Figures la to lj, the device termination region is located at the right hand side of the figures and the central active cell portion of the transistor is at the left hand portion of the figures. Also, the process steps are shown schematically and not to scale.) Then in Figure 1c an LTO (low temperature oxide) second mask layer (not shown) is conventionally deposited and patterned, and trenches 120, 122, 124, 126 are each formed by anisotropic reactive ion dry etching to a depth of 1.5 to 3 micrometer (microns) and a width of 1 to 2 micrometer (microns). Trenches 120, 122, 124 serve as the gate electrode trenches and trenches 124, 126 separate the field rings from adjacent structures. After the trench walls and corners are smoothed by an isotropic plasma round hole etch and a sacrificial oxide growth and subsequent stripping of the sacrificial oxide, the gate oxide layer 130 is conventionally grown on the sidewalls of the trenches 120, 122, ..., 126 to a thickness of 40-80 nm (400-800Å). Then in Figure ld the trenches are planarized by the deposition of a layer of polycrystalline silicon 132 which is at least as thick as the width of each trench. This relatively thick polysilicon layer 132 is partially dry etched away (without a mask) leaving a thickness of 0.5 micrometer (microns). By protecting the principal surface with photo resist (not shown), the substrate back side polysilicon and oxide layers are removed by wet chemical etch. The remaining polysilicon 132 is then doped to less than 2 ohm/unit area (ohm/square). Then masking of polysilicon 132 and a second polysilicon etching is performed, resulting in the structure of Figure 1d defining windows for subsequent processing. The use of the LOCOS oxide process eliminates the prior art "poly stringer" problem by reducing the oxide step height. This is followed in Figure le by a blanket boron P-body implant and diffusion at an energy of about 60 KeV and dose of 3 x 10 13 to 4 x 10 13 /cm 2 , providing a final surface concentration of about 2 x 10 17 /cm 3 forming doped regions 134, 136, 138. Then a blanket N+ arsenic source implant and diffusion are performed at an energy of 60 to 120 KeV at a dosage of 1 x 10 15 to 1 x 10 16 /cm 2 to achieve a final surface concentration of 5 x 10 19 /cm 3 in Figure lf forming regions 140, 142. The N+ source junction 140, 142 depth is about 0.5 microns. Then in Figure 1g a layer of boro-phosphosilicate glass (BPSG) 146 is conventionally deposited to a thickness of about 1.35 microns over the entire structure. Then in Figure lh BPSG layer 140 is masked and patterned to define the electrical contact openings 150, 152, 154, 156 to the transistor structure. The BPSG layer 140 is then conventionally reflowed to smooth the corners. Then in Figure li a layer of metal 160 (e.g. aluminum or aluminum plus 1% silicon) is deposited such as by sputtering over the entire structure and etched using a conventional patterned metal mask layer. The polysilicon 132a at the edge termination is also etched away in this same step. In this wet metal etch and silicon residue removal etching step, the metal layer 160 is etched away in the termination region and this step also etches away unneeded portions 132a of the polysilicon layer in this region. Thus no separate masking layer is needed to remove unneeded polysilicon 132a in this step. Then in Figure 1j a passivation layer 162 such as PSG or plasma nitride is conventionally deposited and by a mask step bonding pad holes (not shown) to contact the gate and source area are opened therethrough. As will be recognized, six masking steps are thereby utilized in one embodiment of the fabrication process described in Figures 1a to 1j of the present invention. These six masking steps are as follows: 1) a deep body P+ and LOCOS masking step in which openings are formed in layer 102 as shown in Figure la through which a P+ region is doped and LOCOS 118 is grown; 2) a trench masking step in which a portion of photoresist is formed to define the trenches 120, ..., 126 shown in Figure 1c; 3) a polysilicon masking step in which portions of photoresist are used to protect and thereby to form the portions of polysilicon layer 132 shown in Figure 1d; 4) a contact hole masking step in which portions of a BPSG layer 146 are removed to form a contact to the P+ regions and to form a contact to the polysilicon in trench 124 of Figure 1h. 5) a metal masking step in which portions of a metal layer 160 are removed to form the metal source electrode 160(a), the metal gate finger 160(b), of Figure 1i; and 6) a pad masking step in which portions of passivation layer 162 are removed to expose portions of a gate bonding pad and source bonding pad. It is to be understood that the above-described process is for fabricating an N-channel vertical DMOS transistor device as shown. By reversal of the various polarities to the opposite type, a P-channel vertical DMOS transistor structure may also be formed. Also, with reference to the structure of Figure 1j, the field rings 112, 114 are separated by insulated trench 126, thus allowing the field rings to be closely spaced together and hence conserving chip surface area. More field rings can be formed in a similar way. Trench 126 is filled with polysilicon that is electrically floating. Trench 124 is also filled with polysilicon and is electrically connected to the gate finger electrode connected in turn (outside the plane of Fig. 1i) to the polysilicon which is filling trenches 120, 122. The drain electrode is conventionally formed on the back side (not shown) of the substrate. The area immediately to the right of trench 122 has no active (source or body) regions and hence serves as a dummy cell adjacent to the termination structures; this dummy cell can be dispensed with in one embodiment. Also, the above described process can be implemented in a transistor having a termination other than that described herein.

Claims: A method for forming a trenched field effect transistor comprising: providing a semiconductor substrate (100) having a principal surface and being of a first conductivity type; forming a patterned mask layer (104) on the principal surface; doping semiconductor regions (106, 108, 110, 112, 114) of a second conductivity type in portions of the substrate exposed by the mask layer (104), thereby forming deep body regions of the transistor; growing an oxide layer (118) on portions (102) of the principal surface exposed by the mask layer (104); forming a plurality of trenches (120, 122, 124, 126) in the substrate (100) and located between the previously formed doped regions (106, 108, 110, 112, 114); forming a layer of conductive material (132) in the trenches (120, 122, 124, 126) and over at least a part of the oxide layer (118), the portion of the conductive material layer (132) in the trenches being a gate of the transistor; after forming the trenches, forming doped first regions (134, 136, 138) of the second conductivity type in the substrate (102) extending from the unmasked portions of the principal surface into the substrate; after forming the trenches, forming doped second regions (140, 142) of the first conductivity type extending from the unmasked portions of the principal surface into the substrate, the first and second doped regions respectively being body and source regions of the transistor; wherein the trenches (120, 122, 124, 126) and oxide layer (118) are used as masks for the subsequent formation of the body and source regions; forming a patterned insulating layer (146) overlying the principal surface and the conductive material layer (132); and forming a patterned interconnect layer (160a, 160b) overlying the principal surface and over the patterned insulating layer (146) and contacting the deep body, body, and source regions, and the gate electrode. The method of claim 1, wherein the step of growing an oxide layer (118) comprises locally oxidizing the exposed portions of the principal surface to form a layer in the range of about 500 to about 800 nm thick. The method of Claim 1, wherein the step of forming a plurality of trenches comprises: anisotropically etching a plurality of U-shaped trenches; smoothing the trench walls and rounding the trench corners by an isotropic plasma dry etch; growing a layer of sacrificial oxide on the sidewalls of the trenches; and removing at least part of the layer of sacrificial oxide. The method of Claim 1, wherein the depth of the trenches is in the range of about 1.5 to about 3 micrometer (microns). The method of claim 1, wherein the step of forming a layer of conductive material (132) comprises: depositing a layer of non-conductive material in the trenches and overlying the principal surface; etching away a portion of the deposited layer; doping remaining portions of the deposited layer thereby rendering the deposited layer conductive; forming a patterned mask layer over the doped deposited layer portions; and etching away those portions of the doped deposited layer exposed by the patterned mask layer, wherein the trenches are filled with the doped deposited layer, and the doped deposited layer is over the oxide layer only in a termination region of the transistor. The method of Claim 5, wherein the step of forming a patterned interconnect layer (160a, 160b) comprises: depositing a layer of metal overlying the principal surface and the patterned insulating layer (146); forming a patterned mask layer over the layer of metal; etching away those portions of the metal layer exposed by the patterned mask layer, and further etching away in the same step that portion of the doped deposited layer in the termination region that is not overlain by the patterned insulating layer.

Inventors: CHANG MIKE F, HO YUEH-SE, HSHIEH FWU-IUAN, KWAN SZE-HON, OWYANG KING, CHANG, MIKE F., HO, YUEH-SE, HSHIEH, FWU-IUAN, KWAN, SZE-HON, OWYANG, KING
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L29