Amplifier and method for detecting the BEMF of a coil of a polyphase sensorless DC motor

Abstract: A circuit and method for detecting when the back emf of a motor coil passes a predetermined level includes circuitry for providing a voltage proportional to the back emf of the motor coil, and circuitry for providing a voltage proportional to a reference potential. A first bias voltage is added to the voltage proportional to the back emf to produce a first added voltage, and a second bias voltage os added to the reference potential when the back emf of the motor coil is expected to change in a predetermined direction to produce a second added voltage. A comparator produces an output change when the first added voltage becomes larger than the second added voltage at the predetermined level.

Description: This invention relates to improvements in circuitry that can be used in driving polyphase dc motors, and still more particularly to methods and apparatus for developing information concerning the crossing of a reference voltage by the back emf (bemf) of non-selected or floating field coils for controlling a spinning rotor of a polyphase dc motor, and still more particularly to methods and apparatus for detecting the reference voltage crossings of the back emf of floating field coils for controlling coil commutation signals, even at low motor speeds. Electronic Components and Applications, Vol. 10, No. 1, pp 2-10, "Full Wave Sensorless Drive ICs for Brushless DC Motors", Dominique Pouillox, discloses a drive circuit for a brushless DC motor in which commutation timing is determined by internally sensing the zero crossings of the back-EMF generated by the three status windings during their non-energised periods. Although the present invention pertains to polyphase dc motors, in general, it finds particular application in conjunction with three phase dc motors, particularly of the brushless, sensorless type which are used for rotating data media, as may be found in computer related applications, such as hard disk drives, CD ROM drives, floppy disks, VCRs, and the like. In such computer applications, three phase brushless, sensorless dc motors are becoming more popular, due to their reliability, low weight, and accuracy. Usually, motors of this type can be thought of as having a stator with three field coils, generally connected in a "Y" configuration, although actually, a larger number of stator coils are usually employed with multiple motor poles. Typically, in such applications, eight pole motors are used which have four electrical cycles per revolution of the rotor. The stator coils, however, can be still be analyzed in terms of three "Y" connected coils, connected in three sets of four coils, each physically separated by 90°. In operation in bipolar applications, the coils are energized in sequences in each of which a current path is established through two coils of the "Y", with the third coil left floating. The sequences are arranged so that as the current paths are changed, or commutated, one of the coils of the current path is switched to float, and the previously floating coil is switched into the current path. Moreover, the sequence is defined such that when the floating coil is switched into the current path, current will flow in the same direction as in the coil which was included in the prior current path. In this manner, six commutation sequences are defined for each electrical cycle in a three phase motor. In the past, during the operation of a such polyphase, sensorless dc motor, it has been recognized that maintaining a known position of the rotor is an important concern. There have been various ways by which this was implemented. The most widely used way, for example, was to start the motor in a known position, then develop information related to the instantaneous or current position of the rotor. One source of such instantaneous position information was developed as a part of the commutation process, and involved identifying the floating coil, and monitoring its back emf (bemf), that is, the emf induced into the coil as it moves through the magnetic field provided by the stator. When the voltage of the floating coil crossed zero (referred to in the art as "a zero crossing"), the position of the rotor was assumed to be known. Upon the occurrence of this event, the rotor coil commutation sequence was incremented to the next phase, and the process repeated. However, particularly at startup of the motor, a problem exists, since the motor speed is low, and the bemf developed is very small and is difficult to detect with the sufficient accuracy to enable precision commutation of the activation voltages on the field windings of the motor. The inability to accurately determine the position of the rotor can lead to motor position inaccuracies, and even loss of synchronization. Thus, in the past, great care had to be taken to insure that the startup algorithms and running conditions were precisely controlled to avoid anything which might cause such out of synchronization condition to occur. In light of the above, therefore, it is an object of the invention to provide an improved method by which the back emf of a floating coil of a polyphase dc motor can be detected. It is another object of the invention to provide a method of the type described which is effective to detect the back emf of a polyphase dc motor that can be used at low motor speeds or with small magnitudes of back emf. It is another object of the invention to provide a method of the type described that does not contribute to jitter or motor switching imprecision. It is yet another object of the invention to provide an apparatus for performing the method in accordance with the invention. It is another object of the invention to provide an improved apparatus and method of the type described which is useful three phase dc motor applications, particularly motors of the brushless, sensorless type which are used for rotating data media, such as found in computer related applications, including hard disk drives, CD ROM drives, floppy disks, and the like. These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims. According to a first aspect of the present invention there is provided a circuit for detecting a back emf signal of a motor coil, comprising circuitry for providing a differential voltage proportional to the back emf of the motor coil, circuitry for adding a first hysteresis bias current to said circuitry for providing a differential voltage, to modify the differential voltage and thereby produce a modified differential voltage, circuitry for adding a second hysteresis bias current to said circuitry for providing a differential voltage, to further modify the modified differential voltage responsive to the back emf approaching a zero crossing from a predetermined direction, said second hysteresis bias current opposing and of greater magnitude than said first hysteresis bias current and a comparator connected to receive the modified differential voltage to produce an output state change when the modified differential voltage exceeds a predetermined value. According to a second aspect of the present invention there is provided a method of detecting a back emf signal of a motor coil, for use in determining a position of the rotor of the motor, comprising generating a first voltage, proportional to a voltage on said motor coil, generating a second voltage, proportional to said reference potential, of the same proportional ratio as said first voltage is proportional to the voltage on said motor coil, generating a differential voltage, proportional to the back emf of the motor coil, in dependence on said first and second generated voltages, adding a first hysteresis bias voltage to said first voltage to modify the generated differential voltage and thereby produce a modified differential voltage, switchably adding a second hysteresis bias voltage to said second voltage to further modify the modified differential voltage responsive to the back emf approaching a zero crossing from a predetermined direction, the second hysteresis bias voltage opposing and of greater magnitude than said first hysteresis bias voltage and producing an output state change when the modified differential voltage exceeds a predetermined value. The dependent claims relates to further embodiments of the invention. The invention is illustrated in the accompanying drawings in which: Figure 1 is a block diagram of a motor control circuit showing its connections to a Y-connected motor winding, and including a back emf amplifier and zero-crossing detector, in accordance with a preferred embodiment of the invention. And, Figure 2 is an electrical schematic diagram of a back emf amplifier and reference voltage crossing detector, in accordance with a preferred embodiment of the invention. In the various figures of the drawing, like reference numerals are used to denote like or similar parts. A portion of an electrical schematic block diagram of a motor controller circuitry 10 in which the apparatus and method in accordance with a preferred embodiment of the invention may be incorporated is shown in Figure 1. Although the motor controller can be constructed of discrete components, preferably, the motor controller 10 is integrated onto a single semiconductor chip adapted for connection to the stator coils of a three phase dc brushless spindle motor, for use, for example, to turn a magnetic or other disk in systems such as computer hard disk drives, cd-rom drives, floppy disk drives, VCRs, and the like. Such three phase motor preferably has "Y" connected stator windings 11, although such Y configured winding connections are not essentially required. Thus, the respective windings 11 and their center connection point can be connected to output terminals A, B, C and CTR TAP, as shown. It should be noted that although a preferred embodiment of the invention is described with regard to a three phase motor, in particular, the principles of the invention can be equally advantageously applied to polyphase motors, in general; also, it should be understood that the center tap (CT) connection may be simulated in some applications. The driving voltage is provided to the output terminals A, B, and C by a power stage 12. The power stage 12 is sequenced to provide sequential control output signals to the output terminals A, B, and C by a sequencer circuit 13 and a signal interface circuit 14 that delivers the output signals from the sequencer circuit 13 to the power stage 12. The sequencer 13 also provides drive signals to other circuits of the controller circuitry to control the various aspects of rotation of the motor driven by the circuit 10. The output terminals A, B, and C are also switchably connected to a back-emf sense amplifier and reference voltage crossing detector circuit 15, the details of which are described below with reference to Figure 2. The back-emf sense amplifier and reference voltage crossing detector circuit 15 in turn delivers signals to a load and reset circuit 16 that controls a delay counter 17 to control the increment operation of the sequencer 13. A period counter 18 and mask counter 19 are also provided to control the operation of the sequencer 13 and of the control circuit 10. The motor controller circuitry 10 also includes system clock circuitry 23, and velocity control loop 24, and may include various other circuitry, not shown, such as circuitry to support pulse width modulation operation of the motor, "align and go" start up circuitry to facilitate start up of the motor from a stopped condition, port control logic and associated shift register circuitry to facilitate control of the motor controller circuitry by an external microprocessor (not shown), and so forth. In operation, during an energized phase, one node (for example, node A) is driven high by the circuitry of the power stage 12, and another node (for example, node B) is driven low. The remaining node (for example, node C) is left floating. This is be referred to as the "AB phase". The coils are then switched in a commutation sequence determined by the sequence circuit 13 in a manner such that in each commutation phase current always flows in two of the three coils, with the third coil floating, and that after switching current will continue to flow, and in the same direction, in one of the two coils in which current was flowing in the previous phase. Such operation is commonly referred to as "bipolar operation." "Unipolar operation", in which only one coil is energized at any time, may alternatively be employed. The switching of the driver transistors of the power stage 12 to effect the switching currents for each commutation phase is accomplished by a sequencer circuit 13 and an associated interface.circuit 14. The commutation among the coils 11 is performed in response to information indicating the specific position of the rotor of the motor in conjunction with circuit information indicating the desired position of the rotor. More specifically, the commutation to apply the each successive sequence of driving signals to the coils 11 is determined in response to a corresponding coil reaching a particular rotational position and its correlation with sequencer information indicating where the motor should be at a particular time prior to when a commutation is to occur. The determination of the precise rotational location of the rotor is continuously being updated by monitoring the reference voltage crossing voltage in each non-driven, or floating, coil. More particularly, as the coils 11 are switched during the commutation sequence of the rotor, the voltage of the floating coil is monitored by the back emf amplifier circuit 15 shown in Figure 2. With reference now to Figure 2, the back emf amplifier circuit 15 receives inputs from the output of the sequencer 13 shown in Figure 1, as well as connections to the center tap and nodes A, B, and C of the coils 11. The back emf amplifier circuit 15 includes circuitry 30 that includes current path pairs 31 and 32 in which the current is respectively controlled by the voltage on one of the coils 11, for example on node A, and the center tap potential. Similar current path circuitry (not shown) are provided for the remaining two coil connections B and C. Bias circuitry 33 is provided to bias the current path pairs 31 and 32, in a manner described below in detail. Outputs derived from the current path pairs 31 and 32 are respectively connected to the inverting and non-inverting inputs of a comparator 34, the output of which represents the back emf signal for use in the motor driver circuitry 10, shown in Figure 1. The outputs from the sequencer 13 in Figure 1 are connected to the inputs of an anticipated slope detector circuit 35, which provides outputs to switchably select which of the current path pairs (i.e., the pairs 30 or the pairs, not shown, associated with coils connected to nodes B and C) are instantaneously operative. The purpose of the current path pairs 30 is to develop voltage signals for comparison from the input signals applied to the bases of transistors 40 and 41, respectively from the node A and the node CT from the center tap connection of the coils 11. Thus, the outputs from the collectors of the transistors 40 and 41 are connected respectively to the inverting and non-inverting inputs of the comparator 34. More particularly, the particular current path pairs 30 to be instantaneously operative, depending upon the commutative sequence of the coils 11, is determined from the input lines 43 from the sequencer circuit 13 in Figure 1. Thus, for example, the first two lines of the lines 43 representing, for instance, a pair of upper and lower drivers (not shown) in the power stage 12 of Figure 1, are compared in a NAND gate 44 to operate a transistor switch 45 that controls the bias to select the current path pairs 30. Similar sequencer line comparators are provided for the respective current path pairs provided for the other coils of the coils 11 that operate from respective other lines in the lines 43 from the sequencer 13. A first part of the bias circuit 33 supplies normal current bias to the emitters of the transistors 40 and 41 in the current path pairs 31 and 32. It should be understood that similar stages are employed for the various other driving combinations, connected for example, to control line 36. For this purpose, the first stage 33 includes a PNP transistor 46 that is connected with its emitter-collector path connected to an input voltage, VI. The current path pair 31 and 32 respectively include FETs 50 and 51, connected between the collector of the transistor 40 and ground, and FETs 52 and 53 connected between the collector of the transistor 41 and ground. The gates of the transistors 50-53 are connected to a positive voltage supply different from the input voltage, VI, for example to a +5 volt supply as shown. The FETs 50-53, therefore, operate as resistive loads upon the collectors of the PNP transistors 40 and 41. Thus, in normal operation, when the current path pair 30 is selected through the operation of the transistor switch 45, bias current is supplied to the current paths 31 and 32 through the PNP transistor 46 to flow through the transistors 40 and 41 and their respective loads 50 and 51, as well as 52 and 53. It should be noted that FETs 50 and 52 and FETs 51 and 53 are equally sized so that a balanced current flows through both current paths 31 and 32, in the absence of other factors. Resistors may also be used in place of the FETs. A hysteresis bias current is additionally supplied to both current paths 31 and 32. The hysteresis current that is applied to the path 31 is of a value of twice the hysteresis current that is supplied to the current path 32. In addition, the hysteresis bias current that is applied to the current path 31 is switchably applied in dependence upon the voltage of the back emf output produced by the comparator 34. More particularly, two hysteresis bias current paths 60 and 61 are provided. The hysteresis bias current path 60 includes PNP transistors 63 and 64, the emitter-collector current paths of which being connected in series between a source of potential, such as a +5 volt on a line 65 and a line 66 connected to a node 67 between the two resistive loads provided by FETs 52 and 53. In addition, the hysteresis current bias path 61 includes an NPN transistor 72, having its emitter-collector current path connected in series with the current flow path of the PNP transistors 63 and 64. The emitter of the transistor 72 is connected by a line 73 to a node 74 at the interconnection between the resistive load FETs 50 and 51. Thus, a hysteresis current bias of 1 X I hyst is applied on line 66 to the node 67 between resistor transistors 52 and 53, and when the back emf output from the comparator 34 goes high, through the operation of the transistor 75, the transistor 72 is biased to prevent the hysteresis bias current from being applied to the node 74 between the resistive load transistors 50 and 51. On the other hand, when the back emf voltage at the output of the comparator 34 is low, by virtue of the action of the NPN transistor 72, twice the hysteresis bias current, 2 X I hyst , is applied to the node 74 between the resistive load transistors 50 and 51, and at the same time, one times the hysteresis current, 1 X I hyst , is applied to the node between the resistor transistors 52 and 53. The effect of this biasing arrangement, with respect to the hysteresis current, is to change the threshold at which the comparator 34 is switched in response to the voltage between the coil on node A and the center tap of the coils 11. Thus, in operation, when the output from the comparator 34 is high, a bias current of 1 X I hyst is supplied to the node 67 between the resistive load transistors 50 and 51, and no hysteresis bias current is supplied to the node 74 between the resistive load transistors 50 and 51. As the voltage applied to the base of the PNP transistor 40 from the coil on node A increases to a level at which the comparator 34 begins to switch, the change in state on the output of the comparator 34 causes a bias current of 2 X I hyst to be applied to the node 74 between the resistive load transistors 50 and 51. No change occurs in the hysteresis bias upon the node 67. This operation assists the transition at the threshold of the comparator 34, resulting in a clean, rapid transition through the threshold at the switch-over point. In addition to the foregoing hysteresis bias circuit, a preset bias is also applied to the nodes 67 and 74 between the respective resistive load transistors 50 and 51, and 52 and 53. The preset bias applied to the node 74 between the transistors 50 and 51 is a single valued preset bias (i.e., 1 X I pre ) supplied by the PNP transistor 77 and NPN transistor 78 in the current path 76. In addition, a preset current bias path 80 is provided, including PNP transistor 81 and NPN transistor 82, connected between the voltage supply line 65 and the node 67 between the resistive load transistors 52 and 53. The base of the NPN transistor 82 is controlled by a switch transistor 83, which receives an input on its gate from the anticipated slope detector circuit 35 on line 84. In operation, when the signal on the line 84 from the anticipated slope detector circuit 35 indicates that a positive to negative transition is anticipated by the back emf on the coil on node A, the switch 83 is activated, whereby only the preset bias of 1 X I pre is provided on the current path 76 to the node 74 between the resistive load transistors 50 and 51. On the other hand, when the anticipated slope of the back emf is expected to be from negative to positive, the switch 83 allows the NPN transistor 82 to apply a bias current of 2 X I pre to the node 67 between the resistive load transistors 52 and 53. Thus, in the operation of the preset portion of the circuit, a normal preset bias exists on the comparator 34 by virtue of the current bias equal to 1 X I pre applied by the current path 76 to the node 74 between the resistive load transistors 50 and 51. To be detected, a back emf voltage that is transitioning from positive to negative must cause a current that overcomes the preset bias current 1 X I pre . In similar fashion, on the other hand, to be detected, a back emf voltage that is transitioning from negative to positive must also produce a current in the current path 32 that overcomes the preset bias I pre , since a bias current of 2 X I pre is applied through the current path 80 to the node 67 between the resistive load transistors 52 and 53. The ultimate effect of the biasing arrangement is to preset or set the output of the back emf amplifier to a specific state in the absence of a back emf signal, such as at startup after an align has been performed, to enable the first zero crossing to be correctly detected. This allows correct positioning of the back emf comparator when no motion exists so as to correctly detect the first transition of the back emf when the motor starts moving. The problem that is addressed is that in a comparator that has hysteresis, if the input is within the range of the hysteresis, the state of the output is uncertain. For example, the output can be either high or low, because the input will not force either state. Therefore, by the shifting of the reference level to above or below the hysteresis region, it can be assured that the comparator is forced in one particular state. That is it is assured that the comparator is in one particular output state, either high or low, depending on what the expected transition of the output will be once motor is moved from the startup position. It should also be noted that the provision of a voltage detection that is non-zero may produce a delay between the time the back emf actually crosses zero and the time that the back emf crosses the preset voltage threshold. This can be compensated easily in the delay circuitry 17 (see Figure 1) by appropriate adjustment of the clock frequency, or of the count to which the delay counter is permitted to count prior to incrementing the sequencer 13. It should also be noted that with respect to the relative sizes of the bias currents, preferably the normal bias current that is provided by the current path that includes the PNP transistor 46 is larger than the bias of the preset circuitry on line 76. The bias of the preset circuitry on line 76, in turn, preferably is larger than the bias of the hysteresis circuit provided on the line 73. It will be appreciated, however, that other biasing arrangements and relative magnitudes may be employed, depending upon the particular application in which the circuit 15 is used. As mentioned one advantage provided by the back emf amplifier of the invention is that by virtue of the preset bias, at startup of the motor, the output of the back emf amplifier is in a correct state to enable rapid synchronization with the rotor of the motor with which the circuit is associated. More particularly, without a preset bias, the output of the back emf amplifier could be either high or low; however, by virtue of the preset bias, the output of the back emf amplifier is in a known correct state to enable the rapid synchronization of the motor upon the occurrence of a correctly sensed back emf signal. Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the scope of the appended claims.

Claims: A circuit for detecting a back emf signal of a motor coil, comprising: circuitry (40,41) for providing a differential voltage proportional to the back emf of the motor coil; circuitry (63,64) for adding a first hysteresis bias current (60) to said circuitry (40,41) for providing a differential voltage, to modify the differential voltage and thereby produce a modified differential voltage; circuitry (72) for adding a second hysteresis bias current (61) to said circuitry (40,41) for providing a differential voltage, to further modify the modified differential voltage responsive to the back emf approaching a zero crossing from a predetermined direction, said second hysteresis bias current (61) opposing and of greater magnitude than said first hysteresis bias current (60) ; and a comparator (34) connected to receive the modified differential voltage to produce an output state change when the modified differential voltage exceeds a predetermined value. The circuit for detecting a back emf signal of a motor coil according to claim 1, wherein said circuitry (40,41) for providing a differential voltage includes: first (31) and second (32) current paths each comprising a current control element (40,41) and at least one resistor element (50,51,52,53) on which a voltage is developed in response to a current in the current path, the voltage on each at least one resistor element being connected to respective inputs of said comparator (34), one end of said motor coil being connected to said current control element (40) of said first current path (31), and a reference potential (cr) being connected to said current control element (41) of said second current path (32), whereby the back emf signal across said coil produces a change in voltage across the resistor element (50,51) of said first current path (31) with respect to the voltage across the resistor element (52,53) of said second current path (32); circuitry (35) for selectively producing a first signal during detection of the back emf signal developed in said motor coil when the back emf signal approaches the zero crossing from a predetermined direction; circuitry (77,78) for biasing said first current path (31) with a first preset bias current (76); circuitry (81,82) for switchably biasing said second current path (32) with a second preset bias current (80) of greater amplitude than said first preset current (76); and a switch (83) operative in response to said first signal to switchably apply said second preset bias current to said second current path, said comparator (34) further producing an output state change when the back emf signal of said motor coil exceeds a value determined by said preset bias current. The circuit for detecting the back emf of a motor coil according to claim 2, wherein said first (31) and second (32) current paths each comprise two resistive elements (50,51,52,53) said respective current control elements (40,41) being transistors having respective current paths, said current path of said transistor (40)and said two resistive elements (50,51) being connected in series with said current path and one of said two resistive elements being connected at first nodes, and said two resistive elements being connected at second nodes (74,67); the first node of said first current path (31) and the first node of said second current path (32) being connected to respective inputs of said comparator (34); said circuitry (77,78) for biasing said first current path (31) with the first preset bias current being connected to a first of said second nodes (74) of said first current path (31); and said circuitry (81,82) for switchably biasing said second current path (32) with the second preset bias current being connected to a second of said second nodes (67) of said second current path (32). The circuit for detecting the back emf of a motor coil according to claim 3, wherein said circuitry (63,64) for adding a first hysteresis bias current is connected to said second of said second nodes (67) of said second current path (32); said circuitry (72) for adding a second hysteresis bias current is connected to said first of said second nodes (74) of said first current path (31); and a switch (75) is provided operative in response to the output state change of said comparator (34) to switchably apply the second hysteresis bias current to said first current path (31). The circuit of any preceding claim, wherein said motor coil is one of a plurality of motor field coils (11) connected in a "Y" configuration. The circuit of any preceding claim, wherein said circuitry (72) for adding said second hysteresis bias current (61) is coupled to said comparator (34), so that the second hysteresis bias current is added responsive to the output of said comparator (34) being low. The circuit of any preceding claim, wherein the magnitude of said second hysteresis bias current (61) is twice as large as the magnitude of said first hysteresis bias current (60). The circuit of any one of claims 2 to 7, wherein said comparator (34) has an inverting input and a non-inverting input operative to produce a change in output state when a voltage applied to the inverting input exceeds a voltage applied to the non-inverting input, said voltage across said resistor element (50,51) in said first current path (31) being connected to the inverting input of said comparator (34), and said voltage across said resistor element (52,53) in said second current path (32) being connected to the non-inverting input of said comparator (34). The circuit of claim 5 when dependent on claim 2, wherein said reference potential connected to said current control element (41) of said second current path (32) is produced at a centre tap (CT) connection of said plurality of motor field coils (11). The circuit of any one of claims 2 to 9, wherein said circuitry (81,82) for switchably biasing said second current path (32) with said second preset bias current (80) comprises circuitry for switchably biasing said second current path (32) with a bias current of twice said first preset bias current (76). The circuit of any one of claims 2 to 10, wherein said current control element (40,41) of each of said first (31) and second (32) current paths is a bipolar transistor. The circuit of any one of claims 2 to 11, wherein said resistor element (50,51,52,53) of each of said first (31) and second (32) current paths is an FET. The circuit of claim 12, wherein said FETs of said first (31) and second (32) current paths have equal resistance. The circuit of claim 11, wherein said resistor element (50,51,52,53) of each of said first (31) and second (32) current paths is a pair of FETs, the current paths of said bipolar transistor (40) and said FETs (50,51) being connected in series, the output voltage being developed between said bipolar transistor (40)and one of said FETs (50) and the bias current being connected between said FETs (50,51). The circuit of any one of claims 2 to 14, further comprising means (45) for switchably applying a normal bias current to both said first and second current paths, and means (44) for generating a signal when said motor coil is floating for actuating said means for switchably applying a bias current. The circuit of any one of claims 3 to 15, wherein said two resistor elements (50,51,52,53) of said first (31) and second (32) current paths are resistors. A method of detecting a back emf signal of a motor coil, for use in determining a position of the rotor of the motor, comprising: generating a first voltage (31), proportional to a voltage on said motor coil; generating a second voltage (32), proportional to said reference potential (CT), of the same proportional ratio as said first voltage is proportional to the voltage on said motor coil; generating a differential voltage, proportional to the back emf of the motor coil, in dependence on said first (31) and second (32) generated voltages; adding a first hysteresis bias voltage (60) to said first voltage to modify the generated differential voltage and thereby produce a modified differential voltage; switchably adding a second hysteresis bias voltage (61) to said second voltage to further modify the modified differential voltage responsive to the back emf approaching a zero crossing from a predetermined direction, the second hysteresis bias voltage opposing and of greater magnitude than said first hysteresis bias voltage; and producing an output state change when the modified differential voltage exceeds a predetermined value. The method of claim 17, further comprising: selectively generating a first signal (84) during a detection period of the back emf signal developed in said motor coil, responsive to the back emf signal approaching the zero crossing from the predetermined direction; adding a first preset bias voltage (76) to said second voltage to produce a first added voltage; and in response to said first signal, switchably adding a second preset bias voltage (80) higher than said first fixed bias voltage to said first voltage to produce a second added voltage. The method of claim 18, wherein said step of switchably adding said second preset bias voltage (80) higher than said first preset bias voltage (76) to said first voltage comprises switchably adding a bias voltage two times higher than said first preset bias voltage. The method of any one of claims 17 to 19, wherein said step of switchably adding said second hysteresis bias voltage (61) higher than said first hysteresis bias voltage (60) comprises switchably adding a bias voltage two times higher than said first hysteresis bias voltage (60). The method of any one of claims 17 to 20, comprising: commutating field coil voltages in response to the back emf signal of a floating field coil crossing a reference voltage (CT), the crossing being determined by determining when the total resulting differential voltage crosses zero to produce an output voltage for timing said field coil commutation.

Inventors: CAROBOLANTE FRANCESCO, ROHRBAUGH MARK E, CAROBOLANTE, FRANCESCO, ROHRBAUGH, MARK E.
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1993
Main classification: H02P6
IPC codes: H02P6