Apparatus providing a MOS temperature compensated voltage reference for low voltages and wide voltage ranges

Abstract: A reference voltage generator which compensates for temperature and V CC variations includes a constant current source and a MOS P-channel transistor (28). The constant current source provides a constant current over a wide range of V CC that corresponds to biasing a p-channel transistor (28) in a region where its resistance is constant. The output of the current source is supplied to the P-channel transistor (28), which is in saturation. The constant current provides a constant voltage drop across the P-channel transistor (28). Hence, a stable reference voltage is generated. Temperature compensation is provided by biasing the P-channel transistor (28) to saturation and supplying a constant current that the corresponds to biasing a p-channel transistor (28) where the resistance is substantially constant over a temperature range. The current causes a voltage drop across the P-channel transistor (28) to maintain a stable reference voltage. Also, temperature compensation is further provided by utilizing the negative temperature coefficients of the resistors (14, 24) included in the constant current source.

Description: The present invention relates to a reference voltage generator and more particularly to a metal oxide semiconductor ("MOS") temperature compensated reference voltage generator for low and wide voltage ranges for use on integrated circuitry. Many electronic devices require a reference voltage to implement their design. The reference voltage may be used no control the electronic device or may, for example, be compared to another voltage. These uses require that the reference voltage remain stable. The challenge is to provide a reference voltage generator which gives a stable voltage despite temperature and power supply (voltage) variations, or others. One type of device that is used to generate a reference voltage is a "bandgap" circuit. The bandgap circuit was originally developed for bi-polar technology. It has been modified for use with Complementary Metal Oxide Semiconductor ("CMOS") technology. Among the elements used to implement the modified bandgap circuit are transistors biased as diodes. This type of bias requires the P-N junctions of the transistors to be forward biased. This type of biasing is not well-suited for CMOS technology since any generation of substrate current may cause the bandgap circuit to latch-up. Manufacturers avoid this problem by using specially isolated wells in the semiconductor manufacture in order to collect the current. Another reference voltage generator, as shown in Fig. 5, provides a reference voltage determined by the difference between the threshold voltages of transistors used in the device. Referring to Fig. 5, a transistor 40 has a threshold voltage V T1 that is less than the threshold voltage V T2 of transistor 42. V REF is calculated by the equation: V REF = V T2 - V T1 . For example, if V T1 = -1.6V and V T2 = -0.6V, then V REF = +1.0V. In this example, both transistors are P-channel devices, and each has a respective threshold voltage. However, most CMOS technologies readily provide P-channel MOS transistors on a chip with uniform, single V T . Extra processing steps, such as masking and implanting, are needed to fabricate a P-channel transistor with another V T . These extra steps add considerable expense to the fabrication of this second device and the resulting circuit. Turning to Fig. 2, reference may be had to Mobley and Eaton, Jr. U.S. Patent 5,134,310 entitled "Current Supply Device For Driving High Capacitance Load In An Integrated Circuit," issued July 28, 1992, for a description of a similar configuration used in another application, however, without FET 28 and connections 36 (explained infra ). More specifically, the present invention relates to a generator according to the preamble of claim 1, which is known, e.g. from US-A-4 009 432. It is the general object of this invention, having the further features set forth in claim 1, to overcome the above-listed problems. Another object of the present invention is to provide a reference while allowing the use of any standard CMOS or MOS processes, thereby to obviate extra or costly processing. A further object of the present invention is to implement a reference voltage generator that works well at low voltages and despite wide voltage variations. Still another object of the present invention is to provide a reference voltage generator that has low power consumption. A salutary object of the present invention is to provide a reference generator which can be designed to have a positive, negative, or an approximately zero temperature coefficient. In providing a stable reference voltage, a preferred embodiment of the present invention includes a constant current source and a MOS P-channel transistor. The constant current source is designed to provide a constant current over a wide range of V CC . The output of the current source is supplied to a saturation biased P-channel transistor. The preferred embodiment is configured so that the current of the current source is constant as V CC varies, which causes the voltage drop across the P-channel transistor to be constant and hence provide the stable voltage reference. To control voltage, temperature compensation is provided by supplying to the P-channel transistor a constant current that corresponds to the transistor's bias region where V DS (drain-to-source voltage) at 0°C is substantially equal to V DS at temperatures up to and inclusive of, for example, 90°C. While operating the P-channel transistor in this bias region, its resistance remains substantially constant for varying temperatures. With the resistance and current remaining substantially constant, it follows from Ohm's Law that V REF will remain substantially constant. It will be understood that a novel and important aspect of the operation of such a voltage reference generator is the provision of a saturation biased P-channel transistor, a constant current corresponding to a transistor bias region where V DS (drain-to-source voltage) is substantially equal over a temperature range, and the use of the temperature coefficients of the resistors used in the constant current source. The invention, together with the objects and the advantages thereof, may be better understood by reference to the following detailed description taken in conjunction with the accompanying drawings of which: Fig. 1 is a simplified diagram of a circuit embodying the present invention. Fig. 2 is a detailed diagram of the Fig. 1 embodiment. Fig. 3 is a graph showing the stability of the generated reference voltage over a V CC range for the Fig. 1 embodiment. Fig. 4 is a graph of the bias region for the preferred biased P-channel transistor of the Fig. 1 embodiment where V DS (drain-to-source voltage) is substantially equal over a temperature range. Fig. 5 is a diagram of a prior art reference voltage generator. Fig. 6 is a detailed diagram of a tuning circuit for the V REF transistor shown in Fig. 2. Fig. 1 shows a circuit 10 embodying the present invention. A constant current source 2, coupled to receive a first power supply voltage V CC , supplies a constant current I to a transistor 6. A voltage drop between a node 4 and a node 8 (across transistor 6) generates a reference voltage V REF at node 4. Node 8 is coupled to receive a second (power supply) voltage, preferably V SS . Preferably but not necessarily circuit 10 is located on an integrated circuit. Fig. 2 is a detailed diagram of a preferred embodiment of such a circuit 10. A first node 12 and a first electrode 14a of a resistor 14 are preferably coupled to a voltage V CC . Although Fig. 2 shows them coupled together by line 15, it is possible to couple node 12 to V CC at one connection and to couple the (first) electrode 14a of resistor 14 to V CC at a second connection. A source electrode of a preferably P-channel metal oxide semiconductor ("MOS") field-effect transistor ("FET") 16 is also preferably coupled to first node 12. A second electrode of resistor 14, a gate electrode of transistor 16, and a source electrode of another P-channel MOS FET 18 are coupled to a second node 20. A drain electrode of transistor 16 and a gate electrode of transistor 18 are coupled to a third node 22. A first electrode 24a of a second resistor 24 is connected to third node 22 and a second electrode 24b of resistor 24 is connected to a second potential (e.g. ground potential) . A fourth node 26 is illustratively coupled to a drain electrode of transistor 18 and a source electrode of a MOS FET 28. Also, V REF is preferably output at fourth node 26. A gate electrode and a drain electrode of transistor 28 are preferably coupled to a fifth node 30, which is also preferably coupled to second potential (e.g. ground potential). Thus, it will be seen that paths from V CC to ground are: (1) via the source-drain path of FET 16 and then resistor 24, and (2) via resistor 14 and then the source-drain paths of FETS 18 and 28. The use of resistors 14 and 24 with values preferably in the 100-500 kΩ range will decrease the amount of current through the circuit. This in turn will reduce the power consumption. Preferably transistor 16 has a larger channel width to length ratio than transistors 18 and 28. For example, transistor 16 can have such a ratio of 200:1, transistor 18 can have a ratio of 4:10 and transistor 28 can have a ratio of 2.2:10 while resistors 14 and 24 can be 500 kΩ. The operation of the Fig. 2 embodiment will now be discussed. The circuit in Fig. 2 is preferably configured so that the voltage difference between nodes 20 and 22 will remain the same when V CC varies. V CC preferably varies at a greater rate than the variances of nodes 20 and 22. It is preferred that transistors 16, 18 and 28 are biased to their saturation regions so that the current between transistors 16, 18 and 28 source-to-drain path is given by the equation: I DS = βW/L (V GS - V T ) 2 where β is a constant which is equal to the capacitance of the oxide multiplied by the mobility of the current carriers of a saturated transistor, W is the channel width of a transistor, L is the channel length of the transistor, V GS is the voltage difference between the gate and source of the transistor, and V T is the threshold voltage of the transistor. When V CC increases, the voltage at node 20 increases in such a manner that the voltage difference (V GS of transistor 16) between nodes 12 and 20 increases, thereby increasing the source-to-drain current I 16 of transistor 16 as calculated by Equation 2. Increased current I 16 causes the voltage at node 22 to increase simultaneously with node 20, which maintains the voltage difference (V GS of transistor 18) between nodes 20 and 22 substantially the same. Thus, the current I 18 is substantially unchanged as calculated by Equation 2. Conversely, as V CC decreases, the voltage at node 20 decreases in such a manner that the voltage difference between nodes 12 and 20 decreases, thereby decreasing current I 16 . Decreased current I 16 causes the voltage at node 22 to decrease along with the decreasing voltage of node 20. The voltage difference between nodes 20 and 22 of transistor 18 remains the same which maintains the current I 18 substantially unchanged as calculated by Equation 2. The constant current I 18 flows through transistor 28 which is preferably biased by connecting its gate and source electrodes together. This leaves transistor 28 in a preferred saturation mode. With transistor 28 in saturation, its resistance is held constant. Therefore, the constant current flowing through saturated transistor 28 causes a constant voltage drop and, hence, a stable V REF available at node 26. Fig. 3 illustrates the value of reference voltage V REF as V CC varies. The portion of Fig. 3 with a positive slope indicates that transistor 28 is in its linear region. The portion with the approximately zero slope (i.e., where transistor 28 is in saturation) shows that the preferred embodiment of the present invention will maintain V REF at a substantially constant value when V CC varies between approximately 2.5 volts and 6.0 volts. As also can be seen in Fig. 3, V REF is substantially maintained at varying temperatures, illustratively shown for 0°C (solid line) and 90°C (dashed line). If V CC decreases below 2.3 volts, transistor 28 will leave saturation and enter its linear region. Any V CC fluctuations while transistor 28 is in the linear region will vary its resistance. As a result, V REF would also vary. Various transistor types and dimensions, along with the variation of other components of the circuit will alter the voltage range over which the circuit will generate a stable V REF . Fig. 4 shows the I-V characteristics of transistor 28. The two lines of Fig. 4 illustrate the inverse resistance (1/R) of transistor 28 for two temperatures (illustratively 25°C and 90°C). The intersection of these lines is the transistor 28 bias region where V DS (drain-to-source voltage) is substantially equal over a temperature range. This bias region corresponds to the transistor resistance where a constant current supplied to the transistor will cause a voltage drop that does not vary with temperature. When a current, illustratively I in Fig. 4, is supplied to transistor 28, V REF remains substantially stable regardless of temperature fluctuations within or about the range from 25° to 90° centigrade. If the current supplied to transistor 28 were to increase, illustratively shown in Fig. 4 by the dashed lines, it would intersect the lines representing 25°C and 90°C at different respective V REF . Hence the need for biasing the constant current source in the appropriate region to avoid temperature variations. In Equation 2, β = µC OX , where µ is the mobility carrier constant at a given temperature, C OX is the capacitance of the gate oxide and VGS = -V REF . The mobility carrier constant decreases with increases in temperature. The threshold voltage V T also decreases with increases in temperature. The parenthetical quantity of Equation 2 increases when V T decreases. Hence, the I-V curves T25 and T90 exhibit exponential characteristics. As shown in Fig. 4, it is important to supply a current to transistor 28 which will generate a substantially constant VREF regardless of temperature. To show that such a current exists, the following equations are required: I DS25 = µ 25 C OX W L ( V GS - V T25 ) 2 I DS90 = µ 90 C OX W L ( V GS - V T90 ) 2 where µ 25 and µ 90 are the mobility constants for temperatures 25°C and 90°C, respectively, V T25 and V T90 are the threshold voltages for temperatures 25°C and 90°C, respectively, and I DS25 and I DS90 are the drain to source current for temperatures 25°C and 90°C, respectively. By setting I DS25 = I DS90 (current I 18 is substantially constant for all temperatures) the following equation is obtained: ( µ 25 -µ 90 ) ( V GS ) 2 + (- µ 25 2 V T25 +µ 90 2 V T90 ) V GS -µ 90 ( V T90 ) 2 + µ 25 ( V T25 ) 2 =0 Since Equation 5 is a quadratic equation, a value for V GS can be found which remains substantially constant for the constant current. Other values calculated for V GS using other temperatures will be approximately equal. Therefore, a substantially constant V REF will be generated for varying temperatures by supplying a corresponding constant current I 18 to transistor 28. Essentially, the carrier mobility variable µ and V T compensate for each other's changes as the temperature changes, thus allowing lines T 25 and T 90 to intersect. This self-compensation allows for other temperature lines (not shown) to intersect at approximately the same point at lines T 25 and T 90 . Thus, supplying a constant current to transistor 28 will generate a substantially constant voltage V REF regardless of temperature changes due to the self-compensation of the carrier mobility variable µ and V T upon each other. The temperature coefficients of the resistors used in the preferred embodiment can be also utilized to further compensate for temperature variations. For example, a resistor having a negative temperature coefficient (decreased resistance with increased temperature) will allow more current to flow when the temperature increases because of its decreased resistance. This in turn would supply more current to transistor 28 and would generate a greater V REF . As seen in Fig. 3, a greater V REF at an increased temperature, for example 90°C, would move the dashed line closer to the line representing 0°C. It is also preferred that the substrate of transistors 16, 18 and 28 should be biased to a voltage equivalent to their source voltage (as shown by wirings 36 in Fig. 2). This is done to eliminate a body effect. Body effect is the characteristic shift in threshold voltage resulting from the bias difference from the source to its substrate. If there is a high body effect, the threshold voltage increases. If there is a low body effect, the threshold voltage decreases. Biasing the substrate with a voltage equivalent to that of the source eliminates the body effect which causes variations in the threshold voltage of the preferred embodiment. Depending on the circuit application of V REF , it may be necessary to tune V REF to the desired value in order to compensate for variations in V T and other process parameters such as mobility. To accomplish tuning of V REF , it is preferable that when the embodiment of Fig. 2 is fabricated, not just one transistor 28 but multiple such transistors are created between node 26 and ground (V SS ), as shown in Fig. 6. Upon testing, the transistor or transistors that generate the required V REF are chosen and will then operate as transistor 28. The other transistors will be configured to be inactive. In Fig. 6, source electrodes of P-channel tuning transistors 50, 52, 54 and 56 are coupled to node 26. Gate and drain electrodes of tuning transistors 50, 52, 54 and 56 are coupled to drain electrodes of N-channel transistors 58, 60, 62 and 64, respectively. The gate electrodes of transistors 58, 60, 62 and 64 are coupled to receive signals A, B, C and D, respectively, which are supplied from an external source (not shown). Source electrodes of transistors 58, 60, 62 and 64 are preferably coupled to the second potential. Transistors 50, 52, 54 and 56 also have their sources coupled to their substrate (shown by wirings 66 in Fig. 6). It is preferred that tuning transistors 50, 52, 54 and 56 have a channel width to length ratio determined by the equation: W n L n = K n- 1 W 1 L 1 where n equals the number of tuning transistors, W n is the width of the channel of transistor n, L n is the length of the channel of transistor n, K is a constant which sets the minimum difference between the tuning transistors width to length ratios, and W 1 /L 1 is the width to length ratio of the transistor that is used as a reference from which the other width to length ratios are determined. A large K will cover a broad range of V REF variations, but the tuning will be more coarse because small incremental changes in V REF will not be possible. Therefore, K should be chosen to be as small as possible, but large enough to cover the worst case variations of V REF . The tuning of V REF will now be explained with reference to Fig. 6. During testing, transistors 58, 60, 62 and 64 will turn on when they receive their respective signal A, B, C and D as active. Once on, transistors 58, 60, 62 and 64 will create a path from node 26, through transistors 50, 52, 54 and 56, respectively, to the second potential (V SS ). Tuning transistors 50, 52, 54 and 56 activated by various combinations of signals A, B, C and D creates various voltage drops at node 26, and the desired value of V REF can be achieved. After a combination of signals A, B, C and D is selected, a preferred fuse circuit, preferably on the chip with the present invention, is configured to maintain the selected combination of signals A, B, C and D. Other types of circuitry may be used to render permanently conductive the selected combination. One skilled in the art will appreciate that the P- and N-channel transistors used in Fig. 6 may be replaced by other types of transistors. The number of tuning transistors used in Fig. 6 is illustrative only, and the number of tuning transistors used can depend on the degree of accuracy needed for tuning V REF or the range of variation of V REF expected from the variations in V T or the other process parameters. One skilled in the art will appreciate too that resistors 14 and 24 may be replaced with other devices that impart resistance. Transistors are one example.

Claims: An integrated circuit reference voltage generator having a first path and a second path each coupled between a first supply voltage and a second voltage, the first path comprising a first node (12), a source-drain path of a first transistor (16), and a second node (22), the second path comprising a first resistance (14), a third node (20), a source-drain path of a second transistor (18), and a fourth node (26), said first transistor (16) having its gate electrode coupled to said third node (20), said second transistor (18) having its gate electrode coupled to said second node (22), characterized by: a second resistance (24) of a substantially constant value in the first path, a source-drain path of a third transistor (28) in the second path, and an output path coupled to said second path, wherein said first path is further characterized by only one transistor (16) and only one resistance (24) and wherein said third transistor (28) is biased to saturation. The generator of Claim 1 wherein all of said transistors (16, 18, 28) are P-channel FETs. The generator of Claim 2 wherein each of said P-channel transistors (16, 18, 28) has its source electrode coupled to a substrate or region containing said transistor. The generator of Claims 1, 2, and 3 wherein said third transistor (28) has a gate electrode and a drain electrode, said electrodes being shorted together. A reference voltage generator according to any of the preceding claims wherein said third transistor (28) is operated in a region where a carrier mobility and a threshold voltage of said third transistor (28) are self-compensating so that temperature changes do not substantially change said reference voltage (VREF). A reference voltage generator according to Claim 1 wherein said first node (12) is coupled to receive a first supply voltage (VCC), said first resistance (14) having a first electrode (14a) coupled to receive said first supply voltage (VCC) and a second electrode coupled to said second node (20), said first transistor (16) having a first electrode coupled to said first node (12), a second electrode coupled to said third node (22) and a control electrode coupled to said second node (20), said second transistor (18) having a first electrode coupled to said second node (20), a second electrode coupled to said fourth node (26) and a control electrode coupled to said third node (22), said second resistance (24) having a first electrode (24a) coupled to said third node (22) and a second electrode (24b) coupled to a second potential and said third transistor (28) having a first electrode coupled to said fourth node (26), a second electrode and a control electrode coupled to said second potential, wherein a reference voltage (VREF) is available at said fourth node (26). A reference voltage generator according to Claims 1 and 6 wherein said first electrode and a substrate of said respective first, second and third transistors (16, 18, 28) have equal potential. A reference voltage generator according to any preceding claim wherein said first and second resistances (14, 24) have negative temperature coefficients. A reference voltage generator according to any preceding claim wherein said first, second and third transistors (16, 18, 28) each have a channel, and wherein said channel of said first transistor (16) has a substantially greater width to length ratio than said channels of said second and third transistors (18, 28). A reference voltage generator according to any preceding claim wherein the ohmic value of each said first and second resistance devices (14, 24) is in the range of 100 to 500kΩ, indusive. A reference voltage generator according to any preceding claim wherein said third transistor (28) is selected from a plurality of transistors coupled to said fourth node (26) in parallel.

Inventors: BUTLER DOUGLAS B, CORDOBA MICHAEL V, HARDEE KIM C, BUTLER, DOUGLAS B., CORDOBA, MICHAEL V., HARDEE, KIM C.
Applicants: NIIPON STEEL SEMICONDUCTOR, UNITED MEMORIES INC, NIPPON STEEL SEMICONDUCTOR CORPORATION, UNITED MEMORIES, INC.
Application year: 1993
Main classification: G05F3
IPC codes: H03G3, H03K19, G05F3