Analogue to digital converter

Abstract: A digital equivalent of a periodic analogue signal is generated in a manner substantially insensitive to variations in the reference about which the analogue signal oscillates by switching the digital equivalent between high and low levels based on reference voltages derived from the peaks and valleys of the analogue signal. The manner of generating the digital equivalent is substantially insensitive to common mode noise across the analogue signal generator by locking a differential signal output when significant common mode noise in sensed. Generator faults are also diagnosed.

Description: This invention relates to a method and apparatus for generating a digital representation of a fluctuating analogue signal. Sensors are in conventional use for measuring the angular rate of rotation of wheels or gears. Such sensors generate an analogue signal, substantially sinusoidal, with a frequency proportional to the angular rate. Representative of these sensors is the well-established variable reluctance sensor which measures the rate of change in flux as appendages such as teeth on the wheel or gear pass the sensor. Ideally, the rate of change in flux over time is sinusoidal and is centred around a fixed reference voltage. Applications of such sensors are widespread in the automotive field, where sensors are used to measure the rate of rotation of the crankshaft or camshaft of the vehicle engine, or may be used to measure the rate of rotation of the vehicle wheels. As such vehicles typically employ digital controllers, any wheel speed information of interest to the controller must by converted to digital form. The typical digital controller will require a substantially square wave binary signal within some predetermined voltage range, such as zero to five volts. Of course, the frequency of the digital signal should be proportional to the frequency of the analogue signal from which it was generated. Furthermore, it is desirable to maximise resolution of the signal, which is provided by approaching a 1:1 ratio between the analogue and digital signal frequencies. Converters are available commercially which compare the analogue signal to fixed voltage thresholds and switch the digital equivalent between its binary levels when the analogue signal crosses the thresholds. Such systems may reliably generate a digital equivalent of the analogue signal in the ideal case, such as when the analogue signal is centred around a fixed reference voltage, but when the signal drifts, for instance when the a.c. components of the signal are not centred around a fixed voltage level such as zero volts, the system may miss one or many oscillations of the signal. The reference of the analogue signal may vary so much as to take the entire signal outside the fixed threshold voltage range, so that the circuit does not see a crossing of the thresholds and consequently does not switch the digital equivalent. As described, the output of an ideal variable reluctance sensor is sinusoidal and is centred around a fixed reference voltage. However, in practice sensors may deviate substantially from the sinusoidal model, and may be centred around a reference which varies significantly and unpredictably. So great may be the variations in the reference voltage that the sensor output oscillations may not cross a fixed reference relied upon in a conventional digital converters. As such, analogue oscillation information will be lost and the digital signal generated by the converter will be less accurate. Variations in the reference voltage may result from a wheel or gear which does not rotate about its centre, or from teeth which fluctuate in size. Such defects may not be easy to diagnose, and may not be easily or inexpensively repaired. US-A-4575677 discloses a method which disregards any signals having a peak amplitude of less than 80% of the highest amplitude signal. JP-A-56115024 discloses a method which generates a limit signal according to the mean of minimum and maximum voltages. The present invention seeks to provide an improved method and apparatus for generating a digital representation of an analogue signal. A method of and apparatus in accordance with the present invention are characterised by the features specified in claims 1 and 4 respectively. It is possible in some embodiments to provide a method and apparatus for converting the analogue output of a wheel or gear speed sensor to a digital value usable by a digital controller and which is insensitive to unpredictable variations in the reference voltage of the analogue signal. It is also possible to provide a method and apparatus for converting an analogue waveform to a digital representation with digital switchpoints determined not from analogue signal crossings of fixed voltage thresholds, but from analogue crossings of variable thresholds. The variable thresholds can be determined from the analogue signal itself, generally as the sensed maximum or minimum peak of the analogue signal less a predetermined offset voltage. A deadband circuit may be provided to receive a sensor signal from signal conditioning circuitry which may include voltage range limiting circuitry, circuitry to reduce the effect of common mode noise, or diagnostic circuitry. The deadband circuit can detect signal peaks and valleys and can hold its output constant just after the peak or valley passes. The output is preferably held while the analogue signal passes through a deadband, after which the output is released to change in inverse proportion to the analogue signal until a valley is detected, after which the output is held again. The output of the deadband circuit may be fed to a hysteresis circuit, for comparing the conditioned analogue signal to the sum of a value proportional to the deadband circuit output and a predetermined voltage, and for switching its output between high and low digital levels when the two compared signals cross. The output of the hysteresis is a substantially square wave signal having a frequency proportional to the rotation rate of the wheel. Such circuitry is not sensitive to the stability of the reference of the analogue signal as the reference is simply ignored in generating the digital equivalent. Rather attention is focused on an amount of change in voltage magnitude from the peaks and valleys of the signal. An embodiment of the present invention is described below, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a general hardware diagram of an embodiment of this invention in which the analogue outputs of each of four wheel speed sensors are converted to digital form using the conditioning circuitry of a preferred embodiment; Figures 2a and 2b are general circuit diagrams of the conditioning circuit of Figure 1 used for conditioning an analogue signal and generating a digital representation thereof; and Figure 3 is a diagram illustrating various signals generated by certain stages of the circuit of Figures 2a and 2b. Referring to Figure 1, an automotive vehicle 10 is outlined with four wheels 12a - 12d, each wheel having a respective conventional wheel speed sensor 14a - 14d, such as a variable reluctance sensor which measures the rate of change in flux as appendages such as teeth on each wheel pass the sensor. The output of each of the sensors 14a - 14d is proportional to the rate of change in flux measured by that sensor, is substantially sinusoidal for a moving wheel, and is communicated to a respective converter 16a - 16d, which generally conditions the sinusoidal signal and outputs a digital equivalent to a respective input capture port IC1 - IC4 of a conventional input/output section 18 of a vehicle controller 22. The frequency of each of the four digital signals received by the input/output section is proportional to the speed of each of the respective four wheels. In a conventional manner, the four input capture ports may count the rising or falling edges of the received digital signals and store the count in controller memory (not shown) for access by the central processing unit 20 for conversion to a measurement of the speed of the four wheels. The wheel speed information thus provided may be used for any one of a variety of applications well known in the art of vehicle control. While Figure 1 illustrates signal conversion of wheel speed information from all four wheels of the vehicle, it should be noted that the inventors do not intend that the signal conditioning and conversion of this embodiment be limited to such applications. Rather, this embodiment may be applied to any subset of the four wheels in a wheel speed sensing application, or may be applied to other analogue outputs of sensors on the vehicle, such as crankshaft or camshaft rotation sensors. Generally, the signal conditioning and conversion of this embodiment may be applied to generate a digital representation of any analogue periodic signal on a vehicle. Figures 2a and 2b illustrate the circuitry of one of the converters 16a - 16d (Figure 1), its connection to a variable reluctance sensor 14 from the group 14a - 14d (Figure 1), and its connection to the controller 20. Specifically in Figure 2a, conventional variable reluctance sensor 14 is biased by pulling its high side up to supply voltage Vcc through resistor R2, and pulling its low side to ground voltage (ground) through resistor R4. High frequency noise is shorted to ground on both the first and second terminals of sensor 14 via capacitors C1 and C2, respectively, consistent with well-known noise filtering practise. The first terminal of sensor 14 is connected through resistor R1 to the non-inverting input of op-amp 46. The second terminal is connected to non-inverting input of op-amp 48 through resistor R3. The pair of resistors R1 and R3 along with shunt combination resistor R5 and capacitor C3 provide a low pass filter through which the sensor signal passes. This filter is conventionally used with variable reluctance sensors which have the well-known characteristic of an output magnitude proportional to the frequency of the wheel being sensed. The low pass filter operates not only to block passage of high frequency signals (noise) to later stages of the circuit of Figures 2a and 2b, such as signals above 2000 Hz, but also reduces the sensor amplitude with frequency to mitigate against the wheel speed related changes in sensor output amplitude. For instance, the filter may attenuate signals above 500 Hz by an amount proportional to signal frequency. The sensor bias provides that if the high or low side of the sensor 14 is in an open circuit condition, the low side will drop to ground and remain there as long as the condition persists. To detect this open circuit condition, circuit elements 60 - 66 are provided in the configuration shown. Specifically, the inverting input of comparator 64 is connected to low side of sensor 14 through resistor R3, and the non-inverting input of comparator 64 is connected to a fixed reference voltage, 1.7 volts in this embodiment. Comparator 64 output is connected as one input to conventional two input AND gate 66. The other input to AND gate 66 is connected to the output of AND gate 58. AND gate 58 provides a diagnostic indication which is set low when either of two sensor short circuit conditions are detected, as will be described. Accordingly, when the inverting input drops below 1.7 volts, the comparator output goes high and, if the output of AND gate 58 is high, the output of the AND gate 66 will be set high enabling counter 62, which is a divide-by-31 counter in this embodiment. AND gate 66 thus not only conditions the signal to be read by the counter 62, but, via line 106, prevents the counter from being enabled when a sensor short has been detected, as the circuit otherwise might improperly diagnose a short condition as an open sensor condition. If the output of AND gate 66 is low, the preset input to the counter is active, keeping the counter effectively disabled. Once enabled from a high output from AND gate 66, the counter moves through its counting states at its clock frequency, set by the output of oscillator 60. After 31 clock cycles, the counter 62 will overflow, setting output line 104 low (active). The low output indicates an open sensor condition, and may be input to NAND gate 86 and fault decoder 94, to be described. The oscillator frequency is set by selecting appropriate values for R21 and C5 to ensure that sensor transients which drop below 1.7 volts are not diagnosed as open sensor faults. For example, the voltage induced across a conventional variable reluctance sensor is proportional to change in flux. Flux changes more rapidly if the tooth on the toothed wheel passes by the sensor more rapidly. Accordingly, the peak to peak voltage magnitude induced across the sensor 14 will increase at higher wheel speeds, increasing the potential for the signal to drop below the 1.7 volt threshold needed to start the counter 62. The values of R21 and C5 should be set for a given application to avoid diagnosing the low voltage peaks, or decreases in the reference of the waveform generally, as open circuits. The voltage on line 2 and on line 4 should be limited or clamped before being input to the amplifiers used in the circuit of Figures 2a and 2b (to be described), to protect the amplifiers from overvoltage and to ensure that the amplifiers behave in a predictable manner. In this embodiment, lines 2 and 4 are limited to a minimum voltage of approximately one volt and a maximum of approximately four volts. The one volt limit is provided by setting the base of transistors Q1 and Q2 to slightly more than one volt, via the voltage divider including R7, D1, D2, and R6, wherein the resistance of R7 and R6 are set appropriately, using circuit design practise generally known in the art. Accordingly, when the voltage on line 2 is less than approximately one volt, Q1 turns on and limits the voltage on line 2 to the base voltage of Q1 (less the minor voltage drop across the base-emitter junction). Likewise, when the voltage on line 4 drops below approximately one volt Q2 turns on, limiting the voltage on line 4 to slightly less than the base voltage, approximately one volt. The four volt limit is provided in an analogueous manner by setting the base of Q3 and Q4 to slightly less than four volts via the divider including R11, D3, D4, and R10 which may be appropriately selected to ensure that the drop across R10 is just over four volts. Thus, when line 2 increases to approximately four volts, Q3 will turn on and limit the emitter voltage to a voltage slightly greater than the base voltage of just under four volts. Likewise, when line 4 increases to approximately four volts, Q4 will turn on and limit the voltage on line 4 to substantially four volts. The clamped voltages on line 2 and 4 are input to a conventional three amplifier instrumentation amplifier circuit. As is well-known in the art of instrumentation amplification, the first stage of the amplifier including op-amp 46 and op-amp 48 provides a differential output with a high differential gain set by the value of R12 and R13, each of which is of substantially the same resistance, which is fed to the next stage of the amplifier, a conventional differential amplifier 50 which amplifies the difference in the signals at its input terminals with a gain of one. The output of the amplifier is fed to an R-C filter including resistor R20 and capacitor C4. A normally open switch S1 is interposed between R20 and C4. First-order R-C filtering of the output of the instrumentation amplifier is provided as is generally understood in the art when S1 is closed. However, when S1 is open, capacitor C4 holds the output voltage of the amplifier since there is no path by which the capacitor C4 may discharge. S1 is controlled by a common mode noise lockout circuit including AND gate 58 and comparators 54 and 56, which form a window comparator to be described. The common mode noise lockout circuit "locks" the output of the instrumentation amplifier when common mode noise causes the differential signal at the first stage of the instrumentation amplifier to exceed the input common mode range. Such common mode noise can occur with variable reluctance sensors, and can cause misleading instrumentation amplifier outputs. For instance, the amplifier output can be driven to a voltage limit, such as the Vref of the conventional instrumentation amplifier, when both amplifier inputs are pushed to a common high or low voltage limit. This embodiment addresses these concerns by locking out such potentially misleading amplifier outputs. Specifically, the voltage signal between R12 and R13, which is the bias voltage of the differential signal of the first stage of the instrumentation amplifier, is input to the inverting input of comparator 54, and to the non-inverting input of comparator 56. In this embodiment, the inputs will indicate an excursion out of the common mode range when the bias voltage of the differential signal is greater than approximately 3.3 volts or is less than approximately 1.7 volts. Input 107 of the non-inverting terminal of op-amp 54 is thus set at 3.3 volts, such that the output of op-amp 54 will be low when the bias voltage exceeds 3.3 volts forcing the output of AND gate 58 low, opening conventional switch S1, and locking the amplifier output by not allowing capacitor C4 to charge or discharge. Likewise, the inverting input 108 to comparator 56 is set to approximately 1.7 volts, whereby the comparator 56 output will be low when the bias voltage drops below 1.7 volts, driving the output of AND gate 58 low, opening switch S1, and locking the amplifier output, as described. Beyond being communicated to switch S1, the output of AND gate 58 is provided as an input to AND gate 66, via line 106. When the bias voltage indicates that the inputs are within their common mode input range, the outputs of comparators 54 and 56 will be high, pulled up via respective pull-up resistors R14 and R15. Thus the output of AND gate 58 will be driven high, closing switch S1 and thereby allowing the output of the amplifier to vary with the differential input voltage. The output of the instrumentation amplifier, whether locked out by switch S1 or not, is next passed through a conventional voltage follower 52 (Figure 2B), acting as an impedance buffer, to a deadband circuit consisting of three amplifiers 70, 72, and 74, two resistors R22 and R23, two diodes D5 and D6, and a capacitor C6. In general, the deadband circuit compensates for drift in the reference voltage around which the amplified sensor voltage swings. As discussed, the signal reference can vary significantly. Conventional systems which attempt to derive digital representations of the signal compare the signal to fixed thresholds to determine whether it may be modelled as being in a high or low digital state. When the reference drifts from a modelled reference, these traditional systems may lose critical information on the nature of the sinusoidal sensor signal. The deadband circuit establishes voltage levels on which output switching threshold voltages are based. These levels are not fixed, but are based on the sensor output signal itself. For instance, while the sensor signal is increasing above an upper threshold voltage, the deadband circuit output voltage is decreasing proportionally. The upper threshold voltage is the difference between a fixed voltage and a value proportional to the output voltage. Accordingly, when the sensor signal is increasing, the output voltage is decreasing, increasing the upper threshold voltage. When the substantially sinusoidal sensor signal reaches its peak and starts to decrease, the peak is detected by the proportionally large upper threshold voltage, as will be described, and the output is held constant until the sensor signal decreases below a lower threshold voltage. The lower threshold voltage is the difference between a fixed voltage and a value proportional to the deadband circuit output voltage. While the sensor signal is decreasing below the lower threshold voltage, the output voltage is increasing proportionally, decreasing the lower threshold voltage. When the sensor signal reaches its valley and starts to increase, the valley is detected by the proportionally small lower threshold voltage as will be described, and the output is held constant until the sensor signal increases once again above the upper threshold voltage, as described. Specifically in Figure 2b, the output of buffer 52 passes through resistor R22 to line 6 and is input to an inverting input of conventional operational transconductance amplifier operational transconductance amplifier 70, and to an inverting input of conventional operational transconductance amplifier operational transconductance amplifier 72. The outputs of the operational transconductance amplifier 70 and operational transconductance amplifier 72 are tied to a common side of capacitor C6, the opposite side of which is grounded. Operational transconductance amplifier 70 may be described as a "sink" operational transconductance amplifier as diode D5, placed in series with its output, only allows the operational transconductance amplifier 70 to sink current from capacitor C6, otherwise it is reverse biased. Likewise, operational transconductance amplifier 72 may be described as a "source" operational transconductance amplifier as diode D6, placed in series with the operational transconductance amplifier output, only allows the operational transconductance amplifier 72 to source current to capacitor C6, otherwise it is reverse biased. The output of sink operational transconductance amplifier 70 "sinks" current from the capacitor C6 at a rate proportional to the potential difference at its input pins. The diode D5 prevents its output from sourcing current from the capacitor C6. Therefore, as is generally understood in the art of circuit design, sink operational transconductance amplifier 70 can only compensate for the input condition in which the potential at its inverting input (node 6) increases above the potential at its non-inverting input, which is fixed at DB+, to be described. The output of source operational transconductance amplifier 72 on the other hand will source current to the capacitor C6 when the voltage at its inverting input (node 6) decreases below the voltage at its non-inverting input, which is fixed at DB-, to be described. The voltage Vcap across the capacitor C6 is passed through voltage follower buffer 74, which prevents external loading on capacitor C6. The output of buffer 74 is fed back to node 6 via resistor R23. Accordingly, using well-known circuit analysis principles with a ratio R22/R23 of 5/4, the voltage Vx on line 6 may be expressed as Vx = 4Vs/9 + 5Vcap/9 where Vs is the amplified sensor output signal from the output of buffer 52. Accordingly, as described, sink operational transconductance amplifier 70 will sink current from capacitor C6 when 4Vs/9 + 5Vcap/9 > DB+ and source operational transconductance amplifier 72 will source current into capacitor C6 when 4Vs/9 + 5Vcap/9 < DB-. The rate at which current sinks from or sources to the capacitor C6 is proportional to the potential difference between the operational transconductance amplifier inputs according to the following equation i = gm(e2 - e1) where i is the sink or source current, gm is the transconductance gain, set in a manner well-known in the art to provide stable, predictable capacitor charging, e2 is the potential at the non-inverting input to the operational transconductance amplifier, and e1 is the potential at the inverting input. The operational transconductance amplifier reference voltages DB+ and DB- may be set to 2.6 volts and 2.4 volts, respectively. Functionally, when Vs, the signal from the output of buffer 52 increases sufficiently, such as near its peak such that 4Vs/9 + 5Vcap/9 is greater than DB+ per equation (2), the sink operational transconductance amplifier 70 will sink current from the capacitor C6 at a rate proportional to the changing potential between the inputs of operational transconductance amplifier 70 according to equation (4). The sink of current will decrease Vcap proportionately, which will decrease or at least reduce the increase of Vx, the described voltage at the operational transconductance amplifier inverting inputs, per equation (1). When Vs reaches its peak, and starts to decrease in magnitude, both components of Vx in equation (1) will be decreasing contemporaneously, causing Vx to drop rapidly in magnitude below DB+, at which time operational transconductance amplifier 70 will stop sinking current from capacitor C6. As DB- is significantly less than DB+, Vcap will remain constant while Vx is between DB+ and DB-, the voltage "deadband." Accordingly, the only component of Vx that changes while Vx is in the deadband is Vs, which is decreasing in magnitude. When Vs decreases to the extent necessary to reduce Vx below DB- according to equations (1) and (3), the source operational transconductance amplifier 72 will start sourcing current into capacitor C6, proportionally increasing Vcap which, through feedback resistor R23, will add to Vx, mitigating the decrease in Vx caused by the decreasing Vs. When Vs moves through its valley and starts to increase in magnitude, both components of Vx in equation (1) will be increasing contemporaneously, rapidly increasing Vx to a magnitude above DB-, so that shortly after the valley of Vs is reached, Vcap will no longer receive source current from operational transconductance amplifier 72. Vx will then be in the described voltage deadband in which Vcap is held constant until Vx again swings up to a value above DB+, as described. The resulting signal Vcap, which is passed to the next phase of the circuit of Figure 2b through buffer 74, gradually moves between high and low hold voltages based on the peaks and valleys of the sensor signal Vs, not based on any fixed threshold. The peaks and valleys need not be centred around a fixed reference voltage, but can swing significantly above and below modelled limits and still be detected by the deadband circuit. For instance, a significant peak increase in Vs will be appropriately compensated by a proportionally decreased Vcap so that shortly after the peak, Vx will still cross DB+, deactivating sink operational transconductance amplifier 70. Likewise, a significant decrease in the valley of Vs will be appropriately compensated by a proportionally increased Vcap so that shortly after the valley, Vx will still cross DB-, deactivating source operational transconductance amplifier 72. As discussed, Vcap is passed through buffer 74 to the next phase of the circuit of Figure 2b, called the hysteresis stage, consisting of, in this embodiment, resistors R24 and R26, amplifier 80, comparator 76, inverter 78, and two analogue switches 82 and 84. Vs, the amplified sensor output signal from the output of buffer 52 is also input to the hysteresis stage. Generally, the hysteresis stage compares Vs to the difference between a constant voltage and the deadband circuit output and thereby generates a squared signal recognisable by the digital controller 20, with a frequency representative of the rotational speed of the toothed wheel, such as one of the toothed wheels 16a-16d of Figure 1. The output signal from comparator 76 of the hysteresis circuit is passed to a digital processor port capable of interpreting the signal. For instance, with the wheel speed sensor of this embodiment, such a port must be capable of determining the frequency of the signal, which is representative of the angular rate of the wheel. In this embodiment then, the port is an input capture port, which is known generally in the art as a port which may be configured to detect signal edges or levels and provide certain servicing functions upon receiving such levels or edges. For example, the controller 20 may be software configured to generate an interrupt when an appropriate rising or falling edge is detected at the input capture port or when a high voltage level is detected. On the interrupt, a service routine may store the time of the interrupt and reset the interrupt for the next like event. Another routine may then process the interrupt times to determine the frequency of the square wave signal and thus the wheel angular rate. The use of wheel angular rate information is well known in the art of engine control. For instance, it may be communicated to a speedometer or odometer, or it may be used in conventional anti-lock brake control, traction control, or vehicle speed control. Returning to Figure 2b, aside from being communicated to controller 20, the output of comparator 76 is fed to conventional digital inverter 78, which inverts the signal and passes the inverted signal to the control input of analogue switch 84. The comparator output signal is fed directly (in uninverted form) to the control input of analogue switch 82. The operation of analogue switches 82 and 84 is well-known in circuit design: if the control input is high, the switch will close and the input will be passed to the output; otherwise the switch will be open. Accordingly in Figure 2b, if comparator 76 output is high (greater than approximately 3 volts), switch 82 will close and switch 84 will be open (as its input from the digital inverter 78 is low) and voltage HYST+ will be input to the non-inverting terminal of amplifier 80. Alternatively, if comparator output is low, switch 82 will be open, and switch 84 will be closed and voltage HYST- will be input to the non-inverting terminal of amplifier 80. HYST+ and HYST- are set to provide a hysteresis voltage range centred within the deadband voltage range defined by DB+ and DB-, wherein the magnitude of the hysteresis range is roughly 85 percent of the magnitude of the deadband range. As will be apparent to one with ordinary skill in the art, if the hysteresis range exceeds the deadband range, the output of comparator will not switch. Accordingly, to account for offsets in the circuitry that cannot be modelled, the hysteresis range is set an amount less than the deadband range. For example, in this embodiment, DB+ and DB- are set as 2.6 and 2.4 volts respectively. Accordingly, HYST+ is set to approximately 2.585 volts and HYST- is set to approximately 2.415 volts. Returning to the hysteresis circuit, the output Va of amplifier 80 may be expressed as follows Va = 9Vh/4 - 5Vcap/4 where Vh is the voltage input to the noninverting terminal of amplifier 80 and Vcap is the output of buffer 74 (the voltage across capacitor C6). Accordingly, as illustrated in Figure 3, the comparator 76 output will switch from low to high when 9(HYST-)/4 - 5Vcap/4 > Vs. When the comparator output switches high, HYST+ will be substituted for HYST- in equation (6), increasing Va of equation (5), for example as shown in Figure 3 at point A, providing that the next comparator output switch will occur a significant time after the next valley of Vs, when Vs rises above Va, for example at point B in Figure 3. At point B, HYST- will be substituted for HYST+ allowing for the next switch to occur a significant time after the next peak of Vs. The substitution of hysteresis voltages in the switching determination changes Va in direction to be symmetrical around Vs, so a substantially square wave may be produced by the comparison of the two signals. As shown in Figure 3, the signal from sensor 14 (Figure 2a) may not centre around a fixed reference. The perturbation in the signal of Figure 3 resulting in increased peaks C and D, and in increased valley E, is typical of that caused by a short tooth on the wheel that rotates in proximity to sensor 14. The range of the signal over one such signal period, such as from C to E to D in Figure 3, may not cross a fixed threshold voltage, such as that provided in the above-described prior art systems, and thus may not be detected. However, with the described embodiment, Va tracks the varying magnitude of the peaks and valley and, due to the deadband circuitry generating an output related to the peak and valley of the signal, and due to the provision of a threshold based on the deadband output, the crossing of Vs and Va provides a reliable indication of those peaks and valleys. In this embodiment, fault detection circuitry may be provided with the circuitry of Figures 2a and 2b. Information on whether the variable reluctance sensor is open-circuited, shorted to ground or shorted to the supply, such as the vehicle battery (not shown) are available with the described circuitry of Figures 2a and 2b. As detailed, the output line 104 of the divide-by-31 counter 62 is low when an open-circuited sensor has been detected. Further, the outputs 100 and 102 of window comparator are low respectively when a short to supply is detected and when a short to ground is detected. Lines 100-104 detail fault detection outputs for the wheel speed sensing circuitry of Figure 2a and 2b for a single vehicle wheel. However, in this embodiment, three like outputs may be generated for any of the remaining wheels. For instance, twelve outputs detailing specific fault information for all wheels of a four wheel vehicle may be generated by providing the above-described circuitry of Figures 2a and 2b to each of the wheels of a four wheel vehicle. To process these outputs, all twelve outputs are provided as inputs to a conventional NAND gate 86 and to fault decoding block 94. If at least one of these outputs is low (active), the output of NAND gate 86 will be high, turning off FET 88. Capacitor C7 will then discharge through resistor R28 pulling the non-inverting input of comparator 90 below the inverting input, set at 0.73*Vcc, after a short delay such as 75 microseconds in this embodiment, driving comparator output low in a manner generally known in the art of circuit design. The low output of comparator 90 is fed to fault data transmission block 92 to trigger communication of the fault to controller 20. The delay provided by the R-C circuit including R28 and C7 acts as a filter to prevent short duration voltage glitches which may have driven the output of gate 86 high from moving further through the circuit of Figure 2b. The output of comparator 90 is also fed as an input to latch 110, which may for example be a conventional D-type flip flop. A low input to latch 110 drives its output high, turning on transistor Q5, pulling the collector of Q5 low. The collector of Q5 is read by a controller port, for example where the port is software readable as an address in controller memory. If the collector is low, the port will appear as a logic "0" which indicates a fault in the wheel speed sensing circuit, as described. Otherwise, the port will read as a logic "1", indicating no such fault. Returning to the AND gate 86, if the fault indications input to the gate are all high (inactive), the gate output will be low, FET 88 will be on, keeping comparator 90 output high, indicating to fault data transmission block 92 that no fault data is available for communication to controller 20, and Q5 will output a high (inactive) signal to controller 20. The fault decoding block 94 may be used to convert the data input to it to a form communicable to controller 20 such as a multiplexed byte of data representative of the state of its inputs. This multiplexed byte may then be input to the fault data transmission block 92. When the output of comparator 90 is low, the controller 20 will read the port as low. In a well-known manner, such as that used for the serial peripheral interface of the Motorola eight-bit processor family (for example the MC68HC11 controller), the controller may then send a chip select signal to block 92 to prepare for the start of communication of the fault information. The controller may then send out clock pulses to block 92 which will trigger bit by bit serial communication of the fault information to controller 20. When communication is complete, the chip select line will drop low. The chip select line is also input to the conventional reset input of latch 110, such that the falling edge of the chip select signal will reset the latch 110, and thereby allow it to clear the port and wait for any future fault information that may again set the latch. The controller may, after receiving the data, demultiplex it to resolve the type of fault sensed, and the wheel at which it was sensed. Action may then be taken on the fault, such as by logging information on the fault in non-volatile memory (not shown), so that further information from the associated sensor may be ignored until serviced.

Claims: A method of generating a digital representation of an analogue signal which periodically fluctuates between maximum and minimum voltages, comprising the steps of sensing (70, D5, C6) a maximum voltage of the analogue signal; sensing (72, D6, C6) a minimum voltage of the analogue signal; generating (C6, 74, R24, R26) a limit signal which fluctuates between upper and lower limit values determined in relation to the sensed maximum and minimum voltages, respectively, such limit signal being maintained substantially at the upper limit value between the sensing of the maximum voltage and a point at which the analogue signal thereafter falls by a predetermined amount, and being maintained substantially at the lower limit value between the sensing of the minimum voltage and a point at which the analogue signal thereafter rises by the predetermined amount; calculating (80) a reference signal as a function of a predetermined voltage and the generated limit signal; generating (76) a digital signal having a high output level when the analogue signal is less than the reference signal and a low output level when the analogue signal is greater than the reference signal. A method according to claim 1, wherein the predetermined voltage is a first predetermined voltage when the digital output is high and a second predetermined voltage when the digital output is low. A method according to claim 1 or claim 2, wherein for an analogue voltage induced across first and second output terminals of a sensor (14) and which periodically fluctuates between minimum and maximum voltages, the method comprises the steps of sensing first and second voltages at respective first and second output terminals of the sensor; generating (46-50) an analogue output signal as a difference between a first amplified voltage, which is a predetermined function of the first voltage and a second amplified voltage, which is a predetermined function of the second sensed voltage; comparing (54,56) the first and second sensed voltages to a predetermined upper voltage limit and to a predetermined lower voltage limit; prohibiting change (107,58,S1) in the magnitude of the generated analogue output signal when the sensed voltage at the first and second terminals contemporaneously exceeds the predetermined upper voltage limit, thereby providing the maximum voltage of the analogue output signal; and prohibiting change (108,58,S1) in the magnitude of the generated analogue output signal when the predetermined lower voltage limit contemporaneously exceeds the sensed voltage at the first and second terminals, thereby providing the minimum voltage of the analogue output signal. Apparatus for generating a digital representation of an analogue voltage which periodically fluctuates between minimum and maximum voltages, comprising a sensor (14) including first and second output terminals providing respective first and second sensor output voltages; a difference amplifier (46-50) for generating an analogue output signal as a difference between a first amplified voltage, which is a predetermined function of the first sensor output voltage and a second amplified voltage, which is a predetermined function of the second sensor output voltage; comparing means (54,56) for comparing the first and second sensor output voltages to a predetermined upper voltage limit and a predetermined lower voltage limit; first holding means (107,58,S1) for holding the generated analogue output signal at a substantially constant magnitude when the first and second sensor output voltages contemporaneously exceed the predetermined upper voltage limit; second holding means (108,58,S1) for holding the generated analogue output signal at a substantially constant magnitude when the predetermined lower voltage limit contemporaneously exceeds the first and second sensor output voltages; a first peak detector (70,D5,C6) for sensing a maximum voltage of the analogue output signal; a second peak detector (72,D6,C6) for sensing a minimum voltage of the analogue output signal; a signal generator (C6,74,R24,R26) for generating a limit signal which fluctuates between an upper and a lower limit, wherein the upper limit is a predetermined function of the magnitude of the sensed maximum voltage and the lower limit is a predetermined function of the magnitude of the sensed minimum voltage; a signal summer (80) for generating a reference signal as a function of a predetermined voltage and the limit signal; a comparator (76) for comparing the analogue output signal to the reference signal, wherein the comparator output is high when the analogue output signal is less than the reference signal and the comparator output is low when the analogue output signal is greater than the reference signal. Apparatus according to claim 4, comprising a rate detector for detecting the rate of analogue output signal variation between the sensed maximum and minimum voltages, and wherein the signal generator generates a signal which fluctuates between the upper and lower limits at a rate in predetermined proportion to the detected rate. Apparatus according to claim 4 or 5, wherein the predetermined voltage is a first predetermined voltage when the comparator output is high and is a second predetermined voltage when the comparator output is low. Apparatus according to claim 4, 5 or 6, comprising a pull-up resistor (R2) having a predetermined pull-up resistance, connected between the first output terminal and a predetermined supply voltage; a pull-down resistor (R4) having a predetermined pull-down resistance, connected between the second output terminal and a predetermined ground voltage; and indicating means (60-64) for indicating an open sensor fault condition when a voltage in predetermined proportion to a voltage across the pull-down resistor is less than a fault threshold voltage for a predetermined period of time.

Inventors: CARPENTER CLIFFORD LEROY, HACH LARRY RAYMOND, WISE WILLIAM DOUGLAS, CARPENTER, CLIFFORD LEROY, HACH, LARRY RAYMOND, WISE, WILLIAM DOUGLAS
Applicants: DELCO ELECTRONICS CORP, DELCO ELECTRONICS CORPORATION
Application year: 1993
Main classification: G01D5
IPC codes: G01D5, G01P3, H03K5