Receiver

Abstract: In a receiver for use in demodulating a modulated wave modulated by a digital data signal arranged within a preselected channel to produce a reproduced data signal by the use of a local frequency signal of a local frequency, a VCO and a PLL circuit are intermittently put into active states with reference to an offset frequency between a channel frequency and the local frequency. The PLL circuit is put into the active state for a time interval determined by the offset frequency before reception of the preselected channel while the VCO is put into the active state during the active state of the PLL circuit and during reception of the preselected channel. The duration of the active state in the PLL circuit becomes long when the offset frequency does not fall within a predetermined range determined by predetermined offset frequencies and, otherwise, the duration of the active state in the PLL circuit becomes short. The offset frequency is detected by a frequency detector which produces a control signal appearing only when the offset frequency is present outside of the predetermined range. The control signal is sent to a control circuit for controlling battery saving operations of the VCO and the PLL circuit.

Description: This invention relates to a receiver which is operable to receive a modulated wave which carries a baseband signal of a binary digital signal and which may be subjected to FSK (Frequency Shift Keying), although this invention may not be restricted to the FSK. The invention seeks to provide a receiver which is capable of reducing power consumption in a phase locked loop circuit. It is a recent trend that such a receiver has become smaller in size with the development of the semiconductor integrated circuit technique. In a receiver of, for example, a superheterodyne type, a radio section usually comprises an element or elements which may be, for example, a high frequency amplifier, an intermediate frequency filter, and the like and which can not be simply manufactured by the semiconductor integrated circuit technique. Therefore, it has been pointed out that the size of the receiver comes near to a limit. In order to make such a receiver small in size and light in weight more and more, direct conversion, namely, quadrature detection, has been proposed to detect or demodulate a modulated wave which may convey a baseband signal of, for example, POCSAG codes. More specifically, a local oscillation frequency is controlled to be matched with a channel frequency received by a receiver and to extract a beat frequency between the local oscillation frequency and the channel frequency. With this receiver, the baseband signal alone is directly extracted from the beat frequency through a low pass filter (LPF) after amplitude limitation and is demodulated by a demodulator into a reproduced baseband signal. When the direct conversion is used to demodulate the modulated wave, the local oscillation frequency is substantially equal to the channel frequency with only a phase difference component or an offset signal component left between the local oscillation frequency and the channel frequency. Thus, the direct conversion can render an intermediate frequency into zero and, as a result, can avoid production of an image frequency. Therefore, such direct conversion dispenses with the necessity of any filter which has a high selectivity to attenuate the image frequency which might occur in a high frequency amplifier and an intermediate frequency amplifier. In addition, the above-mentioned receiver essentially comprises a channel filter for attenuating a jamming wave imposed on adjacent channels. However, it is possible to structure such a channel filter by an active low frequency pass filter which can be manufactured by the semiconductor integrated circuit technique. Heretofore, a proposal has been made about an FSK receiver which is combined with a Phase Locked Loop circuit (which is abbreviated to a PLL circuit hereinunder) so as to receive a modulated wave which subjects a baseband signal to FSK and which may be referred to as an FSK modulated wave. Specifically, the PLL circuit is used as a local oscillation circuit to produce a local oscillation signal of a local oscillation frequency which is substantially equal to each of the channel frequencies. At any rate, the PLL circuit can receive a plurality of channel frequencies by the use of a single quartz crystal which cooperates with a frequency divider, a read-only memory (ROM), and the like. In the meanwhile, let such an FSK receiver be used as a paging receiver in a paging system which has a plurality of zones to which the channel frequencies are individually preassigned. The above-mentioned receiver which comprises the PLL circuit can receive each of the channel frequencies even when the channel frequencies are changed from one to another due to movement of the receiver from one zone to another zone. However, the PLL circuit consumes large electric power so as to carry out a PLL operation. In other words, the receiver of the above-mentioned type is disadvantageous in that power consumption becomes large in the PLL circuit. As a result, the paging receiver driven by a battery of a small capacity has a very short life time due to the large power consumption in the PLL circuit. WO-A-91/19357 discloses a battery saving method for a radio receiver in which sections are switched on or off selectively in accordance with stored timing parameters. This invention seeks to provide a receiver which is capable of reducing power consumption even when a PLL circuit is used. This invention also seeks to provide a receiver of the type described, which is capable of generating a wide variety of local oscillation frequencies by the use of a single quartz crystal. Yet again, this invention seeks to provide a receiver of the type described, which is applicable to a paging receiver and which has a long life time. The invention is set out in Claim 1. Further features are characterised in the dependent claims. Preferred features of the present invention are now described, by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a receiver according to a preferred embodiment of this invention; Fig. 2 is a time chart for use in describing operation of a part of the receiver illustrated in Fig. 1; Fig. 3 is a block diagram of a demodulator included in the receiver illustrated in Fig. 1; Fig. 4 is a block diagram of a frequency detector included in the receiver illustrated in Fig. 1; Fig. 5 is a block diagram of a demodulation circuit for use in the frequency detector illustrated in Fig. 4; Fig. 6 is a time chart for use in describing operation of the frequency detector illustrated in Fig. 4; Fig. 7 is a block diagram of a low pass filter included in the frequency detector illustrated in Fig. 4; Fig. 8 is a block diagram of an average calculation circuit included in the frequency detector illustrated in Fig. 4; Fig. 9 is a block diagram of an offset circuit included in the frequency detector illustrated in Fig. 4; Fig. 10 is a block diagram of a comparator included in the frequency detector illustrated in Fig. 4; Fig. 11 is a time chart for use in describing operation of a control circuit included in the receiver illustrated in Fig. 1; Fig. 12 is a block diagram of a PLL circuit included in the receiver illustrated in Fig. 1; and Fig. 13 is a block diagram of a control circuit included in the receiver illustrated in Fig. 1. Referring to Fig. 1, a receiver according to a preferred embodiment of this invention is supplied with an input signal which may be an FSK modulated wave modulated by a baseband signal of, for example, POCSAG codes or the like and which is obtained by subjecting the baseband signal to FSK. In this connection, the FSK modulated wave is obtained by modulating a channel frequency by the baseband signal. From this fact, it is readily understood that the baseband signal itself is composed of a digital data signal specified by a mark or a space. More particularly, the receiver comprises a direct converter 20 which receives the FSK modulated wave from an antenna (not shown) and which produces a reproduced data signal in a manner to be described later in detail. In the direct converter 20, the FSK modulated signal is sent as the input signal to a high frequency amplifier 21 to be amplified into an amplified modulated signal which is delivered to first and second mixers 22 and 23 connected to a phase shifter 24 given a local frequency signal from a local frequency oscillation circuit 25 as described later in detail. The local frequency signal has a local frequency. At any rate, the phase shifter 24 shifts a phase of the local frequency signal to produce first and second local signals both of which have phases different from each other by 90°, namely, π/2 radians. Specifically, the first local signal is obtained by rotating the phase of the local frequency signal by +45° while the second local signal is obtained by rotating the phase of the local frequency signal by -45°. As a result, the first local signal has a frequency identical with that of the second local signal with the local frequency of the local frequency signal kept unchanged. Herein, it is to be noted that the local frequency of the local frequency signal is substantially equal to the channel frequency which is equal to a non-modulated wave frequency. The first and the second mixers 22 and 23 carry out frequency conversion of the amplified modulated signal by mixing the amplified modulated signal with the first and the second local signals to produce first and second frequency converted signals, respectively. Inasmuch as each of the first and the second local signals has its frequency substantially equal to the channel frequency, as mentioned before, each of the first and the second frequency converted signals that appears as a beat signal having a beat frequency specifies the baseband signal. The first and the second frequency converted signals are sent to first and second low pass filters (LPF's) 26 and 27 in which first and second baseband components alone are subjected to band restriction of a noise signal to be extracted from the first and the second frequency converted signals. The first and the second baseband components are supplied to first and second limiters 28 and 29 to be digitalized into first and second baseband digital signals I and Q which may be referred to as in-phase and quadrature baseband signals, respectively. The first and the second baseband digital signals I and Q have the phase differences of 90° relative to each other and are sent to a demodulator 31. Referring to Fig. 2 together with Fig. 1, let the second baseband digital signal Q convey the digital data signal as depicted at DQ in Fig. 2 and be demodulated into a demodulated data signal L by the demodulator 31. This shows that the digital data signal DQ acts as a modulation signal to modulate the second baseband digital signal depicted at Q in Fig. 2. In the illustrated example, no digital data signal is included in the first baseband digital signal I. Referring to Fig. 3 in addition to Figs. 1 and 2, the demodulator 31 is structured by a delay flip flop (which is abbreviated to a D F/F) 32 which has a data input terminal D, a clock terminal CL, and an output terminal Qo. In the illustrated example, the data input terminal D of the D F/F 32 is given the second baseband digital signal Q as illustrated in Fig. 2, while the clock terminal CK is given the first baseband digital signal I as shown in Fig. 2. In this event, the second baseband digital signal Q is sampled at each leading edge of the first baseband digital signal I, as symbolized by arrows in Fig. 2 and, as a result, the second baseband digital signal Q is converted into the demodulated data signal L which appears through the output terminal Qo of the D F/F 32. Although the second and the first baseband digital signals Q and I are given to the data input terminal D and the clock terminal CL, respectively, the data input terminal D and the clock terminal CL of the D F/F 32 may be considered as the clock terminal CL and the data input terminal D for the first and the second baseband digital signals I and Q, respectively. Consequently, the first baseband digital signal I can be also demodulated into the demodulated data signal by the illustrated D F/F 32 in a manner similar to that mentioned in conjunction with the second baseband digital signal Q when the digital data signal is included in the first baseband digital signal I. Thus, the demodulated data signal L includes both of the digital data signals carried by the first and the second baseband digital signals I and Q. The demodulated data signal is sent to a low pass filter (LPF) 35 to remove a noise component and is thereafter given to a comparator 36 to be digitalized into an output binary digital signal or the reproduced data signal. As shown in Fig. 1, the receiver comprises a frequency detector 41 and a control circuit 42 together with the direct converter 20 and the local frequency oscillation circuit 25. Referring to Fig. 4, the frequency detector 41 is connected to the direct converter 20. Although the second baseband digital signal Q is given to the frequency detector 41 in the example being illustrated, the first baseband digital signal I may be supplied to the frequency detector 41. Briefly, the frequency detector 41 serves to detect whether or not each of the first and the second baseband digital signals I and Q has a frequency falling with a predetermined frequency range and to produce a control signal FL, as will become clear later. More specifically, the illustrated frequency detector 41 comprises a demodulation circuit 411 which is supplied with the second baseband digital signal Q to produce a sequence of pulses D. Temporarily referring to Figs. 5 and 6 along with Fig. 4, the demodulation circuit 411 is composed of a delay detection circuit which comprises a delay circuit 411a of a delay time T and an Exclusive OR gate 411b. Herein, the second baseband digital signal Q has first and second pulse frequencies which are assigned to the space and the mark on carrying out the FSK, as shown at a top line of Fig. 6. Specifically, a first period of the first pulse frequency is equal to a half of a second period of the second pulse frequency. The delay time T is assumed to be shorter than a half of the first period. Moreover, it is assumed that the second baseband digital signal Q which is sent from the second limiter 29 includes an offset frequency ΔF representative of a frequency deviation from the channel frequency. In this connection, each of the first and the second pulse frequencies is specified by ± FD - ΔF, where FD is representative of a maximum frequency deviation on the FSK. From this fact, it is readily understood that the Exclusive OR gate 411b produces a sequence of pulses D each of which has a pulse width equal to T, as illustrated along a second line of Fig. 6. Thus, the demodulation circuit 411 supplies the pulse sequence D to a low pass filter 412 shown in Fig. 4. Referring to Fig. 7 together with Figs. 4 and 6, the low pass filter (LPF) 412 integrates the pulse sequence D into an integrated output signal O as shown along a third line of Fig. 6. The integrated output signal O is given from the LPF 412 to an average calculation circuit (abbreviated to AVE in Fig. 4) 413 on tne one hand and to first and second comparators 414 and 415 on the other hand. It should be noted that the integrated output signal O has an amplitude proportional to the pulse frequency of the second baseband digital signal Q, as is apparent from Fig. 6, and may be produced as an output voltage from the LPF 412. As shown in Fig. 7, the LPF 412 comprises first and second resistors 412a and 412b connected in series to each other, a capacitor 412c having a terminal connected to the second resistor 412b and another terminal grounded, and a comparator 412d having an input terminal connected to the terminal of the capacitor 412c and another input terminal connected to an output terminal of the comparator 412d. An additional capacitor 412e is connected between the output terminal of the comparator 412d and a point of connection between the first and the second resistors 412a and 412b. With this structure, it is possible to carry out the integration operation of the pulse sequence D given to the first resistor 412a and to produce the integrated output signal O through the output terminal of the comparator 412d in a known manner. In the mean time , the second baseband digital signal Q has its frequency variable between FD - ΔF and |- FD - ΔF|, where ΔF is indicative of the offset frequency, as mentioned before. When such a second baseband digital signal Q is integrated by the LPF 412, the frequency of the integrated output signal O is averaged by the LPF 412 into an average frequency between FD - ΔF and | FD - ΔF|. As a result, the offset frequency is cancelled out of the average frequency of the integrated output signal O. The average frequency therefore becomes equal to FD. Referring to Fig. 8, the average calculation circuit 413 is supplied with the integrated output signal O to calculate an average voltage A of the integrated output signal O. As shown in Fig. 8, the average calculation circuit 413 is structured by a time constant circuit which comprises a resistor 413a and a capacitor 413b and which has a time constant determined by the resistor 413a and the capacitor 413b in consideration of a reception band width and the like. The illustrated average calculation circuit 413 forms an RC integration circuit of a first order, as readily understood from Fig. 8. Referring to Fig. 9 afresh and Fig. 4 again, the average voltage A is sent to an offset circuit 416 which adds predetermined voltages of ±ΔV to the average voltage A. Each of the predetermined voltages ±ΔV corresponds to a predetermined offset frequency, as will become clear as the description proceeds, and may be called predetermined offset voltages. For this purpose, the offset circuit 416 comprises a voltage follower 416a having first and second input terminals and an output terminal which is connected to one of the first and the second input terminals in common, as illustrated in Fig. 9. In the illustrated circuit 416, the average voltage A is given to the remaining one of the input terminals of the voltage follower 416a. In addition, the output terminal of the voltage follower 416a is connected to first and second output resistors 416b and 416c which are connected to first and second constant current circuits 416d and 416e, respectively. The first and the second output resistors 416a and 416b give the predetermined voltages ±ΔV to the average voltage A. Consequently, first and second output voltages V H and V L are produced through a first point of connection between the first constant current circuit 416d and the first output resistor 416b and through a second point of connection between the second constant current circuit 416e and the second output resistor 416c, respectively. When the predetermined voltages ±ΔV are added to the average voltage A, the first and the second output voltages V H and V L are represented by: V H = A + ΔV and V L = A - ΔV. Referring to Fig. 4 again and Fig. 10 anew, the first and the second output voltages V H and V L are supplied to the first and the second comparators 414 and 415 which are given the integrated output signal O from the LPF 412. Each of the first and the second comparators 414 and 415 is similar in structure to each other, although the first comparator 414 alone is illustrated in Fig. 10. The first comparator 414 comprises first and second transistors 414a and 414b having emitters connected in common to a constant current source 414c, collectors connected to first and second resistors 414d and 414e, respectively, and bases supplied with the integrated output signal O and either one of the first and the second output voltages V H and V L , respectively. The collector of the second transistor 414b is connected to an additional transistor 414f of a PNP type which is connected to an additional resistor 414g in series. With this structure, a combination of the first and the second transistors 414a and 414b, the constant current source 414c, the first and the second resistors 414d and 414e is operable as a differential amplifier while the additional transistor 414f and the additional resistor 414g is operable as a level shifter. In such a comparator, the differential amplifier supplies the level shifter with an internal voltage determined by a difference between the integrated output voltage O and each of the first and the second output voltages V H and V L represented by Equations 1 and 2 mentioned above while either a first shifter output voltage V OH or a second shifter output voltage V OL appears at a point of connection between the additional transistor 414f and the additional resistor 414g. In any event, it is assumed that the first shifter output voltage V OH takes a high level when the integrated output voltage O is lower than the first output voltage V H while the second shifter output voltage V OL takes a high level when the integrated output voltage O is higher than the second output voltage V L . As illustrated in Fig. 6, the first shifter output voltage V OH takes a low level each time when the integrated output voltage O is higher than the first output voltage V H while the second shifter output voltage V OL takes the high level when the integrated output voltage O exceeds the second output voltage V L . High level durations of the first and the second shifter output voltages V OH and V OL are partially overlapped with each other, as depicted at C in Fig. 6. Referring back to Fig. 4, the first and the second shifter output voltages V OH and V OL are supplied to a NAND gate 416 to produce the control signal FL. As readily understood from Fig. 4, the control signal FL produced by the NAND gate 418 takes the low level only when both the first and the second shifter output voltages V OH and V OL are put into the high levels. In other words, the control signal FL intermittently becomes the low level for the high level durations depicted at C in Fig. 6. This means that the control signal FL takes the low level when the integrated output voltage O falls within the predetermined voltage range between +ΔV and -ΔV. Stated otherwise, the control signal FL is put into the high level when the integrated output voltage O exceeds the predetermined voltage range defined by the predetermined offset voltages +ΔV and -ΔV. An operation of the frequency detector 41 mentioned above will be described in more detail on the assumption that the demodulation circuit 411 illustrated in Figs. 4 and 5 has a demodulation sensitivity depicted at KD (V/kHz). In this event, the integrated output voltage O of the LPF 412 is given by: O = KD x Δf. Accordingly, when the integrated output voltage O, namely, KD x Δf is smaller than the predetermined offset voltage depicted at ΔV, the control signal FL takes the low level. For example, let KD = 10 mV/kHz and ΔV = 10 mV. In this case, the control signal FL takes the high level when the Δf is higher than 1 kHz. As is apparent from Fig. 4, the control signal FL is supplied to the control circuit 42 which is given the reproduced digital signal from the comparator 36, as shown in Fig. 1. It may be understood for the time being that the control circuit 42 serves to control a battery saving operation in the direct converter 20 and the local frequency oscillation circuit 25, as will become clear later. Referring to Fig. 11 along with Fig. 1, it is assumed that the direct converter 20 is supplied with the input signal which comprises first through third groups of the data signals, as shown along a top line of Fig. 11 and that the control circuit 42 is operated to extract the third group of the data signals from the input signal, as symbolized by circles in Fig. 11. The third group of the data signals may be considered as being arranged in a preselected channel. In this case, the control circuit 42 delivers a first battery saving control signal RFBS to the direct converter 20, as shown along a second line of Fig. 11. In addition, the control circuit 42 delivers second and third battery saving control signals VCOBS and PLLBS to the local frequency oscillation circuit 25 (Fig. 1) in response to the control signal FL, as illustrated along third and fourth lines of Fig. 11. Turning back to Fig. 1 again, the local frequency oscillation circuit 25 comprises a PLL circuit 50 connected to the control circuit 42, a voltage controlled oscillator (VCO) 51 connected to the control circuit 42 and the PLL circuit 50, and a loop filter 52 between the PLL circuit 50 and the VCO 51. The VCO 51 is connected to the PLL circuit 50 to feed the local frequency signal back to the PLL circuit 50. Thus, the VCO 51, the loop filter 52, and the PLL circuit 50 forms a phase locked loop which is put into an active state and an inactive state by the second and the third battery saving control signals VCOBS and PLLBS. Specifically, the first battery saving control signal RFBS is sent to a power source (not shown) which intermittently puts the direct converter 20 into an active state while the second and the third battery saving control signals VCOBS and PLLBS are sent to the VCO 51 and the PLL circuit 50, respectively. Referring to Fig. 11, the first battery saving control signal RFBS takes the high level for a time interval of the first through the third groups at first and thereafter for a following time interval slightly longer than a time interval of the third group. Such a first battery saving control signal RFBS can be produced by the use of a conventional technique. The third battery saving control signal PLLBS is concerned with the first battery saving control signal RFBS and the control signal FL sent from the frequency detector 41 (Figs. 1 and 4) while the second battery saving control signal VCOBS is produced with reference to the third battery saving control signal PLLBS and the control signal FL. More specifically, the third battery saving control signal PLLBS is specified by a sequence of pulses each of which is determined by a leading edge and a trailing edge. A first one of the pulses in the third battery saving control signal PLLBS appears in synchronism with the first battery saving control signal RFBS while each of second and third ones of the pulses in the third battery saving control signal PLLBS has a leading edge synchronized with the first battery saving control signal RFBS and a trailing edge positioned before the third group is received. In other words, the third battery saving control signal PLLBS has a high level duration before reception of the third group. The high level duration is changed from T1 to T0 after reception of the control signal FL, as depicted at a fourth one of the pulses in the third battery saving control signal PLLBS in Fig. 11. As readily understood from Fig. 11, the control signal FL is produced when the frequency deviation between the local frequency (depicted at VCOf) and the channel frequency becomes equal to ΔF which is determined by each of the predetermined offset voltage ΔV. On the other hand, the second battery saving control signal VCOBS has a leading edge synchronized with the leading edge of each pulse of the third battery saving control signal PLLBS and a trailing edge synchronized with that of the first battery saving control signal RFBS. From Fig. 11, it is understood that the third battery saving control signal PLLBS has a high level duration which is shorter than that of the second battery saving control signal and which becomes long after reception of the control signal FL. This means that the high level duration of each pulse in the third battery saving control signal PLLBS is very much shorter than that of the conventional third battery saving control signal depicted by broken lines. Likewise, the second battery saving control signal VCOBS is also shorter than that of the conventional second battery saving control signal specified by broken lines in Fig. 11. Referring back to Fig. 1, the first, the second, and the third battery saving control signals RFBS, VCOBS, and PLLBS illustrated in Fig. 11 are delivered to the power source of the direct converter 20, the VCO 51, and the PLL circuit 50, respectively. In consequence, the direct converter 20 is intermittently operated at least for the time interval longer than a reception time interval of the third group. Similarly, the VCO 51 is also put into an active state during reception of the second battery saving control signal VCOBS and is continuously operated during reception of the third group. However, it is to be noted that the third battery saving control signal PLLBS lasts for the time interval T1 and is extinct before reception of the third group, as illustrated in Fig. 11. Therefore, the PLL circuit 50 is put into an inactive state during reception of the third group. Stated otherwise, the PLL circuit 50 is rendered into a high impedance state during reception of the third group to supply a constant voltage to the loop filter 52 (Fig. 1). In addition, when the integrated output voltage O exceeds the predetermined offset voltage ΔV and the control signal FL is consequently given to the control circuit 42, the PLL circuit 50 is put into the active state for the time interval T0 longer than the time interval T1. This means that the PLL circuit 50 is operated for a very short time when the frequency deviation is.;small between the local frequency and the channel frequency, while the PLL circuit 50 is operated for a comparatively long time when the frequency deviation is large. This is because the PLL circuit 50 is put into a pull-in state of synchronization with a very short time when the frequency deviation is small and, otherwise, the PLL circuit 50 is put into the pull-in state after the lapse of a long time. Thus, the illustrated receiver can reliably establish synchronization even when the offset voltage exceeds the predetermined range. Referring to Fig. 12, the PLL circuit 50 comprises a reference generator 251 for generating a reference oscillation signal of an oscillation frequency of, for example, 10 kHz and a frequency indication ROM 252 for indicating a frequency to be received to produce a frequency indication signal S of, for example, 14 bits which may indicate a frequency division factor. The reference generator 251 includes a single quartz crystal. The frequency indication signal is sent to a PLL controller 253 which is turned on or off in response to the third battery saving control signal PLLBS given from the control circuit 42 (Fig. 1). During the on-state, the PLL controller 253 supplies a variable frequency divider 254 and a reference frequency divider 255 with a division factor signal D. The variable frequency divider 254 is given the local frequency from the VCO 51 switched by the second battery saving control signal VCOBS while the reference frequency divider 255 is supplied with the reference oscillation signal. Thus, the variable frequency divider 254 divides the local frequency into a divided local frequency while the reference frequency divider 255 divides the reference oscillation frequency into a divided reference frequency. Both the divided local frequency and the divided reference frequency are supplied to a phase comparator 256 to be subjected to phase comparison. The phase comparator 256 compares the phases of the divided local frequency and the divided reference frequency with each other to produce a phase error signal PD representative of a phase error between the divided local frequency and the divided reference frequency. The phase error signal PD is sent through the loop filter 52 to the VCO 51. The phase error signal PD is given to the VCO 51 as a control voltage and controls the local frequency in response to the control voltage FL. The VCO feeds the local frequency back to the PLL circuit 25 so that the phase error is always kept constant. In the illustrated example, the variable frequency divider 254 can change the frequency division factor in response to the division factor signal D sent from the PLL controller 253. This shows that the local frequency can be also changed from one to another in the VCO 51. Herein, when the frequency indication signal S is composed of 14 bits, a maximum local frequency is given by: (2 15 - 1) x 10 kHz = 327.67 MHz. Referring to Fig. 13, the control circuit 42 is supplied with the reproduced data signal RD and the control signal FL from the comparator 36 (Fig. 1) and the frequency detector 41 to produce the first through the third battery saving control signals RFBS, VCOBS, and PLLBS, as shown in Fig. 11. To this end, the control circuit 42 comprises a synchronization circuit 421 and an intermittent operation control circuit 422. The synchronization circuit 421 establishes bit and frame synchronization in response to the reproduced data signal RD in a known manner to produce a sequence of timing signals TM. The intermittent operation control circuit 422 is given the timing signal sequence TM to produce the first battery saving control signal RFBS and to produce the third group, as shown in Fig. 11. Likewise, the intermittent operation control circuit 422 produces the third battery saving control signal PLLBS which is determined by the timing signals and the control signal FL. Such a third battery saving control signal PLLBS can be produced by measuring the time intervals T1 and T2 with reference to the timing signals and the control signal FL and by putting a timer into a set state or a reset state on the basis of a result of measurement of the time intervals T1 and T2. Therefore, the third battery saving control signal PLLBS can be readily produced by combining known circuit elements. In addition, the second battery saving control signal VCO can be produced by a flip flop which is put in a set state at a leading edge of the third battery saving control signal PLLBS and in a reset state at a trailing edge of the first battery saving control signal RFBS. In summary, the preferred embodiment of receiver includes all or some of the following features. In the receiver, which may be for use in demodulating a modulated wave modulated by a digital data signal arranged within a preselected channel to produce a reproduced data signal by the use of a local frequency signal of a local frequency, a VCO and a PLL circuit are intermittently put into active states with reference to an offset frequency between a channel frequency and the local frequency. The PLL circuit is put into the active state for a time interval determined by the offset frequency before reception of the preselected channel while the VCO is put into the active state during the active state of the PLL circuit and during reception of the preselected channel. The duration of the active state in the PLL circuit becomes long when the offset frequency does not fall within a predetermined range determined by predetermined offset frequencies and, otherwise, the duration of the active state in the PLL circuit becomes short. The offset frequency is detected by a frequency detector which produces a control signal appearing only when the offset frequency is present outside of the predetermined range. The control signal is sent to a control circuit for controlling battery saving operations of the VCO and the PLL circuit. While this invention has thus far been described in conjunction with a preferred embodiment thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, the modulated wave which is given to the receiver may not be restricted to the FSK modulated wave but may be a PSK modulated wave or the like. In addition, a quadrature modulated wave may be also supplied to the receiver. Furthermore, the local oscillation frequency circuit 25 may generate an invariable local frequency.

Claims: A receiver operable in response to a modulated signal which is subjected to modulation by a baseband digital signal and which has a channel frequency, said receiver comprising demodulating means (20) supplied with said modulated signal and a local frequency signal of a local frequency for carrying out demodulation of said modulated signal by the use of said local frequency signal to produce the baseband digital signal as a demodulated signal, and local signal supplying means (25); characterised in that: the local signal supplying means (25) has a phase locked loop (50) selectively put into an inactive state and an active state, for supplying said local frequency signal to said demodulation means; and said receiver further comprises: frequency difference detecting means (41) coupled to said demodulating means for detecting a frequency difference between said channel frequency and said local frequency to judge whether or not said frequency difference falls within a predetermined range and to produce a control signal (FL) when said frequency difference exceeds said predetermined range; and control means (42) coupled to said frequency difference detecting means (41) and said local signal supplying means (25) for controlling said local signal supplying means (25) to put said phase locked loop (50) of the local signal supplying means (25) into the active state in the presence of said control signal so as to keep said local frequency under control of said phase locked loop (50) and, on the other hand, to put said phase locked loop (50) into the inactive state in the absence of said control signal so as to keep said local frequency with the phase locked loop (50) kept inactive. A receiver as claimed in Claim 1, wherein said local signal supplying means (25) comprises: a voltage controlled oscillator (51) coupled to said controlling means (42) to produce said local frequency signal; a PLL circuit (50) which is coupled to said control means (42) and which has frequency generating means for generating a predetermined reference frequency, said PLL circuit (50) being also coupled to said voltage controlled oscillator (51) to form said phase locked loop and producing a phase error signal (PD) between a predetermined local frequency related to said local frequency signal and said predetermined reference frequency under control of said control means (42); and means (52) for supplying said phase error signal (PD) to said voltage controlled oscillator (51) to control said local frequency signal. A receiver as claimed in Claim 2, wherein said frequency generating means of said PLL circuit comprises: a reference frequency generator (251) for generating a reference frequency signal of a reference frequency; a frequency divider (255) for frequency dividing said reference frequency into said predetermined reference frequency; said PLL circuit further comprising: a variable divider (254) for dividing said predetermined local frequency into said local frequency; a phase error detection circuit (256) for comparing said predetermined reference frequency with said local frequency to produce said phase error signal. A receiver as claimed in Claim 1, 2 or 3 wherein said frequency difference detecting means (41) comprises: detection means (412) for detecting said demodulated signal to produce a detected signal (0) which has a detected voltage; average means (413) for receiving said detected signal and for calculating an average voltage of said demodulated signal; adding means (416) for adding first and second predetermined offset voltages to said average voltage to produce first and second output voltages (V H , V L ) representative of sums of each of said first and said second predetermined voltages and said average voltage; and means (414,415,418) for comparing said first and said second output voltages (V H , V L ) with said detected signal (0) to produce said control signal (FL) on the basis of a result of the comparison. A receiver as claimed in any preceding claim, wherein said control means (42) comprises: signal supplying means (422) for receiving a reproduced data signal (RD) and said control signal (FL) and for supplying said local signal supplying means (25) with an operation control signal (PLLBS) for controlling said PLL (50) specified by a sequence of pulses which has a predetermined width in the absence of said control signal (FL) and an additional pulse width longer than said predetermined width in the presence of said control signal (FL); said local signal supplying means (25) being adapted to carry out phase locked operation for a time interval determined by said operation control signal (PLLBS). A receiver as claimed in any preceding claim, wherein said control means (42) is adapted to produce an operation control signal which includes a primary battery saving control signal (VCOBS) which defines a generation duration of said local frequency signal and an additional battery saving control signal (PLLBS) which defines an operation duration of phase locked operation shorter than said generation duration; and said local signal supplying means (25) comprises: a voltage controlled oscillator (51) for receiving said primary battery saving control signal (VCOBS) and for generating said local frequency signal during a first time interval defined by said primary battery saving control signal; and a PLL circuit (50) which is coupled to said voltage controlled oscillator (51) for carrying out said phase locked operation during a second time interval defined by said additional battery saving control signal (PLLBS). A receiver as claimed in Claim 6, wherein each of the generation duration of the local frequency signal and the operation duration of the phase locked operation becomes long after reception of the control signal (FL) in said control means (42) in comparison with each of the generation duration and the operation duration before said control signal (FL) is received by said control means (42).

Inventors: MINAMI YOICHIRO, MINAMI, YOICHIRO, Minami, Yoichiro, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H03D3
IPC codes: H03D3, H04W88, H04W52