Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices

Abstract: A plurality of identical circuit blocks (PG0-PG15) is supplied with address signals (A0-A3,A0N-A3N) and each one generating a respective selection signal (P0-P15) which is activated by a particular logic configuration of said address signals (A0-A3,A0N-A3N) for the selection of a particular row (WL0-WL15) of the matrix; each one of said circuit blocks (PG0-PG15) also generates a carry-out signal (C00-C015) which is supplied to a carry-in input (CI0-CI15) of a following circuit block (PG0-PG15) and is activated when the respective selection signal (P0-P15) is activated; a first circuit block (PG0) of said plurality of circuit blocks (PG0-PG15) has the respective carry-in input (C10) connected to a reference voltage (GND); each of said circuit blocks (PG0-PG15) is also supplied with a control signal (E), which is activated by a control circuitry (6) of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row (WL0-WL15) is addressed, to enable the activation of the respective selection signal (P0-P15) if the carry-out (C00-C014) signal supplying the respective carry-in input (CI1-CI15) is activated, so that two adjacent rows (WL0-WL15) can be simultaneously selected.

Description: The present invention relates to a double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for Flash EEPROM devices. In the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The reason for the high probability of defects of this type resides in that in a semiconductor memory device the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits. In order to avoid that the presence of a limited number of defective memory elements on many millions forces the rejection of the entire chip, and therefore to increase the manufacturing process yield, the technique is known of providing for the manufacture of a certain number of additional memory elements, commonly called "redundancy memory elements", to be used as a replacement of those elements that, during testing of the memory device, prove defective; the selection circuits, with which the integrated component must necessarily be provided, and which allow the abovementioned functional replacement of a defective memory element with a redundancy memory element are indicated as a whole with the name of "redundancy circuitry", while the set of redundancy memory elements and circuitry is defined for short as "redundancy". The redundancy circuitry comprises programmable non-volatile memory registers suitable to store those address configurations corresponding to the defective memory elements; such registers are programmed once and for all during the memory device testing, and must retain the information stored therein even in absence of the power supply. In practical implementations of redundancy, both rows ("word lines") and columns ("bit lines") of redundancy memory elements are provided in the memory matrix; each redundancy word line or bit line is associated to a respective non-volatile memory register, wherein the address of a defective word line or bit line is stored so that, whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected. As far as matrix word lines are concerned, it has been recognized that the most frequent defect consists in short-circuits between adjacent word lines: this situation is easily detected during testing because when the selection of one of two short-circuited word lines is attempted, the potential of such word line cannot raise to the designed value, being linked by the short-circuit to the potential of the adjacent non-selected word line. When during testing a matrix word line is found that is short-circuited to an adjacent one, both of the two defective matrix word lines must be replaced by two redundancy word lines; from then on the two defective matrix word lines will never be selected, neither during programming nor during reading. The implementation of word line redundancy in Flash Electrically Erasable Programmable ROM devices (shortly, Flash EEPROMs) poses some problems. Flash EEPROM devices are characterized by being not only electrically programmable, but also electrically erasable; as EPROM devices, they are programmed on a per-byte basis, raising to a high voltage (typically 12 V) the selected word line; erasing is instead a bulk operation, performed on the whole memory matrix, or at least on sectors of it, by switching the common source line of the memory matrix to the high voltage, while keeping all the word lines to ground. To prevent memory elements which are already in the non-programmed condition from being overerased, with the unacceptable consequence of obtaining, after the erasure, memory elements with negative threshold voltages, it is necessary to carry out a preliminary programming step of all the memory elements in the memory matrix, or in the matrix sector that is to be erased. In this way, all the memory elements are put in a common starting condition, so that after erasure all the memory elements have approximatively the same threshold voltage. Such preliminary programming is called "preprogramming" or "preconditioning". Preprogramming, similarly to normal programming, is performed on a per-byte basis, sequentially addressing the word lines of the memory matrix. This implies that, if defective word lines which have been replaced by redundancy word lines exist, since when such defective word lines are addressed the redundancy circuitry generates a deselection signal that prevents the defective word lines from being selected, the memory elements connected to them can never be preprogrammed; on the other hand, since erasure does not require the selection of the word lines, the memory elements connected to defective word lines are subjected to erasure. This means that, if the traditional word line redundancy approach is utilized in a Flash EEPROM device, the memory elements connected to defective word lines are destined to acquire more and more negative threshold voltages. To overcome such a problem, the word line redundancy approach utilized in Flash EEPROMs provides for the inhibition of the defective word line deselection signal, generated by the redundancy circuitry, when, during preprogramming, a defective word line is addressed: in this way, when during preprogramming a defective word line is addressed, the memory elements connected to it can be effectively programmed. This however requires not only the currently addressed defective word line is effectively selected, but also the selection of an adjacent word line: since in fact it is assumed that the defective word line is short-circuited to an adjacent word line, if said adjacent word line is not selected and its potential is kept to ground, the potential of the addressed defective word line cannot raise to the designed value necessary for the programming of the memory elements (12 V); in other words, two adjacent word lines that are short-circuited one to another must be simultaneously selected during preprogramming. This requirement is responsible of a significant increase in complexity of the word line address decoding and selection circuitry, which means an increase in the overall chip size. In view of the state of art described, the object of the present invention is to realize a row address decoding and selection circuitry which allows the simultaneous selection of two adjacent defective word lines during the preprogramming phase, with the minimum increase in the overall chip size. According to the present invention, such object is attained by means of a Row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy which comprises a matrix of memory elements located at the intersection of columns and rows of said matrix, comprising a plurality of identical circuit blocks supplied with address signals and each one generating a respective selection signal which is activated by a particular logic configuration of said address signals for the selection of a particular row of the matrix, characterized in that each one of said circuit blocks also generates a carry-out signal which is supplied to a carry-in input of a following circuit block and is activated when the respective selection signal is activated, a first circuit block of said plurality of circuit blocks having the respective carry-in input connected to a reference voltage, each of said circuit blocks being also supplied with a control signal , which is activated by a control circuitry of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row is addressed, to enable the activation of the selection signal of said following circuit block if its carry-in input is activated, so that two adjacent rows are simultaneously selected. The double-row address decoding and selection circuitry according to the present invention allows the simultaneous selection of two adjacent defective rows (word lines) during the preprogramming phase. Furthermore, being made up of a plurality of identical circuital blocks, it is very simple and can be physically realized with a compact layout. The chip size is therefore reduced. According to a preferred embodiment of the invention, the rows in the matrix are grouped together in packets, said plurality of circuit blocks represents a first-level decoding and selection circuitry which is supplied with first-level row address signals and drives first-level selection means for the selection of a particular row inside each packet, and the double-row address decoding and selection circuitry further comprises a second-level decoding and selection circuitry supplied with second-level row address signals and generating second-level selection signals for the selection of a particular packet of rows. The features of the present invention will be made more evident by the following detailed description of its preferred embodiment, illustrated as a non-limiting example in the annexed drawings, wherein: Figure 1 is an electrical schematic diagram of a part of a matrix of memory elements of an electrically erasable and programmable semiconductor memory device; Figure 2 is a schematic block diagram of a double-row address decoding and selection circuitry according to the preferred embodiment of the invention; Figure 3 is an electrical schematic diagram of one block of the circuitry of Figure 2. As shown in Figure 1, an electrically erasable and programmable semiconductor memory device, for example of the Flash EEPROM type, comprises a plurality of memory elements TF, represented by stacked-gate MOS transistors having a control gate and a floating gate, located at the intersection of columns or bit lines BL0, BL1 etc. with rows or word lines WL0-WL15, to form a matrix of memory elements TF. Each one of the memory elements TF is connected by its drain to a respective bit line BL0, BL1 etc., and by its control gate to a respective word line WL0-WL15. The sources of all the memory elements TF are connected to a common source line 2. A per-se known row address decoding and selection architecture, shown in Figure 1, provides for the existance of groups or "packets" WLP0-WLP15 of an equal number of rows (in the following called "word lines"), in the shown example sixteen packets WLP0-WLP15 of sixteen word lines WL0-WL15 each, for a total of 256 word lines. Each word line WL0-WL15 in each packet WLP0-WLP15 is connected at one end to a driving inverter 1. Second-level selection signals L0-L15 allow the selection of one packet among all the packets WLP0-WLP15; such signals L0-L15 are generated by a per-se known second-level row address decoding and selection circuitry 8 (Fig. 2) which is supplied by a first subset of the whole set of address signals, represented in the drawing by the address bus ADD; in the shown example, four address signals are necessary to generate the sixteen signals L0-L15. To select a given packet WLP0-WLP15 of word lines, let's say WLP0, the respective second-level selection signal L0 is driven to the low logic level, while all the other signals L1-L15 are kept high. First-level selection signals P0-P15 drive respective selection transistors TS connected to the input of the driving inverters 1, and allow the selection of a given word line among all the word lines WL0-WL15 of a given packet WLP0-WLP15: if for example the word line WL0 in the packet WLP0 is to be selected, L0 is driven low and P0 is driven high, so that a logic "0" is supplied to the input of the respective driving inverter 1: the potential of the word line WL0 is thus raised to the value of the voltage supply of the inverters 1; this voltage can be switched between the normal 5 V voltage supply (in reading condition) and a programming high voltage of about 12 V (in programming condition); all the other signals P1-P15 are kept low so that the respective selection transistor TS is kept off; the input of the driving inverters 1 is therefore left floating; since however the driving inverters 1 are provided with an internal pull-up to the voltage supply of the inverters 1, the potential of the non-selected word lines WL1-WL15 is kept low. As shown in Figure 2, the first-level selection signals P0-P15 are generated by a first-level row address decoding circuitry comprising a number of identical blocks PG0-PG15, each one generating a respective signal P0-P15. Said circuitry performs a decoding of a second subset of the whole set of address signals ADD: each block PG0-PG15 is supplied with a different combination of signals, taken from the address bus ADD, wherein each signal represents one address signal A0-A3 or its logic complement A0N-A3N. Each block PG0-PG15 is also supplied by a carry-in signal CI0-CI15 connected to a carry-out signal CO0-CO15 of a preceding block or, in the case of the first block PG0, connected to a ground voltage line GND. The carry-out signal C015 of the sixteenth block PG15 is instead left floating. All the blocks PG0-PG15 are further supplied with a common signal E activated by a control circuitry 6 internal to the memory device, as will be explained in the following. As shown in Figure 3, each block PG0-PG15 comprises a four-input NOR gate 3 supplied by the respective combination of address signals A0,A0N-A3,A3N; an output of the NOR gate 3 constitutes both the carry-out signal CO0-CO15 of the block and a first input of a two-input OR gate 5 whose second input is supplied by an AND gate 4 which has a first input supplied by the signal E, and a second input supplied by a respective carry-in signal CI0-CI15; the OR gate 5 generates one of the signals P0-P15. The memory device is also provided with a redundancy circuitry 7 (Fig. 2) for the selection of redundancy word lines in substitution of defective word lines. The redundancy circuitry 7 supplies the second-level row address decoding and selection circuitry 8 with a signal DIS which is activated when the memory device is operated in normal reading or programming condition and a defective word line is addressed. The redundancy circuitry 7 is further supplied by the control circuitry 6 with the signal E. If for example during testing the word line WL0 of the packet WLP1 is found to be short-circuited with the adjacent word line WL1 of the same packet WLP1, the two word lines WL0 and WL1 of the packet WLP1 are replaced by two redundancy word lines (not shown), the address configuration of the two short-circuited word lines being programmed into two non-volatile memory registers included in the redundancy circuitry 7 and associated to said two redundancy word lines. From then on, provided that the memory device is operated either in normal reading or programming conditions, any attempt to address either one of the two short-circuited word lines WL0, WL1 of the packet WLP1 will be recognized by the redundancy circuitry 7; this will prevent the addressed defective word line from being selected, by activating the signal DIS which supplies the second-level row address decoding and selection circuitry 8, to prevent the second-level selection signals L0-L15 from being activated, and will instead enable the selection of the corresponding redundancy word line. In this way, data are neither read from or programmed into the memory elements TF of the defective word lines WL0, WL1, but are instead read from or programmed into the memory elements TF of the corresponding redundancy word lines. When, differently, the memory device must be erased, all the memory elements TF, included the memory elements TF belonging to the defective word lines WL0 and WL1 of packet WLP1, must be preprogrammed. This operation can be controlled externally by a microcontroller, or internally by the control circuitry 6 of the memory device: in the first case, the microcontroller must put the memory device in the erase mode, and then sequentially supply to the memory device all the possible address configurations; in the second case, the microcontroller must just put the memory device in the erase mode: the internal control circuitry 6 will carry out the preprogramming operation by generating internally all the possible address configurations. In both cases, as long as non-defective word lines are addressed, the internal control circuitry 6 keeps the signal E low, so that in each block PG0-PG15 the second input of the NOR gate 5 is kept low independently on the logic state of the respective carry-in signals CI0-CI15; this causes only one of the signals P0-P15 generated by each of the blocks PG0-PG15 to be activated at a time when the exact configuration of address signals A0,A0N-A3,A3N is supplied to the respective block. When however the first defective word line is addressed, in our example WL0 in WLP1, the signal E is activated by the control circuitry 6 to prevent the signal DIS generated by the redundancy circuitry 7 from being activated: in this way the second-level selection signal L1 can be driven low. Due to the activation of the signal E, in each block PG0-PG15 the logic level of the signal P0-P15 not only depends on the address configuration currently supplied to the memory device, but also on the logic state of the carry-in signal CI0-CI15 supplied to the block, i.e. on the logic state of the carry-out signal CO0-CO15 of the preceding block: in our example, when the word line packet WLP1 is addressed, and A0=A1=A2=A3="0", the output CO0 of the NOR gate 3 in the block PG0 is a logic "1", P0 is driven high and causes the logic "0" present on L1 to be transferred to the input of the driving inverter 1; this in turn puts the programming high voltage on the selected word line WL0; since the signal CO0 also represents the carry-in signal CI1 of the following block PG1, and since the signal E is activated, one input of the OR gate 5 of the block PG1 is a logic "1" even if the current configuration of the address bits A0N, A1-A3 does not activate the output of the NOR gate 3 of PG1; in this way also P1 is driven high, and the defective word line WL1 of WLP1 is also connected to the programming high voltage. As a result, addressing the defective word line WL0 in WLP1 causes the short-circuited word line WL1 to be simultaneously selected. It should be noted that the double-row address decoding and selection circuitry according to this embodiment of the invention does not allow to repair memory device chips wherein the last word line WL15 in a given packet WLP0-WLP15 is short-circuited to the first word line WL0 in the next adjacent packet. This however is not a big drawback, since the probability of having a short-circuit between such two word lines is given by the reciprocal of the total number of word lines in each packet WLP0-WLP15, and is therefore not very high.

Claims: Row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy which comprises a matrix of memory elements (TF) located at the intersection of columns (BL0,BL1) and rows (WL0-WL15) of said matrix, comprising a plurality of identical circuit blocks (PG0-PG15) supplied with address signals (A0-A3,A0N-A3N) and each one generating a respective selection signal (P0-P15) which is activated by a particular logic configuration of said address signals (A0-A3,A0N-A3N) for the selection of a particular row (WL0-WL15) of the matrix, characterized in that each one of said circuit blocks (PG0-PG15) also generates a carry-out signal (CO0-C015) which is supplied to a carry-in input (CI0-CI15) of a following circuit block (PG0-PG15) and is activated when the respective selection signal (P0-P15) is activated, a first circuit block (PG0) of said plurality of circuit blocks (PG0-PG15) having the respective carry-in input (CI0) connected to a reference voltage (GND), each of said circuit blocks (PG0-PG15) being also supplied with a control signal (E), which is activated by a control circuitry (6) of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row (WL0-WL15) is addressed, to enable the activation of the respective selection signal (P0-P15) of said following circuit block if its carry-in input (CI1-CI15) is activated, so that two adjacent rows (WL0-WL15) are simultaneously selected. Row address decoding and selection circuitry according to claim 1, the rows (WL0-WL15) in the matrix being grouped together in packets (WLP0-WLP15), characterized in that said plurality of circuit blocks (PG0-PG15) represents a first-level row address decoding circuitry which is supplied with first-level row address signals (A0-A3,A0N-A3N) and drives first-level selection means (TS) for the selection of a particular row (WL0-WL15) inside each packet (WLP0-WLP15), and in that it further comprises a second-level row address decoding and selection circuitry (8) supplied with second-level row address signals and generating second-level selection signals (L0-L15) for the selection of a particular packet (WLP0-WLP15). Row address decoding and selection circuitry according to claim 2, characterized in that each of said circuital blocks (PG0-PG15) comprises a first logic gate (3) supplied with a respective combination of signals of said first-level row address signals (A0-A3,A0N-A3N), the output of the first logic gate (3) being activated when said combination of signals is in a particular logic condition and supplying a first input of a second logic gate (5) whose second input is supplied by the output of a third logic gate (4) which is activated when both the control signal (E) and the respective carry-in signal (CI0-CI15) are activated, the output of the second logic gate (5) representing the selection signal (P0-P15) of the circuit block (PG0-PG15), the output of the first logic gate (3) also representing the carry-out signal (CO0-CO15) of said circuit block (PG0-PG15). Row address decoding and selection circuitry according to claim 2, characterized in that said second-level row address decoding and selection circuitry (8) is supplied by an inhibition signal (DIS) activated by a redundancy circuitry (7) of the memory device when a defective row is currently addressed to prevent the activation of said second-level selection signals (LO-L15), the redundancy circuitry (7) being supplied by said control signal (E) which prevent, when activated, the activation of said inhibition signal (DIS).

Inventors: GOLLA CARLA MARIA, OLIVO MARCO, GOLLA, CARLA MARIA, OLIVO, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C8
IPC codes: G11C29, G11C8, G11C16, G11C17