Vector processing device

Abstract: A vector processing device includes a vector unit (100A) having operation pipelines and a vector register connected to the operation pipelines, a memory unit (300) to be operated by the operation pipelines and results of operations obtained from the operation pipelines, and a memory control unit (200A) having a data buffer (30) provided between the vector register and the memory unit. The vector processing device also includes first means (70) for counting the number of pieces of data read from the vector register and sent to the data buffer, and second means (72) for selectively interrupting outputting an access request from the vector unit to the memory unit on the basis of the number of pieces of data counted by the first means when the operation pipelines are chained via the vector register.

Description: The present invention relates to a vector processing device that processes a large quantity of data by one instruction. A vector processing device has a plurality of pipelines, and carries out a complex process by means of the pipelines, whereby a large quantity of data can be processed at a high speed. Normally, the vector processing device includes an instruction executing unit composed of a vector unit and a scaler unit, a main memory unit, and a memory control unit. The vector unit includes a vector register, and operation pipelines of addition, multiplication and division. Data to be operated, that is, operation data is read from the main memory unit and is stored in a data buffer provided in the memory control unit. Thereafter, the operation data is read from the data buffer and is loaded to the vector register. The operation data is operated by the operation pipelines in accordance with a vector instruction. The result of the operation is transferred from the vector unit, and is stored in the data buffer in the memory control unit. Thereafter, the operation result is stored in the main memory unit. Recently, the vector processing device has employed a chaining process for vector registers in order to process data at a high speed. The chaining of vector registers is such that, when a vector register, in which the operation result of a preceding vector instruction is stored, is referred to by a subsequent vector instruction, execution of the subsequent vector instruction is started before the preceding instruction writes all data into the vector register. The chaining of vector registers involves a major problem to be solved. That is, when the preceding vector instructions is a load instruction, vector data is not supplied to the operation pipelines executing the subsequent vector instruction every cycle due to a collision that occurs when accessing the main memory unit. In this case, the process cannot be correctly performed. In order to avoid the above situation, it is necessary to perform a control such that the operation pipelines executing the subsequent vector instruction and a data transfer pipeline are temporarily stopped from operating, and hence the reading of data from the vector registers is interrupted. The present invention was made with the above background in mind. According to the present invention, there is provided a vector processing device comprising: a vector unit having operation pipelines and a vector register connected to the operation pipelines; a memory unit to be operated by the operation pipelines and results of operations obtained from the operation pipelines; a memory control unit having a data buffer provided between the vector register and the memory unit; first means comprising a counter for incrementing a count value each time when data is written into the data buffer from the vector register and decrementing the count value each time when data is read therefrom; and second means for stopping all operations of the pipelines when the value of the counter drops below a predetermined threshold. An embodiment of the present invention may provide a vector processing device in which data buffers are efficiently used and a data transfer pipeline (particularly, a store pipeline) does not have any disturbance when it is necessary to temporarily stop the operation of operation pipelines while a vector instruction is being executed in the chaining state of vector registers. Reference is made, by way of example, to the accompanying drawings in which:- Fig. 1 is a block diagram of the overall structure of a vector processing device; Fig. 2 is a block diagram of the details of the vector processing device shown in Fig. 1; Fig .3 is a diagram showing a chain of vector registers; Fig. 4 is a block diagram of essential parts of the structure shown in Fig. 2; Fig. 5 is a block diagram of the principle of the present invention; Fig. 6 is a block diagram of an embodiment of the present invention; Fig. 7 is a flowchart of the operation of a request address generator shown in Fig. 6; Fig. 8 is a flowchart of the operation of a register read controller shown in Fig. 6; Fig. 9 is a flowchart of the operation of a data buffer valid counter shown in Fig. 6; Fig. 10 is a flowchart of the operation of a pipeline stop control predictor shown in Fig. 6; Fig. 11 is a flowchart of a buffer invalidating processor shown in Fig. 6; Fig. 12 is a flowchart of the operation of a buffer write controller shown in Fig. 6; Fig. 13 is a timing chart of the operation in the prior art and the operation of the embodiment of the present invention; and Fig. 14 is a timing chart of the operation of the embodiment of the present invention. Fig. 1 is a block diagram of the structure of a vector processing device. The vector processing device shown in Fig. 1 includes an instruction executing unit 100, a memory control unit (MCU) 200, and a main memory (storage) unit (MSU) 300. The operation executing unit 100 includes a vector unit VU and a scaler unit SU. The vector unit VU performs an operation consisting of a plurality of elements by an instruction. The scaler unit SU performs an operation consisting of a single element by an instruction. The vector unit VU includes a vector instruction execution control part VI, an operation pipeline part VE, and an access pipeline part VS. Similarly, the scaler unit SU includes a scaler instruction execution control part I, a scaler operation part E, and an access part S. Address and store data (data to be stored) from the scaler unit SU are sent to the main memory unit 300 via the memory control unit 200, and instructions and load data (data to be loaded) are sent to the scaler unit SU via the memory control unit 200. Similarly, address and store data from the vector unit VU are sent to the main memory unit 300 via the memory control unit 200, and load data from the main memory unit 300 is sent to the vector unit VU via the memory control unit 200. Fig. 2 is a block diagram of the details of the vector processing device shown in Fig. 1. The access pipeline part VS of the vector unit VU includes a vector register 12, a mask register 14, a controller 16 and data transfer pipelines 18 and 20. The operation pipeline part VE includes add/logic operation pipeline ADD, a multiplication pipeline MLT, a division pipeline DIV, and a mask pipeline MSK. The vector instruction execution control part VI shown in Fig. 1 is not shown in Fig. 2 for the sake of simplicity. The scaler operation unit E of the scaler unit SU includes a scaler operation unit 22, and the access part S includes a scaler register 24 and a buffer 26. The scaler instruction execution control part I shown in Fig. 1 is omitted for the sake of simplicity. The memory control unit 200 includes a data buffer 30 and a controller 32. The vector processing device shown in Fig. 2 operates as follows. By way of example, execution of a vector addition instruction will now be described. The vector addition instruction VADD is executed as follows: VLOAD VR1 VLOAD VR2 VADD VR1, VR2, VR3 VSTORE VR3. At the commencement of execution of the vector addition instruction, the first vector load instruction VLOAD is executed, and hence data is loaded from the main memory unit 300 into a register VRl formed in the vector register 12 via the data buffer 30 of the memory control unit 200 and the load pipeline 18 of the vector unit VU. Next, the second vector load instruction VLOAD is executed, and hence data is loaded from the main memory unit 300 to a register VR2 in the vector register 12 via the same route. Then, using the addition/logic pipeline ADD, the vector addition instruction VADD is executed, and hence the data stored in the register VR1 and the data stored in the register VR2 are added. The result of the addition operation is stored in a register VR3 formed in the vector register 12. Finally, the vector store instruction VSTORE is executed, and hence the operation result stored in the register VR3 is stored in the main memory unit 300 via the store pipeline 20 and the data buffer 30. Fig. 3 illustrates execution of the above vector addition instruction. As has been described previously, the vector processing device employs the chaining of vector registers in order to improve the operation speed. In the example shown in Fig. 3, execution of the vector addition instruction VADD is started before all data is written into the vector register by execution of the vector load instruction VLOAD that precedes the vector addition instruction VADD. In this case, when the preceding vector load instruction collides with another vector load instruction during accessing of the main memory unit 300, vector data may not be supplied to the addition/logic pipeline. This prevents the normal execution of the vector operation. The above problem may be eliminated by stopping the supplying of a clock signal used to read data from the vector register 12, so that the reading of data is interrupted. The stopping of supplying the clock signal does not greatly affect the operation pipeline part VE. However, stopping the supplying of the clock signal causes the following problem with respect to the data transfer pipelines 18 and 20. Normally, a condition for the store pipelines is determined in which a data buffer 30 is provided between the main memory unit 300 and the vector register 12, and vector data can be definitely read and sent to the data buffer 30 during a predetermined number of machine cycles. The predetermined number of machine cycles corresponds to the time necessary to send data to the main memory unit 300 after the priority order of execution in the controller 32 of the memory control unit 200 is determined. Under the above condition, data cannot be written into the data buffer 30 if the clock signal used to read data from the vector buffer 12 is stopped in a case where data to be stored is read from the vector register 12 and sent to the data buffer 30 at the same time as the controller 16 of the vector unit VU sends an access request to the main memory unit 300 and where the data stored in the data buffer 30 is read in response to receipt of a write enable signal. Hence, it is not possible to ensure such an operation in which data regarding an access request that has been sent or an access request that has been assigned the priority order can be stored in the data buffer 30 within the predetermined number of machine cycles. In this case, the stored data will become different from the original data. Alternatively, it may be possible to stop accessing from the vector unit VU to the memory control unit 200 in order to interrupt the reading of data from the store pipeline. Fig. 4 is a diagram of the structure of the controller 16 of the vector unit VU shown in Fig. 2 relating to an access request (address generation of the main memory unit 300). A register read control part 34 controls the read operations of the vector register 12 and the mask register 14. The register read control part 34 includes a pipeline stop predictor 36 provided therein. When the pipeline stop predictor 36 receives an operation pipeline stop alarm warning signal VE-STOP-WARNING from the vector instruction execution control part VI, the predictor 36 makes a decision that it is necessary to interrupt the reading of data from the vector register 12, and immediately generates an access request stop signal VE-STOP. The operation pipeline stop warning signal VE-STOP-WARNING indicates that a situation necessary to stop the operation of the operation pipelines due to a drain on data in the chaining state of vector registers and that it is necessary to stop storing data. The address generation is carried out by means of a distance value register 38, a beginning address 40, a full adder 42, a logical address register 44, an address translator 46, and a real address register 48. The beginning address of the main memory unit 300 and the distance value (information indicating the position of data which is placed every bytes corresponding to the distance value) are written, as start signals, into the registers 40 and 38, respectively. The full adder 42 derives a logical address from the addresses written into the registers 38 and 40, and writes the logical address into a register 44. The logical address is translated into a real address of the main memory unit 300 by means of the address translator 46, and is then written into a register 48. The real address written into the register 48 is queued in an address queue buffer 50 in the controller 32 of the main memory unit 200. The controller 32 performs a request priority order determining process with respect to the queued real address, and selects one real address via a read unit 52. The aforementioned address request stop signal VE-STOP is applied to the logical address register 44, and stops the operation of the register 44. Thus, the logical address cannot be applied to the address translator 46, and hence the real address cannot be supplied to the address queue register 50. The pipeline stop predictor 36 stops outputting the access request stop signal VE-STOP, for example, when a predetermined time elapses after receiving the operation pipeline stop warning signal VE-STOP-WARNING. However, the structure shown in Fig. 4 interrupts a data transfer by an access request which is generated after the access request stop signal VE-STOP and is not necessary to stop execution of the data transfer. As a result, a wasteful empty area is formed in the data buffer 30, and the operation of the store pipeline is disturbed. The present invention is intended to eliminate the above disadvantages. Fig. 5 is a block diagram of the principle of the present invention, and shows an essential part of the vector processing device shown in Fig. 6, which will be described in detail later. In order to eliminate the above disadvantages, the vector processing device of the present invention includes a vector unit 100A (Fig. 6) having a plurality of pipelines and a vector register 12 (Fig. 6) connected to the pipelines, a memory unit 300 (Fig. 6) storing data to be operated by the pipelines and the results of operations, a memory control unit 200A (Fig. 6) having a data buffer 30 (Fig. 6) provided in the vector register and the memory unit, first means (data buffer valid counter) 70 for counting the number of items of data read from the vector register and sent to the data buffer, and second means (pipeline stop predictor) 72 for selectively interrupting, in a state in which the operation pipelines are chained via the vector register, an access request from the vector unit to the memory unit on the basis of the number of items of data counted by the first means. In the configuration which has been described with reference to Fig. 4, the sending of all access requests is stopped when a drain of data in the operation pipelines in the chaining state. On the other hand, according to the present invention, it becomes possible to interrupt only a minimum number of necessary access requests by selectively interrupting, by means of the second means, the sending of access requests from the vector unit to the memory unit on the basis of the number of pieces of data counted by the first means in the state in which the operation pipelines are chained via the vector register. Fig. 6 is a block diagram of a vector processing device according to an embodiment of the present invention. In Fig. 6, parts that are the same as parts shown in Fig. 2 are given the same reference numbers. The vector processing device shown in Fig. 6 includes the vector unit 100A, the memory control unit 200A, the main memory unit 300 and a scaler unit. For the sake of simplicity, the scaler unit is omitted from Fig. 6. The vector unit 100A includes a vector instruction execution control part 110, a controller 16A, the vector register 12, the mask register 14 and operation pipelines. For the sake of simplicity, the operation pipelines are not shown in Fig. 6, but are connected to the vector register 12 and the mask register 14, as shown in Fig. 2. The vector instruction execution control part 110 is connected to the unshown scaler unit, and sends a start signal START and the operation pipeline stop warning signal VE-STOP-WARNING to the controller 16A. Further, the vector instruction execution control part 110 receives a write valid signal WV from the controller 16A. The controller 16A includes a request address generator 54, a register write controller 56, a register read controller 58, a buffer write controller 60, and a buffer read controller 62. These controllers are formed by, for example, respective microcomputers or a single microcomputer, and execute programs which will be described later. Fig. 5, which has been previously described, indicates the respective essential parts of the request address generator 54, the register read controller 58, and a request priority order determining unit 64 which will be described later. The request address generator 54 includes the aforementioned distance value register 38, the beginning address register 40, the full adder 42, the logical address register 44, the address translator 46 and the real address register 48. The logical address in the logical address register 44 is assigned identification information ID identifying the logical address. The identification information ID is assigned to the address by the vector operation execution control part 110, and is also assigned to the real address translated from the logical address. The real address with the identification information ID added thereto is transferred to the address queue register 50. As shown in Fig. 5, the register read controller 58 includes a data buffer valid counter 70, and a pipeline stop predictor 72. The counter 70 and the predictor 72 are formed by, for example, software carried out by the register read controller 58. As will be described later, the data buffer valid counter 70 counts the number of pieces of data read from the vector register 12 and sent to the data buffer 30 in order to interrupt the operation of the transfer pipeline used to store data with respect to only a minimum number of necessary access requests. The pipeline stop predictor 72 receives the operation pipeline stop warning signal VE-STOP-WARNING from the vector instruction execution control part 110, and sends the access request stop signal VE-STOP to the request priority order determining unit 64 of the memory control unit 200A together with the identification information ID assigned to the vector instruction to be stopped. The register write controller 56 controls the write operations of the vector register 12 and the mask register 14. The register read controller 58 controls the read operation of the vector register 12 and the mask register 14. The buffer write controller 60 controls the write operation of the data buffer 30 in the memory control unit 200A. The buffer read controller 62 controls the read control of the data buffer 30. The controller 32A of the memory control unit 200A includes the request priority order determining unit 64, a buffer invalidating processor 66, and a main memory unit controller 68. As shown in Fig. 5, the request priority order determining unit 64 includes the address queue register 50 and the read unit 52 in addition to a part which executes a control which will be described later. The real address (access request) stored in the address queue register 50 is temporarily stored in the address queue register 50 until the request priority order is assigned thereto. When the read unit 52 receives the access request stop signal VE-STOP and the identification information ID, the read unit 52 reads, from among real addresses stored in the address queue register 50, only the real address to which different identification information ID has been assigned, and sends the read real address to the main memory controller 68. Hence, only a minimum number of necessary access requests can be interrupted without interrupting access requests unnecessary to be interrupted. The main memory controller 68 receives the access request (real address) from the request priority order determining unit 64, and outputs necessary signals including the real address to the main memory unit 300. The buffer invalidating processor 66 performs an invalidating process for the buffer 26 of the scaler unit shown in Fig. 2. The data buffer 30 is segmented into an area for the store operation and an area for the load operation. The operation of the embodiment of the present invention shown in Figs. 5 and 6 will now be described. First, a description will be given of an outline of the operation carried out when a load instruction or a store instruction is executed. The scaler unit SU receives a vector instruction read from the main memory unit 300 via the data buffer 30, and sends the received vector instruction to the vector instruction execution controlling part 110. When the received vector instruction is a load instruction, the request address generator 54 generates an access request (the generation of the real address) in response to the start signal START of the vector instruction. On the basis of the access request to which the priority order is assigned by the request priority order determining unit 64, the main memory controller 68 sends the address signal and a start signal (GO) to the main memory unit 300. At the same time, the main memory controller 68 sends a data output signal to the buffer write controller 60 in synchronism with a timing with which data fetched from the main memory unit 300. The buffer write controller 60 receives the above data output signal, and writes the fetched data from the main memory unit 300 into the data buffer 30. Then, the register write controller 56 writes the data written into the data buffer 30 into the vector register 12. When the vector instruction received from the scaler unit SU is a store instruction, the register read controller 58 reads data from the vector register 12 at the same time as outputting the start signal START of the vector instruction, and writes the received data into the data buffer 30. The request priority order determining unit 64 assigns the priority order to the access request, and sends the data transfer signal to the buffer read controller 62 and the buffer invalidating processor 66. When the access request is a fetch operation from the scaler unit SU, the buffer invalidating processor 66 registers the relevant address in a tag register (TAG) provided therein. When the access request is a vector store operation, the buffer invalidating processor 66 refers to the tag register, and performs the invalidating process for the buffer 26 (Fig. 2) of the scaler unit SU when the address has been registered in the tag register. In response to the data transfer signal, the buffer read controller 62 reads the stored data from the data buffer 30, and sends the read data to the main memory unit 300. At the same time as the above, the main memory controller 68 of the memory control unit 200A sends the address and the start signal (GO) to the main memory unit 300. A detailed description will now be given of the operation of the embodiment of the present invention. Fig. 7 is a flowchart of the operations of the request address generator 54 and the request priority order determining unit 64. The process is started in response to the start signal START from the scaler unit SU (step S11). Information indicating the beginning address of and distance value of the access request is received from the vector instruction execution control unit 110, and the logical address is calculated therefrom (step S12). When it is confirmed that the logical address corresponding to a vector length (step S13), the request address generator 54 determines whether or not a virtual address mode has been set (step S14). When it is determined that the virtual address mode has been set, the logical address is translated into the real address (step S15). Then, the request address generator 54 determines whether or not any read address is held in the address queue buffer 50 (step S16). When the virtual address mode has not been specified, step S16 is performed without step S15. When it is determined, in step S16, that a real address (access request) has been registered in the address queue register 50, step S20 is performed. When not, the request address generator 54 determines whether or not the request priority order determining unit 64 is busy (step S17). This determination can be carried out by, for example, referring to the state of a busy signal line extending from the request priority order determining unit 64. When it is determined that the unit 64 is busy, step S20 is carried out. When it is determined, in step S17, that the unit 64 is not busy, the read unit 52 of the request priority order determining unit 64 determines whether or not the access request stop signal VE-STOP has been supplied (step S18). When the determination result of step S18 is NO, the access request (real address) is immediately sent to the main memory unit 300 via the request priority order determining unit 64 without writing the real address into the address queue register 50 (step S22). When it is determined, in step S18, that the access request stop signal VE-STOP has been supplied, it is determined whether or not the identification information ID assigned to t he real address from the request address generator 54 coincides with the identification information ID from the register read controller 58 (step 19). When the identification information ID from the request address generator 54 does not coincide with the identification information ID from the register read controller 58, the address and the start signal are immediately sent to the main memory unit 300 (step S22). When it is determined, in step S19, that the identification information ID from the request address generator 54 coincides with the identification information ID from the register read controller 58, the read address is written into the address queue buffer 50, and is held until the supplying of the access request stop signal VE-STOP is stopped. That is, step S22 is performed when the address queue register 50 is accessed in step S21, and the determination results of the steps S16 and S17 are NO, and when the determination result of step S18 is YES. Fig. 8 is a flowchart of the operation of the register read controller 58. First, the register read controller 58 determines whether or not the data buffer 30 is full (step S31). When it is determined that the data buffer 30 is full, the register read controller 58 repeatedly performs step S31 until the determination result of step S32 becomes NO. When the determination result of step S32 becomes NO, the register read controller 58 determines whether or not the access request stop signal VE-STOP has been generated (step S32). When the result of this determination is YES, the process returns to step S31. When the result of step S32 is NO, the register read controller 58 determines whether or not data equal to the vector length has been read from the vector register 12 (step S33). When the result of this determination is NO, the process returns to step S31. When the determination result of step S33 is YES, the register read controller 58 reads the data from the vector register 12 (step S34), and writes the read data into the data buffer 30 (step S35). Fig. 9 is a flowchart of the operation of the data buffer valid counter 70 provided in the register read controller 58 shown in Fig. 5. The register read controller 58 determines, on the basis of the write valid signal WV generated when the write controller 56 writes data into the vector register 12, whether or not the writing of data into the vector register 12 has been carried out (step S41). When the result of this determination is YES, the register read controller 58 increments the count value of the data buffer valid counter 70 by 1 (step S42). The register read controller 58 determines, on the basis of a read valid signal RV generated when data is read from the vector register 12, whether or not the reading of data from the vector register 12 has been carried out (step S43). When the result of this determination is YES, the register read controller 58 decrements the count value of the data buffer valid counter 70 by 1 (step S44). Then, the process returns to step 41. Fig. 10 is a flowchart of the operation of the pipeline stop predictor 72 provided in the register read controller 58 shown in Fig. 5. First, the operation pipeline stop warning signal VE-STOP-WARNING is received from the vector instruction execution control part 110 (Fig. 6) (step S51). In response to the signal VE-STOP-WARNING, the predictor 72 determines whether or not the counter value of the data buffer valid counter 70 (the number of pieces of data read from the vector register 70) is smaller than a predetermined value X (step S52). The predetermined value X corresponds to a predicted value of an allowable number of accesses (allowable quantity of data) even when the operation pipeline stop warning signal VE-STOP-WARNING indicating a drain of data in the operation pipeline VE is generated. If the counter value of the data buffer valid counter 70 becomes equal to or smaller than the predetermined value X, there is a possibility, due to acceptance of the access request, that a failure (a drain of data) may occur in execution of vector instructions in the chaining state of vector registers. When it is determined, in step S52, that the counter value of the data buffer valid counter 70 is smaller that the predetermined value, it is concluded that the operation of the pipelines should be stopped (step S53), and the predictor 72 outputs the access request stop signal VE-STOP to the read unit 52 together with the identification information ID. Fig. 11 is a flowchart of the operation of the buffer invalidating processor 66. The buffer invalidating processor 66 receives the data transfer signal from the request priority order determining unit 64 (step S61), and determines whether or not the received data transfer signal is a store instruction (step S62). When the received signal is not a store instruction, the processor 66 determines whether or not the access request is a fetch from the scaler unit SU (step S63). When the access request is a fetch from the scaler unit SU, the buffer invalidating processor 66 registers the address of the access request in the tag register (TAG) provided therein (step S64). Further, the buffer invalidating processor 66 determines whether or not the access request is a store instruction from the vector unit 100A (step S65). When the determination result of step S65 is YES, the processor 66 refers to the tag register (step S66). When the access request has been registered in the tag register (step S67), the processor 66 stores the access request in the queue register provided therein (step S68), and then carries out the invalidating process for the buffer 26 (shown in Fig. 2) (step S69). Fig. 12 is a flowchart of the operation of the buffer write controller 58. The buffer write controller 58 receives a warning signal DTW (Data Transfer Warning) indicating a drain of data from the request priority order determining unit 64 (step71). Then, the buffer write controller 58 reads data from the data buffer 30 (step S72), and reports the reading of data to the register read controller 58 (step S73). Fig. 13 is a timing chart of the operation of the embodiment of the present invention. A part I of Fig. 13 shows the conventional access control operation, and a part II thereof shows the access control operation according to the embodiment of the present invention. Parts (A) in I of Fig. 13 and (C) in II thereof show the operation timings of the load instruction, and parts (B) in I of Fig. 13 and (D) in II thereof show the operation timing of the store instruction. The operation timing of the load instruction in the prior art is the same as that of the load instruction according to the embodiment of the present invention. In the conventional execution of the store instruction, as shown in (B) in I of Fig. 13, the address translation is not performed while the access request stop signal VE-STOP is active. As has been described previously with reference to Fig. 4, the access request stop signal VE-STOP is output to the logical address register 44, and the outputting of the logic address to the address translator 46 is inhibited. When the access request stop signal VE-STOP is turned OFF, the address translating operation is started. According to the embodiment of the present invention, as shown in (D) in II of Fig. 13, the access translating operation is being carried out while the access request stop signal VE-STOP is ON. As has been described previously, only a minimum number of necessary access requests are interrupted, and hence the address translating operation continues to be carried out. When the access request signal VE-STOP is turned OFF, the priority order is given to the access requests. Fig. 14 is a diagram showing another executing timing of the store instruction, A part (A) of Fig. 14 shows the conventional operation timing of the store instruction, and a part (B) thereof shows the operation timing of the store instruction according to the embodiment of the present invention. In the conventional control, when the access request stop signal VE-STOP is turned ON during the address translating operation, the address translating operation is immediately stopped. The preceding instruction which has been assigned the priority order continues to be executed, and data is read from the data buffer 30 and stored in the main memory unit 300. When the access request stop signal VE-STOP is turned OFF, the address translating operation is started again. According to the embodiment of the present invention, the address translating operation is not interrupted even when the access request signal VE-STOP is turned ON. When the operation must be selectively carried out, the mask register 14 is used to extend the application of the pipeline process by providing the result of a decision on the selection as a mask pattern of a bit sequence. However, the mask register 14 is not directly used in the control by the embodiment of the present invention, and hence the details of the operation of the mask register 14 will be omitted. According to the present invention, the following advantages are obtained. First, with the data buffer valid counter, it becomes possible to interrupt only a minimum number of necessary access requests by referring to the state of the data buffer when the pipelines become the state in which the operation thereof should be stopped. Hence, it becomes possible to efficiently use the pipelines having the data buffer. Second, it becomes possible to certainly identify the vector instruction whose address request should be stopped by assigning the identification information ID to each vector instruction and comparing it with identification information of a vector instruction requested to be stopped. Third, it becomes possible to apply the above-mentioned control to a vector processing device operating under a condition in which the throughput of address generation does not correspond to the throughput of reading of data from the vector register. Conventionally, in such a condition, the operation of the pipelines is stopped. The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention as defined by the appended claims.

Claims: A vector processing device comprising: a vector unit (100A) having operation pipelines and a vector register connected to the operation pipelines; a memory unit (300) to be operated by the operation pipelines and results of operations obtained from the operation pipelines; a memory control unit (200A) having a data buffer (3) provided between the vector register and the memory unit; characterized in that it further comprises : first means (70) comprising a counter for incrementing a count value each time when data is written into the data buffer from the vector register and decrementing the count value each time when data is read therefrom; and second means (72) for stopping all operations of the pipelines when the value of the counter drops below a predetermined threshold. The vector processing device as claimed in claim 1, wherein the counter (70) counts the number of pieces of data on the basis of a first number of times that data in the data buffer is written into the vector register and a second number of times that data is read from the vector register and sent to the data buffer. The vector processing device as claimed in claim 1, further comprising: third means (54) for receiving a logical address associated with an access request from the vector unit to the memory unit, and for outputting address information including a real address corresponding to said logical address and identification information identifying said logical address; fourth means (50), provided in the memory control unit, for temporarily storing said address information; and fifth means (52, 72) for selectively interrupting the access request by referring to said identification information stored in the fourth means and selecting said access request from among the access requests from the vector unit to the memory unit. The vector processing device as claimed in claim 1, 2, or 3, wherein said second means (72) is responsive to a signal (VE_STOP_WARNING) which warns of a drain of data supplied to one of the operation pipelines chained via the vector register. The vector processing device as claimed in claim 2, wherein said second means (72) stops all operations of the pipelines on the basis of a difference between the first number of times and the second number of times.

Inventors: SHINJO NAOKI, YOSHINAGA TORU, SHINJO, NAOKI, YOSHINAGA, TORU, SHINJO, NAOKI, C/O FUJITSU LIMITED, YOSHINAGA, TORU, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1993
Main classification: G06F15
IPC codes: G06F15, G06F17, G06F9