SEMICONDUCTOR DEVICES WITH A DOUBLE GATE

Abstract: An integrated circuit arrangement comprising a pair of insulated-gate transistor devices connectible in series, the first transistor of said pair being operable as a depletion-mode device whilst the second transistor of said pair serves as an enhancement-mode device. A separately-biasable gate electrode permits the threshold voltage of the depletion-mode transistor to be adjusted independently.

Description: Semiconductor devices with a double gate This invention relates to semiconductor devices and, in particular, to the fabrication of thin film transistors and integrated circuits incorporating such transistors. In designing circuits for integrated electronics it is an advantage to have more than one type of active device available - for example CMOS has n and p channel and most n-MOS integrated circuit fabrication processes allow selective variation of threshold voltage and in particular fabrication of enhancement and depletion mode devices simultaneously. For an n-channel enhancement mode device the minimum current (off state) flows with zero applied gate voltage and is increased by applying a positive gate voltage (on state). Conversely for a depletion mode device a negative gate voltage is applied to turn the device off whilst at zero gate voltage the device is in the on state. In n-MOS circuits use of enhancement-depletion circuitry gives improved performance when compared with enhancement-only circuits, in terms of switching speed, output voltage levels, and power consumption. As indicated above, improved circuit performance is possible if depletion mode devices are also available. Possible .ways to produce depletion type thin film active devices are to increase the semiconductor film thickness for the depletion devices as compared to the enhancement, or to selectively add n-type dopant material into the channel region of the depletion devices. In either case additional process steps would be needed, involving the use of extra mask layers, and hence increased cost and reduced yield. Depletion and enhancement devices may also be produced by using different geometries for the CdSe layers without an additional mask step. We have devised a process using cadmium selenide which produces a double gated n-channel enhancement mode device, combining the desirable characteristics of high speed operation due to the high carrier mobility, high on current and low off current. It has been found possible to produce depletion-mode TFTs without any additional processing steps by biasing one of the gates of the device to control the threshold voltage of the device so that it has a suitable (negative) value. Thus the TFTs can be made to be enhancement or depletion types as required, with both types co-existing in the same circuit. No alterations to the fabrication process are needed, and no additional mask layers, merely a small variation in mask design to allow separate control of the potential of both gates of the TFTs. An externally applied voltage is applied to one gate of the depletion mode devices in the circuit to set the required threshold voltage. According to the present invention there is provided an integrated circuit arrangement comprising a pair of insulated-gate transistor devices connectible in series wherein the first transistor of said pair is operable as a depletion-mode device whilst the second transistor of said pair serves as an enhancement-mode device. The invention will now be particularly described with reference to the accompanying drawings, in which: Figure 1 is a cross-section through a thin film transistor in accordance with a specific embodiment of the invention; Figure 2 shows electrical characteristics of the transistor of Figure 1; and Figure 3 is the circuit diagram of an inverter; and Figure 4 shows electrical characteristics of this inverter. Referring now to the drawings, Figure 1 shows a cross-section through a thin film transistor in accordance with a specific embodiment of the present invention. A diffusion barrier 1 is formed on a substrate 3. The device has a bottom gate 5 separated by an insulator layer 7 from a layer of cadmium selenide 9. An n-channel region 11 is formed in this semiconductor layer. A pad contact 13 and column conductor 15 are provide for the source and drain electrodes. An upper gate 17 is separated from the semiconductor by an insulator layer 19. Figure 2 shows the current through the transistors as a function of the top gate voltage for two values of the bottom of the top gate voltage. It is seen there is a marked difference in the position of the curves particularly in the theshold region (i.e. the steeply rising part). Figure 3. shows the circuit diagram of an inverter for use with the transistor of Figure 1. Its transfer characteristics are shown in Fig. 4. where the advantage of using the depletion TFT as the pull-up transistor is seen in the larger voltage swings. In the example chosen an enhancement pull-up device would not operate a shift register. Fabrication of enhancement and depletion type CdSe thin film transistors is simultaneously possible, with no additional masking or processing steps to those required for a purely enhancement type process. The same technique may be applied to the production of TFTs using other semiconductor materials. In the case of polysilicon this process would compensate for the low mobility of holes in p-type material and produce enhanced circuits.

Claims: Claims 1. An integrated circuit arrangement comprising a pair of insul ted-gate transistor devices connectible in series characterised in that the first transistor of said pair is 5 operable as a depletion-mode device whilst the second transistor of said pair serves as an enhancement-mode device. 2. An integrated circuit arrangement according to claim 1 characterised in that said first transistor of a separately-biasable gate electrode adapted to permit the 10 threshold voltage of said transistor to be adjusted independently. 3. An integrated circuit arrangement according to claim 1 characterised in that the channel region of said transistors is formed of cadmium selenide. 154. An integrated circuit arrangement according to claim 1 character ed in that the channel region of said transistors is formed of silicon. 5. A switching circuit characterised in that it incorporates a pair of transistors in an integrated circuit arrangement in 20 accordance with any one of the preceding claims.

Inventors: LEE MICHAEL JOHN, LEE, MICHAEL, JOHN
Applicants: BRITISH TECH GROUP, LEE MICHAEL JOHN, BRITISH TECHNOLOGY GROUP LTD.
Application year: 1993
Main classification: H01L29
IPC codes: H01L27, H01L29