Method and device for detection and correction of errors in ATM cell headers

Abstract: Of the type wherein it is made a series to parallel conversion (2) of the serial data stream (1), obtaining a parallel data format of n bits, the clock rate of which is n times lower than the original. From the parallel input data of the ATM header, a syndrome word (3) is generated according to a determined function that indicates that no error has been detected, that more than one error has been detected, or which bit has to be corrected when only one error has been detected. The ATM cell headers are delayed (4) until the syndrome word has been completed, the error correction process (5) then being carried out, when required, in accordance with the syndrome word generated. In addition, an individual indication (7) for external use is generated of the result of the detection and possible correction process made. The device implements the method described.

Description: OBJECT OF THE INVENTION This invention refers to a method and a device for detection and correction of errors in ATM (Asynchronous Transfer Mode) cell headers, in which a conversion is made from series to parallel of the n bits in the serial data stream, a n-bit parallel data format being obtained which has a clock rate n times lower than that of the original. The invention is for application in digital communications systems. BACKGROUND TO THE INVENTION In this type of systems it is common to add a few extra bits in the so-called cell header in order to protect the information it contains. In the case of CCITT Recommendations G.707, G.708 and G.709, a fifth byte of redundant information is added to the four initial bytes in the ATM cell header. This fifth byte is termed the protection byte and is produced by means of a cyclic coding with a cyclic code (40, 32) generated by the polynomial g(X) = X 8 + X 2 + X + 1. To extract the error-free initial information, these cyclic codes have to be decoded. One of the decoding methods for cyclic codes is that described in the book "Error Correcting Codes" by W.W. Peterson, published by the Massachusetts Institute of Technology and John Wiley & Sons, Inc., New York and London, 1961, pages 201-204. The method consists in applying the coded data vector to a divider circuit based on a Meggit Decoder with serial data input and, simultaneously, to a storage register. The divider circuit, which includes a shift register, calculates the so-called "syndrome", such that there is a one-on-one correspondence between this syndrome and the error pattern that is assumed to have occurred. The combinational logic circuit, that is connected to the outputs of the shift register, is designed to have a "1" at its output if, and only if, the syndrome obtained from the divider circuit corresponds to an error pattern with an error in the next bit to leave the storage register. The storage register must first contain an initial value for a correct decoding, which for this particular case, is all registers set to "0", corresponding also to the initial value of the shift register in the polynomial generator used by the CCITT Recommendations mentioned earlier. The output of the divider circuit can be expressed in matrixial form as: S ts+1 = T•S ts + U ts , where S ts is the output of the codes vector from the shift register in the livider circuit, at the time ts, S ts+1 is the output of the codes vector at the time ts+1, T is a square matrix that represents the codes transformation of the serial divider circuit (transformation matrix), and U ts is the input vector to the shift register at the time ts. This systematic method works at the same rate as the binary data rate and produces, at its output, the syndrome corresponding to the current input. The main drawback of this type of method that works in series, in addition to the limitation in the type of integration technology to be used with present-day communications systems which work at increasingly faster speeds, is that the power consumption of devices working in series, whether at current speeds or at speeds foreseen for the near future, can reach levels that are unacceptable in practice. TECHNICAL PROBLEM TO BE OVERCOME Consequently the technical problem to be overcome consists in reducing the total power consumption or, what is the same thing, lowering the working frequency of the digital circuits that perform the error detection and correction function in ATM cell headers. CHARACTERISATION OF THE INVENTION To overcome the aforementioned drawbacks, this invention is characterised in that it performs the generation of a syndrome word from the parallel input data in the ATM cell header in accordance with the functional relation: n S tp+1 = T n • S tp + U tp , where T n is the n-th power of the serial transformation matrix; U tp is the n-bit input data vector at time tp; S tp is the syndrome word at time tp; and S tp+1 is the syndrome word at time tp+1; and in that the syndrome word generated indicates, for the header of each ATM cell with n-bit parallel format: that no error has been detected; or that more than one error has been detected; or the erroneous bit to be corrected when only one error has been detected. The methcd described here is also characterised in that the ATM cell headers with a n-bit parallel format are delayed until the syndrome word is completed, the error correction process then being carried out in accordance with the syndrome word generated. Optionally, an individual indication for external use can be produced showing that no error has been detected, that more than one error has been detected, or that an error has been corrected. In claim 4, and in those claims that depend on it, a device is characterised which implements the method of this invention. With the aforementioned method and device, significant advantages are obtained such as the possibility of using cheaper technologies when the serial data rate is very high (e.g. CMOS instead of ECL), or simply a reduction in power consumption because of the lower working frequency. BRIEF FOOTNOTES TO THE FIGURES A more detailed explanation of the invention is given in the following description based on the attached figures, in which: figure 1 shows a flowchart of the method used in the invention, figure 2 shows the block diagram of a device that implements the invention, and figure 3 shows a preferred implementation of the means to generate the syndrome word, in accordance with the invention. DESCRIPTION OF THE INVENTION The flowchart in figure 1 illustrates the steps in the method used in the invention. The information is received as a serial data stream that forms the ATM cells. The ATM cell, consisting of a serial data stream 1, is changed to a n-bit parallel data format by means of a series to parallel conversion 2. After this, a syndrome word 3 is generated from the n-bit parallel data format of the ATM cell header. The relation between the syndrome word generated and the parallel input data is described later for the case of using eight bits but can be generalised for any value of n. When the entire ATM cell header has passed through the syndrome generator, the word obtained indicates that no error has occurred, that more than one error has occurred, or the position of the erroneous bit to be corrected when only one error has occurred. In addition, the ATM cell with a n-bit parallel data format is delayed 4 until the syndrome word is available and an error correction 5 can be performed, when required, taking into account the above syndrome word. As a result, the corrected ATM cell header is obtained 6, when required, in accordance with the syndrome word. Also, an individual indication 7 to the exterior can be generated from the result of the detection and correction process carried out. The block diagram of figure 2 shows the device that implements this invention, in which a n-bit parallel data bus 16 is obtained from the ATM cell header with a serial data format 14 by means of a series to parallel converter 9, the parallel data signalling rate being n times lower than the serial data stream 14. The serial data clock 13 is also divided by n in a frequency divider 8, a parallel data clock 15 being obtained that will be the working frequency for all subsequent digital circuits in the device. The device has means 10 to generate a syndrome word 20. They also receive the parallel data clock 15, the n-bit parallel data bus 16, an initialisation signal 17 to set the initial values of the means 10, an ATM cell header indication signal 18 to indicate the ATM cell bits from which the syndrome word 20 has to be calculated, and an indication signal of the last eight bits in the ATM cell header 19, to indicate the inversion 27 of those bits that were previously inverted in the transmission part, shown in the figure 3. Turning now to the figure 2, these means 10 to generate a syndrome word 20 in the specific case where n = 8, are based on applying the serial data stream 14 mathematically, eight times consecutively, to a divider circuit defined by the polynomial g(X) = X 8 + X 2 + X + 1, the transformation matrix of which is: Mathematically it can be probed that the above operation is equivalent to a divider circuit for eight input bits, where the transformation matrix is given by the following expression: and the output of this divider circuit can be expressed in matrixial form as: S tp+1 . =T 8 .S tp + U tp , where S tp is the eight-bit intermediate syndrome word at the time tp of the parallel data clock 15, S tp+1 is the eight-bit intermediate syndrome word in the next time period of the parallel data clock 15, U tp is the eight-bit input vector to the means 10 for generating the syndrome word 20, and T 8 has been presented previously and corresponds with the transformation matrix of the parallel divider circuit that relates the intermediate syndrome words between two consecutives cycles of the parallel data clock, and which can be expressed in logic functions as follows: (S 8 ) t+1 = (S 8 ) t + (S 7 ) t + (S 6 ) t + U 8 (S 7 ) t+1 = (S 7 ) t + (S 6 ) t + (S 5 ) t + U 7 (S 6 ) t+1 = (S 6 ) t + (S 5 ) t + (S 4 ) t + U 6 (S 5 ) t+1 = (S 5 ) t + (S 4 ) t + (S 3 ) t + U 5 (S 4 ) t+1 = (S 8 ) t + (S 4 ) t + (S 3 ) t + (S 2 ) t + U 4 (S 3 ) t+1 = (S 7 ) t + (S 3 ) t + (S 2 ) t + (S 1 ) t + U 3 (S 2 ) t+1 = (S 7 ) t + (S 2 ) t + (S 1 ) t + U 2 (S 1 ) t+1 = (S 8 ) t + (S 7 ) t + (S 1 ) t + U 1 where the + symbol indicates a modulo-2 sum. A preferred physical implementation is shown in figure 3, under the reference 26. After the input of the five bytes in an ATM cell header to these means 26, the syndrome word 20 indicates: syndrome erroneous bit S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 0 0 0 0 0 error free header 1 0 0 0 0 0 0 0 bit 1 0 1 0 0 0 0 0 0 bit 2 0 0 1 0 0 0 0 0 bit 3 0 0 0 1 0 0 0 0 bit 4 0 0 0 0 1 0 0 0 bit 5 0 0 0 0 0 1 0 0 bit 6 0 0 0 0 0 0 1 0 bit 7 0 0 0 0 0 0 0 1 bit 8 1 1 1 0 0 0 0 0 bit 9 0 0 1 1 0 0 0 0 bit 10 0 0 1 1 1 0 0 0 bit 11 0 0 0 1 1 1 0 0 bit 12 0 0 0 0 1 1 1 0 bit 13 0 0 0 0 0 1 1 1 bit 14 1 1 1 0 0 0 1 1 bit 15 1 0 0 1 0 0 0 1 bit 16 1 0 1 0 1 0 0 0 bit 17 0 1 0 1 0 1 0 0 bit 18 0 0 1 0 1 0 1 0 bit 19 0 0 0 1 0 1 0 1 bit 20 1 1 1 0 1 0 1 0 bit 21 0 1 1 1 0 1 0 1 bit 22 1 1 0 1 1 0 1 0 bit 23 0 1 1 0 1 1 0 1 bit 24 1 1 0 1 0 1 1 0 bit 25 0 1 1 0 1 0 1 1 bit 26 1 1 0 1 0 1 0 1 bit 27 1 0 0 0 1 0 1 0 bit 28 0 1 0 0 0 1 0 1 bit 29 1 1 0 0 0 0 1 0 bit 30 0 1 1 0 0 0 0 1 bit 31 1 1 0 1 0 0 0 0 bit 32 0 1 1 0 1 0 0 0 bit 33 0 0 1 1 0 1 0 0 bit 34 0 0 0 1 1 0 1 0 bit 35 0 0 0 0 1 1 0 1 bit 36 1 1 1 0 0 1 1 0 bit 37 0 1 1 1 0 0 1 1 bit 38 1 1 0 1 1 0 0 1 bit 39 1 0 0 0 1 1 0 0 bit 40 any other code more than one erroneous bit In addition, in figure 2, a delay circuit 11 is shown, the purpose of which is to delay the ATM cell until the syndrome word 20 is available, in this case five cycles of the parallel data clock, and which receives the eight-bit parallel data bus 16 and the parallel data clock 15 to obtain a delayed eight-bit parallel data bus 21. Finally the device shown in figure 2 includes error correcting means 12 to correct the ATM cell header according to the previously mentioned table, which receive the delayed eight-bit parallel data bus 21 and the syndrome word 20, and that obtain the corrected ATM cell header 25 when required, and, optionally, the following three control signals: no error indication signal 22, corrected error indication signal 23, and more than one error indication signal 24.

Claims: Method for detection and correction of errors in ATM cell header signals in which a serial to parallel conversion (2) takes place for n bits in a serial data signal (1), obtaining an n-bit parallel data signal with a clock rate that is n times lower than an input clock rate of the serial data signal (1); characterised in that the method further comprises the steps of: a) generating a syndrome word signal (3) from the n-bit parallel data signal in an ATM cell header signal in accordance with a functional relation: S tp+1 . = T n * S tp + U tp ; where T n is an n-th power of a serial transformation matrix signal; U tp is an n-bit input data vector signal at a time tp; S tp is the syndrome word signal (3) at the time tp; and S tp+1 .is the syndrome word signal (3) at a time tp+1; b) indicating with the syndrome word signal (3) for the ATM cell header signal with the n-bit parallel data signal: that no error has been detected; or that more than one error has been detected; or an erroneous bit to be corrected when only one error has been detected; c) delaying (4) the ATM cell header signal with the n-bit parallel data signal until the syndrome word signal (3) is generated; d) performing an error correction process (5) on the delayed n-bit parallel data signal in accordance with the syndrome word signal (3) generated; and e) generating a corrected ATM cell header signal (6), when required, in accordance with the syndrome word signal (3). Method for detection and correction of errors in ATM cell header signals according to claim 1; characterised in that the method further comprises the steps of providing an individual indication signal (7) for external use showing that no error has been detected, that more than one error has been detected, or that one error has been corrected. Device for detection and correction of errors in ATM cell header signals according to claim 1 in which a serial to parallel conversion (2) takes place for n bits in a serial data signal (1), obtaining an n-bit parallel data signal with a clock rate that is n times lower than an input clock rate of the serial data signal (1), having a serial to parallel converter (9), responsive to a serial data signal (14), for providing an n-bit parallel data signal; a frequency divider (8), responsive to a serial data clock signal (13), for providing an n-bit parallel data clock signal (15); characterised in that further comprises: a) syndrome word generator means (10), responsive to an n-bit parallel data bus (16), further responsive to an initialisation control signal (17) to set the initial values of the syndrome word generator means (10), and further responsive to the parallel data clock signal (15) to set the clock rate signal of said syndrome word generator means (10), for providing a syndrome word signal (20) in accordance with a functional relation: Stp+1. = Tn * Stp + Utp; where Tn is an n-th power of a serial transformation matrix signal; Utp is an n-bit input data vector signal at a time tp; Stp is the syndrome word signal (3) at the time tp; and Stp+1.is the syndrome word signal (3) at a time tp+1; and b) the syndrome word signal (3) adapted for indicating for the ATM cell header signal with the n-bit parallel data signal: that no error has been detected; or that more than one error has been detected; or an erroneous bit to be corrected when only one error has been detected; c) a delay circuit (11), responsive to the n-bit parallel data signal (16) and the parallel data clock signal (15), for generating a delayed n-bit parallel data signal (21) delayed by the time necessary to obtain the syndrome word signal (20) of the ATM cell header signal; and d) error correction means (12), responsive to the syndrome word signal (20) and the delayed n-bit parallel data signal (21), for providing an ATM cell header signal (25) in accordance with the indications contained in the syndrome word signal (20), as well as a no error detection signal (22) for showing that no error has been detected, a multiple error detection signal (24) for showing that more than one error has been detected, or a one error correction signal (23) for indicating that one error has been corrected. Device for detection and correction of errors in ATM cell header signals according to claim 3; characterised in that the means (10) adapted for generating the syndrome word (20) also receive an ATM cell header indication signal (18) in order to indicate the bits from which the syndrome word signal (20) has to be obtained. Device for detection and correction of errors in ATM cell header signals according to claim 4; characterised in that the means (10) adapted for generating the syndrome word (20) also receive an indication signal of the last eight bits in the ATM cell header signal (19) for an inversion of those bits that were previously inverted in the transmission part. Device for detection and correction of errors in ATM cell header signals according to claim 5; characterised in that the means (10) adapted for generating the syndrome word (20), when the number of bits is n=8, satisfy the following logic functions: (S 8 ) t+1 = (S 8 ) t + (S 7 ) t + (S 6 ) t + U 8 (S 7 ) t+1 = (S 7 ) t + (S 6 ) t + (S 5 ) t + U 7 (S 6 ) t+1 = (S 6 ) t + (S 5 ) t + (S 4 ) t + U 6 (S 5 ) t+1 = (S 5 ) t + (S 4 ) t + (S 3 ) t + U 5 (S 4 ) t+1 = (S 8 ) t + (S 4 ) t + (S 3 ) t + (S 2 ) t + U 4 (S 3 ) t+1 = (S 7 ) t + (S 3 ) t + (S 2 ) t + (S 1 ) t + U 3 (S 2 ) t+1 = (S 7 ) t + (S 2 ) t + (S 1 ) t + U 2 (S 1 ) t+1 = (S 8 ) t + (S 7 ) t + (S 1 ) t + U 5 where the symbol + indicates a module-2 sum, and where: (S i ) t is the i-th bit of the syndrome word (20) at the time t of the intermediate calculation, (S i ) t+1 is the i-th bit of the syndrome word (20) in the following period t+1 of the intermediate calculation; and U i is the i-th bit of the n-bit parallel data bus (16) that is applied to the means (10) to generate the syndrome (20).

Inventors: LEQUERICA CABELLO CARMEN MARIA, MERINO GONZALEZ JOSE LUIS, LEQUERICA CABELLO, CARMEN MARIA, MERINO GONZALEZ, JOSE LUIS, MERINO GONZALEZ, JOSE LUIS, C/ MONDEJAR P. 1410
Applicants: CIT ALCATEL, ALCATEL
Application year: 1993
Main classification: H04L12
IPC codes: H04L12, H04L1, H04Q11, H04Q3