Lead on chip type semiconductor integrated circuit device to avoid bonding wire short

Abstract: The lead structure for a first power supply potential is formed by first and second power supply leads 35a and 35b and a first connecting conductor part 36a connected thereto, and the lead structure for a second power supply potential is formed by third and fourth power supply leads 35c and 35d and a second connecting conductor part 36b connected thereto. The first connecting conductor part 36a and the second connecting conductor part 36b are placed at the central part of a semiconductor chip with a predetermined spacing between them, a plurality of first signal leads 34a and first signal pads 32a which are respectively connected thereto are disposed in the area between the first connecting conductor part 36a and a first edge 41, and a plurality of second signal leads 34b and second signal pads which are respectively connected thereto are disposed in the area between the second connecting conductor part 36b and a second edge 42.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a semiconductor integrated circuit device, and more particularly to a wiring connection structure in a lead on chip (LOC) type semiconductor integrated circuit device. Description of the Related Art Since an LOC type semiconductor integrated circuit device in which leads of a lead frame are extended on a semiconductor chip and the tip parts of the leads are connected to bonding pads by means of bonding wires enables one to increase the area of the semiconductor chip and to install the bonding pads not only in the periphery of the semiconductor chip but also in its central part, the device is in widespread use in recent years. An example of the prior art LOC type semiconductor integrated circuit device is shown in FIG. 1. Bonding pads 13 for supplying power supply potentials (abbreviated as power supply pads hereinafter) and bonding pads 12 for supplying and receiving clock signals, address signals, data input and output signals, or the like (abbreviated as signal pads hereinafter) are disposed in the direction of the long side of the semiconductor chip 11 at its central part. It should be mentioned that in each of the drawings a black square indicates a power supply pad and an unpainted square indicates a signal pad. Leads 15 for supplying power supply potentials (abbreviated as power supply leads hereinafter) and leads 14 for supplying and receiving various kinds of signals (abbreviated as signal leads hereinafter) come onto the semiconductor chip 11 with their tip parts connected to the corresponding power supply pads 13 and signal pads 12, respectively by the bonding wires 17. However, in this type of semiconductor integrated circuit has problem which the power supply leads 15 are required corresponding to a plurality of power supply pads 13 so that the leads of the lead frame end up with a large number. To solve this problem, if one employs a method in which a power supply wiring layer is formed on the semiconductor chip by photolithography technique and the power supply potentials provided are connected to the same plurality of power supply pads 13 by laying the wiring layer around, the number of the power supply leads 15 can be reduced. However, in this method the resistance and the parasitic capacity of the wiring layer is increased caused by the elongation of the power supply wiring layer, bringing about an adverse effect on the properties of the device. As a technique for eliminating the above-mentioned inconvenience, an LOC type semiconductor integrated circuit device as shown in FIG. 2 is disclosed in U.S. Patent No. 4,916,519. In the figure, a power supply lead structure for supplying a first power supply potential, for example, for supplying potential Vcc, is constructed by inserting a connecting conductor part 26a between a pair of power supply leads 25a and 25b to form a unified body, and another power supply lead structure for supplying a second power supply potential, for example, for supplying the ground (GND) potential, is constructed by inserting a connecting conductor part 26b between a pair of power supply leads 25c and 25d to form a unified body. The power supply pads 13 for supplying potential Vcc are connected to the connecting conductor part 26a by the bonding wires 17, and the power supply pads 13 for supplying potential GND are connected to the connecting conductor part 26b by the bonding wires 17. The signal pads 12 are connected to the corresponding signal leads 14 by means of the bonding wires 27. However, since the connecting conductor parts 26a and 26b for supplying potentials are disposed between the signal pads 12 and the signal leads 14, the bonding wires 27 grade separate the connecting conductor parts 26a and 26b, that is, cross over the connecting conductor parts 26a and 26b. However, in the above-mentioned structure there is a possibility of generating an accident in which the bonding wires 27 that straddle over the connecting conductor parts may sag down and the bonding wires 27 which form the signal system may be short circuited to the connecting conductor parts which form the power supply system. SUMMARY OF THE INVENTION A device according to the first part of claim 1 is known from US-A-5 068712. It is the object of this invention to provide an LOC type semiconductor integrated circuit device which minimizes the number of the power supply leads, reduces the resistance of the power supply system, and avoids short circuit accident between the signal leads and the power supply system. This is achieved by providing a device according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein: FIG, 1 is a plan view showing the relation between the semiconductor chip and the leads in a conventional semiconductor integrated circuit device; FIG. 2 is a plan view showing the relation between the semiconductor chip and the leads in another conventional semiconductor integrated circuit device; FIG. 3 is a plan view showing the relation between the semiconductor chip and the leads in a further convertional device; FIG. 4 is a perspective view showing the interior of the device of Fig. 3 by partially breaking the sealing resin; FIG. 5 is a plan view showing the relation between the semiconductor chip and the leads in an example that is useful for understanding the invention; and FIG. 6 is a plan view showing the relation between the semiconductor chip and the leads in a first embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 3 a plurality of first power supply pads 33a for supplying Vcc, a plurality of second power supply pads 33b for supplying the ground potential, and a plurality of first and second signal pads 32a and 32b are formed at the central part of a semiconductor chip 31 having 20 mmlong first and second edges 41 and 42 which run mutually parallel in the X direction and 10 mn long third and fourth edges 43 and 44 which run mutually parallel in the Y direction. On the other hand, a first and a second power supply leads 35a and 35b for supplying Vcc come onto the semiconductor chip 31 crossing the first edge 41 and extending in the Y direction over the third and the fourth edges 43 and 44, respectively, where they are connected continuously to a 0.5 to 0.8 mm wide first connecting conductor part 36a having a portion extending in the X direction to form a power supply lead structure for Vcc. Similarly, the third and the fourth power supply leads 35c and 35d for supplying the ground potential come onto the semiconductor chip 31 crossing the second edge 42 and extending in the Y direction over the third and the fourth edges 43 and 44, respectively, where they are connected continuously to a 0.5 to 0,8 mm wide second connecting conductor part having a portion extending in the X direction by maintaining a distance of 2.0 to 2.5 mm from the first connecting conductor part 36a to form a power supply lead structure for the ground potential. In addition, a plurality of first and second signal leads 34a and 34b for supplying and receiving various kinds of signals such as clock signals come onto the semiconductor chip for a distance of about 3 mm by crossing the first and the second edges 41 and 42, respectively. The whole of the plurality of the first signal pads 32a and a part of the first power supply pads 33a are disposed along the X direction in the space between the first edge 41 and the first connecting conductor pad 36a, where the first signal pads 32a are arranged facing respectively the bonding regions of the first signal leads 34a to be connected with them. Similarly, the whole of the plurality of the second signal pads 32b and a part of the second power supply pads 33b are disposed along the X direction in the space between the second edge 42 and the second connecting conductor part 36b, where the second signal pads 32b are arranged facing respectively the bonding regions of the second signal leads 34b to be connected with them. The remaining the first and the second power supply pads 33a and 33b are arranged in the space between the first connecting conductor part 36a and the second connecting conductor part 36b. With such a configuration, it is possible to connect by bonding the plurality of the first power supply pads 33a to portions near the lead structure for Vcc consisting of the first and the second power supply leads 35a and 35b, and the first connecting conductor part 36a by means of the respective first bonding wires 47, and similarly to connect by bonding the plurality of the second power supply pads 33b to portions near the power supply lead structure for the ground potential consisting of the third and the fourth power supply leads 35c and 35d, and the second connecting conductor part 36b by means of the respective first bonding wires 47. Since the connecting conductor part is a part of the lead frame and has the same material and film thickness as the lead, it is possible to neglect the resistance at the connecting conductor part. Moreover, according to the above-mentioned configuration, the plurality of the first signal pads 32a and the first signal leads 34a that are connected thereto are disposed in the area between the first edge 41 and the first connecting conductor part 36, and the plurality of the second signal pads 32b and the second signal leads 34b that are connected thereto are disposed in the area between the second edge 42 and the second connecting conductor part 36b. In other words, these pads and the bonding regions of these leads that are connected thereto are placed within the same region surrounded by a pair of power supply leads and a connecting conductor part. Accordingly, the bonding wires 37 that connect by bonding the first and the second signal leads 34a and 34b to the first and the second signal pads 32a and 32b will not traverse the power supply lead structures including the first and the second connecting conductor parts 36a and 36b. Because of this, there will be absolutely no short circuiting accident between the first bonding wires 37 and the power supply lead structures. Moreover, a bonding wire will never cross over other signal leads or other bonding wires as shown in the figure so that short circuiting accident that might otherwise occur will not take place. The bonding wires 37 and 47 are fine gold wires of, for example, diameter 0.03 mm and length 1.2 to 2.5 mm, and their connection to the pads is accomplished by thermocompression bonding method or ultrasonic method. In addition, the various kinds of signal leads, power supply leads, and connecting conductor parts form a lead frame, integrally formed from a copper plate of, for example, 0.2 mm thickness, which is affixed to the top surface of the semiconductor chip by an adhesive tape of, for example, 0.09 mm thick. Following the process shown in FIG. 3, the semiconductor chip and its vicinity are molded with resin as shown in FIG. 4, the leads that are led out of the side faces of sealing resin 40 are cut off from the lead frame, and bent by 90°, completing the semiconductor integrated circuit device. In FIG. 5, portions with identical or similar functions as in FIG. 3 are given the same reference symbols to avoid repeated explanation. In this second embodiment, the power supply pads 33a and 33b are all disposed in the area between the first connecting conductor part 36a and the second connecting conductor part 36b. On the other hand, the first and the second signal pads 32a and 32b are disposed in the Y direction perpendicular to the first and the second edges 41 and 42 of semiconductor chip 51, the first signal leads 34a are passed over the first edge 41 by extended in the Y direction, bent toward the X direction after laid on the semiconductor chip 51, and their tip parts are faced against the signal pads 32a. Similarly, the second signal leads 34b are passed over the second edge 42 by extended in the Y direction, bent toward the X direction after laid on the semiconductor chip 51, and their tip parts are faced against the signal pads 32b. Depending upon the shape of the semiconductor chip and the circuit layout there arises a case where the arrangement of this embodiment becomes preferable. An example of an embodiment of this invention in a semiconductor memory device is shown in FIG. 6. In FIG. 6 portions with identical or similar functions as in FIG. 3 are given the same reference symbols to avoid repeated explanation. A plurality of the first and the second signal leads 34a and 34b traverse the first and the second edges 41 and 42 of the semiconductor chip 61, and extend on the chip. The first signal leads 34a include a signal lead I 3 for data input and output, a signal lead WE for write enable, a signal lead RAS for row address strobe input, and signal leads A 0 to A 5 for address input, and the second signal leads 34b include signal leads A 6 to A 12 for address input, a signal lead OE for output enable, a signal lead CAS for column address strobe input, and signal leads I 4 and I 5 for data input and output. In addition, on their outside (on the right side of the figure) there are laid extended signal leads I 0 to I 2 for data input and output as third signal leads, traversing the first edge 41, and signal leads I 6 and I 7 are laid extended as fourth signal leads 34d traversing the second edge 42. On the other hand, the first power supply lead 35a for supplying Vcc traverses the first edge 41 and extends in the Y direction on the third edge 43 to enter the semiconductor chip 61, and the second power supply lead 35b enter the chip 61 by traversing the first edge 41, and they form a lead structure for Vcc by being connected continuously to the first connecting conductor part 36a. Similarly, the third power supply lead 35c for supplying the ground potential (GND) enters the semiconductor chip 61 traversing the second edge 42 and extending in the Y direction on the third edge 43, and the fourth power supply lead 35d enters the chip 61 by traversing the second edge 42, and they form a lead structure for GND by being connected continuously to the second connecting conductor part 36b. In this embodiment, a fifth power supply lead 35e for supplying Vcc unconnected to the first connecting conductor part 36a enters the semiconductor chip 61 by extending in the Y direction on the fourth edge 44 from the first edge 41, and similarly, a sixth power supply lead 35f for supplying GND unconnected to the second connecting conductor part 36b enters the semiconductor chip 61 by extending in the Y direction on the fourth edge 44 from the second edge 42. Further, a part of the power supply lead structure system for Vcc protrude in the direction of the second edge 42 and is bonded to the power supply pads 33a for Vcc in the vicinity of the second edge by the first bonding wires 47, and a part of the lead structure system for the grounding potential protrude in the direction of the first edge 41 and is bonded to the power supply pads 33b for the grounding potential in the vicinity of the first edge by the first bonding wire 47. The tip parts of the first to the fourth signal leads 34a to 34d are given indented forms 63 in order to prevent disconnection of wires due to the difference in the coefficients of thermal expansion of the sealing resin and the lead frame, and parts away from the tip parts are bonded to the first to the fourth signal pads 32a to 32d represented by unpainted squares by the second bonding wires 37. In addition, the parts protruding in the Y direction of the first to the sixth power supply leads 35a to 35f and the first and the second connecting conductor parts 36a and 36b are also given indented forms for similar purposes, and the parts near the indented forms are bonded to the first and the second power supply pads 33a and 33b by the first bonding wires 47. All of the first signal pads 32a connected to the first signal leads 34a, all of the third signal pads 32c connected to the third signal leads, and a part of the first power supply pads 32a and 32b are arranged in the vicinity of the first edge 41 along the X direction in parallel to the edge 41. Similarly, all of the second signal pads 32b connected to the second signal leads 34b, all of the fourth signal pads 32d connected to the fourth signal leads 34d, and a part of the first and the second power supply pads 33a and 33b are arranged in the vicinity of the second edge 42 along the X direction in parallel to the edge 42. The other part of the first and the second power supply pads 33a and 33b are arranged in the direction of the X direction at the central part, and its extension, of the semiconductor chip the area between the first connecting conductor part 36a and the second connecting conductor part 36b. According to such a configuration, as shown in FIG. 6, it is possible to make the second bonding wires 37 that are connected to the first and the third signal leads 34a and 34c and are respectively connected to the first and the third signal pads 32a and 32c toward the direction of the first edge 41, and the second bonding wires 37 that are connected to the second and the fourth signal leads 34b and 34d and are respectively connected to the second and the fourth signal pads 32b and 32d, neither traverse any part of the other power supply lead structure and other signal leads nor traverse other bonding wires. Consequently, it is possible to absolutely eliminate short circuiting accident of the wires due to the traversing. It should be mentioned in FIG. 6 that NC means an unused lead and an unpainted square not connected to a wire indicates and unused pad. Furthermore, the reason for giving a zigzag form to each lead outside of the semiconductor chip 61 is to prevent the lead from falling off the sealing resin due to external pulling force after it is cut off from the lead frame following resin sealing. Although the invenion has been described with reference to specific embodiments, this description is not meant to be construced in a limiting sense. Various modifications of the disclosed embodiments, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any modifications of embodiments within the true scope of the invention.

Claims: A semiconductor integrated circuit device including: a semiconductor chip (61), a plurality of power supply, bonding pads (33a, 33b) and a plurality of signal bonding pads (32a-d) formed on said semiconductor chip (61), a plurality of power supply, leads (35a, 35b, 35c, 35d) and a plurality of signal leads (34a, 34b) formed extended on said semiconductor chip (61) coming from outside of first and second opposing edges of said semiconductor chip (61), each of said leads having a bonding region; a connecting conductor part (36a, 36b) extended on said semiconductor chip (61) and connecting a pair of said power-supply leads (35a, 35b / 35c, 35d), first bonding wires (47) connecting said power supply bonding pads (33a, 33b) and said connecting conductor part (36a, 36b), second bonding wires (37) connecting said signal bonding pads (32a, 32b) and the bonding regions of said signal leads (34a, 34b), said signal bonding pads (32a, 32b) and the bonding regions of said signal leads (34a, 34b) connected thereto are arranged facing each other without interposition of said connecting conductor part (26a, 26b) between them, thereby avoiding short circuiting of said second bonding wires (37) over said connecting conductor parts (36a, 36b), characterized in that, all of said signal bonding pads (32a-d) and a part of said power supply bonding pads are arranged in the vicinity of said first and second edges, such that each of said bonding regions of said signal leads (34a, 34b) is provided between the corresponding signal bonding pad (32a, 32b) and said connecting conductor part (36a, 36b). A semiconductor integrated circuit device according to claim 1, further comprising a sealing resin cover (40) wherein said signal leads (32a, 32b) and said power supply, leads (35a, 35b, 35c, 35d) have indented forms in order to prevent disconnection of said wires (37, 47) due to a difference in the coefficients of thermal expansion of the sealing resin and said leads. A semiconductor integrated circuit device according to claim 1, further comprising a sealing resin cover (40), wherein said signal leads (32a, 32b) and said power supply leads (35a, 35b, 35c, 35d) have zigzag forms outside said semiconductor chip (61) to prevent said leads from falling off said sealing resin due to an external pulling force.

Inventors: TAKEUCHI YASUHITO, TAKEUCHI, YASUHITO, Takeuchi, Yasuhito, c/o NEC IC Microcomputer
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H01L23
IPC codes: H01L23