Low-noise pnp transistor

Abstract: A low-noise transistor comprising a cutoff region (38; 47) laterally surrounding the emitter region (36; 45) in the surface portion of the transistor and of such conductivity as to practically turn off the surface portion of the transistor, so that the transistor operates mainly in the bulk portion. In the NPN transistor, the cutoff region is formed by a P ring (38) in a P⁻ type well region (35), and, in the PNP transistor, by the N⁺ type enriched base region (47) between the emitter region (45) and the collector region (49).

Description: The present invention relates to a low-noise bipolar transistor, according to the preamble of claim 1. As known, in electronic devices, the term "noise" indicates a random fluctuation in currents or voltages at the device terminals, and may seriously limit the minimum signal level that can be handled by the device. The noise in each device is due to various physical causes, some of which have been known for some time. Of particular interest are what are known as "flicker" noise (also indicated 1/f) and "burst" noise, the first of which exists in all and the second in a significant percentage of devices. Flicker noise is commonly acknowledged to be caused by fluctuations in the number of carriers, due to entrapment of the carriers in surface layers of the device, i.e. to tunneling at the semiconductor-oxide interface. According to accepted theory, the carriers in the semiconductor may communicate with trap levels at a given distance within the tunnel oxide layer, and remain trapped for some time prior to being re-emitted. In the case of transistors, in particular, flicker noise sources are located at the base-emitter junction. Flicker noise is especially undesirable in the case of operational amplifier input transistors and audio preamplifiers. Burst noise, on the other hand, is caused by a sharp variation in current between two or more constant values. Variation frequency may be very low (less than 1 Hz) or high (hundreds of herz), in which case, burst noise may be confused with a high degree of flicker noise. This type of noise is generally attributed to the presence of defects, metal inclusions and precipitates in the space charge region of the junction; and the fluctuation in current depends on the extent, if any, to which the defect participates in conduction. The fact that burst noise is reduced by deficiency-reducing processes, such as gettering, would appear to bear out this theory. In the case of flicker noise, the noise power at the output terminals of a transistor is proportional to I B α , where I B is the base current and α a constant ranging between 1 and 2. In the case of burst noise, the output noise power is inversely proportional to the square of the gain of the transistor, so that, for a given collector current, high-gain transistors are less affected by flicker and burst noise as compared with low-gain types. It is an object of the present invention to provide a transistor designed to overcome the drawbacks posed by known solutions, and which, in particular, provides for reducing the noise on transistors by means of a flexible solution, adaptable to various requirements, and ensuring high breakdown voltages. A low noise bipolar transistor of the type defined in the preamble of claim 1 is disclosed in EP-A-0 029 548, describing an NPN transistor with a cutoff region arranged between the emitter region and the collector contact region and indicating the possibility of implementing an analogous transistor having regions specularly modified as to their P or N conductivity type. Patent Abstracts of Japan, vol. 14, no. 338 [E-954] 20 July 1990; Patent Abstracts of Japan, vol. 11, no. 161 [E-509] 23 May 1987 and Patent Abstracts of Japan, vol. 6, no. 230 [E-142] 16 November 1982 disclose cutoff regions formed by N type annular regions having a higher doping concentration than the rest of the base region; two of them also teach arranging the base contact in direct connection with the annular region. In none of these documents, however, the N type annular region extends for the entire length of the base channel to form PN junctions with P regions on both its sides. According to the present invention, there is provided a low-noise bipolar transistor as claimed in Claim 1. In practice, the transistor according to the present invention operates solely in the bulk portion and very little in the surface portion, thus minimizing flicker noise with no reduction in breakdown voltage and, at least in most cases, with no need for additional masks. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a cross section in perspective of a silicon wafer featuring a known type of PNP transistor; Figure 2 shows a cross section in perspective of a silicon wafer featuring a PNP transistor in accordance with one embodiment of the present invention; Figure 3 shows a cross section of a silicon wafer featuring a PNP transistor in accordance with a further embodiment of the present invention. Figure 1 shows a known PNP transistor with a P type substrate 21; an N type epitaxial layer 22; a junction isolation region 23 (formed by a bottom portion 23a and a top portion 23b on account of the two-step fabrication process); a buried layer 24; a P type emitter region 25; a P type collector region 26; a P - type ring 27 surrounding collector region 26 (P-well 27); and an N + type enriched region 28 at the base contact. The known transistor in Figure 1 presents considerable surface phenomena resulting in flicker noise; and a high total base resistance (including enriched region 28, epitaxial layer 22 and buried layer 24) resulting in less than optimum noise levels. Figure 2 shows a first embodiment of a PNP transistor in accordance with the present invention, wherein the transistor is formed in a silicon wafer including a P type substrate 41; an N type epitaxial layer 42; an N + type buried layer 43; and a P + type junction insulation region 44 (formed by a bottom portion 44a and a top portion 44b on account of the two-step fabrication process). Inside epitaxial layer 42 and facing surface 51 of the wafer, there are formed: a P + type emitter region 45; a P type annular region 46 surrounding and contiguous with emitter region 45; an N + type enriched base region 47 surrounding and contiguous with annular region 46; a P - type well region 48 surrounding and contiguous with enriched base region 47; a P + type deep collector region 49 surrounding and contiguous with well region 48; and a P type internal collector region 50 inside deep collector region 49, but facing surface 51 of the wafer, for connection to collector contact C. Figure 2 also shows schematically the base and emitter contacts B and E. In the Figure 2 transistor, location of the enriched base region 47 between emitter region 45 and collector region 49-50 provides for predominantly bulk operation of the transistor, i.e. in the deep inner portion of the epitaxial layer, and for cutting off the surface portion of the transistor, as shown schematically by the arrows indicating the path of the charge carriers (in this case, holes). In this case, non-participation of the surface portion in the transfer process provides for reducing flicker noise. Location of enriched base region 47 close to emitter region 45 also provides for considerably reducing base resistance, thus further reducing flicker noise. In the Figure 2 transistor, P type annular region 46 between emitter region 45 and enriched base region 47 is required for avoiding an N + /P + junction, which, as known, involves current leakage. Similarly, well region 48 prevents current leakage between regions 47 and 49. Collector region 49 is formed simultaneously with top portion 44b of junction isolation region 44, so that no additional masks are required. Deep portion 49 is required for the emitter region to "see" a sufficient collector area and ensure adequate current collection. On the other hand, the emitter area must be minimum, compatible with etching requirements, for preventing high gain of the parasitic vertical PNP transistor (formed by substrate 41, buried layer 43, epitaxial layer 42 and emitter region 45). Internal collector region 50 is not essential to operation of the lateral PNP transistor, and is provided solely for ensuring the thickness of the oxide over the collector region, at the point in which the contacts are opened, is equal to that of the oxide over regions 45 and 47. The Figure 2 structure requires no additional masks as compared with the standard process. In fact, as already stated, deep collector region 49 is formed simultaneously with top portion 44b of junction isolation region 44; internal collector region 50 is equivalent to standard transistor collector region 26 (Figure 1) and is formed simultaneously with annular region 46; and a P-well mask is already included in the standard process (for forming standard transistor region 27 - Figure 1). Following P implantation on substrate 41 for forming bottom portion 44a of isolating region 44, and N diffusion for forming buried layer 43, a typical process for fabricating the Figure 2 transistor therefore includes, in sequence: growing epitaxial layer 42; simultaneously forming top portion 44b of isolating region 44 and deep collector region 49; forming well region 48; forming annular region 46; and forming emitter region 45 and enriched base region 47. In the Figure 2 transistor, channel width W B between regions 46 and 48 is subject to a certain amount of inaccuracy, due to the distance between annular region 46 and well region 48 possibly varying as a result of misalignment of the respective masks. To solve this problem, an alternative structure may be employed as shown in Figure 3, which is identical to that of Figure 2 (and the corresponding regions of which are therefore indicated using the same numbering system), with the exception of P type annular region 46, which, in Figure 3, is replaced by a less heavily doped annular well region 46'. Annular region 46' is formed using the same mask as for well region 48, so that channel width W B ' is unaffected by misalignment of the masks. In the Figure 3 transistor, the gain of the parasitic vertical PNP transistor is also reduced by reducing the doping level of region 46' as compared with region 46. The area of annular well region 46' must, however, be minimum, for the purpose, as before, of maintaining the gain of the parasitic transistor as low as possible. To those skilled in the art it will be clear that changes may be made to the transistor and relative fabrication process as described and illustrated herein without, however, departing from the scope of the present invention.

Claims: A PNP low-noise bipolar transistor comprising an emitter region (45); a base region (42, 47); a collector region (49, 50) integrated in a layer of semiconductor material (42) defining a surface portion and a deeper bulk portion; said base region comprising an N type annular region (47) laterally surrounding said emitter region (45) and located in said surface portion and at least a portion of said layer of semiconductor material (42) for operating the transistor predominantly in said bulk portion; said layer of semiconductor material being N type and presenting a first doping level; said annular region (47) presenting a second doping level higher than said first doping; a base contact (B) being directly connected to said N type annular region (47); characterized in that said N type annular region (47) forms PN junctions at both its internal, smaller radius lateral edge and its external, larger radius lateral edges. A transistor as claimed in Claim 1, characterized in that said collector region comprises a deep annular layer (49) formed by an upper isolating diffusion embedded in said layer of semiconductor material (42) and laterally surrounding said N type annular region (47). A transistor as claimed in one of Claims 1 or 2, wherein said emitter region (45) is a P type and presents a third doping level; the emitter region comprises a P type annular layer (46; 46') located in said surface portion between and contiguous with said emitter region (45) and said annular region (47); said annular layer presenting a fourth doping level lower than said third level and forming one of said PN junctions with said N type annular region (47). A transistor as claimed in one of the foregoing Claims 1-3, further comprising a P type well region (48) located in said surface portion between and contiguous with said annular region (47) and said collector region (49), said P type well region having a doping level lower than said collector region (49) and forming one of said PN junction with said N type annular region (47). A transistor as claimed in Claims 3 and 4, characterized in that said well region (48) presents the same doping level and the same depth as said annular layer (46'). A process for fabricating a transistor as claimed in Claim 1, comprising an emitter region (45), a base region (42, 47) and a collector region (49, 50) integrated in a layer of semiconductor material (42) defining a surface portion and a deeper bulk portion; the process comprising the step of forming an N type annular region (47) in said surface portion of said layer of semiconductor material; said region laterally surrounding said emitter region (45) and operating the transistor mainly in said bulk portion, wherein said layer of semiconductor material (42) is of N type and has a first doping level, said step of forming an N type annular region comprising the steps of forming, in said layer of semiconductor material and said surface portion, an N type annular region (47) interposed between said emitter region and said collector region and having a second doping level higher that said first doping level; and forming a base contact above and in direct contact with said N type annular region (47); characterized in that said step of forming an N type annular region comprises forming PN junctions at both the internal, smaller radius lateral edge and the external, larger radius lateral edges of said N type annular region. A process as claimed in Claim 6, characterized in that it comprises the steps of: simultaneously forming an upper isolating region (44b) and a deep annular collector region (49) in said layer of semiconductor material (42); and forming, in said layer of semiconductor material (42) and said surface portion, a P type emitter region (45) surrounded at a distance by said deep collector region (49). A process as claimed in Claim 7, characterized in that it also comprises the steps of: forming, in said layer of semiconductor material (42) and said surface portion, a P type intermediate region (46; 46') between and contiguous with said emitter region (45) and said annular region (47); said intermediate region (46) presenting a lower doping level as compared with said emitter region; and forming, in said layer of semiconductor material and said surface portion, a P type well region (48) between and contiguous with said annular region (47) and said collector region (49). A process as claimed in Claim 8, characterized in that said steps of forming said intermediate region (46') and said well region (48) are performed simultaneously using the same mask. A process as claimed in Claim 8, characterized in that it comprises the step of forming an annular contact region (50) inside said deep collector region (49); said steps of forming said annular contact region (50) and said intermediate region (46) being performed simultaneously using the same mask.

Inventors: VILLA FLAVIO, VILLA, FLAVIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H01L29
IPC codes: H01L29, H01L21