Testing apparatus for testing and handling a multiplicity of devices

Abstract: A testing apparatus for testing and handling a multiplicity of devices, in particular electronic components such as integrated circuits or boards, comprises a test executor with a multiplicity of hierarchical operating levels assigned to respective physical or logical entities. At each level except the lowest one, test level controllers (10) are provided which include a pre-activity sequence of tasks (12), a call (13) to a lower operating level, a return (14) from said lower operating level, and a post-activity sequence of tasks (15). At the lowest level, device test processors execute the actual test.

Description: FIELD OF THE INVENTION This invention relates to a testing apparatus and a method for testing and handling a multiplicity of devices. More specifically, it relates to a tester for testing electronic circuitry, particularly integrated circuits. BACKGROUND OF THE INVENTION Electronic testing equipment, such as integrated circuit or board testers. has become more and more complex over the last decades. This is particularly due to the increased functionality of the circuitry to be tested - e.g., latest microprocessors, RISC CPU's. combined logic/memory IC's -, which calls for complex test procedures and high-sophisticated tester equipment. However, there is also another aspect related to this technology. This is the demand for an integrated tester environment, particularly under production conditions. That is. the integrated test environment does not only include the tester itself. but also supporting machinery, e.g., a prober or handler for automatic supply and exchange of devices to be tested (DUT's, e.g., integrated circuits or loaded or unloaded boards). Further, the handling machinery has to be able to deal with several physical or logical entities, such as lots or cassettes containing DUT's, and process them in the correct order. There are even logical or physical entities which have to be handled by the tester itself (not by additional handling tools); a common example is a wafer containing a multiplicity of integrated circuits (IC's) of the same kind. In the latter case, the contacts of the test head have to be advanced from one die to the next one as soon as the first one has been tested (or the wafer has to be advanced instead), and the correct steps have to be taken when the complete wafer has been tested (e.g., the wafer has to be removed and replaced with the next one). It will be understood that the sequence of operating steps to be performed is not easy to define. Even worse, they depend completely upon the kind of device to be tested (e.g., board, IC, or wafer), and upon the available equipment (e. g., kind of IC handler). Thus, the manufacturer of a tester cannot provide all of the required control hardware and/or software to a customer; instead, the customer has to adapt the tester himself to his specific demands. On the other hand, once all controllers for a given test equipment have been set up. there is seldom a need for later modifications, just as the available hardware components are not subject to frequent modification or replacement. What may in fact be changed are the test specifications of the IC or the board, but these are widely independent of the environmental specifications. It will be appreciated that the initial set-up of the control equipment by the customer is a laborious and time-consuming task. The manufacturers of IC or board testers have therefore already tried to meet the customer's demands by the provision of configurable control programs, i.e. control programs which permit adaptation to a specific test environment. However, the control equipment so far known in the art is still difficult and complex to operate. This is mainly due to the fact that the complete sequence of control functions has to be defined without any supporting structure, and that the operator is forced never to loose sight of the overall process, despite of the specific part of the process he is editing. His task can thus still be described as fully-qualified programming, despite of the available tools, with all related requirements in terms of time and work. Yet another drawback of the known control programs is that, once they have been created, they are not easy to modify, due to their complex structure. Further, it is not easy to split the task of making the set-up between multiple operators, just as any of them has to have the "full picture", i.e., knowledge about the overall testing process, and about the work of his colleagues. EP-A-0 296 884 discloses a system for in-circuit testing of an electronic circuit device which utilizes a distributed processing architecture wherein separate controllers are used to control the testing and for data collection and correlation of the collected data to the testing conditions. The testing may be conducted by sending test vector addresses from the test controller to each of the driver/sensor boards in the tester electronics, which addresses, in turn, are used to access driver memories containing the test conditions corresponding to the test vector addresses. The circuit containing the device is powered up and a tester coupling mechanism is connected to the terminals of the device. Determinations are made of the physical orientation of the device with respect to the tester coupling mechanism, and of whether the device terminals are in electrical contact with the tester mechanism and with the other components of the circuit. Functional testing is then performed, and failure data resulting from the test are stored and correlated to the test conditions which were applied during the functional testing. EP-A-0 296 884 represents the closest prior art and, in particular, discloses a testing apparatus for testing and handling a multiplicity of devices comprising a test executor provided for controlling operation of the individual test steps, at least one test adapter for receiving at least one device to be tested, a multiplicity of physical or logical entities in which the devices to be tested are arrange, a return from a specific level to another one, and the use of a device test processor. EP-A-0 068 994 discloses a method of testing with computers, wherein a unit is tested by a test instrument with the aid of a master, an intermediate and a slave computer. The latter connects to the test instrument for sensing its measurements. The method includes the step of despatching one of a plurality of instruction signals to the intermediate computer from the master computer. Another step is issuing to the slave computer, when it is not halted, a signal to halt from the intermediate computer after receipt by the intermediate computer of one of the instruction signals. Another step is transmitting from the intermediate to the slave computer, after the latter has halted, that one of a plurality of command signals corresponding to the currently dispatched one of the instruction signals. The method also includes the step of forwarding a go signal to the intermediate computer from the master computer and issuing to the slave computer from the intermediate computer a run signal signifying a request to run and sense measurements from the test instrument. There is a need for a new control processor which avoids the above drawbacks. SUMMARY OF THE INVENTION The present invention relates to a tester which includes a new test executor (or test program executor, i.e., the device which controls overall operation of the test). This test executor permits a "structured" set-up. Basically, a testing apparatus according to the invention comprises the features of claim 1. The invention also relates to embodiments with test level controllers incorporating a pre-activity sequence of tasks only, or a post-activity sequence of tasks only. The testing apparatus according to the invention includes a test executor for performing and controlling the necessary steps of testing and test processing. For this purpose, it controls a test adapter which receives the DUT (in case of an IC tester, this may be a test socket), as well as handling tools for processing the physical or logical entities into which the DUT's are arranged. Again referring to an IC tester, such a handling tool may be a prober or handler. In contrast to the prior art approach, the test executor according to the present invention comprises a high-sophisticated structural segmentation. Specifically, it makes use of a "level model" which reflects all of the various handling or packaging entities, in descending order. Every logical or physical entity into which the devices to be tested are arranged is reflected by a corresponding (physical or logical) hierarchical operating level. It is important to note that the entities in which the DUT's are arranged are not entities of equal importance, such as ceramic packaging versus plastic packaging. Instead, the operating levels are arranged such that an entity at a certain level comprises, i.e., includes at least one, but preferably multiple entities of lower order (this is why the term "hierarchical operating level" has been used). For instance, suppose that wafers to be tested in an IC tester are arranged in cassettes, wherein each cassette contains multiple wafers. On the other hand, as each wafer contains a multiplicity of identical IC's, we end up with the hierarchical operating levels "cassette - wafer - IC". If the cassettes are arranged in lots (which is, by the way, a logical entity, in contrast to the physical entities so far discussed), we have the levels "lot - cassette - wafer - IC". It is worth mentioning that this is a preferred embodiment of the invention. However, if we look, e.g., at a tester for parts of the automobile industry, the levels could be "lot - box - package - part". It is understood that the various levels, and their operating characteristics, differ from application to application. Thus, what the customer has to do is apply the level structure, and the operating steps at each level, to his specific demands. In order to make this task easy, the present invention provides a unified structure at each level which is characterized by a test level controller. All test level controllers - regardless of the very level they serve for - are of similar structure. That is, each test level controller includes preferably: A block of so-called pre-activity task sequences. These could be, in a preferred example: Communication (dialog) with the user, e.g., entry of process data, a user identification (ID) number, a level ID number, sublevel count etc.; input of process data, e.g., by reading such data from an appropriate execution input file; control command input, e.g., operator instructions such as to skip or repeat the very test level controller, quit operation or go on; operation of a handling tool, e.g., a prober. Suppose, for example, that the test level controller controls the "wafer" level of an IC tester. In such case, the pre-activity sequence could include an instruction to put the next wafer onto a test bed; a call to a lower (preferably, but not necessarily the next lower) operating level; a return from said lower operating level; and a block of post-activity task sequences. These could preferably be: Data logging, i.e., processing and/or storing of acquired process data in a data logging file; again, operation of a handling tool - in the above example of a "wafer" level, this could be an instruction to remove the last wafer; the post-activity sequence could also include a communication with the user, and/or appropriate command input. This "test level controller" structure is of a very general, uniform and easy-to-learn nature. As soon as a test level controller has completed its pre-activity task sequence, it calls a test level controller at a lower level. If appropriate, this further test level controller calls deeper levels, and then returns operation to the calling test level controller. That is, the test operation is segmented into a "cascaded structure". However, there is one exception. This is the lowest hierarchical operating level which includes the actual test of the device; in case of an IC tester, this may be the appliance of electrical test ("stimulus") signals to the DUT, and the receipt of response signals from the DUT. Operation at this level is not controlled by a test level controller of the above kind, but rather by a device test processor which contains and executes the instructions for the actual test. In contrast to the test level controller, the device test processor does not include the call of some processor or controller at a lower level (and, consequently, also no "return" function). Further, it may or may not include some pre- or post-activity task sequences (usually, it will not). This operating concept has a multiplicity of outstanding advantages. First, all test level controllers are of basically the same kind, and thus easy to learn and to apply. They implement a uniform structure which does not require an extensive learning curve. Thus, a lot of time and money can be saved. Second, the engineer at a production floor may easily adapt the operating environment to his needs. He does not have to train his operators (of lower skills) to the complete given test environment. In other words, the easy process of customization (e.g., interactive changes) provided by the present invention allows to keep to the knowledge and traditions already present at the relevant production floor. This increases safety and reliability, as the tester so-to-say adapts to human knowledge, instead of createing a need to adapt a human being to machine demands. Third, it is very easy to modify or adapt an existing test structure. Suppose, for example, that an additional operating level has to be introduced, just because the cassettes containing wafers are delivered in packages. The additional "package" operating level may be easily implemented, without or only with minimal modifications in the adjoining levels. It is understood that this feature saves an enormous amount of time and money. It is even possible to deliver a testing apparatus with a "standard" operating model, which has only to adapted, i.e., modified by the customer ! Fourth, it is easy to split the various tasks of setting-up the tester control functions among various operators. This is just because the tasks can easily be segmented; for example, an operator may set up a certain operating level, with none or only minimal knowledge of the work of his colleagues, and without having insight into the complete test procedure. Another important feature, in terms of easy modification, is that the device test modules can be easily replaced, or additional device test modules can be included, without interfering with the existing structure. By the way, this is the most common case, as the features of IC's or other devices to be tested are constantly enhanced, whereas the overall test equipment is seldom modified. It is evident that this novel and advantageous concept may be easily enhanced. For example, it is not always necessary to call, from a certain operating level, the level just below; instead, one may allow "jumps", in dependence of operator instructions, or on an automatic basis. Likewise. operation of a test level controller may be repeated without return to the preceding level (e.g., in dependence of the test results), or the call of the next lower level may be skipped. It is also possible to call another test level controller at the same operating level. All of this functionality may be performed under operator or automatic control. It has already been mentioned that the present invention is particularly suited for integrated circuit testers or board testers. However, it may also be useful for other kinds of testing equipment, such as test of goods upon delivery, mechanical testing, quality tests and the like. The invention also relates to a method for testing and handling a multiplicity of devices according to claim 13. BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be explained, by means of a non-limiting example, with reference to the accompanying drawings, in which: Fig. 1 depicts an overall diagram of an integrated IC testing environment, Fig. 2 is a structural diagram of a test level controller, Fig. 3 depicts stacking of test level controllers, and device test processors, at various operating levels in the form of a timing diagram, Fig. 4 shows an example of a pre-activity sequence of tasks and Fig. 5 an example of a post-activity sequence of tasks. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to Fig. 1, ref. no. 1 denotes an integrated circuit tester (IC tester) 1 including a display 2, a keyboard 3 and all of the control circuitry required to test an integrated circuit, in particular a test controller or executor (which is basically a computer system). It is understood that the outer appearance mav also be quite different; e.g., the data console may be separated from the tester itself. Leads 4 connect the IC tester with a test head 5 for applying and contacting integrated circuits, or wafers to be tested (the so-called "DUT's", i.e., devices under test). Device 6 is a handler able to handle cassettes which, in turn, contain wafers to be tested (the mechanical details of handler 6 are not shown in detail in Fig. 1, as they are anyway well known in the art). The handler takes a wafer from a cassette and applies it to test head 5 which sits right on top of the handler. The apparatus proceeds from IC to IC on a single wafer by advancing the wafer under test head 5 (of course, one could also move the test head instead, but this is not common practice). Tested wafers are removed and replaced by untested wafers. The same applies to cassettes. Provided the cassettes pertain to one lot of DUT's to be tested, we can thus divide the test process into various logical and physical entities in a hierarchical order. The entity of the highest order is the lot, i.e., the totality of the cassettes (this is a logical entity, as no common packaging, or other tangible means which keep the cassettes physically together, is provided for all of the cassettes). If we go on in descending order, the next operating levels are the cassette level, the wafer level and the IC (die) level. All of these entities are physical entities, as their elements are kept together by physical means. It will be understood that automated test processing requires that all steps are performed in the correct order. For example, once all wafers in a cassette have been tested, the apparatus has automatically to advance to the first wafer in the next cassette. Likewise, after the (successful or unsuccessful) test of a die, the apparatus has to advance to the next die, but only until all dice on the wafer have been tested, in which case the wafer has to be exchanged. However, the test environment shown in Fig. 1 is only an exemplary embodiment. It will be noted that there exist a variety of alternate embodiments; for example, the "lot" level may be removed, the wafers may be packed in other units than cassettes (e.g., racks), or they may not be packed at all. Likewise, the hierarchical structure is different in case the devices under test are not wafers, but rather IC's (either unpacked or packed, such as in dual-in-line-packages). Yet another example are the various test adapters available on the market. In all of these cases, the user of the test environment (i.e., the "customer" from the viewpoint of the manufacturer of the tester) has to be able to adapt the test controller to his specific embodiment and demands, and it will be appreciated that this may be a costly, time-consuming and error-prone process. The present invention provides a unique solution for this problem by the provision of a unified test structure which includes test level controllers of basically the same operating characteristics and outer appearance at each level (whether the corresponding entities is of logical or physical nature). Fig. 2 depicts a structural diagram of such a test level controller 10. Operation starts at arrow 11. This is the entry from the next higher operating level (provided one exists; if not, it is simply the call from a supervisor program or an operating system). Box 12 includes a set of so-called "pre-activity sequence of tasks". i.e., tasks or actions to be performed at this very level before the next lower level is called, such as a dialog with the operator (more examples will be discussed below). Operation then proceeds to the next lower hierarchical operating level, as indicated by arrow 13. When the test level controller at the next lower level has performed its task (which may include calls to even lower levels), operation returns to test level controller 10, see arrow 14. The test level controller then executes a set of "post-activity sequence of tasks" 15, like data logging (see more detailed discussion below). Thereafter, operation returns to the calling process, i.e., the next higher operating level (arrow 16). As the test level controllers at each operating level are of basically similar structural design, we obtain thus a unified, "stacked" overall structure which permits easy modification and adaptation. In particular, a "sample" test executor may be provided to the customer for the purpose of adaptation, such that he does not have to start from scratch when creating his own test procedure. The above explanation of the present invention requires some additional remarks. First, it will be understood that the lowest hierarchical operating level requires a different structure. This is just because there is no lower level which may be called. It is this very level - the test level - that contains the "device test processors", i.e., processors which directly execute the test of a die, such as test of the leakage current, the DC characteristics, the AC transmission characteristics, the response time etc. of a specific IC. For more details of the features and characteristics of the device test processor, reference is made to the European patent applications EP-93115096.5, EP-A-646 802, EP-A-541 840, EP-A-541 837 and EP-A-541 839. Second, there may be conditions which interrupt the regular flow of operation within a test level controller as described above. Suppose, for example, that the operator renders (during the pre-activity sequence of tasks) an instruction to skip an operating level, or that this information is retrieved from an execution input file. In such case, the call of the next lower operating level may be skipped, as indicated by dashed arrow 17. Likewise, a test level may be repeated (dashed arrow 18), e.g., if a specific test has failed. The last exception is continuation at the same test level, e.g.. In response to an appropriate operator or command file instruction in the course of the pest-activity sequence of tasks (dashed arrow 19). Reference is now made to Fig. 3 which depicts the typical operation of the various test level controllers, as well as the device test processors, in the embodiment of Fig. 1 (time is running to the right). The "lot" level is designated as 20; likewise, the "cassette" level, the "wafer" level and the "die" level are labelled as 21, 22 and 23, respectively. The "test" level is below (23a). Boxes with hatching inclined to the right indicate a pre-activity sequence of tasks in Fig. 3, whereas hatching with inclination to the left indicates a post-activity sequence of tasks, and horizontal hatching relates to a device test processor. Operation starts at the "lot" level. namely the pre-activity task sequence 24 of the test level controller assigned to the lot level. At each level, the test level controllers execute now their respective pre-activity task sequences, as indicated by reference numbers 25. 26 and 27, and perform a call to the test level controller of the next lower level. This scheme continues down to the lowest level, wherein a device test processor 28 performs an actual test of a die. After execution of the post-activity task sequences 29 and 30 of the corresponding test level controllers, the latter are restarted, as indicated by pre-activity task sequence boxes 31 and 32. Thereafter, the next die is tested by a device test processor (box 33). This scheme continues until three dice have been tested (assuming that one wafer carries three dice - this is not a very reasonable assumption which has only been made for purposes of illustration, as an actual wafer will carry considerably more dice), and all test level controllers execute their respective post-activity task sequences, see boxes 34, 35. 36 and 37. Again, processing of more than one wafer, or more than one cassette have not been shown in Fig. 3 for graphical purposes, but it will be understood that such processing is performed in basically the same manner as multiple dice are tested, although at higher levels of operation. Fig. 4 depicts a typical example of a pre-activity sequence of tasks to be performed by a test level controller. Entry into the pre-activity task sequence is indicated by dashed arrow 38. A first box 39 includes input of process data, such as level identification, sublevel count or reading data from an execution input file. Box 40 comprises a dialog with the operator, i.e., control command input such as an instruction to skip or repeat a level, to continue at the same level or to quit operation (cf. Fig. 2). (It will be understood that, instead of interactive operation, the respective instructions may also be read from a command file). Finally, box 41 includes instructions for handling devices, such as for handler 6 (Fig. 1), just before operation proceeds (dashed arrow 42). A similar example of a post-activity task sequence is given in Fig. 5. After entry (dashed arrow 43), appropriate control commands are rendered to the handling device (box 44). Thereafter, data (such as test data obtained from a DUT) are logged, e.g., in a data log file (box 45), and operation proceeds (dashed arrow 46). However, it will be understood that the above examples for performing the pre-activity and post-activity sequences of tasks are not strictly necessary for practicing the present invention, and that they could be structured differently; for example, the post-activity task sequence may also include a dialog with the operator.

Claims: Testing apparatus for testing and handling a multiplicity of devices, comprising (1.1) a test executor provided for controlling operation of the individual test steps, (1.2) at least one test adapter (5) for receiving at least one device to be tested, (1.3) a multiplicity of physical or logical entities in which the devices to be tested are arranged, said test executor includes at least two hierarchical operating levels each assigned to one of said physical or logical entities, and further including (1.4) at least one test level controller (10) set up to perform at least the following sequence of operating steps: (1.4.1) a pre-activity sequence of tasks (12), if available; (1.4.2) a call (13) to a lower hierarchical operating level; (1.4.3) a return (14) from said lower operating level; and (1.4.4) a post-activity sequence of tasks (15), if available; and wherein (1.5) the lowest hierarchical operating level is processed by at least one device test processor (28,33) provided for the test of parameters of individual devices. Testing apparatus according to claim 1, wherein the at least one test level controller (10) is set up to perform the operating step of calling to a lower hierarchical level by calling to the next lower hierarchical level. Testing apparatus according to claim 1 with at least three hierarchical operating levels, wherein the test level controller (10) assigned to the highest hierarchical operating level is set up to perform a call to the test level controller (10) assigned to the next lower hierarchical operating level, and so on until operation arrives at the lowest hierarchical operating level to which said device test processor (28,33) is assigned. Testing apparatus according to claim 1, wherein the test level controller (10) includes, in its pre-activity sequence of tasks, an instruction (17) to skip the call to a lower hierarchical operating level if an appropriate indicator is set. Testing apparatus according to claim 1, wherein the test level controller (10) includes, in its post-activity sequence of tasks, an instruction (18) to return to its pre-activity sequence of tasks if an appropriate indicator is set. Testing apparatus according to claim 1, wherein the test level controller (10) includes, in its post-activity sequence of tasks, an instruction (19) to continue operation at the same hierarchical level of operations. Testing apparatus according to claim 1 including at least one handling tool (6) for processing said physical or logical entities. Testing apparatus according to claim 1, wherein the pre-activity sequence of tasks (12) includes at least one of the following tasks: input of process data (39), command input (40), operation (41) of at least one handling tool (6). Testing apparatus according to claim 1, wherein the post-activity sequence of tasks (15) includes at least one of the following actions: data logging (45), operation (44) of at least one handling tool (6). Use of the testing apparatus according to claim 1 as a testing apparatus for electronic components. Use of the testing apparatus according to claim 10 as a testing apparatus for integrated circuits. Use of the testing apparatus according to claim 10, wherein the hierarchical operating levels include at least one of the following levels: lot level (20), cassette level (21), wafer level (22), die level (23). Method for testing and handling a multiplicity of devices which are arranged in a multiplicity of physical and logical entities, the method comprising the steps of: (13.1) calling a test level controller (10), (13.2) performing a pre-activity sequence of tasks (12), if available; (13.3) calling (13) a next level controller at a lower hierarchical operating level; (13.4) returning (14) from said lower hierarchical operating level; (13.5) performing a post-activity sequence of tasks (15), if available; wherein said next level controller is a device test processor (28,33) at the lowest hierarchical operating level, and another test level controller (10) in all other cases.

Inventors: BIWER ALFRED, LANGHOF MARCO, BIWER, ALFRED, LANGHOF, MARCO
Applicants: HEWLETT PACKARD GMBH, HEWLETT-PACKARD GMBH
Application year: 1993
Main classification: G01R31
IPC codes: G01R31, H01L21