Circulating pointer monitor

Abstract: In a system for enforcing the validity of circulating pointers, one or more target pointers are generated and compared to circulating pointers. If a pointer does not circulate through the system within a prespecified time, then a pointer has been lost and an error is reported. If a circulating pointer matches a target pointer, it is suppressed by being removed from the set of circulating pointers. Another timer is then set to determine whether further circulating pointers match a target pointer. If so, then multiple pointers to the same location are present and all duplicate pointers are suppressed. After expiration of the second time, the target pointers are added to the set of circulation pointers. This process repeats with new target pointers, so that the validity of the set of the set of circulating pointers is verified.

Description: Cross-Reference to Related Application This application is related to EP-A-0 581 486, hereinafter referred to as 'HBPS', filed concurrently with this application. Technical Field This invention relates to the field of resource allocation in computer systems and computer controlled systems, and more specifically to the area of monitoring circulating pointers to ensure validity. Background of the Invention Efforts to increase speed and throughput of various systems, specifically packet switching systems, involve using circulating pointers. These systems store data at an address pointed to by a circulating pointer, and then switch the pointer instead of switching the data through the system. Circulating pointer schemes increase switching speed because less data is being moved through the system (i.e., pointer instead of an entire packet). For example, a high bandwidth packet switch disclosed in HBPS comprises a plurality of input ports, each comprising a first plurality of time slots; a plurality of output ports, each comprising a second plurality of time slots; and a plurality of message buffers, each being equal to or greater than the size of the largest expected message; all of which are interconnected by a bus. A buffer manager connected to the input ports and the output ports selects a circulating pointer to one of the message buffers in response to notification of receipt of an incoming packet during one or more time slots on one of the input ports. The buffer manager delivers the selected pointer to the receiving input port, the input port saves the destination address from the message and uses the circulating pointer to write the incoming message from the incoming time slot(s) to the selected message buffer. When the write to the message buffer is completed, the input port delivers the circulating pointer and the destination address to a router connected to the input ports and the output ports. The router selects one of the plurality of output ports responsive to the destination address, and delivers the circulating pointer to the selected output port. The output buffer uses the circulating pointer to retrieve the message from the message buffer and then transmits the message through the appropriate time slot(s). The output port then delivers the circulating pointer to the manager for reuse. In the above-described system, or in a software system that uses circulating pointers, there is a risk that a circulating pointer may become duplicated or lost. A small voltage change, component weakness, programming error, or the like, which occur regularly in large, complex systems, can affect one bit or many bits in a pointer, which causes duplication or loss of a pointer. If a circulating pointer is lost, then there is a memory resource that cannot be accessed. If a circulating pointer is duplicated, then multiple writes occur to the same location in memory, and data is directed to the wrong destination or corrupted. Therefore, a problem in the art is that there is no method for enforcing the validity of circulating pointers. EP-A-0 492 025 discloses a FIFO buffer memory for use in the output queue of a packet switching network. Each output port is associated with a respective memory access control. Each memory access control is connected to each input port. The memory access control associated with a particular output port receives all incoming packets destined for that port and stores the packets in adjacent memory locations, which form the FIFO buffer queue. Alternatively, instead of storing the packets, the FIFO may be used to store pointers to the packets stored in another memory. This publication recognizes the risk that some packet switch designs may cause the loss of packets when insufficient internal resources are available to accommodate a large number of packets arriving in a given time. The architecture of the buffer memory is designed to avoid packet loss. EP-A-0422 910 discloses several high-capacity memory-based packet switches. In a first embodiment, several input ports are connected to a centralized queue memory; the memory is connected to several output ports and a processing means. Each input port includes an input buffer. Each output port includes an output buffer. Packets are received at the input ports and read into the corresponding input buffers. Once a packet is received at the input buffer, the packet is transferred to a centralized queue memory over an "N-bit" parallel bus. The packet is then transferred to a respective output buffer selected according to an address received with the packet and then serially clocked out of the switch. Circulating pointers may be used to manage the central memory. Summary of the Invention A method and system according to the invention are as set out in the independent claims. This problem is solved and a technical advance is achieved in the art by a pointer monitor that enforces the validity of circulating pointers. A target pointer generator in the pointer monitor generates one or more target pointers within a predefined range of the set of circulating pointers and compares the target pointers to circulating pointers. A first timer is set, and if a pointer does not circulate through the pointer monitor within a prespecified time, that is, no circulating pointer matches a target pointer before the timer expires, then a pointer has been lost and an error is reported. If a circulating pointer matches a target pointer, the circulating pointer is suppressed by being removed from the set of circulating pointers. Another timer is then set to determine whether further ones of the set of circulating pointers match the target pointer. If another pointer matches, then multiple pointers to the same location in memory are present and all duplicate pointers are suppressed. After expiration of the second timer, the target pointers are added to the set of circulation pointers. This process repeats with new target pointers, so that the validity of the entire set of circulating pointers is verified. Advantageously, the number of pointers checked in one prespecified time period may be a function of system congestion. Brief Description of the Drawing FIG. 1 is a block diagram illustrating an exemplary embodiment of this invention in the context of a buffer manager as described in HBPS; FIG. 2 is a diagram illustrating a monitor circuit according to an exemplary embodiment of this invention; FIG. 3 is a state diagram illustrating the permitted states and the transition between states in the state machine of FIG 2; and FIGS. 4 and 5 are a flow charts describing the flow of control of a monitor circuit according to the exemplary embodiment of this invention. Detailed Description FIG. 1 is a block diagram of a buffer manager 100, including a monitor circuit 110 according to the exemplary embodiment of this invention. Buffer manager is similar to buffer manager 208, FIG. 12 of HBPS, but simplified for purposes of this application. Buffer manager 100 allocates circulating pointers for storing packetized data received from an incoming bus. The pointer may then be handed off to a router which then determines the destination and hands off the pointer to an output. The output then uses the pointer to read the data from the buffer and distribute the data according to the destination. The output then returns the pointer to the buffer manager. This system is more fully described in HBPS. The monitor circuit according to this invention has, however, far wider applicability than this particular exemplary embodiment and this embodiment is by no means limiting. Buffer manager 100 comprises a FIFO controller 112, a monitor circuit 110 and a memory FIFO 114 that stores circulating pointers until used by the system. FIFO controller 112 controls the reading and writing of FIFO 114 in response to pointer requests on input lead 118 and requests for returning pointers on lead 140. Pointer monitor 110 enforces pointer validity as will be described further in connection with FIG. 2 below. FIFO 114 comprises a RAM which is initialized at the time of system initialization via processor interface 116. Processor interface 116 comprises a bus connected to a microprocessor (not shown), as is known in the art, which provides initialization and updates to FIFO 114. Processor interface 116 is also used to deliver reports of errors found by pointer monitor 110, as will be described below. Requests for pointers are received by FIFO controller 112 on pointer request line 118. In response, FIFO controller 112 causes a pop operation to be sent over pop address line 120 to pointer FIFO 114. Pointer FIFO 114 delivers the pointer to the allocated pointer bus 122 and valid line 124 is asserted by FIFO controller 112. Parity checks, as are known in the art, may be performed at this point. Returning pointers arrive on returning pointer bus 126 when valid line 128 is asserted. A first check of the range of the pointer is made in box 130, as is known in the art. This check suppresses pointers that point to locations outside the range of the buffer memory. If this test passes, then the pointer is delivered via bus 130 to monitor circuit 110 and a further valid line 134 is asserted. Monitor circuit 110 enforces the validity of circulating pointers by generating one or more target pointers within a pre-specified range, and comparing the target pointers to pointers circulating through the monitor circuit, that is, pointers returning after use. If a pointer is not encountered within a prespecified time, then it is presumed that the pointer has been lost and an error is reported. When a pointer is encountered, it is suppressed so that it is removed from circulation. A second timer is then set to determine whether the pointer is encountered again. If the pointer is encountered again, then all encountered pointers are suppressed and an error is reported. After the second timer expires, the generated pointer is then pushed onto pointer FIFO 114 as a circulating pointer. Monitor circuit 110 then generates a further one or more target pointers and performs the same tests on these new targets. This method continually repeats, with new target pointers being generated, etc., so that monitor circuit 110 checks all of the set of circulating pointers. After monitor circuit 110 performs its tests of each target pointer, then monitor circuit 110 places the pointer on data bus 136 and asserts the push request line 138 to the FIFO controller 112. FIFO controller 112 sends the next address to FIFO 114 via push address bus 142, and FIFO 114 writes the received pointer to the assigned memory location. If there is a high demand for pointers, that is, many circulating pointers are being used at a given time, FIFO controller 112 informs monitor circuit 110 via system congestion line 144. Monitor circuit 110 responds by generating fewer target pointers, thus taking less system time. Turning now to FIG. 2, monitor circuit 110 according to an exemplary embodiment of this invention is shown. In FIG. 2, monitor circuit 110 includes a pointer generator 202 which generates target pointers within a prespecified range and delivers the generated target pointers to a content addressable RAM 204. Content addressable RAM 204 stores the target pointers in predetermined memory locations, herein labeled pointer targets 206. As a pointer is returned on the return pointers bus 132 and valid line 134 is asserted, the returned pointer is also delivered to a plurality of comparators 208. Target pointers are also delivered to these comparators 208 in content addressable RAM 204. When a target pointer matches a returning pointer, then a corresponding state machine 210 is incremented, which causes the corresponding state machine 210 to transition to a valid state. After a predetermined time, control unit 211 determines which of the pointer targets were encountered. Control unit 211 comprises a state machine, including combinational logic 212, a register 214, and a feed back loop 215, as is known in the art. If the pointer delivered on return pointers bus 132 does not match any of the target pointers, as determined by combinational logic 212, then nothing is done to block the valid line 134 from being asserted. Valid line 134 asserts the push request through OR gate 220, and the pointer is delivered on data bus 136 to FIFO 114 (FIG. 1). If the pointer matches one of the target pointers, then comparator 208 asserts line 222 which increments state machine 210 and causes OR gate 224 to assert push block line 226. Asserting push block line 226 causes AND gate 228 to block the valid signal which suppresses the pointer on return pointer bus 132, thus preventing the pointer on return bus 132 from returning to FIFO 114 (FIG. 1) and being reused. After a predetermined period of time, combinational logic 212 checks state machines 210 to determine whether all target pointers were encountered. If not, an error condition is reported. A second timer is then set. Because all of the target pointers have been suppressed, as described above, if a further circulating pointer matches a target pointer, then a duplicate pointer has been found. State machine 210 increments, thus transitioning to the duplicate state, and combinational logic 212 may report an error condition. After the second timer expires, control unit 213 causes each target pointer to be written to data line 136 through selector 218, and register 214 asserts the push request, thereby pushing the target pointer onto FIFO 114 (FIG. 1). Processing of the next set of target pointers then occurs. Processing continues until all of the valid pointers are checked; then processing begins again. Turning now to FIG. 3, a state machine diagram is shown showing the three states of state machines 210 of FIG. 2. In this exemplary embodiment of this invention there are three states: cleared 300 (00), valid 310 (01), and duplicate 320 (11). Processing begins in cleared state 300. When a returning pointer matches the generated pointer, processing moves to valid state 310. If the target pointer is not found again during the second predetermined time then a reset causes the state to change back to cleared 300. If a second pointer is encountered during the predetermined time then the state transitions to the duplicate state 320. Processing transitions from duplicate state 320 to duplicate state 320 every time another pointer is encountered that matches a target pointer. Eventually, a reset causes the state to change from duplicate state 320 back to cleared state 300. Turning now to FIG. 4, processing according to the exemplary embodiment of this invention in control of FIG. 2 is shown. Processing begins at 400; starting at box 402, the target pointers are loaded into the content addressable RAM 204. At box 404, the state machine is reset, and then a timer is set at box 406. In decision diamond 408, a test is made to determine whether the pointer being returned is equal to one of the generated pointers. If the pointer being returned is equal to one of the generated pointers, then processing proceeds to box 410 where the state machine is incremented, and then processing continues to box 412 where the return pointer is suppressed. Processing from both decision diamond 408 and box 412 continues to decision diamond 414 where a determination is made if the timer has expired. If the timer has not expired then processing proceeds back to decision diamond 408. If, in decision diamond 414, the timer has expired, then processing continues to decision diamond 416 where a determination is made whether all first state bits in state machines 210 are set. If all state machine bits are not set then an error has been encountered and processing continues to box 418 where an error routine is invoked. Processing continues through connector A to FIG. 5. Turning now to FIG. 5, from connector A, a timer is set at box 500. At decision diamond 502, a determination is made whether a pointer being returned is equal to one of the targets in the content addressable RAM. If the pointer being returned is equal to one in the addressable RAM then processing continues to box 504 where the state machine is again incremented. Processing proceeds to box 506, where the pointer is suppressed. Processing from both decision diamond 502 and box 506 continues to decision diamond 508 where a determination is made whether the timer has expired. If the timer has not expired then processing returns to decision diamond 502. If, in decision diamond 508, the timer has expired then processing proceeds to decision diamond 510 where a determination is made whether any second state bits in state machine 210 are set. If a second bit is set, then processing proceeds to box 512 where an error routine is invoked. Following the error routine from box 512, or if no second bit is set in state machine 210 in decision diamond 510, the process continues to box 514, where the generated pointers are pushed into the pointer FIFO and processing ends at 516. It is to be understood that the above-described embodiments are merely illustrative of the invention and that many variations may be devised by those skilled in the art without departing from the scope of the invention. For example, this invention has been described in connection with a specific circuit implementation. This invention is equally adaptable to be applied in the software area as an audit of circulating pointers.

Claims: A method for enforcing the validity of circulating pointers in a system having an addressable memory (114) and a set of circulating pointers corresponding to addresses of said addressable memory, said method CHARACTERISED BY the steps of: (a) establishing a target pointer (206) as a sole pointer to a selected location in said addressable memory (114); and (b) removing all pointers from the set of circulating pointers that point to said selected location in memory during a predetermined period of time. A method according to claim 1 wherein said step of establishing a target pointer is further CHARACTERISED BY : generating a plurality of target pointers (206) each corresponding to one of said selected locations in said addressable memory (114). A method according to claim 2 further CHARACTERISED IN THAT : the number of target pointers (206) in said plurality of target pointers is a function of the number of circulating pointers being used at a given time. A method according to claim 1 further CHARACTERISED BY the step of: determining whether one of said set of circulating pointers matches said target pointer (206) during a first portion of said predetermined time, and if none of said set of circulating pointers matches said target pointer (206) during said first portion of said predetermined time, reporting an error. A method according to claim 4 further CHARACTERISED BY the step of: after removing all pointers from said set of circulating pointers that point to said location in memory (114), adding said target pointer (206) to said set of circulating pointers. A method according to claim 1 further CHARACTERISED BY the step of: determining whether each of said set of circulating pointers matches said target pointer (206) during said predetermined period of time, and reporting an error if any of said set of circulating pointers match said target pointer during said predetermined period of time. A method according to claim 1 further CHARACTERISED BY the step of: after removing all pointers from said set of circulating pointers that point to said location in memory (114), adding said target pointer (206) to said set of circulating pointers. A method according to claim 1 further CHARACTERISED IN THAT : said steps are repeated for each location in memory (114). A method according to claim 1 further CHARACTERISED IN THAT : said set of circulating pointers each identifies a unique location in said addressable memory (114); step (a) thereof includes generating said target pointer (206) within a prespecified range of locations of said addressable memory (114); and said method further includes the steps of: responsive to determining that said target pointer (206) matches one of said set of circulating pointers during a first predetermined time, removing said one matching circulating pointer from said set of circulating pointers; responsive to determining that said target pointer (206) matches a further one or more of said set of circulating pointers during a second predetermined time, removing said further matching one or mare circulating pointers from said set of circulating pointers; and adding said target pointer (206) to said set of circulating pointers. A method according to claim 9 further CHARACTERISED IN THAT : said step of generating a target pointer (206) comprises generating a plurality of target pointers each comprising a unique one of said selected locations in said addressable memory (114). A method according to claim 9 further CHARACTERISED BY the step of: repeating said steps for each of said set of circulating pointers. A system for enforcing the validity of circulating pointers in a system having an addressable memory (114) and a set of circulating pointers each corresponding to a unique location in said addressable memory, said system CHARACTERISED BY : means (202) for generating a target pointer (206) within a prespecified range; means (208, 210, 212), responsive to determining that said target pointer matches one of said circulating pointers during a first predetermined time period, for removing said matching circulating pointer; means (208, 210, 212), responsive to determining that said target pointer matches a further one of said circulating pointers during a second predetermined time period, for removing said further matching circulating pointer; and means (213, 218, 214), responsive to expiration of said second time period, for adding said target pointer to said circulating pointers. A system according to claim 12 further CHARACTERISED BY : means (204) for storing said target pointer, said storage means comprising a content addressable random access memory (RAM) (206) and a comparator (208), said (208) comparator comparing said target pointer in said RAM to each of said circulating pointers. A system according to claim 13 further CHARACTERISED IN THAT : said means responsive to determining that said target pointer matches one of said circulating pointers during a first predetermined time period comprises combinational logic (224, 228) connected to said comparator (208) for blocking said matching circulating pointer responsive to receipt of a signal (222) from said comparator (208). A system according to claim 13 further CHARACTERISED IN THAT : said means responsive to determining that said target pointer matches a further one of said circulating pointers comprises combinational logic (224, 228) connected to said comparator (208) for blocking said matching circulating pointer responsive to receipt of a signal from (222) said comparator.

Inventors: MCHARG CHRISTOPHER GORDON, SCHAFF KENNETH NICHOLAS, MCHARG, CHRISTOPHER GORDON, SCHAFF, KENNETH NICHOLAS
Applicants: AT & T CORP, AT&T CORP.
Application year: 1993
Main classification: H04L12
IPC codes: H04L12, G06F13, H04Q11