Noise reduction device

Abstract: An input video signal is supplied to addition units 1, 2 and 3, an output of the addition unit 1 is supplied to the addition unit 2 via a delay unit 4 for according a delay z⁻¹. An output of the addition unit 2 is supplied via a coefficient multiplication unit 5 having an attenuation coefficient k₁ to the addition unit 1 and via a coefficient multiplication unit 6 having an attenuation coefficient k₂ to the addition unit 3 to carry out a noise reducing operation in accordance with a transfer function H(z) H(z) = {(1 - k₂) - (k₁ - k₂) z⁻¹}/(1 - k₁ z⁻¹) for diminishing the residual image and effectively reducing the noise component contained in the input video signal.

Description: This invention relates to a device for reducing the noise in picture signals and, more particularly, to a noise reduction device for reducing the noise in picture signals by taking advantage of field correlation or frame correlation. In video signal transmission or recording/reproducing apparatus, such as a TV receiver or a VTR, a noise reducing device for processing video signals with a noise reducing operation by taking advantage of the field correlation or frame correlation may be utilized for obtaining high-quality video signals. Such noise reducing device is provided with a memory having a storage capacity corresponding to a one-field or one-frame period. The difference between the input video signal and the video signal delayed by one field or by one frame from the input video signal is detected as noise. The detected output is multiplied by a noise-reducing coefficient and the resulting product is subtracted from the input video signal to produce a noise-reduced video signal. With such noise reducing device, since the step of the noise-reducing effect is compulsorily changed over from outside, only a fixed noise reducing effect may be achieved for changes in the image or picture, so that a noise-reducing effect cannot be adapted to the actual state of the picture or the residual image. On the other hand, if the noise reducing effect is enhanced, residual image tends to be left in the picture portions where changes in the motion are acute, so that a picture which is only hard to view can be produced. Conversely, if the residual image is inhibited, it becomes impossible to achieve the noise-reducing effect. Consequently, it is extremely difficult to set the characteristics of the noise reducing device so as to achieve the noise reducing effect in such a manner as to eliminate the residual image. US-A-4,926,361 discloses a number of different digital noise reducers. One of the circuits disclosed comprises first addition means, to a first input of which the input video signal is supplied; second addition means to a first input of which the input video signal is also supplied; third addition means to a first input of which the input video signal is supplied and which outputs a noise-reduced video signal: delay means for delaying an addition signal output by said first addition means by a predetermined delay amount, and for supplying a delayed output signal to a second input of said second addition means; first multiplication means for multiplying an addition signal output by said second addition means by a first attenuation coefficient k 1 , and for supplying the resulting signal to a second input of said first addition means; and second multiplication means for multiplying an addition signal output by said second addition means by a second attenuation coefficient k 2 , and for supplying a resulting signal to a second input of said third addition means. This circuit of US-A-4,926,361 also includes a so-called "correlation detection circuit" which detects when the addition signal output by the second addition means becomes equal to or larger than a certain value and in such a case reduces the first and second attenuation co-efficients. According to the present invention, there is provided a noise reducing device for reducing the noise contained in an input video signal, the device comprising: first addition means, to a first input of which the input video signal is supplied; second addition means to a first input of which the input video signal is also supplied; third addition means to a first input of which the input video signal is supplied and which outputs a noise-reduced video signal; delay means for delaying an addition signal output by said first addition means by a predetermined delay amount, and for supplying a delayed output signal to a second input of said second addition means; first multiplication means for multiplying an addition signal output by said second addition means by a first attenuation coefficient k 1 , and for supplying the resulting signal to a second input of said first addition means; and second multiplication means for multiplying an addition signal output by said second addition means by a second attenuation coefficient k 2 , and for supplying a resulting signal to a second input of said third addition means, characterised in that said noise reducing device further comprises: scene change detection means for detecting the rate of change in the scene of the picture represented by the input video signal based on the addition signal output by said second addition means; and control means for controlling at least one of the first attenuation coefficient k 1 and said second attenuation coefficient k 2 in response to the output of said scene change detection means which indicates the detected rate of change in the scene of the picture. In a noise reducing device according to the present invention, it is possible to minimise the residual image and to reduce the noise components contained in the input video signals, and it is possible for the noise-reducing effects to be achieved adaptively with respect to changes in the state of the picture. The delay may be a memory having a storage capacity corresponding to a one-frame period or a one-field period, whereby the second addition means may detect a one-field or one-frame difference of the input video signal. Preferably k 1 > k 2 . A preferred embodiment of the invention will now be described by way of non-limitative example with reference to the accompanying drawings, in which:- Fig. 1 is a block diagram showing the fundamental arrangement of a first embodiment of a noise reducing device according to the present invention. Fig. 2 is a block diagram showing a concrete arrangement of the noise reducing device according to the present invention. Fig. 3 is a block diagram showing an arrangement of a level detection circuit constituting a detection block of the noise reducing device shown in Fig. 2. Fig. 4 is a block diagram showing an arrangement of an edge detection circuit constituting a detection block of the noise reducing device shown in Fig. 2. Fig. 5 is a block circuit diagram showing an arrangement of an edge width adjustment circuit constituting the edge detection circuit shown in Fig. 4. Fig. 6 is a block circuit diagram showing another arrangement of an edge width adjustment circuit constituting the edge detection circuit shown in Fig. 4. Fig. 7 is a block circuit diagram showing an arrangement of a scene change detection circuit constituting a detection block of the noise reducing apparatus shown in Fig.2. Fig.8 is a partial front view of a screen for illustrating the operation of the scene change detection circuit shown in Fig.7. Fig.9 is a graph showing an operation of each pre-limiter circuit constituting IIR block of the noise reducing device in Fig.2. Fig.10 is a block circuit diagram showing the fundamental arrangement of a second embodiment of a noise reducing device according to the present invention. The fundamental arrangement of a first embodiment of the noise reducing device according to the present invention is shown in Fig.1, and includes first to third additive nodes 1 to 3, supplied with an input picture signal S IN , a delay unit 4 for delaying a sum output signal from additive node 1 by a predetermined delay z -1 and supplying a delayed output signal S DL to the second additive node 2, a first coefficient multiplication unit 5 for multiplying a sum output signal from the second additive node 2 by a first attenuation coefficient k 1 and supplying the resulting signal to the first additive node 1, and a second coefficient multiplication unit 6 for multiplying a sum output signal from the second additive node 2 by a second attenuation coefficient k 2 and supplying the resulting signal to the third additive node 3. In the present noise reducing apparatus, the delay unit 4 accords the delay z -1 corresponding to a field or a frame to a sum output signal from the first additive node 1. The second additive node 2 detects a difference between the input picture signal S IN and the delayed output signal S DL supplied from the delay unit 4. The first coefficient multiplication unit 5 multiplies a sum output signal from the second additive node 2, that is the detected noise component, with the first attenuation coefficient k 1 to transmit the resulting signal to first additive node 1. The first additive node 1 subtracts the noise component multiplied by the first attenuation coefficient k 1 by the first coefficient multiplication unit 5 for level controlled from the input video signal S IN to transmit the noise-reduced input video signal S IN to delaying unit 4. That is, the second additive node 2 detects the noise component by taking advantage of the field or frame correlation. Specifically, the second additive node 2 detects the difference between the delayed output signal S DL , which is equal to the input video signal S IN noise-reduced by the first additive node 1 and delayed by the delay amount z -1 corresponding to one frame or one field by the delay unit 4, and the input video signal S IN , as a noise component of the input video signal S IN . The second coefficient multiplication unit 6 multiplies a sum output signal of the second additive node 2, that is the detected noise component, by the second attenuation coefficient k 2 , to transmit the resulting signal to the third additive node 3. The third additive node 3 subtracts the noise component, level-controlled by being multiplied with the second attenuation coefficient k 2 by the second coefficient multiplication unit 6, from the input video signal S IN , to output an output video signal S OUT , which is a signal obtained by processing the input video signal S IN in accordance with a transfer function H(z) H(z) = {(1 - k 2 ) - (k 1 - k 2 ) z -1 }/(1 - k 1 z -1 ) With the above-described noise reducing apparatus, the first attenuation coefficient k 1 to be multiplied by the noise component detected by the second additive node 2 may be varied for adaptively changing characteristics of a processing system designed for detecting the noise component contained in the input video signal S IN . On the other hand, the second attenuation coefficient k 2 to be multiplied by the noise component detected by the second additive node 2 may be varied for adaptively changing characteristics of a processing system designed for reducing the noise component contained in the input video signal S IN . In this manner, the residual image may be diminished to enable a noise component contained in the input video signals S IN to be reduced effectively. The noise reducing device according to the second embodiment whose fundamental arrangement is shown in Fig.10 includes a scene change detection unit 7 supplied with the sum output signal from the second additive node 2, in addition to the features according to the first fundamental arrangement shown in Fig.1. In the instant noise reducing device, the delay unit 4 accords a delay z -1 , corresponding to one field or to one frame, to a sum output signal from the first additive node 1. The second additive node 2 detects the difference between the input video signal S IN and the delayed output signal S DL , supplied from the delay unit 4, as a noise component. The scene change detection unit 7 detects the rate of changes in the scene of the picture represented by the input video signals based on the sum output of the second additive node 2. The scene change detection unit 7 controls the first attenuation coefficient k 1 of the first coefficient multiplication unit 5 and the second attenuation coefficient k 2 of the second coefficient multiplication unit 6 in accordance with the rate of changes in the scene to diminish the first and second coefficients k 1 , k 2 for scenes presenting acute changes. By detecting the rate of changes in the scene by the scene change detection unit 7 based on the noise component detected by the second additive node 2 for controlling the first and second attenuation coefficients k 1 , k 2 of the first and second coefficient multiplication units 5, 6 to be smaller, it becomes possible to diminish the residual image and to reduce the noise component contained in the input video signal S IN effectively. Referring to Figs.2 to 9, more concrete embodiments of the noise reducing apparatus according to the present invention are explained in detail. The noise reducing device shown in Fig.2 is a large-scale integrated circuit arranged in one chip and is made up of a BUF block 11, a DET block 12, a CNT block 13, an IIR block 14, a MEM block 15, a GAI block 16, a TOU block 17, an OBF block 18 and a SEP block 19. The chip is designed to be operated by itself as a signal- adaptive type noise reducing unit or a 1-frame delay unit. The BUF block 11 is a block for processing the input video signals S IN with conversion, such as data rate conversion, and is adapted for delaying address control signals or real-time control signals in association with delay of the video signals caused by a decimator. Output video signals from the BUF block 11 are supplied to the above-mentioned DET block 12, IIR block 14 and TOU block 17. The address control signals are supplied to the DET block 12, MEM block 15 and to OBF block 18. The real-time control signals are supplied to the CNT block 13. The DET block 12, which is a block for processing the input video signals S IN , supplied via BUF block 11, with various detecting operations, such as level detection, edge detection or scene change detection, is made up of a level detection unit 21, an edge detection unit 22 and a scene detection unit 23. Output detection signals of these detection units are transmitted to CNT block 13. The level detection circuit 21 is made up of a limiting circuit 31, a detection point selector 32 and an absolute value conversion circuit 33, as shown for example in Fig.3. The limiting circuit 31 processes the input video signal S IN , supplied thereto via BUF block 11, with a limiting operation conforming to level detection points. If the 8-bit input signal S IN , having its MSR as a sign bit, is represented by I(8:1), and level detection points are set at 4 bits of I(6:3), then I(6:3) of the input video signal I(8:1) is directly outputted should I8(MSB), I7 and I6 remain the same. However, should may of I8, I7 and I6 be different, then I(6:3) = 0111 or I(6:3) = 1000 is outputted, depending on I8(MSB), that is on the sign. This output of the limiting circuit is supplied to detection point selector 32. The detection point selector 32 is made up of detection point circuits 32A, 32B, where the level detection points, such as I(6:3) or I(7:4), are set, and a selector 32C for selecting an output of one of them as a level detection output. The level detection output, as selected by selector 32C, is supplied to the absolute value conversion circuit 33. The absolute value conversion circuit is so constructed that the level detection output of the detection point selector is supplied to a selector 33B directly or via an inverter 33A. The selector 33B of the absolute value conversion circuit 33 performs a selecting operation in accordance with the sign bit (MSB) of the input video signal S IN to output an absolute value level detection signal. For edge detection of chrominance signals, the edge detection circuit 22 is constructed as shown for example in Fig.4. The edge detection circuit 22 delays the input video signals S IN , supplied via BUF block 11 by two clocks by delay units 41, 43, with inversion by an inverter 42, and causes the inverted and delayed signals to be mixed with the input video signal at an additive node 44 by way of edge detection. It is noted that the input video signal is delayed by one clock, instead of by two clocks, for detecting luminance signals. Since overflow may be incurred, the edge detection circuit 22 shown in Fig.4 is so arranged that the addition output from additive node 44, that is an edge detection output, is passed through an overflow limiter 45 and thence through a detection point selector 46, similar to that provided in the level detection circuit 21, before being converted by an absolute value converter 37 into an absolute value and outputted via an edge width adjustment circuit 48. The edge width adjustment circuit 48 compares an input signal with a signal which is the input signal delayed by two clocks by a delay circuit 48A, and outputs a larger one of the two signals, as selected by a selector 38B, for according a width to the edge, as shown for example in Fig.5. It is noted that the input signal is delayed by one clock, instead of by two clocks, for detecting luminance signals. The edge width adjustment circuit 48 may be arranged as a low-pass filter adapted for adding the input signal to a signal, as produced by delaying the input signal by two clocks by a delay unit 48C, by an additive node 48D, and outputting the resulting sum signal, as shown in Fig.6. The scene change detection circuit 23, equivalent to the scene change detection unit 7 in the noise reducing device shown in Fig.10, is arranged as shown for example in Fig.7. The scene change detection circuit 23 includes an absolute value conversion circuit 51 supplied from IIR block 14 with differential data indicating the difference between the input video signal and signal preceding the input video signal by one field or by one frame. The absolute value conversion circuit 51 converts the difference data into absolute value data which is supplied via limiting circuit 52 to a level comparator 53. The level comparator outputs a logical H signal via AND gate 54 to a counter 55 when the data of the absolute difference value difference from limiting circuit 52 is larger than a predetermined value. The scene change detection circuit 23 also includes an H, V and CK counter 56 for deciding effective data of the difference information. The H, V and CK counter 56 controls the AND gate 54 so that data at points at intervals of 16 clocks (CK) at intervals of 16 lines (H) are accepted as effective data for each field (V), as indicated by ▪ in Fig.8. The counter 55 counts the number of effective data for which the output of the comparator 53 via AND circuit 54, that is the absolute difference value from the limiting circuit 52, exceeds the predetermined value. The count value of the counter 55 indicates the rate of change of the scene produced by the input video signals S IN . The CNT block 13 is a block for controlling the operation of the IIR block 14 and the GAI block 16. The CNT block evaluates various detection outputs of the DET block comprehensively to transmit an optimized control signal to IIR block 14 and to GAI block 16. If real-time control signals are applied to the CNT block from outside via BUF block 11, a control operation responsive to the real-time control signal is carried out preferentially. The IIR block 14 is a block for taking the difference between the input video signal S IN supplied thereto via BUF block 11 and the video signal S DL delayed by one frame by the MEM block 15 to extract noise components. An extracted output, that is noise components, is supplied to DET block 12 and to GAI block 16. The IIR block 14 is made up of a first additive node 61 supplied with the input video signal S IN from BUF block 11 and the video signal S DL from MEM block 15, first and second pre- limiters 62, 63 supplied with sum outputs of the first additive node 61, a coefficient ROM 64 supplied with an output of the first pre-limiter 62, and a second additive node 66 supplied with an output of coefficient ROM 64 via attenuator 65 and with the input video signal S IN from BUF block 11. The first additive node 61 is equivalent to the second additive node 2 of the fundamental arrangement of the noise reducing device shown in Fig.1, and transmits an addition output indicating the difference between the input video signals S IN supplied via BUF block 11 and the video signal S DL read out from MEM block 15 after delay by one frame to scene change detection circuit 23 of DET block 12 and to first and second pre-limiters 62, 63. The first pre-limiter 62 performs a motion detection based on the assumption that a signal level of the addition output of the first additive node 61 not lower than a predetermined limiting level L 1 is ascribable to motion, and extracts a signal component lower than the limiter level L 1 as a noise component which is supplied to coefficient ROM 63, as shown by a solid line in Fig.9. The second pre-limiter 63 performs motion detection based on an assumption that a signal level of the addition output of the first additive node 61 higher than a predetermined limiting level L 2 is ascribable to motion, and extracts a signal component lower than the limiter level L 1 as a noise component which is supplied to GAI block 16, as shown by a broken line in Fig.9. The limiting levels L 1 , L 2 of the first and second pre- limiters 62, 63 are set so that L 1 < L 2 . The coefficient ROM 64 converts the noise level in accordance with predetermined conversion characteristics and is so designed as to read out level data, which are stored noise level data multiplied by coefficients, using data supplied from first adder 61 via first pre-limiter 62 as read-out addresses. The noise level data thus read out from coefficient ROM 64 is supplied via attenuator 65 to the second additive node 66. The attenuator 65 accords a predetermined amount of attenuation to the noise level data read out from coefficient ROM 64 by bit shifting. The coefficient ROM 64 and the attenuator 65 are equivalent to the first coefficient multiplication unit 5 in the first fundamental arrangement of the noise reducing device shown in Fig.1. The second additive node 66 is equivalent to the first additive node 1 in the first fundamental arrangement of the noise reducing device shown in Fig.1 and subtracts the noise level data supplied from coefficient ROM 64 via attenuator 65 from the input video signals supplied via BUF block 11 to produce a subtraction signal which is supplied to MEM block 15. The subtraction signal is the noise-reduced video signal. In the embodiment illustrated, three different level data with different conversion characteristics are previously recorded in coefficient ROM 64. The conversion characteristics of the coefficient ROM 64 and the amount of attenuation by attenuator 65 are controlled by an IIR control signal from the IIR block 13. In this manner, the characteristics of the IIR block 14 are finely adjusted at steps of 0.25 for assuring effective utilization of lower order bits. The MEM block 15 is equivalent to the delay means 4 in the fundamental arrangement of the noise reducing device shown in Fig.1. It is composed of a frame memory having a storage capacity for one frame for storing video signals supplied from the second additive node 66 of the IIR block 14 for supplying video signals delayed by one frame to the first additive node 61 of the IIR block 14 and to the TOU block 17. The GAI block 16 is equivalent to the second coefficient multiplication unit 6 in the fundamental arrangement of the noise reducing device shown in Fig.1, and is adapted for supplying the noise component extracted by the IIR block 14 after changing its gain. Similarly to the IIR block 14, it is made up essentially of a coefficient ROM 71 and an attenuator 72 for attenuation by bit shifting. The amount of attenuation by the attenuator 72 is variably controlled at steps of 1/8 by gain controlling signals from CNT block 13. The TOU block 17 performs an operation of reducing the noise in the input video signal supplied thereto via BUF block 11, and is composed essentially of an additive node 81 and a changeover switch 82. The additive node 81 of the TOU block 17 is equivalent to the second additive node 3 in the fundamental arrangement of the noise reducing device shown in Fig.1, and is adapted for subtractively synthesizing the noise component, gain-adjusted by GAI block 16, to the input video signals supplied via BUF block 11, for generating noise-reduced video signals. During the noise-reducing mode operation, noise-reduced video signals from the additive node 81 are outputted via changeover switch 82. During the delaying mode, the video signals delayed by one frame are read out from MEM block 15 so as to be outputted via changeover switch 82. The OBF block 18 is a block for processing the video signals supplied from TOU block 17 by e.g. data rate conversion, and is adapted for delaying address control signals, real time control signals etc. in association with delaying of the video signals by the interpolation filter, for outputting the delayed signals. The SEP block 19 converts serial data from a microcomputer, not shown, into parallel data for controlling the operation of various components. In the above-described noise reducing device, the CNT block 13 is responsive to the various detection outputs of the DET block 12 to control the IIR block 14 and the GAI block 16 in the following manner. That is, if the edge level indicated by the edge detection output from the edge detection circuit 22 is low, CNT block 13 gives a decision that the picture portion is a part of a larger scene to increase the coefficient k 1 of the IIR block 14 and the coefficient k 2 of the GAI block 16 for applying a more intensive noise reduction. By reflecting the edge detection output on the noise-reducing operation, the noise reducing operation may be intensified in a picture portion which is a part of a larger scene where the noise is outstanding for rendering the noise less perceptible. On the other hand, since the moving parts of the still picture may be grasped by such edge detection, the noise reducing operation for the moving parts may be weakened to reduce the residual image to maintain the overall noise reducing effect. The CNT block 13 is responsive to the signal level indicated by the level detection output by the level detection circuit 21 to control the coefficient k 1 of the IIR block 14 and the coefficient k 2 of the GAI block 16. Since the noise becomes more outstanding if the luminance signal is at a lower level, the coefficient k 1 of the IIR block 14 and the coefficient k 2 of the GAI block 16 may be enlarged in case of the lower level of the luminance signal to render the noise less outstanding. On the other hand, since the noise becomes more outstanding if the chrominance signal is at a higher level, the coefficient k 1 of the IIR block 14 and the coefficient k 2 of the GAI block 16 may be enhanced in case of the higher level of the luminance signal to render the noise less outstanding. A control operation by the CNT block 13 is performed as that the lesser the rate of change in the video scene indicated by the detection output of the scene change detection circuit 23, the more is the increase in the coefficient k 1 of the IIR block 14 and the coefficient k 2 of the GAI block 16. By changing the noise reducing effect responsive to the rate of change of the video scene, it becomes possible to diminish the residual image and to increase the noise reducing effect. On the other hand, the loop coefficient k 1 of the IIR block 16 is minimized in case of a complete scene change to diminish the residual image. In the noise reducing device of the present invention, output image signals are derived from the input video signals by processing the input video signals with a noise reducing operation in accordance with a transfer function H(z) H(z) = {(1 - k 2 ) - (k 1 - k 2 ) z -1 }/(1 - k 1 z -1 ) so that, by varying the first attenuation coefficient k 1 to be multiplied by the noise component detected by the second additive node, the characteristics of the processing system for detecting the noise component contained in the input video signals may be controlled adaptively and variably. Besides, by varying the second attenuation coefficient k 2 to be multiplied by the noise component detected by the second additive node, the characteristics of the processing system for reducing the noise component contained in the input video signals may be controlled adaptively and variably. In this manner, the residual image may be diminished to realize effective reduction of the noise components contained in the input video signals. On the other hand, with the noise reducing device of the present invention, a memory having a storage capacity corresponding to a one-frame period or a one-field period is employed as delay means and a one-field difference or a one-frame difference of input video signals is detected by the second additive node. The one-field difference or the one-frame difference thus produced is multiplied with the first attenuation coefficient k 1 or the second attenuation coefficient k 2 by first and second coefficient multiplication units, respectively, where k 1 > k 2 , by way of a noise reducing operation by taking advantage of field correlation or the frame correlation for reducing the residual image and effectively reducing the noise components contained in the input image signals. Besides, by detecting the motion of the picture represented by the input video signals by motion detection means and adaptively controlling the first and second attenuation coefficients k 1 , k 2 of the first and second coefficient multiplication units, it becomes possible to reduce residual image and to reduce the noise component contained in the input video signals effectively.

Claims: A noise reducing device for reducing the noise contained in an input video signal, the device comprising: first addition means (66), to a first input of which the input video signal is supplied; second addition means (61) to a first input of which the input video signal is also supplied; third addition means (81) to a first input of which the input video signal is supplied and which outputs a noise-reduced video signal; delay means (15) for delaying an addition signal output by said first addition means by a predetermined delay amount, and for supplying a delayed output signal to a second input of said second addition means; first multiplication means (64,65) for multiplying an addition signal output by said second addition means by a first attenuation coefficient k 1 , and for supplying the resulting signal to a second input of said first addition means; and second multiplication means (71,72) for multiplying an addition signal output by said second addition means by a second attenuation coefficient k 2 , and for supplying a resulting signal to a second input of said third addition means, characterised in that said noise reducing device further comprises: scene change detection means (23) for detecting the rate of change in the scene of the picture represented by the input video signal based on the addition signal output by said second addition means; and control means for controlling at least one of the first attenuation coefficient k 1 and said second attenuation coefficient k 2 in response to the output of said scene change detection means which indicates the detected rate of change in the scene of the picture. A noise reducing device as claimed in claim 1, wherein said predetermined delay amount is a one-frame period or a one-field period, whereby said second addition means (61) detects a one-frame or one-field difference of said input video signal. A noise reducing device as claimed in claim 2, wherein the relation between said first attenuation coefficient k 1 and said second attenuation coefficient k 2 is defined by the formula k 1 > k 2 . A noise reducing device as claimed in any one of the preceding claims, wherein said scene change detection means (23) comprises: comparator means (51,52,53) for comparing whether the absolute value of the addition signal output by said second addition means exceeds a predetermined level; and means (54,55) for counting the number of times that the output of the comparator means indicates that said predetermined level is exceeded at predetermined points of said picture whereby the output of said means for counting indicates the rate of change in the scene. A noise reducing device as claimed in any one of the preceding claims, further comprising edge detection means (22) for detecting an edge of the input video signal, and wherein said control means (13) are also for controlling at least one of the first attenuation coefficient k 1 and said second attenuation coefficient k 2 in response to the output of said edge detection means which indicates the detected edge level. The noise reducing device as claimed in any one of the preceding claims, further comprising level detection means (21) for detecting the level of the input video signal, and wherein said control means are also for controlling at least one of the first attenuation coefficient k 1 and said second attenuation coefficient k 2 responsive to the output of said level detection means which indicates the detected level. A noise reducing device as claimed in any one of the preceding claims, further comprising a limiter (62) for limiting the addition signal output from the second addition means before it is supplied to said first multiplication means. A noise reducing device as claimed in any one of the preceding claims, further comprising a limiter (63) for limiting the addition signal output from the second addition means before it is supplied to said second multiplication means. A noise reducing device as claimed in any one of the preceding claims, further comprising a change-over switch (82) for switchably connecting one of a first input and a second input to an output, said noise-reduced video signal output by said third addition means (81) being supplied to the first input of said change-over switch and said delayed signal output by said delay means (64,65) being supplied to the second input of said change-over switch.

Inventors: NOJIMA SATOSHI, SENUMA TOSHITAKA, NOJIMA, SATOSHI, SENUMA, TOSHITAKA, NOJIMA, SATOSHI, SONY CORPORTION, SENUMA, TOSHITAKA, SONY CORPORTION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H04N5
IPC codes: H04N5