Line interface for high-speed transmission line

Abstract: A line interface incorporated in a hgh-speed transmission line system for transmitting and receiving one time slot of the transmission line. A speed changing circuit replaces a high-speed transmission line with n low-speed internal lines. Hence, data transmitting and receiving circuits in each internal unit operate at low speed, saving power to be consumed by the internal unit. Since the time slots which each internal unit uses are the same on all of the internal lines, a single time slot selecting circuit suffices for each internal unit, promoting efficient circuit configuration.

Description: The present invention relates to a hight-speed transmission line system and, more particularly, to a line interface for a high-speed transmission line system. It is a common practice to provide a high-speed transmission line system with a line interface connected to a high-speed transmission line. The line interface is made up of an interface circuit for effecting AMI/TTL or similar conversion, and a line state sensing circuit. Usually, a signal format on the high-speed transmission line has one period implemented as n time slots TS1-TSn and is maintained even after the high-speed line has been converted to internal lines by the line interface. Internal units incorporated in the transmission line system each transmits and receives data in one of the time slots TS on the internal lines. Hence, the time slot to be received by each of the internal units is determined on the basis of the location, internal arrangement and so forth of the unit. Each internal unit has n blocks for transmitting and receiving data in the time slots on the internal lines. Connected to the internal lines, the blocks each has a time slot selecting circuit for selecting a time slot, a data transmitting and receiving circuit for transmitting and reeiving data in the time slot selected, and a logic circuit. Further, each block reports the time slot selected by the time slot selecting circuit to the data transmitting and receiving circuit which in turn reports such data to the logic circuit. However, the conventional high-speed transmission line system, particularly a system having a plurality of time slot transmitting and receiving blocks in each internal unit, has some problems left unsolved. Namely, n identical time slot selecting circuits are built in each unit, resulting in wasteful circuit arrangement. Since the data transmitting and receiving circuits are connected to the internal lines and built in each internal unit, the individual unit consumes great current to thereby aggravate the current consumption of the entire system. EP-A-0 254 878 discloses a packet data communication system with a ring type transmission line and which saves power by speed reduction implemented by splitting a high-speed line to a number of low-speed lines. It is, therefore, an object of the present invention to provide a line interface for a high-speed transmission line system which simplifies internal units and saves current to be consumed by individual internal unit. This object is achieved with the features of the claims. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which: FIG. 1 is a block diagram schematically showing a conventional high-speed transmission line system; FIG. 2 shows a signal format particular to the conventional high-speed transmission line system; FIG. 3 is a schematic block diagram showing an internal unit included in the conventional system; FIG. 4 is a block diagram schematically showing a high-speed transmission line system embodying th present invention; FIG. 5 shows a signal format vailable with the embodiment and in which time slots are changed; FIG. 6 shows a signal format in which line numbers are changed; FIG. 7 shows a specific construction of a line interface included in the embodiment; FIGS. 8 and 9 are timing charts demonstrating the operation of the embodiment; FIG. 10 shows another specific construction of the line interface of the embodiment; and FIG. 11 is a flowchart representative of the operation of the line interface shown in FIG. 10. To better understand the present invention, a brief reference will be made to a conventional line interface for a high-speed transmission line system, shown in FIG. 1. As shown, the system includes a line interface 22 connected to a high-speed transmission line 21. The line interface 22 is made up of an interface circuit 23 and a line state sensing circuit 24. The interface circuit 23 effects AMI/TTL similar conventional conversion. FIG. 2 shows a signal format particular to the high-speed transmission line 21 and having n time slots TS1 to TSn in one period thereof. The signal format does not change even after the high-speed line 21 has been converted to an internal line 27 by the line interface 22. Units 25-1 to 25-n are incorporated in the system, and each transmits and receives data by using a particular time slot over the internal line. Specifically, a particular time slot is assigned to each of the units 25-1 to 25-n depending on the location, internal arrangement and so forth of the unit. As shown in FIG. 3, the units 25-1 to 25-n (represented by the unit 25-1) have each n blocks for transmitting and receiving data over the intenal line 27. The n blocks have respectively time slot selecting circuits 32-1 to 32-n, data transmitting and receiving circuits 31-1 to 31-n for transmitting and receiving data in the time slot selected, and logic circuits 33-1 to 33-n. These n blocks are commonly connected to the internal line 27. Each of the blocks 1- n reports the time slot selected by associated one of the time slot selecting circuits 32-1 to 32-n to associated one of the data tansmitting and receiving circuits 31-1 to 31-n. Then, the data transmitting and receiving circuit of interest transfers only such data to associated one of the logic circuits 33-1 to 33-n. As stated above, in the conventional system, n idetntical time slot selecting circuits 32-1 to 32-n are wastefully built in each of the units 25-1 to 25-n. Moreover, since the data transmitting and receiving circuits connected to the internal line 27 are incorporated in all of the units 25-1 to 25-n, each unit consumes great current. This aggravates the current consumption of the entire system incorporting a great number of such units. Refering to FIG. 4, a high-speed transmission line system embodying the present invention is shown. The embodiment will be described with reference also be made to FIGS. 5 and 6. As shown in FIG. 4, the system embodying the present invention has a line interface 2 connected to a high-speed transmission line 1. The line interface 2 is made up of an interface circuit 3 for, for example, AMI/TTL conversion, a line state sensing circuit 4, a time slot changing circuit 5, a line number changing circuit 6, and a line speed changing circuit 7. The line interface 2 is connected to internal units 8-1 to 8-m by internal lines 91- to 9-n. The high-speed transmission line 1 is converted to an internal level by the interface circuit 3 and then applied to the time slot changing circuit 5. In the embodiment, assume that the internal units 8-1 to 8-m each include m blocks for transmitting and receiving n time slots, i.e., m data transmitting and receiving circuits. Therefore, at least n x m time slots exist on the transmission line 1. As shown in FIG. 5, the time slot changing circuit 5 changes (replaces) the order of time slots depending on which time slot on the transmission line 1 is occupied by which of the internal units 8-1 to 8-m. The time slot changing circuit 5 transfers the high-speed line whose time slots have been changed in matching relation to the units 8-1 to 8-m. As shown in FIG. 6, the line number changing circuit 6 changes the high-speed line to n lines on a period basis. Specifically, as shwon in FIG. 5, the lines are changed such that the same time slots are assigned to each of n internal lines 9-1 to 9-n, e.g., time slots TS1-1 to TS1-n are assigned to the internal unit 8-1. On receiving the n lines from the line number changing circuit 6, the line speed changing circuit 7 converts the high speed to a low speed and delivers it to the internal lines 9-1 to 9-n. Since the units 8-1 to 8-m are respectively connected to the internal lines 9-1 to 9-n, the time slots to be used by each of the units 8-1 to 8-m are the same on the internal lines. Therefore, it is not necessary to incorporate the same number of time slot selecting circuits as data transmitting and receiving circuits, i.e., a single time slot selecting circuit has only to be built in each of the units 8-1 to 8-m. When data are sent from the units 8-1 to 8-m to the high-speed transmission line 1, the n internal lines 9-1 to 9-n are inputted to the line speed changing circuit 7 to have their speed changed to the high speed. The line number changing circuit 6 converges the lines 9-1 to 9-n to a single line. Subsequently, the time slot changing circuit 5 changes the time slots to ones matching the transmission line 1 and delivers the resulting time slots to the interface circuit 3. In response, the interface circuit 3 converges the level of the time slots and then feeds them out to the transmission line 1. Referring to FIGS. 7, 8 and 9, a specific construction of the line interface 2, FIG. 4, will be described. As shown, the high-speed transmission line 1 and the low-speed internal lines 9 are assumed to have frequencies N1 and N2 (MHz), respectively. The line interface 2 accommodates m internal lines 9-1 to 9-M. There are shown in FIG. 7 a local phase synchronizing circuit 50, elastic memories 51-1 to 51-M and 52-1 to 52-M, an RR1 generating circuit 53 for generating a read reset signal RR1, an RR2 generating circuit 54 for generating a read reset signal RR2, an RR3 generating circuit 55 for generating a read reset signal RR3, a WR1 generating circuit 56 for generating a write reset signal WR1, a WR2 generating circuit 57 for generating a write reset signal WR2, a WR3 generating circuit 58 for generating a write reset signal WR3, a WI1 generating circuit 59 for generating a write inhibit signal WR1, an RI generating circuit 60 for generating signals RI3-1 to RI3-M, a selector 61, and a control signal generating circuit 62. In operation, in the event of reception, a signal from the high-speed transmission line 1 is applied to the local phase synchronizing circuit 50 as data having the frequency N1. The local phase synchronization is customary with an ordinary transmission line interface and implemented with a local clock in place of a remote clock which suffers from, for example, jitter. As shown in FIG. 8, the data resulting from the local is stable at the negative-going edges of a basic period signal. The beginning of the data output is indicated by the read reset signal RR1. The elastic memories 51-1 to 51-M change the time slots, line number, and speed. Specifically, the write reset signals WR initialize the input addresses to the elastic memories 51-1 to 51-M while the write inhibit signal WI generates an input permission timing. The output timing is indicated by the read reset signal RR2 and is synchronous with a low-speed line clock CLK (N2 MHz). At the time of transmission, the low-speed internal lines 9-1 to 9-M are synchronous with the basic synchronizing signal, as shown in FIG. 9. The write reset signal WR3 initializes the write addresses of the elastic memories 52-1 to 52-M to thereby write one period of data. The data are read out of the elastic memories 52-1 to 52-M in synchronism with the clock (N1) of the high-speed line 1 in response to the read timing generated by the RI generating circuit 60 and meant for each memory. As shown in FIG. 9, this timing differs from one memory to another. As a result, speed and line number are changed. After the low speed to high speed conversion, a control signal meant for the high-speed line 1 (e.g. framing signal) is inserted in the data and then sent out to the line 1 via the interface circuit 3. FIG. 10 shows another specific construction of the interface 2 while FIG. 11 demonstrates a specific operation thereof. The construction of FIG. 10 differs from that of FIG. 7 in that it implements the conversion of the time slots with software. There are shown in FIG. 10 a first serial IN/parallel OUT memory 61, a second serial IN/parallel OUT memory 62, a CPU (Central Processing Unit) 63, selectors 64-1 to 64-M, a switchover controller 65, and a pattern setting circuit 66. In operation, data on the high-speed transmission line 1 are serially and alternately applied to the first and second serial IN/parallel OUT memories 61 and 62 every basic period (one frame). When one frame of data is accumulated, a signal BUFFER FULL is outputted from the system of interest. The CPU 63 reads the data out of the full serial IN/parallel OUT memory 61 or 62 one byte at a time and writes them in a predetermined address (time slot, phase, etc.) of one of the lines 9-1 to 9-M set by the pattern setting circuit 66 and indicating "buffer empty". After data have been written in all the addresses (time slots), the CPU 63 permits transmission and sends the data in synchronism with the low-speed line clock CLK (N2) and at the timing for switching over the selectors 64-1 to 64-M. In the next period, data having been written in the opposite system are sent. At this instant, the low speed to high speed conversion is also effected in the opposite sequence. In summary, it will be seen that the present invention provides a line interface having a speed changing circuit which replaces a high-speed transmission line with n low speed internal lines. Hence, data transmitting and receiving circuits in each internal unit operate at low speed, saving power to be consumed by the internal unit. Moreover, since the time slots which each internal unit uses are the same on all of the internal lines, a single time slot selecting circuit suffices for each internal unit, promoting efficient circuit configuration. Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims: A high-speed transmission line system connected to a high-speed transmission line (1) for transmitting and receiving one time slot of said high-speed transmission line , said system comprising: m units (8-1 to 8-m) each being made up of n blocks for transmitting and receiving data; and n low-speed lines (9-1 to 9-n) connected to said m units; characterized by: line interface means (2) for converting time slots of a signal received over the high-speed transmission line (1) to said n low-speed lines (9) and reconstructing said n low-speed lines (9) into a single high-speed line and connecting said single high-speed line to said high-speed transmission line, and wherein the m units are arranged such that the n blocks of each of said m units select same time slots of said n low-speed lines. A system as claimed in claim 1, wherein said line interface means comprises: a time slot changing means (5) for changing time slots from the high-speed transmission line (1) to a predetermined order matching said units, and rearranging time slots changed in a predetermined order to recover time slots for the high-speed transmission line (1); line number changing means (6) connected to said time slot changing means (5) for dividing the changed time slots into n further high-speed lines in matching relation to said low-speed lines, and combining said n further high-speed lines to recover the time slots changed to said predetermined order; and line speed changing means (7) connected to said line number changing means (6) for changing the n further high-speed lines to the n low-speed lines, and combining the n low-speed lines to recover the n further high-speed lines.

Inventors: SHIMIZU TOSHIMITSU, SHIMIZU, TOSHIMITSU, Shimizu, Toshimitsu, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: G06F13
IPC codes: H04J3, H04L25, H04L29, H04Q11, G06F13