Non-volatile electrically programmable semiconductor memory device comprising a voltage regulator

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

Description: Field of the invention The present invention relates to an electrically programmable non-volatile semiconductor memory device comprising a voltage regulator. More specifically the present invention relates to a voltage regulator of the type comprising a gain stage supplied by a programming voltage and having an input terminal connected to a divider of said programming voltage and an output terminal connected to a programming line of at least one memory cell. As known an individual non-volatile memory cell comprises an MOS transistor in which the gate electrode located over the channel region is floating, i.e. displays high continuous impedance to all the other terminals of the same cell and of the circuit in which the cell is inserted. The cell also includes a second electrode, called control gate, which is piloted through appropriate command voltages. The other electrodes of the transistor are the usual drain, source and body terminals. By applying appropriate voltages to the cell terminals it is possible to change the charge quantity present in the floating gate, e.g. utilising known Fowler-Nordheim Tunnelling and/or Channel Hot Electron Injection phenomena. This allows placing the transistor in two logic stages: a first state with "high" threshold voltage and a second state with "low" threshold voltage. If at the control gate is applied a voltage intermediate between these two values it is possible to "read" the state of the transistor since it displays between the drain and source terminals a low or high impedance depending on the threshold voltage value. Therefore said transistor can be considered a logic memory element. Since the floating gate presents a high impedance toward any other cell terminal, the charge stored therein can persist for an indeterminate time even if supply is removed from the circuit in which it is inserted. The cell therefore displays non-volatile memory characteristics. The operation by which the charge is stored in the floating gate is termed "programming" while the operation by which the charge is removed from the floating gate is termed "erasure". Generally a non-volatile memory circuit integrated on a semiconductor comprises a multiplicity of cells of the above type organised in lines called 'word lines', and columns called 'bit lines'. The cells belonging to the same word line have in common the electric line which pilots the respective control gates while the cells belonging to the same bit line have in common the drain terminals. It is also known that non-volatile memory cells and in particular the FLASH type require accurate control of drain voltage Vd during the programming phase, i.e. the voltage applied on the bit line. Said drain voltage must indeed satisfy divers conditions listed below: It must be high enough to allow fast cell programming, it must be at the same time low enough to avoid the so-called 'soft-erasing' phenomenon, which consists of partial erasure of the cell or degradation of the characteristics of the cell with use, and for reliability reasons it must always be such as to avoid setting off the phenomenon known as 'bipolar-parasite'. The optimal range for such a voltage is in general rather small and typically between 5 and 6 volts. It is noted also that the conditions indicated above are variable depending on the production process and in particular depending on the length of the memory cell. The production processes indeed lead to variations in the dimensions of the cells and in particular of the polysilicon layers and this represents one of the critical parameters in production. Taken all together the above observations lead to the conclusion that it is necessary to equip the memory circuit with a particularly refined and accurate voltage regulator to supply the correct voltage to the bit line in the programming phase. The known art already proposes some solutions to meet this requirement. In general since the voltages supplied from the outside to the memory circuit are substantially two and in particular a 5V supply voltage vcc and a 12V programming voltage Vpp, control of drain voltage is normally achieved by division of the programming voltage Vpp. In this manner there is achieved a drain voltage relatively stable as concerns temperature and the circuit production process parameters and variable by ± 5 % with the programming voltage Vpp. Prior art In the annexed FIG. 1 is shown diagramatically a first circuit solution of known type provided by utilising division of the programming voltage. The voltage regulator shown in FIG. 1 comprises a resistive divider consisting of three resistances R1, R2, R3 connected between the programming voltage line Vpp and ground. In parallel with said resistances is a group of four MOS transistors connected in series with each other through their respective source and drain terminals. The gate terminals of the first transistor M1 and fourth transistor M4 are connected between the first and second resistances and between the second and third resistances. The voltage applied to the bit line is taken on the gate terminal of the second transistor M2 which is inserted in the circuit in diode configuration with gate and drain short-circuited. Said voltage is actually applied to the bit line unless there is a negative translation of level due to the presence of a first selection transistor M6 and a second selection transistor M7 for writing. Although advantageous from certain viewpoints, this solution is not entirely effective and displays some shortcomings. As already mentioned, the programming current absorbed by the memory cell can vary from one integrated circuit to another because of the inevitable variations inherent in the production process. It can undergo variations also because of the surrounding conditions in which the circuit is made to operate. If the current passing through the bit line and hence the output stage of the regulator is actually different from the one called for by the design it follows that the voltage on the bit line will also be wrong or different from that desired. In addition, since during programming the threshold voltage of the cell tends to rise progressively it follows that the current absorbed by the cell decreases in time. Since with the circuit described above voltage regulation is based on an average programming current, it will not give good results steadily. A second solution of the known art is shown in FIG. 2 and provides that the drain voltage be supplied by a so-called source-follower piloted by an appropriately fedback operational amplifier. Even this solution is not free of shortcomings. In particular, this circuit proved to be slow in the reading phase because it seems to increase the capacitance of the bit line. In addition, it has been observed that with the decrease in the cell dimensions and in particular their actual length, ever closer limits are imposed on drain voltage variation range and this compromises the reliability and performance of the entire memory circuit. A voltage regulator for a transistor, comprising impedance means to set up the output voltage level with high accuracy, is disclosed in the European Patent Application No. EP-A-0 145 254 in the name of FUJITZU Limited. The technical problem underlying the present invention is to conceive a voltage regulator which would supply the bit line constantly at the output with a voltage such as to pursue optimally production process variations. In other terms, the purpose of the present invention is to conceive a voltage regulator capable of adapting to the actual length of the memory cell and overcoming the limits of the present solutions. Summary of the invention The solution idea underlying the present invention is to incorporate in the regulator a resistive network on which the voltage drop would be a function of the actual length of the memory cell. On the basis of this solution idea the technical problem is solved by a voltage regulator of the type set forth above and defined in the characterising part of claim 1. The characteristics and advantages of the voltage regulation circuit in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of nonlimiting example with reference to the annexed drawings. Brief description of the drawings In the drawings: FIG. 1 shows a diagram of a programming circuit incorporating a voltage regulator achieved in accordance with the known art, FIG. 2 shows another diagram of a programming circuit incorporating another voltage regulator of known type, FIG. 3 shows a diagram of a first embodiment of the regulator in accordance with the present invention, FIG. 4 shows a diagram of a second embodiment of the regulator in accordance with the present invention, FIGS. 5 and 6 show diagrams of embodiments of the regulator of FIG. 1, and FIGS. 7 to 9 show diagrams of details of the regulator in accordance with the present invention. Detailed description With reference to the figures 1 designates as a whole and diagramatically a programming circuit for at least one electrically programmable non-volatile memory cell 2, e.g. a FLASH cell. The cell 2 together with other cells of the same type is provided with an MOS transistor with floating gate G equipped with another gate CG termed control gate. The cells 2 are organised in columns with the respective source terminals S all connected to the same reference voltage, e.g. a signal ground GND, and with the respective drain terminals D connected together on a so-called bit line 5. The bit line 5 also comprises a pair of MOS transistors MB and MW connected in series together for selection of the bit line. The circuit 1 comprises a voltage regulator 3 designed in accordance with the present invention to regulate drain voltage of the cell 2 during programming thereof and designated below by Vd. For this purpose the regulator 3 comprises a gain stage provided by an operational amplifier Av, e.g. with unit gain, in cascade with which is connected a source-follower stage. The follower stage comprises an MOS transistor Mout polarised by a constant current generator Ib. The amplifier Av has a non-reversing input on which is applied a voltage Vref to be repeated on an output of the regulator 3 to supply the load consisting of the bit line 5. The output U is connected in feedback on another reversing input of the amplifier Av. The above said voltage Vref is achieved by division of a programming voltage Ppp performed by a resistive divider 6 comprising a pair of resistors R1 and R2. Said resistances R1 and R2 are inserted between a voltage terminal Vpp and the signal ground. Advantageously in accordance with the present invention the regulator comprises at least one circuit element allowing adaptation of the output voltage to the electrical length L of the memory cell. In the embodiment described here by way of non-limiting example said element is a resistive network 4 connected in series with the divider 6 to ground. Specifically the network 4 is a variable resistivity and is connected between the resistor R2 and ground. In the embodiment described here the network 4 comprises a series of MOS transistors M1,...,Mn of minimal area. Said transistors are connected in series between the resistor R2 and ground through the respective source and drain terminals. The gate terminals of said transistors all lead to the programming voltage Vpp as shown in the example of FIG. 7. In this manner the network 4 compensates also for the percentage variations resulting from the normal oscillations of the programming voltage Vpp. But it is important to note that the connections of the gate terminals and in general the connections of all the terminals of the transistor M1,..., Mn can be optimised with an adequate simulation. For example, an alternative solution provided again in accordance with the present invention is shown in FIG. 8 in which all the above transistors have their respective gate terminals connected to the interconnection point between the resistors R1 and R2. In an equivalent manner the example of FIG. 9 accentuates a solution in which all the transistors M1,..., Mn are inserted in the network 4 in diode configuration with their respective gate and drain terminals short-circuited. Again in these cases the percentage variations of the voltage Vpp are compensated even though indirectly. Advantageously, the number and size of transistors in terms of amplitude W and length L of the channel region are regulated in such a manner that the network 4 has a resistivity correlated with the length of the memory cell 2. Of course, the inventive solution proposed here is applicable in various circuit embodiments for programming circuit voltage regulators. For example, with reference to FIGS. 4, 5 and 6 it can be appreciated that the network 4 can be inserted in the resistive divider 6 regardless of the fact that the gain stage of the regulator 3 is provided with a single transistor, a pair of transistors or transistors in series or parallel, as in the known art solution of FIG. 1. Therefore, at the ends of the network 4 there is a voltage drop varying with the actual length of the memory cell. Specifically, said voltage drop increases with the length of the cell. Concretely, having on the drain terminal D of the cell 2 a drain voltage varying with the actual length of the cell means being able to operate with cells having an actual length which can vary in a broader range, thus improving the performance, feasibility and reliability of the memory circuit. In conclusion the main advantage of the voltage regulator in accordance with the present invention is to supply at. output a voltage whose value is constantly and appropriately adapted to the dimensions of the cell. Said regulator is therefore particularly suited to supplying power to the bit line of an electrically programmable non-volatile memory. In addition, the configuration of the transistors incorporated in the network 4 with variable resistivity is such as to perform a partial compensation of the variations of the programming voltage Vpp on the order of ± 0.6V thanks to the fact that the resistance is also variable with the programming voltage Vpp.

Claims: Electrically programmable non-volatile semiconductor memory device comprising a voltage regulator which in turn comprises a gain stage (3) supplied by a programming voltage (Vpp) and has an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2), said divider (6) comprising a first (R1) and a second resistive element (R2), the line programming voltage being derived from a common node between said first and second resistive elements (R1, R2), characterised in that said divider (6) is connected in series with at least one circuit element (4) having a variable resistivity correlated to the length (L) of the memory cell (2), in this way adapting the line programming voltage (5) to the length (L) of the memory cell (2). Memory device in accordance with claim 1 characterised in that said circuit element (4) has a resistivity varying with the programming voltage (Vpp). Memory device in accordance with claim 1 characterised in that said circuit element (4) is a network which comprises a plurality of transistors (M1,..., Mn) connected in series with each other. Memory device in accordance with claim 3 characterised in that said transistors (M1,..., Mn) are the MOS type and connected in series through their respective source and drain terminals between the resistive divider and ground. Memory device in accordance with claim 3 characterised in that said transistors (M1,..., Mn) are connected in series in diode configuration. Memory device in accordance with claim 3 characterised in that the respective gate terminals of said transistors (M1,..., Mn) are all supplied by said programming voltage (Vd). Memory device in accordance with claim 1 characterised in that said circuit element (4) is connected between one (R2) of the resistive elements and a reference potential. Memory device in accordance with claims 3 and 7 characterised in that the respective gate terminals of said transistors (M1,..., Mn) are all connected to one interconnection point between the first resistive elements (R1) and the second resistive element (R2).

Inventors: CAMERLENGHI EMILIO, CASAGRANDE GIULIO, CAMERLENGHI, EMILIO, CASAGRANDE, GIULIO, CASAGRANDE, GIULIO, C/O SGS-THOMSON MICR.SRL.
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C16
IPC codes: G11C16, G11C5, G11C17