Mixed typology output stage

Abstract: An output power stage composed of a pair of transistors driven in phase opposition and wherein the pull-up transistor is a PNP bipolar transistor and the push-down transistor is an n-channel FET has an outstandingly improved power handling capability per semiconductor area occupied, coupled with a large output voltage swing, without requiring the use of externally connected discrete boot-strap components. The "hybrid" output stage is fully complementary and the current-driven, bipolar, pull-up transistor may be driven through an auxiliary stage composed of a field effect transistor for substantially eliminating output power requisites of a signal amplification stage.

Description: FIELD OF THE INVENTION The present invention relates to an output stage for an integrated power amplifier particularly suited for audio amplifiers. BACKGROUND OF THE INVENTION The document US-A-4,588,960 discloses a class B output stage specifically for a low power, low voltage amplifier with particularly low quiescent power dissipation and low cross-over distortion composed by a bipolar transistor and a field effect transistor connected in series between power supply rails so that the input voltage dead band is advantageously reduced. Most preferably the upper or high side range of the out stage is realized with a bipolar junction NPN transistor and the lower or low side range of the stage is realized with a p-channel field effect transistor. The document EP-A-0 349 954 discloses a voltage clamped differential to single ended converter circuit, the output stage of which is composed of a MOS transistor connected between an output node and ground and a current source is operatively connected between the positive supply rail and the output node. The document US-A-5,028,881 discloses an operational transconductance amplifier with differential output employing saturated MOS transistor in the lower branches of the two output stages to improve linearity and dynamic range. The output stages of power amplifiers are normally designed for maximizing the dynamic excursion of the output voltage (output voltage swing), by reducing as much as possible voltage drops due to the series resistance of the active components (transistors) that form the output stage. There is an ample specific bibliography out of which the volume "Power Integrated Circuit", published by Mc.Graw Hill, in 1986, pages 9.28 - 9.35 may be cited. A widely used technique in power output stages is that of realizing a "bootstrap" line, using for this purpose a relatively large capacitance, that may be externally connected to the IC pins, in order to obtain the maximum peak-to-peak variation of the output voltage. Unfortunately, this technique conflicts with a general IC design trend of eliminating or reducing the need of passive external components to a minimum. The known configurations of a power output stage are amply reported in literature and substantially are those employing a pair of transistors operating in phase opposition, namely an NPN/NPN, PNP/NPN, pMOS/nMOS and nMOS/nMOS pair. Of course, the selection of one of the above configurations depends on the fabrication technology that is employed, which determines also the maximum reverse voltage that can be withstood by the devices (for example the maximum V CE of bipolar junction transistors or the maximum V DS of MOS transistors). Bipolar NPN transistors notably suffer from the problem connected to the so-called "second breakdown" phenomenon. Also bipolar PNP transistors are affected by this phenomenon but in a lesser measure than NPN transistors. On the contrary, DMOS transistors are notably exempt of this problem. In a mixed technology fabrication process (BJT, CMOS and DMOS) or BCD process, the power MOS transistors that can be realized in a compatible manner with the other type of integrated structures, have internal resistance characteristics that typically show the following values: (n-channel) DMOS : Ron = 0.5Ω x mm 2 (p-channel) DMOS : Ron = 2.2Ω x mm 2 In particular, the solution of using a complementary pair of DMOS output transistors would appear an ideal choice, by considering also the advantage represented by the fact that the two output transistors would not need a driving current, being intrinsically voltage-controlled devices. However, a p-channel DMOS transistor requires an integration area that may be four times the integration area of an n-channel, complementary DMOS transistor, for the same Ron. Therefore the solution that employs a complementary pair of DMOS transistors is adopted only in a limited number of applications, where the relatively large silicon area requirement is not a problem. On the other hand, the use of a (more compact) pair of transistors of the same polarity (that is noncomplementary), for example a pair of n-channel DMOS transistors, beside losing a portion equivalent to a VGS voltage of the maximum voltage swing of the output signal or otherwise requiring a bootstrap line, requires also a somewhat more complex driving circuit than the circuit that would be necessary for driving, in phase opposition, a complementary pair of output transistors. There is a long felt need or utility of a complementary output stage with good breakdown characteristics that would not need externally connected bootstrap components and require a relatively large area of integration. SUMMARY OF THE INVENTION It has been found that in a normal BCD fabrication process it is possible to realize a bipolar PNP power transistor, having an internal resistance Ron of about 0.3Ω x mm 2 , which can be satisfactorily used as the high side part of a complementary output power stage that employs as its low side part, an n-channel field effect transistor. A so configured output stage is perfectly complementary and therefore does not reduces the output dynamics by a VGS (or by a VBE) and may be driven by a relatively simple stage. The output stage has an intrinsically high voltage swing characteristic and does not need externally connected bootstrap components. The use of power transistors of different technology (a bipolar transistor of the high side or pull-up part and a field effect transistor for the low side or push-down part), permits to reach an outstandingly good compromise between the extent of silicon area necessary for integrating the two power transistors, by exploiting the relatively small size of an n-channel DMOS structure and of a vertical, isolated collector, PNP structure and the driving power requisite, which is required only by the active pull-up element constituted by the bipolar PNP transistor. The pull-up power element, constituted by a bipolar PNP transistor, is driven by a stage composed of a field effect transistor, for example a p-channel MOS transistor, of sufficient size to provide the driving power required by the bipolar output transistor. According to an embodiment of the invention, the PNP transistor may be constituted by a complex structure that comprises PNP and NPN transistors, the electrical behaviour of which can be equated to that of an equivalent PNP transistor. This solution permits to further reduce the integration area, being the power NPN structure of the PNP-equivalent complex structure capable of operating at a higher current density than a PNP structure and therefore requiring a reduced area of integration. Of course, in this latter case, the output voltage swing would be reduced by a VBE but this could be advantageously traded-off with a maximized saving of silicon area. BRIEF DESCRIPTION OF THE DRAWINGS The different aspects and advantages of the output stage of the invention will become more evident through the following description of several embodiments and by referring to the annexed drawing, wherein: Figure 1 is a circuit diagram of an output stage of the invention, according to an alternative embodiment thereof; Figure 2 is a more detailed circuit diagram of the output stage of Fig. 1. DESCRIPTION OF PREFERRED EMBODIMENTS The output stage of the invention is essentially constituted by a pull-up power element PW H , composed of a bipolar PNP transistor, and by a push-down power element PW L , composed of a DMOS transistor. The collector of PW H and the drain of PW L are connected in common to an output node OUT of the amplifier. The complementary pair of transistors of the output stage is customarily driven by a suitable driving stage. Of course, while the driving of the MOS transistor PW L occurs essentially in a voltage mode, with a practically null driving power, the driving of the high side element of the push-pull output stage, that is of the bipolar PNP transistor PW H , requires a certain driving current (base current). To this purpose, a MOS transistor M1 is employed for driving the bipolar PNP transistor PW H , so as to prevent to load the relative output node of the driver stage. A circuit diagram of the driver stage is depicted in Fig. 2. As may be observed, the driver stage may be realized with field effect transistors in a substantially symmetrical form. The high side part of the push-pull output stage, that is the power transistor PW H (driven through the MOS M1) is driven by the amplifier composed of R3, M2, M3 and the current generator I1. The low side part of the push-pull output stage, composed of the n-channel DMOS transistor PW L is driven by the amplifier composed of R4, M4, M5 and the current generator I2. In order to ensure compatibilitv to ground potential, the two resistances R1 and R2, connected between the IN- node and ground and between the IN-node and the load, respectively, determine the voltage gain.

Claims: A push-pull power output stage for an integrated power amplifier particularly suited for audio amplifiers, composed by a first transistor of a first type of conductivity and a second transistor of a second type of conductivity in a push-pull configuration, connected between a positive (+VCC) and a negative (-VCC) supply rail, the transistor (PW L ) connected to the negative supply rail (-VCC) being an n-channel DMOS power transistor having a gate, a drain operatively connected to an output node (OUT) of the amplifier, and a source operatively connected to said negative supply rail, the transistor (PW H ) connected to the positive supply rail (+VCC) being a bipolar junction PNP power transistor having a base, a collector operatively connected to said output node (OUT) and an emitter operatively connected to said positive supply rail, and a driver circuit (DRIVER STAGE) connected to drive said base and said gate of said transistors (PW L , PW H ), characterized in that said PNP power transistor (PW H ) is a vertical, isolated collector transistor, driven by said circuit (DRIVER STAGE) through an additional field-effect transistor (M1) operatively connected to drive the base of said PNP power transistor (PW H ).

Inventors: CINI CARLO, STEFANI FABRIZIO, CINI, CARLO, STEFANI, FABRIZIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H03F3
IPC codes: H03F3