Transistor with deep submicron channel

Abstract: A method of fabricating field effect transistors (FETs) that employs only optical lithography involves the formation of a relatively wide aperture using optical techniques is disclosed hereunder. The formation of composite sidewalls having differential etch resistance in the aperture to define a final aperture width less than that available with conventional optical techniques. A conventional P⁻is performed substrate (10) with ROI regions (15) defining an active N⁻ region (110) coated with a thin SiO2/Si3N4 insulating layer (20) is first provided. Then, a polish-stop layer of CVD boronitride (40) having a thickness equal to the desired thickness of the transistor gate is deposited. Next, an aperture (210) is formed therein by conventional optical lithrography and RIE using a CF ₄/O₂plasma. Two sidewall layers, a first layer of CVD oxide (50) and a second layer of CVD nitride (60) are now deposited onto the structure. A first selective etching step using an anisotropic dry etch of CHF ₃/C1₂removes the CVD nitride layer (60) from all the horizontal surfaces of the structure. A second selective etching step using a CF 4 /O₂plasma removes the CVD oxide layer (50) at the bottom of the aperture. A first boron implantation establishes the threshold level and another boron implantation prevents punch-through between the source and drain. They finally result in the formation of the channel (220). The thin insulating layer is stripped and a gate oxide (25) is grown within aperture (210).

Description: The invention relates to MOS integrated circuits, including CMOS integrated circuits, in the deep submicron region. For transistors having dimensions of less than 0.4 micron (the deep submicron region), the resolution limits of optical technology are approached. In order to avoid exotic technologies such as x-ray lithography, it is preferable to devise a method of manufacturing a CMOS transistor that does not press the limits of the optical methods. EP-A-145 927 describes a method of forming a field effect transistor structure which has a sub-micrometer channel length. US-A-5 120 688 describes a method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. The technique that is used permits to go beyond the limit of the optical equipment being used. US-A-5 069 747 describes a process of forming MOSFETs using sidewalls. The channel width definition corresponds to the resolution of the optical equipment used. The problem addressed by the present invention is that of providing reliable control of the channel length in a dimensional range smaller than that in which optical methods are reliable. The invention relates to a method of forming a deep submicron transistor in which an aperture is opened in a polish stop layer having a dimension that is considerably larger than the final channel width and within the limits of optical lithography. Sidewalls are formed within the aperture in a controllable manner to determine the final channel width of the transistor. The thickness of the sidewalls is maintained during the fabrication process by the use of a two-component sidewall and a selective etch, so that the etching process that determines the final channel dimension does not change the sidewall thickness. The channel implant is local, not blanket, eliminating the need to counterdope the source and drain areas. Figures 1 through 10 illustrate cross sections of a transistor site in various steps of formation. Referring now to Figure 1, there is shown a cross section of a P integrated circuit wafer 10, in which a transistor site or active area 150 is formed between two field areas 15. The steps of preparing the wafer, forming the field areas, etc. are conventional. The transistor will be an N-channel device and those skilled in the art will readily be able to manufacture P-channel devices in the light of this disclosure. The active areas will have a dopant concentration of a first polarity, which may be that of the substrate or may be that of a "well" formed in the substrate. Field areas 15 may be formed by a conventional field oxide or may be formed by a trench process. On the top of active area 150 there is a protective layer of initial nitride 22 and initial high quality dry oxide 21 (collectively referred to as layer 20) having a nominal thickness of 12 nm for nitride 22 and 8 nm for oxide 21. Oxide 21 is preferably a dry oxide because it will be left in place over the LDD areas of the source and drain. Within the active area there is a region, denoted by the numeral 110, that has been implanted with a dose of phosphorous of 4x10¹³/cm² at 35 KeV to convert P⁻ substrate 10 to the N⁻ doping concentration that is suitable for the low doped drain LDD portion of the transistor. The depth of implantation is not critical, since punch through and threshold adjustment implants will be performed later. The notation used here is conventional, with P⁻ and N⁻ meaning a volume density of approximately 1x10¹⁵/cm³ and P⁺ and N⁺ meaning a volume density of 1x10¹⁷/cm³. Referring to Figure 2, there is shown active area 150 after the deposition of a layer of CVD boronitride 40 (deposited as taught in "Hot filament activated chemical vapor deposition of boron nitride" R. R. Rye, J. Vac. Sci. Tech. A9 (3) May/Jun 1991, p1099), having a thickness equal to the desired thickness of the transistor gate, nominally 300 nm in the preferred embodiment. This boronitride layer will be referred to as a polish-stop layer, since a subsequent layer of polysilicon (poly) will be polished down to stop on layer 40. In Fig. 3, an aperture 210 having a transverse dimension of 800 nm, indicated by the bracket, has been formed in boronitride 40 by conventional optical lithography and a reactive ion etch RIE process using a CF₄/O₂ plasma. The final channel width has a nominal value of less than 0.4 micron in this embodiment, which is difficult to establish reliably with optical lithography. The following example illustrates parameters that result in a physical channel length of about 0.4µm. Two sidewall layers, a first layer of CVD oxide 50, having a thickness of 200 nm, and a second layer of CVD nitride 60, having a thickness of 12 nm, have been put down conformally as known in the art, so that the interior dimension of the aperture 210 is controlled very tightly. The deposition is conventional, well known to those skilled in the art. Referring now to Fig. 4, a first selective etching step using an anisotropic dry etch of CHF₃/Cl₂ has removed the CVD nitride layer 60 from all the horizontal surfaces without affecting the vertical nitride sidewalls in aperture 210. In the next step in Fig. 5, a second selective etching step using a CF₄/O₂ plasma has removed the CVD oxide 50 at the bottom of the aperture. The initial silicon nitride 22 in the channel area has served as an etch stop. The sidewalls within aperture 210 have a nominal thickness denoted by the bracket 216 that has not been affected by the second etch because this second etch has essentially no affect on the nitride sidewalls 60. Because of the anisotropic etch, there is no horizontal etch at the bottom of aperture 215. There may be some etching of sidewall 50 behind sidewall 60 because of process tolerances, but that has no effect on the aperture dimension, which is set by sidewalls 60. The result is a tightly controlled interior final aperture 215. In the preferred embodiment, dimension 216 is 210 nm with a tolerance of ±5 nm. This combines with a tolerance of 10 nm in the width of aperture 210 to give a width of 380 ± 5 nm for aperture 215. Referring now to Fig. 6, a boron implantation of 1x10¹²/cm² at 15 KeV to establish the threshold level and a boron implant of 3x10¹²/cm² at 140 KeV to prevent punch through between the source and drain have implanted the channel in an area denoted by the numeral 220 to convert the initial N⁻ doping to P⁻ (referred to as counterdoping). After these channel implants, the initial nitride and oxide layers are stripped by a conventional wet etch and a gate oxide 25 is grown within aperture 215. The gate oxide is preferably grown after the channel implant step so that it will be free from implant damage. It has been found that transistors in the deep submicron region are highly sensitive to the quality of the gate oxide, so that the small amount of implant damage to the gate oxide that was tolerable for longer channel lengths is no longer acceptable. U.S.-A- 5 082 794 illustrates in Figs 7 - 10 the formation of an inverse-T transistor by means of a local channel implant through an aperture having nitride sidewalls. This patent says nothing about the use of sidewall thickness control to provide a short channel unobtainable with conventional optical processing. The figures in that patent illustrate single-material sidewalls having a non-uniform thickness that teaches away from the present invention because variation in sidewall thickness will result in a poorly defined channel length. In addition, the channel implant was done through the bottom polysilicon gate as well as the gate oxide. as a result, the damaged gate oxide will have a low breakdown voltage that eventually leads to reliability problems because of the hot carrier effect. In the next step, a layer 70' of polysilicon has been deposited filling up aperture 215 and extending above the aperture by some tolerance amount to assure full coverage of the aperture. A conventional chemical-mechanical polishing step such as that illustrated in "Chemical-Mechanical wafer Polishing and Planarization in Batch System", (Solid State Technology, June 1992, p 112) is performed (Fig 8) in which polysilicon 70' is polished away, leaving a polysilicon gate 70, having a planar top surface, within aperture 215. Polish-stop 40 has performed its function of setting the reference for the polishing operation. At this time, the top of gate 70 can be silicided if desired to reduce the gate resistivity. Layer 40 is then removed in Fig 9 by a selective wet or dry etch, leaving a gate structure comprising the gate 70 consisting of the remainder of the polysilicon and the two composite sidewalls 55. If desired, a non-critical mask step can be used to expose the transistor site and layer 40 can be removed only over the source and drain. The boronitride in layer 40 etches much more quickly than the material of the gate structure, so that the gate structure does not need to be protected. In Fig. 10, an N⁺ implant of As with a dose of 2x10¹⁵/cm² at 80 KeV is performed to implant source 222 and drain 224 with a conventional N⁺ concentration. The result is an LDD transistor having a tightly controlled channel width of 380 ±5 nm in the area 220 that has been accomplished without the need to define an aperture of that size. In a corresponding P-channel transistor, the relevant parameters are: LDD: B, 6x10¹³ at 15 KeV S/D: B, 3x10¹⁵/cm² at 20 KeV V t adjust: P, 1x10¹²/cm² at 60 KeV Punch through: P, 5x10¹²/cm² at 180 KeV Those skilled in the art will readily be able to modify the embodiment illustrated to suit their purposes. Different combinations of material may be used for the polish stop and the two sidewalls, so long as differential etch and/or polish resistance is still present. Sidewalls 55 may be removed or left in place as desired. The LDD implant could be done after the gate is defined and after removal of sidewalls 55. The LDD implant could also be done after aperture 216 is formed and before formation of sidewalls 55. Other polish stop materials, such as CVD diamond ("Electrical characteristics of Schottky diodes fabricated using plasma assisted chemical vapor deposited diamond films", Appl. Phys. Lett. 53(7), 15 Aug 1988, p 586) or CVD silicon carbide could be used. If sidewalls 55 are damaged during the RIE steps, they may be stripped and regrown before the Source/Drain implant.

Claims: A method of forming a CMOS field effect transistor in a silicon substrate comprising in the following sequence the steps of: a) preparing a silicon substrate (10) of a first type of polarity (P) including a transistor active area (150); b) forming a LDD region (110) within said transistor active area having the opposite type of polarity (N); c) forming a polish-stop layer (40) of a predetermined polish-stop layer thickness over said LDD region; d) patterning said polish-stop layer to define a first aperture (210), having a predetermined first aperture width above said LDD region, said first aperture having first aperture sidewalls having a height equal to said polish-stop layer thickness and a first aperture bottom surface; e) forming a first sidewall layer (50) of a first conformal sidewall material onto the structure to a predetermined first sidewall layer thickness; f) forming a second sidewall layer (60) of a second conformal sidewall material onto the structure to a predetermined second sidewall layer thickness; first and second sidewall layers together forming a conformal composite layer thereby defining a second aperture (215) within said first aperture having a predetermined second aperture width less than said first aperture width and a second aperture bottom surface; g) performing at least one selective directional (anisotropic) etch, to eliminate the horizontal portions of said conformal composite layer just leaving composite sidewalls (55) in said second aperture; h) performing a local channel implant using a dopant of said first type of polarity through said second aperture to form the channel region (220) of the CMOS transistor in said LDD region, said channel width being determined by said second aperture width; i) growing a layer of gate oxide (25) in said second aperture; j) filling said second aperture with a layer of a conductive gate material (70'); k) eliminating said layer of polish-stop layer at least over portions adjacent to the composite sidewalls; and, l) blanket implanting a dopant of said second type of polarity at a predetermined energy to form source (222) and drain (224) regions for said transistor, said predetermined energy being related to said sidewall height whereby said transistor has a heavily doped source and drain separated from said channel by a portion of said LDD region. A method according to claim 1, further including between steps b) and c) the step of: forming a protective layer (20) at the surface of said LDD region; and between steps h) and i) the step of: removing the exposed portions of the protective layer in said second aperture.

Inventors: HSU LOUIS LU-CHEN, HUANG DANIEL L, WANG WEN-YUAN, HSU, LOUIS LU-CHEN, HUANG, DANIEL L., WANG, WEN-YUAN
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1993
Main classification: H01L21
IPC codes: H01L29, H01L21