Moving picture decoding device

Abstract: A moving picture decoding device in which picture data is read from a picture memory (20) responsive to a motion vector to perform decoding the motion-compensated moving picture and in which the picture data is also read in a pre-set sequence for display. With the present moving picture decoding device, the combination of data, that is a word format, for a word simultaneously read from four memory devices (DRAMs), is set so as to be different for the motion compensation and for display. That is, during motion compensation, simultaneous reading of a word consisting of luminance (Y) signal component data (D0, D1, D2 and D3) is time-divisionally changed over to simultaneous reading of a word consisting of chroma (Cb and Cr) signal component data (D2, D3, D0 and D1). During display, two luminance data (D0 and D1 (or D2 and D3)) are read out simultaneously with the chroma (Cb and Cr) signal component data (D2, D3 (or D0 and D1)). .

Description: BACKGROUND OF THE INVENTION This invention relates to a moving picture decoding device in which picture data is read from a picture memory responsive to a motion vector to perform decoding of motion-compensated moving picture and in which the picture data are also read in a pre-set sequence for display. There are a variety of systems for compressing and encoding moving picture signals, such as television telephone /television conference signals or telecast signals. Recently, a hybrid encoding system, such as MC-DCT, which consists in a combination of a so-called motion compensated (MC) inter-frame prediction and discrete cosine transform (DCT), is thought to be promising. Fig.1 shows a circuit arrangement for illustrating the above-mentioned MC-DCT hybrid system. In this figure, moving picture signals, such as television signals, are supplied as input signals to an input terminal 111. These input signals are supplied to a motion detection circuit 113 and a subtractive node 114 via a picture memory 112 employed as a frame memory. An output of the subtractive node 114 is transmitted to a DCT circuit 115 for discrete cosine transformation and thence supplied to a quantizer 116 for quantization before being supplied to a series circuit as a local decoder, consisting of a inverse quantization unit 117 and an inverse DCT (IDCT) circuit 118. An output of the IDCT circuit 118 is supplied via an additive node 119 to a picture memory 120 employed as a field memory. An output read from the picture memory 120 is transmitted to the motion detection circuit 113 and to a motion compensation circuit 121. The motion detection information such as the motion vector from the motion detection circuit 113 is transmitted to the motion compensation circuit 121. An output of the motion compensation circuit 121 is supplied to the subtractive node 114 and to the additive node 119. It is noted that the input signals are stored temporarily in the field memory 112 and subsequently read and processed on the basis of a block of a pre-set size. The motion detection circuit 113 compares the values of pixels of a signal block from the picture memory 112 to the values of pixels of locally decoded signals from the picture memory 120 for detecting the motion vector. The motion compensation circuit 121 outputs a reference block to the subtractive node 114 based on this motion vector. The subtractive node 114 outputs a difference between the input picture signal block and the reference block. The difference output is discrete cosine transformed by the DCT circuit 115 and quantized by the quantizer 116 before being supplied to a variable length coding unit 123, such as an entropy coding unit, for variable length coding. The motion vector from the motion detection circuit 113 is also supplied to the variable length coding unit 123 for variable length coding. An output of the variable length coding unit 123 is supplied to a transmitting buffer memory 125 where the coded data to be transmitted is stored transiently. The quantization by the quantizer 116 and the coding by the variable length coding unit 123 are controlled so that the amount of transmitted data per unit time will be constant. An output of the buffer memory 125 is outputted via an output terminal 126 so as to be transmitted over a communication network or recorded/reproduced on or from recording medium. If the input signals are color component picture signals, made up of Y (luminance) signals and C (chroma) signals, the MC and DCT operations are performed on both the Y signal data and the C signal data. The C signals are made up of color difference signals C b and C r corresponding to so-called B-Y signals and R-Y signals, respectively. As for the numbers of samples or the sampling frequency, the ratio of Y : C b : C r is set to 4 : 2 : 2, such that one C b pixel data and one C r pixel data are associated with two Y pixel data. In decoding the signals, processed with the above-described MC-DCT hybrid coding operations, it is necessary to read data of a frame directly preceding the current frame from the frame memory in accordance with the motion vector to perform motion compensation thereon. On the other hand, in displaying the signals on a display unit, such as a cathode ray tube (CRT) monitor, it is necessary to read the data sequentially from the memory in accordance with the scanning operation for display. The frame memory is made up of a number of, such as four, memory devices, such as DRAMs, and is adapted for reading out data from the memory devices by parallel reading with four bytes, as an example, as a word, at a rate of one byte from each memory device. In accessing the data on the frame memory, such a word format may be contemplated in which two bytes, for example, of Y data and each one byte of the C b and C r data, totalling at four bytes, make up each word. Such word format dispenses with a buffer memory for display. However, a problem is raised that the buffer memory for adjusting the timing when summing the motion - compensated picture data to the inter-frame difference data is increased in capacity. On the other hand, if a word format convenient for MC processing such as a word format in which a word consisting only of four Y bytes is changed over to a word consisting only of four C bytes or vice versa as time elapses, is employed, a buffer memory for display becomes necessary to provide, while the number of times of data reading from the frame memory for Mo processing is increased, even although the buffer memory for timing adjustment for MC processed data may be reduced in capacity. From EP-A-0503956 a technique to decode intra-frame and interframe coded compressed video data is known. The two-dimensional display space is mapped into external DRAM addresses by embedding in the address space x and y vectors of the display space. Mapping of the x and y vectors allows a microblock of pixels to be stored in one DRAM memory page, so that an access to a microblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of 4 pixels can be obtained at one time in one of 2 pixel x 2 pixel "quad pixel" configuration, or in a 4 pixel x 1 pixel horizontal "scan" configuration. SUMMARY OF THE INVENTION In view of the above-depicted status of the art, it is an object of the present invention to provide a moving picture decoding device in which the buffer memory for display may be dispensed with and the number of times of data reading from the frame memory during MC processing is not increased, while the buffer memory for timing adjustment for motion - compensated data may be reduced in capacity. This object is achieved by means of a device comprising the features of claim 1. The dependent claims develop further the central idea of the invention. With the moving picture decoding device, signals encoded by a so-called MC-DCT hybrid coding system are entered as input signals. The inter-frame difference data produced on inverse DCT and picture data read out from the picture memory in accordance with the motion vector are summed together and the resulting sum signals are written in the picture memory. The picture memory is made up of plural memory devices each having a first storage area for storing picture data of luminance signal components and a second storage area for storing picture data of chroma signal components. The operation of reading the picture data of the luminance signal components from the first storage area of all of the memory devices is changed over time-divisionally during motion compensation to the operation of reading the picture data of the chroma signal components from the second storage area of all of the memory devices. During display, the picture data of the luminance signal components are read from the first storage areas of one or more of the memory devices at the same time as the picture data of the chroma signal components are read from the second storage areas of the remaining memory devices. During the motion compensation, a word consisting of m row by n column luminance signal component picture data is time-divisionally changed over on a two-dimensional screen to a word consisting of m row by n/2 column chroma signal component picture data. Besides, two m row by n/2 column chroma signal component picture data in the word format during the motion compensation are written in memory devices different from the memory devices in which the luminance signal component picture data of the same row are written. Specifically, when simultaneously reading the Y data and the C data during the display, even row Y data are read from the memory devices M0 and M1, and the C b and C r data of the same even rows are read from the memory devices M2 and M3, while odd row Y data are read from the memory devices M2 and M3, and the C b and C r data of the same odd rows are read from the memory devices M0 and M1. With the moving picture decoding device according to the present invention, picture data only of luminance signal components are read time-divisionally from the picture memory and picture data only of chroma signal components are also read time-divisionally from the picture memory during motion compensation, so that the buffer memory for timing matching with respect to the motion-compensated data may be reduced in capacity. Besides, the Y data and the C data are read simultaneously during the display, so that the buffer memory for display may be eliminated. In addition, by setting the word of the Y data during motion compensation, such as a 4-byte word, to a m row by n column word, such as a 2-row by 2 column word, the number of times of data reading per macro-block may be prevented from being increased as compared to the case in which each word is arranged as a one-row word, such as a 4-byte one-row word. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a block circuit diagram showing an example of a basic arrangement of a motion compensation (MC) -discrete cosine transform (DCT) hybrid encoding system. Fig.2 is a block circuit diagram showing a schematic arrangement of a moving picture decoding device according to the present invention. Fig.3 is a block circuit diagram showing a concrete arrangement of a frame memory and a memory control unit making up the moving picture decoding device according to the present invention. Fig.4 shows a word format for the moving picture decoding device according to the present invention. Fig.5 illustrates an example of a memory map of a frame memory of the moving picture decoding device according to the present invention. Fig.6 illustrates the state of switching of the word format between that during the motion compensation (MC) and that during display. Fig.7 illustrates macro-blocks for transfer of inter-frame difference data of the moving picture decoding device according to the present invention. Fig.8 illustrates an example of a conventional word format suited to display. Fig.9 illustrates a memory map of every memory device of the frame memory in case of using the word format shown in Fig.8. Fig.10 illustrates the number of times of reading per macro-block during MC processing in case of using the word format shown in Fig.8. Fig.11 illustrates an example of a conventional word format suited to MC processing. Fig.12 illustrates a memory map of every memory device of the frame memory in case of using the word format shown in Fig.11. Fig.13 illustrates the number of times of reading per macro-block during MC processing in case of adoption of the word format shown in Fig.11. Fig.14 illustrates the number of times of reading per macro-block during MC processing in case of using the word format shown in Fig.11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig.2 shows, by a schematic block circuit diagram, an arrangement of an embodiment of a moving picture decoding device according to the present invention. To an input terminal 11 of the present embodiment, shown in a block circuit diagram of Fig.2, there is supplied a signal data string or so-called bit stream which has been encoded in accordance with e.g. the above-described MC-DCT coding. The input signal is also supplied to an inverse variable length coding or decoding circuit (IVLC) 12 for inverse variable length decoding for generating compressed data and motion vector data for motion compensation. The compressed data from the IVLC circuit 12 is transmitted to an inverse DCT circuit 13 for an inverse DCT operation, that is a reverse operation of the DCT operation, before being supplied to an additive node 14. The motion vector data for motion compensation from the IVLC circuit 12 is supplied to a motion compensation circuit 15 from which a read address for a motion compensation block based on the motion compensation vector is supplied to a memory controller 21 of a frame memory 20 used as a picture memory. Data of the motion compensation block is read from the frame memory 20 in accordance with the readout address and transmitted to the motion compensation circuit 15. The motion-compensated picture data from the motion compensation circuit 15 is transmitted via a 16 timing - adjustment buffer memory to the additive node 14. Addition output data from the additive node 14 is supplied to the frame memory 20 so as to be written in locations designated by addresses from a write address counter 17 which is adapted for counting up at each output timing of the sum data from the additive node 14. For sequentially reading picture data written in the frame memory 20 for display on a display unit, such as a CRT monitor, address data from a display address counter 31 are transmitted to a memory control unit 21 and picture data read in accordance with the display addresses are occasionally outputted at an output terminal 33 via a display buffer memory 33. In the present embodiment, the word format of a word as a readout unit for picture data for motion compensation and that of a word as a readout unit for picture data for display are changed over to a respective proper word format. To this end, the frame memory 20 and the memory control unit 21 are arranged as shown in detail in Fig.3 to realize the relation between the memory and the picture data shown in Figs.4 to 6. Fig.3 shows an example of a concrete arrangement for memory control in which an emphasis of representation is placed on readout addresses for the frame memory 20 and readout data from the frame memory 20. A changeover control signals for changing over the motion compensation (MC) to the display and vice versa is supplied to an input terminal 22. The changeover signal for MC/display switching is supplied to each of changeover control terminals of selectors 23, 24. As a select input A of the selector 23, the bits of an address for reading picture data for motion compensation (MC) from the least significant bit (LSB) up to the most significant bit (MSB) are supplied as MC address data. In more detail, these bits are made up by 8 bits for coordinate points X1 to X8 of a column excluding X0, 8 bits for coordinate points Y1 to Y8 of a row excluding Y0 and a 1 bit for a Y data /C data selection flag. As a select input B of the selector 23, the bits of an address for reading display picture data from the least significant bit (LSB) up to the most significant bit (MSB) are supplied as displayed address data. In more detail, these bits are made up by 8 bits for coordinate points X1 to X8 of a column excluding X0, 8 bits for coordinate points Y1 to Y8 of a row excluding X0 and 1 bit for Y0 data. One of these select inputs is selected responsive to the changeover control signal so as to be outputted at an S output. The even and odd rows for the MC addresses are represented by the Y/C bit which is supplied as a changeover control signal for selectors 26, 27 as later explained. Meanwhile, if the pixels of the display screen are represented by a two-dimensional matrix of display addresses, in a manner not shown, the lower most bit of a row address, such as an address A g , may be used as a changeover control signal for indicating an even row or an odd row. The S output of the selector 23 is supplied to memory devices, such as DRAMs M0, M1, M2 and M3 making up the field memory 20 as address data for the respective DRAMs (DRAM addresses). It should be noted that the S output of the selector 24 is employed as each of the MSBs of the addresses of the memory devices M2 and M3. The MSB of the S output of the selector 23 is supplied as a select input A of the selector 24, while a complement of the S output is supplied via an invertor (NOT gate) 25 as a select input B of the selector 24. One of these select inputs is selected depending on the MC/display changeover control signal so as to be supplied as the MSBs of the address data for the memory devices M2 or M3. The picture data read from the memory devices M0, M1, M2 and M3 are taken out as motion compensation (MC) data. Besides, the picture data read from the memory devices M0, M1 are supplied as a select input A for the selector 26 and a select input B for the selector 27, respectively, while the picture data read from the memory devices M2, M3 are supplied as a select input B for the selector 26 and a select input A for the selector 27, respectively. The selectors 26, 27 select one of the select A input or the select B input, depending on the lower most bit of the row outputted from the selector 23 during the display, that is the bit indicating the even row or the odd row. The S output from the selector 26 and the S output from the selector 27 is employed as a luminance (Y) component and as a chroma (C) component during display, respectively. If the picture data read from the four memory devices (DRAMs) M0, M1, M2 and M3 making up the field memory 20 are indicated as D0, D1, D2 and D3, respectively, the relation between the pixel data D0, D1, D2 and D3 and the pixel positions on a one-field two-dimensional array is as shown in Fig.4, in which two words during the MC processing are shown. The memory map for the memory devices M0, M1, M2 and M3 is as shown in Fig.5. The word format during the MC processing for two words and the word format during the display for two words are shown at (A) and (B) in Fig.6, respectively. Each one byte of the picture data is read from each of the four memory devices M0, M1, M2 and M3, thus a sum total of 4 bytes, are read out simultaneously. These four bytes make up a word as a picture data read unit. That is, a word as a picture data accessing unit in general means a group of picture data in the memory devices of the picture memory accessed simultaneously. The one word may be set to the number of bytes other than the four bytes, such as 8 or 16 bytes. In the present embodiment, the word format during the MC processing is set so as to be different from that during display, as shown at A and B in Fig.6, in such a manner that the word format suited to the MC processing or display may be employed for the MC processing or display, respectively. The main features of these word formats reside in that the word composed only of the luminance (Y) components is time-divisionally changed over to the word composed only of the chroma (C) components or vice versa during the MC processing, while the word displayed is the word composed of the Y and C components. Reference is had to Fig.4 for more detailed explanation. As for the Y data, that is picture data of the luminance signal component, 2 vertical pixels by 2 horizontal pixels are associated with coordinate points (2i, 2j), where 2i denote the horizontal positions (i = 0 to 359) and 2j denote the vertical positions (2j = 0 to 119), each frame being made up by 720 horizontal pixels by 240 vertical pixels. These 2 vertical pixels by 2 horizontal pixels are associated with the data D0, D1, D2 and D3 of the memory devices M0, M1, M2 and M3, respectively. As for the C b data, that is picture data of the chroma components C b , the pixel data D2, D0 of the memory devices M2, M0 in an array of two vertical pixels by one horizontal pixel are associated with coordinate points (i, 2j) in a two-dimensional area of a frame made up of 360 horizontal pixels by 240 vertical pixels, where i denotes the horizontal position (i = 0 to 359) and 2j denotes the vertical position (j = 0 to 119). As for the C r data, that is picture data of the chroma components C r , the data D3, D1 of the memory devices M3, M1 in an array of two vertical pixels by one horizontal pixel are associated with coordinate points (i, 2j) in the two-dimensional area of the frame made up of 360 horizontal pixels by 240 vertical pixels, where i denotes the horizontal position (i = 0 to 359) and 2j denotes the vertical position (j = 0 to 119). It is seen from Fig.4 that the mapping to the memory devices of one-field Y, C b and C r data is so designed that the memory devices M0 and M1 in which the Y data D0, D1, for example, of a given row, such as row 2j, are recorded are not the same as the memory devices M2 and M3 in which the Cb data D2, and the Cr data D3 of the same row, are recorded. Fig.5 shows an exemplary memory map for the four memory devices M0, M1, M2 and M3. In Fig.4, each of the memory devices M0, M1, M2 and M3 has a Y data storage area and a C (C b , C r ) data storage area, each having a storage capacity equal to one-half the total storage capacity. In the Y data storage area of the memory device M0, Y data for even columns and even rows, corresponding to the coordinate indications 2i and 2j, are stored, while, in the Y data storage area of the memory device M1, Y data for odd columns and even rows, corresponding to the coordinate indications 2i+1 and 2j, are stored. In the Y data storage area of the memory device M2, Y data for even columns and odd rows, corresponding to the coordinate indications 2i and 2j+1, are stored, while, in the Y data storage area of the memory device M3, Y data for odd columns and odd rows, corresponding to the coordinate indications 2i+1 and 2j+1, are stored. In the C data storage areas of the memory devices M0, M1, M2 and M3, C b data for odd rows, C r data for odd rows, C b data for even rows and C r data for even rows are stored, respectively. Returning to Fig.3, assuming that the memory devices, mapped as described above, are employed, and the operation is that for motion compensation, the selector 23 selects and outputs the MC address at the select A input, while the selector 24 outputs the MSB without complementation. Consequently, during the motion compensation for the Y data, the Y data D0, D1, D2 and D3 are read from the Y data storage areas of the memory devices M0, M1, M2 and M3, respectively, while, during the motion compensation for the C data (C b and C r data), the C b data D0 and D2 and the C r data D3 and D1 are read from the respective C data storage areas of the memory devices M0, M1, M2 and M3, respectively, these data being outputted as the MC data. As for the operation during display, the selector 23 selects the display address of the select input B to issue the S output, while the selector 24 issues the output S the MSB of which has been complemented by the invertor 25. On the other hand, the lower most bit of the row of the input display address, that is the bit indicating whether the row is an even row or an odd row, such as the bit A g , is separately taken out from the selector 23 so as to be supplied to changeover control terminals of the selectors 26, 27. If the odd/even row indicating bit is 0, that is if the row is even, the selector 26 outputs picture data from the memory devices M0 and M1, that is Y data D0 and D1, while the selector 27 outputs picture data from the memory devices M2 and M3, that is C b and C r data D2 and D3. If the odd/even row indicating bit is 1, that is if the row is odd, the selector 26 outputs picture data from the memory devices M2 and M3, that is Y data D2 and D3, while the selector 27 outputs picture data from the memory devices M2 and M3, that is C b and C r data D0 and D1. The above may be summarized as shown at A and B in Fig.6. That is, during the MC operation, a word consisting only of Y data D0, D1, D2 and D3 and a word consisting only of C (C b and C r ) data D2, D3, D0 and D1 are read out time-divisionally, while, during display, a word consisting of the Y data D0 and D1 and the C (C b and C r ) data D2 and D3 is read for even rows and a word consisting of the Y data D2 and D3 and the C (C b and C r ) data D0 and D1 is read for odd rows. If the word format shown at A in Fig.6 is employed, the buffer memory for display 32 shown in Fig.1 may be eliminated and the buffer memory for timing adjustment shown in Fig.1 may be reduced in capacity, while the number of times of data reading per macro-block during motion compensation may be diminished. The explanation of the macro-block is now made by referring to Fig.6. Fig.7 shows the transfer sequence of picture data to the IDCT circuit 13 in the circuit arrangement of Fig.2, that is the inter-frame difference data, by numerals 1 to 8. The eight blocks, each consisting of 8 x 8 pixels, make up a macro-block. The capacity of the buffer memory for timing adjustment 16 shown in Fig.2 may be reduced by first performing the processing of the word consisting only of Y data, followed by the processing of the word consisting only of C (C b and C r ) data, in accordance with the data transfer sequence shown in Fig.7. On the other hand, the number of times of data reading per macro-block may be prevented from being increased as compared to that with the conventional word format. For clarifying the operation and effect of the present embodiment, conventional data accessing to the frame memory is explained. Fig.8 shows as a word format suited to display, an illustrative word format in which Y data is formed by two bytes of D0 and D1, C b data is one byte of D2 and C r data is one D3 byte. In such case, it suffices to employ the memory devices M0 and M1, the memory device M2 and the memory device M3, for storage exclusively of the Y data, C b data and the C r data, respectively. If such word format, shown in Fig.8, is employed, the number of times of data reading on the frame memory during motion compensation may be diminished, as shown in Fig.10. That is, while the Y data macro-block shown in Fig.7 is made up of 16 x 16 pixels, the motion vector for motion compensation is expressed on the basis of 0.5 pixel, and hence it becomes necessary to take a mean value between two pixels if there is a fraction number of 0.5. Consequently, an area of 17 x 17 pixels has to be read. With the word format shown in Fig.8, data shown by a solid line in Fig.9 may be employed when the horizontal component V x (the component along the x-axis) of the motion vector is 0 or 0.5. On the other hand, if V x is 1 or 1.5, data indicated by a broken line may be employed, while, if V x is 2, 2 is added to the column address of each of the memory devices M0 to M3 to perform the same operation as that for V x equal to 0. Since the data D0 to D3 are collectively read as one word, data reading in the column direction is carried out 9 times, while data reading in the row direction is carried out 17 times, so that the number of times of data reading is equal to 17 x 9 = 153. The Y data and the C data are read simultaneously. Thus the number of times of data reading per macro-block in Fig.7 becomes equal to 153. However, if the word format shown in Fig.8 is employed, in which the Y data and the C data are read simultaneously, the memory capacity of 8 blocks corresponding to 512 bytes is necessary to provide for the buffer memory for timing adjustment 16 of Fig.2 for achieving timing adjustment with respect to data transfer from the IDCT circuit 13 to the additive node 14 in the transfer sequence shown in Fig.2. It may also be contemplated to employ a word consisting only of 4 bytes of Y data and a word consisting only of 4 bytes of C (C b and C r ) data, as shown in Fig.11, as a word format suited to motion compensation, or as a word format which lends itself to reduction in the capacity of the timing adjustment buffer memory 16. In such case, the capacity of the timing adjustment buffer memory 16 of 4 blocks corresponding to 256 bytes suffices if the processing of the word consisting only of the Y data is performed first and that of the word consisting only of the C data is performed subsequently in accordance with the transfer sequence of the data supplied to the IDCT circuit 13 shown in Fig.7. Fig.12 shows an example of the memory map for the memory deices M0, M1, M2 and M3 in such case. It is noted that each of the memory deices has a Y data storage area and a C data storage area. However, if the word format as shown in Fig.11 is employed, the number of times of data reading on the frame memory per macro-block is increased, as may be seen from Fig.12. That is, if the horizontal component (x-component) of the motion vector V x is 0 or 0.5, solid-line data shown in Fig.13 is employed, while, if V x is 3 or 3.5, broken-line data shown in Fig.13 is employed. If V x is in range of from 1 and 2.5, data intermediate between the solid and broken lines are employed. If V x is 4, 2 is added to the column addresses of the memory devices M0 to M3 to perform an operation similar to that when V x is 0. Since the data D0 to D3 are collectively read as one word, data reading in the column direction is made 5 times, while data reading in the row direction is made 17 times, so that the number of times of data reading becomes equal to 17 x 5 = 85. Besides, since both the Y data and the C data need to be read, the number of times of data reading per macro-block in Fig.7 becomes equal to 170. Besides, if the word format shown in Fig.11 is employed, the capacity of 4 bytes or more is necessary to provide for the display buffer memory 32 shown in Fig.2, because the Y data and the C data then cannot be read simultaneously during the display. Conversely, if the word format shown in Fig.4, that is in Figs.6A and 6B, is employed, the defect proper to the word format of Figs.8 or 11 may be resolved. Tat is, by reading the Y and C data simultaneously during the display as shown at B in Fig.6, the buffer memory for display 32 may be eliminated. Besides, by time-divisionally reading only the Y data or the C data during the MC processing as shown at A in Fig.5, the capacity of the buffer memory for timing adjustment 16 may be reduced to 4 blocks corresponding to 256 bytes. In addition, the number of times of data reading per macro-block during the MC processing may be diminished as compared to that in the case of employing the word format shown in Fig.11. Fig.14 illustrates the reading of the Y macro-block data. For assuring an area of 17 x 17 pixels for motion compensation, solid-line data shown in Fig.14 may be employed if the horizontal component (x-direction component) V x of the motion vector is 0 or 0.5, while broken-line data shown in Fig.14 may be employed if the horizontal component (x-direction component) V x of the motion vector is 1 or 1.5. If V x is equal to 2, it suffices if 1 is added to the column addresses of the memory devices M0 to M3 to perform an operation for V x equal to 0. On the other hand, solid-line data shown in Fig.14 may be employed if the vertical component (y-direction component) V y of the motion vector is 0 or 0.5, while broken-line data shown in Fig.14 may be employed if the vertical component (y-direction component) V y of the motion vector is 1 or 1.5. If V x is equal to 2, it suffices if 1 is added to the row addresses of the memory devices M0 to M3 to perform an operation for V y equal to 0. Since the data D0 to D3 are collectively read as one word, data reading in the column direction is made 9 times, while data reading in the row direction is made 9 times, so that the number of times of data reading becomes equal to 9 x 9 = 81. Besides, since both the Y data and the C data need to be read, the number of times of data reading per macro-block in Fig.7 becomes equal to 81 x 2 =170. The above may be summarized as sown in the following Table 1. buffer memory for timing adjustment 16 buffer memory for display 32 number of times of data reading per macro-block (during MC) word format of Figs.3 and 4 4 blocks (256 bytes) unnecessary 162 word format of Figs.7 and 8 8 blocks (512 bytes) unnecessary 153 word format of Figs.10 and 11 4 blocks (256 bytes) necessary (4 bytes or more) 170 It is seen from the above Table that the capacity of the buffer memory for timing adjustment 16 may be reduced to 4 blocks corresponding to 256 bytes, while the buffer memory for display 32 may be eliminated. On the other hand, while the number of times of data reading per macro-block during the MC processing is not so small as 153 for the word format shown in Fig.8, it is significantly less than 170 for the word format shown in Fig.10. It is to be noted that the present invention is not limited to the above-described embodiments. For example, the number of bytes per word is not limited to 4, but may be set to an arbitrary value, such as 8 or 16. Although the word array of 2 rows by 2 columns is used for motion compensation, a word array of m rows by n columns, where preferably m is an integer not less than 2 and n is an even number, may also be employed.

Claims: A moving picture decoding device, comprising an inverse discrete cosine transforming means (13) outputing luminance signal blocks and chrominance signal blocks representing luminance and chrominance signal components, respectively, a picture memory (20) comprising at least one first storage area for storing picture data of luminance signal components (Y) and at least one second storage area for storing picture data of chrominance signal components (Cb, Cr), and control means (21,23,24) for providing two different word formats for the reading out of the picture memory (20), one word format being used for motion compensation and the other word format being used for displaying of the picture data, by inputting a control signal to a predetermined address input terminal (MSB) of the picture memory (20), characterized in that said picture memory(20) is made up of plural memory devices (M) each having a first storage area for storing picture data of luminance signal components (Y) and a second storage area for storing picture data of chrominance signal components, wherein the luminance signal components of a given row are recorded in other memory devices (M) than the chrominance signal components of the same row, and said control means (23, 24) addresses the picture memory (20) such that during said motion compensation the operation of reading words composed of the luminance signal components (Y) corresponding to the luminance signal blocks from said first storage area of all memory devices (M) is changed over time-divisionally to the reading of words composed of the chrominance signal components (Cb, Cr) corresponding to said chrominance signal blocks from said second storage area of all memory devices (M), and during said displaying words composed of said luminance signal components (Y) from said first storage area of one or more of said memory devices (M) and of said chrominance signal components (Cb, Cr) from said second storage areas of the remaining ones of said memory devices (M) are provided by reading out simultaneously said luminance and chrominance components. The moving picture decoding device as claimed in claim 1 wherein picture data obtained by addition of the motion-compensated data to inter-frame difference data are written in said picture memory. The moving picture decoding device as claimed in claim 1 or 2 wherein, during said motion compensation, a word format consisting of two m row by n column luminance signal component picture data (Y) is time-divisionally changed over to a word format consisting of two m row by n/2 column chroma signal component picture data (D0, D1, D2 and D3). The moving picture decoding device as claimed in claim 3 wherein two m row by n/2 column chroma signal component picture data (D0, D1, D2 and D3) in the word format during the motion compensation are written during motion compensation in memory devices different from the memory devices (M) in which the luminance signal component picture data of the same row are written.

Inventors: SUMIHIRO HIROSHI, SUMIHIRO, HIROSHI, SUMIHIRO, HIROSHI, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H04N7
IPC codes: H04N5, H04N7, H04N11