Adaptive cache miss prediction mechanism

Abstract: In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined wish an address in the stack to develop a predictive address. The cache miss prediction mechanism is adaptively selectively enabled by an adaptive circuit that develops a short term operand cache hit ratio history and responds to ratio improving and ratio deteriorating trends by accordingly enabling and disabling the cache miss prediction mechanism.

Description: Field of the Invention This invention relates to the art of data processing systems which include a cache memory feature and, more particularly, to a method and apparatus for adaptively selectively predicting memory cache misses for operand calls and using this information to transfer data from a main memory to cache memory to thereby lower the cache miss ratio. Background of the Invention The technique of employing a high speed cache memory intermediate a processor and a main memory to hold a dynamic subset of the information in the main memory in order to speed up system operation is well known in the art. Briefly, the cache holds a dynamically variable collection of main memory information fragments selected and updated such that there is a good chance that the fragments will include instructions and/or data required by the processor in upcoming operations. If there is a cache "hit" on a given operation, the information is available to the processor much faster than if main memory had to be accessed to obtain the same information. Consequently, in many high performance data processing systems, the "cache miss ratio" is one of the major limitations on the system execution rate, and it should therefore be kept as low as possible. The key to obtaining a low cache miss ratio is obviously one of carefully selecting the information to be placed in the cache from main memory at any given instant. There are several techniques for selecting blocks of instructions for transitory residence in the cache, and the more or less linear use of instructions in programming renders these techniques statistically effective. However, the selection of operand information to be resident in cache memory at a given instant has been much less effective and has been generally limited to transferring one or more contiguous blocks including a cache miss address. This approach only slightly lowers the cache miss ratio and is also an ineffective use of cache capacity. Thus, those skilled in the art will understand that it would be highly desirable to provide means for selecting operand information for transitory storage in a cache memory in such a manner as to significantly lower the cache miss ratio. That end was accomplished in accordance with the invention disclosed in published European Patent Application no. 90110881.1 / 0402787 for CACHE MISS PREDICTION METHOD AND APPARATUS by Charles P. Ryan, by special purpose apparatus in the cache memory which stores recent cache misses and searches for operand patterns therein. Any detected operand pattern is then employed to anticipate a succeeding cache miss by prefetching from main memory the block containing the predicted cache miss. It was determined, however, that under certain operating conditions, the full time use of the foregoing procedure can actually raise the long term miss ratio (i.e., lower the long term hit ratio). In a typical cache based processor that executes a single process during a given period, the cache hit ratio will stabilize after some time interval following the institution of the process. If a change to another process is made, new instructions and data must be loaded into the cache such that cache hit ratio instantaneously drops dramatically and then increases as the new process is "experienced". If the cache miss prediction mechanism is in operation, the initial rate of increase in the cache hit ratio is much faster. However, the hit ratio never reaches the level it would reach in the long term if the cache miss prediction mechanism was not in use. This result is caused by the fact that the cache miss prediction mechanism continues to find and load from main memory the next possible miss which, however, is not used, thus forcing the cache to replace blocks that are more important. The invention disclosed and claimed in United States Patent Application Serial No. 07/841,687 filed February 26, 1992, for SELECTIVELY ENABLED CACHE MISS PREDICTION METHOD AND APPARATUS by Charles P. Ryan, overcomes the limiting effect of using the cache miss prediction mechanism continuously after, a process has been changed by selectively enabling the cache miss prediction mechanism only during cache "in-rush" following a process change to increase the recovery rate; thereafter, it is disabled, based upon timing-out a timer or reaching a hit ratio threshold, in order that normal procedures allow the hit ratio to stabilize at a higher percentage than if the cache miss prediction mechanism were operated continuously. There are operating conditions, however, under which it would be advantageous to have the cache miss prediction mechanism in operation even after cache inrush following a process change. An example of such an operating condition is when very large sets (even in excess of the cache size) of regularly addressed operand data (matrix/vector/strings) are used by a procedure. Objects of the Invention It is therefore a broad object of this invention to provide an improved cache memory in a data processing system. It is another object of this invention to provide a cache memory particularly characterized by exhibiting a lower cache miss ratio in operation. It is a more specific object of this invention to provide a cache memory for adaptively selectively enabling circuitry for effectively predicting operand cache misses not only during an "in-rush" period following a process change but also in other operating conditions in which it would be advantageous to enable the cache miss prediction mechanism. Summary of the Invention Briefly, these and other objects of the invention are solved in advantageous manner basically by applying the features laid down in the independent claims. Further enhancements are provided by the subclaims. There is provided special purpose apparatus which stores recent cache misses and searches for address patterns therein. Any detected pattern is then employed to anticipate a succeeding cache miss by prefetching from main memory the block containing the predicted cache miss. The cache miss prediction mechanism is adaptively selectively enabled by an adaptive circuit that develops a short term operand cache hit ratio history and responds to ratio improving and ratio deteriorating trends by accordingly enabling and disabling the cache miss prediction mechanism. Description of the Drawing The invention may best be understood by reference to the following description taken in conjunction with the accompanying drawings of which: FIG. 1 is a generalized block diagram of a typical data processing system employing a cache memory and therefore constituting an exemplary environment for practicing the invention; FIG. 2 is a flow diagram illustrating, in simplified form, the sequence of operations by which the invention is practiced; FIG. 3 is a logic diagram of a simple exemplary embodiment of the cache miss prediction mechanism; FIG. 4 is a logic diagram of a more powerful exemplary embodiment of the cache miss prediction mechanism; and FIG. 5 is a logic diagram of an exemplary embodiment of the adaptive circuit for selectively enabling the cache miss prediction mechanism. Detailed Description of the Invention Referring now to FIG. 1, there is shown a high level block diagram for a data processing system incorporating a cache memory feature. Those skilled in the art will appreciate that this block diagram is only exemplary and that many variations on it are employed in practice. Its function is merely to provide a context for discussing the subject invention. Thus, the illustrative data processing system includes a main memory unit 13 which stores the data signal groups (i.e., information words, including instructions and operands) required by a central processing unit 14 to execute the desired procedures. Signal groups with an enhanced probability for requirement by the central processing unit 14 in the near term are transferred from the main memory unit 13 (or a user unit 15) through a system interface unit 11 to a cache memory unit 12. (Those skilled in the art will understand that, in some data processing system architectures, the signal groups are transferred over a system bus, thereby requiring an interface unit for each component interacting with the system bus.) The signal groups are stored in the cache memory unit 12 until requested by the central processing unit 14. To retrieve the correct signal group, address translation apparatus 16 is typically incorporated to convert a virtual address (used by the central processing unit 14 to identify the signal group to be fetched) to the real address used for that signal group by the remainder of the data processing system to identify the signal group. The information stored transiently in the cache memory unit 14 may include both instructions and operands stored in separate sections or stored homogeneously. Preferably, in the practice of the present invention, instructions and operands are stored in separate (at least in the sense that they do not have commingled addresses) memory sections in the cache memory unit 14 inasmuch as it is intended to invoke the operation of the present invention as to operand information only. The cache miss prediction mechanism which is an aspect of the invention is based on recognizing and taking advantage of sensed patterns in cache misses resulting from operand calls. In an extremely elementary example, consider a sensed pattern in which three consecutive misses ABC are, in fact, successive operand addresses with D being the next successive address. This might take place, merely by way of example, in a data manipulation process calling for successively accessing successive rows in a single column of data. If this pattern is sensed, the likelihood that signal group D will also be accessed, and soon, is enhanced such that its prefetching into the cache memory unit 14 is in order. The fundamental principles of the cache miss prediction mechanism are set forth in the operational flow chart of FIG. 2. When a processor (or other system unit) asks for an operand, a determination is made as to whether or not the operand is currently resident in the cache. If so, there is a cache hit (i.e., no cache miss), the operand is sent to the requesting system unit and the next operand request is awaited. However, if there is a cache miss, the request is, in effect, redirected to the (much slower) main memory. Those skilled in the art will understand that the description to this point of FIG. 2 describes cache memory operation generally. In the context of the present invention, however, the address of the cache miss is meaningful. It is therefore placed at the top of a miss stack to be described in further detail below. The miss stack (which contains a history of the addresses of recent cache misses in consecutive order) is then examined to determine if a first of several patterns is present. This first pattern might be, merely by way of example, contiguous addresses for the recent cache misses. If the first pattern is not sensed, additional patterns are tried. Merely by way of example again, a second pattern might be recent cache misses calling for successive addresses situated two locations apart. So long as there is no pattern match, the process continues through the pattern repertoire. If there is no match when all patterns in the repertoire have been examined, the next cache miss is awaited to institute the process anew. However, if a pattern in the repertoire is detected, a predictive address is calculated from the information in the miss stack and from the sensed pattern. This predictive address is then employed to prefetch from main memory into cache the signal group identified by the predictive address. In the elementary example previously given, if a pattern is sensed in which consecutive operand cache miss operand addresses ABC are consecutive and contiguous, the value of the predictive address, D, will be C + 1. In order to optimize the statistical integrity of the miss stack, the predictive address itself may be placed at the top of the stack since it would (highly probably) itself have been the subject of a cache miss if it had not been prefetched in accordance with the invention. Since speed of operation is essential, the cache miss prediction mechanism may advantageously be embodied in a "hard wired" form (e.g., in a gate array) although firmware control is contemplated. Consider first a relatively simple hardwired implementation shown in FIG. 3. A miss stack 20 holds the sixteen most recent cache miss addresses, the oldest being identified as address P with entry onto the stack being made at the top. Four four-input electronic switches 21, 22, 23, 24 are driven in concert by a shift pattern signal via line 25 such that: in a first state, addresses A, B, C, D appear at to respective outputs of the switches; in a second state, addresses B, D, F, H appear at the outputs; in a third state, addresses C, F, I, L appear at the outputs; and in a fourth state, addresses D, H, L, P appear at the outputs. Subtraction circuits 26, 27, 28 are connected to receive as inputs the respective outputs of the electronic switches 21, 22, 23, 24 such that: the output from the subtraction circuit 26 is the output of the switch 21 minus the output of the switch 22; the output from the subtraction circuit 27 is the output of the switch 22 minus the output of the switch 23; and the output from the subtraction circuit 28 is the output of the switch 23 minus the output of the switch 24. The output from the subtraction circuit 26 is applied to one input of an adder circuit 31 which has its other input driven by the output of the electronic switch 21. In addition, the output from the subtraction circuit 26 is also applied to one input of a comparator circuit 29. The output from the subtraction circuit 27 is applied to the other input of the comparator circuit 29 and also to one input of another comparator circuit 30 which has its other input driven by the output of the subtraction circuit 28. The outputs from the comparator circuits 29, 30 are applied, respectively, to the two inputs of an AND-gate 32 which selectively issues a prefetch enable signal. Consider now the operation of the circuit shown in FIG. 3. As previously noted, miss stack 20 holds the last sixteen cache miss addresses, address A being the most recent. When the request for the signal group identified by address A results in a cache miss, circuit operation is instituted to search for a pattern among the addresses resident in the miss stack. The electronic switches 21, 22, 23, 24 are at their first state such that address A is passed through to the output of switch 21, address B appears at the output of switch 22, address C appears at the output of switch 23 and address D appears at the output of switch 24. If the differences between A and B, B and C, and C and D are not all equal, not all the outputs from the subtraction circuits 26, 27, 28 will be equal such that one or both the comparator circuits 29, 30 will issue a no compare; and AND-gate 32 will not be enabled, thus indicating a "no pattern match found" condition. The switches are then advanced to their second state in which addresses B, D, F, H appear at their respective outputs. Assume now that(B - D) = (D - F) = (F - H) ; i.e., a sequential pattern has been sensed in the address displacements. Consequently, both the comparators 29, 30 will issue compare signals to fully enable the AND-gate 32 and produce a prefetch enable signal. Simultaneously, the output from the adder circuit 31 will be the predictive address(B + (B - D)). It will be seen that this predictive address extends the sensed pattern and thus increases the probability that the prefetched signal group will be requested by the processor, thereby lowering the cache miss ratio. If a pattern had not have been sensed in the address combination BDFH, the electronic switches would have been advanced to their next state to examine the address combination CFIL and then on to the address combination DHLP if necessary. If no pattern was sensed, the circuit would await the next cache miss which will place a new entry at the top of the miss stack and push address P out the bottom of the stack before the pattern match search is again instituted. Consider now the somewhat more complex and powerful embodiment of the cache miss prediction mechanism illustrated in FIG. 4. Electronic switches 41, 42, 43, 44 receive at their respective inputs recent cache miss addresses as stored in the miss stack 40 in the exemplary arrangement shown. It will be noted that each of the electronic switches 41, 42, 43, 44 has eight inputs which can be sequentially selectively transferred to the single outputs under the influence of the shift pattern signal. It will also be noted that the miss stack 40 stores, in addition to the sixteen latest cache miss addresses A - P, three future entries WXY. Subtraction circuits 45, 46, 47 perform the same office as the corresponding subtraction circuits 26, 27, 28 of the FIG. 3 embodiment previously described. Similarly, adder circuit 48 corresponds to the adder circuit 31 previously described. Comparator circuit 49 receives the respective outputs of the subtraction circuits 45, 46, and its output is applied to one input of an AND-gate 38 which selectively issues the prefetch enable signal. Comparator circuit 50 receives the respective outputs of the subtraction circuits 46, 47, but, unlike its counterpart comparator 30 of the FIG. 3 embodiment, its output is applied to one input of an OR-gate 39 which has its other input driven by a reduce lookahead signal. The output of OR-gate 39 is coupled to the other input of AND-gate 38. With this arrangement, activation of the reduce lookahead signal enables OR-Gate 39 and partially enables AND-gate 38. The effect of applying the reduce lookahead signal is to compare only the outputs of the subtraction circuits 45, 46 in the comparator circuit 49 such that a compare fully enables the AND-gate 38 to issue the prefetch enable signal. This mode of operation may be useful, for example, when the patterns seem to be changing every few cache misses, and it favors the most recent examples. With the arrangement of FIG. 4, it is advantageous to try all the patterns within pattern groups (as represented by the "YES" response to the ">1 PATTERN GROUP?" query in the flow diagram of FIG. 2) even if there is a pattern match detected intermediate the process. This follows from the fact that more than one of the future entries WXY to the miss stack may be developed during a single pass through the pattern repertoire or even a subset of the pattern repertoire. With the specific implementation of FIG. 4 (which is only exemplary of many possible useful configurations), the following results are obtainable: SWITCH STATE PATTERN GOAL 0 ABCD W 1 ACEG X 2 ADGJ Y 3 BDFH W 4 BEHK X 5 CFIL W 6 CGKO X 7 DHLP W The goal states are searched in groups by switch state; i.e.: Group 1 includes switch states 0, 1, 2 and could result in filling future entries WXY; Group 2 includes states 3, 4 and could result in filling entries WX; Group 3 includes states 5, 6 and could also result in filling entries WX; and Group 4 includes state 7 and could result in filling entry W. When a goal state is reached that has been predicted, the search is halted for the current cache miss; i.e., it would not be desirable to replace an already developed predictive address W with a different predictive address W. Those skilled in the art will understand that the logic circuitry of FIGs. 3 and 4 is somewhat simplified since multiple binary digit information is presented as if it were single binary digit information. Thus, in practice, arrays of electronic switches, gates, etc. will actually be employed to handle the added dimension as may be necessary and entirely conventionally. Further, timing signals and logic for incorporating the cache miss prediction mechanism into a given data processing system environment will be those appropriate for that environment and will be the subject of straightforward logic design. The foregoing discussion relates to the invention disclosed and claimed in the above-referenced United States Patent No. 5,093,777 which forms an exemplary environment for the present invention. Attention is now directed to FIG. 5 which is a logic diagram of exemplary control apparatus for adaptively selectively enabling the cache prediction mechanism in accordance with the present invention. An OR-gate 71 is driven by "system reset" and "process switch" signals, and its output drives one input to another Or-gate 72. The output of the OR-gate 72 serves to reset the counters 61, 63 and the registers 64, 64', 65, 65', 67 and 68 in the circuit. The counter 61 drives a 100 count decoder 62 whose output is coupled to one input of an AND-gate AND-gate 73. The other input to the AND-gate 73 is driven by an "operand data request" signal which is also applied to an increment input of the counter 61. The output of the AND-gate 73 drives load inputs to the counter 63 and each of the registers 64, 64', 65 and 65' and to one input of AND-gate 75. An "operand cache hit" signal drives an increment input to presettable counter 63 whose output is applied to the input of register 64. In addition, "0" logic signals are present at the data inputs to counter 63. The instantaneous count held in counter 63 is applied to the data inputs of register A 64. A one-bit register 64', which can be preset to "1", serves as a validity indicator for register 64. The instantaneous count held in register 64 is applied to the data inputs of register B 65, and a one-bit register 65' serves as a validity indicator for register 65. The state of one-bit register 65' is applied to the second input of AND-gate 75 which drives load inputs to one-bit registers 67 and 68. The instantaneous counts in the registers 64 and 65 are applied to the inputs of a comparator 66 which issues a "1" output only when the count in register A 64 is equal to or greater than the count in register B 65. This output signal drives an inverter 74 which drives one-bit register C 67. The state of one-bit register 67 is applied to the input of one-bit register D 68 and also to one input of AND-gate 76. The state of one-bit register 68 is also applied to an input of AND-gate 76. Preferably, but not necessarily, AND-gate 76 has a third input driven by a "mode" signal which may be supplied by the process in execution. Optional circuitry which may be employed includes hit ratio register 69 which may be loaded with a predetermined "hit ratio threshold" supplied by a new process. The value resident in the hit ratio register 69 is applied to one input of a comparator 70 which has its other input driven by the instantaneous count in register A 64 such that the comparator 70 issues a logic "1" only when A is greater than or equal to the hit ratio threshold. The output from comparator 70 is applied to one input of an AND-gate 78 which receives at its other input the logical inversion of the "mode" signal. The output from the AND-gates 76 and 78 are applied to the two inputs of an OR-gate 77 which issues a "disable miss prediction" signal when it is enabled. Consider now the operation of the apparatus shown in FIG. 5. Either a "system reset" or a "process switch" will reset the counters 61, 63 and the registers 64, 64', 65, 65', 67 and 68 to initialize the adaptive circuitry. The counter 61 and the 100 decoder 62 cooperate to enable the AND-gate 73 every 100 times the "operand data request" signal increments the counter 61. This causes the counter 63 to load a count of zero as it passes along its just previous count to register A 64. Register 64 passes its previous count to register B 65. One-bit register A' 64' is loaded with a "1", and its previous state is passed to register B' 65'. That previous state will only be a "0" if a system reset or process switch took place just prior to the immediately previous count to 100 by the counter 61 took place. The counter 63 is now incremented each time an operand cache hit takes place such that it accumulates, over the next 100 operand data requests, the short term cache hit ratio. In the meantime, comparator 66 compares the hit ratio now held in register A 64 to the ratio now held in register B 65 to determine if A is greater than or equal to B; i.e., if the most recent ratio is as good or better than the second most recent ratio. Hence, an upward (or flat) or downward trend is sensed. If an upward trend is sensed, the output from the comparator 66 is a "1" which is inverted by the inverter 74 and applied as a logic "0" to the input of one-bit register C 67. This state will be loaded into the register 67 when the AND-gate 73 is next enabled if the state of the one-bit register B' 65' is "1"; i.e., if the AND-gate 75 is fully enabled. This would be the case two cycles following the occurrence of a system reset or process switch since the "1" applied to the one-bit register A' 64' would have flushed out the "0"s placed therein and in the one-bit register B' 65' by the OR-gate 72. Thus, it will be seen that the purpose of the registers 64' and 65' is to lock out invalid hit ratio information which would otherwise be generated immediately following a system reset or process switch. When the state of the comparator 66, inverted through the inverter 74, is loaded into the one-bit register 67, the previous state of the register 67 is loaded into the one-bit register 68. As a result, if the hit ratio trend is down for two consecutive cycles such that the one-bit registers 67, 68 both contain "1"s, and assuming the "mode" signal is "1", then the AND-gate 76 is enabled to enable the OR-gate 77 which therefore issues the "disable miss prediction" signal. This signal remains until a subsequent comparison of the contents of the registers 64, 65 again indicates an upward (or flat) trend in the short term hit ratio. The optional use of the "mode" signal permits selective overriding of the adaptive apparatus by establishing a predetermined hit ratio threshold at which, notwithstanding the presence of an upward trend in the hit ratio, the "disable miss prediction" signal is issued. This may be an appropriate operating procedure when it is known that a new process would not benefit from, or whose performance may be detrimentally affected by, the use of the adaptive circuit following cache "in-rush". In the early stages of the execution of a new process, the new process switches the "mode" signal to "0" to partially enable the AND-gate 78 and to disable the AND-gate 76 to thereby lock out the decision section of the adaptive circuit and also causes the predetermined hit ratio to be loaded into the register 69. Under these conditions, a short term hit ratio is still being developed in the register A 64, and this hit ratio is compared to the hit ratio threshold held in the register 69 by the comparator 70. As long as the actual hit ratio is less than the hit ratio threshold, the comparator 70 output is "0". However, when the hit ratio reaches or exceeds the hit ratio threshold, the comparator 70 output switches to "1" to fully enable the AND-gate 78 to enable the OR-gate 77 which issues the "disable miss prediction" signal. It will be noted that, if the short term hit ratio again falls below the hit ratio threshold, the "disable miss prediction" signal will switch back to "0", thus permitting the cache miss prediction mechanism to resume operation.

Claims: Method for predicting cache request addresses for prefetching signal groups from a main memory (13) into a cache memory (12) in a data processing system comprising a central processing unit (14), an address translation apparatus (16), a cache memory (12), a system interface (11), a main memory (13) and user units (15), wherein said cache memory (12) is repeatedly interrogated to determine whether an address corresponding to a cache request address is stored therein, said data processing system including a stack (20) for storing cache miss addresses, said method including the steps of: upon the occurrence of a cache miss when the cache memory (12) is interrogated, entering the cache request address corresponding to said miss into said stack (20); examining the cache request addresses in said stack (20) to determine whether an address pattern can be found by examining a set of entries (A .... P) in said stack (20) on equal differences between the contents of consecutive entries of the set; if a pattern match is determined, generating a predictive address based on said pattern and at least one of said cache request addresses present in said stack (20), said predictive address being used to obtain a signal group stored in said main memory (13) and to write said signal group under said predictive address into the cache memory (12); characterized in that short term operand cache hit ratios of said cache memory (12) are repetitively determined; pairs of the successively determined short term operand cache hit ratios are compared to establish a cache hit ratio trend which can be upward, flat or downward; and when the short term cache hit ratio trend is upward or flat, the operand cache miss prediction is in effect, whereas when the short term cache hit ratio trend is downward, the operand cache miss prediction is disabled. The method of claim 1, wherein the operand cache miss prediction is also disabled when said short term operand hit ratio reaches a predetermined value. The method of claim 2, wherein said predetermined value is determined by the process commencing execution following a process change. The method of claim 1, wherein each of said short term operand hit ratios is determined by counting the number of operand cache hits occurring during an interval in which a predetermined number of operands are requested from said cache memory (12). Apparatus for predicting cache request addresses for prefetching signal groups from a main memory (13) into a cache memory (12) in a data processing system, which comprises: a central processing unit (14), an address translation apparatus (16), a cache memory (12), a system interface (11), a main memory (13), and user units (15), wherein said cache memory (12) is repeatedly interrogated to determine whether an address corresponding to a cache request address is stored therein; said data processing system further including: a stack (20) for storing cache miss addresses, a plurality of electronic switch means (81-84) each having a plurality of address inputs and outputs, said plurality of addresses (A ... P) stored in said stack (20) being coupled to said electronic switch means inputs in predetermined orders (AAABBCCD, ... DGJHKLOP); means to establish at said plurality of electronic switch means outputs (61, 62, 63, 64) predetermined combinations of said plurality of addresses; at least two subtraction units (26-28) coupled to receive a unique pair of addresses from said switch means outputs (61-64) and adapted to issue a displacement value representing the difference therebetween; at least a first comparator (49, 50) coupled to receive a pair of outputs from a corresponding pair of said subtraction units (45-47) and responsive thereto for issuing a compare signal if there is a compare condition; and predictive address development means (48) adapted to combine one of said addresses appearing at one of said switch means outputs (61) and said displacement value appearing at one of said subtraction units (45) to obtain a predictive address, characterized in that the apparatus further comprises: hit ratios determination means (61-63, 71-73) for repetitively determining the short term operand cache hit ratios (A, B) of said cache memory (12); comparison means (64-66) for comparing pairs of successively determined short term operand cache hit ratios (A, B) to establish a cache hit ratio trend which can be upward (A>B), flat (A=B) or downward (A<B); and disabling means (67, 68, 74-78) responsive to a downward operand cache hit ratio trend for disabling the operand cache miss prediction. The apparatus of claim 5, wherein the operand cache miss prediction is also disabled when said short term operand hit ratio (A) reaches a predetermined value (HRT). The apparatus of claim 6, wherein said predetermined value (HRT) is determined by the process commencing execution following a process change. The apparatus of claim 5, wherein said hit ratios determination means (61-63, 71-73) generate numbers which represent successive short term operand hit ratios of said cache memory (12). The apparatus of claim 5, characterized in that said hit ratios determination means comprise : a first counter means (61, 62) for counting operand data requests, and a second counter means (63) for counting operand cache hits; and that said comparison means comprise: a first register (64) for storing a first operand cache hit ratio (A), a second register (65) for storing a second operand cache hit ratio (B), and a first comparator (66) for comparing the contents of said first and second registers (64, 65) to determine whether the count in the first register (64) is greater, equal or smaller than the count in the second register (65), whereupon if a downward trend in said short term operand hit ratios is determined at the output terminal of said first comparator (66), the said disabling means (67, 68, 74-77) generate a control signal which disables the cache miss prediction. The apparatus of claim 6 or claim 9, characterized by a hit ratio register means (69) which upon process change is loaded with said predetermined value (HRT); and a second comparator (70) which compares the contents of said hit ratio register means (69) with the contents of said first register (64) to determine whether said short term operand hit ratio (A) has reached said predetermined value (HRT) or not, whereupon if the said predetermined value (HRT) has been reached, the said third means (78) generate a control signal which disables the cache miss prediction.

Inventors: RYAN CHARLES P, RYAN, CHARLES P.
Applicants: BULL HN INFORMATION SYST, BULL HN INFORMATION SYSTEMS INC.
Application year: 1993
Main classification: G06F12
IPC codes: G06F12