Semiconductor device

Abstract: A semiconductor device comprising a main circuit having a p-channel MOSFET formed on the surface of the substrate and an n-channel MOSFET formed on the p-type well region which is formed on the n-type Si substrate (chip), an input/output (I/O) circuit formed on the substrate, and a substrate bias generating circuit formed on the substrate, characterized by controlling the substrate bias generating circuit via the I/O circuit, and varying a bias supplied to the substrate and the p-type well region, in accordance with the operation mode of the main circuit.

Description: This invention relates to a semiconductor device, and more particularly to a semiconductor device wherein an integrated circuit including MOSFETs allows a potential of its substrate having the device to be varied. An integrated circuit includes many MOSFETs. ON-OFF switching characteristics of a transistor depend on a threshold voltage of each MOSFET. The threshold voltage depends on limitations of the integrated circuit such as the speed, the standby current, etc. i.e. the current drivability of the MOSFET or the leakage current of the MOSFET when the gate voltage is 0V. The threshold voltage of the MOSFET is generally determined by the thickness of a gate oxide film or the impurity concentration in the Si substrate under the gate oxide film. In general, in order to increase the threshold voltage, it is merely necessary to increase the thickness of the gate oxide film or the impurity concentration in the Si substrate under the gate oxide film. On the other hand, in order to lower the threshold voltage, it is necessary to reduce the thickness of the gate oxide film and the impurity concentration in the Si substrate under the gate oxide film. However, if the threshold voltage is increased, the current drivability of the MOSFET fails while the leakage current is restricted. On the other hand, if the threshold voltage is decreased, the current drivability of the MOSFET increases and at the same time the leakage current increases. As explained above, when the threshold voltage of the MOSFET is set, the leakage current and the current drivability are set by themselves. If the MOSFET is scaled down, the thickness of the gate oxide thickness must be reduced small to prevent the punch-through and the short channel effect. In this case, a preferable threshold voltage may not be obtained unless the impurity concentration is excessively increased. There is a manner proposed to solve this problem, such as supplying a substrate bias to a portion of the integrated circuit or all the portions thereof, and this is accomplished mainly in a DRAM. Since the substrate bias causes the threshold voltage of the MOSFET to be increased, the leakage current can be lowered even at the time when the impurity concentration is slightly low. Then, it has been proposed and accomplished to vary the impurity concentration in the Si substrate under the gate oxide film of the MOSFET in the integrated circuit in accordance with an area of the substrate, to set the threshold voltage of the MOSFET to be small for the purpose of increasing the current drivability, or to set the threshold voltage of the MOSFET to be great for the purpose of increasing the leakage current. This improvement manner is effective when the concentration is low or when the operating voltage is under 5V. However, if the degree of the integration of MOSFET is increased, difficulty in the processes is also increased, since preparation manners for the high-speed operation is not consistent with that for the low standby. If the operating voltage is lowered, a rate of the threshold voltage to the operating voltage is increased to keep off-leakage current, and thus the difficulty is further increased. It is analytically known that the threshold voltage should be under 0.3V to maintain the high-speed operation, i.e. the threshold voltage should be approximately under 20% of the operating voltage, for example when the operating voltage is 1.5V. On the other hand, in order to make the standby current of an integrated circuit having more than 300,000 logic gates approximately under 10 µA, the threshold voltage should be higher than 0.6V. If operating voltage is different, since the threshold voltage for keeping high-speed operation is different, for example, the threshold voltage of 0.6V is enough for high-speed operation when an operating voltage is 3V, however the threshold voltage less than 0.3V is required when an operating voltage is 1.5V. Therefore it is very difficult to set both a proper threshold voltage and a low standby current in the conventional manner. As described above, in the semiconductor device having the MOSFETs, only one threshold voltage value can be set by one MOSFET in the integrated circuit. Setting both the high-speed operation of the integrated circuit and the low standby current or determining the optimum threshold voltage at which the operating voltages are different is difficult in prior art. US-A-4 961 007 discloses a substrate bias potential generator of a semiconductor integrated circuit device and a corresponding generating method, where the generator includes first and second substrate bias generating circuits which operate alternatively according to the potential of the substrate. The substrate potential is measured by a substrate potential detector. Therefore, this document is basically directed towards a substrate potential control loop circuit. DE-A-30 09 447 deals with an integrated CMOS semiconductor component containing p-MOS and n-MOS field effect transistors. This document shows a regulation circuit for the sum of the threshold voltages in a CMOS component. EP-A-0 469 587 A3 discloses a circuit for providing a bias to the substrate of a dynamic memory device, including a first pump and oscillator to provide a substrate bias in a memory stand-by mode, and a second power pump and oscillator to provide a substrate bias when the memory is active. A low power oscillator and pump are activated upon power up and remain active throughout until the power of the device is switched off, whereas a high power oscillator and pump are only activated when the device becomes active. EP-A-0 222 472 A3 discloses a complementary semiconductor device with a substrate bias voltage generator, where the semiconductor device has a substrate of a first conductivity type including a well of a second conductivity type opposite to the first conductivity type and the device comprises a bias potential generating circuit and a potential detecting circuit for detecting the substrate potential. The substrate potential is adjusted according to the detected potential. The object of this invention is to provide a semiconductor device wherein optimum threshold voltages of MOSFET can be set by an operating mode or an operating voltage such as the high-speed performance of MOSFET is considered or when a low power dissipation is considered. The object of the invention is solved by a device and method according to the independent claims appended to the description. Preferred embodiments are contained in the dependent claims. According to the invention, the substrate bias in the main circuit is varied in accordance with the operation mode or the operating voltage of the main circuit. Therefore, both the high-speed performance and the low power dissipation or the determination of the optimum threshold voltage at different operating voltage can be achieved. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the first embodiment; Fig. 2 is a sectional view showing an element structure according to the first embodiment; Fig. 3 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the second embodiment; Fig. 4 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the third embodiment; Fig. 5 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the fourth embodiment; Fig. 6 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the fifth embodiment; Fig. 7 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the sixth embodiment; and Fig. 8 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the seventh embodiment. This invention will be explained below in detail with reference to embodiments shown in the drawings. Fig. 1 is a schematic block diagram showing a circuit of a semiconductor device according to the first embodiment of this invention. An LSI chip 1 has an input/output (I/O) circuit 2, a substrate bias generating circuit 3, and a main circuit 4. The LSI chip 1 is in the CMOS structure in which an n-type substrate has a p-type well. The I/O circuit 2 performs the input/output of the data in/from the outside. The substrate bias generating circuit 3 generates potentials of, for example, both -0.5V and 0.5V, on the basis of a signal 6 supplied through the I/O circuit 2. The main circuit 4 comprises p-channel and n-channel MOSFETs. Fig. 2 is a cross-sectional view showing an element structure of the LSI chip 1, and particularly a fundamental structure of the main circuit 4. A p-type well (second conductive well) 31 is formed on a portion of a surface layer of an n-type Si substrate (first conductive semiconductor substrate) 21. Formed on the surface of the substrate 21 is a p + -type source-drain region 22 and a p-channel MOSFET (first MOSFET) consisting of a gate oxide film 23 and a gate electrode 24, and formed on the surface of a p-type well 31 is an n + -type source-drain region 32 and an n-channel MOSFET (second MOSFET) consisting of a gate oxide film 33 and a gate electrode 34. An element separating insulator 41 is formed between the p-channel MOSFET and the n-channel MOSFET. Circuit operations of a semiconductor device according to this invention having the above structure will be explained. The LSI chip 1 includes the n-channel MOSFET (hereinafter called "nMOS") and the p-channel MOSFET (hereinafter called "pMOS") which have a dimension of 0.5 µm at minimum. The thickness of the gate oxide film is 11 nm, and the peak value of impurity concentration is approximately 1.5 × 10 17 cm -3 . When the substrate bias is 0V, the threshold voltage of the nMOS is 0.3V and the threshold voltage of the pMOS is -0.3V. When the LSI chip 1 is in the standby mode, a potential of -0.5V is generated at the p-type well 31 having the nMOS and a potential of 0.5V is generated at the n-type substrate 21 having the pMOS, through the paths of a signal 7 and a signal 8. Then, the threshold voltage of the nMOS is varied to approximately 0.6V, and the threshold voltage of the pMOS is varied to approximately -0.6V. Therefore, the subthreshold leakage current of the MOSFET is approximately 1pA/µm, and if the total length of width of transistors included in the LSI chip 1 is approximately 10m, a very small standby current of 10 µA can be realized at an entire LSI. On the other hand, since no substrate bias is generated during the operation of the MOSFET, the substrate bias is 0V, and since the threshold voltage of the nMOS is 0.3V and the threshold voltage of the pMOS is -0.3V, no performance of the LSI chip is degraded at all. Another circuit operation of the semiconductor device according to this invention will be explained below. In an integrated circuit similar to the above circuit, when the substrate bias is 0V, the threshold voltage of the nMOS is 0.6V and the threshold voltage of the pMOS is -0.6V. At this time, the subthreshold leakage current of the MOSFET is approximately 1pA/µm. If the total length of the width of transistors included in the LSI chip 1 is approximately 10m, a very small standby current of 10 µA can be realized at the entire LSI chip. During the operations, a potential of 0.3V is generated at the p-type well 31 having the nMOS and a potential of -0.3V is generated at the n-type substrate 21 having the pMOS, through the paths of the signals 7 and 8. Then, the threshold voltage of the nMOS is varied to approximately 0.3V and the threshold voltage of the pMOS is varied to approximately -0.3V, and consequently no performance of the LSI chip is degraded at all. As described above, according to the semiconductor device of this invention, the substrate bias generating circuit 3 is formed together with the main circuit 4 in the LSI chip 1, and the substrate bias is variably set in accordance with the operation mode of the MOSFET. Therefore, the threshold voltage can be set low when a high-speed performance is considered important, and it can be set high when low power dissipation at the standby is considered important. Accordingly, the current drivability during the operations can be developed and at the same time the leakage current at the standby can be reduced, i.e. both the high-speed performance and the low power dissipation can be achieved without complicated processes. This advantage is effective particularly when the operating voltage is lowered and the integration degree is increased. In the first embodiment, the substrate bias is varied at operation and standby as an operating mode. The present invention is not limited to this embodiment, the substrate bias may be varied by a high-speed mode and a low-speed mode at operation. The other embodiments of the semiconductor device of this invention will be explained with reference to Figs. 3 to 5. In the figures, the portions as shown in Fig. 1 have the same reference numerals, and their detailed explanations are omitted. Fig. 3 is a schematic block diagram showing the circuit configuration of the semiconductor device according to the second embodiment. In the semiconductor device of the third embodiment, an ON-OFF operation of the substrate bias generating circuit 3 is not performed by the I/O signal, but by a control signal 9 from the outside. Fig. 4 is a schematic block diagram showing the circuit configuration of the semiconductor device according to the third embodiment. In the semiconductor device of the fourth embodiment, the substrate bias is not simultaneously supplied to the p-type well having the nMOS and the n-type substrate having the pMOS, but the bias voltage is supplied to either the p-type well or the substrate through the path of a signal 10. In the fourth embodiment, for example, a potential of -0.5V may be supplied to only the p-type well and conversely a potential of 0.5V may be supplied to only the n-type substrate. Fig. 5 is a schematic block diagram showing the circuit configuration of the semiconductor device according to the fourth embodiment. In the semiconductor device of the fourth embodiment, a bias voltage is supplied directly from the outside to both the n-type substrate and the p-type well, or either the n-type substrate or the p-type well, to control the bias in the system. Fig. 6 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the fifth embodiment. In the semiconductor device of the fifth embodiment, the I/O circuit 2 does not receive the outputs 7 and 8 from the substrate bias generating circuit 3, thus the I/O circuit 2 controls only the main circuit 4 not to control the substrate bias. The same advantage as obtained in the semiconductor device of the first embodiment can be obtained in the semiconductor devices of the second, third and fifth embodiments. The sixth embodiment of the present invention will be explained with reference to Fig. 7. Fig. 7 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the sixth embodiment. In Fig. 7, the semiconductor device comprises an LSI chip 13, an input/output (I/O) circuit 14, a detection circuit 15, a substrate bias generating circuit 16, and a main circuit 18. The LSI chip 13 is in the CMOS structure in which an n-type substrate has a p-type well. The I/O circuit 14 performs the input/output of the data in/from the outside. The detection circuit 15 detects the input voltage to the LSI chip 13. The substrate bias generating circuit 3 generates potentials of, for example, -1.5V and 1.5V, on the basis of a signal 17 supplied through the detection circuit 15. The main circuit 18 comprises p-channel and n-channel MOSFETs. The LSI chip 13 has the I/O circuit 14, the detection circuit 15, the substrate bias circuit 16 and the main circuit. The cross-sectional view showing fundamental structure of the LSI chip 13 is about the same as the first embodiment and the detail explanation will be omitted. The operation of the circuit will be explained. The threshold voltage of the nMOS is set to 0.1V and that of pMOS to -0.1V when the substrate bias is 0V. The detection circuit 15 outputs the H-level voltage when for example the 3V is inputted to the LSI chip 13. This H-level voltage is inputted to the substrate bias generating circuit 16 through the pass of the signal 17. The substrate bias generating circuit 16 generates the potential of -1.5V to the p-type well 31 on which the nMOS is formed and the potential of 1.5V to the n-type substrate 21 on which the pMOS is formed through the pass of the signal 19 and 20 on the basis of the signal 17. The threshold voltage of the nMOS is set to approximately 0.6V and the threshold voltage of the pMOS is set to approximately -0.6V. Therefore, the high-speed performance and the low power dissipation can be achieved at 3V operation. The detection circuit 15 outputs the L-level voltage when for example the 1.5V is inputted to the LSI chip 13. This L-level voltage is inputted to the substrate bias generating circuit 16 through the pass of the signal 17. The substrate bias generating circuit 16 generates the potential of -0.7V to the p-type well 31 on which the nMOS is formed and the potential of 0.7V to the n-type substrate 21 on which the pMOS is formed through the pass of the signal 19 and 20 on the basis of the signal 17. The threshold voltage of the nMOS is set to approximately 0.3V and the threshold voltage of the pMOS is set to approximately -0.3V. Therefore, the high-speed performance and the low power dissipation can be achieved at 1.5V operation. As described above, since the appropriate threshold voltage being equal to or lower than 15 to 20% of the operating voltage can be achieved by comprising the detection circuit, high-speed operation can be assured in wide range of the voltage. Another embodiment of the circuit operation of the sixth embodiment will be explained. The threshold voltage of the nMOS is set to 0.5V and that of pMOS to -0.5V when the substrate bias is 0V. The detection circuit 15 outputs the H-level voltage when for example the 5V is inputted to the LSI chip 13. This H-level voltage is inputted to the substrate bias generating circuit 16 through the pass of the signal 17. The substrate bias generating circuit 16 generates the potential of -0.8V to the p-type well 31 on which the nMOS is formed and the potential of 0.8V to the n-type substrate 21 on which the pMOS is formed through the pass of the signal 19 and 20 on the basis of the signal 17. The threshold voltage of the nMOS is set to approximately 1V and the threshold voltage of the pMOS is set to approximately -1V. Therefore, the high-speed performance and the low power dissipation can be achieved at 5V operation. The detection circuit 15 outputs the L-level voltage when for example the 3V is inputted to the LSI chip 13. This L-level voltage is inputted to the substrate bias generating circuit 16 through the pass of the signal 17. The substrate bias generating circuit 16 does not generate the substrate bias to be set to 0V, the threshold voltage of the nMOS is 0.5V and the threshold voltage of the pMOS is -0.5V. Therefore, the high-speed performance and the low power dissipation can be achieved at 3V operation. As described above, an inhibition of leakage current due to the punch through caused by increasing the voltage and low power dissipation can be achieved by generating the substrate bias to raise the threshold voltage. In the present invention, LSI chip 13 comprises the main circuit 18, the substrate bias generating circuit 16 and the detection circuit 15, and the substrate bias is set according to the operating voltage of the main circuit 18. Therefore, the determination of the threshold voltage when high-speed performance at the different operating voltage or low power dissipation is considered, can be automatically achieved by the chips which are made in the same process condition. The seventh embodiment of the present invention will be explained with reference to Fig. 8. Fig. 8 is a schematic block diagram showing a circuit configuration of a semiconductor device according to the seventh embodiment. In Fig. 8, the semiconductor device comprises an LSI chip 50, an input/output (I/O) circuit 51, a voltage down converter circuit 52, a detection circuit 53, a substrate bias generating circuit 54, and a main circuit 56. The LSI chip 50 is in the CMOS structure in which an n-type substrate has a p-type well. The I/O circuit 51 performs the input/output of the data in/from the outside. The voltage down converter circuit 52 steps down the voltage inputted to the LSI chip 50. The detection circuit 53 detects the voltage outputted from the voltage down converter circuit 52. The substrate bias generating circuit 54 generates potentials of, for example, -1.5V and 1.5V, on the basis of a signal 55 supplied through the detection circuit 53. The main circuit 56 comprises p-channel and n-channel MOSFETs, and has high-voltage operating unit and low voltage operating unit. The LSI chip 50 has the I/O circuit 51, the voltage down converter circuit 52, the detection circuit 53, the substrate bias circuit 54 and the main circuit 56. In this embodiment, the main circuit unit 56 is divided to the high-voltage operating unit and the low-voltage operating unit, and only the substrate bias of the low-voltage operating unit is controlled. For example, the detection circuit 53 detects the voltage operating the low-voltage operating unit and generates the H- or L-level signal 55 in corresponding to the detected value. The substrate bias generating circuit 54 generates the substrate bias through the pass of the signals 55 and 57 when receiving H-level signal. The substrate bias generating circuit 54 does not generate the substrate bias when receiving L-level signal. As described above, the same advantage as the sixth embodiment can be obtained by controlling the substrate bias using operating voltage of the low-voltage operating unit. The substrate bias can be controlled by the operating mode of the low-voltage operating unit based on the signal from the I/O circuit 51. In this case, the same advantage as the first embodiment can be obtained. Especially, it is very effective to control the substrate bias of the low-voltage operating unit, since it is difficult to achieve both high-speed performance and low power dissipation when operating voltage is lowered. The detection circuit 53 is not always necessary when the substrate bias is controlled in accordance with the operating mode. As described above, in this embodiment, the LSI chip 50 comprises the main circuit 56, the substrate bias generating circuit 54, the voltage down converter circuit 52 and the detection circuit 53, and the substrate bias of only the low-voltage operating unit is set to be variable. In the low-voltage operating unit the optimum threshold voltage can be obtained. In addition, the second embodiment to the sixth embodiment can be applied to the seventh embodiment and eighth embodiment the same as the first embodiment. This invention is not limited to each of the above embodiments. The n-type substrate is used in each embodiment, but a p-type Si substrate may be used. Further, a semiconductor other than Si can be used as a substrate material. In the above embodiments, the semiconductor device is in the CMOS-type well structure in which there is the p-type well at the n-type substrate. Of course, it can be in the CMOS-type well structure in which there is the n-type well at the p-type substrate, which does not depend on the substrate type. It can be applied to a CMOS-type LSI chip, an nMOS-type or pMOS-type integrated circuit, and further a Bi CMOS-type integrated circuit combining the MOS with the bipolar. There may be a manner that the substrate bias circuit is worked to make the threshold voltage of the MOSFET high, when the ability is not considered important, but the power dissipation is considered important during the operations, while the substrate bias generating circuit is cut off to make the threshold voltage of the MOSFET low when the ability is considered more important.

Claims: Method for varying a threshold voltage of a semiconductor device containing n-channel and p-channel MOSFETs according to the operating mode or voltage of the device, characterized by increasing the absolute value of the threshold voltage of the MOSFETs in the stand-by mode of the semiconductor device by generating a negative potential at the p-type substrate of the n-channel MOSFETs and a positive potential at the n-type substrate of the p-channel MOSFETs; and/or decreasing the absolute value of the threshold voltage of the MOSFETs in the active mode of the semiconductor device by generating a positive potential of the p-type substrate of the n-channel MOSFETs and a negative potential at the n-type substrate of the p-channel MOSFETs. A semiconductor device for carrying out the method of claim 1, comprising a main circuit (4, 18, 50); an input/output-circuit (2, 14, 51) for performing the input/output of data into/from the main circuit from/to the outside; a substrate bias generating circuit (3, 16, 54) for varying the substrate bias in the main circuit (4, 18, 50) in accordance with the operating mode or the operating voltage of the main circuit (4, 18, 50), where said substrate bias generating circuit (3, 16, 54) is connected to said main circuit (4, 18, 50) and said input/output-circuit (2, 14, 51), and where the main circuit (4, 18, 50), the input/output-circuit (2, 14, 51) and the substrate bias generating circuit (3, 16, 54) are all part of an LSI chip (1, 13, 50) in the CMOS structure having a semiconductor substrate of one conductivity type and wells of the opposite conductivity type. A semiconductor device according to claim 2, characterized by said substrate bias generating circuit (3, 16, 54) having means for increasing the absolute value of the threshold voltage of the MOSFETs in the stand-by mode of the semiconductor device by generating a negative potential at the p-type substrate of the n-channel MOSFETs and a positive potential at the n-type substrate of the p-channel MOSFETs; and/or for decreasing the absolute value of the threshold voltage of the MOSFETs in the active mode of the semiconductor device by generating a positive potential of the p-type substrate of the n-channel MOSFETs and a negative potential at the n-type substrate of the p-channel MOSFETs. A semiconductor device according to claim 2 or 3, characterized in that said bias generating circuit (3, 16, 54) is controlled by a signal from an external device of the semiconductor substrate of said LSI chip (1, 13, 50). A semiconductor device according to one of claims 2 to 4, characterized by further comprising a detection circuit (15, 53) which is mounted on the semiconductor substrate of said LSI chip (1, 13, 50), for detecting a value of an operation voltage of said main circuit (4, 18, 50) and for controlling said substrate bias generating circuit (3, 16, 54).

Inventors: KAKUMU MASAKAZU, NOGAMI KAZUTAKA, SATOH YUKI, KAKUMU, MASAKAZU, NOGAMI, KAZUTAKA, SATOH, YUKI, Kakumu, Masakazu, c/o Intellectual Property Div., Nogami, Kazutaka, c/o Intellectual Property Div., Satoh, Yuki, c/o Intellectual Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: G05F3
IPC codes: G05F3