EFFICIENT CRC REMAINDER COEFFICIENT GENERATION AND CHECKING DEVICE AND METHOD

Abstract: Various parallel CRC remainder coefficient generation devices (100, 200, 300, 400, 500, 600, 700) and methods (1100, 1200) are described for providing efficient error detection in various digital data communication systems (800, 900, 1000). A K-bit CRC remainder is calculated from m bits at a time, where m can be less than, equal to, or greater than K, and where the processing of each of the m bits requires a total of j K-bit table look-ups into a total of j tables (410, 412, 414, 516, 518, 520, 522, 616, 614, 712, 714) of 2<b> entries each, where m = jb. Also required are one m-bit exclusive-or operation (208, 306, 506, 608, 706), a total of (j-1)K-bit exclusive-or operations (422, 532, 626, 628, 720), and one (K-m)-bit exclusive-or operation (216, 632) if m < K. A 16-bit CRC using the new method can be implemented on a 16-bit DSP processor.

Description: EFFICIENT CRC REMAINDER COEFFICIENT GENERATION AND CHECKING DEVICE AND METHOD Field of the Invention This invention relates generally to digital communication error detection and, more particularly, to a cyclic redundancy checking (CRC) device and method for error- detection in a digital data communication system. Background In a digital data communication system a receiver may receive transmitted data signals that contain errors. A number of factors, such as attenuation of signals, transmission line loss, magnetic field changes, and noise may cause such errors. Various error detection methods have been developed to check received digital data for errors. Linear systematic cyclic codes, commonly known as cyclic redundancy (CRC) codes are typically used to provide error detection capability at various network layers of modern data communications networks. CRC remainder coefficient generation and checking devices are implemented both in hardware and in software. Typical hardware implementations use serial shifter register schemes wherein feedback shift registers perform a long division of polynomials one bit at a time. To improve throughput, octet algorithms that handle one 8 bit-byte at a time have been developed. These octet algorithms are realized in both hardware and software. However, error processing utilizing CRC computations has a high degree of computational complexity, and thus can have a significant impact on the performance or cost of a digital data communication system. For example, in one application, 1/3 of the processing available from a DSP56156 processor is consumed by CRC computation. Thus, there is a need for an efficient CRC computation device and method that reduces the complexity and processing requirements for CRC computation in a digital data communication system. Summary of the Invention Described is a cyclic redundancy check (CRC) remainder coefficient generator, and a method for utilizing the generator, in a CRC circuit for generating a plurality of CRC remainder coefficients for an (n+m) bit frame utilizing a first input of data for a plurality of m coefficients representing a last m bits of an (n+m) bit frame (n, m are positive integers, m > 1 ; K is a degree of a CRC generating polynomial) and a second input of data for a plurality of K previously calculated CRC remainder coefficients of a first n bits of the frame. The generator includes at least a CRC circuit combining unit and a CRC circuit conversion unit. The CRC circuit combining unit is operably coupled to receive a preselected portion of the first input data and a preselected portion of the second input data, and substantially performs bitwise modulo-two addition of the preselected portion of the first input data and the preselected portion of second input data to provide adjusted coefficients. The CRC circuit conversion unit is operably coupled at least to the CRC circuit combining unit, and comprises a plurality (more than one) of look-up tables and substantially at least a first EXCLUSIVE-OR circuit, for utilizing at least the plurality of adjusted coefficients to provide a plurality of CRC remainder coefficients for the (n+m) bit frame. The method of the present invention implements the generator as described above, i.e., utilizing at least the CRC circuit combining unit and the CRC circuit conversion unit, to provide a plurality of CRC remainder coefficients for the (n+m) bit frame. Brief Descriptions of the Drawings FIG. 1 is a block diagram of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. FIG. 2 is a block diagram of a first embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein K is a length of the CRC. FIG. 3 is a block diagram of a second embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m = K. FIG. 4 is a block diagram of an embodiment of a remainder conversion unit (RCU) in accordance with the present invention, wherein m = bj and where b and j are a positive integers. FIG. 5 is a block diagram of a fourth embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m = K = 32, j = 4, and b = 8. FIG. 6 is a block diagram of a fifth embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein K = 32, m = 16, j = 2, and b = 8. FIG. 7 is a block diagram of a seventh embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m = K = 16, j = 2, and b = 8. FIG. 8 is a block diagram of a point-to-point communication network system utilizing a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. FIG. 9 is a block diagram of a multipoint communication network system utilizing a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. FIG. 10 is a block diagram of a mixed communication network system utilizing a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. FIG. 1 1 is a flow chart setting forth steps in accordance with a first implementation of the method of the present invention. FIG. 12 is a flow chart setting forth steps in accordance with a second implementation of the method of the present invention. FIG. 13 is a block diagram of an embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m > K. Detailed Description of a Preferred Embodiment The present invention is described below, with a description of its application to a digital transmission system in general. Then, special cases are described. A frame is a block of data that is transmitted or received in a digital data system. Cyclic code error-detection methods typically divide a data message as a polynomial d(x) by a predetermined generating polynomial g(x) to provide a quotient polynomial q(x) and a remainder polynomial r(x) such that: d(x) = q(x) * g(x) + r(x). The remainder r(x) is the cyclic redundancy check (CRC) and may be, for example, 16 bits in length (two 8 bit bytes). The CRC is appended to the block of data to be transmitted, and the receiving device uses the same predefined generating polynomial to generate its own internally generated CRC based on the received message block, comparing the CRC it has generated with the transmitted CRC. If an error has occurred during transmission, the internally generated CRC does not match the transmitted CRC. The CRC remainder coefficient generator of the present invention provides CRC remainder coefficients for efficient generation of a frame check sequence for a frame to be transmitted and for efficient cyclic redundancy check (CRC) error detection for a received digital signal frame in a digital communication system, typically by utilizing a system that includes multiple look-up tables having preselected precalculated CRC remainder coefficients. This minimizes actual computation time during CRC error-checking such that, where the present invention is combined with efficient encoding, the amount of time used for CRC computation is reduced by almost one-half for a software implementation. Significant savings can also be achieved with a hardware implementation. The present invention may be applied to any K-bit CRC with any frame length, but is particularly efficient for 16-bit and 32-bit CRCs with frame length of 8n bits (n is a positive integer). The present invention may be implemented to support a 16-bit CRC as specified in the CCITT (International Telegraph and Telephone Consultative Committee) X.25 recommendation. In addition, the present invention supports the 32-bit CRC specified in the ANSI/IEEE (American National Standards Institute/Institute of Electrical & Electronics Engineers, Inc.) 802.X standard. First, with respect to the 32-bit CRC, the ANSI/IEEE Standard 802. X specifies that the Frame Check Sequence (FCS) is the one's complement of the remainder r(x) = Remg(χ){χiι(x) + x 32 sf(x)} where g(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x u + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 is a generating polynomial, ι (x) = x 31 + x 30 + ... + x + 1 represents an initial remainder polynomial, i is a number of bits in the frame (not including the FCS), and Sf(x) is a polynomial formed by contents of the frame. The ANSI/IEEE 802.5 standard specifies that each octet of the frame is transmitted most significant bit first, and that the FCS be transmitted commencing with the coefficient of the highest term. The coefficient of the highest order term is the most significant bit of the first octet of the frame. The basis for the present invention may be understood as follows: Let g(x) be any CRC generating polynomial of degree K, s(x) be a polynomial of (n-1 )th degree formed by the first n bits of the frame, and l(x) be a polynomial of (K-1 )th degree formed by an initial remainder. Throughout the description of this invention, m, n and K are defined to be positive integers. Upon processing a first n bits of the frame, a remainder polynomial for the n bits is r(x) = Remg(χ){χnι(χ) + χ s ( x )} = rκ-ix κ_ 1 + rκ-2 κ"2 + ••• + π + ro. where rκ-1 , rκ-2> •••■. π, ro are remainder coefficients. To find a remainder r'(x) for a first (n+m) bits of the frame, where 0 < m < K, the polynomial s'(x) formed by the first (n+m) bits may be written as s'(x) = s(x)x m + d(x) where d(x) = d m -ι x m-1 + d m -2X m"2 + ... + dix + do is a polynomial whose coefficients are from an m additional bits of the frame. Thus, the new remainder r'(x) is given by: r'(x) = Rem g (χ) {x n+m ι(x) + χKs'(x)} = Remg( χ ){χn+ I ( x ) + x K[ s ( x ) x m + d(χ)] } = Remg(χ) {χm[χnι(χ) + χK s ( x yj + x Kd( x )}. Since r(x) = Remg(χ){x n l(x) + x κ s(x)}, which means that x n l(x) + x κ s(x) = q(x)g(x) + r(x), where q(x) is the quotient polynomial, the above equations may be rewritten: r'(x) = Remg(χ){χm[q(χ) g (χ) + r(x)] + χKd(x) } = Remg( x ) {x m q(x)g(x) + x r(x) + x κ d(x)} = Remg(χ) {χmq(χ)g(χ)} + Rem g(x) {χmr(x) + χKd(x) } =Rem g(x) <x m r(x) + x κ d(x) > =Rem g(x) {[r K -i + d m _ι]χK+m-l + ... + [-^^ + o]χK + r κ-m-ix κ" 1 + — + ri m + ro m" 1 } =Rem g(x ){[rκ-i + dm-ilx*-*™ " 1 + ... + [rκ- m + do]x κ } + r K-m-lx K" 1 + ••• + rιx m + r 0X m_1 • Thus, utilizing the above relationship for 0 < m < K, the present invention provides for obtaining the new remainder coefficients for the first (n+m) bits from the previous remainder coefficients for the first n bits by: 1 ) bitwise modulo-two addition of the m new bits to the m coefficients of the m highest order terms of the previous remainder polynomial (i.e., rκ-ι + d m -ι » r κ-2 + d m -2ι ■■•> rκ-m + do); 2) determining coefficients of an intermediate remainder Rem g (χ){[r K -ι + d m -ι]χK+m-ι + ... + [rκ- m + do]x κ }; and 3) obtaining the new remainder coefficients by adding the (K-m) lowest order term coefficients of the previous remainder r κ-m-ιx κ" 1 + — + rιx m + r ox m"1 to the (K-m) highest order term coefficients of the intermediate remainder. For m > K, r'(x) becomes: r'(x) = Rem g( χ ) {x m r(x) + x κ d(x)} = Remg ( χ ) {[rκ- 1 + d m _ι] x κ+m-ι + . . . + [ ro + d m _ κ ]χ m + d m _κ-ιx m_ 1 + • • ■ + dox κ } Hence, for the case of m>K, a new remainder for the first (n+m) bits can be obtained from the m additional bits and a previous remainder of the first n bits by: 1. bitwise adding (modulo 2) the K bit previous remainder to the K coefficients of the K highest order terms of d(x); i.e., r'κ-1 + d m _ 2 , rκ-2 + d m - 2 , ro + d m _κ; and 2. the new remainder r'(x) is then: Remg (X) {[rκ- 1 + d m _ι] x κ+m-i + . . . + [ ro + d m -κ . χ m + d m _κ-ix m" 1 + • • + dox κ } FIG. 1 , numeral 100, is a block diagram of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. The invention comprises two elements: a CRC circuit combining unit (102) and a CRC circuit conversion unit (104). The CRC circuit combining unit (102) combines data of a first input, a preselected portion of a last m coefficients of an (n+m) bit frame, with a preselected portion of the second input data that represents a preselected portion of previously calculated CRC remainder coefficients of a first n bits of the (n+m) bit frame to provide a plurality of adjusted coefficients. The CRC circuit combining unit (102) typically is an EXCLUSIVE-OR circuit (see FIG. 2, 208) that performs bitwise modulo-two addition on said inputs. The CRC circuit conversion unit (104) is operably coupled at least to the CRC circuit combining unit (102), and comprises at least one of A) a first look-up table, and B) a plurality (more than one) of look-up tables and substantially at least a first EXCLUSIVE-OR circuit, for utilizing at least the plurality of adjusted coefficients to provide a plurality of CRC remainder coefficients for the (n+m) bit frame. An EXCLUSIVE-OR circuit performs bitwise modulo- two addition. Selected implementations of the present invention are set forth below. For example, FIG. 2, numeral 200, is a block diagram of a first embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein K is a length of the CRC. Here D m = [d m -ι , d -2, •■■ , d-i , do] (202) represents m coefficients of an (n+m) bit frame (i.e., m bits after the first n bits), RMm = [rκ-1 , rκ-2 rκ-m] (204) represents a preselected portion of previously calculated CRC remainder coefficients of n bits of the (n+m) bit frame (here, m highest order remainder coefficients of the second input data, where m is greater than zero and less than or equal to K), and R|_(K-m) = [rκ-m-1 , rκ-m-2- ■••. ro] ((206) represents a second preselected portion of previously calculated CRC remainder coefficients of n bits of the (n+m) bit frame (here, (K-m) lowest order remainder coefficients of the second input data). In this implementation, the CRC circuit combining unit (102) includes an EXCLUSIVE-OR circuit (208) that performs bitwise modulo- two addition of D m (202) and RMm (204) ( m highest order coefficients of the previous remainder polynomial, where 1 < m ≤ K) to provide (output) adjusted coefficients. The CRC conversion unit (104) in this implementation includes a Remainder Conversion Unit 1 (210) that typically includes one of A-B: A) one memory look-up table of size 2 m by K, operably coupled to the CRC circuit combining unit (102), for utilizing the adjusted coefficients to output one of: A1 ) all coefficients (FIG. 3 (310)) of the CRC intermediate remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in the memory look-up table; and A2) K coefficients (212, 214) of a CRC intermediate remainder (212, 214) comprising K-m highest order coefficients (212) of the CRC intermediate remainder and m lowest order coefficients (214) of the CRC intermediate remainder that are m lowest order coefficients of the CRC remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in the memory look-up table; and B) j memory look-up tables (1 < j < m; j is a positive integer) of size 2 by K (where jb = m), operably coupled to the CRC circuit combining unit (102), for utilizing the adjusted coefficients to output all coefficients (212, 214) of the CRC intermediate remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in one of the j memory look-up tables. The Remainder Conversion Unit 1 (210) utilizes adjusted coefficients to provide intermediate remainder coefficients (TM(K-m)ι (K-m) highest order coefficients of the intermediate remainder (212); R'Lm, m lowest order coefficients of the intermediate remainder (214)). The adjusted coefficients are [rκ-ι + d m -ι ], [rκ-2+ d m -2] [rκ-m+ do] for the remainder terms χK+m-1 1 x κ+m-2 j mm __ X K ; respectively. The CRC conversion unit (104) further includes an EXCLUSIVE-OR circuit (216) that performs bitwise modulo-two addition of T (K-m) (212) (the highest order coefficients of the intermediate remainder)and R[_(K-m) (214) (the lowest order coefficients of the previous remainder (for n bits) rκ-m-ι x κ"1 + •■• + r-| X m + rox 171-1 ) to provide R'M(K-m) (218) (the highest order coefficients of the CRC remainder for the (n+m) bit frame), typically to a memory register. The Remainder Conversion Unit 1 (210) also provides R'Lm (220) (the lowest order coefficients of the CRC remainder for the (n+m) bit frame), typically to a memory register. These two outputs, R'M(K-m) (218) and R'Lm (220), represent all the coefficients of the CRC remainder for the (n+m) bit frame. Where selected, the CRC remainder coefficients for the (n+m) frame may be stored as a set of bits in a memory register. FIG. 3, numeral 300, is a block diagram of a second embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m = K. Here, the remainder for an (n + m) bit frame, where m = K, is calculated K bits at a time, significantly saving in CRC remainder generation time. In this implementation, D m = DK = [dκ-1 , dκ-2 d-i , do] (302) represents m = K coefficients of an (n+m) bit frame (i.e., m bits after the first n bits), RK = [rκ-1 , rκ-2 ro] (304) represents all of the previously calculated CRC remainder coefficients of n bits of the (n+m) bit frame or, identically, all of the remainder coefficients of the second input data. In this implementation, the CRC circuit combining unit (102) includes an EXCLUSIVE-OR circuit (306) that performs bitwise modulo- two addition of DK (302)and RK (304) to provide adjusted coefficients to the CRC conversion unit (104). The CRC conversion unit (104) in this implementation includes a Remainder Conversion Unit 2 (308) that typically includes one of: one memory look-up table of size 2 K by K, operably coupled to the CRC circuit combining unit (102), for utilizing the adjusted coefficients to output all coefficients (R'κ, 310) of the CRC intermediate remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in the memory look-up table; and _ j memory look-up tables (j < K; j is a positive integer) of size 2 by K (where jb = K), operably coupled to the CRC circuit combining unit (102), for utilizing the adjusted coefficients to output all coefficients (R'κ, 310) of the CRC intermediate remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in one of the j memory look¬ up tables. In the special case of the second implementation, the coefficients of the CRC intermediate remainder are simply the coefficients of the CRC remainder for the (n + K) bit frame. Thus, the Remainder Conversion Unit 2 (308) provides intermediate remainder coefficients R'κ = [rκ-ι + dκ-ι], [rκ-2+ dκ-2], •■• , [ro+ do] that represent all of the coefficients for the CRC remainder for the n + K bit frame. Note that this implementation does not require a second EXCLUSIVE-OR circuit, as was utilized in the first implementation, thus saving on circuit complexity or computation time. Thus, it is clear that the remainder conversion unit (RCU) may be implemented in a number of ways. Where the remainder conversion unit utilizes only one memory look-up table of size 2 m by K to store precomputed intermediate remainder coefficients, a fastest implementation is achieved. However, where m is large (for example, m = K), such a look-up table would require a large memory space consumption, On the other extreme, the RCU can be implemented by using m precomputed tables of size 1 by K, which will require (m-1 ) additional K-bit EXCLUSIVE-OR operations, significantly lowering conversion speed of the RCU. Generally, it is possible to trade-off some speed with memory space consumption in an implementation that utilizes j memory look-up tables of size 2 b by K, where jb = m, as is set forth in FIG. 4. FIG. 4, numeral 400, is a block diagram of an embodiment of a remainder conversion unit (RCU) in accordance with the present invention, wherein m = bj and where b is a positive integer, typically 8, and j is a positive integer. In this implementation, the RCU includes j memory look-up tables (Table Ki Lookup (410), Table K 2 Lookup (412), ... , Table Kj Lookup (414)) of size 2 b by K that are operably coupled to the CRC circuit combining unit (102), and an EXCLUSIVE-OR circuit (422) that is operably coupled to the memory look-up tables. The adjusted coefficients from the CRC circuit combining unit (102) are utilized by the j memory look-up tables (Table Ki Lookup (410), Table K 2 Lookup (412) Table Kj Lookup(414)), to output, typically to memory registers, j sets Tκ 1 (416), Tκ 2 (418), ..., TKJ (420), each having K bits, of precomputed intermediate remainder coefficients, which, bitwise modulo- two summed (i.e., EXCLUSIVE-ORed) together (j-1 ) times, are all coefficients of the CRC intermediate remainder for the (n + m) bit frame, wherein each coefficient has been precomputed and stored in one of the j memory look-up tables. Hence, in the FIG. 4 RCU implementation, the intermediate CRC remainder may be rewritten as (i.e., the formula for generating the tables of coefficients): Rem g ( x) {[rκ-i + m-i x^™ " 1 + ... + [rκ-m + do]x κ > = Rem g(x ){[r K -i + dm-il *^ 1 " ' 1 + ... + [rκ-b + d m _ b ]x κ+m - b } Rem g(x ){[rκ-b- i + dm-b- ilx^" 1"13 - 1 + ... + [rκ-2b-m + d m _2b]x κ+m - 2b } + ... + Rem g ( x ) {[r K -(j-i)b-i + d m _(j_ i)_ι]x κ+m - ( J- l ) - l + ... + [rκ-jb + do]x κ > Thus, in general, each of j terms of the the above equation calculates a remainder of a polynomial of degree [K + m - (j - 1 )b - 1] whose all but b highest order terms are zeros. Thus, where m = jb, the m bits are partitioned into j segments Ai b (408), A 2 b(406), ... (404), A j (402), of b bits each, and each segment is used as an address for a memory look-up table of coefficients. Each table of coefficients is precomputed and prestored for each of the j intermediate remainder terms, each table containing 2 entries, and each entry consisting of K coefficients of the intermediate remainder of such polynomial of degree [K + m - (j - 1)b - 1] with a particular combination of b highest order coefficient terms (all other terms must be zero by definition). For applications where the word lengths are shorter than K, each entry of the table occupies more than one memory location. For example, for a 32-bit CRC determination, if the word length of the device is 16, then each table entry requires 2 memory locations and 2 b+ 1 memory words for each lookup table. Depending on the architecture and addressing mode of the device, each lookup table may be organized as 2 b entries with each entry occupying two consecutive 16-bit words. Alternatively, each lookup table may be organized as two halves, where the upper half table contains the 2 upper word of every entry and the lower half table contains the 2 b lower word of every table entry. In this implementation, the CRC circuit combining unit (102) includes an EXCLUSIVE-OR circuit (422), operably coupled to receive the j memory register (416, 418 420) outputs, that performs bitwise modulo-two addition of all j look-up table coefficients, Tκ 1 (416), Tκ 2 (418) TKJ ( 420 HO provide all (TK, 424) of the the coefficients of the intermediate remainder. FIG. 5, numeral 500, is a block diagram of a fourth embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m = K = 32, j = 4, and b = 8. This implementation is well-suited to a 32-bit device. Where D3 = [d3i , d3o, ... , d-i , do] (502) represents 32 coefficients of an (n+32) bit frame (i.e., 32 bits after the first n bits), R32 = [r3i , rκ-2 ro] (504) represents a preselected portion of previously calculated CRC remainder coefficients of 32 bits of the n bit frame (here, 32 highest order remainder coefficients (i.e., all) of the second input data). In this implementation, the CRC circuit combining unit (102) includes an EXCLUSIVE-OR circuit (506) that performs bitwise modulo-two addition of D32 (502) and R3 2 (504) to provide (output) adjusted coefficients, which, in this implementation, are partitioned into four segments A-| ,8 (514), A 2>δ (512), A3,s (510), (508), of 8 bits each, and each segment is used as an address for a memory look-up table of coefficients of the CRC circuit conversion unit (104): Table 321 Lookup (516), Table 322 Lookup (518), Table 323 Lookup (520), and Table 324 Lookup (522), respectively. Each table of coefficients is precomputed and prestored for each of the 4 intermediate remainder terms, each table containing 2 8 entries, and each entry consisting of 32 adjusted coefficients of the intermediate remainder of such polynomial of degree [K + m - (j - 1)b - 1] with a particular combination of 8 highest order coefficient terms (all other terms must be zero by definition). Each look-up table (Table 32ι Lookup (516), Table 32 2 Lookup (518), Table 32 3 Lookup (520), and Table 32 4 Lookup (522)) of the RCU (104) is operably coupled to a memory register ( T3 2 1 - (524) ; T 32 2 , (526); T 2 3 , (528); T32 4 , (530)) (102) for storing the entries in the memory registers. The CRC conversion unit (104) further includes an EXCLUSIVE-OR circuit (532) that performs bitwise modulo-two addition of T32 1 (524), T32 2 (526), T32 3 (528), T 3 2 4 (530) to provide R'32 (534), all the coefficients of the CRC remainder for the (n+m) bit frame. Where selected, the CRC remainder coefficients for the (n+m) frame may be stored as a set of bits in a memory register. FIG. 6, numeral 600, is a block diagram of a fifth embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein K = 32, m = 16, j = 2, and b = 8. This implementation is well-suited to a 16-bit processing device. Here D m = Die = [dιs, d , ■■■ , di , do] (602) represents 16 coefficients of an (n+16) bit frame (i.e., 16 bits after the first n bits), RM I 6 = 1/31 , o, ••• » r i 6] (604) represents a preselected portion of previously calculated CRC remainder coefficients of n bits of the (n+16) bit frame (here, 16 highest order remainder coefficients of the second input data), and R I 6 = [rκi 5ι 1 * 14 I •■■» ro] ((606) represents a second preselected portion of previously calculated CRC remainder coefficients of n bits of the (n+16) bit frame (here, a (16) lowest order remainder coefficients of the second input data). In this implementation, the CRC circuit combining unit (102) includes an EXCLUSIVE-OR circuit (608) that performs bitwise modulo-two addition of Die (602) and RMI Θ (604) to provide (output) adjusted coefficients, which, in this implementation, are partitioned into two segments, A-i .β (612) and A 2 ,8(610), of 8 bits each, and each segment is used as an address for a memory look-up table of coefficients of the CRC circuit conversion unit (104): Table 321 Lookup (614) and Table 32 2 Lookup (616), respectively. Each table (of which there are two) of coefficients is precomputed and prestored for each of the 2 intermediate remainder terms, each table containing 2 8 entries, each entry consisting of 32 adjusted coefficients of the intermediate remainder. Each table (Table 321 Lookup (614) and Table 32 2 Lookup (616)) provides 32 bit intermediate remainder coefficients for a separate intermediate remainder, wherein the coefficients from each table are partitioned into two segments, one segment having 16 highest order remainder coefficients (T 1 M16 (620); T 2 M 1 6 (624)) and the other segment having 16 lowest order remainder coefficients (T 1 L16 (618); T L16 (622)). Thus, each look-up table (Table 321 Lookup (614) and Table 32 2 Lookup (616)) of the RCU (104) is operably coupled to a memory register that is partitioned to provide two 16 bit entries (T 1 L16 (618) and T1 M 16 (620), and T L 16 (622) and T 2 M 1 6 (624)) for storing the entries in the memory registers. In FIG. 6, the CRC conversion unit (104) includes a second EXCLUSIVE-OR circuit that includes a first (626) and a second (628) intermediate EXCLUSIVE-OR circuit, the first (626) being operably coupled to memory registers for T 1 L16 (618) and T 2 L16 (622), and the second (628) being operably coupled to memory registers for T 1 16 (620) and T 2 M16 (624) , respectively, that perform bitwise modulo-two addition of {T L 16 (618) and T 2 U 6 (622)}, and on {T 16 (620), T M 16 (624)} respectively to provide two 16 bit coefficient (highest (630) and lowest (634)) sets to a memory register unit ((R'LI Θ (634); R' M 16 (630)). A third intermediate EXCLUSIVE-OR circuit (632), operably coupled to memory register unit having the 16 highest order coefficients (630) of the second EXCLUSIVE-OR circuit and to the memory register for RLI Θ (606), performs bitwise modulo-two addition on R' 16 (630) and RLI 6 (606) to provide coefficients R"M16 (636) (higher coefficients) that together with R'LI 6 (634) (lower coefficients) represent CRC remainder coefficients for the (n+m) bit frame. Where selected, the CRC remainder coefficients for the (n+m) frame may be stored in a memory register. According to the definition of the ANSI/IEEE 802.3/Ethernet, the frame check sequence is based on the same CRC generating polynomial as that of IEEE/ANSI 802.5, but the order of transmission and bits arrangement are different. However, utilizing a similar derivation, it is clear that for the ANSI/IEEE 802.3/Ethernet CRC, FIGs. 1 through 6 stay the same if m is restricted to be 8,16, 24, or 32, with slightly different definitions for Ds, Di6, D24, D32, R32, R'32, and TJ32 's etc.: Dδ = [d7, d6, • • • , do] Dl6 = [d7, do, • • • , do, dis, di4, • • • , dβ] D24 = [ 7, do, • • • , do, dis, di4, • • • , ds, d23, d22, ■ ■ • , diό] D32 = [d7, do, • • • , do, dis, di4, • • • , ds, d23, d22, • • • , dιβ,d3i, d30, • • • , d24] R32 = [f7, r6, • • ■ , ro, ri5, ri4, • • • , rg, r 2 3, r22, ■ • ■ , r\6, r3i, T30, • • ■ , T24] R*32 = [r'7, Γ*6, • ■ • , r'o, r'15, r*ι , • • • , r' 8 , r'23, r' 2 2, • • • , r'i6, r'31,r'3θ, • • • ,r , 24] TJ32 = [tJ7, tJ 6 , • • ■ , tJ 0 , tϊi5, t ) i4, • • • , tig, tϊ 2 3, tJ22, • • • , ii6, tJ 3 l, J30, ' • ■ , tJ24] where 1< j < 4 and the dj's, η's, r'i's, tJj's are the coefficients of d(x) = d m -ι + d m _2 + d m _3x 2 + • • ■ + dix m " 2 + dox 1 "" 1 r(x) = T3i + r3ox + T2 9 X 2 + ■ • • + rix 30 + rox 1 r'(x) = r'3i + r ! 3o + r ! 2 9 2 + • • • + r'ιx 30 + r'ox 31 tJ(x) = Rem g ( x ) {[a7 + aβx + • • • + aox 7 ]x 32+( J- 1)8 } = tJ32 + tJ30X + U29 2 + • • • + tJiX 30 +,UQX 31 and ao, ai, • • • , a7 are any combination of 1's and O'J FIG.7, numeral 700, is a block diagram of a seventh embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m = K = 16, j = 2, and b = 8. This implementation is similar to that in FIG. 5. The order of bits is similar to that of ANSI/IEEE 802.3/Ethernet. Here D m = Dι 6 =[d7, dβ, ... , di, do, di5, d , — , β] (702) , R16 = [17. re ro, ris, ri4, ... , r 8 ] (704), and R'ι 6 = [r'7, r' 6 r'o,- r'15, r'14, ... , r'β] (722). That is, the two octets of D16, R16, and R'ιβ are swapped. Actually, for memory organized as 16-bit word units, an X.25 frame is stored in exactly the same order shown given by D16. The bit ordering reversal is solved utilizing the following equations to generate the two look-up tables, Table 1 61 (712) and Table 162 (714): tι (x) = Rem g(x ) {x 16 [(ri5 + dis) + (H4 + dι 4 )x 1 + ... + (rg +ds)x 7 ] } = tl,15 + tl,14X + .- + ti,8X 7 + ti, 7 X 8 +ti,6X 9 +...+ tl,0X 15 ^(x) = Rem g(x ) {x 16 [(r 7 + d 7 )x 8 + (r 6 + d )x 9 + ... + (r 0 +do)x 15 ] } = t2,15 + t2,14X + ... + t2,8X 7 + t2,7X 8 +t2,6X 9 +-+ 2,0 15 t-i (x) is utilized to generate the coefficients of Table 161 (712), t 2 (x) is utilized to generate the coefficients of Table 1 62 (714), and the coefficients are stored in the following order: [tι,7, tι,6, ... ,tι,o, tι,i5, tι,i4, ... ti.s] and [t2,7, t2,6, ••., t2,0, t2,15, t2, 14, •••, t2,8_ . Thus, in real-time remainder calculation, no additional time is required. For frames containing an odd integer number of octets, the last octet of the frame has to be treated differently for CRC remainder generation if the rest of the frames are processed 16 bits at a time. Calculation of the CRC remainder 8 bits at a time is a known technique and may be implemented together with the present invention for processing a last byte of a frame where the frame has an odd number of bytes. However, for completeness, it is shown here. Letting m=8 and d(x) = d7 + dβx + ..-+ rox 7 : r'(x) = Rem g(x) {χn+8i( x ) + x 16 s <( x )} = Rem g(x) {χn + 8l(χ) + χl6[ s ( x ) x 8 + d ( x )] =Rem g ( x ){x 8 tl(x)x n + x* 6 s(x)] + x 16 d(x) } = Rem g ( x ){x 8 r(x) + x 16 d(x) } = Rem g ( x ){(r 7 + d7)x 16 + (r6+ d6)x 17 + ... + (ro+ do)x 23 } + ri5X 8 + r l4X 9 +... + T8X 15 - In this implementation, the CRC circuit combining unit (102) includes an EXCLUSIVE-OR circuit (706) that performs bitwise modulo-two addition of Dιε (702) and Ri6 (704) to provide (output) adjusted coefficients, which, in this implementation, are partitioned into two segments, Aι ,8 (71 0) and A 2j 8 (708), of 8 bits each, and each segment is used as an address for a memory look-up table of coefficients of the CRC circuit conversion unit (104): Table 16ι Lookup (712) and Table 1 6 2 Lookup (714), respectively. Each table (of which there are two) of coefficients is precomputed and prestored for each of the 2 intermediate remainder terms, each table containing 2 8 entries, each entry consisting of 16 adjusted coefficients of the intermediate remainder. Each table (Table 16ι Lookup (712) and Table 16 2 Lookup (714)) provides 16 bit intermediate remainder coefficients (T 1 16 (716) and T 2 1 6 (718)) for a separate intermediate remainder. Each look-up table (Table 16ι Lookup (712) and Table 16 2 Lookup (718)) of the CRC circuit conversion unit (104) is operably coupled to a memory register that is partitioned to provide two 16 bit entries ( T 1 16> (716) and T 2 16, (718) for storing the entries in the memory registers. In FIG. 7, the CRC circuit conversion unit (104) further includes an EXCLUSIVE-OR circuit (720) that performs bitwise modulo-two addition of T 1 16 (716) and T 2 6 (718) to provide a 16 bit set (R'i 6 (722) of coefficients that together represent CRC remainder coefficients for the (n+16) bit frame. Where selected, the CRC remainder coefficients for the (n+16) frame may be stored in a memory register. Thus, FIG. 7 illustrates a very fast generation for the FCS of a frame based on a 16-bit CRC on a 16-bit device, while utilized a reasonable amount of memory (for two 256-by-16 look-up tables). Similarly, FIG. 6 illustrates a very fast generation of a FCS of a frame for a 32-bit CRC on a 16 bit device with reasonable amount of memory (for two 256-by-32 look-up tables). Of course, the fastest way to generate the 32- bit CRC remainder is to use a 32 bit device with 1024-by-32 bit memory with the implementation shown in FIG. 5. FIG. 8, numeral 800, is a block diagram of a point-to- point communication network system utilizing a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. The point-to-point communication network system includes a computer (802), operably coupled to selected modems (804,...), wherein at least one modem is further coupled to another modem that is coupled to a terminal (806), and at least one modem is coupled to a switched network (806) that is coupled to an acoustic device (such as a telephone) (808). The acoustic device is coupled to an acoustic coupler (810) that is coupled to a further terminal. Any of: the computer (802), modems (804, ...), switched network (806), and terminals (812,...) in this system may be selected to include the cyclic redundancy check remainder coefficient generator of the present invention (100). Since the point-to-point communication network system, not including the present invention, is known in the art, it will not be further described here. FIG. 9, numeral 900, is a block diagram of a multipoint communication network system utilizing a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. The multipoint communication network system includes a computer (902), operably coupled to selected modems (904,...), wherein at least one modem is further coupled to a plurality of other modems, each further modem being further coupled to a terminal (906). Any of: the computer (902), modems (904, ...), and terminals (912,...) in this system may be selected to include the cyclic redundancy check remainder coefficient generator of the present invention (100). Since the multipoint communication network system, not including the present invention, is known in the art, it will not be further described here. FIG. 10, numeral 1000, is a block diagram of a mixed communication network system utilizing a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention. The mixed (i.e., including point-to-point and multipoint) communication network system includes a computer (1002), operably coupled to selected modems (1004,...), wherein at least one modem is further coupled to another modem that is coupled to a terminal (1006), wherein at least one modem is further coupled to a plurality of other modems, each further modem being further coupled to a terminal (1006) and at least one modem is coupled to a switched network (1006) that is coupled to an acoustic device (such as a telephone) (1010). The acoustic device is coupled to an acoustic coupler (1012) that is coupled to a further terminal. Any of: the computer (1002), modems (1004, ...), switched network (1008), and terminals (1006,...) in this system may be selected to include the cyclic redundancy check remainder coefficient generator of the present invention (100). Since the mixed communication network system, not including the present invention, is known in the art, it will not be further described here. FIG. 1 1 , numeral 1 100, is a flow chart setting forth steps in accordance with a first implementation of the method of the present invention, a method for generating cyclic redundancy check (CRC) remainder coefficients in a CRC circuit having a first input of data for a plurality of m coefficients representing m bits of an (n+m) bit frame (n, m are positive integers, m > 1 ; K is a positive integer representing a degree of a CRC generating polynomial) and a second input of data for a plurality of K previously calculated CRC remainder coefficients of n bits of the frame. The method includes the steps of: (1 ) substantially performing, in a CRC circuit combining unit, bitwise modulo-two addition of a preselected portion of the first input data and the preselected portion of the second input data to provide a plurality of adjusted coefficients (1 102); and (2) in a CRC circuit conversion unit, utilizing at least the plurality of adjusted coefficients to provide a plurality of CRC remainder coefficients for the (n+m) bit frame (1 104). In the method set forth in FIG. 1 1 , the CRC circuit combining unit may be selected to include at least an EXCLUSIVE-OR circuit, as described above. The preselected portion of the first input data comprises one of: (1 ) where m < K, all remainder coefficients of the first input data; and (2) where m > K, K highest-order remainder coefficients of the first input data. Also, the preselected portion of the second input data typically comprises one of: (1 ) where m ≥ K, all remainder coefficients of the second input data; and (2) where 1 < m < K, m highest-order remainder coefficients of the second input data. The CRC circuit conversion unit generally includes at least a remainder conversion unit that includes one of: (1) one memory look-up table of size 2 m by K, operably coupled to the CRC circuit combining means, for utilizing the plurality of adjusted coefficients to output all coefficients of the CRC intermediate remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in the memory look-up table; and (2) j memory look-up tables (1 < j < m) of size 2 b by K (where jb = m; 1 < b < m), operably coupled to the CRC circuit combining means, for utilizing the plurality of adjusted coefficients to output all coefficients of the CRC intermediate remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in one of the j memory look-up tables, wherein, where selected, the coefficients of the CRC intermediate remainder for the (n+m) bit frame are stored in memory registers for output to an EXCLUSIVE-OR circuit. Further, in the method set forth in FIG. 1 1 , the CRC circuit conversion unit may be selected to include one of: (1 ) at least a first memory register unit for receiving and storing the coefficients output by the included set of table(s) (above) and a second EXCLUSIVE-OR circuit for performing bitwise modulo two addition on K-m coefficients for highest order terms of the CRC intermediate remainder for the (n+m) bit frame, and K-m coefficients of lowest order remainder terms of the second input to provide K-m CRC remainder coefficients for a K-m highest order term coefficients for the (n+m) bit frame and for outputting the K-m highest order remainder coefficients with m lowest order remainder coefficients output by the included set of table(s) to provide the CRC remainder coefficients for the (n+m) bit frame; (2) where m=bj, j memory register units for each receiving and storing K coefficients output by the included set of table(s), and a second EXCLUSIVE-OR circuit for performing bitwise modulo two addition on the K coefficients of the j memory register units to provide the CRC remainder coefficients for the (n+m) bit frame; and (3) wherein K =32, m=16, j=2, and b=8, and two 32 bit look-up tables are utilized , further being characterized by: (3a) the second EXCLUSIVE-OR circuit being utilized for receiving and processing by bitwise modulo-two addition, 16 coefficients for highest order terms from each of the two 32 bit look-up tables to provide 16 highest order remainder coefficients for the CRC remainder coefficients for the (n+m) bit frame, and (3b) a third EXCLUSIVE-OR circuit being utilized for receiving and processing by bitwise modulo-two addition, 16 coefficients for lowest order terms from each of the two 32 bit look-up tables to provide 16 lowest order remainder coefficients for the CRC remainder coefficients for the (n+m) bit frame, such that the plurality (32) of CRC remainder coefficients are provided for the (n+m) bit frame. Similarly, where K=32, m=8, j=1 , and b=8, the method set forth in FIG. 1 1 typically provides that (1 ) the preselected remainder coefficients of the second input data are 8 coefficients for highest order terms of the second input data, (2) the CRC circuit combining unit includes at least a first EXCLUSIVE-OR circuit for receiving and performing bitwise modulo two addition on the preselected remainder coefficients and the first input data to provide 8 intermediate coefficients; and (3) the CRC circuit conversion unit includes: (3a) a 32 bit memory look-up table for utilizing the 8 intermediate coefficients to output 32 coefficients of an intermediate 32 bit CRC remainder for the (n+m) bit frame, wherein each coefficient has been precomputed and stored in the memory look-up tables; (3b) a first storage register (1 st SR) unit for receiving and storing, for 1 st SR output, the 32 coefficients of the intermediate 32 bit CRC remainder, (3c) a shifting unit for receiving and shifting left by 8 bits (and inserting 8 zeros as lowest order term coefficients), 24 coefficients for lowest order terms of the second input data to provide a shift unit output, (3d) a second storage register (2nd SR) unit for receiving and storing, for 2nd SR output, the shifting unit output (data for 32 coefficients), and (3e) a second EXCLUSIVE-OR circuit, for receiving the 1 st SR output and the 2nd SR output, for performing bitwise modulo-two addition on the 1 st SR output and 2nd SR output to provide the plurality (32) of CRC remainder coefficients for the (n+m) bit frame. FIG. 12, numeral 1200, is a flow chart setting forth steps in accordance with a second implementation of the method of the present invention, a method for generating cyclic redundancy check (CRC) remainder coefficients in a CRC circuit. The method includes the steps of: (1 ) storing data for a plurality of m coefficients representing m bits of an (n+m) bit frame (n, m are positive integers, 1 < m < K; K is a positive integer representing a degree of a CRC generating polynomial) in a first memory register unit (1202), (2) storing data for a plurality of K previously calculated cyclic division polynomial remainder coefficients of a remaining portion of n bits of the frame in a second memory register unit (1204), (3) in a CRC circuit combining unit, substantially performing bitwise modulo-two addition on data from the first memory register storage unit and on a preselected portion of data from the second memory register unit to provide a plurality of adjusted coefficients (1206); and (4) in a CRC circuit conversion unit, utilizing at least the plurality of adjusted coefficients for providing a plurality of CRC remainder coefficients for the (n+m) bit frame (1208), wherein the CRC circuit is in a modem. This implementation may also include the additional elements described above for FIG. 1 1. Thus, those further descriptions for the method in FIG. 12 are not repeated here. It is clear, for example, that the present invention may be implemented in a LAN (local area network), a WAN (wide area network), or a MAN (metropolitan area network). Clearly, the implementation where 1 < m < K may be extended to the case where m > K, as is illustrated in FIG. 13, where DMK = [d m -ι , d m - 2 , • ■ ■ , d m -κ], DL(m-K) = [dm-κ-1 , do], and RK = [rκ-1 , rκ-2. ■ ■ ■ , ro]. Note that it is very similar to the special case of m = K except that RK is XORed with DM K only. This case is useful where K is small relative to a word length of a processor/device, as in header checking for asynchronous transfer mode cells. FIG. 13, numeral 1300, is a block diagram of an embodiment of a cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit in accordance with the present invention wherein m > K. Here RK represents a K-bit previously calculated CRC remainder [ro, η rκ-1] (1 302), DM K (1304) represents K most significant bits of the m data bits, and DL( ΓTI -K) (1306) represents (m-K) bits of a least significant portion of the m data bits. In this implementation, the CRC circuit combining unit (102) includes an EXCLUSIVE-OR circuit (1308) that performs bitwise modulo-two addition of Rκ (1302) and DMK (1304), outputting K adjusted coefficients (AM K) (1 31 0) that represent K most significant coefficients of an intermediate result, typically to a register (1310) of the CRC circuit conversion unit (104). The (m-K) bits of the least significant portion of the m data bits (DL(m-K) (1306)), may be implemented, for example, by utilizing an (m-K) least significant bit portion of a register (1312) and inputting AM K (1310) and DL( ΓTI -K) (1306) into a Remainder Conversion Unit (1314). Thus, the CRC circuit conversion unit (104) in this implementation includes a Remainder Conversion Unit (1314), implemented as described above for Remainder Conversion Unit 2 (308), that outputs a K-bit remainder R'κ (1316), representing all the coefficients of the CRC remainder. Where selected, the CRC remainder coefficients for the (n+m) frame may be stored as a set of bits in a memory register. It is clear to one skilled in the art that, in one implementation, a register 1304/1306 may be the same register as register 1310/1312. A 16-bit CRC may be implemented using the method (700) in a 16-bit DSP processor, for example a DSP56156 processor, with m=16, j=2 and b=8, thereby reducing processor loading by 43% relative to the fastest prior art method which uses m=8, j=1 , and b=8. A 32-bit CRC may be implemented using the method (600) in a 16-bit DSP processor with m=16, j=2, and b=8, thereby reducing the processor loading by 41 % relative to the fastest prior art method which uses m=8, j=1 , and b=8. Hardware implementation of the new method provides similar benefits with respect to throughput and area. Although exemplary embodiments are described above, it will be obvious to those skilled in the art that many alterations and modifications may be made without departing from the invention. Accordingly, it is intended that all such alternations and modifications be included within the spirit and scope of the invention as defined in the appended claims. We claim:

Claims: Claims: 1 . A cyclic redundancy check (CRC) remainder coefficient generator in a CRC circuit having a first input of data for a plurality of m coefficients representing a last m bits of an (n+m) bit frame (n, m are positive integers, m >1 ; K is a positive integer representing a degree of a CRC generating polynomial) and a second input of data for a plurality of K previously calculated CRC remainder coefficients of a first n bits of the frame, comprising: 1 A) CRC circuit combining means, operably coupled to receive a preselected portion of the first input data and a preselected portion of the second input data, for substantially performing bitwise modulo-two addition of the preselected portion of the first input data and the preselected portion of second input data to provide a plurality of adjusted coefficients; and 1 B) CRC circuit conversion means, operably coupled at least to the CRC circuit combining means, comprising a plurality (more than one) of look-up tables and substantially at least a first EXCLUSIVE-OR circuit, for utilizing at least the plurality of adjusted coefficients to provide a plurality of CRC remainder coefficients for the (n+m) bit frame. 2. The generator of claim 1 wherein the CRC circuit combining means includes at least an EXCLUSIVE-OR circuit, and, where selected, one of 2A-2B: 2A) the preselected portion of first input data that the EXCLUSIVE-OR circuit is coupled to receive comprises one of 2A1 -2A2: 2A1 ) where m > K, K most significant coefficients of m first input data; and 2A2) where 1 < m < K, all coefficients of the first input data, and 2B) the preselected portion of second input data that the EXCLUSIVE-OR circuit is coupled to receive comprises one of 2B1 -2B2: 2B1 )) where m > K, all remainder coefficients of the second input data; and 2B2) where 1 < m < K, m highest-order remainder coefficients of the second input data. 3. The generator of claim 1 wherein the CRC circuit conversion means includes at least a remainder conversion unit that includes j memory look-up tables (1< j < m) of size 2 by K (where jb = m; 1 < b < m), operably coupled to the CRC circuit combining means, for utilizing at least the plurality of adjusted coefficients to output all coefficients of the CRC intermediate remainder for the (n+m) bit frame, and wherein each coefficient has been precomputed and stored in one of the j memory look-up tables, wherein, where selected, the coefficients of the CRC intermediate remainder for the (n+m) bit frame are stored in memory registers for output to an EXCLUSIVE-OR circuit, and, where selected, one of 3A-3B: 3A) one of: b = 8 and b = 16, 3B) the CRC circuit conversion means further includes a second EXCLUSIVE-OR circuit, operably coupled to j register means, each of which is operably coupled to a separate one of the j memory look-up tables such that the circuit receives j sets of K coefficients for the CRC intermediate remainder, for performing bitwise modulo-two addition (j-1 times) on said coefficients to provide the CRC remainder coefficients for the (n+m) bit frame, and where selected, wherein K =32, m=16, j=2, and b=8, and two 32 bit look-up tables are utilized, wherein the second EXCLUSIVE-OR circuit includes one of 3B1- 3B4: 3B1 ) a first intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo- two addition, 16 coefficients for lowest order terms from each of the two 32 bit look-up tables; 3B2) a second intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo- two addition, 16 coefficients for highest order terms from each of the two 32 bit look-up tables; 3B3) remainder means, operably coupled to the first intermediate EXCLUSIVE-OR circuit and to the second intermediate EXCLUSIVE-OR circuit, for storing 16 coefficients for highest order terms of an intermediate remainder and 16 coefficients for lowest order coefficients of a CRC remainder for the (n+m) bit frame; and 3B4) a third intermediate EXCLUSIVE-OR circuit, operably coupled to the second EXCLUSIVE-OR circuit and to receive 16 lowest order coefficients of the second input of data for the plurality of K previously calculated CRC remainder coefficients of n bits, for performing bitwise modulo-two addition on the 16 coefficients for highest order terms of an intermediate remainder and the 16 lowest order coefficients of the second input of data to provide 16 highest order term coefficients that, together with the 16 lowest order coefficients (from the remainder means) of the CRC remainder coefficients for the (n+m) bit frame, represent all (32) CRC remainder coefficients for the (n+m) bit frame. 4. The cyclic redundancy check (CRC) remainder coefficient generator of claim 1 , wherein the generator is a component of a communication network system that comprises at least a computer, a plurality of modems, and a plurality of terminals, and, where selected, a switched network. 5. A cyclic redundancy check (CRC) remainder coefficient generator in a communication network system comprising: 5A) first storage means for storing data for a plurality of m coefficients representing a last m bits of an (n+m) bit frame (n, m are positive integers, m > 1 ; K is a positive integer representing a degree of a CRC generating polynomial); 5B) second storage means for storing data for a plurality of previously calculated CRC remainder coefficients of a precomputed CRC remainder for a first n bits of the frame; 5C) an EXCLUSIVE-OR circuit, operably coupled to the first storage means and to the second storage means, for substantially performing bitwise modulo-two addition on a preselected portion of first storage means data and on a preselected portion of second storage means data to provide a plurality of adjusted coefficients; 5D) CRC circuit conversion means, operably coupled at least to the EXCLUSIVE-OR circuit, comprising a plurality (more than one) of look-up tables and substantially at least a first EXCLUSIVE-OR circuit, for utilizing at least the plurality of adjusted coefficients to provide a plurality of CRC remainder coefficients for the (n+m) bit frame. 6. The generator of claim 5 wherein at least one of 6A-6B: 6A) wherein the CRC circuit combining means includes at least an EXCLUSIVE-OR circuit, and, where selected, one of 6A1 -6A3: 6A1 ) wherein the preselected portion of first input data that the EXCLUSIVE-OR circuit is coupled to receive comprises one of 6A1 a-6A1 b: 6A1 a) where m > K, K most significant coefficients of m first input data; and 1 6A1 b) where 1 < m < K, all coefficients of the first input data, 6A2) wherein the preselected portion of second storage means data that the EXCLUSIVE-OR circuit is coupled to receive comprises one of 6A2a-6A2b: 6A2a) where m > K, all remainder coefficients of the second input data; and 6A2b) where 1 < m < K, m highest-order remainder coefficients of the second input data, and 6A3) wherein the CRC circuit conversion means includes at least a remainder conversion unit that includes j memory look-up tables (1 < j < m) of size 2 b by K (where jb = m; 1 < b < m), operably coupled to the CRC circuit combining means, for utilizing at least the plurality of adjusted coefficients to output all coefficients of the CRC intermediate remainder for the (n+m) bit frame, and wherein each coefficient has been precomputed and stored in one of the j memory look-up tables, wherein, where selected, the coefficients of the CRC intermediate remainder for the (n+m) bit frame are stored in memory registers for output to an EXCLUSIVE-OR circuit, and, where selected, one of 6A3a-6A3b: 6A3a) wherein one of: b = 8 and b = 16, and 6A3b) wherein the CRC circuit conversion means further includes a second EXCLUSIVE-OR circuit, operably coupled to j register means, each of which is operably coupled to a separate one of the j memory look-up tables of claim 12B such that the circuit receives j sets of K coefficients for a CRC intermediate remainder, for performing bitwise modulo-two addition (j-1 times) on said coefficients to provide the CRC remainder coefficients for the (n+m) bit frame, and where selected, wherein K =32, m=16, j=2, and b=8, and two 32 bit look-up tables are utilized in claim 16, wherein the second EXCLUSIVE-OR circuit includes 6A3b1 -6A3b4: 6A3b1 ) a first intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo-two addition, 16 coefficients for lowest order remainder terms from each of the two 32 bit look-up tables; 6A3b2) a second intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo-two addition, 16 coefficients for highest order remainder terms from each of the two 32 bit look-up tables; 6A3b3) remainder means, operably coupled to the first intermediate EXCLUSIVE-OR circuit and to the second intermediate EXCLUSIVE-OR circuit, for storing 16 coefficients for highest order terms of an intermediate remainder and 16 lowest order coefficients of a CRC remainder for the (n+m) bit frame; and 6A3b4) a third intermediate EXCLUSIVE-OR circuit, operably coupled to the second EXCLUSIVE-OR circuit and to receive 16 lowest order coefficients of the second input of data for the plurality of K previously calculated CRC remainder coefficients of n bits, for performing bitwise modulo-two addition on the 16 highest order coefficients of an intermediate remainder and the 16 lowest order coefficients of the second input of data to provide 16 highest order coefficients that, together with the 16 lowest order coefficients (from the remainder means) of the CRC remainder coefficients for the (n+m) bit frame, represent all (32) CRC remainder coefficients for the (n+m) bit frame, and 6B) wherein the communication network system comprises at least a computer, a plurality of modems, and a plurality of terminals, and, where selected, a switched network. 7. A method for generating cyclic redundancy check (CRC) remainder coefficients in a CRC circuit having a first input of data for a plurality of m coefficients representing a last m bits of an (n+m) bit frame (n, m are positive integers, m > 1 ; K is a positive integer representing a degree of a CRC generating polynomial) and a second input of data for a plurality of K previously calculated CRC remainder coefficients of a first n bits of the frame, comprising the steps of: 7A) substantially performing, in a CRC circuit combining unit, bitwise modulo-two addition of a preselected portion of the first input data and a preselected portion of the second input data to provide a plurality of adjusted coefficients; and 7B) in a CRC circuit conversion unit comprising a plurality (more than one) of look-up tables and substantially at least a first EXCLUSIVE-OR circuit, utilizing at least the plurality of adjusted coefficients to provide a plurality of CRC remainder coefficients for the (n+m) bit frame. 8. The method of claim 7 wherein the CRC circuit combining unit includes at least an EXCLUSIVE-OR circuit, and, where selected, at least one of 8A-8C: 8A) wherein the preselected portion of first input data that the EXCLUSIVE-OR circuit is coupled to receive comprises one of 8A1-8A2: 8A1 ) where m > K, K most significant coefficients of m first input data; and 8A2) where 1 < m < K, all coefficients of the first input data, 8B) wherein preselected portion of the second input data comprises one of 8B1-8B2: 8B1 ) where m > K, all remainder coefficients of the second input data; and 8B2) where 1 < m < K, m highest-order remainder coefficients of the second input data, 8C) wherein the CRC circuit conversion unit includes at least a remainder conversion unit that includes j memory look¬ up tables (1 < j < m) of size 2 b by K (where jb = m; 1 < b < m), operably coupled to the CRC circuit combining means, for utilizing at least the plurality of adjusted coefficients to output all coefficients of the CRC intermediate remainder for the (n+m) bit frame, and wherein each coefficient has been precomputed and stored in one of the j memory look-up tables, wherein, where selected, the coefficients of the CRC intermediate remainder for the (n+m) bit frame are stored in memory registers for output to an EXCLUSIVE-OR circuit, and where selected, one of 8C1 -8C2: 8C1 ) wherein one of: b = 8 and b = 16, and 8C2) wherein the CRC circuit conversion means of claim 23 further includes a second EXCLUSIVE-OR circuit, operably coupled to j register means, each of which is operably coupled to a separate one of the j memory look-up tables of claim 23 such that the circuit receives j sets of K coefficients of a CRC intermediate remainder, for performing bitwise modulo-two addition (j-1 times) on said coefficients to provide the CRC remainder coefficients for the (n+m) bit frame, and where selected, wherein K =32, m=16, j=2, and b=8, and two 32 bit look-up tables are utilized in claim 25, wherein the second EXCLUSIVE-OR circuit includes 8C2a-8C2d: 8C2a) a first intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo-two addition, 16 coefficients for lowest order remainder terms from each of the two 32 bit look-up tables; 8C2b) a second intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo-two addition, 16 coefficients for highest order remainder terms from each of the two 32 bit look-up tables; 8C2c) remainder means, operably coupled to the first intermediate EXCLUSIVE-OR circuit and to the second intermediate EXCLUSIVE-OR circuit, for storing 16 coefficients for highest order remainder terms of an intermediate remainder and 16 lowest order coefficients of a CRC remainder for the (n+m) bit frame; and 8C2d) a third intermediate EXCLUSIVE-OR circuit, operably coupled to the second EXCLUSIVE-OR circuit and to receive 16 lowest order coefficients of the second input of data for the plurality of K previously calculated CRC remainder coefficients of n bits, for performing bitwise modulo-two addition on the 16 coefficients for highest order terms of an intermediate remainder and the 16 lowest order coefficients of the second input of data to provide 16 highest order coefficients that, together with the 16 lowest order coefficients (from the remainder means) of the CRC remainder coefficients for the (n+m) bit frame, represent all (32) CRC remainder coefficients for the (n+m) bit frame. 9. A method for generating cyclic redundancy check (CRC) remainder coefficients in a CRC circuit in a communication network system, comprising the steps of: 9A) storing data for a plurality of m coefficients representing a last m bits of an (n+m) bit frame (n, m are positive integers, m > 1 ; K is a positive integer representing a degree of a CRC generating polynomial) in a first memory register unit; 9B) storing data for a plurality of K previously calculated cyclic division polynomial remainder coefficients of a remaining portion of a first n bits of the frame in a second memory register unit; 9C) in a CRC circuit combining unit, substantially performing bitwise modulo-two addition on data from a preselected portion of the first memory register storage unit and on a preselected portion of the data from the second memory register unit to provide a plurality of adjusted coefficients; 9D) in a CRC circuit conversion unit comprising a plurality (more than one) of look-up tables and substantially at least a first EXCLUSIVE-OR circuit, utilizing at least the plurality of adjusted coefficients to provide a plurality of CRC remainder coefficients for the (n+m) bit frame. 1 0. The method of claim 9 wherein at least one of 10A-10C: 1 0A) the CRC circuit combining unit includes at least an EXCLUSIVE-OR circuit, and where selected at least one of 1 0A1 -1 0A3: 10A1 ) wherein the preselected portion of first input data that the EXCLUSIVE-OR circuit is coupled to receive comprises one of 10A1 a-10A1 b: 1 0A1 a) where m > K, K most significant coefficients of m first input data; and 1 0A1 b) where 1 < m < K, all coefficients of the first input data, 10A2) wherein the preselected portion of the data from the second memory register unit that the EXCLUSIVE-OR circuit is coupled to receive comprises one of 10A2a-10A2b: 10A2a) where m > K, all remainder coefficients of the second input data; and 10A2b) where 1 < m < K, m highest-order remainder coefficients of the second input data, 10A3) wherein the CRC circuit conversion unit includes at least a remainder conversion unit that includes j memory look-up tables (1 < j < m) of size 2 b by K (where jb = m; 1 < b < m), operably coupled to the CRC circuit combining means, for utilizing at least the plurality of adjusted coefficients to output all coefficients of the CRC intermediate remainder for the (n+m) bit frame, and wherein each coefficient has been precomputed and stored in one of the j memory look-up tables, wherein, where selected, the coefficients of the CRC intermediate remainder for the (n+m) bit frame are stored in memory registers for output to an EXCLUSIVE-OR circuit, and where selected, at least one of 1 0A3a-1 0A3b: 10A3a) wherein one of: b = 8 and b = 16, and 10A3b) wherein the CRC circuit conversion means of claim 31 further includes a second EXCLUSIVE-OR circuit, operably coupled to j register means, each of which is operably coupled to a separate one of the j memory look-up tables of claim 31 such that the circuit receives j sets of K coefficients a CRC intermediate remainder, for performing bitwise modulo-two addition (j-1 times) on said coefficients to provide the CRC remainder coefficients for the (n+m) bit frame, and where selected, wherein K =32, m=16, j=2, and b=8, and two 32 bit look¬ up tables are utilized in claim 33, wherein the second EXCLUSIVE-OR circuit includes 103b1 -103b4: 103b1 ) a first intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo-two addition, 16 coefficients for lowest order remainder terms from each of the two 32 bit look-up tables; 103b2) a second intermediate EXCLUSIVE-OR circuit, operably coupled to receive and process by bitwise modulo-two addition, 16 coefficients for highest order remainder terms from each of the two 32 bit look-up tables; 103b3) remainder means, operably coupled to the first intermediate EXCLUSIVE-OR circuit and to the second intermediate EXCLUSIVE-OR circuit, for storing 16 coefficients for highest order remainder terms of an intermediate remainder and 16 lowest order coefficients of a CRC remainder for the (n+m) bit frame; and 103b4) a third intermediate EXCLUSIVE-OR circuit, operably coupled to the second EXCLUSIVE-OR circuit and to receive 16 lowest order coefficients of the second input of data for the plurality of K previously calculated CRC remainder coefficients of n bits, for performing bitwise modulo-two addition on the 16 coefficients for highest order remainder terms of an intermediate remainder and the 16 lowest order coefficients of the second input of data to provide 16 highest order coefficients that, together with the 16 lowest order coefficients (from the remainder means) of the CRC remainder coefficients for the (n+m) bit frame, represent all (32) CRC remainder coefficients for the (n+m) bit frame, 1 0B) wherein the communication network system comprises at least a computer, a plurality of modems, and a plurality of terminals, and, where selected, a switched network, and where selected, wherein the communication network system is one of 1 0B1 -1 0B3: 10B1 ) a point-to-point communication network line structure system; 10B2) a multipoint communication network line structure system; and 10B3) a mixed communication network line structure system, and 10C) wherein the steps of the method for generating the cyclic redundancy check (CRC) remainder coefficients in the CRC circuit are implemented in a digital signal processor.

Inventors: LI SHIPING, PASCO-ANDERSON JAMES A, LI, SHIPING, PASCO-ANDERSON, JAMES, A.
Applicants: CODEX CORP, CODEX CORPORATION
Application year: 1993
Main classification: H03M13
IPC codes: H03M13, H04L1