MOS technology amplifier circuit

Abstract: When amplifier circuits of this type are realised in modern MOS technology, non-linear distortion occurs as a result of the high field strengths in the channel region due to the small dimensions. It is an object of the invention to eliminate this distortion and reduce the noise. This is achieved in that the amplifier circuit comprises a second series combination (T₃,T₄) identical with the first series combination (T₁,T₂) and forming a what is commonly referred to as long tailed pair with the latter, the long tailed pair circuit comprising an additional differential amplifier (4) whose output is connected to the gate electrode of a load transistor (T₄) of the long tailed pair circuit by way of a voltage divider (R₁,R₂), and the transistors in the long tailed pair circuit being mutually identical.

Description: The invention relates to a MOS technology amplifier circuit comprising a first series combination of the main current paths of a first and a second MOS transistor, the input of the amplifier circuit being coupled to the gate electrode of the first transistor, an output of the amplifier circuit being coupled to the drain electrode of the first transistor and the gate electrode of the second transistor being coupled to the drain electrode. A circuit of this type is known from the book entitled "Analysis and design of analog integrated circuits", 2nd Edn., by Paul R. Gray and Robert G. Meyer, published by John Wiley & Sons, more specif. Fig. 12.13(a). The voltage gain of such an amplifier is determined by the ratios of the channel dimensions of the transistors and is approximately equal to the square root of this ratio expressed as √k'. Since said gain ratio is unequal to one, the gate-source voltage V GS of the first transistor is unequal to that of the second transistor. In the saturation zone the current produced by the drain electrode of a modern technology MOS transistor is in a proper approximation equal to: I D = β 0 /2 ( V GS - V T ) 2 1 + ( V GS -V T ) , where V T is the power source electrode threshold voltage, β 0 = µ 0 C ox . (W/L) where µ 0 is the average mobility of the load carrier in the channel region of a MOSFET transistor having a low channel field strength, C ox is the gate electrode capacity per surface unit, W is the width and L the length of the channel region and  is a mobility reduction factor occurring at higher channel field strengths. Document EP, 0,123,275 discloses a differential MOS amplifier circuit having a differential input section comprising two main current paths of two series connected transistors. Due to the reduction factor  and the unequal gate-source voltage V GS of the two transistors, the gain is not linear, so that distortion occurs. It is an object of the invention to reduce this distortion considerably. The invention is defined by the appended claims. For this purpose, the amplifier circuit according to the invention comprises a second series combination identical with the first series combination and including the main current paths of a third and a fourth MOS transistor, another input of the amplifier circuit being coupled to the gate electrode of the third MOS transistor, the source electrodes of the first and third MOS transistors being intercoupled and coupled to a current source, the drain electrodes of the second and fourth MOS transistors being intercoupled, the drain electrodes of the first and third transistors being connected to a differential amplifier, the output of the differential amplifier being coupled to the output of the amplifier and also, via a series combination of a first and a second resistor, to the drain electrodes of the second and fourth MOS transistors, the junction of the first and second resistors being coupled to the gate electrode of the fourth transistor and the MOS transistors being mutually identical. This amplifier circuit is advantageous in that the distortion due to the mobility reduction of the load carriers in the channel region is eliminated and that still a gain factor of the order of 10 to 100 may be realised. This amplifier circuit further has the additional advantage of the gain factor being independent of the threshold voltage V T of the transistors. According to a further embodiment of the invention the differential amplifier circuit comprises a third series combination of the main current paths of a fifth and a sixth MOS transistor, a fourth series combination identical with the third series combination and including the main current paths of a seventh and an eighth MOS transistor, the source electrodes of the fifth and seventh MOS transistors being interconnected and, via a second current source, connected to the drain electrodes of the second and fourth MOS transistors, the gate electrodes of the fifth and seventh MOS transistors together forming the input to the differential amplifier, the gate electrodes of the sixth and eighth MOS transistors being intercoupled and coupled to the drain electrode of the eighth MOS transistor, the amplifier circuit comprising a ninth MOS transistor whose source electrode is coupled to the source electrode of the sixth and eighth MOS transistors and a power supply terminal, the gate electrode being coupled to the drain electrode of the sixth transistor, the drain electrode of the ninth MOS transistor forming the output of the amplifier circuit, and the fifth and seventh MOS transistors being complementary to the further MOS transistors. This embodiment is advantageous in that the operational amplifier comprises a minimum number of components, has a good dynamic range and in that a low supply voltage is sufficient for the amplifier circuit to operate. The invention and its advantages will be further explained with reference to the embodiments showing in the drawing Figures, in which: Fig. 1 shows an amplifier circuit according to the invention, and Fig. 2 shows a preferred embodiment of the amplifier circuit as shown in fig. 1. The basic circuit diagram of an amplifier circuit according to the invention shown in Fig. 1 comprises a first series combination of two MOSFET transistors, being a first transistor T 1 and a second transistor T 2 , a second series combination of two further MOSFET transistors being a third transistor T 3 and a fourth transistor T 4 . The source electrodes of the transistors T 1 and T 3 are interconnected and connected to a current source 1 and form what is commonly referred to as a long tailed pair. An input voltage V in applied to the input terminals 2 and 3 of the amplifier is applied to the gate electrodes of the transistor T 1 and T 3 . The transistors T 2 and T 4 form the loads of the transistors T 1 and T 3 . For this purpose, the source electrodes of the transistors T 2 and T 4 are connected to the drain electrodes of the transistors T 1 and T 3 and the drain electrodes of the transistors T 2 and T 4 as well as the gate electrode of transistor T 2 are connected to a point of fixed potential 7 (ground). The output voltage V u of the circuit described thus far is tapped between the drain electrodes of the transistors T 1 and T 3 . For the explanation of the operation of the amplifier circuit according to the invention it is first assumed that also the gate electrode of the fourth transistor T 4 is connected to ground, that the transistors T 1 and T 3 as well as the transistors T 2 and T 4 are mutually identical and that the geometric ratio W/L of the transistors T 1 and T 3 is in the proportion to the geometric ratios of the transistors T 2 and T 4 to the ratio of K:1, W representing the width and L representing the length of the channel regions of the MOSFET transistors, so that: W 1 L 1 : W 2 L 2 = K and that W 3 L 3 : W 4 L 4 = K For the current I D flowing through the MOSFET transistors it holds in a first approximation in the saturation zone that: I D = β 2 . ( V GS - V T ) 2 where V T is a threshold voltage resulting from the integration process, V GS is the voltage between the gate and the source electrode, and β = µ n C ox W L where µ n is the average carrier (holes in this case) mobility in the channel region of the MOSFET transistor and C o is the gate electrode capacitance per surface unit. From 2 it follows that: V GS = 2 I D β + V T Furthermore, V in = V GS 1 - V GS 3 Substitution of (4) yields that: V in = 2 I 1 β 1 - 2 I 2 β 1 where β 1 of transistor T 3 is equal to β 1 of transistor T 1 due to the fact that the transistors are identical and thus also have equal W/L ratios. Assuming that the gate electrode of V GS 4 is also grounded, for V u it holds that: V u = V GS 2 - V GS 4 Substitution of (4) and (6) yields that: V u = 2 I 1 β 2 - 2 I 2 β 2 where β 2 comprises the factor W 2 /L 2 which is identical for both transistor T 3 and T 4 . The gain factor is equal to: A = V T V in Substitution of (1), (3), (5), and (7) yields that: A = V T V in = 1 k When MOS transistors are realised in modern technology, the channel dimensions are so small and the field strengths in the channel are consequently so large that the average electron mobility µ n in formula (2) is no longer a constant value, but becomes dependent on the voltage difference (V GS - V T ). For µ n then holds that: µ n = µ o 1 +  ( V GS - V T ) where  is a mobility reduction factor which is approximately equal to 0.2 V -1 . This mobility reduction factor  in its turn depends on the channel dimension factor W/L. This should be taken to mean that formula 9 generally no longer holds. The gain factor A is in first instance equal to β 2 β 1 , due to the unequal mobility reduction factors  1 and  2 in (10) for (3) and shows that and β 1 β 2 have a value depending on the gate-source voltage V GS which causes distortion to occur. The invention compensates for this in that the transistors T 1 up to T 4 inclusive are all selected to be identical, so that V GS 1 = V GS 2 and V GS 3 = V GS 4 , β 2 is then identical with β 1 . This avoids distortion but it does have the disadvantage of the gain A being equal to one, because K = 1. In accordance with the invention the embodiment shown in Fig. 1 comprises an operational amplifier 4 whose inputs are connected to the drain electrodes of the transistors T 1 and T 3 and whose output, on one hand, forms the output 5 carrying output voltage V out of the amplifier and, on the other, through a series combination of a first resistor R 1 and a second resistor R 2 , is connected to ground. The junction of the resistors R 1 and R 2 is connected to the gate electrode of the fourth MOSFET transistor T 4 . Since the operational amplifier 4 continues to keep the voltages of the source electrodes of the transistors T 2 and T 4 equal to each other and since all the transistors are identical, the following holds: V out · R 2 R 1 + R 2 = V GS 2 - V GS 4 = V GS 1 - V GS 3 = V in The gain of the amplifier circuit is therefore equal to: The factor  is eliminated and, therefore, the distortion is very low. In addition, the noise of this amplifier is determined by the resistance ratio R 1 /R 2 and is therefore low too. Besides, all input current of this amplifier is fully used, so that the amplifier needs to have little power. Furthermore, the gain factor does not depend on the threshold voltage V T , although the amplifier circuit has a single-ended output. The amplifier circuit shown in Fig. 2 comprises a differential amplifier 4 known per se . This amplifier comprises what is commonly referred to as a long tailed pair circuit, formed by the mutually identical MOSFET transistors T 5 and T 7 whose source electrodes are interconnected and connected to ground via a current source 8. These transistors are complementary to the further transistors of the amplifier. The load of this long tailed pair circuit is formed by a current source circuit comprising a transistor T 6 included in a third series combination with transistor T 5 , and a transistor T 8 arranged as a diode and included in a fourth series combination with transistor T 7 , the gate electrodes of the transistors T 6 and T 8 being interconnected and the source electrodes of these transistors T 6 and T 8 being interconnected and connected to the positive terminal 9 of a power supply source (not shown). In addition, the operational amplifier 4 comprises an output transistor T 9 whose source electrode is connected to the positive supply terminal 9 and whose drain electrode forms the output 5 of the amplifier circuit. A differential current caused by the input voltage V 1 is applied from transistor T 5 to transistor T 9 as a control voltage and presented as an amplified version on output terminal 5. The use of this differential amplifier 4 in the amplifier circuit according to the invention provides that voltage shifts are not necessary for realising the amplifier circuit. The amplifier circuit is therefore pre-eminently suitable for operation with a very low supply voltage. For realising an optimum drive of the amplifier circuit, it is possible to compensate for the voltage drop across the current source 7 at the gate electrode of the second transistor T 2 in that a reference voltage coming from a DC voltage source 10 is supplied.

Claims: MOS technology amplifier circuit comprising a first series combination of the main current paths of a first (T 1 ) and a second (T 2 ) MOS transistor, the input (2) of the amplifier circuit being coupled to the gate electrode of the first transistor, an output (5) of the amplifier circuit being coupled to the drain electrode of the first transistor and the gate electrode of the second transistor being coupled to the drain electrode of the second transistor, characterized in that the amplifier circuit comprises a second series combination identical with the first series combination and including the main current paths of a third (T 3 ) and a fourth (T 4 ) MOS transistor, another input (3) of the amplifier circuit being coupled to the gate electrode of the third MOS transistor, the source electrodes of the first and third MOS transistors being intercoupled and coupled to a current source (1), the drain electrodes of the second and fourth MOS transistors being intercoupled (7), the drain electrodes of the first and third transistors being connected to a differential amplifier (4, T 5 -T 9 ), the output of the differential amplifier being coupled the output of the amplifier (V out ) and also, via a series combination of a first (R 1 ) and a second (R 2 ) resistor, to the drain electrodes of the second and fourth MOS transistors, in that the junction of the first and second resistors are coupled to the gate electrode of the fourth transistor and in that the MOS transistors are mutually identical. Amplifier circuit as claimed in Claim 1, characterized in that the differential amplifier circuit comprises a third series combination of the main current paths of a fifth (T 5 ) and a sixth (T 6 ) MOS transistor, a fourth series combination identical with the third series combination and including the main current paths of a seventh (T 7 ) and an eighth (T 8 ) MOS transistor, the source electrodes of the fifth and seventh MOS transistors being interconnected and, via a second current source (8), to the drain electrodes of the second and fourth MOS transistors, the gate electrodes of the fifth and seventh MOS transistors forming the inputs to the differential amplifier, the gate electrodes of the sixth and eighth MOS transistors being intercoupled and coupled to the drain electrode of the eighth MOS transistor, in that the amplifier circuit comprises a ninth MOS transistor (T 9 ) whose source electrode is coupled to the source electrode of the sixth and eighth MOS transistors and a power supply terminal (9), the gate electrode being coupled to the drain electrode of the sixth transistor, in that the drain electrode of the ninth MOS transistor forms the output of the amplifier circuit, and in that the fifth and seventh MOS transistors are complementary to the further MOS transistors.

Inventors: BOLT JACOB HENDRIK, SEEVINCK EVERT, BOLT, JACOB HENDRIK, SEEVINCK, EVERT, BOLT, JACOB HENDRIK, C/O INT. OCTROOIBUREAU B.V., SEEVINCK, EVERT, C/O INT. OCTROOIBUREAU B.V.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1993
Main classification: H03F3
IPC codes: H03F3, H03F1