Method of manufacturing a semiconductor well structure

Abstract: A method of forming a doped well 24 or 30 in a semiconductor layer is disclosed herein. In a preferred embodiment, an oxide layer 16 is formed on the surface of a silicon layer 14. A nitride layer 18 is then formed on the oxide layer 16 and is patterned and etched to define a first well region 24. The first well region 24 is then doped, for example with phosphorus or boron. A resist layer 26 is formed over the first well region 24 and over a portion of the nitride layer 18 after which a portion of the nitride layer 18 not beneath the resist layer 26 is removed to expose a second well region 30. The second well region 30 is then doped. After the remaining portion the resist layer 26 is removed, an oxide layer 32 is formed over the first 24 and second 30 well regions while the surface 38 over the region 36 separating the well regions is left bare. The layer 14 is then heated in a nitridizing environment (e.g., ammonia ambient) such that dopants tend to diffuse into the silicon layer 14.

Description: FIELD OF THE INVENTION This invention generally relates to the fabrication of semiconductor devices and specifically to a method for forming well structures in a silicon layer. BACKGROUND OF THE INVENTION Advanced CMOS (complementary metal-oxide-semiconductor) and BiCMOS (bipolar and complementary metal-oxide-semiconductor), as well as some other device technologies, require the formation of doped N or P wells or both N and P wells in bulk silicon or epitaxial (for example, a P - epi-layer on a P + substrate or an N - epi-layer on an N + substrate) wafers. The well formation process is usually based on ion implantation of boron (for P-well) or phosphorus (for N-well) followed by a long (e.g., a few hours), high-temperature (e.g., 1100° to 1200°C) furnace anneal in an inert or oxidizing ambient. The relatively long furnace anneal is required to form deep N and P well regions via thermal diffusion. The well junction depth is usually at least a few times larger than the source/drain junction depths. For instance, a 0.35µm CMOS technology may require N and P wells with greater than one micrometer well-to-substrate If the well formation process is to be performed in a single-wafer-based semiconductor factory, the time and temperature requirements for a single-wafer well drive-in process can be rather excessive (e.g., temperatures of 1100°-1200°C for more than 30 min.) resulting in low manufacturing throughput. This requirement could make the manufacturing costs unbearably high. Moreover, conventional furnace diffusion processes for formation of diffused wells cause lateral diffusion of both N and P dopants, resulting in lateral dopant compensation. This undesirable lateral diffusion places a limit on the minimum N-to-P well spacing and makes device layout scaling more difficult. In the article "CMOS well drive-in in NH 3 for reduced lateral diffusion and heat cycle", IEEE ELECTRON DEVICE LETTERS, Vol.EDL-6, No. 10, December 1985, pages 659-661, S. S. Wong and T. W. Ekstedt describe CMOS n-well drive-in performed in an NH 3 ambient. A 150-nm-thick CVD Si 3 N 4 layer is deposited on a 40-nm-thick stress-relief thermal SiO 2 layer. The Si 3 N 4 layer is then patterned and etched to define the well regions into which P is implanted. For the well drive-in, the wavers are prepared to have about 50-nm-thick of SiO 2 on the well regions and to be bare elsewhere. The well drive-in is then performed at 1125°C in an NH 3 ambient for 15 h, thereby receiving 3.5-µm deep n wells. At the SiO 2 substrate interface on the well regions where oxynitridation occurs the diffusion of P towards the bulk is enhanced, whereas at the etch of the well where direct nitridation occurs because of the bare Si surface the lateral diffusion of P is less enhanced or possibly retarded. In the article "Effect of Si and SiO 2 thermal nitridation on impurity diffusion and oxidation induced stacking fault size in Si", JOURNAL OF APPLIED PHYSICS, Vol. 54(7), July 1983, pages 3860-3866, Shoichi Mizuo et al. describe that enhanced B and P diffusion is found in Si masked with SiO 2 films, whereas retarded B and P diffusion is found in nonmasked Si that has undergone NH3 heat treatment. On the other hand, in N 2 or N 2 + H 2 (1:3) ambients no significant ambient effect on impurity diffusion is found in Si masked with SiO 2 films. However, retarded B and P diffusion is found in nonmasked Si with N 2 ambient. From "PATENT ABSTRACTS OF JAPAN", Vol. 7, No. 251 (E-209) [1396], 8 November 1983 & JP-A-58-138068 a method of forming a p-well region and an n-well region in a self-alignment manner by removing a pattern and a material layer section to be oxidized under the pattern and implanting the ions of a second conduction type impurity is known. There is still a need for an RTP (rapid thermal processing) based well formation process which can form the necessary N and P well regions based on reasonable RTP temperature/time conditions. Moreover, there is a need for a well formation process which can form the wells of desired depths using reduced temperature/time process parameters without excessive lateral interdiffusion of the N and P well dopants. SUMMARY OF THE INVENTION Other objects and advantages will be obvious, and will in part appear hereinafter and will be accomplished by the present invention which provides a method of forming at least two doped wells in a first silicon layer as defined in claim 1. A first doped well region is formed in the silicon layer adjacent a separation region. An oxide layer (e.g., silicon dioxide) is formed over the first doped well region but not over the separation region. The silicon layer is then heated in a nitridizing environment such that dopants in the doped well region diffuse vertically at a higher rate than the dopants diffuse laterally. The method also includes forming a second doped well region in the silicon layer. This invention can be utilized in either multi-wafer or single-wafer processing chambers. The reasonable time (e.g., less than ten minutes) and temperature (e.g., less than 1150°C) requirements make the process practical in a high-volume manufacturing environment. This is especially true for single-wafer processing equipment where the processing time per wafer is critical since wafers are processed one at a time. A further advantage of this invention is that the process flow may be modified so that both the N-well and P-well regions are formed without producing any substantial nonplanar topography or steps on the substrate. A planar device structure is typically preferred for subsequent microlithography steps. BRIEF DESCRIPTION OF THE DRAWINGS The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which: Figures 1 through 7 are cross-sectional views of a device during various stages of the process flow for forming a well structure; Figures 8 and 9 are cross-sectional views of a device during various stages of the process flow for forming a well structure in accordance with the invention; and Figure 10 is a cross-sectional view of a circuit which utilizes the well structure of the present invention. Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The making and use of the presently preferred embodiments are discussed below in detail. The specific embodiments discussed are illustrative of specific ways to make and use the invention. The present invention is related to U.S. Patent No. 5,219,783 (TI-16125). The following is a description of the method of the present invention. An application example will then be briefly described. The present invention proposes a useful and practical process based on RTP (rapid thermal processing) or standard furnace processing which can be used to form N and/or P wells for technologies such as advanced submicrometer CMOS (complementary metal-oxide-semiconductor) or BiCMOS (bipolar and complementary metal-oxide-semiconductor on same chip) technologies. The process flow described herein allows optimization of the CMOS wells without any need for MeV (mega-electron-volt) or very high energy ion implantation steps and without significant process throughput limitation problems. In one aspect, the process utilizes two main features. The first feature is an effect known as "oxynitridation-enhanced diffusion" or "ONED." This effect is used during the RTP well drive-in cycle to cause a significant enhancement of the boron and phosphorus diffusion in the vertical direction. This effect can be much stronger than the so-called "oxidation-enhanced diffusion" or "OED" effect for boron and phosphorus and allows for a reduction in the well diffusion time and temperature requirements. Further, the OED method is not typically considered desirable since silicon is consumed through thermal oxidation. The ONED effect on the other hand consumes only a negligible amount of silicon. Another effect known as "nitridation-retarded diffusion" or "NRD" is also utilized. This effect is used in order to minimize the lateral diffusivities of boron and phosphorus during the RTP well formation. This will allow closer spacings between N and P wells due to reduced lateral dopant compensation and reduced lateral N and P well diffusions. For more information on oxidation and nitridation, see the following papers: 1) Moslehi et al. "Thermal Nitridation of Si and SiO 2 for VLSI", IEEE Transactions on Electron Devices , Vol. ED-32, No. 2, February 1985, pp. 106-123. 2) Moslehi et al. "Compositional Studies of Thermally Nitrided Silicon Dioxide (Nitroxide)", Journal of the Electrochemical Society, Vol. 132, No. 9, September 1985, pp. 2189-2197. 3) Moslehi et al. "Rapid Thermal Nitridation of SiO2 for Nitroxide Thin Dielectrics", Appl. Phys. Lett. 47 (10), 15 November 1985, pp. 1113-1115. The RTP and standard furnace based CMOS well formation process proposed herein is fully compatible with standard CMOS and BiCMOS technologies. The electrical characteristics of the wells (e.g., crystal quality) are expected to be as good as those of the conventional CMOS wells. The process flow described herein utilizes two masks to form both the N and P wells. For the specific embodiment described in detail, a twin-cell CMOS technology is assumed even though the process may also be used for a wide variety of other technologies. For the example used to describe the process flow, it is assumed that both N and P wells are formed on P - epi/P + wafers. The use of epitaxial material is known to be very helpful for CMOS latch-up immunity. To describe the proposed flow, it is assumed that the object is to form 1.0 to 1.5 µm deep wells on P - /P + epitaxial wafers. Typically the epitaxial thickness is between 2 and 4 micrometers. Although described with respect to a specific embodiment, the present invention may be performed in a variety of environments. For example, the substrate may be bulk silicon or an epitaxial grown layer grown on bulk semiconductor or on an insulator such as any of the known SOI (semiconductor on insulator technologies). In addition, the process may be performed in a single wafer or multi-wafer processing chamber. The process steps for forming a well structure will now be described with respect to Figures 1 through 7. The process steps according to the invention are described with respect to Figures 8 and 9. A cross sectional view of an exemplary application will then be shown in Figure 10. Referring first to Figure 1, a semiconductor workpiece 10 comprises a P + silicon substrate 12 over which P - epitaxial layer 14 is formed. As previously mentioned, the doping of the workpiece may vary (e.g., P-type, N-type, intrinsic) depending upon the application. An oxide layer 16 is formed on the surface of layer 14. The oxide layer 16 may comprise silicon dioxide and may be formed by thermal oxidation. The oxide layer 16 may also be deposited by LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition). The oxide layer 16 is typically between about 10 and 100 nm thick and preferably about 25 nm thick. The next step of the process flow is to form nitride (e.g., Si 3 N 4 ) layer 18 over oxide layer 16. The nitride layer 18 is typically formed by chemical vapor deposition and is typically between about 30 nm and 80 nm thick. A resist layer 20 is then formed over nitride layer 18. The resist layer 20 may be any standard photolithography resist as is well known in the art. Referring now to Figure 2, a first mask is used to define the first well regions. The resist layer 20 is patterned and etched as is well known in the art. Using the pattern formed in resist layer 20, nitride layer 18 is etched with either an isotropic or an anisotropic etch. During this etch process, the oxide layer 16 will serve as an etch stop. During this process, the second well region as well as a separation region (i.e., an unimplanted region that separates the first and second well regions) are beneath nitride layer 18 and resist layer 20. The next step is to perform the first well region implantation. For the example illustrated herein, this will be the n well implantation. This step is illustrated in Figure 2 by the arrows 22. Typically, but not necessarily, this is a double implant at various doses and energies. For example, it alternatively may be a single or triple implant. The most common n type dopant is phosphorus but other dopants such as arsenic and antimony may also be used. The implanted region in layer 14 is denoted by the dashed lines and the numeral 24. Referring next to Figure 3, the resist layer 20 is removed. For example, resist layer 20 may be removed using an ash process. A resist layer 26 is then formed and patterned to define the second well regions. The portion of nitride layer 18 exposed by the second photoresist mask 26 is then etched away. It is noted that the portions of nitride remaining 18a and 18b are left over the separation regions between the first and second well regions. The next step is to perform the second well region implantation. In the example illustrated here, the second well region is a p well region. This step is illustrated in Figure 3 by the arrows 28. Typically, but not necessarily, this doping step also comprises a double implant. For example, the step may alternatively be a single or a triple implant. The preferred p-type dopant is boron but other dopants such as aluminum or gallium may also be used. In Figure 3, the second implanted region in layer 14 is denoted by the dashed lines and the numeral 30. Although discussed herein as a n-well region 24 and a p-well region 30, the regions 24 and 30 may both be n-well regions (e.g., with different doping concentrations) or both be p-well regions as required by the specific application. Of course, the region 24 may be doped with p-type impurities and the region 30 with n-type impurities. Referring next to Figure 4, the resist layer 26 is stripped. A short steam oxidation is then performed to increase the thickness of the exposed portions of oxide layer 16. These exposed portions of thicker oxide are denoted in Figure 4 with the reference numeral 32. The portions of oxide layer 16 beneath nitride layer 18 are denoted with the numeral 34. The thermal process used for the oxidation may be a rapid thermal process or a standard furnace process. The thicker oxide regions 32 will typically be between 50 nm and 100 nm thick. Referring now to Figure 5, the remaining portions 18a and 18b of the nitride layer are removed. It is noted that a short oxide deglaze is normally required to revive the thin oxide which will have formed on nitride layer 18 prior to stripping the nitride layer. The thin oxide layers 34 are then removed. The thin oxide layers 34 may be removed by performing a timed wet HF or vapor-phase HF deglaze to remove the oxide. The last oxide etch will also remove a fraction of thick oxide 32. Typically, the thick oxide 32 will now be between about 20 nm and 60 nm thick. It is noted that well regions 30 and 24 are now covered by oxide layers 32 while separation regions 36 (i.e., the unimplanted region which separates regions 30 from 24) has bare silicon surface 38. These features allow for the ONED and NRD phenomena described earlier to benefit the resulting structure as illustrated in Figure 6. Next a RTP or batch furnace tank formation anneal is performed in a nitridizing ambient. Preferably, an ammonia ambient is used. The temperature may be less than 1150°C and preferably between about 1050 and 1150°C. The typical anneal times will be less than ten (or possibly five) minutes. This feature provides a throughput advantage, especially in single-wafer processing chambers. The oxide regions 32 over the doped well regions 24 and 30 will cause significant vertical diffusion enhancement via the ONED effects for boron and phosphorus. However, the exposed silicon surfaces 38 between the well regions 24 and 30 (and over the separation regions 36) will reduce the lateral diffusivities of boron and phosphorus via the NRD effects (direct nitridation of exposed silicon surfaces). The workpiece after the anneal step is illustrated in Figure 6. Also illustrated in Figure 6 are the silicon nitride layers 40 which will form on silicon surface 38 as well as the oxynitride layers 42 which will form on oxide layers 32. The result of the anneal step is the formation of n and p wells with reduced lateral dopant compensation and therefore improved CMOS packing density. In other words, due to the limited lateral diffusion, the wells may be spaced more closely together. If desired, a short steam oxidation may be performed to consume the nitride regions 40. An oxide deglaze may then be performed to remove regions 32 and 40 and other oxides from the surface of substrate 14. Alternatively, a wet etch may be performed. The substrate, illustrated in Figure 7, is now ready to proceed with the standard processing steps. It should be noted that the final topography of layer 14 will not be perfectly smooth because of the oxidation of the doped regions 24 and 30 while forming thick oxide layers 32. An embodiment of the present invention which substantially eliminates this topography problem is illustrated with reference to Figures 8 and 9. Figure 8 illustrates a polycrystalline or amorphous silicon layer 17 formed between oxide layer 16 and nitride layer 18. The polysilicon layer is typically between about 10 nm and 50 nm thick and may be formed by LPCVD. In the preceding example, Figure 8 would replace Figure 1 for the embodiment of the present invention. The process flow according to the invention would continue substantially like that illustrated in Figures 2 through 5. In the embodiment of the invention, however, the thick oxide regions 32 will be formed by oxidation of polysilicon layer 17 rather than portions of semiconductor layer 14. This variation is shown in Figure 9 (which is similar to Figure 6 discussed above). Since the silicon substrate 14 is not oxidized, when the oxide is removed as discussed with reference to Figure 7, the substrate will remain substantially unchanged. Therefore, these additional steps will avoid any topography issues with the final substrate. The substrate 10 which includes n-well regions 30 and p-well regions 36 may be used in a great number of applications. It is noted that the application in which the substrate 10 is used is not critical to this invention. Referring now to Figure 10, a cross-section of one exemplary transistor device 50 is illustrated. The transistor device 50 includes P-well region 30 and N-well region 24 and is included herein to illustrate one of the many possible applications of the process of present invention.

Claims: A method of forming at least two doped wells in a first silicon layer (14), said method comprising the steps of: forming an oxide layer (16) on the surface of the silicon layer (14); forming a second silicon layer (17) on the oxide layer (16); forming a nitride layer (18) on the second silicon layer (17); forming a first patterned resist layer (20) on the nitride layer (18); etching of the nitride layer (18) by using the first patterned resist (20) as a mask; forming a first well region (24) by doping a portion of the silicon layer (14) by ion implantation using the first patterned resist and the patterned nitride layer (18) as a mask; removing the first patterned resist (20); forming a second patterned resist (26) over the first well region (24) and the patterned nitride layer (18), the second resist (26) being patterned so as to define a second well region (30) exposed from the resist and separation regions (36) adjacent the first well region under the nitride layer and covered by the resist; etching the nitride layer (18) by using the second patterned resist as a mask, leaving remaining portions of the nitride layer (18a, 18b) defining the separation regions (36); doping the second well region (30) by ion implantation; removing the second patterned resist (26); oxidizing portions of the second silicon layer (17) above the first and second well regions (24, 30) so as to form an oxide region (32) over the first and second well regions (24, 30); removing the remaining portions of the nitride layer (18a, 18b) and the oxide layer (16) under the remaining portions of the nitride layer (18a, 18b) so as to expose the separation regions (36); and heating the silicon layer (14) in a nitridizing environment in order to diffuse the dopants in the first and second well regions (24, 30) vertically in the silicon layer at a greater rate than they diffuse laterally. The method of claim 1, wherein said heating step comprises heating in an environment with an ammonia ambient. The method of claim 1 or claim 2, wherein said heating step comprises heating to a temperature less than about 1150°C. The method of any preceding claim, wherein said heating step comprises heating for a period of less than ten minutes. The method of any preceding claim, further comprising chosing said dopants from the group comprising phosphorus and boron. The method of any preceding claim, further comprising providing said silicon layer (14) as an epitaxially grown silicon layer. The method of any preceding claim, wherein doping said first well region (24) comprises doping with N-type impurities and doping said second well region (30) comprises doping with P-type impurities. The method of any preceding claim, wherein said forming of said oxide layers is by thermal oxidation.

Inventors: KUEHNE JOHN W, MOSLEHI MEHRDAD M, KUEHNE, JOHN W., MOSLEHI, MEHRDAD M.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L27