STRUCTURE AND METHOD FOR TESTING WIRING SEGMENTS IN AN INTEGRATED CIRCUIT DEVICE

Abstract: According to the present invention, means are provided for joining metal wire segments into one or more serpentine structures during the testing phase so that a signal applied at one end will be detected at the other end if the metal segments are continuous. Metal segments connected into one serpentine chain can be simultaneouly tested for continuity from a single origin and destination. Preferably two serpentine chains are provided, physically interdigitated with each other so that electrical shorts between adjacent wire segments will cause a signal applied to one serpentine chain to be detected on the other serpentine chain.

Description: STRUCTURE AND METHOD FOR TESTING WIRING SEGMENTS IN AN INTEGRATED CIRCUIT DEVICE FIELD OF THE INVENTION The invention relates to integrated circuit devices and to a method for testing the devices during manufacturing. More particularly the invention relates to testing of wiring segments in a programmable integrated circuit device. BACKGROUND OF THE INVENTION When an integrated circuit device is being manufactured, it is necessary to test components of the device, preferably all components, for proper operation. For example all transistors must be tested. All antifuses must be tested for non-conductivity in their original state (antifuses can not be tested in their programmed state because the programming is one-time-only and must be left to the user) . All metal lines must also be tested, both for continuity throughout their length and for shorts to adjacent metal lines. A simple means for applying test vectors to the metal lines is preferred in order to facilitate testing. SUMMARY OF THE INVENTION According to the present invention, means are provided for joining metal wire segments into one or more serpentine structures during the testing phase so that a signal applied at one end will be detected at the other end if the metal segments are continuous. Metal segments connected into one serpentine chain can be simultaneously tested for continuity from a single origin and destination. Preferably two serpentine chains are provided, physically interdigitated with each other so that electrical shorts between adjacent wire segments will cause a signal applied to one serpentine chain to be detected on the other serpentine chain. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a first embodiment of the invention. Fig. 2 shows a second embodiment of the invention. Fig. 3 shows a third embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION Fig. 1 shows a plurality of wiring segments LI, L2, and L3, representative of wiring segments in a programmable logic device. During operation of the device, these wiring segments are available for connecting other structures not shown in Fig. 1 to each other or to other wiring segments. According to the invention, transistors such as Tl, T2, and T3 are formed so that when turned on they join the wiring segments into a continuous chain. A test signal TEST is applied to the gates of transistors Tl, T2, and T3 causing the transistors to turn on for interconnecting the wiring segments LI, L2, and L3. A signal applied at A will be detected at AX if the wiring segments have been properly formed so that no defects break the continuity. During operation of the device, transistors Tl, T2, and T3 which interconnect the wiring segments are turned off, so that the wiring segments may be used separately for interconnecting parts of the device as desired. Testing transistors Tl, T2, and T3 can be very small transistors, since they need carry only a small current for continuity testing. In a preferred embodiment, there are two serpentine structures connected as shown in Fig. 2. Physically adjacent metal lines are connected alternately into two different serpentine chains A and B. By electrically isolating alternate metal lines into two different chains, the structure can be tested both for shorts between adjacent metal lines and for continuity of each metal line. The single or double serpentine interconnection method may be used for testing any kind of architecture in which multiple conductive lines must be tested. A single control signal, labeled in Fig. 2 as TEST turns on all transistors simultaneously for testing metal continuity. Fig. 3 shows a third embodiment of the invention. Both horizontal and vertical lines are shown. Separate pairs of serpentine chains are used for testing horizontal and vertical lines. With this arrangement, shorts which may occur at cross-overs between horizontal and vertical lines can be detected. The label H refers to horizontal lines or to transistors or antifuses which interconnect horizontal lines. Likewise, the label V refers to vertical lines or to transistors or antifuses which interconnect vertical lines. For simplicity, not all labels have been shown. Antifuses are used in some programmable devices for interconnecting horizontal and vertical lines. One such antifuse AHV is illustrated in Fig. 3. In an actual device using antifuse interconnect, there would be such antifuses at many of the intersections. Such antifuses are typically formed between conductive lines in adjacent conductive layers of the device. For example, horizontal conductive lines may be formed primarily in first metal and vertical conductive lines may be formed primarily in second metal. .Antifuses formed at the intersections in a layer or layers between first and second metal may be programmed by applying a sufficient voltage difference between lines which contact one antifuse. A structure such as shown in Fig. 3 is particularly useful for testing a device which includes antifuses between horizontal and vertical lines. If antifuse AHV fails to be nonconductive when manufactured, this failure can be detected by applying a particular test signal, for example 5 volts, to node A and detecting this voltage at node DX. If antifuse AHV were properly formed, no current flow between node A and node DX would be detected during testing. From the above description, many other embodiments will become obvious to those skilled in the art.

Claims: CLAIMS 1. A test structure for testing an integrated circuit device comprising: a plurality of conductive wiring segments (Ll, L2, L3); means (Tl, T2, T3, TEST) for controllably connecting said wiring segments into at least one serpentine chain; means (A) for applying a test signal to one end of said serpentine chain; means (AX) for detecting said test signal at the other end of said serpentine chain. 2. A test structure as in Claim 1 in which said at least one serpentine chain comprises two serpentine chains; said means (A) for applying a test signal to one end of said serpentine chain comprises means (A,B) for applying a test signal to one end of each of said two serpentine chains; and said means (AX) for detecting said test signal at the other end of said serpentine chain comprises means (AX,BX) for detecting said test signal at the other end of each of said two serpentine chains. 3. A test structure as in Claim 2 in which: said two serpentine chains comprises two horizontal serpentine chains formed primarily from horizontal wiring segments and two vertical serpentine chains formed primarily from vertical wiring segments; said means (A,B) for applying two test signals to one end of each of said two serpentine chains comprises means (A,B,C,D) for applying two test signals to one end of each horizontal serpentine chain and two test signals to one end of each vertictal serpentine chain; and said means (AX,BX) for detecting two test signals the other end of each of said two serpentine chains comprises means (AX,BX,CX,DX) for detecting two test signals at the other end of each horizontal serpentine chain and t i test signals at the other end of each vertictal serpentine chain. 4. A method for T-s ing wiring segments in an integrated circuit device c. - ~ i.sing the steps of: connecting said ring into at least one serpentine ch applying a test s_ 1 to one end of said serpentine chain; detecting said test signal at the other end of said serpentine chain. 5. A method for testing wiring segments as in Claim 4 in which said step of connecting comprises connecting said wiring segments into two serpentine chains interdigitated with each other such that wir. segments forming one chain are physically close to wiring segments forming the other chain; said step of applying a test signal to one end of said serpentine chain comprises applying two test signals to one end of each of said serpentine chains; and said step of detecting said test signal at the other end of said serpentine chain comprises detecting test signals at the other ends of each of said serpentine chains. 6. A test structure for testing an integrated circuit device comprising: a plurality of conductive wiring segments (Ll, L2, L3 ) ; means (Tl, T2, T3 , TEST) for controllably connecting said wiring segments into at least two serpentine chains; means (A) for applying a test signal to one end of one of said serpentine chains; means (BX) for detecting said test signal at one end of the other of said serpentine chains. 7. A test structure as in Claim 6 in which said one of said serpentine chains is formed in a first conductive layer, and said other of said serpentine chains is formed in a second conductive layer. 8. A test structure as in Claim 7 in which antifuses are formed between crossovers of at least some of said serpentine chains, whereby said means for detecting said test signal at one end of the other of said serpentine chains is able to detect shorts in said antifuses. 9. A test structure as in Claim 6 in which said two serpentine chains are formed in the same conductive layer.

Inventors: CARPENTER ROGER D, GOETTING F ERICH, TONG VINCENT L, CARPENTER, ROGER, D., GOETTING, F., ERICH, TONG, VINCENT, L.
Applicants: XILINX INC, XILINX, INC.
Application year: 1993
Main classification: G01R31
IPC codes: G01R31, H01L21, H03K19