Method of writing data into a semiconductor nonvolatile memory

Abstract: The present invention provides a method of writing data into and erasing it from a semiconductor nonvolatile memory having two diffusion layers (19, 20) formed in a semiconductor substrate (11), a floating gate (13) formed on a layer between the two diffusion layers, a control gate (15) and a select gate (18) formed on a side portion of the control. The method is achieved by applying a potential enabling a channel to be formed between the two diffusion layers (19, 20) to the control gate (15), applying a potential preventing the channel from being formed therebetween to the select gate (18), injecting an electric charge into the floating gate (13) without causing current to flow between the diffusion layers and writing data into the semiconductor nonvolatile memory. Using this method, the memory can be operated with low energy and the number of times in which the data is reloaded or rewritten can be made greater.

Description: Background of the Invention This invention relates to a method of writing data into semiconductor nonvolatile memory. As electrically data-reloadable ROMs (Read Only Memory), there has heretofore been proposed various flash EEPROMS (Electrical Erasable and Programmable ROM) memory cells. For example, a sidewall type flash EEPROM cell has been described in "IEDM 1989 P. 603 TO 606 'A New Flash-Erase EEPROM CELL With a Sidewall Select-Gate on its Source Side' K. Naruke et al." In this type of sidewall type flash EEPROM cell, the writing of data therein is effected by injecting hot electrons thereof into a floating gate. In this case, an energy of 3.1eV or higher is required to write the data in the sidewall type flash EEPROM cell in view of the structure of the sidewall type flash EEPROM cell to be described later. Further, when the data is written into the cell under such high energy, the number of times in which the data is rewritten or reloaded reaches several thousands or so. The article "EEPROM adapts easily to in-system changes" by F. Jones et al. published in Electronics Design, vol. 31 (1983) Aug. No.17, pages 191-196, (corresponding to the preamble of claim 1) describes a method of programming a Flash EEPROM. The Flash EEPROM described comprises first and second diffusion regions formed on a p-well, which diffusion regions are termed the drain and the source respectively. Formed over the p-well, in between the drain and the source, is a silicon nitride layer with an ultra-thin tunnelling layer of silicon dioxide between the substrate and the nitride layer. The nitride layer, which acts as a floating gate, is formed between and partly overlapping an isolation gate and a selection gate. Furthermore a storage gate is formed above the nitride layer. A first channel region exists in the upper surface of the p-well substrate beneath the nitride adjacent the p-well substrate, a second channel region exists beneath the isolation gate and a third channel region exists beneath the select gate; each of these channel regions may be inverted by the application of a sufficiently large voltage to the respective gate immediately above the channel region, or, in the case of the first channel region by the application of a suitable voltage to the storage gate. The method of programming described involves applying a high voltage (about 20V) to the storage gate, a similarly high voltage to the selection gate and a low voltage (about 0V) to the drain. The application of these voltages inverts the first and third channel regions and allows charge to be transferred to the nitride layer by electron tunnelling from the first channel region to the nitride layer via the ultra-thin silicon oxide tunnelling layer. US Patent No. 5,045,491 describes a non volatile memory array having cells with separate program and erase regions. It also describes a method of programming individual cells of this array by applying a preselected programming voltage (of about 16-18V) to a selected Row Line and a second preselected voltage (of about 6 to 7V) to the deselected Row Lines, the Row Lines being connected to each of the control gates of a row of cells. The selected source line is held at approximately OV while the deselected source lines are held at the second preselected voltage; each source line is connected to each of the sources of a column of cells. Finally, all of the drain lines are held at the second preselected voltage, the drain lines connecting the drains of a column of cells. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of writing data into a semiconductor nonvolatile memory, wherein a data writing operation can be made with a low energy of 3V or lower and the number of times in which data can be reloaded can be increased. According to the present invention, for achieving the above object, there is provided a method of writing data into a semiconductor nonvolatile memory having a source and a drain diffusion region, a control gate and a floating gate disposed over a first channel region, and a select gate disposed over a second channel region which is located between the first channel region and the source diffusion region, said method comprising the steps of: applying a first potential to the control gate so that the first channel region is inverted; simultaneously applying a second potential to the select gate so that the second channel region is not inverted; and simultaneously applying a third potential to the drain diffusion region so that an electric charge is transferred by tunnelling from the drain diffusion region into the floating gate through the first channel region the method being characterised in that the floating gate is partially disposed over the drain diffusion region and extends over substantially the whole of the first channel region which is located adjacent to and adjoining the drain diffusion region. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a sidewall type flash EEPROM cell; Fig. 2 is a view for describing a first method of writing data into a sidewall type flash EEPROM cell, according to a first embodiment of the present invention; Fig. 3 is a circuit diagram showing a memory device in which a plurality of N type and sidewall type flash EEPROM cells have been arranged; Fig. 4 is a view for describing a second method of writing data into a sidewall type flash EEPROM cell, according to a second embodiment of the present invention; Fig. 5 is a view for describing a method of erasing data from a sidewall type flash EEPROM cell; and Fig. 6 is a graph for describing the relationship between the number of times in which data is repeatedly written and erased and a threshold voltage (V t ) at the time that data is written under the action of conventional hot electrons and data is written into the sidewall type flash EEPROM cell according to the first embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view showing a sidewall type flash EEPROM cell. FIG. 2 is a view for explaining a first method of writing data into a sidewall type flash EEPROM cell, according to a first embodiment of the present invention. The configuration of the sidewall type flash EEPROM cell shown in FIG. 1 will first be described. A gate insulative film 12 having a film thickness ranging from 50 Å to 150Å (1Å = 0.1 nm) is formed on a monocrystalline silicon substrate 11. A floating gate 13 composed of polycrystalline silicon is deposited on the gate insulative film 12. Further, an insulative film 14 is formed on the floating gate 13 and a control gate 15 composed of the polycrystalline silicon is fabricated on the insulative film 14. An insulative film 16 is formed on the monocrystalline silicon substrate 11. A sidewall type select gate 18 made up of the polycrystalline silicon is formed on the insulative film 16. The sidewall type select gate 18 is insulated from the floating gate 13 and the control gate 15 by an insulative film 17. Next, a drain diffusion layer 19 and a source diffusion layer 20 are formed on the surface of the monocrystalline silicon substrate 11. The drain diffusion layer 19 is formed on the floating gate 13 side, whereas the source diffusion layer 20 is formed on the select gate 18 side. The first data writing method according to the present invention will now be described with reference to FIG. 2. FIG. 2 is a cross-sectional view of an N type and sidewall type flash EEPROM cell. N-type impurities are implanted into the drain diffusion layer 19 and the source diffusion layer 20. The same elements of structure as those shown in FIG. 1 are identified by the same reference numerals. A drain voltage V D applied to the drain diffusion layer 19, a control gate voltage V CG applied to the control gate 15, a select gate voltage V SEL applied to the select gate 16, a source voltage V S applied to the source diffusion layer 20 and a substrate voltage applied to the silicon substrate 11 will be set as 0V, 18V, 0V, 0V and 0V respectively. However, the source voltage is not necessarily limited to 0V. The source voltage may be about 10V or below or may be a floating state. An inversion layer 26 is formed on the surface of the monocrystalline silicon substrate 11 below the floating gate 13 under such applied voltages. The inversion layer 26 is made up of electrons supplied from the drain diffusion layer 19 by a difference in potential between the drain voltage V D and the control gate voltage V CG . The electrons in the inversion layer 26 and those in the drain diffusion layer 19 are attracted to the control gate 15 to which the high voltage (V CG ) has been applied. Thereafter, these electrons pass through the gate insulative film 12 so as to be injected into the floating gate 13. The flow of the electrons in the gate insulative film 12 is called "Fowler/Nordheim tunnel current". An arrow in FIG. 2 shows a direction of a movement of electrons. Therefore, a direction of the current flow is opposite to the direction of the arrow shown FIG. 2. Thus, data is written into the sidewall type flash EEPROM cell by injecting the electrons into the floating gate 13. Further, the above operations will be described in connection with the case where the cell shown in FIG. 2 is arranged in plural form. FIG. 3 is a circuit diagram showing a memory device wherein the N type and sidewall type flash EEPROM cell shown in FIG. 2 is arranged in plural form. Respective cells A00 through A22 are arranged in the form of a matrix of 3x3. Elements of structure of the cell A11, which correspond to those shown in FIG. 2, are identified by the same reference numerals. Similarly to the cell A11, elements of structure of other respective cells also correspond to those shown in FIG. 2. However, their reference numerals are omitted. The drain diffusion layers 19 of the cells A0X (X = 1, 2, 3) are respectively electrically connected to one another by a bit line B0. The drain diffusion layers 19 of the cells A1X (X = 1, 2, 3) are respectively electrically connected to one another by a bit line B1. The drain diffusion layers 19 of the cells A2X (X = 1, 2, 3) are respectively electrically connected to one another by a bit line B2. The control gates 15 of the cells AX0 (X = 1, 2, 3) are respectively electrically connected to one another by a word line W0. The control gates 15 of the cells AX1 (X = 1, 2, 3) are respectively electrically connected to one another by a word line W1. Further, the control gates 15 of the cells AX2 (X = 1, 2, 3) are respectively electrically connected to one another by a word line W2. The select gates 18 of the cell AX0 (X = 1, 2, 3) are respectively electrically connected to one another by a select line S0. The select gates 18 of the cells AX1 (X = 1, 2, 3) are respectively electrically connected to one another by a select line S1. The select gates 18 of the cells AX2 (X = 1, 2, 3) are respectively electrically connected to one another by a select line S2. The source diffusion layers 20 of the respective cells are grounded. Each of the source diffusion layers 20 may be set to a floating state. A description will now be made of the case where data is written into the cell A11 of the cells A00 through A22 electrically connected to one another as described above. Voltages of 0V, 18V and 0V are applied to or across the bit line B1 (selection bit line), the word line W1 (selection word line) and the select line S1 (selection select line) respectively. At this time, the Fowler/Nordheim tunnel current 23 flows in the gate insulative film 12 so as to store an electric charge in the floating gate 13. At this time, the bit lines B0, B2 (non selection bit lines), the word lines W0, W2 (non selection word lines) and the select lines S0, S2 (non selection select lines) should be respectively supplied with voltages which do not cause variations in the quantity of electric charges already stored in the respective floating gates of the memory cells (A00, A01, A02, A10, A12, A20, A21 and A22) other than the cell A11. The application of the voltages to their corresponding lines will be described below. The memory cells A10 and A12 are first electrically connected to the selection bit line B1 (0V). Thus, a voltage of 0V, for example, which does not cause the gate insulative films 12 of the memory cells A10 and A12 to conduct the Fowler/Nordheim tunnel current 23, is applied to each of the non selection word lines W0 and W2 electrically connected to these memory cells A10 and A12. Next, the memory cells A01 and A21 are electrically connected to the selection word line W1(18V). Thus, a voltage, which does not cause the gate insulative films 12 of the memory cells A01 and A21 to conduct the Fowler/Nordheim tunnel current 23, is applied to each of the non selection bit lines B0 and B2 electrically connected to these memory cells A01 and A21. When a voltage of 5V, for example, is applied to each of the non selection bit lines B0 and B2, the Fowler/Nordheim tunnel current 23 does not flow into the gate insulative films 12 of the memory cells A01 and A02 even if the voltage applied across the selection word line W1 is 18V. Thus, when the voltage of 0V is applied across each of the non selection word lines W0 and W2 and the voltage of 5V is applied across each of the non selection bit lines B0 and B2, the quantity of the electric charges stored in the floating gates 13 of the memory cells A00, A02, A20 and A22 respectively electrically connected to the non selection word lines and the non selection bit lines does not vary. The role of the selection select line S1 is to prevent the inversion layer 26 and the source diffusion layer 20 from electrically conducting, the manner of which has been described with reference to FIG. 2. If the voltage applied to the selection select line S1, i.e., the select gate voltage V SEL shown in FIG. 2 is of such a voltage that the inversion layer can be formed on the surface of the monocrystalline silicon substrate 11 below the select gate 18, the source diffusion layer 20 and the drain diffusion layer 19 are brought into a conducting state. Since the source diffusion layer 20 is grounded in this case, the surface of the monocrystalline silicon substrate 11 is brought to 0V. Since the selection word line W1 is maintained at a high potential of 18V, the electrons flowing between the source diffusion layer and the drain diffusion layer are injected into the floating gate. The movement of the electrons to the floating gate occurs in each of the non selected memory cells A01 and A21 to thereby produce miswriting. In order to avoid such miswriting, the selection select line S1 is supplied with such a voltage that the inversion layer 26 is electrically disconnected from the source diffusion layer 20. When the select voltage V SEL is 0V as shown in FIG. 2, for example, the inversion layer 26 is not formed on the surface of the monocrystalline silicon substrate 11 below the select gate 18. As a result, the source diffusion layer and the drain diffusion layer in each of the non selected memory cells A01 and A21 are kept in non conduction. Therefore, the miswriting is no longer produced. It is thus necessary to take into consideration the voltage applied to the select gate 18 or the width of the select gate 18 so that conducting current does not flow between the source and drain thereof. A second embodiment of the present invention will now be described below. FIG. 4 is a view for describing a second method of writing data into a sidewall type flash EEPROM cell according to the second embodiment of the present invention. Figure 4 illustrates a well-layer as the silicon substrate 11. The sidewall type flash EEPROM cell shown in FIG. 4 is identical in structure to that illustrated in FIG. 1. The same elements of structure as those shown in FIG. 1 are identified by the same reference numerals. N-type impurities are implanted into a source diffusion layer and a drain diffusion layer. The second data writing method according to the present invention will first be described. A drain voltage V D , a control gate voltage V CG , a select gate voltage V SEL , a source voltage V S and a well-layer voltage are set to -5V, 13V, -5V, -5V and -5V respectively. However, it is difficult that the substrate voltage keep to -5V . Therefore, a well-layer voltage V W applied to the well layer formed within the substrate is set to -5V. In a manner similar to the first data writing method which has been with reference to FIG. 2, an inversion layer 26 is formed on the surface of a monocrystalline silicon substrate 11 provided below a floating gate 13 even under the applied voltages referred to above. The inversion layer 26 is made up of electrons supplied from a drain diffusion layer 19 by a difference in potential between the drain voltage V D and the control gate voltage V CG . The drain diffusion layer 19 are attracted to a control gate 15 to which the high voltage (V CG ) has been applied. Thereafter, these electrons pass through a gate insulative film 12 so as to be injected into the floating gate 13. Thus, data is written into the sidewall type flash EEPROM cell by injecting the electrons into the floating gate 13. Further, the quantity of electric charges stored in the floating gate of each non selected memory cell does not vary due to the setting of the non selection word and bit lines to -5V and 0V. A description will now be made of the case where the sidewall type flash EEPROM cell employed in the present invention can be activated under an applied voltage of 3V. In the data writing method according to either first or second embodiment of the present invention, when each of the gate insulative layers 12 shown in FIGS. 2 and 4 ranges in thickness from 60Å to 100Å, the difference in potential between the control gate 15 and the drain diffusion layer 19 requires a voltage range of about 12V to 20V to produce the Fowler/Nordheim tunnel current 23. This potential difference is large as compared with the case where data is written under the action of the conventionally-used hot electrons. However, when it is desired to write data using the Fowler/Nordheim tunnel current, the required amount of current is much less because of several pAmps per cell. Thus, even if an external power source is of 3V, the required current can be produced by an internal booster circuit. Since data represented in the form of 10kbits or so can be written at one time if the internal boosting capability of the internal booster circuit is rated to 10µA, the data can be written at a high speed. A description will next be made of a method of erasing data. FIG. 5 is a view for describing a method of erasing data from a sidewall type flash EEPROM cell. The sidewall type flash EEPROM cell illustrated in FIG. 5 is substantially identical in structure to that shown in FIG. 1. However, reference numeral 11' indicates a P-type well layer formed within a monocrystalline silicon substrate 11. Components of the sidewall type flash EEPROM cell shown in FIG. 5, which correspond to those of the sidewall type flash EEPROM shown in FIG. 1, are identified by like reference numerals. N-type impurities are implanted into a source diffusion layer and a drain diffusion layer. A drain voltage V D , a select gate voltage V SEL and a source voltage V S are respectively set to an open state. Further, a control gate voltage V CG and a well-layer voltage V W applied to the well layer 11' formed within the monocrystalline substrate 11 are set to -9V and 9V respectively. In this condition, Fowler/Nordheim tunnel current 27 flows from the substrate to the floating gate through a gate insulative film 12. Therefore, the electrons stored in the floating gate 13 move into the surface of the monocrystalline silicon substrate 11 through the gate insulative film 12. This function is called to "erasing data". According to the data erasing method as described above, the electric charge stored in the floating gate 13 can be transferred over the entire surface of the monocrystalline silicon substrate 11. As a result, a large current does not flow locally and the gate insulative film can be prevented from deterioration. Further, the number of times in which data is rewritten or reloaded can also be increased. FIG. 6 is a graph for describing the relationship between the number of times in which data is repeatedly written and erased and a threshold voltage (V T ) at the time that data is written under the action of the conventional hot electrons and data is written into the sidewall type flash EEPROM cell employed in the first embodiment of the present invention. Here, the threshold voltage (V T ) represents a voltage at the time that current begins to flow between the source diffusion layer and the drain diffusion layer when the voltage applied to the control gate is varied. Further, a represents the result of the number of times vs threshold voltage, which has been obtained in conventional data writing, b shows the result of the number of times vs threshold voltage, which has been obtained in data writing according to the present invention, c represents the result of the number of times vs threshold voltage, which has been obtained in conventional data erasing, and d shows the result of the number of times vs threshold voltage, which has been obtained in data erasing. Thus, when the number of times in which the data is written and erased in accordance with the conventional method, is about 10 3 , the threshold voltage is brought to -4V or higher after the erasion of the data. Even when, on the other hand, the number of times in which data is written in accordance with the method of the present invention, is 10 4 or more, the threshold voltage is brought to -4V or lower after the erasion of the data. As a result, the number of times in which the data is reloadable can be improved. Incidentally, the erasion of the data was made in accordance with a drain-tunnel erasing method.

Claims: A method of writing data into a semiconductor nonvolatile memory having a drain (19) and a source (20) diffusion region, a control gate (15) and a floating gate (13) disposed over a first channel region (26), and a select gate (18) disposed over a second channel region which is located between the first channel region (26) and the source diffusion region (20), said method comprising the steps of: applying a first potential to the control gate (15) so that the first channel region (26) is inverted; simultaneously applying a second potential to the select gate (18) so that the second channel region is not inverted; and simultaneously applying a third potential to the drain diffusion region (19) so that an electric charge is transferred by Fowler-Nordheim tunnelling from the drain diffusion region (19) into the floating gate (13) through the first channel region (26) the method being characterised in that the floating gate (13) is partially disposed over the drain diffusion region (19) and extends over substantially the whole of the first channel region (26) which is located adjacent to and adjoining the drain diffusion region (19). A method according to claim 1, wherein the first potential is 10V or higher, the second potential is OV, and the third potential is OV. A method according to claim 1, wherein the first potential and the second potential have the opposite polarity each other and a voltage difference between the first and second potentials is 10V or higher. A method according to claim 1, wherein a voltage of the third potential is substantially equal to that of the second potential.

Inventors: ONO TAKASHI, ONO, TAKASHI, ONO, TAKASHI, C/O OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1993
Main classification: H01L29
IPC codes: G11C16, H01L29, G11C17, H01L21, H01L27