Level detection circuit and automatic color control circuit

Abstract: A level detection circuit for detecting the level of input signals is disclosed. The level detection circuit includes a multiplier and an adder for computing the sums of square values of a burst signal, a maximum value holding circuit for holding a maximum value of the sums of the squared values of the burst signal, a counter for counting sampling clocks, a multiplier, an adder and a 1/2 processing circuit for computing a half value of the sum of two consecutive count values, and a delay circuit, a latch circuit and a comparator for outputting a first one of the two consecutive count values as a level of the burst signal when an output of the 1/2 processing circuit becomes larger than the output of the maximum value holding means. The present level detection circuit permits level detection by finding a square value by a small-sized circuit.

Description: This invention relates to a level detection circuit for detecting the signal level of input signals and, more particularly, to such circuit employed in an automatic color saturation control (ACC). A television receiver or video tape recorder, for example, is provided with an automatic color saturation control (ACC) circuit. In the television receiver, if the level difference between luminance signals and the carrier chrominance signals fluctuates due to e.g. fluctuations in the received electrical waves or mismatching of an antenna system, saturation on a display screen is changed in an irregular manner. Besides, solely the color saturation may be changed by channel switching. Consequently, the aforementioned ACC circuit is built into the television receiver for automatically adjusting the gain of the bandwidth amplifying circuit which is operated for maintaining a constant level of the carrier chrominance signals applied to a demodulation circuit. The ACC circuit, which compares a burst amplitude value to a reference value for controlling the gain for maintaining the color saturation at all times at a constant level, is arranged as shown for example in Fig. 1 of the accompanying drawings. In this figure, carrier chrominance signals are supplied to an input terminal 21 of the ACC circuit and thence supplied to a level detection circuit 25 via a multiplier 23. The level detection circuit 25 detects the level of the carrier chrominance signals. Since the chroma level is decided by the level of a burst signal, the level detection circuit 25 detects the level of the carrier chrominance signal, that is the burst amplitude, when a burst gate pulse supplied via terminal 22 from a sync deflection block of the television receiver is at e.g. a high "H" level. The ACC circuit decides a loop gain by integrating the difference between the level detection output from the level detection circuit 25 and a reference. That is, with this ACC circuit, the level detection output of the level detection circuit 25 is supplied as an additive signal to an additive node 26 also supplied with a predetermined reference value as a subtractive signal from a level reference value generating circuit 28. A difference output between the level reference value and the level detection output is produced by the additive node 26 so as to be supplied to an integrating circuit 27. An integrated output of the integrating circuit 27 is supplied as a multiplication coefficient to the multiplier 23. The carrier chrominance signal from multiplier 27 is multiplied by the multiplication coefficient from the integrating circuit 27. A multiplication signal from multiplier 23 is outputted as ACC output at an output terminal 24 so as to be supplied to a downstream decoder, not shown. The aforementioned burst gate pulse is generated in the following manner. For example, horizontal synchronization signal H SY is extracted from a composite video signal shown in Fig.2, by a sync separator, not shown, provided within he deflection system. The horizontal synchronization signal H SY is differentiated, as shown in Fig.3, and a rising part of the differentiated waveform is cut along a threshold value V TH for producing the aforementioned burst gate pulse which is a pulse having a position corresponding to the burst period. Meanwhile, in the above-mentioned level detection circuit 25, shown in Fig.1, a square root value is found for finding the burst amplitude of the color chrominance signals. Typical of the prior-art arrangements for finding the square root is an arrangement employing a read-only memory (ROM). However, if higher precision in square root calculation is desired in the arrangement for finding the square root by ROM, the number of address bits of ROM and the number of bits of data stored in ROM are increased so that the ROM of a larger capacity in required and hence the circuit is undesirably increased in size. In view of the above-depicted state of the prior art, it is an object of the present invention to provide a level detection circuit whereby level detection can be made by finding a square root by a circuit having a smaller circuit size. It is another object of the present invention to provide an ACC circuit which has improved precision despite the small circuit size. Each of the foregoing and additional objects are achieved by the provision of a level detection circuit and an ACC circuit employing the level detection circuit according to the present invention. In its one aspect, the present invention provides a level detection circuit for detecting a level of input signals comprising a first square value computing means for computing a squared value of the input signal level, count means for counting predetermined clocks, second square value computing means for computing a square of a count value of the count means, and level decision means for outputting the level of the input signals as the count value of the count means when an output of the second square value computing means exceeds an output of the first square value computing means. In another aspect, the present invention provides a level detection circuit for detecting a level of input signals comprising a first square value computing means for computing a square of the input signal level, count means for counting predetermined clocks, second square value computing means for computing a half value of the sum of two consecutive count values of the count means, and level decision means for outputting the level of the input signals when an output of the second square value computing means exceeds an output of the first square value computing means. In still another aspect, the present invention provides a level detection circuit for detecting the level of a burst signal comprising an A/D converter for sampling the burst signal having a frequency f sc with sampling clocks having a frequency of 4 f sc , a first square value computing means for computing the sum of square values of two consecutive output data of the A/D converter, a maximum value holding circuit for holding a maximum value of outputs of the first square value computing means within a burst pulse period, count means adapted for counting the sampling clocks and being reset by the burst gate pulse, second square value computing means for computing a half value of the sum of two consecutive count values of the count means outside the burst gate pulse period, and level decision means for outputting a first one of the two consecutive count values as a level of the burst signal when an output of the second square value computing means becomes larger than the output of the maximum value holding means. In yet another aspect, the present invention provides an ACC circuit comprising multiplication means for multiplying an image signal containing a burst signal having a frequency f sc with a predetermined coefficient, an A/D converter for sampling an output of the multiplication means with sampling clocks having a frequency of 4 f sc , first square value computing means for computing the sum of squared values of two consecutive output data of the A/D converter, a maximum value holding circuit for holding a maximum value of outputs of the first square value computing means within a burst pulse period, count means adapted for counting the sampling clocks and for being reset by the burst gate pulse, second square value computing means for computing a half value of the sum of two consecutive count values of the count means outside the burst gate pulse period, level decision means for outputting a first one of the two consecutive count values as a level of the burst signal when an output of the second square value computing means becomes larger than the output of the maximum value holding means, addition means for adding an output of the level decision means to a predetermined reference signal, and integrating means for integrating an output of the addition means for generating the predetermined coefficient. The present invention will be further described by way of example only in the following detailed description of preferred embodiments with reference to the accompanying drawings, in which like reference numerals are used to identify the same or similar parts in the several views:- Fig.1 is a schematic block circuit diagram showing an arrangement of a conventional ACC circuit. Fig.2 is a waveform diagram for illustrating a composite video signal and a burst gate pulse. Fig.3 is a waveform diagram for illustrating a method for generating the burst gate pulse shown in Fig.2. Fig.4 is a schematic block circuit diagram showing an arrangement of a level detection circuit according to the present invention. Fig.5 is a waveform diagram for illustrating the manner of sampling of burst signals. Fig.6 is a timing chart showing waveforms of signals appearing at a counter. Referring to the drawings, preferred embodiments of the present invention will be explained in detail. The level detection circuit of the present embodiment is employed as a level detection circuit for e.g. the above-mentioned ACC circuit. The level detection circuit for detecting a level of input signals according to a preferred embodiment of the present invention comprises first square value computing means for computing a squared value of input signals, count means for counting predetermined clocks, second square value computing means for computing a square value of a count value of the count means, and level decision means for outputting the level of the input signals as the count value of the count means when an output of the second square value computing means exceeds an output of the first square value computing means. That is, the level detection means embodying the present invention comprises, besides the first square value computing means and the count means, second square value computing means for computing a half value of the sum of two consecutive count values of the count means, and level decision means for outputting the level of the input signals when an output of the second square value computing means exceeds an output of the first square value computing means. Specifically, the level detection circuit according to the present embodiment comprises, as shown in Fig.4, a multiplier 2 and an additive node 3, as first square value computing means, for computing the sum of square values of two consecutive data of a burst signal of a frequency f sc sampled with sampling clocks of a frequency 4 f sc , a maximum value holding circuit 4 for holding a maximum value of outputs of the first square value computing means within a burst gate pulse period, a counter 5 adapted for counting the sampling clocks and being reset by the burst gate pulse, a multiplier 2, additive node 3 and a 1/2 processing circuit 8, as second square value computing means, for computing a half value of the sum of two consecutive count values of the counter 5 outside the burst gate pulse period, and a delay circuit 6, latch circuit 7 and a comparator 9, as level decision means, for outputting a first one of the two consecutive count values as an approximate value of the level of the burst signal, that is as an approximate value of a square root, when an output of the second square value computing means becomes larger than the output of the maximum value holding means. In Fig.4, an output signal of the multiplier 23 of Fig.1 supplied to an input terminal 1 (ACC output signal) is supplied to a fixed terminal a of a selector 11 via an 8-bit analog/ digital (A/D) converter 10 which is operated based on a sampling clock of a sampling frequency of 4 f sc supplied from terminal 13. This selector 11 is switched over responsive to the burst gate pulse supplied to terminal 14. Specifically, the selector 11 has its movable contact set to the fixed terminals a and b when the burst gate pulse is "H" and "L", respectively. When the burst gate pulse becomes "H" so that the selector 11 is set to the side of the fixed terminal a , the sampled ACC output data is transmitted to multiplier 2 via selector 11. The multiplier 2 squares the ACC output data supplied thereto to find a square value which is supplied to an additive node 3. The additive node 3 is also supplied with an output of the multiplier 2 via a delay circuit Z -1 which delays an input signal by one clock. Thus the sum of two squared consecutive ACC output data is found by additive node 3. That is, in the present embodiment, if the frequency of the burst signal is the above-mentioned frequency f sc and the frequency of the sampling clocks is 4 f sc , the phase difference between adjacent data, that is the phase difference between two adjacent sampled data, becomes equal to 90°. Thus, if the amplitude of the burst signal is A and an arbitrary data in this domain is A cos , a data preceding the arbitrary data A cos is A sin. In other words, if the amplitude of the burst signal is A and a reference sampling data is A sin, the next following sampling data becomes A sin( + 90°) = A cos If these two data are squared by multiplier 2 and the squared values are summed together at the additive node 3, the result becomes equal to A 2 as shown by the following formula (2) (A cos) 2 + (A sin) 2 = A 2 In this manner, the sum of the squared values of the two consecutive ACC output data, that is the squared value of the burst level, is produced. The squared value A 2 of the burst level from additive mode 3 is supplied to the maximum value holding circuit 4. The maximum value holding circuit 4 is operated responsive to the burst gate pulse and holds a maximum value A 2 max among plural squared values A 2 from the additive node 3 during the time the burst gate pulse remains "H". An output of the maximum value holding circuit 4 (maximum value A 2 max ) is transmitted to a comparator 9. If the burst gate pulse goes low "L", counter 5 counts the sampling clocks to output a count value C n . Also the counter 5 is reset when the burst gate pulse goes high "H". The count value C n of the sampling clocks, outputted from counter 5 when the burst gate pulse becomes "L", is transmitted to a delay circuit 6 while being simultaneously supplied to the fixed terminal b of the selector 11. At this time, the selector 11 has its movable contact set to the side of the fixed terminal b when the burst gate pulse becomes "L", so that the count value C n from the counter 5 is transmitted via selector 11 to multiplier 2. The count value C n , transmitted to multiplier 2, is squared by the multiplier 2 (C n 2 ) and subsequently transmitted to the additive node 3 and to the delay circuit 12. The additive node 3 adds the output data C n 2 of the multiplier 2 to the squared value C n-1 2 of the count value preceding the above count value C n by one clock. An output (C n 2 + C n-1 2 ) of the additive node 3 is supplied to a 1/2 processing circuit 8. Meanwhile, the maximum value holding circuit 4 is not in operation because the burst gate pulse is "L". The 1/2 processing circuit 8 performs an operation of finding a halved value of the output data (C n 2 + C n-1 2 ), that is. (C 2 = (C n 2 + C n-1 2 )/2). That is, in the 1/2 processing circuit 8, a halved value of the sum of the squared values of the two consecutive count values outside the burst gate pulse period is found. An output C 2 of the 1/2 processing circuit 8 is supplied to the comparator 9. The comparator 9 compares the maximum value A 2 max from the maximum value holding circuit 4 to the output C 2 from the 1/2 processing circuit 8 from time to time. The comparator 9 outputs, at a time point when the output C 2 from the 1/2 processing circuit 8 becomes larger than the maximum value A 2 max from the maximum value holding circuit 4, a signal which is changed in level to high "H" from low "L". This output signal is supplied to a latch circuit 7. The latch circuit 7 is supplied with the count value C n-1 from counter 5 delayed by the delay circuit 6 which introduces a one-clock delay to its input signal. That is, when the burst gate pulse becomes "L" and the squared value C 2 of the count value of the counter 5 becomes larger than the maximum value A 2 max , the first of the two consecutive count values, that is the count value C n-1 , is stored by the latch circuit 7. The data of the latch circuit 7 is the count value of the counter 5 which temporally precedes the squaring operation by the multiplier 2. In the present embodiment, the count value C n-1 is employed as an approximate value of the square root of the burst level (A 2 max ). The output of the latch circuit 7 is outputted at an output terminal 15 as a level detection output of the present level detection circuit. Meanwhile, with standardized signals, such as television signals, the frequency of the burst signal f sc and the frequency of the horizontal synchronization signal f H is related to each other by a formula 4 f sc = 910 f H . That is, if the sampling frequency f s is set for example to f s = 4 f sc , there are 910 clocks having the frequency of f s between adjacent horizontal synchronization signals. On the other hand, since the A/D converter is of an 8-bit type, the counter 5 of an 8-bit type suffices for measuring the burst signal level. Since the 8-bit counter 5 is employed in the present embodiment, and 2 8 = 256, the burst level may be measured while a 256 number of clocks having the frequency of f s are counted during a1/f H interval. That is, the burst level detection is achieved during a count-up interval of counter 5, as may be seen from a timing chart of Fig.6. It may be seen from Fig.3 that counter 5 counts clocks having the frequency of 4 f sc and directly outputs the count value. It is noted that, when the count value of the counter 5 is squared and the resulting squared value is compared by comparator 9 to the maximum value A 2 max a processing of C 2 = (C n 2 + C n-1 2 )/2 is carried out in the 1/2 processing circuit 8. Alternatively, the squared value C n2 , obtained by squaring the output of counter 5 by multiplier 2, may be directly supplied to comparator 9 without being transmitted through additive node 3, delay circuit 12 and 1/2 processing circuit 8. However, in this case, the level detection output of the latch circuit 7 as an approximate value of (A 2 max ) becomes slightly lower in accuracy. Referring to Fig.7, which is a level chart for detection of the ACC level, the accuracy of (A 2 max ) is hereinafter explained. First, as shown at (a) in Fig.7, when the maximum value A 2 max is directly compared to the squared value C n 2 of th n'th count by the counter 5 for producing an approximate solution of √(A 2 max ), the count value of counter 5 is stored for c n = 'A when the maximum value A 2 max is produced at time T 1 , so that √(A 2 max ) is approximately equal to A - 1. This applies when the maximum value A 2 max is produced at time T 2 as well. On the other hand, when the mean value C 2 of the sum of the squared values C n 2 and C n-1 2 of counter 5 is compared to the above-mentioned maximum value A 2 max , the count value of counter 5 is stored for c n = A + 1 when the maximum value A 2 max is produced at time T 1 , so that √(A 2 max ) is approximately equal to A. On the other hand, the count value of counter 5 is stored for c n = A when the maximum value A 2 max is produced at time T 2 , so that √(A 2 max ) becomes approximately equal to A - 1. It is seen from Fig.7 that the value of √(A 2 max ) for time T 1 is approximate to A, while the value of √(A 2 max ) for time T 1 is approximate to A -1, so that the value of √(A 2 max ) becomes higher in accuracy when the operation of C 2 = (C n 2 + C n-1 2 )/2 as indicated at (b) in Fig.7 is carried out. From the foregoing it is seen that the level detection circuit of the present invention performs a calculation of finding a squared value by counter 5, and compares the squared value to a value a square root of which is to be fund to set the value of counter 5 as a square root, so that the circuit for finding a square root may be reduced in size to permit level detection using this small-sized circuit. While specific embodiments of the present invention have been shown and disclosed, it is to be understood that numerous changes may be made by those skilled in the art without departing from the scope of the invention as defined in the claims.

Claims: A level detection circuit for detecting a level of input signals characterized by:- a first square value computing means (2, 3) for computing a squared value of input signals, a counter (5) for counting predetermined clock signals, second square value computing means (2, 3, 8) for computing a value related to a count value of said counter (5), and level decision means (7, 9) for outputting the level of said input signals as the count value of said count means when an output of said second square value computing means (2, 3, 8) exceeds an output of said first square value computing means (2, 3). A level detection circuit according to claim 1 wherein the second square value computing means (2, 3, 8) is for computing a square of the count value. A level detection circuit according to claim 1 wherein the second square value computing means (2, 3, 8) is for computing a half value of the sum of two consecutive count values of said counter (5). A level detection circuit according to claim 1, 2 or 3 for detecting a level of a burst signal having a frequency f sc , comprising an A/D converter (10) for sampling said burst signal with a sampling clock having a frequency of 4 f sc , the first square value computing means (2, 3) being connected to compute the sum of square values of two consecutive output data of said A/D converter (10) and said counter (5) being reset by said burst gate pulse, a maximum value holding circuit (4) for holding a maximum value of outputs of said first square value computing means (2, 3) within a burst pulse period, said second square value computing means (2, 3, 8) being adapted to compute a half value of the sum of two consecutive count values of said counter (5) outside said burst gate pulse period, and the level decision means (7, 9) being adapted to output a first one of said two consecutive count values as a level of said burst signal when an output of said second square value computing means (2, 3, 8) becomes larger than the output of said maximum value holding means (4). The level detection circuit as claimed in claim 4 wherein said first square value computing means (2, 3) comprises multiplication means (2) for squaring an output of said A/D converter (10), delay means (12) for delaying an output of said multiplication means (2) by one clock pulse, and addition means (3) for adding an output of said multiplication means (2) and an output of said delay means (12). The level detection circuit as claimed in claim 4 or 5 wherein said first square value computing means (2, 3) comprises multiplication means (2) for squaring an output of said counter (5), delay means (12) for delaying an output of said multiplication means (2) by one clock pulse, addition means (3) for adding an output of said multiplication means (2) and an output of said delay means (12), and processing means (8) for computing a half value of said addition means (3). The level detection circuit as claimed in claim 4, 5 or 6 wherein said level decision means (7, 9) comprises delay means (6) for delaying an output of said counter (5) by one clock signal, latch means (7) for latching an output of said delay means (6), and comparator means (9) for causing data to be latched by said latch means (7) when the output of said second square value computing means (2, 3, 8) exceeds the output of said maximum value holding means (4). An ACC circuit for controlling the chroma level of an image signal containing a burst signal having a frequency f sc , and including a level detection circuit according to any one of the preceding claims, the ACC circuit further comprising multiplication means (23) for multiplying said image signal with a predetermined coefficient, and supplying its output to said level detection circuit, addition means (26) for adding an output of the level decision means (7, 9) of the level detection circuit to a predetermined reference signal, and integrating means (27) for integrating an output of said addition means (26) for generating said predetermined coefficient.

Inventors: HOSHINO TAKAYA, TODO HIROFUMI, WATANABE KAZUO, HOSHINO, TAKAYA, TODO, HIROFUMI, WATANABE, KAZUO, Hoshino, Takaya, c/o Sony Corporation, TODO, HIROFUMI, C/O SONY CORPORATION, WATANABE, KAZUO, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H04N9
IPC codes: H04N9