Auto-reset circuit with improved testability

Abstract: A first active element (41) has its first terminal coupled to a first power-supply terminal (31), its second terminal coupled through a resistor (51) to a second power-supply terminal (32), and its third terminal coupled to the second power-supply terminal (32), or to a control signal input terminal that is normally at the same potential as the second power-supply terminal (32). A second active element (42) has its first terminal coupled to the second power-supply terminal (32), its second terminal coupled through a resistor (52) to the first power-supply terminal (31), and its third terminal coupled to the second terminal of the first active element (41). A reset signal is taken from the second terminal of the second active element (42). The control signal can be used to prevent current flow during static current measurements.

Description: BACKGROUND OF THE INVENTION This invention relates to an auto-reset circuit used to initialize an electronic circuit when the electronic circuit is powered up, or when its power supply is momentarily interrupted. When a complex electronic device such as a large-scale-integrated (LSI) circuit is powered up, it must generally be reset by placing its internal circuits in certain initial states. The device must also be reset if its power supply is interrupted during operation, as sometimes happens due to temporary conditions. For these purposes, LSI and other devices often have an auto-reset circuit that detects the rise of the power supply and generates an internal reset signal. Many types of auto-reset circuits can be found in the prior art. One of the simplest comprises a resistor and capacitor coupled in series between the two power-supply terminals, which are commonly referred to as power and ground, or V DD and V SS . The reset signal is taken from a point between the resistor and capacitor. At power-up the reset signal starts with the value of one of the two power-supply potentials, then changes to the value of the other as the capacitor charges. The reset signal can be used directly, or it can be used to drive an output stage such as an inverter or Schmitt trigger. A disadvantage of this simple auto-reset circuit is that it fails to produce a reset signal if the supply voltage rises slowly in comparison to the resistor-capacitor time constant, or if power is interrupted for an interval that is brief in relation to that time constant. To overcome the disadvantages of this simple circuit, many auto-reset circuits incorporating active elements have been developed. The one that comes closest to the present invention has a p-channel metal-oxide-semiconductor field-effect transistor (referred to below as a P-MOSFET) and a resistor coupled in series between the power-supply terminals, the source of the P-MOSFET being coupled to V DD and its drain to the resistor. An n-channel metal-oxide-semiconductor field-effect transistor (referred to below as an N-MOSFET) and another resistor are also coupled in series between the power-supply terminals, the source of the N-MOSFET transistor being coupled to V SS and its drain to the resistor. The gates of both the P-MOSFET and N-MOSFET are coupled to the drain of the P-MOSFET. The reset signal is output from the drain of the N-MOSFET. This circuit produces a reset signal that is initially high, but goes low when the supply voltage reaches a value equal to the sum of the threshold voltages of the two MOSFETs. With the traditional five-volt power supply, the reset signal is typically output while the supply voltage rises from zero to about 1.4 V, then released as the supply voltage rises from 1.4 V to a steady-state 5 V. The recent trend toward three-volt operation has created a problem for this auto-reset circuit, however. The problem arises, for example, during device tests carried out prior to shipment to the customer. Consider a device specified to operate reliably on a 3.0-V ±10% power supply over a temperature range of -40°C to +85°C. The nominal transistor threshold voltage is 0.7 V, but there is a variability of about ±0.25 V inherent in the fabrication process, and further variability results from the temperature dependence of the threshold voltage, so within the above temperature range the threshold voltage may be as high as 1.2 V. If both the P-MOSFET and N-MOSFET have this threshold voltage, then the reset signal will not be released until the supply voltage reaches at least 2.4 V. This would not necessarily be a problem if tests were carried out with supply voltages between 2.7 V and 3.3 V, but to prevent degradation of circuit elements, tests may be performed at a reduced supply voltage such as 2.4 V. When the device is powered up to this voltage, the auto-reset circuit may fail to release the reset signal, causing the device to be rejected as defective. To allow a reasonable margin in such tests, the auto-reset circuit needs to release the reset signal at about 1.9 V. The problem becomes even more serious at lower supply voltages, such as the 1.8 V supply voltage employed in devices driven by two nickel-cadmium cells. For such devices the auto-reset circuit described above is completely unsatisfactory. Another problem that occurs in device testing is that current flow through the above auto-reset circuit cannot be reduced to zero. One of the tests performed to detect photolithography defects and other defects is a measurement of static current consumption (I DD ). The presence of current flow through the auto-reset circuit impairs the precision of this measurement, because the exact amount of current flowing through the auto-reset circuit is unknown. Also, it becomes impossible to characterize the device down to extremely small current values. Thus the test fails to screen out devices having minor defects that may lead to failure in the field. Yet another problem of the above auto-reset circuit is that in some cases it may generate a reset signal with an inadequate pulse width, or fail to output a reset signal at all. This problem occurs not only at power-up, but also when the supply voltage drops momentarily during operation, then recovers. It occurs particularly when the supply voltage rises rapidly (in a few hundred nanoseconds, for example), and the reset signal must drive a significant capacitive load. In many devices the internal reset signal does drive a significant capacitive load, because there are many internal circuits to be reset. If the reset signal is routed to those circuits directly, the capacitance of the signal-line wiring is large. If buffers are used, the reset signal must drive the input capacitance of the buffers. A capacitive load on the order of half a picofarad is typical. If the resistor through which the reset signal is output has sufficient resistance to hold current flow through the auto-reset circuit to about ten microamperes during the steady state, and the power supply rises to five volts in a few hundred nanoseconds, then the reset signal will be released while the capacitive load is still charging and the reset signal is still inactive. This problem could be alleviated by reducing the resistance value of the resistor, but then more current would flow through the circuit during steady-state operation. If the current flow is too high, problems such as excessive power consumption and battery drain arise. From JP-A-01-032716 and Patent Abstracts of Japan, volume 13, no. 220 (E-762) an auto-clearing circuit is known having first and second switching elements. To prevent a current from flowing in a back-up condition and to stabilize action, the on-off control of the second switching element is executed with voltage inputted to an input terminal and, when the first switching element is in an off-condition, the second switching element is turned off too. SUMMARY OF THE INVENTION It is accordingly an object of the present invention to. ensure release of the reset signal, even in devices with a low supply voltage. Another object of the invention is to ensure that an adequate reset signal is generated even if the power-supply potential rises rapidly. Yet another object of the invention is to ensure that a reset signal is output when the power supply is interrupted, even if the interruption is momentary. Still another object of the invention is to avoid needlessly high current drain during operation. A further object of the invention is to enable current drain through the auto-reset circuit to be reduced to zero for testing purposes. An auto-reset circuit according to the invention is defined in claim 1. The dependent claims describe further aspects of the invention. The invented circuit can be fabricated as a complimentary metal-oxide-semiconductor (CMOS) circuit in which the first and second active elements are MOSFETs and their first, second, and third terminals are their source, drain, and gate, respectively. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of an auto-reset circuit illustrating a first illustrative example. Fig. 2 is a voltage waveform diagram illustrating the operation of Fig. 1. Fig. 3 is a circuit diagram of an auto-reset circuit illustrating a second illustrative example. Fig. 4 is a voltage waveform diagram illustrating the operation of Fig. 3. Fig. 5 is a circuit diagram of an auto-reset circuit illustrating an embodiment of the invention. Fig. 6 is a circuit diagram of an auto-reset circuit illustrating a second embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION Various embodiments of the invention will be described with reference to the attached drawings. These drawings illustrate the invention but do not restrict its scope. It will be assumed that the auto-reset circuits described below are incorporated in an LSI or other device powered by two potentials, the higher of which is denoted V DD and the lower V SS . The terms "high" and "low" will also be used to refer to these potentials. The term "supply voltage" will refer to the difference V DD - V SS . The symbols V TN and V TP will be used to denote N-MOSFET and P-MOSFET threshold voltages, respectively, the threshold voltage of a MOSFET being the absolute gate-source voltage at which the MOSFET turns on. Typically, V TN and V TP are about 0.7 V. It will be assumed that during normal, steady-state operation the supply voltage V DD - V SS exceeds the threshold voltages V TN and V TP sufficiently to enable the MOSFETs to turn on "hard;" that is, with negligible on-resistance. 1st Example Fig. 1 is a circuit diagram of an auto-reset circuit illustrating a first illustrative example This auto-reset circuit has a first power-supply input terminal 31 to which V DD is applied, a second power-supply input terminal 32 to which V SS is applied, and an output terminal 33, the potential at which is denoted V O . The reset signal RS is output at the output terminal 33. The circuit comprises a first three-terminal active element 41, a second three-terminal active element 42, and two resistors 51 and 52. The first active element 41 is a P-MOSFET. The second active element 42 is an N-MOSFET. The circuit is thus a CMOS circuit. P-MOSFET 41 and resistor 51 are coupled in series between the two power-supply terminals: the source of P-MOSFET 41 is coupled to the first power-supply terminal 31, the drain of P-MOSFET 41 is coupled to one terminal of resistor 51, and the other terminal of resistor 51 is coupled to the second power-supply terminal 32. The gate of P-MOSFET 41 is also coupled to the second power-supply terminal 32; this is a novel feature of the present invention. V DD is applied not only to the source of P-MOSFET 41 but also to the substrate or well in which P-MOSFET 41 is formed, as indicated by the conventional symbol in the drawing; that is, P-MOSFET 41 has no back-gate bias. N-MOSFET 42 and resistor 42 are likewise coupled in series between the two power-supply terminals: one terminal of resistor 52 is coupled to the first power-supply terminal 31, the other terminal of resistor 52 is coupled to the drain of N-MOSFET 42, and the source of N-MOSFET 42 is coupled to the second power-supply terminal 32. The output terminal 33 is coupled to the drain of N-MOSFET 42. The gate of N-MOSFET 42 is coupled to the drain of P-MOSFET 41. The gate potential of N-MOSFET 42 is denoted by the symbol V G . N-MOSFET 42 also has no back-gate bias; its source is at the same potential (V SS ) as the well or substrate in which it is formed. The operation of the first example will be explained with reference to Fig. 2. In this drawing the threshold voltages V TP of P-MOSFET 41 and V TN of N-MOSFET 41 are shown as slightly unequal: for example, V TP is 0.7 V and V TN 0.8 V. This is not a necessary condition; the invention is also applicable to circuits with equal threshold voltages. In interval A before power-up, V DD , V G , and V O are all at the same potential as V SS . In interval B power is turned on and the supply voltage begins to rise at a rate determined by a time constant of the power supply. V DD is shown rising in relation to V SS . The supply voltage V DD - V SS is initially less than the threshold voltage V TP of P-MOSFET 41, so P-MOSFET 41 is off. N-MOSFET 42 is also off, because its gate is pulled down through resistor 51 to V SS . The output terminal 33 is therefore pulled up through resistor 52 to V DD , and the output voltage V O rises together with V DD . In interval C, the supply voltage V DD - V SS exceeds V TP so P-MOSFET 41 turns on. P-MOSFET 41 and resistor 51 now act as a voltage divider between V DD and V SS , and the gate potential V G of N-MOSFET 42 begins to rise. V G - V SS is still less than the threshold voltage V TN , however, so N-MOSFET 42 remains off and the output voltage V O continues to match V DD . In interval D, V G - V SS passes V TN and N-MOSFET 42 turns on. N-MOSFET 42 and resistor 42 now act as a voltage divider between V DD and V SS , but as the gate potential V G of N-MOSFET 42 continues to rise, the on-resistance of N-MOSFET 42 quickly decreases in comparison with the resistance of resistor 52, and the drain potential of N-MOSFET 42 approaches V SS . The output voltage V O at output terminal 33 accordingly falls back toward V SS . In the drawing, for clarity, V O is shown as falling to V SS instantaneously, but the fall actually takes place over a certain span of time within interval D. In interval E, power-up is completed and V DD holds to its steady state. In this state the gate-source voltage of P-MOSFET 41 is V DD - V SS , so P-MOSFET 41 is turned on hard, the on-resistance of P-MOSFET 41 is negligible in comparison with the resistance of resistor 51, and V G is substantially equal to V DD . The gate-source voltage V G - V SS of N-MOSFET 42 is therefore substantially equal to V DD - V SS , N-MOSFET 42 is also turned on hard, the on-resistance of N-MOSFET 42 is negligible in comparison with the resistance of resistor 52, and the output voltage V O is substantially equal to V SS . The reset signal RS thus goes high (V O = V DD ) during intervals B and C, then goes low (V O = V SS ) in interval D and remains low in the steady state in interval E. RS is an active-high reset signal that can be used to initialize the internal circuits of an LSI or other device at power-up. In both the circuit of Fig. 1 and the above-mentioned prior art, the reset signal RS is released when the supply voltage V DD - V SS equals the threshold voltage V TN of N-MOSFET 42 plus the voltage drop across P-MOSFET 41. In the prior art circuit in which the drain and gate of P-MOSFET 41 were interconnected, this voltage drop was V TP . In Fig. 1 the voltage drop can be made arbitrarily small by increasing the resistance value of resistor 51. If the resistance of resistor 51 is high enough that the voltage drop across P-MOSFET 41 is substantially nil, then the reset signal RS will release when the supply voltage V DD - V SS equals the larger of V TP and V TN . If V TP = 0.7 V and V TN = 0.8 V, the reset signal will release when V DD - V SS = 0.8 V, for example. This assures that even a device powered at 3.0 V will come out of reset at power-up, and will do so even during tests performed at extreme temperatures with a reduced supply voltage. 2nd Example Fig. 3 is a circuit diagram of an auto-reset circuit illustrating a second illustrative example. Elements identical to elements of the first embodiment shown in Fig. 1 have the same reference numerals. In this example V SS is applied to the first power-supply terminal 31 and V DD is applied to the second power-supply terminal 32. The first active element is therefore an N-MOSFET 61 instead of the P-MOSFET 41 in Fig. 1, and the second active element is a P-MOSFET 62 instead of the N-MOSFET 42 in Fig. 1. Apart from these replacements, the active elements and resistors are interconnected in the same manner as in Fig. 1. Fig. 4 is a voltage waveform diagram illustrating the operation of the second example. In this drawing, when power is turned on V DD is shown as remaining constant while V SS decreases. This may appear different from Fig. 2, but in fact the two drawings show the same power-up event. V DD and V SS do not have independent absolute values; only the difference between them is meaningful. V G now denotes the gate potential of P-MOSFET 62. V G and V O are shown in relation to V DD . The operation of the second example as illustrated in Fig. 4 is the same as the operation of the first example illustrated in Fig. 2, except that the roles of V DD and V SS are reversed. In interval A, V SS , V G , and V O are all equal to V DD . As V SS decreases in intervals B and C the gate-source voltage |V G - V DD | remains less than the threshold voltage V TP of P-MOSFET 62, so P-MOSFET 62 stays off, and the output voltage V O decreases together with V SS . In interval D, |V G - V DD | exceeds V TP and P-MOSFET 62 turns on, causing the output voltage V O to return to the V DD level. In interval E the supply voltage V DD - V SS is in its steady state and the output voltage V O remains at V DD . The reset signal in this second example is active low: it normally stays at the high level (V DD ), but goes low (V SS ) for an interval during power-up. The choice between the first and second examples depends on whether an active-high or an active-low reset signal is more convenient. 1 st Embodiment Fig. 5 is a circuit diagram of an auto-reset circuit illustrating a first embodiment of the invention. Elements identical to elements of the first example shown in Fig. 1 have the same reference numerals. In this auto-reset circuit, the gate (third terminal) of the P-MOSFET 41 shown in Fig. 1 is coupled to a control signal input terminal 81 which receives a control signal CS1, and output terminal 33 is coupled to the first input terminal of a two-input AND gate 91. The second input terminal of the AND gate 91 is coupled to another control signal input terminal 82, which receives a control signal CS2. The output side of AND gate 91 is coupled to an output terminal 83. The reset signal RS is the signal output from output terminal 83; that is, the reset signal RS is gated by AND gate 91. During normal operation, control signal CS1 is held low and control signal CS2 is held high. The gate potential of P-MOSFET 41 is therefore V SS as in Fig. 1, and the outputs at output terminals 33 and 83 are either both high or both low. This circuit accordingly operates in substantially the same way as the first embodiment. To measure the static current consumption of an LSI or other device containing this auto-reset circuit without placing the device in the reset state, control signal CS1 is driven high and control signal CS2 low. The gate and source of P-MOSFET 41 are now both at the V DD level, so P-MOSFET 41 turns off. The gate potential of N-MOSFET 42 is then pulled down through resistor 51 to V SS , so N-MOSFET 42 also turns off. Accordingly, no current flows through the auto-reset circuit. Output terminal 33 is pulled up through resistor 52 to the V DD level, but since control signal CS2 is low, the reset signal RS output at output terminal 83 remains low. To measure static current consumption in the reset state, or to verify output of the reset signal RS, it suffices to drive control signals CS1 and CS2 both high. Current flow through the auto-reset circuit stops, and the resulting high potential at output terminal 33 is passed through AND gate 91 and output as a reset signal RS at output terminal 83. Another useful possibility is to route the signal from output terminal 33 to some circuits in an LSI or other device, and the signal from output terminal 83 to other circuits. Static current consumption can then be measured in either a partially or a completely initialized state. The advantage of performing static current tests with current flow through the auto-reset circuit cut off is that it removes the ambiguity resulting from inexact knowledge of the size of that current. That is, it improves the resolution of the tests, enabling more accurate identification of devices with photolithography defects or other defects that might impair long-term reliability. 2nd Embodiment Fig. 6 is a circuit diagram of an auto-reset circuit illustrating a second embodiment of the invention. Elements identical to elements of the second example shown in Fig. 3 have the same reference numerals. In this embodiment, the gate of N-MOSFET 61 is coupled to a control signal input terminal 81, and output terminal 33 is coupled to the first input terminal of a two-output OR gate 92. The second input terminal of the OR gate 92 is coupled to another control signal input terminal 82 and the output side of OR gate 92 is coupled to an output terminal 83. As in the thirteenth embodiment, the inputs at control signal input terminals 81 and 82 are control signals CS1 and CS2, and the reset signal RS, which is active low, is taken from output terminal 83; that is, the reset signal RS is gated by OR gate 92. During normal operation, control signal CS1 is high and control signal CS2 is low, and this embodiment operates like the second example. During static current measurements, control signal CS1 is driven low to turn off N-MOSFET 61. The gate potential V G of P-MOSFET 62 is then pulled up to V DD through resistor 51, so P-MOSFET 62 also turns off and current flow through the auto-reset circuit ceases. If the measurement is to be performed in the reset state, control signal CS2 is left low, permitting output of a low reset signal RS from output terminal 83; otherwise, control signal CS2 is driven high, forcing RS to remain inactive (high). This embodiment has the same effect as the first embodiment, the only difference being that the meanings of the high and low levels of the reset and control signals are reversed. In all of the above embodiments, if resistors 51 and 52, or resistors 51, 52, and 53, have resistance values of about 500 kilohms and the supply voltage is 5 V, total steady-state current flow through the auto-reset circuit is between ten and twenty microamperes. This amount of current is insignificant in comparison with the current drawn by most LSI and other devices during operation. The invention accordingly can provide a reliable reset signal without dissipating excessive current. As will be apparent to those skilled in the art, the preceding embodiments can be modified in further ways without departing from the invention. The three-terminal active elements need not be MOSFETs; other active elements in which conduction between a first terminal and a second terminal is controlled by the input at a third terminal can be employed instead.

Claims: An auto-reset circuit for generating a power-up reset signal, comprising: a first power-supply terminal (31) for receiving a first potential; a second power-supply terminal (32) for receiving a second potential different from said first potential; an output terminal (33) for output of the power-up reset signal; a first control signal input terminal (81) for inputting a first control signal having a first or second potential level; a first transistor (41 or 61) having a first terminal, a second terminal, and a third terminal for controlling electrical conduction between the first terminal and second terminal thereof, the first terminal of which is coupled to said first power-supply terminal (31), and the third terminal of which is coupled to said first control signal input terminal (81), the first transistor (41 or 61) electrically conducting between the first terminal and the second terminal when the first control signal received by the third terminal is at the first potential level, the first transistor being nonconducting when the first control signal is at the second potential level; a first resistor (51) coupled between the second terminal of the first transistor (41 or 61) and said second power-supply terminal (32); a second resistor (52) coupled between said first power-supply terminal (31) and said output terminal (33); and a second transistor (42 or 62) having a first terminal, a second terminal, and a third terminal for controlling electrical conduction between the first terminal and the second terminal thereof, the first terminal of which is coupled to said second power-supply terminal (32), the second terminal of which is coupled to said output terminal (33), and the third terminal of which is coupled to the second terminal of the first transistor (41 or 61); characterized in that said auto-reset circuit further comprises a second control signal input terminal (82), for inputting a second control signal to control output of said reset signal, the second control signal having a third potential level or a fourth potential level; and a logic gate (91 or 92) having input terminals coupled to said output terminal (33) and said second control signal input terminal (82), for gating said power-up reset signal, and in that said second control signal is used to prevent output of said power-up reset signal, by placing said second control signal at said third potential level, during certain times when said first control signal is at said second potential level. The circuit of claim 1, wherein said logic gate (91) is an AND gate. The circuit of claim 1, wherein said logic gate (92) is an OR gate.

Inventors: FUJISAWA YOSHIMITU, SHIN YASUHIRO, FUJISAWA, YOSHIMITU, SHIN, YASUHIRO, Fujisawa, Yoshimitu Oki LSI Technology Kansai Co
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1993
Main classification: H03K17
IPC codes: H03K17