Power semiconductor integrated circuit device with uniform electric field distribution

Abstract: There is provided a power semiconductor integrated circuit device without lowering a breakdown voltage of a pn junction located below a wiring layer to which a high voltage is applied. The device includes an N⁻-type semiconductor substrate (11) which is provided with an N⁺-type region (12) and a P⁺-type region (13) to form, for example, a lateral diode. An insulating film (14) is formed over the substrate surface, on which a wiring layer (15) is provided so as to be connected to the N⁺-type region (12) and to pass through the P⁺-type region (13). A film resistor (17) connected between the N⁺-type region (12) and the P⁺-type region (13) is formed in the insulating film (14) so as to be crossed by the wiring layer (15) at least once.

Description: The present invention relates to a semiconductor integrated circuit device, and more particularly to a power semiconductor integrated circuit device. US-A-4 157 563 discloses a planar semiconductor device having a planar p-n junction which in order to increase the breakdown voltage is shunted by a resistance layer of a very high resistance provided on an insulating layer. A resistance layer is used in the form of an elongate strip. The strip is preferably in the form of a coil, or a number of concentric contact layers present on the insulating layer are used which cross the resistance layer and assume the potential of the resistance layer at the area of the crossover. In more detail, this document discloses a npn transistor structure whose base-collector junction is shunted by a resistance layer of polysilicon in the form of a coil-shaped strip formed on an insulating film connected between a base contact and a collector contact. Such arrangement is intended to extend a depletion layer by the resistance layer or coil-shaped strip, for increasing the breakdown voltage of the base-collector junction. WO-A-85/03167 discloses a semiconductor structure, e.g. a p-i-n diode which includes a resistive layer, e.g. a SIPOS layer provided over a dielectric layer and connected to electrodes in contact with localized semiconductor regions, respectively. This semiconductor structure is intended to limit a charge on or in a dielectric layer from affecting the breakdown voltage in the silicon below by virtue of the resistive layer (SIPOS). As described in this prior art document, the breakdown voltage of high voltage discrete devices and integrated circuits can be decreased by the presence of charge (usually ionic) on top surface insulator layers or within the insulating layers. Such charge may spread out from the point of origination. If the potential generated by such leakage charge is different from that of the silicon below it, then field crowding results and breakdown voltages can be reduced. A prior art technique for limiting this effect consisted of shielding the silicon surface of the device from the effects of the charge on the insulator layer or layers by using a resistive field shield which contacts the surface of the device, or is at some distance above the surface and makes electrical contract to conductors on the surface. A SIPOS layer (semi-insulating polisilicon) may be used as such a shield, however, the use of such a SIPOS shield layer may create a problem, that is introducing leakage which may be greater than is acceptable in some applications. For maintaining breakdown voltages of high voltage devices, while maintaining any extra generated leakage at a relatively low level, this document suggests to provide a resistive layer having a relatively high resistivity and being patterned so as to have openings and/or windows therein, the size and the geometry of the openings and/or windows being such that the resistance of the resistive layer between electrodes coupled thereto is relatively high, as compared to the resistance of a resistive layer of the same overall dimensions but without the openings and/or windows, whilst the surface of a semiconductor body under the resistive layers is effectively screened from electric fields due to charges in portions of the structure above the resistive layer. EP-A-0 190 423 discloses a planar semiconductor device having a field plate electrode which includes a plurality of reverse-biased and forward-biased PN junctions formed between P and N portions. This field plate electrode operates in the same manner as the resistance layer according to US-A-4 157 563. US-A-5 086 332 discloses a planar semiconductor device having a high breakdown voltage and a low ON-resistance. The planar semiconductor device includes a semiconductor layer of a first conductivity type and a first semiconductor region of a second conductivity type selectively formed, together with the semiconductor layer, in the surface of the semiconductor layer forming a pn junction. The first semiconductor region is formed to have an impurity concentration higher than that of the semiconductor layer and therefore a resistivity higher than that of the semiconductor layer. A second semiconductor region of the second conductivity type having an impurity concentration lower than that of the first semiconductor region, is formed around and in contact with the first semiconductor region and together with the semiconductor layer constitutes a pn junction. A high resistance film is formed at least over the first semiconductor region and the second semiconductor region. A voltage is applied across the high resistance film to create a uniform electric field in the high resistance film. With the second semiconductor region of the low impurity concentration and the high resistance layer, the concentration of electric field in the semiconductor layer can be prevented. As a result, the breakdown voltage of the pn junction between the first semiconductor region and the semiconductor layer can be enhanced to more than 85% of the theoretical breakdown voltage of an ideal plane junction formed in a bulk. In contrast, when only the second semiconductor region of the low impurity concentration is formed, at most 75% of the theoretical breakdown voltage can be attained, and when only the high resistance layer is used, at most 70% of the theoretical breakdown voltage can be attained. EP-A-0 077 072 discloses a high voltage resistor having a zigzag-like pattern which is suitable for integrated circuits. For facilitating to understand the present invention, the technical background thereof will be briefly outlined hereinafter. Lateral semiconductor devices such as FRDs (Fast Recovery Diodes), power bipolar transistors, power MOS transistors, and IGBTs, to which a high voltage is applied, have been used in power semiconductor integrated circuit devices including a three-phase full bridge circuit, a rectifying circuit, a switching regulator, a high-side switching circuit, and a low-side switching circuit. In such power semiconductor integrated circuit devices, a potential difference between two diffused layers becomes about several hundreds volts or more by application of the high voltage. Fig. 8 shows an example where a voltage is applied across the two diffused layers. An N + -type diffused layer 102 and a P + -type diffused layer 103 are formed in an N - -type semiconductor substrate 101 to provide a lateral diode. An insulating film 104 is formed on the substrate surface, and first and second wiring layers 105 and 106 are provided on the diffused layers 102 and 103, respectively. In this case, when a voltage is applied such that the first diffused layer 102 is subject to a high voltage with respect to the second diffused layer 103, an electric field of the substrate 101 between the diffused layers 102 and 103 is uniformly distributed, thereby providing equipotential lines 107 (dotted line) having equal intervals. In this case, the breakdown voltage is determined by a point exceeding the critical potential density (avalanche breakdown) of silicon. However, since a large number of wiring layers are required for the power semiconductor integrated circuit device, a part of them must pass through semiconductor regions having different potentials. Fig. 9A shows a case where the first wiring layer 105 extending from the first diffused layer 102 passes over the second diffused layer 103 having a potential difference of about several hundreds volts or more. When a reverse bias voltage is applied between the first and second diffused layers 102 and 103, the electric field is concentrated at a portion surrounded by a circle (electric field concentration portion 108) where the second diffused layer 103 is crossed by the first wiring layer 105, as indicated by the equipotential lines 107. As shown in Fig. 9B, the potential of the semiconductor substrate 101 is abruptly changed near the second diffused layer 103, i.e., at a portion where the electric field is concentrated. When the electric field concentration density exceeds a critical point of the breakdown voltage of the semiconductor substrate 101, breakdown occurs due to the concentration of the electric field. Therefore, a desired breakdown voltage cannot be obtained. Referring to Fig. 10, there will be described a semiconductor device that includes a P + -type diffused layer 122 and an N + -type diffused layer 123 formed in an N--type semiconductor substrate 121, an insulating film 124 formed on the substrate surface, and a wiring layer 125 extending from the first diffused layer 122 and passing over the second diffused layer 123. A voltage is applied to the semiconductor device such that a potential difference between the first and second diffused layers 122 and 123 is several hundreds volts or more and the first diffused layer 122 is set to a low voltage with respect to the second diffused layer 123. In this case, equipotential lines 107 are concentrated at the N - -N + interface (a portion indicated by a circle 108), thereby causing the breakdown. At any rate, as shown in Figs. 9A and 10, when a wiring layer passes over a diffused layer having a different potential, an electric field is concentrated at that portion, thereby reducing the breakdown voltage. For this reason, the following techniques have been proposed for increasing the breakdown voltage. One of these techniques is to increase the thickness of the insulating film 104 under the wiring layer 105 as shown in Fig. 11. The electric field in the insulating film 104 is then easily relieved to reduce the concentration of the electric field in the semiconductor substrate 101. This technique can be applied to process steps for making the semiconductor device without using new materials. However, the lateral type high breakdown voltage devices are generally used for integrated circuits, and are often provided in the same semiconductor substrate together with signal processing circuits having a low breakdown voltage and a small size. As shown in Fig. 11, if the insulating layer is thick, a contact hole formed in the insulating layer must be tapered. Therefore, a margin for taper processing is required in proportion to the thickness of the insulating layer. Consequently, the increase in thickness of the insulating layer will increase, e.g., the size of the signal processing circuits, thereby reducing the integration density of the overall integrated circuit device. Another technique will be described below with reference to Fig. 12. A resistor, formed of semi-insulating polysilicon (to be referred to as SIPOS hereinafter) 109, having a high resistance, is formed in the insulating film 104 under the wiring layer 105. Both ends of the SIPOS 109 are connected to the first and second diffused layers 102 and 103, respectively, and are kept at the electric potential thereof. The SIPOS 109 is a resistor having a high resistance, and the electric potential is uniformly distributed by the potential difference between both ends of the SIPOS 109. As indicated by the equipotential lines 107, the electric field is almost uniformly distributed in the semiconductor substrate 101 under the SIPOS 109. Therefore, the breakdown voltage can be increased to about the ideal breakdown voltage of the substrate. However, since the semi-insulating polysilicon is not normally used for such semiconductor devices, the number of process steps is increased to increase the cost. Still another technique will be described below with reference to Figs. 13A and 13B. As shown in Fig. 13A, floating potential polysilicon layers 110 are fragmentarily arranged in the insulating film 104 under the wiring layer 105. As shown in Fig. 13B, the floating potential polysilicon layers 110 are parallelly arranged in the form of strips under the wiring layer 105. Each of the floating potential polysilicon layers 110 serves as a field plate, and the potential of each of the floating potential polysilicon layers 110 is fixed to a predetermined potential due to the influence of a leakage electric field from a semiconductor substrate 101. Therefore, the electric field is not concentrated and is uniformly distributed under the floating potential polysilicon layers 110, thereby obtaining an electric field distribution indicated by equipotential lines 107 in Fig. 13A. According to this technique, the cost is not increased because the integration density is not decreased and new materials are not used. However, the potential of each of the field plates is affected by the arrangement and shape of the field plates, the impurity concentration of the semiconductor substrate, the applied voltage, and the like. For this reason, the field plates must be optimally designed by using a computer in advance. A satisfactory effect cannot be obtained without an optimal design. Even if the field plates are optimally designed at a certain potential, the potential variation makes it very difficult to perform the optimal design under all conditions. Therefore, difficulties in the design of the field plates arise and result in problems. As described above, when a high-voltage wiring layer passes over a diffused layer having a potential difference of several hundreds volts or more, an electric field is concentrated to cause a breakdown. Therefore, a predetermined breakdown voltage cannot be obtained. It is an object of the present invention to provide a power semiconductor integrated circuit device which prevents deteriorating the breakdown voltage of a junction. According to one aspect of the present invention, there is provided a power semiconductor integrated circuit device according to claim 1. Preferred embodiments of the invention are indicated in the dependent claims. The novel and distinctive features of the invention are set forth in the independent claim of the present application. The invention itself, however, together with further objects and advantages thereof may best be understood by reference to the following description and accompanying drawings in which: Figs. 1-3A, 5-7B do not relate to embodiments of the invention, but are useful for understanding the invention; Fig. 1A is a plan view showing a lateral diode having a high voltage wiring layer and a resistor for protecting a junction; Fig. 1B is a sectional view showing the lateral diode along a line IB - IB in Fig. 1A; Fig. 1C is a sectional view showing the lateral diode along a line IC - IC in Fig. 1A; Fig. 1D is a graph showing an electric potential distribution of the resistor in Fig. 1B; Fig. 2A is a plan view showing a lateral diode having a high voltage wiring layer and a resistor for protecting a junction; Fig. 2B is a sectional view showing the lateral diode along a line IIB - IIB in Fig. 2A; Fig. 3A is a plan view showing a lateral diode having a high voltage wiring layer and a resistor constituted by a plurality of diodes for protecting a junction; Fig. 3B is a view schematically showing the resistor provided with a plurality of diodes in Fig. 3A; Fig. 4A is a sectional view showing a lateral double-diffusion MOS FET (DMOS FET) having a high voltage wiring layer according to an embodiment of the present invention; Fig. 4B is a sectional view schematically showing the lateral double-diffusion MOS FET (DMOS FET) except the high voltage wiring layer in Fig. 4A; Fig. 5 is a sectional view schematically showing a lateral NPN bipolar transistor except the high voltage wiring layer; Fig. 6 is a sectional view schematically showing a lateral IGBT except the high voltage wiring layer; Fig. 7A is a sectional view showing a lateral diode having a high voltage wiring layer and a resistor for protecting a junction; Fig. 7B is a graph showing an electric potential distribution of the resistor in Fig. 7A; Fig. 8 is a sectional view showing a conventional lateral diode when a voltage is applied between two diffused layers; Fig. 9A is a sectional view showing an electric field distribution when a wiring layer formed on one of the diffused layers passes through the other of the diffused layers in Fig. 8; Fig. 9B is a graph showing an electric potential distribution of the semiconductor substrate in Fig. 9A; Fig. 10 is a sectional view showing an electric field distribution when a voltage is applied between two diffused layers to a reverse direction in Fig. 9A; Fig. 11 is a sectional view showing an electric field distribution when the thickness of an insulating layer under a wiring layer is increased; Fig. 12 is a sectional view showing a conventional breakdown protection structure, and illustrating an electric field distribution when a field plate of semi-insulating polysilicon is used; Fig. 13A is a sectional view showing another conventional breakdown protection structure, and illustrating an electric field distribution when field plates of floating potential semi-insulating polysilicon are used; and Fig. 13B is a plan view showing the field plates of floating potential semi-insulating polysilicon in Fig. 13A. An embodiment of the present invention will be described below with reference to the accompanying drawings. The same reference numerals denote the same parts throughout the drawings. As shown in Fig. 1B, a semiconductor device is a lateral diode having a pn junction, and includes an N + -type diffused layer 12 and a P + -type diffused layer 13 formed in an N - -type semiconductor substrate 11, an insulating film 14 provided over the substrate surface, a first wiring layer 15 connected to the first diffused layer 12 and passing over the second diffused layer 13, a second wiring layer 16 connected to the second diffused layer 13, and a resistor 17 of polysilicon arranged in the insulating film 14, crossed by the first wiring layer 15 and connected between the first and second diffused layers 12 and 13. As is apparent from Fig. 1A, the resistor 17 is continuously formed such that it is crossed by the first wiring layer 15 at least once, e.g., 8 times. As shown in Fig. 1B (the section along a line IB - IB), the resistor 17 is provided to have a zigzag or corrugated structure just under the first wiring layer 15. As shown in Fig. 1C (the section along a line IC - IC), one end of the resistor 17 is connected to the first wiring layer 15 at a first contact portion 18, while the other end of the resistor 17 is connected to the second wiring layer 16 at a second contact portion 19. Both ends of the resistor 17 are connected between the first and second diffused layers 12 and 13. When a reverse voltage is applied between the first and second diffused layers 12 and 13, the resistor 17 exhibits a potential gradient as shown in Fig. 1D. The portions of the resistor 17 under the first wiring layer 15 have predetermined potentials, respectively, and the potential of the resistor 17 gradually decreases from the first diffused layer 12, kept at a high potential, to the second diffused layer 13 kept at a low potential. That is, since both ends of the resistor 17 are set at the potentials of the first and second diffused layers 12 and 13, respectively, each portion of the resistor 17 is fixed to a predetermined potential, corresponding to the distance from the diffused layer 12 or 13. Therefore, the concentration of the electric field, which occurs when the first wiring layer 15 passes through the second diffused layer 13, can be avoided. In this case, a small leakage current may flow through the resistor 17 because the resistor 17 is connected between the first and second diffused layers 12 and 13. However, since the resistor 17 is formed to be bent many times in the embodiment to obtain a sufficient length, the leakage current can be suppressed to be small. As shown in Fig. 2A, the first diffused layer 12 is arranged inside the resistor 17, while the second diffused layer 13 is arranged outside the resistor 17, and the resistor 17 is provided to surround the first diffused layer 12 and to have a swirl-shaped structure. Both ends of the resistor 17 are fixed to the potentials of the first and second diffused layers 12 and 13 at first and second contact portions 18 and 19, respectively. In the drawings, reference numeral 21 denotes a contact layer for connecting the first diffused layer 12 to the resistor 17. As shown in Fig. 2B, the portions of the resistor 17 under the first wiring layer 15 are spaced apart from one another. Since the resistor 17 has the swirl-shaped structure, the total length thereof can be increased, thereby reducing the leakage current. In addition, even if the first wiring layer 15 extends in any direction, the same advantages described above can be obtained because the resistor 17 is provided to surround the first diffused layer 12. In either one of the first and second examples, the width of the resistor cannot be decreased to a limit value or less in consideration of the design and process. Therefore, it is necessary to increase the length of the resistor as much as possible in order to increase the resistance. The third example for explaining the present invention will be described below with reference to Figs. 3A and 3B. In the example, as shown in Fig. 3A, a resistor 17a, formed of polysilicon, having diodes connected in series is used as a resistor. As shown in Fig. 3B, diodes 30 included in the resistor 17a are obtained by alternately connecting P-type regions 31 and N-type regions 32 in series, and the diodes (30a, 30b, 30a,...) are alternately connected in forward and reverse directions. With the above structure, only a small leakage current flows through reverse-biased diodes. This leakage current is generally made smaller by a few orders of magnitude, as compared with a current flowing through a resistor formed by the same impurity concentration when the same voltage is applied thereto. Therefore, the leakage current can be greatly reduced as compared with a resistor consisting of only polysilicon. However, when a voltage applied to each of the reverse-biased diodes exceeds the breakdown voltage of the corresponding diode, an excessive current may flow through the diode. For this reason, an appropriate number of diodes must be connected in series to divide the voltage. For example, when a resistor having a breakdown voltage of 500 V is used, 100 or more diodes having an anti-series connection may be required if the breakdown voltage of one diode is 5 V. The length of the resistor of the example can be made shorter than that of the resistor including no diodes because of the high resistance. Therefore, the resistor of the example is effective when sufficient space for locating the resistor cannot be provided due a small chip size. The embodiment of the present invention relating to a lateral MOSFET (lateral DMOS FET) will be described below with reference to Figs. 4A and 4B. As shown in Fig. 4A, a N + -type third diffused layer 41 serving as a source region is provided in the second diffused layer 13, and an outer portion 17' of the resistor 17 is used as a gate electrode. The thickness of the insulating film 14 under the resistor portion 17' is less than that of the insulating film 14 under other resistor portions. A potential of about several Volts is applied to the gate electrode with respect to the potential of the source electrode and the second diffused layer. In the embodiment, one end of the resistor 17 is set at the potential of the first diffused layer 12, and the other end is set at the potential (e.g., a gate potential) close to a potential of the second diffused layer 13 or third diffused layer 41. The resistor portion 17' serving as the gate electrode has a potential difference of approximately several Volts with respect to the second diffused layer 13 kept at a low potential, and has a potential difference of several hundred Volts or more with respect to the first diffused layer 12. Therefore, the resistor 17 functions as the gate electrode, and relieves the concentration of the electric field in the semiconductor substrate at the same time. As shown in Fig. 4B, the first diffused layer 12, the resistor 17' and the third diffused layer 41 are connected to the drain electrode (D), the gate electrode (G) and the source electrode (S), respectively. Fig. 4B shows schematically the semiconductor device in Fig. 4A, and the insulating film 14, the resistor 17, and the first wiring layer 15 are omitted. Another example applied to a NPN bipolar transistor will be described below with reference to Fig. 5. Since the basic structure is similar to the embodiment, Fig. 5 is schematically shown as in Fig. 4B, and the high voltage wiring layer 15 and the resistor 17 are omitted. The first diffused layer 12, the second diffused layer 13 and the third diffused layer 41 are connected to the collector electrode (C), the base electrode (B), and the emitter electrode (E), respectively. In this case, one end of the resistor (not shown) is connected to the collector electrode (C), and the other end is connected to the base or emitter region. The outermost portion (corresponding to the resistor portion 17' in Fig. 4) of the resistor may be formed as in the first to third embodiments, or the insulating film under the outermost portion may be formed to have small thickness. A sixth example for explaning the present invention and relating to an IGBT will be described below with reference to Fig. 6. Fig. 6 is schematically shown as in Fig. 5. A P + -type diffused layer 61, the resistor portion 17' and the third diffused layer 41 are connected to the collector electrode (C), the gate electrode (G) and the emitter electrode (E), respectively. At this time, one end of a resistor 17 (not shown) is connected to the collector electrode (C), and the other end is connected to the gate electrode (G) or the emitter electrode (E). A seventh example for explaining the present invention will be described below. As shown in Fig. 7A, a semiconductor device includes a P + -type first diffused layer 72 and a N + -type second diffused layer 73, which are formed in a N - -type semiconductor substrate 71 to provide a lateral diode, an insulating film 74 formed on the substrate surface, a first wiring layer 75 connected to the first diffused layer 72 and passing through the second diffused layer 73, and a resistor 77 of polysilicon formed in the insulating film 74 and crossed by the first wiring layer 75. In this case, as in the first embodiment, the resistor 77 is continuously formed such that it is crossed by the first wiring layer 75 at least once, e.g., 8 times, and both ends of the resistor 77 are set to the potentials of the first and second diffused layers 72 and 73, respectively. When a voltage is applied such that the first diffused layer 72 and the second diffused layer 73 are set to low and high voltages, respectively, the potential of the resistor 77 gradually increases from the first diffused layer 72 at the low potential to the second diffused layer 73 at the high potential as shown in Fig. 7B. Therefore, the semiconductor substrate 71 is shielded from the first wiring layer 75 by the resistor 77. Accordingly, the concentration of the electric field, which occurs at the interface between the semiconductor substrate 71 and the second diffused layer 73 when the first wiring layer 75 passes through the second diffused layer 73 having a potential different from that of the first wiring layer 75, can be avoided. A modification of the first example has been described above with reference to Fig. 7. However, it is apparent that the technical concept of the seventh embodiment is applicable to another embodiments. That is, the resistor according to the present invention can be applied to any structures where a wiring layer passes over a diffused layer having a potential different from that of the wiring layer. According to the present invention, the PN junction or interface formed in the semiconductor substrate can be advantageously shielded from the high voltage wiring layer. That is, since the electric field is uniformly distributed in the semiconductor substrate under the resistor, the breakdown voltage of the semiconductor element can be increased without concentrating the electric field even if the high voltage wiring layer passes over the diffused layer. In addition, the resistor will not be affected by impurity ions in the insulating film because the potentials of the resistor are not fixed by the leaked electric field from the semiconductor substrate, but are fixed by the diffused layers. A complex optimized design is not required in forming the resistor. When the resistor is formed by not only polysilicon but also a plurality of diodes, the resistance of the resistor can be greatly increased.

Claims: A lateral power semiconductor integrated circuit device formed as a DMOSFET comprising: a) a semiconductor substrate (11) of a first conductivity type (N), b) a first semiconductor region (12) of the first conductivity type provided in the semiconductor substrate (11), c) a second semiconductor region (13) of a second conductivity type (P) provided in the semiconductor substrate (11) spaced apart from the first semiconductor region (12), d) a third semiconductor region (41) of the first conductivity type (N) provided in the second semiconductor region (13), e) an insulating film (14) provided on the semiconductor substrate (11) and covering at least partly the first and second semiconductor regions (12, 13), f) a wiring layer (15) provided on the insulating film (14), connected to the first semiconductor region (12) and passing over the second semiconductor region (13), and g) a film resistor (17) formed in the insulating film (14), the film resistor (17) having a first end connected to the first semiconductor region (12) and having a second end overlying the second semiconductor region (13) which operates as the gate electrode (17') of the DMOSFET, h) wherein the film resistor (17) is disposed above the semiconductor substrate (11) and is crossed by the wiring layer (15) at least once. A device according to claim 1, characterized in that the film resistor (17) has a length sufficient to increase the resistance of the film resistor such that a leakage current flowing therethrough is small. A device according to claim 2, characterized in that the film resistor (17) is a meandering strip. A device according to claim 2, characterized in that the film resistor (17) has a corrugated structure. A device according to claim 1, characterized in that the film resistor (17) is disposed above the semiconductor substrate (11) to overlap the first and second semiconductor regions (12, 13). A device according to claim 2, characterized in that the film resistor (17) is zigzag crossed by the wiring layer (15). A device according to claim 2, characterized in that the film resistor (17) has a swirl-shaped structure. A device according to claim 1, characterized in that the film resistor (17a) comprises a plurality of diodes (30a, 30b) composed of polysilicon. A device according to claim 8, characterized in that the diodes (30a, 30b) include P-type regions (31) and N-type regions (32) alternately connected in series such that the diodes are alternately connected in forward and reverse directions. A device according to claim 1, characterized in that the third semiconductor region (41) is the source (S) region of the DMOSFET.

Inventors: ENDO KOICHI, ENDO, KOICHI, Endo, Koichi, c/o Intell.Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: H01L29
IPC codes: H01L21, H01L29