An integrated circuit comprising an EEPROM cell and a MOS transistor

Abstract: An integrated circuit structure is disclosed wherein an EPROM cell has an active area (18) formed by the same operations as are necessary to form a P region (17) intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are necessary to form the source and drain regions (31) of said transistor, a control electrode (15) consisting of an N+ region formed by the same operations as are carried out to form deep regions (14) intended to contact buried N+ regions, and a floating gate electrode (24) consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes (23) of the MOS transistors in the integrated circuit. The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

Description: This invention relates to integrated circuits, and particularly to a monolithic integrated circuit structure including at least one electrically programmable read-only memory (EPROM, EEPROM) cell as defined in the preamble of claim 1 and as known from document JP-A-1-140759. Many industrial applications require complex electronic circuits to perform multiple functions which range from the processing of signals, whether in the analog or the digital form, to the amplification of such signals and the generation of power signals for controlling and powering electric loads, e.g. motors, relays, lamps, etc.. Certain applications involve data storage functions as well. A trend toward ever more compact circuits has led to the development of processes for forming integrated circuits comprised of a large variety of electronic components, which may have even radically different structural and functional features, on a common substrate of semiconductor material. Thus, monolithic integrated structures comprising CMOS (Complementary Metal Oxide Semiconductor) circuits have been developed essentially for processing digital signals, as have bipolar circuits essentially for amplifying analog signals, DMOS (Diffused Metal Oxide Semiconductor) power components, and bipolar power components for generating and controlling high voltages and large currents. For any data storage functions, the prior art provides external devices purposely designed and constructed to perform such functions. Prior to the publication of JP-A-1-140759, it was a widespread opinion among the designers of semiconductor devices that the manufacturing processes of storage devices are too deeply different from the manufacturing processes of so-called mixed integrated circuits of the type described above, and that while memory cells may be integrated, at least in theory, to mixed integrated circuits, this would involve in pratice the addition of a number of processing steps to the already complicated manufacturing process, thereby making the process a highly critical one and the end product generally unreliable. It is the object of this invention to provide for a monolithic integrated circuit structure comprising at least one programmable read-only memory (EPROM or EEPROM) cell to be formed by a manufacturing process of mixed integrated circuits with no processing steps specifically added or with the addition of but few and non-critical processing steps. This object is achieved by an integrated circuit structure as defined in claim 1. The invention and its advantages can be more clearly understood by having reference to the following detailed description of one embodiment thereof, given by way of example and not of limitation in connection with the accompanying drawings, in which: Figure 1 is a sectional view showing schematically a structure according to the prior art, with an EPROM cell and some components obtained by a manufacturing process of a mixed integrated circuit; Figure 2 is an enlarged sectional view of the EPROM cell shown in Figure 1; Figure 3 is a plan view of the EPROM cell in Figure 2; Figure 4 is a sectional view of the EPROM cell taken along line IV-IV in Figure 3; Figures 5 and 6 are sectional views similar to Figure 4 but showing two modifications of the EPROM cell; Figure 7 is a plan view of an EEPROM cell according to an embodiment of the invention; and Figures 8 and 9 are sectional views of the EEPROM cell in Figure 7, as taken along lines VIII-VIII and IX-IX. Shown in Figure 1 are some of the principal components of a mixed integrated circuit. These are identified by the following abbreviations: HVP-CH = a high-voltage P-channel MOS transistor, VDMOS = a vertical conduction power MOS transistor, LDMOS = a horizontal conduction power MOS transistor, CMOS = a pair of complementary MOS transistors, namely a P-channel (P-CH) one and an N-channel (N-CH) one, NPN = a vertical conduction bipolar transistor of the NPN type, LPNP = a lateral, i.e. horizontal conduction, bipolar transistor of the PNP type, and EPROM = an electrically programmable read-only memory cell. In the drawing figure, the electrodes of the various components are identified as follows: S = Source, D = Drain, G = Gate, E = Emitter, B = Base, C = Collector. The main process steps for forming the structure of Figure 1 are summarized, briefly because known per se, herein below with reference to Figure 1. 1. Impurities of the N type are implanted in some selected areas and impurities of the P type are implanted in some other selected areas of a substrate, denoted by 10, of monocrystalline silicon of the P type. 2. A layer of N- silicon, designated 11, is formed by epitaxial growth at a high temperature over the substrate 10; during this step, the impurities of the N and P types implanted during the preceding step will diffuse to form buried N+ regions, designated 12, and deep isolation P regions, designated 13. 3. Deep N+ regions, denoted by 14, are formed by implantation and subsequent diffusion which extend from the front surface of the structure into the N-epitaxial layer 11 to contact some of the N+ buried regions 12, namely the drain region of the VDMOS transistor and buried collector region of the NPN transistor; during the same step, the region 15 is formed which constitutes the control electrode of the EPROM cell. 4. Formed, by implantation followed by diffusion, are intermediate isolation regions, indicated at 16, the so-called P-well region, indicated at 17, for containing the N-channel transistor of the CMOS pair, the collector region of the lateral bipolar LPNP transistor, indicated at 17', and the region, indicated at 18, which is intended to contain the active area of the EPROM cell. 5. The surface areas to be isolated from one another are defined using a LOCOS technique of local oxide growth. 6. Impurities of the P and N types are implanted in selected areas of the epitaxial layer 11. 7. Silicon dioxide regions, indicated at 19, are grown at a high temperature by the LOCOS technique to isolate the previously defined areas from one another; during this step, P regions, as indicated at 20, are formed by diffusion of the impurities implanted during the preceding step, which completes the isolation regions by delimiting portions of the N- epitaxial layer 11 therein. 8. Thin layers, indicated at 22, of silicon dioxide are formed over those areas which define the channels of the MOS transistors, including the EPROM cell channel, and the isolation layer between the floating gate and the control electrode 15 of the EPROM cell is also formed. 9. Impurities of the P type are implanted in the channel areas of the P-channel transistors of the CMOS pairs to bring down their conduction thresholds. 10. Formed from a previously deposited layer of polycrystalline silicon are the gate electrodes, indicated at 23, of the MOS transistors, the floating gate electrode, indicated at 24, of the EPROM cell, and interconnection paths, not shown, for connecting together the various components. 11. Formed, as by implantation followed by diffusion, are additional so-called body regions of the P type, indicated at 25, of the VDMOS and LDMOS transistors, as well as the base region, indicated at 26, of the vertical NPN bipolar transistor. 12. The source and drain P+ regions, indicated at 27, of the transistor HVP-CH and the P-channel transistor in the CMOS pair, P+ body surface enhancement regions 28 of the VDMOS and LDMOS transistors, base contact region 29 of the NPN bipolar transistor, and emitter region 30 of the LPNP lateral bipolar transistor are formed. 13. The N+ source regions, indicated at 31, of the VDMOS and LDMOS transistors, source and drain regions 31 of the transistor N-CH in the CMOS pair and the EPROM cell, N+ emitter region, indicated at 32, of the NPN transistor, and N+ base contact region 33 of the LPNP transistor are formed. 14. An insulating layer 34 is formed through which apertures are opened in selected areas for the ohmic contact of the various components. 15. Formed from a metallic layer previously deposited over the insulating layer 34 are ohmic contacts 35 in the selected contact areas, including that for the control electrode 15 of the EPROM cell, and electric connection paths, not shown, between components of the circuit. As can be seen, in particular from Figures 2, 3 and 4, the EPROM cell yielded by the process just described is a cell with a single layer of polycrystalline silicon and a control gate or control electrode 15 diffused through the epitaxial layer 11. The floating gate 24, formed from the polysilicon layer, is coupled capacitively to both the control electrode 15 and the active area between the source and drain regions 31, i.e. to the channel of the cell. The cell terminals comprise ohmic contacts for the source and drain 35a, 35b and control 35c electrodes (Figures 3 and 4). The cell is conventionally programmed by applying a high voltage (10 to 15 V) to the drain and control electrodes relative to the source electrode and the channel region, to thereby establish a flow of electric charges (hot electrons) from the channel to the floating gate 24 through the gate oxide. The floating gate, once charged, will alter the conduction threshold of the MOS transistor of the cell, that is the minimum source-drain voltage which admits an appreciable current flow through the channel. There are two possible threshold levels of the transistor, corresponding to a state of absence or presence of charges on the floating gate, which define the 0 or 1 logic levels of the cell. The cell state is detected, i.e. the memory cell read, by applying a low voltage (4 to 5 V) to the drain and control electrodes relatively to the source and measuring the current that flows through the channel. Since the gate 24 is fully isolated electrically, its charge state will not change during normal read operations, that is the cell will behave as a read-only memory (ROM) cell. Where necessary, this cell type can be erased, as is known, by exposure to UV radiation. In this case, of course, a transparent window to this radiation would have to be provided in the structure containing the integrated circuit with the EPROM cell. The number of EPROM cells formed will obviously be dependent on individual circuit requirements for storage. The cells may be arrayed across a single N+ region constituting the control electrode common to all the cells, or be arranged otherwise across the various side-by-side N+ regions to form a matrix of cells. It is a recognized fact that the programming speed of an EPROM cell is deeply affected by the concentration of impurities in the channel. When the channel is formed from a region with a low impurity concentration, a special surface enhancement operation is resorted to. This enhancement is advantageously obtained by utilizing the same process step wherein P impurities are implanted in the channels of the P-channel transistors of the CMOS pairs (Step 9 of the process described hereinabove), or utilizing the same process step as provided for forming the body regions of the VDMOS and LDMOS transistors (Step 11 of the process described hereinabove). Cross-sectional views of the cell structure, as altered in accordance with these two modifications, are shown in Figures 5 and 6, where the enhanced region according to the first modification is indicated at 36, and that according to the second modification is indicated at 37. As can be seen, in the embodiment described above, the EPROM cells may be formed in the structure itself of the mixed integrated circuit with no need for additional operations. In an embodiment of the invention, programmable and electrically erasable read-only memory (EEPROM) cells may also be formed in the same structure, alternatively or in combination with the EPROM cells. In this case, an N+ region, shown at 15' in Figures 7 to 9, should be formed which may be termed an injection region and would be isolated from the control electrode region 15. That region 15' is preferably formed in the active area of the cell by the same operation as detailed under 3. of the description of the manufacturing process previously provided whereby N+ deep regions are formed. Then, by a single additional operation, a depressed area 38 is formed in the insulating layer 22 which extends across the injection region 15'. More particularly, a layer of reduced thickness can be obtained by opening a small aperture through the thin layer 22 of silicon dioxide during the gate isolation layer forming step and growing a very thin (8-10 nm as against the 50-60 nm of the gate isolator) layer of silicon dioxide over the exposed surface of the injection region. A flow of charges will occur in a known manner by tunneling effect through that layer as the cell electrodes are suitably polarized. A method of isolating the injection region 15' from the control electrode region 15 would consist of forming a P region adapted to contain both said regions 15 and 15'. Advantageously, this containing region, shown at 18' in Figures 8 and 9, is formed by two P regions obtained concurrently with those for forming the isolation regions in Steps 2., 3, and 4, of the process described above . The last-mentioned expedient may also be practiced where EPROM cells are to be isolated.

Claims: A monolithic integrated circuit structure comprising at least one electrically erasable, programmable read-only memory (EEPROM) cell, which structure is formed on a chip of semiconductor material including, between its bottom surface and front surface a substrate (10) of the P type and a layer (11) of the N-type overlying the P substrate, and also comprising: buried N+ regions (12) formed between the P substrate (10) and the N- layer (11); deep N+ regions (14,15,15') extending from the front surface into the N- layer (11), at least some of said deep N+ regions being in contact with buried N+ regions (12); P regions (16,17,18) extending from the front surface into the N- layer; thin N+ regions (31) providing source and drain regions for MOS transistors and extending from the front surface into at least some of the P regions (16,17,18); thin layers (22) of an insulating material formed over selected portions of the front surface and adapted to provide gate isolation for MOS transistors; layers (23,24) of a conductive material extending over the thin isolating layers and adapted to provide gate electrodes for MOS transistors; and electric connection metallic layers extending across the front surface and being isolated therefrom by a layer (34) of an insulating material and in ohmic contact (35,35a,35b,35c) with selected areas of the deep N+ regions (14,15,15') and the thin N+ regions(31); the memory cell having an active area formed of one of said P regions (18), source and drain N+ regions in said active area formed of a pair of said thin N+ regions (31), a control electrode (15) formed of one of said deep N+ regions (14,15,15'), a floating gate electrode (24) consisting of one of said conductive material layers (23,24) and extending over that portion of the active area between the source and drain N+ regions which forms the cell channel, isolated therefrom by one of said thin layers (22) of insulating material, and over a selected area of the deep N+ region which forms the control electrode (15) and separated therefrom by one of said thin layers (22) of insulating material, and electric connections (35a,35b,35c) to the control electrode (15) and the source and drain regions (31) which are parts of said metallic paths, said monolithic integrated circuit structure being characterized in that the memory cell has an injection N+ region (15') underlying a selected area of the floating gate electrode (24), said injection region (15') being formed of one of said deep N+ regions (14,15,15') and being electrically isolated from the N+ region which constitutes the control electrode (15), and that the thin layer (22) of insulating material which separates the floating gate electrode (24) of the memory cell from the control electrode (15) extends over said injection region (15') to a reduced thickness (38) effective to admit a charge flow by tunneling effect between the floating gate electrode (24) and said injection region (15'). A structure according to Claim 1, characterized in that it comprises a plurality of isolation P regions (13,16,20) extending from the front surface of the N- layer (11) to the substrate (10) such that portions of the N- layer (11) are delimited by isolation P regions of said plurality of isolation P regions and being each formed of one (16) of said P regions (16,17,18) and of one deep P region (13) of a plurality of deep P regions (13) which extend to the substrate (10), and that the memory cell has a containing P region (18') which contains the two N+ regions forming the control electrode (15) and the injection region (15') and is formed of one of said P regions (16, 17, 18) and of one of said plurality of deep P regions (13).

Inventors: CAVIONI TIZIANA, CONTIERO CLAUDIO, MANZINI STEFANO, CAVIONI, TIZIANA, CONTIERO, CLAUDIO, MANZINI, STEFANO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21