Emitter switched thyristor and method of manufacturing the same

Abstract: An emitter switched thyristor having a large main current is disclosed. An n-type base layer (2) is formed on a p-type anode layer (1). The n-type base layer (2) includes in its top center portion a relatively heavily doped p⁺-type region (3a) which is surrounded by p-type region (3b). A p-type base layer (3) is locally coated at its top surface with a relatively thin first n-type emitter layer (4) and a relatively thick second n-type emitter layer (5). A gate electrode (8) buried in a gate oxide film (7) is disposed on two channel regions (CH1 and CH2) and areas around the same. This structure suppresses a current amplification factor of a parasitic thyristor which is formed by the n-type base layer (2), the p-type region (3b) and the first n-type emitter layer (4), which in turn repress latching up of the parasitic thyristor.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a self arc-extinguishing thyristor in which a current flow is MOS gate-controlled. Description of the Background Arts Existing IGBTs (Insulated Gate Bipolar Transistor) are known for their excellent gate-voltage controlled turning on and off of a main current. Fig. 1 shows a basic structure of an IGBT in cross section. An n-type base layer 2 is formed on a p-type anode layer 1. In a top center portion of the n-type base layer 2, a p-type base layer 3 is selectively formed. The p-type base layer 3 consists of a relatively heavily doped p + -type center region 3a and a p-type region 3b surrounding the p + -type region 3a. An n-type emitter layer 4a is selectively formed in a top portion of the p-type base layer 3. A top surface portion of the n-type emitter layer 4a and the top surface of the p + -type region 3a contiguous thereto serve as a cathode surface 6 in direct contact with which a cathode electrode 10 is disposed. An anode electrode 12 is disposed in contact with an anode surface 11, or the bottom surface of the p-type anode layer 1. A gate electrode 8 which is buried in a gate oxide film 7 lies over the p-type region 3b. By controlling a gate voltage applied to the gate electrode 8, a main current is allowed and prohibited between the cathode electrode 10 and the anode electrode 12. The current control by the gate voltage, however, does not work if a cathode-anode current develops large, thereby causing thyristor effect which latches and turns on a four-layer structure formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the n-type emitter layer 4a. Once this has happened the gate-voltage control of current becomes impossible, and hence, the four-layer structure would not turn off, eventually resulting in destruction of the device. As an improved self arc-extinguishing thyristor in which such a problem facing IGBTs is solved, an EST (Emitter Switched Thyristor) was proposed. In an EST, even if thyristor effect latched the four-layer structure formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the n-type emitter layer 4a, it is possible to turn off the four-layer structure by removing the gate voltage. More importantly, an EST purposely causes the latching and utilizes it in an attempt to attain extended control of a main current. An example of the EST is disclosed by B.J. Baliga in "IEEE ELECTRON DEVICE LETTERS," Volume 11, page 75. Fig. 2 shows a cross sectional structures of an EST unit cell 100. An n-type base layer 2 is formed on a p-type anode layer 1. The n-type layer 2 has at its interface with the p-type anode layer 1 a pn junction J 1 . A p-type base layer 3 is selectively formed in the n-type base layer 2 so as to occupy a top center portion of the cell 100. The p-type base layer 3 consists of a relatively heavily doped p + -type center region 3a and a p-type region 3b surrounding the p + -type region 3a. A pn junction J 2 is created at an interface between the n-type base layer 2 and the p-type base layer 3. A first n-type emitter layer 4 and a second n-type emitter layer 5 are selectively formed in a top portion of the p-type base layer 3. The first n-type emitter layer 4 corresponds to the n-type emitter layer 4a of the IGBT of Fig. 1. A cathode surface 6 is formed by a portion of the top surface of the first n-type emitter layer 4 and the top surface of the p + -type region 3a contiguous to the same. The second n-type emitter layer 5 surrounds the first n-type emitter layer 4. The p-type base layer 3 has at its interfaces with the first n-type emitter layer 4 and the second n-type emitter layer 5 pn junctions J 3 and J 4 , respectively. Two channel regions are formed in the vicinity of the top surface of the p-type region 3b, one between the first n-type emitter layer 4 and the second n-type emitter layer 5, namely a first channel region CH1, and the other between the second n-type emitter layer 5 and the n-type base layer 2, namely a second channel region CH2. The channel regions CH1 and CH2 are in a faced relation with gate electrodes 8a and 8b, respectively, which are buried in a gate oxide film 7 and which are electrically connected with an external gate electrode G. The gate oxide film 7 and the cathode surface 6 are entirely covered with a cathode electrode 10. Hence, the gate oxide film 7 insulates the cathode electrode 10 from both the gate electrodes 8a and 8b and the second n-type emitter layer 5. The p-type base layer 3 and the first n-type emitter layer 4 are electrically connected with each other via the cathode electrode 10. The cathode electrode 10 is electrically connected with an external cathode electrode K. An anode electrode 12 is disposed entirely across the bottom surface of the p-type anode layer 1, or an anode surface 11, so that the p-type anode layer 1 and the anode electrode 12 are electrically connected with each other. The anode electrode 12 is connected with an external anode electrode A. EST cells having a geometry as that of the unit cell 100 are arranged in parallel to each other in a matrix to thereby form an EST pellet. The gate electrodes 8a, 8b and the anode electrodes 12 of the respective unit cells 100 are electrically connected with each other. For example, the gate electrodes 8a, 8b of each cell 100 are connected with the gate electrodes 8a, 8b of a neighboring cell 100, and the gate electrodes 8a, 8b as a whole and the external gate electrode G are connected with each other by an aluminum or other suitable wire. The anode electrodes 12 are brazed to the external anode electrode A. The cathode electrodes 10 of the respective cells are also connected with each other, and further connected with the external cathode electrode K by an aluminum or other suitable wire. In the following, behavior of the EST device will be explained focusing on one unit cell 100. First, assume that the gate electrodes 8a, 8b are kept at the same potential as the cathode electrode 10 and the anode electrode 12 is kept at a higher potential than the cathode electrode 10. In this case, the pn junction J 2 is reverse-biased, thereby allowing no current between the anode electrode 12 and the cathode electrode 10. Next, assume that the anode electrode 12 is maintained at a higher potential than the cathode electrode 10 and the gate electrodes 8a, 8b are also maintained at a higher potential than the cathode electrode 10. In this case, charge storage occurs in the gate electrodes 8a, 8b and the channel regions CH1 and CH2 since the p-type region 3b is electrically connected with the cathode electrode 10 through the p + -type region 3a while the gate electrodes 8a, 8b and the p-type region 3b are coupled through the gate oxide film 7. Thus, channels are created in the respective channel regions CH1 and CH2. Since a channel at the channel region CH1 short circuits the first n-type emitter layer 4 and the second n-type emitter layer 5 while a channel at the channel region CH2 short circuits the second n-type emitter layer 5 and the n-type base layer 2, current is initiated between the anode electrode 12 and the cathode electrode 10. The current (main current) is routed from the anode electrode 12 in sequence to the p-type anode layer 1, the n-type base layer 2, the channel region CH2, the second n-type emitter layer 5, the channel region CH1, the first n-type emitter layer 4 and the cathode electrode 10. Hence, a main current exceeding a certain current value gives rise to the thyristor effect which latches and turns on the four-layer structure formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5. As a result, the unit cell 100 turns on. Once the turning on has occurred, most of the main current flows from the anode electrode 12 in sequence to the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3, the second n-type emitter layer 5, the channel region CH1, the first n-type emitter layer 4 and the cathode electrode 10, leaving a little current to flow through the channel region CH2. If the gate voltage is removed during such ON-operation, the charge stored in the channel regions CH1 and CH2 is discharged. While the discharge take places, the potential around the gate oxide film 7 exhibits an exponential-like fall, thereby extinguishing the channel short circuiting the first n-type emitter layer 4 and the second n-type emitter layer 5 and the channel short circuiting the second n-type emitter layer 5 and the n-type base layer 2. This blocks the main current in the channel region CH1 and turns off the unit cell 100 since the channel region CH2 carries a little current whereas the channel region CH1 carries most of the current in the ON-operation. As described above, no problem will be created even if the four-layer structure (i.e., main thyristor) latches which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5. However, this is not observed where the main current has further grown and latched another four-layer structure (i.e., parasitic thyristor) which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the first n-type emitter layer 4. If the parasitic thyristor has latched, a current does not flow through not only the channel region CH1 but also the channel region CH2, thereby making it impossible to turn off the parasitic thyristor by removing the gate voltage. Thus, the EST of Fig. 2 is likely to be destroyed as much as the IGBT of Fig. 1 is. DE 4130899A1 describes a large number of isolated gate thyristors capable of suppressing parasitic transistor operation such as that shown in Figure 37A. However, a heavily doped base region is arranged at one end of this device meaning that the distance travelled by stored holes at switch-off may vary widely, resulting in possible imbalance. US Patent 4500902 discloses a thyristor having a connectable emitter and another emitter. The connectable emitter has a higher current transfer ratio and is used during triggering of the thyristor to provide enhanced trigger sensitivity. EP0454201 describes an insulated gate thyristor comprising a cathode emitter region adjacent the insulated gate to provide a gateable conduction path. SUMMARY OF THE INVENTION According to the present invention, there is provided a self arc-extinguishing thyristor comprising: (a) a body including: (a-1) a first semiconductor layer of a first conductivity type; (a-2) a second semiconductor layer of a second conductivity type having a bottom surface arranged on said first semiconductor layer and having a recess at its top surface, the recess comprising a recess surface; (a-3) a third semiconductor layer of a first conductivity type having a protrusion projecting away from said recess of the second semiconductor layer; (a-4) a fourth semiconductor layer of a second conductivity type arranged in said third semiconductor layer; (a-5) a fifth semiconductor layer of a second conductivity type arranged in a shoulder portion of a top surface of said third semiconductor layer, the fifth semiconductor layer being spaced from said fourth semiconductor layer in the direction away from the top surface of said second semiconductor layer so that a bottom surface of said fifth semiconductor layer is farther from said second semiconductor layer than a top surface of said fourth semiconductor layer and so that the fourth and the fifth semiconductor layer overlap in the direction away from said top surface of the second semiconductor layer; (b) an insulation film disposed on a side wall of said protrusion extending at least from said fourth semiconductor layer to said fifth semiconductor layer; (c) a control electrode disposed at least in said insulation film so as to be in a faced relation with said third semiconductor layer; (d) a first electrode disposed in electrical connection with said third and said fifth semiconductor layers; and (e) a second electrode disposed in electrical connection with said first semiconductor layer; characterized in that the third semiconductor layer comprises: a relatively heavily doped first portion formed through the centre of said protrusion and spaced from sidewalls of said protrusion; and a relatively lightly doped second portion, said second portion together with said first portion completely occupying said third semiconductor layer; and in that the fourth semiconductor layer occupies a part of said recess and a part of said protrusion. In the first aspect of device, a top surface of the fourth semiconductor layer is preferably below the bottom surface of the fifth semiconductor layer. In the first aspect of device, the fourth semiconductor layer preferably intercepts a surface of the body only at the recessed surface and side surfaces of the protrusion. In the first aspect of device, the fifth semiconductor layer preferably intercepts the top surface of the protrusion in a ring shape. In the first aspect of device, the insulation film may include (b-1) an additional portion which extends from the second semiconductor layer, which adjoins the top surface of the body, to the fourth semiconductor layer. In the first aspect of device, the control electrode is preferably electrically connected with the third semiconductor layer. In the first aspect of device, the third semiconductor layer preferably entirely contains, at the top surface of the second semiconductor layer, the protrusion and the recessed surface contiguous thereto. In the first aspect of device, the top surface of the protrusion projects upward from a top surface of the insulation film. The device of the first aspect may further comprise a first external electrode which is in pressure contact with the first electrode. The device of the first aspect may further comprise a second external electrode which is in pressure contact with the second electrode. Thus, in the first aspect of device, the third semiconductor layer is within the protrusion and the fifth semiconductor layer is disposed on the third semiconductor layer. In addition to this, since the bottom surface of the fifth semiconductor layer is far from the bottom surface of the fourth semiconductor layer, the effect as promised in the first described device is also ensured in the device of the first aspect. According to another aspect of the present invention, there is provided a method of manufacturing a self arc-extinguishing thyristor as claimed in Claim 1, comprising the steps of: (a) forming a second semiconductor layer of a second conductivity type having a bottom surface on a first semiconductor layer of a first conductivity type; (b) forming a portion of a third semiconductor layer of a first conductivity type at least selectively in a top surface of said second semiconductor layer; (c) forming a fourth semiconductor layer of a second conductivity type selectively in a top surface of said portion of the third semiconductor layer; (h) selectively thickening said third semiconductor layer to thereby form a protrusion extending away from said top surface of said second semiconductor layer, side surfaces of which protrusion contains said fourth semiconductor layer; (d) forming a fifth semiconductor layer of a second conductivity type selectively in said top surface of said third semiconductor layer spaced from said fourth semiconductor layer in the direction away from said top surface of said second semiconductor layer so that a bottom surface of said fifth semiconductor layer is farther from said second semiconductor layer than a top surface of said fourth semiconductor layer and so that the fourth and the fifth semiconductor layer overlap in the direction away from said top surface of said second semiconductor layer; (e) forming an insulation film on said surfaces of said protrusion extending at least from said fourth to said fifth semiconductor layers in such a manner that a control electrode is buried in said insulation film in a faced relation with said third semiconductor layer; (f) forming a first electrode in electrical connection with said third and said fifth semiconductor layers; and (g) forming a second electrode in electrical connection with said first semiconductor layer. In the first aspect of method, the step (a) may be substantially the step of (a-1) epitaxially growing the second semiconductor layer on the first semiconductor layer. In the first aspect of method, the step (a) may be substantially the step of (a-2) diffusing second conductivity type impurities into the first semiconductor layer. In the first aspect of method, the step (a) may be substantially the step of (a-3) bonding the second semiconductor layer to the first semiconductor layer. In the first aspect of method, the step (b) may substantially consists of the steps of: (b-1) growing a first oxide film having a first aperture on the second semiconductor layer; and (b-2) injecting first conductivity type first impurities into the second semiconductor layer which is masked by the first oxide film and thereby forming a first portion of the third semiconductor layer. In the first aspect of method, the injection of the first impurities is preferably ion implantation. In the first aspect of method, the injection of the first impurities may be followed by diffusion. In the first aspect of method, the step (c) preferably comprises the steps of: (c-1) growing on the second semiconductor layer a second oxide film having a second aperture which is wider than the first aperture and which therefore contains the first aperture; and (c-2) injecting first conductivity type second impurities into the second semiconductor layer which is masked by the second oxide film and thereby forming a second portion of the third semiconductor layer. In the first aspect of method, the first portion preferably has a higher impurity concentration than the second portion. In the first aspect of method, the step (d) may comprise the steps of: (d-1) growing on the second and the third semiconductor layers a third oxide film having a third aperture which is contained in the second aperture; and (d-2) injecting second conductivity type third impurities into the third semiconductor layer which is masked by the third oxide film. In the first aspect of method, the third aperture may be ring-shaped. In the first aspect of method, the step (e) preferably comprises the steps of: (e-1) growing a fourth oxide film which extends from the second to the fourth semiconductor layers and which entirely covers the fourth semiconductor layer and growing a fifth oxide film which covers the first portion; (e-2) forming a control electrode on the fourth oxide film; and (e-3) injecting second conductivity type fourth impurities into the third semiconductor layer which is masked by the fourth and the fifth oxide films and the control electrode. In the first aspect of method, the fifth semiconductor layer may be ring-shaped inside the fourth semiconductor layer. The method of third aspect may further comprise the step of (e-4) growing a sixth oxide film on a top and side surfaces of the control electrode and side surfaces of the fourth oxide film, wherein the insulation film substantially consists of the fourth and the sixth oxide films. In the first aspect of method, the step (f) may be substantially the step of (f-1) vacuum evaporating metal on the entire surface of a structure resulted from the steps (a) to (e). In the first aspect of method, the step (g) may be substantially the step of (g-1) vacuum evaporating metal on a bottom surface of the first semiconductor layer. Thus, the first aspect method is suitable for fabrication of the self arc-extinguishing thyristor of the first aspect of device. In the first aspect of the method, the step (h) preferably includes the steps of: (h-1) forming a second conductivity type a sixth semiconductor layer on a top surface of a structure resulted from the steps (a) to (c); and (h-2) selectively removing the fourth and the sixth semiconductor layers. The top surface of the protrusion may be substantially occupied by the sixth semiconductor layer. In the first aspect of the method, the step (h-1) may be substantially the step of (h-1-1) epitaxially growing the sixth semiconductor layer on the top surface of the structure resulted from the steps (a) to (c). In the first aspect of the method, the step (h-2) preferably involves removal of the second and the third semiconductor layers. In the first aspect of the method, the step (h) may farther comprise the step of (h-3) increasing the impurity concentration of the sixth semiconductor layer. In the first aspect of the method, the step (d) preferably involves selective formation of the fifth semiconductor layer in the top surface of the protrusion. In the first aspect of the method, the fifth semiconductor layer is preferably formed around the protrusion. In the first aspect of the method, the fourth semiconductor layer may be formed to surround the protrusion. In a first aspect of method, the protrusion may be formed to be thicker than the insulation film. The method of the first aspect may farther comprise the step of (I) forming a first external electrode which is in pressure contact with the first electrode. The method of the first aspect may further comprise the step of (j) forming a second external electrode which is in pressure contact with the second electrode. In a first aspect of method, the third semiconductor layer is preferably formed on the entire top surface of the second semiconductor layer in the step (b) and the control electrode is preferably disposed in electrical connection with the third semiconductor layer in the step (e). The second aspect method is suitable for fabrication of self arc-extinguishing thyristor of the first aspect of device. Thus, the self arc-extinguishing thyristors according to the present invention see less chance of latching of the parasitic thyristor which is formed by the first to the third and the fifth semiconductor layers, thereby allowing increased control of a larger main current and hence more reliable prevention of destruction of the device associated with the latching. The manufacturing methods heretofore described are suitable for fabricating the self arc-extinguishing thyristors of the present invention. Accordingly, it is an object of the present invention to offer a self arc-extinguishing thyristor in which a large main current is ensured. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross sectional view showing a conventional IGBT structure; Fig. 2 shows a cross sectional structures of a conventional EST unit cell; Fig. 3 shows a plan view and a cross sectional structure of a known EST cell for assisting the description of the present invention. Figs. 4 to 10 are cross sectional views of the structure of Fig. 3 during successive stages in its manufacturing process; Fig. 11 shows a plan view and a cross sectional structures according to a first preferred embodiment of the present invention; Fig. 12 is a cross sectional view showing a modification of the first preferred embodiment; Figs. 13 to 18 are views of the structure of Fig. 11 during successive stages in its manufacturing process; Figs. 19 to 22 are views of the structure of Fig. 12 during successive stages in its manufacturing process; Fig. 23 is a cross sectional view showing another modification of the first preferred embodiment of the present invention; and Figs. 24 to 26 are views of the structure of Fig. 28 during successive stages in its manufacturing process. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 3 shows a cross sectional structure of a known EST unit cell 101 for assisting the description of the present invention. An n-type base layer 2 is formed on a p-type anode layer 1. A pn junction J 1 is created at an interface between the p-type anode layer 1 and the n-type base layer 2. In a top center portion of the cell 101 of the n-type base layer 2, a p-type base layer 3 is selectively formed which consists of a relatively heavily doped p + -type center region 3a and a p-type region 3b surrounding the p + -type region 3a. The n-type base layer 2 forms a pn junction J 2 at its interface with the p-type base layer 3. A first n-type emitter layer 4 and a second n-type emitter layer 5 are selectively formed in a top portion of the p-type base layer 3 so that the first n-type emitter layer 4 is surrounded by the second n-type emitter layer 5. The p-type base layer 3 forms a pn junction J 3 at its interface with the first n-type emitter layer 4 and another pn junction J 4 at its interface with the second n-type emitter layer 5. Since the first n-type emitter layer 4 is thinner than the second n-type emitter layer 5, a distance between the pn junctions J 3 and J 2 is larger than a distance between the pn junctions J 4 and J 2 . Two channel regions are formed in the vicinity of the top surface of the p-type region 3b, one between the first n-type emitter layer 4 and the second n-type emitter layer 5, i.e., a first channel region CH1, and the other between the second n-type emitter layer 5 and the n-type base layer 2, i.e., a second channel region CH2. A gate electrode 8 buried in a gate oxide film 7 lies over the channel regions CH1 and CH2 and areas around the same. The gate electrode 8 is electrically connected with an external gate electrode G. A top surface portion of the first n-type emitter layer 4 and the top surface of the p + -type region 3a form a cathode surface 6. The cathode surface 6 and the gate oxide film 7 are covered with a cathode electrode 10. Hence, the gate electrode 8 and the second n-type emitter layer 5 are each insulated from the cathode electrode 10 by the gate oxide film 7. On the other hand, the p-type base layer 3 and the first n-type emitter layer 4 electrically contact each other through the cathode electrode 10. The cathode electrode 10 is electrically connected with an external cathode electrode K. An anode electrode 12 is disposed entirely across the bottom surface of the p-type anode layer 1, or an anode surface 11, so that the p-type anode layer 1 and the anode electrode 12 are in electrical contact with each other. The anode electrode 12 is connected with an external anode electrode A. In an EST pellet, a plurality of the EST unit cells 101 are arranged and integrated parallel with each other in a matrix. The gate electrodes 8, the cathode electrodes 7 and the anode electrodes 10 of the respective unit cells 101 are electrically connected with each other. For instance, the gate electrode 8 of each cell 101 is connected with the gate electrode 8 of a neighboring cell 101. The gate electrodes 8 as a whole and the external gate electrode G are connected with each other by an aluminum or other suitable wire. The anode electrodes 12 of the respective cells are brazed or otherwise connected to the external anode electrode A. The cathode electrodes 10 of the respective cells are also connected with each other. Electrical connection between the electrodes 10 as a whole and the external cathode electrode K is ensured by an aluminum wire and the like. In the following, behavior of the unit cell 101 will be described. First, assume that the gate electrode 8 is kept at the same potential as the cathode electrode 10 and the anode electrode 12 is kept at a higher potential than the cathode electrode 10. In this case, since the pn junction J 2 is reversely biased, no current is initiated between the anode electrode 12 and the cathode electrode 10. Next, assume that the anode electrode 12 is maintained at a higher potential than the cathode electrode 10 and the gate electrode 8 is also maintained at a higher potential than the cathode electrode 10. In this case, charge storage occurs in the gate electrode 8 and the channel regions CH1 and CH2 since the p-type region 3b is electrically connected with the cathode electrode 10 through the p + -type region 3a while the gate electrode 8 and the p-type region 3b are coupled through the gate oxide film 7. Thus, channels are created in the respective channel regions CH1 and CH2. Since a channel at the channel region CH1 short circuits the first n-type emitter layer 4 and the second n-type emitter layer 5 while a channel at the channel region CH2 short circuits the second n-type emitter layer 5 and the n-type base layer 2, current is initiated between the anode electrode 12 and the cathode electrode 10. The main current flows from the anode electrode 12 in sequence to the p-type anode layer 1, the n-type base layer 2, the channel region CH2, the second n-type emitter layer 5, the channel region CH1, the first n-type emitter layer 4 and the cathode electrode 10. Hence, if the main current exceeds a certain value, the thyristor effect occurs which latches and turns on a four-layer structure formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5, eventually activating the unit cell 101. Once the unit cell 101 has turned on, most of the main current flows from the anode electrode 12 in sequence to the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3, the second n-type emitter layer 5, the channel region CH1, the first n-type emitter layer 4 and the cathode electrode 10. Thus, only a little current flows through the channel region CH2. Removal of the gate voltage during this ON-operation causes discharge of the charge stored in the channel regions CH1 and CH2, in the process of which the potential around the gate oxide film 7 exponentially decreases. This extinguishes the channel short circuiting the first n-type emitter layer 4 and the second n-type emitter layer 5 and the channel short circuiting the second n-type emitter layer 5 and the n-type base layer 2. Since the channel region CH2 carries a little current while the channel region CH1 carries most of the current during the ON-operation, the main current, a primary component of the current, is blocked in the channel region CH2, thereby turning off the unit cell 101. As described above, no problem will be caused even if the four-layer structure (i.e., main thyristor) latches which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5, which is the same as in the conventional EST unit cell. Likewise the conventional unit cell, the unit cell 101 includes a four-layer structure (i.e., parasitic thyristor) which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the first n-type emitter layer 4. However, the unit cell 101 is different from the conventional unit cell in that the distance between the pn junctions J 3 and J 2 is larger than the distance between the pn junctions J 4 and J 2 . Due to this characteristic geometry, a transistor formed by the n-type base layer 2, the p-type base layer 3 and the first n-type emitter layer 4, which a part of the parasitic thyristor, has a smaller current amplification factor than a transistor formed by the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5, which a part of the main thyristor. Hence, the unit cell 101 sees less chance of latching of the parasitic thyristor than the conventional EST unit cell, preventing destruction of the device associated with latching of the parasitic thyristor. Figs. 4 to 10 show a manufacturing method of the unit cell 101. The illustrative manufacturing method corresponds to a manufacturing method of a known self arc-extinguishing thyristor for describing the present invention. A first step of fabrication is formation of the n-type base layer 2 on the p-type anode layer 1 by epitaxial growth, diffusion or bonding (Fig. 4). Following this, an oxide film 13a which serves as a mask is selectively formed on the n-type base layer 2, and the p + -type region 3a is implanted or diffused through an aperture of the oxide film 13a (Fig. 5). The oxide film 13a is then removed and an oxide film 13b having a wider aperture than the oxide film 13a is selectively grown on the n-type base layer 2. The p-type region 3b is implanted or diffused through the aperture of the oxide film 13b, thereby completing the p-type base layer 3 (Fig. 6). The oxide film 13b is thereafter removed and an oxide film 13c is selectively grown on the n-type base layer 2 and the p-type base layer 3. The oxide film 13c has a narrower aperture than the oxide film 13b and completely covers the p + -type region 3a. The second n-type emitter layer 5 is implanted or diffused through the aperture of the oxide film 13c (Fig. 7). Next, the oxide film 13c is removed, and an oxide film 7a is selectively formed on the second n-type emitter layer 5 which has an aperture narrower than the oxide film 13c itself. An oxide film 13d is selectively grown on the p + -type region 3a and a portion of the p-type region near the p + -type region 3a. The gate electrode 8 is then formed on the oxide film 7a. The gate electrode 8 may be made of polysilicon. The first n-type emitter layer 4 is then implanted or diffused through the aperture of the oxide films 7a and 13d (Fig. 8). In a next stage, side walls of the oxide film 7a and side and top surfaces of the gate electrode 8 are covered with an oxide film, whereby the gate electrode 8 is buried in the gate oxide film 7 (Fig. 9). By forming the cathode and the anode electrodes 10 and 12 by a known technique such as vacuum evaporation of aluminum, fabrication of the unit cell 101 completes (Fig. 10). 〈Preferred Embodiment 1〉 Fig. 11 shows a cross sectional structure of an EST unit cell 102 according to a first preferred embodiment of the present invention. The first preferred embodiment corresponds to a self arc-extinguishing thyristor of the first aspect of the invention. The unit cell 102 is comprised of a semiconductor body and electrodes sandwiching the same. Silicon is used for a base member of the semiconductor body. The bottom most portion of the semiconductor body is occupied by a p-type anode layer 1 so that the p-type anode layer 1 is exposed to the bottom surface of the semiconductor body, or an anode surface 11. Across the top surface of the p-type anode layer 1, an n-type base layer 2 is disposed which selectively includes in its top surface a p-type base layer 3. The p-type base layer 3 consists of a relatively heavily doped p + -type center region 3a and a p-type region 3b which surrounds the p + -type region 3a at the top surface of the semiconductor body. The n-type base layer 2 forms a pn junction J 1 at its interface with the p-type anode layer 1 and a pn junction J 2 at its interface with the p-type base layer 3. The semiconductor body has a recessed surface 6b from which a protrusion projects upward. The protrusion has a top surface 6a and side surface 6c. The top surface 6a serves as a cathode surface. The p + -type region 3a and the p-type region 3b are partially included in the protrusion. A second n-type emitter layer 5 and a first n-type emitter layer 4 are selectively formed in space in the p-type base layer 3 in such a manner that the second n-type emitter layer 5 adjoins the recessed and the side surfaces 6b and 6c while the first n-type emitter layer 4 adjoins the top and the side surfaces 6a and 6c. A pn junction J 3 is created at an interface between the first n-type emitter layer 4 and the p-type base layer 3. A pn junction J 4 is created at an interface between the second n-type emitter layer 5 and the p-type base layer 3. The pn junction J 3 intercepts the side surface 6c at an end and the top surface 6a at the other end while the pn junction J 4 intercepts the side surface 6c at an end and the recessed surface 6b at the other end. In the unit cell 102 tailored as above, a channel region CH1 is realized at a portion of the p-type base layer 3 which resides between the side surface 6c of the protrusion and a channel region CH2 is realized at a portion of the p-type base layer 3 which resides below the recessed surface 6b. The recessed and the side surfaces 6b and 6c are covered with a gate oxide film 7 in which a gate electrode 8 is buried. The gate electrode 8 buried in the gate oxide film 7 is in a faced relation with the portions of the first n-type emitter layer 4 adjoining the side surface 6c, the channel region CH1, the exposed surface of the second n-type emitter layer 5, the channel region CH2 and the exposed surface of the n-type base layer 2. Due to the existence of the gate oxide film 7, the parts of the semiconductor body listed immediately above are electrically insulated from the gate electrode 8. A cathode electrode 10 is disposed to entirely cover the semiconductor body and the gate oxide film 7. Since the cathode electrode 10 is in contact with the p-type base layer 3 and the first n-type emitter layer 4 at the top surface 6a of the protrusion, the p-type base layer 3 and the first n-type emitter layer 4 are electrically connected with each other. An anode electrode 12 is disposed across the bottom surface of the p-type anode layer 1, or the anode surface 11, thereby electrically connecting the p-type anode layer 1 and the anode electrode 12. A plurality of such EST unit cells 102 are arranged and integrated parallel with each other in a matrix so that an EST pellet is formed, which is similar to that described previously. The gate electrodes 8 of the respective unit cells 102 are electrically connected with each other on the pellet and further with the external gate electrode G. The cathode electrodes 7 of the respective unit cells 102 are electrically connected with each other in a similar manner. The anode electrodes 10 of the respective unit cells 102 are contiguous to each other. Principles of turn-on turn-off control of the EST unit cell 102 remain the same as those of the EST unit cell 101. That is, the unit cell 102 is turned on by keeping the anode electrode 12 and the gate electrode 8 each at a higher potential than the cathode electrode 10, and turned off by removing the gate voltage applied to the gate electrode 8. Similarly to the conventional unit cell, the unit cell 102 of the first preferred embodiment includes a four-layer structure (i.e., main thyristor) which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5 and another four-layer structure (i.e., parasitic thyristor) which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the first n-type emitter layer 4. However, since the unit cell 102 requires that the first n-type emitter layer 4 is formed above the second n-type emitter layer 5 and hence the pn junction J 3 is located above the pn junction J 4 , a transistor formed by the n-type base layer 2, the p-type base layer 3 and the first n-type emitter layer 4, which are a part of the parasitic thyristor, has a smaller current amplification factor than a transistor formed by the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5, which are a part of the main thyristor. Hence, the unit cell 102 of the first preferred embodiment shares with the prior art the same effect that the parasitic thyristor is less likely to be latched than in the conventional device. The first preferred embodiment has an advantage over the prior art Since the first and the second n-type emitter layers 4 and 5 are disposed in an overlapping relation in a direction of their thicknesses, the top surface of the semiconductor body is effectively utilized and a current capacity per unit area is enhanced. The unit cell of the first preferred embodiment may have the protrusion which outsoars the gate oxide film 7 as shown in Fig. 12. In such a modification, the gate oxide film 7 will not be damaged even if a cathode electrode body 14 and an anode electrode body 15 are disposed in pressure contact with the unit cell 102. By use of the cathode and the anode electrode bodies 14 and 15, heat created at device operations is effectively dissipated from the two sides of the unit cell 102 through the cathode and the anode electrode bodies 14 and 15. A manufacturing method of the structure of Fig. 11 is shown in Figs. 13 to 18. The illustrative manufacturing method corresponds to a manufacturing method of a self arc-extinguishing thyristor of the first aspect of the invention. First, the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5 are formed through the same process steps as those illustrated in Figs. 4 to 7 (Fig. 13). Next, on the entire surface of the resultant structure, a p-type layer 31 is epitaxially grown (Fig. 14) which is etched except at a region which lies on both the p + -type region 3a and a portion of the p-type region 3b near the p + -type region 3a until the n-type base layer 2 is exposed. As a result, the recessed surface 6b is defined (Fig. 15). The gate electrode 8 buried in the gate oxide film 7 is then formed on the recessed surface 6b (Fig. 16). Following this, the p-type layer 31 is integrated with the p + -type region 3a by ion implantation of diffusion, whereby the first n-type emitter layer 4 is defined (Fig. 17). By forming the cathode and the anode electrodes 10 and 12 through the process step shown in Fig. 10, e.g., by vacuum evaporation of aluminum or other known technique, fabrication of the unit cell 102 completes (Fig. 18). A manufacturing method of the structure illustrated in Fig. 12 is shown in Figs. 19 to 22 The illustrative manufacturing method corresponds to a manufacturing method of a self arc-extinguishing thyristor of the first aspect of the invention. The structure of Fig. 12 is processed in a similar manner to the fabrication of the structure of Fig. 11 up to the stage shown in Fig. 15 where the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3, the second n-type emitter layer 5 and the p-type layer 31 are completed so that the recessed surface 6b is defined (Fig. 19). Then, a treatment as that shown in Fig. 16 is performed to bring about a similar result that the gate electrode 8 buried in the gate oxide film 7 is formed on the recessed surface 6b. To obtain the structure of Fig. 12, however, the top surface 6a of the protrusion needs to be formed so as to project upward beyond the top surface of the gate oxide film 7 (Fig. 20). Next, the p-type layer 31 is integrated with the p + -type region 3a through process steps as shown in Figs. 17 and 18. As a result, the first n-type emitter layer 4 is defined and the cathode and the anode electrodes 10 and 12 are formed (Fig. 21). Following this, the cathode electrode body 14 is attached to the cathode electrode 10 in pressure contact and the anode electrode body 15 is attached to the anode electrode 12 in pressure contact (Fig. 22). 〈Modified Embodiment 1〉 From the description of the self arc-extinguishing thyristor of the present invention, it is understood that the channel region CH2 is not essential to the thyristor structures. Fig. 23 is a cross sectional view of a unit cell 105, or a modification of the first preferred embodiment. In the unit cell 105, the gate oxide film 7 does not completely cover the n-type base layer 2 and allows an end portion 8c of the gate electrode 8 to electrically contact with the p-type base layer 3 in the recessed surface 6b. Even without assistance of the channel region CH2, a higher potential at the gate electrode 8 than at the cathode electrode 10 initiates a current flow from the gate electrode 8 to the cathode electrode 10, with a consequence that the unit cell 105 is turned on. Of great importance, a main thyristor is latched promptly which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the second n-type emitter layer 5, thus suppressing power loss even when a main current is small. The unit cell 105 of this modification is turned off by removing the gate voltage applied to the gate electrode 8 and consequently blocking a current flow in the channel region CH1, which is similar to the first preferred embodiment. A parasitic thyristor would not be easily latched which is formed by the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3 and the first n-type emitter layer 4. A manufacturing method of the unit cell 105 is shown in Figs. 24 to 26. The illustrative manufacturing method corresponds to a manufacturing method of a self arc-extinguishing thyristor of the fourth aspect of the invention. Process steps as those shown in Figs. 13 to 15 are performed to form the p-type anode layer 1, the n-type base layer 2, the p-type base layer 3, the second n-type emitter layer 5 and the p-type layer 31 so as to define the recessed surface 6b. The p-type base layer 3 may be formed on the entire top surface of the n-type base layer 2 since the channel region CH2 is unnecessary (Fig. 29). Then, the gate electrode 8 is formed which has the end portion 8c which is eventually connected with the p-type base layer 3 at the recessed surface 6b, immediately followed by provision of the gate oxide film 7 in which the gate electrode 8 is buried (Fig. 25). Treatments as those shown in Fig. 17 and 18 are then performed in which the p-type layer 31 is integrated with the p + -type region 3a, the first n-type emitter layer 4 is created, and the cathode and the anode electrodes 10, 12 are formed. This completes fabrication of the unit cell 105 (Fig. 26.). If necessary, the gate electrode 8 and the end portion 8c are formed in space and electrically connected with each other by a suitable resistor and the like. This modification has no influence over device operation. This modification is also applicable to the first embodiment with no damage to the effect of the invention, which is needless to mention. While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous modifications and variations can be devised without departing from the scope of the invention as set out in the accompanying claims.

Claims: A self arc-extinguishing thyristor comprising: (a) a body including: (a-1) a first semiconductor layer (1) of a first conductivity type; (a-2) a second semiconductor layer (2) of a second conductivity type having a bottom surface arranged on said first semiconductor layer and having a recess at its top surface, the recess comprising a recess surface; (a-3) a third semiconductor layer (3) of a first conductivity type having a protrusion projecting away from said recess of the second semiconductor layer; (a-4) a fourth semiconductor layer (5) of a second conductivity type arranged in said third semiconductor layer; (a-5) a fifth semiconductor layer (4) of a second conductivity type arranged in a shoulder portion of a top surface of said protrusion of said third semiconductor layer, the fifth semiconductor layer being spaced from said fourth semiconductor layer in the direction away from the top surface of said second semiconductor layer so that a bottom surface of said fifth semiconductor layer is farther from said second semiconductor layer than a top surface of said fourth semiconductor layer and so that the fourth (5) and the fifth (4) semiconductor layer overlap in the direction away from said top surface of the second semiconductor layer; (b) an insulation film (7) disposed on a side wall of said protrusion extending at least from said fourth semiconductor layer to said fifth semiconductor layer; (c) a control electrode (8) disposed at least in said insulation film (7) so as to be in a faced relation with said third semiconductor layer (3); (d) a first electrode (10) disposed in electrical connection with said third (3) and said fifth (4) semiconductor layers; and (e) a second electrode (12) disposed in electrical connection with said first semiconductor layer; characterized in that the third semiconductor layer comprises: a relatively heavily doped first portion (3a) formed through the centre of said protrusion and spaced from sidewalls of said protrusion; and a relatively lightly doped second portion (3b), said second portion together with said first portion completely occupying said third semiconductor layer; and in that the fourth semiconductor layer is arranged in at least a part of said protrusion having an end in the first portion. The self arc-extinguishing thyristor of claim 1, wherein said fourth semiconductor layer (5) intercepts a surface of said body only at said recessed surface and side surfaces of said protrusion. The self arc-extinguishing thyristor of claim 2, wherein said protrusion is an island shape and said fifth semiconductor layer surrounds said first portion of said third semiconductor layer at said protrusion. The self arc-extinguishing thyristor of claim 2, wherein said insulation film includes (b-1) an additional portion which extends from said second semiconductor layer (2), which adjoins said top surface of said body, to said fourth semiconductor layer (5). The self arc-extinguishing thyristor of claim 2, wherein said third semiconductor layer (3) entirely contains, at said top surface of said second semiconductor layer, said protrusion and said recessed surface contiguous thereto. The self arc-extinguishing thyristor of claim 5, wherein said control electrode (8) is electrically connected with said second portion of said third semiconductor layer (3) at said recessed surface. The self arc-extinguishing thyristor of claim 4, wherein said top surface of said protrusion projects upward from a top surface of said insulation film (7). The self arc-extinguishing thyristor of claim 7, further comprising a first external electrode which is in pressure contact with said first electrode (10). The self arc-extinguishing thyristor of claim 8, further comprising a second external electrode which is in pressure contact with said second electrode (12). A method of manufacturing a self arc-extinguishing thyristor as claimed in claim 1, comprising the steps of: (a) forming a second semiconductor layer (2) of a second conductivity type having a bottom surface on a first semiconductor layer (1) of a first conductivity type; (b) forming a portion of a third semiconductor layer (3) of a first conductivity type at least selectively in a top surface of said second semiconductor layer; (c) forming a fourth semiconductor layer (5) of a second conductivity type selectively in a top surface of said portion of the third semiconductor layer; (h) selectively thickening said third semiconductor layer (3) to thereby form a protrusion extending away from said top surface of said second semiconductor layer, side surfaces of which protrusion contains said fourth semiconductor layer (5); (d) forming a fifth semiconductor layer (4) of a second conductivity type selectively in said top surface of said third semiconductor layer (3) spaced from said fourth semiconductor layer (5) in the direction away from said top surface of said second semiconductor layer so that a bottom surface of said fifth semiconductor layer is farther from said second semiconductor layer than a top surface of said fourth semiconductor layer and so that the fourth (5) and the fifth (4) semiconductor layer overlap in the direction away from said top surface of said second semiconductor layer (2); (e) forming an insulation film (7) on said surfaces of said protrusion extending at least from said fourth (5) to said fifth (4) semiconductor layers in such a manner that a control electrode is buried in said insulation film in a faced relation with said third semiconductor layer (3); (f) forming a first electrode (10) in electrical connection with said third and said fifth semiconductor layers; and (g) forming a second electrode (12) in electrical connection with said first semiconductor layer. The method of claim 10, wherein said step (a) is substantially the step of (a-1) epitaxially growing said second semiconductor layer on said first semiconductor layer. The method of claim 10, wherein said step (a) is substantially the step of (a-2) diffusing second conductivity type impurities into said first semiconductor layer (1). The method of claim 10, wherein said step (a) is substantially the step of (a-3) bonding said second semiconductor layer (2) to said first semiconductor layer (1). The method of claim 10, wherein said step (b) substantially consists of the steps of: (b-1) growing a first oxide film having a first aperture on said second semiconductor layer (2); and (b-2) injecting first conductivity type first impurities into said second semiconductor layer (2) which is masked by said first oxide film and thereby forming a first portion of said third semiconductor layer (3). The method of claim 14, wherein the injection of said first impurities is ion implantation. The method of claim 14, wherein the injection of said first impurities is followed by diffusion. The method of claim 14, wherein said step (c) comprises the steps of: (c-1) growing on said second semiconductor layer a second oxide film having a second aperture which is wider than said first aperture and which therefore contains said first aperture; and (c-2) injecting first conductivity type second impurities into said second semiconductor layer which is masked by said second oxide film and thereby forming a second portion of said third semiconductor layer. The method of claim 17 wherein said first portion has a higher impurity concentration than said second portion. The method of claim 17, wherein said step (d) comprises the steps of: (d-1) growing on said second and said third semiconductor layers a third oxide film having a third aperture which is contained in said second aperture; and (d-2) injecting second conductivity type third impurities into said third semiconductor layer which is masked by said third oxide film. The method of claim 19, wherein said third aperture is ring-shaped. The method of claim 19, wherein said step (e) comprises the steps of: (e-1) growing a fourth oxide film which extends from said second to said fourth semiconductor layers and which entirely covers said fourth semiconductor layer and growing a fifth oxide film which covers said first portion; (e-2) forming a control electrode on said fourth oxide film; and (e-3) injecting second conductivity type fourth impurities into said third semiconductor layer which is masked by said fourth and said fifth oxide films and said control electrode. The method of claim 21, wherein said fifth semiconductor layer is ring-shaped inside said fourth semiconductor layer. The method of claim 21, further comprising the step of (e-4) growing a sixth oxide film on a top and side surfaces of said control electrode and side surfaces of said fourth oxide film, wherein said insulation film substantially consists of said fourth and said sixth oxide films. The method of claim 21, wherein said step (f) is substantially the step of (f-1) vacuum evaporating metal on the entire surface of a structure resulted from said steps (a) to (e). The method of claim 24, wherein said step (g) is substantially the step of (g-1) vacuum evaporating metal on a bottom surface of said first semiconductor layer. The method of claim 10, wherein step (h) preferably includes the steps of: (h-1) forming a sixth semiconductor layer of a second conductivity type on a top surface of a structure resulted from said steps (a) to (c); and (h-2) selectively removing said fourth and said sixth semiconductor layers, and wherein a top surface of said protrusion may be substantially occupied by said sixth semiconductor layer. The method of claim 26, wherein said step (h-1) is substantially the step of (h-1-1) epitaxially growing said sixth semiconductor layer on said top surface of said structure resulted from said steps (a) to (c). The method of claim 26, wherein said step (h-2) involves removal of said second and said third semiconductor layers. The method of claim 28, wherein said step (h) further comprises the step of (h-3) increasing the impurity concentration of said sixth semiconductor layer. The method of claim 29, wherein said step (d) involves selective formation of said fifth semiconductor layer in said top surface of said protrusion. The method of claim 30, wherein said fifth semiconductor layer is formed around said protrusion. The method of claim 31, wherein said fourth semiconductor layer is formed to surround said protrusion. The method of claim 10, wherein said protrusion is formed to be thicker than said insulation film. The method of claim 33, further comprising the step of (i) forming a first external electrode which is in pressure contact with said first electrode. The method of claim 34, further comprising the step of (j) forming a second external electrode which is in pressure contact with said second electrode. The method of claim 10, wherein said third semiconductor layer is formed on the entire top surface of said second semiconductor layer in said step (b) and said control electrode is disposed in electrical connection with said third semiconductor layer in said step (e).

Inventors: NIWAYAMA KAZUHIKO, NIWAYAMA, KAZUHIKO, NIWAYAMA, KAZUHIKO, C/O MITSUBISHI DENKI K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: H01L29
IPC codes: H01L21, H01L29