Etching silicon nitride in a process comprising selective oxidation of a trench side wall in a semiconductor wafer

Abstract: The present invention is directed to a technique for selectively oxidizing trench side walls in a silicon substrate. Each of the side walls can be oxidized individually and to different thicknesses according to the requirements of the trench IC, by using a silicon nitride oxidation mask.

Description: The present invention relates to the preamble of claim 1. BACKGROUND OF THE INVENTION Because of the requirements in semiconductor technology to form integrated circuits (IC's) with higher and higher integration densities, trench technology in IC's has attracted much attention. This technology offers additional device areas and an extra degree of freedom in designing semiconductor devices. Such technology in designing semiconductor devices may be seen, for example, in U.S. Patents 4,437,226 or 4,756,793, as well as Japanese Patent Application No. 1-64336 A. These references involve providing films on trench side walls for semiconductor devices. Moreover, the concept of selective etching has been considered in the prior art, such as seen, for example, in Japanese Application No. 1-64336 A as well as U.S. Patent 4,514,251. These various references involve various techniques for forming features in semiconductor technology which provides a basis for accomplishing the presently claimed invention. For example, while the various references discuss oxidation of trench surfaces, nowhere is there any discussion of providing selective growth of oxidation layers at different side walls of the trenches. This knowledge occurs from the present application. Patent abstract JP-A-63133658 discloses a method as mentioned in the preamble of claim 1. It is not disclosed however how the portion of silicon nitride should be removed over the selected sidewall of said trench to expose said first oxide. SUMMARY OF THE INVENTION The method mentioned in the opening paragraph is, according to the invention, characterized by the characterizing part of claim 1. It has been found that ion bombardment using boron, B+, ions at various implant energies results in selective etching at about twice the rate of etching without the ion bombardment. The ion bombardment may occur at various energies, such as 40 keV, 80 keV, or 120 keV, for example. In addition, the etching of the damaged portion is effectively carried out in hot phosphoric acid (H 3 PO 4 ). This etch is especially effective at temperatures, such as about 150°C. The ion bombardment for damaging a nitride layer on a trench side wall is carried out at tilted angles relative to the exposure in the trench. Such angles of ion bombardment may be determined by the width and depth of the trench. These angles may vary up to about 45°, for example. BRIEF DESCRIPTION OF THE DRAWING FIGURES The present invention may be seen by reference to the attached drawing figure which shows without limitation an example of the structure obtained during carrying out the present invention. The drawing is a generalized drawing and is not made to scale dimensionally although it shows differences in side walls oxidation thicknesses. DESCRIPTION OF THE INVENTION The selective oxidation of trench side walls in semiconductor wafers, such as silicon wafers makes use of the technique of growing a first oxide layer over the entire trench surface area. This first oxide layer is grown to a thickness which may be denominated as TO1. Thereafter, silicon nitride is deposited over the first layer of oxide in the trench by chemical vapor deposition (CVD). A selected side wall of the trench is determined and this side wall is damaged by way of an ion implantation, for example, at a predetermined angle to cover the area of the side wall. Thereafter, the damaged portion of the silicon nitride is etched by a wet etch such as, for example, phosphoric acid (H 3 PO 4 ). This etching of the damaged nitride portion occurs at a rate that is twice that of the etching of non-damaged areas in the same etchant. It therefore leaves about 1/3 of the non-damaged nitride while removing the damaged nitride. The exposed first oxide layer is then wet etched and selectively oxidized to a target thickness, such as TO2, where TO2 is greater than TO1. Thereafter, the remaining nitride is wet etched, and the oxide at a thickness of TO1 is then wet etched. This oxide can be thermally regrown to another thickness TO1 i , while the thickness TO2 becomes a third thickness TO3. These latter steps are optional, and may not be necessary for achieving appropriate oxidized trench side walls. The result of this may be seen by reference to the drawing figure in which one side wall 1 of the trench may have a oxide layer of about 2500 angstroms in thickness, while another trench side wall 2 may have an oxide of about 1000 angstroms in thickness. This technique can be repeated at various side walls of the trench, as well as the bottom 3 of the trench. In this manner, the various side and bottoms can each be formed with respective different thicknesses of an oxide layer.

Claims: A method of manufacturing semiconductor devices wherein trench walls formed in a silicon body are selectively oxidized, comprising the steps of: a) growing a first oxide layer over the entire area of a trench to a first thickness, b) depositing silicon nitride over said first oxide layer, c) removing a portion of silicon nitride over a selected side wall of said trench to expose said first oxide, d) etching the exposed portion of said first oxide layer and e) selectively oxidizing said etched and exposed portion to a second thickness different from said first thickness, characterized in that step c) is carried out by first damaging said portion with ions and then by etching the damaged portion away in hot H 3 PO 4 . A method according to claim 1, characterized in that the step of damaging is carried out by ion bombardment with boron ions. A method according to claim 2, characterized in that said ion bombardment is carried out at 40 keV, 80 keV or 120 keV. A method according to claim 1, 2 or 3, characterized in that the step of damaging is carried out by ion bombardment at a predetermined angle.

Inventors: TSOU LEN-YUAN, TSOU, LEN-YUAN, TSOU, LEN-YUAN, C/O INT. OCTROOIBUREAU B.V.
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1993
Main classification: H01L21
IPC codes: H01L21