Semiconductor memory device with redundancy

Abstract: The semiconductor memory device includes at least one pair of redundant digit lines (RD,RDb), first input/output lines (IO,IOb) connected to a pair of digit lines (D,Db) via a respective sense amplifier (SA) and a switch (SW), second input/output lines (IO',IOb')connected to the redundant digit line pair (RD,RDb) via a sense amplifier (RSA) and switch (RSW), and selective amplifier means (IOSW, IOSW`, RIOSW, RIOSW`) for amplifying second input/output lines when redundant digit lines are selected. With this configuration, even when the redundant digit line pair is substituted for the digit line pair, it is possible to execute the redundancy operation by mere translation between these input/output line pairs.

Description: This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a digit line redundancy circuit. In a conventional semiconductor memory there may be found a digit line redundancy circuit having a digit line substitution address programming circuit. In such a semiconductor memory, redundant digit lines are used instead of the digit lines corresponding to input column addresses when the address programming circuit generates a redundancy signal. The digit line substitution address programming circuit is programmed by melting a fuse corresponding to the address of a defective digit line, discovered by electrical, laser irradiation or other types of inspection. The operation of a conventional semiconductor memory device with a digit line redundancy circuit is as follows. First, the digit line substitution address programming circuit generates a redundancy signal when an input column address corresponds to the address of a defective digit line. In response to this redundancy signal, an enable signal for a column decoder goes to an inactive state, and a redundant digit line selection signal is activated. Since the enable signal for the column decoder is in an inactive state at this time, digit line selection signals all go to the inactive state, so that the input/output (IO) lines and the digit lines corresponding to the input column address are not connected. Accordingly, only the redundant digit lines are connected to the IO lines for a data write/read operation. However, in the conventional digit line redundancy circuit mode, where selection is made between connecting the digit lines or the redundant digit lines to the same IO lines, there is a possibility of generating a multiple selected state in which the digit lines and the redundant digit lines are connected simultaneously to identical IO lines. That is, a redundant digit line selection signal is activated in response to the redundancy signal generated by the digit line substitution address programming circuit, but at the same time the enable signal for the column decoder starts to go to the inactive state, namely, the generation of the digit line selection signal of the column decoder begins to be inhibited. Accordingly, since the time of activation of the redundant digit line selection signal is simultaneous with the time of inactivation of the enable signal for the column decoder, there is a possibility of an instantaneous occurrence, at this time, of a multiple selected state in which the digit line selection signal and the redundant digit line selection signal are simultaneously in the active state. When the multiple selected state occurs, data on the IO lines become erroneous, and therefore the memory malfunctions. Further, let us consider what happens when the selected state of the redundant digit lines goes to the selected state of the normal bit lines. The circuit which judges that the normal digit lines are selected with a change in column addresses is also the digit line substitution address programming circuit. It is this circuit which changes the redundancy signal from the active state to the inactive state in response to the input column addresses. In response to this change, the enable signal for the column decoder goes from the inactive state to the active state, causing the column decoder to operate. In other words, in the operation of returning to the normal digit lines, the column decoder is operated only after the change in the redundancy signal so that there is a problem that the activation and the operation of the column decoder are delayed. US-A-4,691,300 discloses a semiconductor memory device according to the preamble of the claim which achieves a first column access time and excludes the possibility of multiple selected states. It is an object of the invention to provide a semiconductor memory device in which additionally a parallel test can be conducted in which both the digit lines and the redundant digit lines can be selected simultaneously. This object is achieved by a semiconductor memory device as defined in the claim. The above-mentioned and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein: FIG.1 is a circuit diagram for the semiconductor memory device which is a first embodiment of the invention; FIG.2 is another circuit diagram for the semiconductor memory device of the first embodiment of the invention; FIG.3 is a waveform diagram for describing the operation of the semiconductor memory device shown in FIG.1 and FIG. 2; FIG.4 is another waveform diagram for describing the operation of the semiconductor memory device shown in FIG.1 and FIG.2; FIG.5 is a circuit diagram for the semiconductor memory device which is a second embodiment of the invention; and FIG.6 is another circuit diagram for the semiconductor memory device of the second embodiment of the invention. Referring to FIG.1 and FIG.2 showing a first embodiment of this invention, the semiconductor memory device of this embodiment has a configuration in which the digit lines are subdivided into two groups, and is operated in its normal mode by bringing one of the two column decoders (14 and 14`) to an active state in response to input addresses. In addition, as a countermeasure to the increase in testing time accompanying a high capacity memory, the memory has a parallel test mode which reads simultaneously data of a plurality of cells on the same word lines. In the parallel test mode, data in two memory cells connected to the same word lines in the same cell array are output simultaneously to two pairs of IO lines, IO,IOb and IO`,IOb` (see FIG.2). A digit line substitution address programming circuit 11 is programmed by melting the fuse of the column address corresponding to a digit line found defective by inspection. This programming circuit 11 receives column addresses Y0 to Yk, and brings ØR and ØRS to the active state when it detects that an input address is for a redundant digit line. The column addresses Y0 to Yk are input to a column address predecoder circuit 12 and column decoder enable signal generating circuit 10 and 10`. The circuit 12 predecodes the column addresses, and outputs predecoded signals Y01 to Yi-li to column decoder circuits 14 and 14`. An address signal Aj and a parallel test signal ØT are input to an address buffer circuit 15 that detects which one of the two groups of the digit line groups is selected. When ØT is in the inactive state, ØYjT is brought to the active state if Aj is a positive logic whereas ØYjN is brought to the active state if Aj is a negative logic. On the other hand, when ØT is in the active state, ØYjT and ØYjN are invariably in the active state. The circuit 10 receives the column address Yk, an enable inhibit signal ØRD and ØYjN, and generates column decoder enable signals ØE and ØEB (the two signals are in complementary relation) in response to the column address Yk when ØYjN is in the active state and ØRD is in the inactive state. The circuit 10` receives the column address Yk, the enable inhibit signal ØRD and ØYjT, and generates column decoder enable signals ØE` and ØEB` under similar conditions. An inhibit circuit 16 receives ØR and ØT, and inhibits activation of the column decode enable signals ØE,ØEB or ØE`,ØEB` when ØT is in the active state. Accordingly, at the time of normal operation other than during the parallel test mode, activation of the column decoder enable signal will not be inhibited even if the programming circuit 11 detects that the input column addresses are for redundant digit lines. The column decoder 14 has the predecoded signals Y01 to Yi-li and the enable signals ØE and ØEB as inputs, and brings either one of digit line selection signals ØSW1 to ØSWx to the active state in response to the predecoded signals when the column decoder enable signals are in the active state. The column decoder 14` has a similar configuration. Redundant digit line selection signal generating circuits 13 and 13' receive ØRS generated by the programming circuit 11 and ØYjT or ØYjN, and generate selection signals ØRSW and ØRSW`, respectively, when both ØRS and ØYjN are in the active state. Next, referring to FIG.2, the configuration of the memory cell array and the IO lines will be described. The digit line group is subdivided into two groups (D, Db and D`, Db`), and there exist redundant digit line pairs RD, RDb and RD`, RDb` that correspond to the groups, respectively. The digit lines D and Db forming a pair (in reality there are a plurality of such pairs) are in complementary relationships, and a sense amplifier SA for amplifying the potentials of the two digit lines is connected to the pair. The outputs of the sense amplifier SA are connected to a first IO line pair, IO and IOb, via a switching circuit SW whose switching is controlled by a digit line selection signal ØSW1. The redundant digit line pair, RD and RDb, corresponding to the digit line pair, D and Db, is connected to the sense amplifier RSA, and the outputs of the same amplifier RSA are connected to a second IO line pair, IO` and IOb`, via a switching circuit RSW whose switching is controlled by the redundant digit line selection signal ØRSW. The configuration of the other digit line pair, D` and Db`, and the corresponding redundant digit line pair, RD` and RDb`, is similar to the above. What is important here is the fact that the IO line pair connected to the digit line pair and the IO line pair connected to the redundant digit line pair are different IO line pairs. The first IO line pair, IO and IOb, and the second IO line pair, IO` and IOb`, are connected to IOSW, RIOSE, IOSW` and RIOSW` that constitute an IO line pair switching circuit, and the switching of the IO line pair switching circuit is controlled by the signal ØR. When ØR is in the inactive state, namely, when the normal digit lines are selected, IOSW and IOSW` go to the on-state, whereas when ØR is in the active state, namely, when the redundant digit lines are selected, RIOSW and RIOSW` go to the on-state. The outputs of the IO line pair switching circuit are connected to data amplifier circuits 41 and 42, and write circuits 43 and 44. The data amplifier 41 and write circuit 43 operate when ØYjN is in the active state, and the data amplifier circuit 42 and the write circuit 44 operate when ØYjT is in the active state. Next, referring also to FIG.3 which is a timing diagram when redundant digit lines are selected and FIG.4, the operation of this embodiment will be described. First, the normal operation mode will be described. At the time of the normal operation, the parallel test signal ØT stays in the inactive state all the time and the inhibit circuit 16 always outputs ØRD at the low level, so that activation of the enable signals ØE, ØEB or ØE`, ØEB` will not be inhibited. In other words, even when the redundant digit lines are used, activation of the column decoder enable signals will not be inhibited. Further, since ØT is in the inactive state, the address buffer circuit 15 brings either one of ØYjT and ØYjN to the active state in response to the address signal Aj. In this embodiment, the case of ØYjN being in the active state will be described as an example. The circuit 10 will go to the active state in response to ØYjN in the active state. Accordingly, the enable signals ØE and ØEB go to the active state, and as a result, the column decoder circuit 14 goes to the active state. When the input column addresses Y0 to Yk are for the normal digit lines, the circuit 11 keeps ØR and ØRS at the low level. Consequently, the circuit 13 is not activated, and the selection signal ØRSW also maintains the low level. The column decoder circuit 14 brings either one of the selection signals ØSW1 to ØSWx (for example, ØSW1) to the active state. As ØSW1 goes to the active state, the switching circuit SW (see FIG.2) goes to the on-state, and the data on the digit line pair, D and Db, are amplified by the sense amplifier SA to be output to the IO line pair, IO and IOb. Since ØR is at the low level at this time, IOSW and IOSW` of the IO line pair switching circuit go to the on-state, and the first IO line pair, IO and IOb, is connected by ØYjN to the data amplifier circuit 41 and the write circuit 43 that are in the active state. On the other hand, when the input column address Y0 to Yk are for redundant digit lines (see the time t1 in FIG.3), the circuit 11 brings ØR and ØRS to the high level. Accordingly, the circuit 13 is activated, and the selection signal ØRSW is brought to the high level. Now, when ØT is in the inactive state, the inhibit circuit 16 will not inhibit the activation of the column decoder enable signal, as mentioned above. Accordingly, the column decoder circuit 14 brings either one of the digit line selection signals ØSW1 to ØSWx (for example, ØSW2) to the active state in response to the changed predecoded signals. As the selection signal ØRSW goes to the active state, the switching circuit RSW (see FIG.2) goes to the on-state, data on the digit line pair, RD and RDb, are amplified by the sense amplifier RSA, and are output to the second line pair, IO` and IOb`. Since ØR is at the high level at this time, RIOSW` of the IO line pair switching circuit goes to the on-state and the second IO line pair, IO` and IOb`, is in the active state in response to ØYjN being in the active state. On the other hand, the first IO line pair, IO and IOb, receives data on a digit line pair (not shown) corresponding to the digit line selection signal ØSW2, and is connected to the data amplifier circuit 42 and the write circuit 44 via RIOSW that is in the on-state, of the IO line pair switching circuit. Since, however, ØYjT is in the inactive state, the data amplifier circuit 42 and the write circuit 44 will not operate. As is clear from the above operations, since the IO line pair that is connected to the digit line pair is different from the IO line pair that is connected to the redundant digit line pair, in this embodiment, even when the redundant digit line pair is substituted for the digit line pair, it is possible to perform the redundancy operation by the mere substitution of these IO line pairs. Accordingly, there is absolutely no possibility of having multiple selections on the same IO line pair as is the case with the conventional device; and there is no need for the operation, at the time of switching from the redundant digit lines to the normal digit lines, of releasing the inhibition on the activation of the column decoder enable signal and activating the column decoder as is required in the conventional case, enabling thereby to increase the operating speed. In the present embodiment, the access speed to the column address was increased by 10 to 20 %. Moreover, since it is possible to use as the second pair of IO lines the IO line pair which has been used conventionally in the parallel test that will be described next, this invention becomes applicable without increasing the occupation area of the device. Next, referring to FIG.4, the operation at the time of parallel test will be described. Since the parallel test signal ØT is in the active state at the time of parallel test, and since the inhibit circuit 16 brings ØRD to the active state when ØR is in the active state, the circuit 16 inhibits the column decoder enable signal generating circuits 10 and 10` to activate the column decoder enable signals ØE,ØEB or ØE`,ØEB`. In addition, since ØT is in the active state, the address buffer circuit 15 always brings both ØYjT and ØYjN to the active state. In other words, at the parallel test both the digit line selection signal and the redundant digit line selection signal are generated simultaneously. When the column addresses Y0 to Yk are for the normal digit lines, the circuit 11 maintains ØR and ØRS at the low level. Accordingly, since the inhibit circuit 16 brings ØRD to the inactive state, it will not inhibit the circuits 10 and 10` to activate the column decoder enable signals ØE,ØEB or ØE`,ØEB`. Moreover, the circuits 13 and 13` are not activated, and the selection signals ØRSW and ØRSW` will also be maintained at the low level. The column decoder circuits 14 and 14` activate one each out of the digit line selection signals ØSW1 to ØSWx and ØSW1` to ØSWx' (for example, ØSW1 and ØSW1`) in response to the predecoded signals. As both ØSW1 and ØSW1` go to the active state, the switching circuits SW and SW'(see FIG.2) are brought to the on-state, and the data on the digit line pair, D and Db, is output to the first IO line pair, IO and IOb, and at the same time the data on the digit line pair D` and Db`,is output to the second IO line pair IO` and IOb`. Since both ØYjT and ØYjN are in the active state, the amplifier circuits 41 and 42, and the write circuits 43 and 44 all go to the active state. Further, since OR is at the low level, IOSW and IOSW` of the IO line pair switching circuit go to the on-state and the first IO line pair, IO and IOb, is connected to the data amplifier circuit 41 and the write circuit 43, and the second IO line pair, IO` and IOb`, is connected to the data amplifier 42 and the write circuit 44. With the above operation, a simultaneous read/write operation of two data becomes possible. On the other hand, when the input column addresses Y0 to Yk are for redundant digit lines (see the time tl in FIG.4), the circuit 11 brings ØR and ØRS to the high level. Accordingly, the circuits 13 and 13` are activated, and the selection signals ØRSW and ØRSW` go to the high level. In addition, since the inhibit circuit 16 activates ØRD, the circuits 10 and 10` are inhibited to activate the column decoder enable signals ØE,ØEB and ØE`, ØEB`. Accordingly, the column decoder circuits 14 and 14` will not generate activated digit line selection signals. As the selection signals ØRSW and ØRSW` go to the active state, both switching circuits RSW and RSW`(see FIG.2) go to the on-state, the data on the digit line pair, RD and RDb, is output to the second IO line pair, IO` and IOb`, and the data on the digit line pair, RD` and RDb`, is output to the first IO line pair, IO and IOb. Since ØR is at the high level at this time, RIOSW and RIOSW` of the IO line pair switching circuit go to the on-state and the second IO line pair, IO` and IOb`, is connected to the data amplifier circuit 41 and the write circuit 43 that are in the active state, and the first IO line pair, IO and IOb, is connected to the data amplifier circuit 41 and the write circuit 43 that are in the active state. Next, referring to FIG.5, the second embodiment of this invention is the same as the first embodiment except that IOSW, RIOSW, IOSW` and RIOSW` that constitute the IO line pair switching circuits in the first embodiment are absent, and that signals for controlling the data amplifier circuit 41 and 42 and the write circuit 43 and 44 are ØYjT` and ØYjN`. Therefore, its detailed description will be omitted. The generating circuit of ØYjT' and ØYjN' is shown in FIG.6. In the following, in which the group of digit lines D and Db of the digit line group is selected, the case of ØYjN being at the high level, will be described as an example. When the normal digit lines are in use, ØYjT` and ØYjN` are identical to ØYjT and ØYjN' since OR is at the low level. As ØYjN` goes to the active level, the first IO line pair, IO and IOb, connected to the digit lines D and Db is connected to the data amplifier circuit 41 and the write circuit 43 that are in the active state. On the other hand, when the redundant digit lines are in use, OYjT` and OYjN' are identical to OYjN and OYjT since OR is at the high level. In other words, the logical values of OYjT and OYjN are output inverted. Accordingly, OYjT` goes to the active state, and the second IO line pair, IO` and IOb`, connected to the redundant digit line pair, RD and RDb, is connected to the data amplifier circuit 42 and the write circuit 44 that are in the active state. As is clear from the above description, this embodiment makes it possible to execute the selection of the two IO line pairs identical to that of the first embodiment without the use of the IO line pair switching circuit of the first embodiment by changing the activity of the group of the data amplifier circuit and the write circuit (that is, whether 41 and 43 are to be activated or 42 and 44 are to be activated). Accordingly, this invention has the effect of eliminating the need for the switching.

Claims: A semiconductor memory device comprising: a decoder circuit (14, 14') which generates a digit line selection signal (ØSW1, ØSW1') that selects predetermined digit lines (D, Db) in response to input addresses (Y0-Yk), a discrimination circuit (11) which discriminates whether redundant digit lines (RD, RDb) are selected based on said input addresses, a circuit (13, 13') which generates a redundant digit line selection signal (ØRSW, RSW') that selects said redundant digit lines in response to a discrimination signal (ØR) of said discrimination circuit, first input/output lines (Io, Iob') connected respectively to the digit lines (D, Db) via a group of switches (SW) whose activation is controlled in response to said digit line selection signal, second input/output lines (Io, Iob) connected to the redundant digit lines (RD, RDb) via a switch (RSW) whose activation is controlled in response to said redundant digit line selection signal, and selecting means (15, 41, 42, IOSW, IOSW', RIOSW, RIOSW') for selecting said second input/output lines in response to said discrimination signal, characterized in that said selecting means is a selective amplifier means for selectively amplifying said input/output lines (Io, Iob) and includes a first amplifier circuit (41) connected to said first input/output lines (Io, Iob), a second amplifier circuit (42) connected to said second input/output lines (Io', Iob'), means (15) for activating said second amplifier circuit when said redundant digit lines are selected, and means (15) for activating both of said first and second amplifier circuits (41, 42) when said redundant digit lines are selected at the time of parallel testing.

Inventors: MATSUI YOSHINORI, MATSUI, YOSHINORI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: G06F11
IPC codes: G11C11, G11C29, G11C16, G11C17