Adaptive-learning type product-sum operation neuron circuit

Abstract: The present invention relates to a product-sum operation circuit element and a circuit for addition by weighting a number of signals input in one neuron circuit (N₁, N₂, ... N n ) in a neural network, and can provide an adaptive-learning neuron circuit (N₁, N₂, ... N n ) for changing an interval of output pulses by learning by connecting a simple pulse generating circuit consisting of at least capacitance, resistance, unijunction transistor UJT and MISFET. A product-sum operation circuit element according to the present invention, comprises an insulator substrate (35), a single crystal semiconductor thin film (36, 37) having a p-n-p or n-p-n structure in a lateral direction formed in the shape of stripes on the insulator substrate (35), a ferroelectric thin film (38) deposited thereon for covering at least the semiconductor stripe structure (36, 37), and a stripe-like gate electrode 39 consisting of a metal or a polycrystalline semiconductor formed thereon for intersecting said semiconductor stripes at a right angle or suitable angle.

Description: The present invention relates to an adaptive-learning type product-sum operation neuron circuit for weighing and adding a number of signals input into a plurality of neuron circuits in a neural network. As a method of giving a weight function to the input portion of a neuron circuit, i.e., synaptic connection, there are two possibilities on the one hand giving a value obtained by software simulation as a certain value and on the other hand determining the optimum value by learning with a teacher after the construction of a network. Both methods have a problem of enormously increasing learning time in a practical network having more than 10,000 neurons. Document GEKKAN SEMICONDUCTOR WORLD, vol. 11, January 1992, JAPAN ; pages 98-101 ; ISHIWARA, describes realizing a self-learning function by means of a MISFET (metal insulator semiconductor field effect transistor) provided with a ferroelectric gate insulator film whose polarization can be gradually changed by applying signal pulses. The present invention is to obviate the aforesaid shortcoming. The present invention relates to a circuit as set out in claim 1. Such a circuit can be used for making the weight of synaptic connection the optimum by adaptive-learning with the aid of residual polarization of a ferroelectric film, and when this circuit is used, even if the use of a network is started under such a condition that the weight of synaptic connection is not the optimum, a function of making the weight of synaptic connection the optimum as the use is progressed can be expected. A concrete circuit constructs a matrix of synaptic connection of m × n by connecting in parallel adaptive-learning type MISFET (metal-insulator-semiconductor field effect transistors) with the use of a ferroelectric thin film as a gate insulating film by m stages equal to a number of input signals to form synaptic connection of one neuron circuit, and further aligning the MISFETs for other neuron circuits so that n rows are formed in total. Further characteristics of the circuit of the present invention lie in the following points. An embodiment of the present invention is obtained by providing a product-sum operation circuit comprising an insulator substrate, a single crystal semiconductor thin film having a p-n-p or n-p-n structure in a lateral direction formed in the shape of stripes on the insulator substrate, a ferroelectric thin film deposited thereon for covering at least the semiconductor stripe structure, and a strip-like electrode consisting of a metal or a polycrystalline semiconductor further formed thereon for intersecting the semiconductor stripes at a right angle or suitable angle. A further embodiment of the circuit of the present invention is obtained by providing an adaptive-learning type product-sum operation circuit comprising a neuron circuit as a constituent having such an adaptive-learning function that a parallel circuit of adaptive-learning type MISFET is connected to a capacitance C in series, resistances R 2 and R 3 are made the other sides of a bridge and connected by a unijunction transistor (UJT), and a junction point of said MISFET and capacitance C is connected to the UJT for narrowing an interval between output pulses by a positive excitatory control signal entered into the MISFET and widening an interval between output pulses by a negative inhibitory control signal entered into the other MISFET. Still a further embodiment of the circuit of the invention is obtained by providing an adaptive-learning type product-sum operation circuit, comprising a photoconductor PC1 conducted by an excitatory optical information input signal and a photo-conductor PC2 conducted by an inhibitory optical information input signal connected in series between positive and negative terminals, a series circuit of a capacitance C and an adaptive-learning type FET connected between said positive and earth terminals, an LED and a series circuit of a UJT and a resistance are connected in parallel, a junction point of said photoconductor is connected to a gate electrode of said adaptive-learning type FET, an intersecting point of the adaptive-learning type FET and the capacitance C is connected to the UJT, the circuit comprising excitatory and inhibitory controls means for narrowing and widening a pulse interval of output pulses by receiving optical information input signals in PC1 and PC2, respectively. Yet still a further embodiment of the circuit of present invention is obtained by providing an provide an adaptive-learning type product-sum operation circuit comprising a series circuit of a p-channel MOSFET switch 18 conducted by an excitatory information input signal and an n-channel MOSFET switch 19 conducted by an inhibitory information input signal, a series circuit of a capacitance C and an adaptive-learning type MISFET 41, a series circuit of a resistance 26, a unijunction transister UJT 42 and a resistance R, a series circuit of a p-channel MOSFET 40 and resistances 28, 29, these circuits being connected in parallel, respectively, a junction point 20 of said FET switches 18 and 19 being connected to a gate electrode of said adaptive-learning type FET 41, a junction point 21 of said adaptive-learning type FET 41 and capacitance C being connected to said UJT 42, a junction point 27 of said UJT 42 and resistance 26 being branched from an excitatory information output terminal 24 and connected to a gate electrode of said p-channel MOSFET 40, an inhibitory information output terminal 25 provided between the resistances 28 and 29, wherein the circuit further comprises excitatory control means for narrowing a pulse interval of an output pulse voltage and inhibitory control means for widening a pulse interval of an output pulse voltage. Yet still a further embodiment of the circuit of the present invention is obtained by providing an adaptive-learning type product-sum operation circuit array comprising an array network of neuron circuits of m × n by providing m stages of a series circuit of a photoconductor PC1 conducted by an excitatory optical information input signal, neuron circuits of n rows and a photoconductor PC2 conducted by an inhibitory optical information input signal between positive and negative terminals, excitatory control means for narrowing an interval of output pulses of each neuron circuit element by excitatory control signals, and inhibitory control means for widening an interval of output pulses of each neuron circuit element by inhibitory control signal, and further comprising adaptive-learning functions such as complement of a displaced or missing letter or pattern of input picture information. Yet still a further embodiment of the circuit of the present invention is obtained by providing an adaptive-learning type product-sum operation circuit array comprising an array network of neuron circuits of m × n by providing m stages of a series circuit of a semiconductor switch conducted by an excitatory electric input signal, n rows of neuron circuits and a semiconductor switch conducted by an inhibitory electric information input signal between positive and negative terminals, excitatory control means for narrowing an interval of output pulses of each neuron circuit by excitatory control signals and inhibitory control means for widening an interval of output pulses of each neuron circuit by inhibitory control signals, and further comprising adaptive-learning functions such as complement of a displaced or missing letter or pattern of an input electric information signal. Here, a semiconductor stripe on an insulator substrate corresponds to a portion where metal-insulator-semiconductor field effect type transistors (MISFETs) are connected in parallel, and the uppermost metal or polycrystalline semiconductor electrode corresponds to gate electrodes of the MISFETs. This structure is characterized by enabling to give a field which can change residual polarization of a ferroelectric film only at a gate insulating film of FET of an intersecting point between a semiconductor stripe and a gate electrode stripe to where a suitable voltage is given. Therefore, when this novel characteristic is used, initial weights of every synapse can be set independently. When a simple pulse generating circuit consisting of a capacitance, a resistance, a unijunction transistor and the like is connected to a circuit according to the present invention, there can be manufactured an adaptive-learning neuron circuit which changes an interval of output pulses by learning. For a better understanding of the circuit of the invention, reference is made to the accompanying drawing, in which: Figs. 1(A) and 1(B) are a principle explanatory view and its equivalent circuit diagram of the present circuit; Fig. 2 is a view showing calculation of the threshold voltage of a MIS diode used in the present invention, the charge density of a semiconductor surface and the condition of time elapsed of a pulse voltage; Fig. 3 is a characteristic diagram showing the relation between a pulse voltage (V) applied to the circuit shown in Fig. 1 and learning times; Fig. 4(A) and 4(B) are fundamental circuits of a pulse generator used in the present invention; Fig. 5(A) is a circuit showing one embodiment of using an optical information input signal according to the present invention, and Fig. 5(B) is a circuit showing one embodiment of using an electric information input signal according to the present invention; Fig. 6 is a circuit showing one embodiment of applying the present invention to a neuron array with the use of an optical information input signal; Figs. 7(A) and 7(B) are a cross-sectional view and a plan view showing one embodiment of an adaptive-learning type product-sum operation neuron circuit of the present invention; and Fig. 8 is a circuit showing another embodiment of applying the present invention to a neuron array with the use of an electric information input signal. Throughout the specification, same reference numeral designate same object or body. 1 is a source, 2 is a drain, 3 is a gate, 4 is a ferroelectric film, 5 is a p-type (n-type) semiconductor, C is a capacitance, R 1 , R 2 , R 3 are resistances, 6 is an input terminal, 7 is an output terminal, 8 is a bias voltage terminal, 9, 14, 30 are +V 0 terminals, 10, 15, 31 are -V 0 terminals, 11, 12 are intermediate points, 16, 17 are input terminals, 18, 19 are FET switches, 20, 21, 22, 27 are intermediate points, 13, 23 are earth terminals, 24, 25 are output terminals, 26, 28, 29 are resistances, 34 is an optical output portion, 35 is an insulator substrate, 36, 37 are Si stripes, 38 is a ferroelectric thin film, 39 is a gate electrode, 40 is a p-channel MOSFET, 41 is an adaptive-learning type MISFET, 42 is a unijunction transistor (UJT), 45, 46 are FET switches, UJT is a unijunction transistor, PC1 is an excitatory photoconductor, PC2 is an inhibitory photoconductor, 47 is an output terminal. The present invention relates to an adaptive-learning neuron circuit having a high density synapse connection consisting of a ferroelectric thin film. The circuit construction of the present invention will be explained by referring to the accompanying drawings in detail. The circuit of the invention achieves an adaptive-learning function by means of an adaptive-learning type MISFET and according to the following principle : (1) The adaptive-learning function has the following two properties. 1 ○ changing or complementing a part or the whole of electrical or optical properties of a device during a period of processing a certain number of usual signals. 2 ○ returning the circuit to the initial state by inputting an initializing signal. That is, the property 1 ○ is for changing a normally OFF-type FET to a normally ON-type FET during a period of applying a certain number of input signals to a gate, and the property 2 ○ is for generating a change of the properties under a sufficiently controlled condition, and it is different from deterioration of a device by input signals. A function similar to this adaptive-learning function is to apply a special control signal different from a usual signal so as to change the condition of a device. This function is different from the adaptive-learning function in the point of using a control signal, which is specified as a self-control function in the circuit of the present invention. A typical self-control device is an electrically erasable non-volatile memory (EEPROM), wherein a read-out signal corresponds to a usual signal, and a write-in signal and an erase signal correspond to special control signals. (2) Operational principle of the adaptive-learning type MISFET The adaptive-learning type MISFET provided in the circuit of the present invention has the same structure as that of the usual MOSFET as shown in a schematic diagram of Fig. 1, but the point of using a ferroelectric thin film as a gate insulating film is novel. Fig. 1 shows an enhancement type FET of an n channel, and when a positive pulse voltage is applied to a gate, an inversion layer is formed at a channel portion in case of applying a pulse and the FET turns ON. At the same time, polarization is generated in the ferroelectric thin film, and this polarization remains even after the voltage is back to 0, so that a conductive layer is stationarily formed on the surface of a semiconductor after several pulses are applied, and source and drain become ON even after a gate voltage is made 0. That is, the FET is changed to a normally ON-type FET by learning. (3) Quantitative analysis of the MIS diode In order to quantitatively examine the operation of the FET shown in Fig. 1, it is necessary to clarify switching properties of a ferro electric thin film in the first place. The ferroelectric thin film requires a switching time t s for inverting spontaneous polarization P s . The switching time in case of applying an electric field E more than a coercive electric field E c is expressed as follow formula. t s = t so exp (E a /E) where, E a is an activation field, which value changes according to the kind of a ferroelectric material. The above equation shows that in general, the stronger the electric field is applied, the shorter time the polarization is inverted. Next, a time change of polarization after the electric field E is applied at time t=0 is shown by the following formula. P = P s [1-2exp{-(t/t s ) n }] where, n is a growth dimension of a domain, and in case of a thin film, n=2.5 is theoretically obtained. The formula (2) shows the state of changing the polarization P from -P s of the time t=0 to +P s of the time t=∞, but its change is continuous, and in case of finite t, P takes an appropriate value between -P s and +P s . It is further considered that P is maintained at the same value after E is made zero at room temperature, so that residual polarization after applying n times of pulses of pulse width τ is obtained by placing t=nτ in formula (2). Fig. 2 shows a calculation example of a threshold voltage of a MIS diode having a metal/ferroelectric film/Si structure and a charge density of a semiconductor surface. For the calculation in Fig. 2, PZT was assumed as a ferroelectric material, and use were made of P s =20 µC/cm 2 (=1.2×10 14 electron/cm 2 ), ε=500, E a =120 kV/cm, t so =12 ns, d=90 nm, N A =1×10 16 cm -3 and V G =5 V. It is further assumed that a ferroelectric thin film is completely polarized to make the surface of semiconductor to an accumulation condition at the initial condition. It is understood from Fig. 2 that a hole density of the semiconductor surface decreases every time when a signal pulse is input, and an inversion layer is formed on the surface of semiconductor after applying the third pulse in this example. On the other hand, it is understood that the surface condition of the semiconductor is again changed toward the initial accumulation condition when a negative bias is applied. Fig. 3 shows a relation between the learning times and a gate input voltage, where the learning times means number of input pulses until an inversion layer is formed on the initially accumulated semiconductor surface. Assumed numerical values are the same as those of Fig. 2. Fig. 3 is usable as a design chart for obtaining the thickness of a gate insulating film when learning times is designated. In Fig. 1, 1 is a source electrode, 2 is a drain electrode, 3 is a gate electrode, 4 is a ferroelectric thin film, and 5 is a p type or n type semiconductor made of silicon (Si) and the like on an insulator substrate, and adaptive-learning effect means that the polarization of the ferroelectric thin film is gradually changed and a resistance value between the source electrode 1 and the drain electrode 2 is changed during usual signal pulses are applies to the gate electrode 3. Fig. 2 shows a calculation data of a threshold voltage of a MIS diode having a metal/ferroelectric film/Si structure and a charge density of a semiconductor surface. Fig. 3 shows a relation between a pulse voltage (V) applied to a MIS diode and a learning times, wherein "learning times" means pulse number for changing the Si surface of the MIS diode to an inversion condition. This number is changed by making the width of 1 pulse 5 ns within a range of 50 nm to 3 µm of a film thickness d of the ferroelectric thin film. Fig. 4 shows a fundamental circuit of a pulse generator known as a trigger circuit of thyristor. In the circuit of Fig. 4, UJT (unijunction transistor) is used as a switch for discharging a capacitance C, and a pulse interval is determined by a time constant of CR 1 . Therefore, if a resistance R 1 is replaced by a source-drain resistance of adaptive-learning FET, it becomes possible to change an output pulse interval of a neuron circuit. The UJT (unijunction transistor) is a positive feedback type device, so that the neuron circuit is formed with an SOI (i.e Si-on-insulator) structure, and each device should electrically insulated so as not to latch up the circuit. Figs. 5(A) and 5(B) show one embodiment of the circuit of the present invention, in which a terminal 9 is kept at a source voltage of +V 0 and a terminal 10 is kept at a source voltage of -V 0 , between which an excitatory photoconductor PC1 and an inhibitory photoconductor PC2 are connected in series, an adaptive-learning type FET is connected to its middle point, a capacitance C is connected between the adaptive-learning type FET and the terminal 9, unijunction transistor UJT is connected to its middle point 12, a light emitting diode LED is connected to said capacitance in parallel between the terminal 9 and the unijunction transistor UJT, and a resistance R is connected between the unijunction transistor UJT and an earth terminal 13. Optical information input signals hν 1 and hν 2 are incident into said excitatory photoconductor PC1 and inhibitory photoconductor PC2, and an optical information output signal hν is output from LED. Fig. 5(B) is substitute of electric elements for the photoconductors PC1 and PC2 shown in Fig. 5(A). In Fig. 5(B), terminals 14 and 15 are kept at voltages (+V 0 ) and (-V 0 ), respectively, switches 18 and 19 consisting of usual MOSFET are connected to said terminals 14 and 15 for switching between source-drain electrodes by a control voltage applied to gates of terminals 16 and 17, an adaptive-learning type MISFET 41 shown in Fig. 1 is connected to a middle point 20 of the FET switches 18 and 19, a capacitance C is connected between a terminal 14 and a terminal 21, a unijunction transistor (UJT) 42 is connected to the terminal 21, a resistance 26 is connected between terminals 14 and 22, R is connected between the unijunction transistor (UJT) 42 and an earth terminal 23, a p channel MOSFET 40 is connected to a middle point 27 of the terminal 22 and an output terminal 24 and an output terminal 25 divided by resistances 28 and 29 is connected to a drain terminal of the MOSFET 40. The other end of the resistance 29 is connected to the terminal 15. In this neural network, an excitatory information input voltage pulse is applied to the terminal 16, an inhibitory information input voltage pulse is applied to the terminal 17, an excitatory information output voltage pulse is output from the terminal 24, and an inhibitory information output voltage pulse is output from the terminal 25. Fig. 6 shows n row of neuron arrays having m stage excitatory optical input terminals and m stage inhibitory optical input terminals, an excitatory optical information input signal is input into photo-conductors of PC1-1, PC1-2, ... PC1-m, an inhibitory optical information input signal is input into photo-conductors of PC2-1, ... PC2-m, a photoconductor PC1-1, n row of the gate electrodes of adaptive-learning type FETs (F1-1, F1-2, ... , F1-n) and a photoconductor PC2-1 are connected in series, other sets PC 1-m , F m-1 , F m-2 , ... , F m-n , PC 2-m are also connected between source terminals 30 and 31, and further connected neuron circuits N 1 , ... Nn enclosed with a broken line in Fig. 5(A). This circuit can take outputs simultaneously from n row of neurons having m stage synaptic connections and its information is taken out of a terminal 34 as an optical output. Fig. 7 shows a circuit of a synaptic layout consisting of such adaptive-learning type FET. Fig. 8 shows the construction of a neuron array circuit substituting the above photoconductors PC1-1, PC1-2, ... PC1-m and PC2-1, ... , PC2-m for FET switches 45-1, 45-2, ... , 45-m and 46-1, ... , 46-m, respectively. Fig. 7(A) and Fig. 7(B) is a sectional view and a plan view of the circuit arrangement. Fig. 7(B) shows such a construction that n-p-n or p-n-p Si stripes 36 and 37 are provided on an insulator substrate 35, a ferroelectric film 38 is coated thereon, and a gate electrode 39 is further coated thereon, so as to make the Si stripes 36, 37 and gate electrode 39 a chess board cross viewed from the above. An adaptive-learning type neural circuit of the present invention was manufactured and a test was conducted for an effect thereof as follows. (1) Object of the test:- In prior neural networks, it is most preferable to change a weighting function of synaptic connection in neuron circuit through an adaptive-learning process. In the present test, the work "adaptive-learning" can be defined as a function for changing a part or the whole of electric or optical properties of a device after the device processes a number of signals. In order to attain an object of the present invention, there is required an adaptive-learning neuron circuit having excitatory control means and inhibitory control means. The adaptive-learning device function returns to the initial value by applying an initializing signal, so that this function is different from the deterioration of the device. (2) Adaptive-learning type MISFET (metal/insulator/semi-conductor junction electric field effect type transistor) The fundamental device for carrying out the adaptive-learning function is MISFET having a ferro-electric gate insulator thin film as shown in Fig. 1. In the self-control device, a pulse having a larger voltage than that of a usual signal pulse is applied to a gate electrode because the pulse having the larger voltage changes properties of a thin film. On the other hand, in the adaptive-learning MISFET, a thickness of the ferroelectric thin film is suitably selected for gradually changing a polarity of the thin film by applying a pulse signal. As a result, the normally OFF type FET where a current does not flow at a gate voltage of zero at first changes to a normally ON type FET where a current flows at a gate voltage of zero. The device structure can easily be designed by using switch properties of a ferroelectric thin film. An embodiment of this design is as shown in Fig. 3, and in Fig. 3, "learning times" means pulse number until the Si surface of a MIS diode changes to the inversion condition. (3) Neuron circuit The function of the adaptive-learning type MISFET gradually changes resistance between source-drain or threshold voltage when input pulse signals are applied to the gate, so that it is compatible with an analog circuit. On the other hand, it is necessary to apply a digital pulse signal to the input of the adaptive-learning type FET. In order to connect two concepts ions of the analog output and the pulse input, a system for generating an asynchronous short interval pulse was proposed, which is similar to a current pulse generation system in human brains. This system is called PFM (pulse frequency modulation), and an interval for generating pulses has no periodicity, so that this system is different from a synchronous pulse density neural system which pulse generating time is determined. Fig. 4 shows a fundamental circuit of a pulse generator which is known as the trigger circuit of thyristor. In Fig. 4, UJT is a unijunction transistor used as a switch for discharging a capacitance C, R 1 , R 2 and R 3 are resistances, 7 is an output terminal, and 8 is a bias voltage terminal for charging C through R 1 . A pulse interval is determined by a time constant of CR 1 . When this resistance R 1 is substituted for source-drain resistances of adaptive-learning type MIS-FET-1 and MIS-FET-2, an interval of output pulses of the neuron circuit can be changed. UJT is a positive feedback type device, so that a neuron circuit is formed with an SOI (Si-on-insulator) structure, and each device should electrically be insulated so as not to latch up (i.e parasitic thyristor action) in the circuit. In order to change the output pulse interval for both long and short, a gate input signal having positive and negative polarities is necessary. A circuit proposed by the present invention is as shown in Figs. 5(A) and 5(B). In Figs. 5(A) and 5(B), there is used optical electrical coupling between neuron circuits. Lastly, a circuit according to the present invention a multiple input neuron circuit and a synaptically connected layout is shown in Figs. 6 and 7. Fig. 6 shows n row neuron arrays having optical coupling. In Fig. 6, each neuron circuit has m stage synaptic connections, which are receivers of signals from respective preceding stages. In this array, adaptive-learning FETs of each neuron circuit are connected in parallel for determining an output pulse interval by a time constant of (capacitance C) × (total resistance R). Fig. 7 shows a synaptic connection layout. In Fig. 7, an Si stripe having a n-p-n structure in a lateral direction is arranged on an insulator substrate, and coated a ferroelectric thin film thereon, while a metal stripe for a gate electrode is arranged on the thin film at a right angle to the Si stripe. In order to weight respective initial synaptic connections separately, a +V 0 /2 pulse-like bias voltage and a -V 0 /2 direct current bias are applied to respectively selected metal and Si stripes. As a result, a potential difference applied to the thin film becomes V 0 at only the intersection point and exceeds a critical value of polarization, and the degree of polarization, that is, the degree of weight can be controlled by varying a duration of the pulse-like bias. Moreover, when a weighting value is 0, it means that there is no response to input, and it also means the more the weighting value increases, the more the portion thereof is regarded as important. Since the synapse circuit has no through-hole as shown in Fig. 7, a packing density of the synapse circuit is expected to be very high. Definitely speaking, one synapse region in case of designing a circuit with a rule of the minimum width of 1 micron is about 4 × 2 µm 2 (3 µm-width Si stripes, 1 µm-width metal stripes and 1 µm-width space). The region of each neuron circuit is not large, and the region of 1000x1000 synapse connections having 1,000,000 synapses is about 8 mm 2 . This region is considered to be sufficiently small as compared with the other neural network. (4) Conclusion The adaptivelearning neuron circuit of the present invention is as follows: (1) Adaptive-learning type MISFET circuit having a ferroelectric gate insulator. (2) Asynchronous PFM output circuit. (3) Excitatory synapse and inhibitory synapse. (4) High density synapse layout. (5) Separate determination of initial weighting of synapse. (6) Optical and electrical connection between neurons. According to a neuron circuit of the present invention connected in a synapse array, there is such an industrially great effect that an adaptive-learning type neuron circuit can be manufactured, in which an interval of output pulses is changed by learning by connecting a simple pulse generating circuit consisting of capacitance, resistance, unijunction transistor and the like for instance. Although the invention has been described with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example and that numerous changes in details may be resorted to without departing from the scope of the invention as hereinafter claimed.

Claims: An adaptive-learning type product-sum operation neuron circuit wherein said neuron circuit is implemented by means of an adaptive-learning type Metal-Insulator-Semiconductor-Field-Effect-Transistor MISFET, each neuron circuit comprising an insulator substrate (35); at least one single crystal semiconductor stripe (36, 37) on the insulator substrate (35), said at least one single crystal semiconductor stripe extending in a first direction; a ferroelectric film (38) deposited on the insulator substrate (38) for covering the at least one single crystal semiconductor stripe (36, 37); and a stripe-like gate electrode (39), formed on the ferroelectric film (38), said gate electrode (39) extending in a second direction ; wherein said at least one single crystal semiconductor stripe (36, 37) includes first second and third semiconductor sections (n-p-n or p-n-p); wherein the first and third sections are of a same conductivity-type and the second section is of a conductivity-type which is the opposite of the conductivity-type of the first and third sections and wherein the first, second and third semiconductor sections are arranged along the second direction with the second section disposed between the first and third sections; wherein each neuron circuit further comprises excitatory pulse control means for narrowing a pulse interval of output pulses of a circuit conducted by excitatory input signals and inhibitory pulse control means for widening a pulse interval of output pulses of a circuit conducted by inhibitory input signals, wherein the plurality of electrode stripes are electrodes for receiving excitatory pulses from said excitatory pulse circuits and for receiving inhibitory pulses from said inhibitory pulse circuits, and wherein the ferroelectric film (38) is responsive to said excitatory pulses for increasing its residual polarization by a first predetermined amount and is responsive to said inhibitory pulses for decreasing its residual polarization by a second predetermined amount, and said adaptive-learning type product sum operation circuit being characterized in that said gate electrode, intersects the at least one single crystal semiconductor stripe (36, 37) and in that each neuron circuit achieves an adaptive-learning function such as compensation of a displacement or missing letter or pattern of an input electric information signal. The adaptive-learning type product-sum operation neuron circuit according to claim 1, wherein said first and third semiconductor sections are n-type semiconductors and the second semiconductor is a p-type semiconductor. The adaptive-learning-type product-sum operation neuron circuit according to claim 1, wherein the first and third semiconductor sections are p-type semiconductors and the second semiconductor section is a n-type semiconductor. The adaptive-learning type product-sum operation neuron circuit according to claim 1, wherein each neuron circuit achieving an adaptive-learning function by means of a parallel circuit of adaptive-learning type MISFET-S (41) connected to a capacitance (C) in series, and to resistances (R 2 and R 3 ) being placed at the other side of a bridge and connected by a unijunction transistor UJT (42), and a junction point of said MISFET-S and said capacitance C being connected to said unifunction transistor (42) for narrowing an interval between output pulses by means of a positive excitatory control signal entered into a first MISFET (MISFET-1) and widening an interval between output pulses by means of a negative inhibitory control signal entered into a second MISFET (MISFET-2). An adaptive-learning type product-sum operation neuron circuit according to claim 1, wherein a first photoconductor (PC1) is conducted by an excitatory optical information input signal and a second photoconductor (PC2) is conducted by an inhibitory optical information input signal are connected in series between positive and negative terminals (9, 10), a series circuit of a capacitance C and an adaptive-learning type FET SL-FET are connected between said positive terminal (9) and an earth terminal (13), and a series circuit of a LED, a unijunction transistor UJT and a resistance (R) is connected in parallel to said series circuit of capacitance and adaptive-learning type FET SL-FET, a junction point (11) of said photoconductor (PC1, PC2) is connected to a gate electrode of said adaptive-learning type FET SL-FET, an intersecting point (12) of the adaptive-learning type FET SL-FET and the capacitance (C) is connected to said unijunction transistor UJT, wherein the circuit comprises excitatory control means for narrowing a pulse interval of output pulses corresponding to optical information input signals incident to said first photoconductor (PC1), and inhibitory control means for widening a pulse interval of output pulses corresponding to optical signals incident to said second photoconductor (PC2). An adaptive-learning type product-sum operation neuron circuit according to claim 1, wherein each neuron circuit is provided with a series circuit of a p-channel MOSFET switch (18) conducted by an excitatory information input signal and an n-channel MOSFET switch (19) conducted by an inhibitory information input signal, a series circuit of a capacitance (C)and an adaptive-learning type MISFET (41), a series circuit of a resistance (26), a unijunction transistor UJT (42) and a resistance (R), a series circuit of a p-channel MOSFET (40) and resistance (28, 29), these series being connected in parallel, respectively, a junction point (20) of said FET switches (18, 19) is connected to a gate electrode of said adaptive-learning type FET (41), a junction point (21) of said adaptive-learning type FET (41) and capacitance (C) is connected to said UJT (42), a junction point (27) of said UJT (42) and said resistance (26) is branched from an excitatory information output terminal (24) and connected to a gate electrode of said p-channel MOSFET (40), an inhibitory information output terminal (25) is provided between the resistance (28, 29), wherein the circuit further comprises excitatory control means for narrowing a pulse interval of an output pulse voltage and inhibitory control means for widening a pulse interval of an output pulse voltage of said neuron circuit. An adaptive-learning type product-sum operation neuron circuit according to claim 1, wherein an array network of neuron circuits (N 1 , N 2 ,... N n ) of m x n dimensions is achieved by providing m stages of a series circuit of a photoconductor (PC 1-1, PC 1-2 , ... PC 1-m ) conducted by an excitatory optical information input signal, n neuron circuits (N 1 , N 2 ,... N n ) placed in n rows and a photoconductor (F 1-1 , F 1-2 , ... F 1-m ) conducted by an inhibitory optical information input signal, said array being connected between positive and negative terminals (30,31); said array being further provided with excitatory control means for narrowing an interval of output pulses of each neuron circuit by excitatory control signals and with inhibitory control means for widening an interval of output pulses of each neuron circuit by inhibitory control signals, wherein said neuron circuit further achieves an adaptive-learning functions such as compensating a displacement or missing letter and a pattern of input picture information. An adaptive-learning type product-sum operation neuron circuit according to claim 1, wherein an array network of neuron circuits (N 1 , N 2 ,... N n ) of m x n dimensions is achieved by providing m stages of a series circuit of a semiconductor switch (45-1, 45-2, 45-m) conducted by an excitatory electric input signal, n rows of neuron circuits (N 1 , N 2 ,... N n ) and a semiconductor switch (45-1,45-2, ... 45-m) conducted by an excitatory electric input signal, n rows of neuron circuits (N 1 , N 2 , ... N n ) and a semiconductor switch (46-1, 46-2, ... 46-m) conducted by an inhibitory electric information input signal between positive and negative terminals (30, 31), wherein said neuron circuit further comprises excitatory control means for widening an interval of output pulses of each neuron circuit by inhibitory control signals and inhibitory control means for narrowing an interval of output pulses of each circuit by excitatory control signals and said circuit further comprises adaptive-learning functions such as compensation of a displacement or missing letter or pattern of an input electric information signal.

Inventors: ISHIHARA HIROSHI, ISHIHARA, HIROSHI
Applicants: TOKYO INST TECH, TOKYO INSTITUTE OF TECHNOLOGY
Application year: 1993
Main classification: G06F15
IPC codes: G06F15, G06N3, G06G7, G06N99