Method for contacting a semiconductor device

Abstract: An electrical contact (46) to a phosphorous doped polysilicon gate electrode (18) is formed by preventing arsenic, from a source and drain implant, from doping a portion (22) of the polysilicon gate electrode (18). A photoresist mask (20) covers a portion (22) of the polysilicon gate electrode (18) during the implant, thus preventing it from being doped. An electrical contact (46) is then formed to the masked portion (22) of the polysilicon gate electrode (18).

Description: Field of the Invention This invention relates generally to semiconductor devices, and more specifically to a method for contacting a semiconductor device. Background of the Invention The semiconductor industry is continually reducing device dimensions in order to meet performance and packing density requirements. As device dimensions are decreased, however, contact geometries are also reduced and this results in an increase in parasitic contact resistance. For devices with submicron geometries, this increase in parasitic contact resistance is substantial and it degrades device performance. Several techniques have been proposed for forming electrical contacts with low contact resistance. A silicided electrical contact approach is one of the most promising techniques for reducing contact resistance. In this process, a metal silicide layer is placed between the contact surface and the overlying metallization to form an ohmic or low resistance electrical contact to the underlying contact surface. The formation of silicided electrical contacts to doped polysilicon surfaces, however, has proved to be a reliability issue. In particular, silicided electrical contacts often delaminate from doped polysilicon surfaces. If this delamination occurs an open circuit is formed and the device becomes non-functional. Accordingly, a need exists for a process that forms electrical contacts to doped polysilicon surfaces. An article entitled "A new self-aligning contact process for MOS LSI" by S. Muramoto et al., Intern. Electron Devices Meeting, Technical Digest, 4 December 1978, Washington, pages 185-188 describes a method for forming a self-aligned contact wherein arsenic doped polysilicon is deposited over a semiconductor substrate and then a silicon nitride layer is deposited on top of the arsenic doped polysilicon layer. A portion of the silicon nitride layer is then etched to expose a portion of the arsenic doped polysilicon layer. Half the thickness of the exposed arsenic doped polysilicon layer is then etched and ions are then implanted through the etched arsenic doped polysilicon layer to form source/drain regions. The silicon nitride layer is then etched again to leave portions of it remaining only over contact hole areas. The exposed portions of the arsenic doped polysilicon layer are then selectively oxidized to form an isolation oxide. The remaining portions of the silicon nitride layer are then removed from the contact hole areas. Summary of the Invention In accordance with the present invention there is provided a method of contacting a semiconductor device as recited in the accompanying claims. These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of the present invention that are not specifically illustrated. Brief Description of the Drawings FIGs. 1-7 illustrate, in cross-section, process steps in accordance with one embodiment of the invention. Detailed Description of a Preferred Embodiment FIGS. 1 through 7 illustrate, in cross-section, process steps in accordance with one embodiment of the invention wherein a contact to a semiconductor device is formed. Shown in FIG. 1 is a portion 10 of an integrated circuit structure comprising a silicon substrate 12, a field isolation region 14, an active region 15, a gate dielectric layer 16, and a patterned polysilicon member 18. Field isolation region 14 is formed within a portion of silicon substrate 12 and defines active region 15. Field isolation region 14 is preferably formed using a conventional LOCOS isolation process. Following the formation of field isolation region 14, gate dielectric layer 16 is formed. A polysilicon film is then deposited and doped using conventional diffusion or implantation processes. The doped polysilicon film is then patterned, using conventional photolithographic patterning and etching techniques, to form polysilicon member 18. Polysilicon member 18 may serve as the control electrode for multiple transistors or for just a single transistor. Gate dielectric layer 16 is preferably a thermally grown silicon dioxide layer and polysilicon member 18 is preferably doped with phosphorous. Alternatively, polysilicon member 18 may be doped with arsenic. A cross section of FIG. 1 taken along the line 2-2 is shown in FIG. 2. As shown in FIG. 3, a photoresist mask 20 is then formed using conventional photolithographic patterning techniques. Photoresist mask 20 overlies a first portion 22 of polysilicon member 18, while at the same time leaving a second portion 24 of polysilicon member 18 exposed. As shown in FIG. 3, first portion 22 of polysilicon member 18 overlies a portion of field isolation region 14 that is adjacent to active region 15. The significance of partially masking polysilicon member 18 will be made clear later. Using conventional implantation techniques, a dopant 26 is implanted into second portion 24, while at the same time photoresist mask 20 substantially prevents dopant 26 from being implanted into first portion 22. Thus the doping concentration in second portion 24 is increased while the doping concentration in first portion 22 remains substantially unchanged. Shown in FIG. 4 is a cross sectional view of FIG. 3 taken along the line 4-4. As shown in FIG. 4, the implantation process is used to form a source region 28 and a drain region 30 within active region 15. Thus, polysilicon member 18 was only partially masked in order to allow source region 28 and drain region 30 to be formed. Source region 28 and drain region 30 are preferably formed with an arsenic implant. Alternatively, source region 28 and drain region 30 may be formed with a phosphorous implant. After implantation, photoresist mask 20 is removed using conventional photoresist stripping techniques. In FIG. 5, the process continues with the deposition of a dielectric layer 32 overlying polysilicon member 18. Using standard photolithographic patterning and etching techniques an opening 34 is formed in dielectric layer 32, and a contact portion 36 of first portion 22 is exposed. As shown in FIG. 6, the process continues with the formation of a silicide layer 38 and a barrier layer 40, which are electrically coupled to contact portion 36. In the preferred embodiment, silicide layer 38 is titanium silicide. Alternatively, silicide layer 38 may be cobalt silicide, platinum silicide, or nickel silicide. Barrier layer 40 is preferably titanium nitride. Alternatively, barrier layer 40 may be tungsten, titanium/tungsten or a different metal nitride layer. In the preferred embodiment a deposited film of titanium is rapid thermally annealed, in a nitrogen ambient, such that a composite layer of titanium silicide and titanium nitride is formed overlying contact portion 36. Other conventional processing techniques, however, may be used to form silicide layer 38 and barrier layer 40. In FIG. 7, the process continues with the deposition of a layer of conductive material. In the preferred embodiment the layer of conductive material comprises aluminum. Alternatively, the layer of conductive material may also be tungsten or copper. Using conventional photolithographic patterning and etching processes a portion 42 of the layer of conductive material and a portion 44 of barrier layer 40 are then patterned. This results in the formation of an electrical contact 46 to contact portion 36, which is composed of silicide layer 38, portion 44, and portion 42, as shown in FIG. 7. Portion 42 is electrically coupled to portion 44 and silicide layer 38. Electrical contact 46, however, may also be formed using other conventional processing techniques. For example, after silicide layer 38 and barrier layer 40 have been formed, and before the layer of conductive material has been deposited and subsequently patterned, the contact opening may be filled with a tungsten plug. The foregoing description and illustrations contained herein demonstrate many of the advantages associated with the present invention. In particular partially masking a polysilicon member during a source and drain implantation process allows an electrical contact to be formed to an underlying doped polysilicon surface. Moreover, the electrical contact to the doped polysilicon surface can be obtained without adversely effecting the source and drain fabrication process. Yet another advantage is that the present invention does not require an additional masking step. Existing source and drain implant masks may be modified to additionally mask that portion of the polysilicon member to which electrical contact is to be formed. Thus it is apparent that there has been provided, in accordance with the invention, a method for contacting a semiconductor device that fully meets the need and advantages set forth previously. Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. For example, it is envisioned that electrical contacts to boron doped polysilicon may also be formed in a similar manner. It is also important to note that the present invention is not limited in any way to a particular source or drain structure. For example, a lightly doped source and drain structure may also be formed with this invention. Furthermore, other substrates such as silicon on insulator or silicon on sapphire could also be used. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.

Claims: A method of contacting a semiconductor device comprising the steps of: providing a substrate (12); forming a field isolation region (14) within a portion of the substrate (12) wherein the field isolation region (14) defines an active region (15); forming a doped polysilicon member (18) overlying the substrate (12); forming a mask (20) overlying a first portion (22) of the polysilicon member (18) and exposing a second portion (24) of the polysilicon member (18), wherein the first portion (22) of the polysilicon member (18) overlies a portion of the field isolation region (14) adjacent to the active region (15); implanting a dopant (26) to form a source region (28) and a drain region (30) within the active region (15) wherein the dopant (26) is implanted into the second portion (24) of the polysilicon member (18) and the mask (20) substantially prevents the dopant (26) from being implanted into the first portion (22) of the polysilicon member (18); removing the mask (20); forming a dielectric layer (32) overlying the first portion of the polysilicon member (18) after the mask has been removed and overlying the second portion of the polysilicon member; forming an opening (34) in the dielectric layer (32) to expose a contact portion (36) of the first portion (22) of the polysilicon member (18); and forming an electrical contact (46) to the contact portion (36). The method of claim 1 wherein the step of forming the electrical contact (46) comprises: forming the electrical contact from at least one material selected from the group consisting of titanium silicide, cobalt silicide, titanium nitride, tungsten, and aluminum. The method of claim 1 wherein the step of forming a doped polysilicon member (18) comprises: forming the doped polysilicon member from a material selected from the group consisting of phosphorous doped polysilicon and arsenic doped polysilicon. The method of claim 1 wherein the step of implanting the dopant (26) comprises: implanting a material selected from the group consisting of arsenic and phosphorous. The method of claim 1, 2, 3 or 4 wherein the step of forming the doped polysilicon member (18) is further characterized as forming a doped polysilicon member that serves as a control electrode for only a single transistor. The method of claim 5 wherein the step of forming the electrical contact (46) comprises the step of: forming a layer of titanium silicide (38) overlying and electrically coupled to the contact portion(36). The method of claim 6 wherein the step of forming the doped polysilicon member (18) is further characterized as forming a phosphorous doped polysilicon member. The method of claim 7 wherein the step of implanting the dopant (26) is further characterized as implanting arsenic. The method of claim 6, 7, or 8 wherein the step of forming the electrical contact (46) further comprises the step of: forming a patterned layer of conductive material (44, 42), the patterned layer of conductive material being electrically coupled to the layer of titanium silicide (38). The method of any preceding claim 1 wherein the step of forming the mask is further characterized as forming a photoresist mask (20).

Inventors: BARKER JEFFREY M, CHERNIAWSKI MICHAEL, KAUSHIK VIDYA S, PYLE RONALD E, BARKER, JEFFREY M., CHERNIAWSKI, MICHAEL, KAUSHIK, VIDYA S., PYLE, RONALD E.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L23