ESD protection of output buffers

Abstract: A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors (e.g., 201, 202) are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, a capacitor (e.g., 205) couples a bond pad (e.g., 200) to the gate of a protective transistor (e.g., 203, 204) that applies a turn-on voltage to the gate of an n-channel output transistor. In this manner, the output transistor itself is used to conduct the ESD current to a power supply conductor (e.g., V DD , V SS ). In one embodiment, to assist in the turn-on of the n-channel output transistor, a transistor (e.g., 208) couples the bond pad to the n-tub (e.g., 213) in which the p-channel pre-driver transistor (e.g., 210) is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique. This technique is especially valuable for SCSI (Small Computer System Interface) chips, since only n-channel output transistors are used. It may also be used in TTL-output buffers, which also use n-channel pull-up and pull-down devices. P-channel output devices may be comparably protected.

Description: This invention relates to integrated circuits. The protection of integrated circuits from electrostatic discharge has been a significant design issue, especially as transistor electrode dimensions shrink below the 1.5 micron level. An excessively high ESD voltage conducted from a package terminal to the integrated circuit bondpad can easily damage input or output circuitry, unless protection techniques are adopted. It appears that the use of the lightly-doped drain (LDD) structure and silicided source/drain regions has increased ESD susceptibility, especially in output buffers that utilize n-channel field effect transistors. One recent study by C. Duvvury and C. Diaz, "Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection" Proceedings of the IRPS (1992), indicates that improved ESD performance can be obtained using a field oxide capacitor to couple the gate of the output transistor to the bondpad; see Figure 6 therein. In that technique, the output transistor is made to carry the ESD current. However, the field oxide capacitor undesirably increases the capacitive load on the bondpad, requiring a larger output transistor. A somewhat similar prior-art technique is shown in Fig. 1, wherein an output buffer 10 is connected to the bondpad 11. A protective n-channel transistor 13 is connected to the bondpad for conducting ESD current (I) to the power supply conductor (V SS ). The ESD voltage is conducted to the gate of transistor 13 by capacitor 12, typically about 10 picofarads in one design. This conduction tends to allow transistor 13 to conduct by means of bipolar break-down action during an ESD event, allowing the current I to flow. The resistor 14, typically about 2 kilohms, causes the positive charge on the gate of transistor 13 to be conducted to V SS , thereby turning transistor 13 off after the ESD event has dissipated. In this manner, transistor 13 does not conduct during normal operation of the output buffer. However, the circuitry of Fig. 1 requires that the protective transistor be sufficiently large so as to be able to carry the relatively large ESD current. This requirement increases the area required to implement the output buffer. In addition, the transistor 13 presents an additional capacitive load to the buffer 10, which again undesirably requires that the buffer have additional drive capability, and hence increased size. In some cases, protection against positive ESD voltages is improved by the presence of a p-channel output transistor. In that case, the p-n junction of the drain electrode, which is connected to the bondpad, provides for clamping positive ESD voltages to a power supply conductor. However, some designs use only n-channel output transistors. For example, TTL output buffers typically use n-channel transistors for both the pull-up and pull-down devices. More recently, the Standard Computer Systems Interface (SCSI) chips have output buffers that typically use only n-channel transistors. It is therefore desirable to have an improved ESD protection technique that is effective with output buffers, and which mitigates certain problems associated with the prior-art techniques. US-A-4 855 620 discloses a high threshold transistor having its source-to-drain path connected between the gate of a drive transistor and a reference supply node. According to this invention there is provided an integrated circuit as claimed in claim 1. In a technique for protecting output transistors an additional device coupled to the bondpad causes an output transistor to conduct during an ESD event. In an illustrative case, an n-channel output transistor has its gate coupled to the output bondpad through an additional transistor having its gate coupled to the bondpad by means of a capacitor. This arrangement allows the output transistor to turn on during an ESD event, thereby conducting the ESD current to a power supply conductor. Both pull-up and pull-down output transistors may be protected in this manner. In one embodiment of the invention, the doped semiconductor region (e.g., n-tub) in which a pre-driver transistor (e.g., p-channel) is formed is also coupled to the bondpad so as to be raised in voltage when an ESD event occurs. Brief Description of the Drawings Fig. 1 shows a prior-art output protection technique. Fig. 2 shows an illustrative embodiment of the present invention. Fig. 3 shows an illustrative resistor used in one embodiment of the invention. Detailed Description The present detailed description relates to an improved integrated circuit electrostatic discharge protection technique. It may advantageously be used with output buffers having pull-up and pull-down transistors of a single conductivity type. In the illustrative case, n-channel output devices are shown. A comparable protective circuit for use with p-channel output devices is the same as that shown, except that p-channel transistors are used in lieu of n-channel transistors, and the power supply connections are the opposite of those shown. Referring to the illustrative embodiment of Fig. 2, an output conductor (bond pad 200) is connected to n-channel pull-up transistor 201 and n-channel pull-down transistor 202. In a first aspect of the invention, the gates of transistors 201 and 202 are connected to protective transistors 203 and 204, which are also connected to bond pad 200 as shown. Furthermore, the gates of protective transistors 203 and 204 are connected to capacitor 205 and resistor 206 at common node 207. During a positive-voltage ESD event, the high voltage is conducted through capacitor 205 to the gates of transistors 203 and 204. This conduction increases the voltage on the gates of these transistors to approximately the same voltage as on their sources/drain regions also connected to bond pad 200. This reduces the breakdown voltage across transistors 203 and 204, allowing them to conduct by means of bipolar action at a relatively low voltage. (As is well known in the art, each MOS transistor may be considered to have a bipolar transistor connected in parallel, comprising emitter, base, and collector regions corresponding to the source, channel, and drain regions of the MOS device.) This conduction through protective transistors 203 and 204 also raises the voltage on the gates of output transistors 201 and 202, respectively. This conduction also lowers the breakdown thresholds of these output transistors, allowing bipolar conduction through these transistors to conduct the ESD current to their respective power supply conductors, V DD and V SS . After a certain period of time following the onset of an ESD event, conduction of current through resistor 206 to the V SS conductor lowers the voltage on node 207, and hence on the gates of protective transistors 203 and 204. The lower gate voltage raises the breakdown threshold of these transistors, and turns them off at some point. Therefore, the gates of output transistors 201 and 202 are no longer placed at a high voltage, and these transistors also cease to conduct by means of bipolar breakdown action at some point. However, in normal circuit operation, the node 207 is held low through resistor 206, and so conduction through the protective transistors 203 and 204 does not occur. Therefore, normal circuit operation is not impaired. I recommend that capacitor 205 have a value in the range of from 0.2 to 50 picofarads, and resistor 206 have a value in the range of from 200 ohms to 50 kilohms. Further, I recommend that the RC time constant provided by these devices be preferably in the range of from 1 to 50 nanoseconds. In an illustrative embodiment, capacitor 205 has a nominal value of 3.3 picofarads, whereas resistor 206 has a nominal value of 3 kilohms. These values provide a nominal RC time constant of about 10 nanoseconds. I recommend that the circuitry be designed so that conduction of the output transistors is obtained only for an ESD event that produces a voltage on the bond pad that rises more rapidly than 100 volts per nanosecond. In that manner, normal information signals do not cause conduction via the protective circuitry. The capacitor 205 is illustratively of the MOS type, wherein a conductive polysilicon layer forms a first capacitor plate, and a doped semiconductor substrate (or tub) region forms the second capacitor plate, with a gate-level silicon dioxide layer forming the capacitor dielectric. Alternatively, the capacitor may comprise two polysilicon layers for the plates, with a deposited dielectric therebetween. Still other capacitor types are known in the art and may be used. Illustratively, resistor 206 is formed in an n-tub in a manner comparable to resistor 209 discussed below. However, it may alternatively be formed in a p-tub, or may be a deposited resistor of the polysilicon or silicide type, or may be of another type known in the art. In the exemplary embodiment of the inventive technique, means are also provided for boosting the voltage on the n-tub region in which the p-channel pre-driver transistor is formed during an ESD event. This boosting prevents conduction from the drain of the p-channel pre-driver to the underlying n-tub from limiting the voltage on the gate of the associated output transistor during an ESD event. That is, as shown in Fig. 2, the p-type drain of the pre-driver transistor 210 forms a diode 212 with the underlying n-type tub region 213 in which the drain is formed. In prior-art CMOS integrated circuit designs, the tub 213 would be connected directly to the V DD conductor. Therefore, conduction through the diode 212 would limit the positive voltage on the gate of output transistor 202 to no more than one junction voltage drop above the voltage on the V DD conductor during an ESD event. This clamping effect of diode 212 would therefore place an undesirable limitation on the effectiveness of the above-described action of protective transistor 204. Therefore, in the illustrative embodiment of the invention, a transistor 208 is connected between the bond pad 200 and the n- tub 213. This transistor 208 also exhibits bipolar breakdown when an ESD event occurs, thereby conducting charge to the n-tub 213 and raising its voltage. To allow the voltage on the n-tub 213 to rise, the n-tub is not connected directly to the V DD conductor, but rather through resistor 209. This resistor limits the conduction through diode 212 to the V DD conductor, and hence allows the voltage on the gate of output transistor 202 to rise to a higher level during an ESD event. The resistor 209 has a value of about 600 ohms in the exemplary embodiment, and is typically in the range of about 50 to 5000 ohms. The resistor may be a deposited (e.g., polysilicon) resistor, or a diffused region in the semiconductor substrate, or other type. For example, as shown in Fig. 3, an n-tub 31 may be used to form the resistor 209, which is connected to V DD via n+ contact region 37. The resistor is connected via n+ contact region 36, conductor 39, and n+ contact region 35 to the n-tub 30, corresponding to region 213 in Fig. 2. The p-channel pre-driver transistor (210 of Fig. 2), comprising source/drain regions 32 and 34, and gate electrode 33, is formed in n-tub 30. The p-channel transistor in the pre-driver complementary inverter 214 may be located in an n-tub similarly connected to V DD , or alternatively in the same n-tub as transistor 210. Note however that the use of tub-boosting transistor 208 and resistor 209, although advantageous in the illustrative embodiment, are not necessary in all cases. That is, the pre-driver stage that produces the logic signal to the output transistor may be of a different design than that shown, and the diode 212 may not be present. For example, the pre-driver pull-up device may be an n-channel transistor, rather than a p-channel transistor; hence the source-to-substrate diode would be connected opposite to diode 212 shown, and would not cause clamping of positive voltages. Note that in contrast to the prior-art technique of Fig. 1, the protective transistors 203 and 204 do not carry the actual ESD current themselves. Hence, the transistors 203 and 204 may be sized to be relatively small, which saves space as compared to certain prior-art techniques. In the present technique, it is the output transistors 201 and 202 that carry the ESD current to one or both of the power supply conductors V SS and V DD . However, the output transistors are usually relatively large anyway, in order to provide sufficient drive capability. Hence, no size increase may be required to provide ESD protection in typical implementations of the present technique. Furthermore, since the protective transistors 203 and 204 are relatively small, they add minimal capacitive loading to the output circuitry, as compared to the prior-art technique. The above embodiment has shown a transistor (e.g., 203 and 204) and an RC network (capacitor 205 and resistor 206) as the protective means that causes the output transistors (201 and 202) to conduct during an ESD event in response to the high voltage on bond pad 200. Note that when the ESD voltage has ceased, the protective means no longer causes the output transistor to conduct, and they are returned to control by the logic signal from the pre-driver circuitry. Normally, ESD events occur when the integrated circuit is not connected in a circuit board or multi-chip module, and hence the logic signals are not present anyway. Conversely, when connected in a circuit board or module, the normal operating logic signals may be present, but the ESD events are less likely to occur. Although digital logic circuitry has been discussed herein, the protected circuitry may be analog. Therefore, the desired operational signal (V in ) may be generally referred to as an "information signal". As discussed above, the present technique may be used with an output buffer having only a single conductivity type of output transistor. However, it may alternatively be used with CMOS output buffers as well, wherein a p-channel transistor serves as the pull-up device and an n-channel transistor serves as the pull-down device. In that case, the n-channel pull-down device may still be protected by the circuitry shown in Fig. 2. If desired, the p-channel device may be protected with comparable circuitry, but with the transistor conductivities opposite to that shown, and also opposite power supply connections. In that case, a resistor comparable to 209 could then be connected between the p-tub in which the n-channel pre-driver transistor is formed and the V SS power supply conductor. The connection between the source/drain electrodes of the output transistors and the output conductor (e.g., bond pad) may include a resistor, as shown for example in U. S. patent 4,990,802 coassigned herewith.

Claims: An integrated circuit comprising an output transistor (201, 202) having a first controlled electrode connected to a power supply conductor (V DD , V SS ), a second controlled electrode connected to an output conductor (200), and a control electrode coupled to receive an information signal (V in ); wherein said integrated circuit further comprises a protective field effect transistor (203, 204) having a first source/drain electrode connected to said output conductor, a second source/drain electrode connected to the control electrode of said output transistor, and a gate electrode connected to a first terminal of a capacitor (205) which has a second terminal connected to said output conductor so as to cause said output transistor to conduct during an electrostatic discharge event on said output conductor; and a resistor (206) having a first terminal connected to the gate electrode of said protective transistor and a second terminal connected to a power supply conductor (V SS ) so that said protective transistor does not conduct in the absence of an electrostatic discharge event on said output conductor. An integrated circuit as claimed in claim I wherein said output transistor is an n-channel field effect transistor, said information signal is supplied by a pre-driver stage that comprises a p-channel pull-up transistor (210) that is located in an n-type tub region (213); and said integrated circuit comprises a field effect transistor (208) for increasing the voltage on said n-type tub region during an electrostatic discharge event and having a first source/drain region connected to said output conductor (200), and a second source/drain region connected to said tub (213). An integrated circuit as claimed in claim I wherein said output transistor is a p-channel field effect transistor, said information signal is supplied by a pre-driver stage that comprises an n-channel pull-up transistor that is located in an p-type tub region; and said integrated circuit comprises a field effect transistor for increasing the voltage on said p-type tub region during an electrostatic discharge event and having a first source/drain region connected to said output conductor, and a second source/drain region connected to said tub. An integrated circuit as claimed in claim 2 comprising a resistor (209) connected between said n-type tub and the positive power supply voltage conductor (V DD ). An integrated circuit as claimed in claim 1 wherein said protective field effect transistor provides for said output transistor to conduct when the electrostatic discharge event produces a voltage on said output conductor that rises more rapidly than 100 volts per nanosecond.

Inventors: PIANKA JUERGEN, PIANKA, JUERGEN
Applicants: AT & T CORP, AT&T CORP.
Application year: 1993
Main classification: H01L27
IPC codes: H01L27, H01L21