A method and apparatus for analog test signal usage in a digital environment

Abstract: In a method for testing an electronic circuitry arrangement, first a test signal of predetermined habitus is provided. Next, the arrangement is operated in a predetermined mode. Finally, a result signal of intended habitus is extracted from one or more specific signal outputs of said the arrangement for subsequent evaluation. In particular, an analog parent signal is modulated to a digital bit stream and subsequently the test signal is produced through analog filtering of the digital bit stream. More in particular, the extracting repeatedly discriminates an output wave result signal with successive threshold levels and subsequently realigns successive discrimination bit stream results for at respective instants generating a thermometer signal code.

Description: FIELD OF THE INVENTION The invention relates to a method as recited in the preamble of Claim 1. The invention also relates to an apparatus as recited in the preamble of Claim 4. The invention also relates to an electronic circuitry as recited in the preamble of claim 10. a The standard according to reference GB-A 2,195,185 (A) is broadly accepted and in consequence, various hardware and software facilities have been developed for facilitating the use thereof. However, reference (A) relates exclusively to the testing of digital circuitry. Testing analog circuitry, whether in isolation, or as part of mixed analog/digital circuitry is by contrast usually performed as functional testing, where the apparatus should execute a part of the intended standard functionality. The test signal is often generated by some sort of signal shaper, such as a sinusoid generator. Subsequently it is observed whether the circuit functionality appeared correct as detectable from some result signal. Such testing is relatively expensive and needs the generation of specific signals often produced by means of extremely versatile and expensive test machines. The inventors have recognized a need for allowing the usage of simplified and general purpose test machines while creatively using available digital techniques as far as possible. Accordingly, amongst other things, it is an object of the present invention to provide a method and apparatus for testing an electronic circuitry arrangement that allows straightforward application of analog test patterns that may lend themselves to easy generation and storage. In consequence, amongst other things, the invention is characterized by the characterizing parts of Claims 1 and 4. The invention also relates to an arrangement according to Claim 10, which therefore accommodates at least of a B uilt- I n S elf- T est functionality By itself, IEEE Journal of Solid-State Circuits, Vol. 26, 1991, no. 12, pages 1757-1762 (B) describes "A Bit-Stream Digital-to-Analog Converter with 18-b Resolution". However, (B) does not contemplate the environment of testing analog circuitry. Furthermore, Proceedings International Test Conference 1991, IEEE, paper 39.2, pages 1049-1054 (C) describes "A 20 Bit Waveform Source for a Mixed-Signal Automatic Test System", that is used for both ac and dc testing of analog to digital converters. In contradistinction, the present invention intends to test analog circuitry which is not restricted to having any particular functionality, through using digital signal streams as a vehicle for transfer, storage and the like, and to thereby allow the usage of digital test standards that have become commonplace throughout industry. SUMMARY OF THE INVENTION As stated above, amongst other things, it is an object of the present invention to provide a method for testing an electronic circuitry arrangement that allows straightforward application of analog test patterns that may lend themselves to easy generation and storage. Now, according to one of its aspects, the invention is defined in claim 1. Advantageously, said modulating is first or second order sigma delta modulation. This way modulating is extremely straightforward, although other techniques would be feasible as well. Advantageously, said extracting comprises a step of repeatedly discriminating an output wave result signal with successive threshold levels and subsequently realigning successive discrimination bit stream results for at respective instants generating a thermometer signal code. Again here, the analog interface part is extremely straightforward. The invention also relates to an apparatus for testing an electronic circuitry arrangement according to the preamble and comprising in particular modulating means for modulating a parent signal to a digital bit stream and filtering means fed by said modulating means for producing said test signal through analog filtering of said digital bit stream as defined in claim 4. This proves a straightforward realization. By itself, the testing may be a boundary scan test or a self-test mechanism. Both these methodologies have proven feasible. The invention also relates to an electronic circuitry arrangement as a target for executing the method supra, as defined in claim 10. Such an electric circuitry arrangement, comprising test signal source means for generating a test signal, test signal input means for receiving the test signal, operating means fed by said test signal input means for in a predetermined operating mode operating on said test signal to produce a result signal of predetermined shape, and result signal output means for outputting said result signal for subsequent evaluation is known from the art. Various advantageous aspects are recited in dependent Claims. BRIEF DESCRIPTION OF THE DRAWING These and other aspects and advantages of the invention will hereinafter be discussed in detail with respect to a preferred embodiment that in particular has been illustrated in and by the appended Figures that show: Figure 1 an archetypical tester machine set-up; Figure 2 a schematic of a test signal generation technique; Figure 3 a general sigma-delta modulation; Figures 4A, 4B first and second order sigma-delta modulation; Figure 5 a comparator circuit as used on a digital tester; Figure 6 a comparator circuit as used for A/D conversion. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Figure I shows an archetypical tester machine set-up, comprising a test signal generator 20, a device under test 22, and a result signal evaluator 24. The test signal generator produces a test signal, the device under test receives this signal and is subsequently controlled in a normal operating mode or other predetermined mode, and the result signal evaluator will from the result signal find out whether the device under test functions well. This qualification applies whether the test is by itself structural or functional. The result may indicate various qualifications, such as good, faulty, partially good, needs repair, but others are feasible as well, such as: operates correctly provided the clock frequency is less than XY MHz, or a particular qualification such as one indicating the signal to noise ratio. The device under test may be a single integrated circuit chip, a board with multiple chips, a wafer scale integrated circuit, or any other feasible package level. With respect to testing with digital signals, US 5 430 735 and US 5 657 329 provide ample detail, and in fact, the test procedure and also the test provisions on the circuitry under test may comply with the Boundary Scan Test Standard. Inter alia, this means serial data in pin, serial data out pin, test clock pin, and one or two extra pins for control signals. The invention uses analog test signals to be applied to the device under test proper, such as sinusoids, multitone signals, and arbitrary waves, including block waves. The environment as described may be used to operate the circuitry arrangement with digital test signals as well, but this is not a restriction. Now, the test signal source block 20 may have one or more test signal output terminals in parallel, it may internally contain a memory for storing test patterns, it may have multiplexing means for multiplexing various test signals on a single output terminal, it may output control bit trains according to the Boundary Scan Test Standard, and other functions. For brevity, these provisions have not been shown, however. Also the providing of clock signals, such by a master clock, has not been shown. Also the initiation and the termination of the test have not been shown for brevity. As to the dividing of the various tasks, a first possibility is that the analog signals are produced in part 28 of the test signal generator, as based on particular elements therein and on a stored digital bit pattern. A second possibility is that these analog test signals are produced in part 28 of the same package (board, chip, etc.) of the device under test. The latter option has been indicated in the drawing by an interrupted line 26 around device under test 22 that also encloses part 28. This means that only the digital representation of the analog test signal need be communicated from outside to the device under test. A further possibility is that substantially all of block 20 is contained in the same package, such as the integrated circuit chip, as the device under test itself. This would, as far as regards the applying of the test patterns, represent a self-test organization. The invention also uses analog result signals that are derived from the device under test proper. In principle, such analog signals may be evaluated directly, for example by therefrom extracting a particular analog quantity, such as amplitude or frequency, etcetera as applicable, or by comparison with a model analog signal. For brevity, this has not been discussed further. A further type of evaluation first converts the analog signal to a bit stream, before evaluating. A first possibility is that this conversion takes place in part 30 of the result signal evaluator, as based on particular elements therein. A second possibility is that this conversion takes place in the same package (board, chip, etc.) of the device under test. The latter option has been indicated by drawing an interrupted line 26 around device under test 22 that also encloses part 30. This means that only the digital representation of the analog result signal need be communicated from the device under test to outside. As a further possibility, also the evaluation could be inside the circuitry. This would, as far as regards the outputting of the result patterns, represent a self-test organization. In the exemplary embodiment, for governing the interaction between the three subsystems, block 20 has a control element 32 that operates as overall master. After transmission of the test signal has been completed, this element sends a control signal to control element 34 in block 22 for driving the latter in a normal state of operation, so that the test signal is effectively transformed into a result signal. Next, control element 32 activates a further control element 36 in block 24 that sets the latter to evaluating the result signal then received. The communication between the various control elements may be as required, and the assignment of the master functionality could be different. In a self-test scheme, all control may reside inside the circuitry under test. The whole test may be executed in a synchronous or asynchronous manner. Figure 2 is a schematic of a test signal generation technique. Inter alia, this relates to the use of digital functionality in an unconventional and versatile way for generating analog test signals. This results in a compact test environment with minimal or no external equipment. This technique is based on the observation that digital waveforms also embody analog signal content. They are adjusted to present desired signal characteristics, and are applied as an analog stimulus. One example of this is the generation of "noise" using digital data with desired statistical properties to detect significant device behaviour. Another candidate to achieve this is to modulate a desired analog signal onto a digital pulse train and to demodulate this signal at the output of a digital tester channel. A modulation scheme which allows subsequent easy demodulation is 1-bit Sigma-Delta Modulation (ΣΔ). An advantage of this scheme is its potential capability of achieving high performance test signals. This is because the process equals the conversion of a "perfect" test signal into a bitstream where the latter can be a high resolution representation of the first. Sigma-Delta modulation has been successfully applied for both A/D and D/A conversion. By itself, other modulation types are feasible as well as will be explained hereinafter. As shown in Figure 2, a software model of the modulation process (42) converts a test signal (40) into e.g. a repeating or nearly repeating digital data-stream (44). When loaded into the tester's pin memory (46), this can then be applied with the required speed to a tester pin in a continuously repeating sequence. Element 48 is a driver circuit. Next, recovering the original analog signal 52 can be accomplished by low-pass filtering the bitstream using a filter, e.g. a simple one or two section passive RC filter (50), which can be mounted on the test-board. The frequency of the signal can be controlled by the modulation characteristics and the test clock rate. The amplitude can simply be changed to a particular value by adjusting the voltage level of the digital pulse, or by changing the amplitude of the signal applied to the modulator circuitry 42. Next Figure 3 shows a general sigma-delta modulation. Generally, 1-bit Sigma-Delta modulation converts a sampled signal into a binary representation using a negative feedback system. It consists of a loop filter (58) h(n), a 1-bit quantizer Q (60) (a comparator for the 1-bit case) and a feedback (62, 56) which subtracts the quantized output y(n) from the input. By itself, such systems have been described earlier, but the present invention expands their use to the field of analog testing. In the conversion process a continuous input signal x(t) is oversampled at a rate f s = 1 / T s much larger than the upper frequency of x(t). The difference between the sampled signal x(n) and the quantized output y(n) is converted to a 1-bit output code y(n) after filtering with the loop filter h(n), and subtracted from the next input sample. By the feedback loop the average digital output signal equals the average input signal as a sort of pulse density modulation. The oversampling and the loop filter or noise shaping filter spread the quantization noise over a large frequency band and shape the frequency content of the large quantization error such that most of its energy lies outside the signal or passband. The frequency spectrum of the bitstream y(n) contains the original signal and a quantization error spectrum with a high-pass character. The amount of in-band quantization noise power in relation to the signal spectrum determines the resolution or dynamic range of the converted analog signal. Now, because of the high-pass character of the quantization noise the simplest possible demodulation to recover the original signal is analog low-pass filtering of the digital waveform. The combination of the digital tester to store the bitstream and a simple discrete analog filter is sufficient to generate high quality test signals. There are various degrees of freedom in the above process, and their choice depends amongst others on the test signals required, i.e. frequency, resolution and type, the available tester frequency and the ease of analog filtering. In the modulation process in particular, the relevant parameters are the sample rate f s and the characteristics of the loop filter h(n). These determine the achievable dynamic range of the signal and impose requirements on the analog low-pass filter. The achievable signal-to-noise-ratio(SNR) for converting a pure sinusoid of frequency f t within a frequency band [0,f b ] through converting at rate f s = OSR. 2f b followed by an ideal low-pass filter with cut off frequency f b is approximated by: SNR = 4 π 3 2 2 L + 1 π L ( OSR ) L + 1 2 In this equation OSR is the oversampling ratio and L is the order of the noise shaping filter h(n). Figures 4A, 4B show examples of first and second order sigma delta modulation, respectively. Figure 4A has a series arrangement of a subtraction element 70, an addition element 72, a delay element 74, and a low-pass filter 76, and provided with two feedback connections as shown. Its behaviour is given by the following difference equation: u(n+1) = u(n) + x(n) - y(n). Figure 4B has a series arrangement of a subtraction element 78, a buffer 80 with an attenuation factor of 0.5, an addition element 82, a delay element 84, a subtraction element 86, an addition element 88, a delay element 90, and a low-pass filter 92, and provided with three feedback connections as shown, of which one is coupled twice into the series arrangement. Its behaviour is given by the following difference equations: v(n+1) = v(n) + 0.5(x(n) - y(n)) u(n+1) = u(n) + v(n) - y(n) The quantizer behaviour is described in both cases as These equations lend themselves well for implementation in a simple computer process, the output of which can be captured in a file (y(n) = 1 ⇒ 1 and y(n) = -1 ⇒ 0) and serve as data-file for the tester. For the situation where a continuous looping over a finite-length data record is used to generate the signal, it is important to acquire periodicity of the data stream for subsequent continuous looping. For sinewave generation this is resolved by an M / N sampling x ( nT s ) = Asin (2 πf t nT s )= Asin (2π n f r f s )= Asin (2π n M N ) in which N samples are taken over M cycles of the sinusoid, thus guaranteeing periodicity in N for the sinewave signal alone. This does not imply that the data stream is periodic as well. Only in the case of first order coders this holds because then the quantization noise occurs in regular patterns and its spectrum is highly coloured. For higher order coders the quantization error tends to be more randomized, resulting in general in a non-periodic bitstream in N, i.e. one which does not repeat itself after N pulses. In order to use such higher order modulator models, one could use a data stream of finite length which contains a whole number of cycles of the original sinewave but not a repetitive noise pattern. Repeating this data stream in a continuous loop will cause the quantization noise pattern to repeat as well and thus it will be harmonically related to the sinewave frequency, resulting in a discrete quantization noise spectrum. Another issue is the amplitude of the sinusoid. The general behaviour is an increase in achievable dynamic range for increasing amplitudes, up to a specific value where overload effects will occur resulting in deterioration of the resolution. Another effect are the oscillations which can occur in coders of order L > 1 under specific input conditions and which will limit the performance of the modulation process. Especially if the repetition frequency of such patterns is comparable to that of the input frequency, they will show up as distortion components in the frequency band of interest. The following table expands the above to allow various decisions to be made in the design: 1. Data record must have finite length 1.1 Continuous looping of data record 1.1.1 This requires signals that are periodic in the length of the record, such as a single cycle of a sinusoid 1.1.1.1 M/N generates periodicity of analog signals 1.1.1.1.1 Quantized noise need not be periodic but is forced to be periodic 1.2 Single sweep of record (needs attention for setting behaviour of filter) 1.2.1 Periodic signals 1.2.1.1 Record may contain several cycles of the signal 1.2.1.2 Put together several records each containing one cycle of the signal 1.2.2 Non-periodic signals 1.2.2.1 If they are bandwidth limited some form of reconstruction may be achieved for approximately the intended signal shape. Figure 5 shows a comparator circuit as used for comparing an analog signal with a reference signal, so that a binary output signal is produced that can be processed in a digital tester. Comparator 100 that receives the unknown voltage V in and a reference voltage V comp as determined by some accessory circuit element 106. Furthermore, the comparator receives strobe signal 104 and outputs to memory 102. For brevity, further control mechanisms have not been shown. The reference voltage V comp is at a predetermined standard value somewhere between an intended high value and an intended low value, so that successive strobes will effect storage of a string of "ones" and "zeroes". Figure 6 shows a comparator circuit as used for A/D conversion. By itself, the hardware corresponds to that of Figure 5. In effect, by means of a variable V comp a kind of serial A/D conversion is realized. The method is based on repeatedly sampling a one-bit digitized version of the analog signal for a particular value of V comp . The compare voltage is now incremented by a number of discrete steps over the range of the analog signal, each step resulting in a one-bit acquisition. This yields a plurality of one/zero bit strings that have been depicted at the right hand side, after realigning with respect to each other. Each column indicates the analog signal value received at a particular instant, expressed as a linear thermometer code, that consists of a string of zeroes followed by a string of ones, the actual value of the analog signal being represented by the transition between the two strings. The latter code can be converted to binary, BCD, or other suitable code. The converter quality predominantly depends on the properties of the comparator, in particular its resolution, accuracy, overdrive quality and hysteresis. The unknown analog signal must be identically repeatable. Through the system described, hardly any further hardware is required.

Claims: A method for testing an electronic circuitry arrangement (22), said method comprising the steps of: providing a test signal of predetermined shape to specific signal input means of the arrangement; operating said arrangement in a predetermined mode; extracting a result signal of intended shape from specific signal output means of said arrangement for subsequent evaluation of said result signal; said method being characterized by modulating a first analog signal (40) into a digital bit stream (44) and presenting said digital bit stream to subsequent filtering means (50) for through analog filtering out of said digital bit stream producing said test signal as a second analog signal (52) at an output of said filtering means. A method as claimed in Claim 1, wherein said modulating is first or second order sigma delta modulation. A method as claimed in Claim 1 or 2, wherein said extracting comprises a step of repeatedly discriminating an output wave result signal with successive threshold levels and subsequently realigning successive discrimination bit stream results for at respective instants generating a thermometer signal code. An apparatus for testing an electronic circuitry arrangement (22), said apparatus comprising: test signal source means (20) for providing a test signal of predetermined shape to specific test signal input means of said arrangement; control means (32, 34) for operating said arrangement in a predetermined mode; extracting means (30) for extracting a result signal of intended shape from specific result signal output means of said arrangement for subsequent evaluation of said result signal; characterized by having modulating means (42) for modulating a first analog signal (40) into a digital bit stream (44) and filtering means (50) fed by said modulating means for through analog filtering out of said digital bit stream producing said test signal as a second analog signal (52) at an output of said filtering means. An apparatus as claimed in Claim 4, wherein said test signal source means has digital storage means (46) for storing the digital bit stream as produced by said modulating means, and for subsequent presentation to said filtering means (50). An apparatus as claimed in claim 4 or 5, wherein said modulating means are arranged for executing first or second order sigma delta modulation. An apparatus as claimed in claims 4, 5 or 6, and comprising boundary scan test interfacing means for interfacing to said electronic circuitry arrangement. An apparatus as claimed in any of claims 4 to 7, and being arranged for executing a selftest by means of having at least partially self-contained said test signal source and/or said evaluation means. An apparatus as claimed in any of claims 4 to 8, wherein said extracting means (30) comprise a discriminating means for discriminating an output wave result signal with successive threshold levels and memory means fed by said extracting means for storing successive discrimination bit stream results for after realigning producing respective thermometer signal codes each associated to an analog signal outputted at a respective instant. An electronic circuitry arrangement as a target for executing a method as claimed in Claim 1, and comprising test signal source means for generating a test signal, test signal input means for receiving the test signal, operating means fed by said test signal input means for in a predetermined operating mode operating on said test signal to produce a result signal of predetermined shape, and result signal output means for outputting said result signal for subsequent evaluation, wherein said test signal source means comprise digital storage means (46) for storing a digital bit stream derived from a first analog signal and filtering means (50) fed by said digital storage means for through analog filtering out of said digital bit stream producing said test signal as a second analog signal (52) at an output of said filtering means.

Inventors: SEUREN GERARDUS PETRUS HELENA, ZWEMSTRA TACO, SEUREN, GERARDUS PETRUS HELENA, ZWEMSTRA, TACO
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1993
Main classification: G01R31
IPC codes: G01R31