Method of manufacturing a heterojunction bipolar transistor

Abstract: The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate (70), a first silicon layer (52) serving as a collector, a first silicon-germanium layer (53) serving as a base, a second silicon layer (54) serving as a collector, and a second silicon-germanium layer (58). A side wall of the second silicon-germanium layer (58) is in contact with side walls of the first silicon layer (52), the first silicon-germanium layer (53) and the second silicon layer (54). The second silicon-germanium layer (58) is disposed to surround the first silicon layer (52), the first silicon-germanium layer (53), and the second silicon layer (54), and has an energy band gap substantially the same as that of the first silicon-germanium layer (53).

Description: The present invention relates to a method of manufacturing a heterojunction bipolar transistor, particularly to a method of manufacturing a heterojunction bipolar transistor which can be operated with a higher speed. The method of the present invention can be used to manufacture a heterojunction bipolar transistor comprising a semiconductor substrate, a first semiconductor layer, which is a collector layer, of a first conductivity type formed on said semiconductor substrate, a second semiconductor layer, which is a base layer, of a second conductivity type formed on said first semiconductor layer, a third semiconductor layer, which is an emitter layer, of the first conductivity type formed on said second semiconductor layer, said third semiconductor layer having an energy band gap larger than that of said second semiconductor layer, and a fourth semiconductor layer of the second conductivity type disposed to surround said first, second and third semiconductor layers, a side wall of said fourth semiconductor layer being in physical contact with side walls of said first, second and third semiconductor layers. Such a transistor is disclosed in IEEE Electron Device Letters, vol. 10, no. 11, November 1989, pp. 503-505 and EP-A-0 430 279. In the latter case, the fourth semiconductor layer is disposed between an upper insulating layer and lower insulating films. Miniaturisation and improvement in the operating speed of a silicon bipolar transistor have now been achieved to some extent. Also, vigorous researches are being made nowadays on a silicon-based heterojunction bipolar transistor in an attempt to further improve the amplification factor and decrease the base resistance of the bipolar transistor. Fig. 1 shows a first example of a conventional heterojunction bipolar transistor of so-called "mesa-type", which is a typical conventional silicon-based heterojunction bipolar transistor. As seen from the drawing, an N - -type silicon layer (collector region) 11, a P-type Si-Ge layer (base region) 12, and an N-type silicon layer (emitter region) 13 are successively formed by an epitaxial growth method on an N + -type silicon substrate 10, followed by forming a P + -type base contact region 14 by means of an ion implantation. Then, the laminate structure consisting of these epitaxial layers is selectively removed by etching to form a mesa structure including the P + -type base contact region 14, followed by forming an insulating film 15 covering the entire surface including the side wall of the mesa structure. After formation of the insulating film 15, emitter and base openings are formed, followed by forming an emitter electrode 18 and a base electrode 17. Further, a collector electrode 16 is formed on the back surface of the substrate. The conventional heterojunction bipolar transistor in Fig. 1 has a rough surface and, thus, is unsuitable for forming an integrated circuit. It should also be noted that the P + -type base contact region 14 is formed after formation of the epitaxial layers in the first prior art shown in Fig. 1. What should be noted is that the heat resistance of the Si-Ge layer 12 included in the epitaxial layers is relatively low. Specifically, the Si-Ge layer 12 is capable of resisting heat of only about 850°C, with the result that a sufficient heat treatment cannot be applied to the P + -type base contact region 14 after the ion implantation step. It follows that the base resistance cannot be lowered sufficiently. What should also be noted is that pn junctions are formed between the P + -type base contact region 14 and the emitter region 13 and between the region 14 and the collector region 11, leading to an increased emitter-base capacitance and an increased base-collector capacitance. Fig. 2 shows a second example of a conventional heterojunction bipolar transistor, which is a typical example of a conventional bipolar transistor of a non-self-alignment type and further details of which are given in G.L. Patton et al., IEEE Electron Device Lett., vol. 11, no. 4, pp. 171-173, April 1990. The second prior art shown in Fig. 2 is of a planar type. As shown in the drawing, an N + -type silicon buried layer 21 and an N-type silicon layer (collector region) 22 are formed in this order on a P-type silicon substrate 20, followed by forming an element separation region 23 consisting of an insulating material so as to define an element-forming region. In the next step, a P-type Si-Ge layer 24 is formed in a manner to cover a transistor-forming region. That portion of the Si-Ge layer which is in contact with a silicon single crystal forms a single crystalline Si-Ge layer 24a. On the other hand, that portion of the Si-Ge layer which is in contact with the element separating region 23 forms a polycrystalline Si-Ge layer 24b. Further, an etching-stopping layer (SiN layer) 25 is formed in a manner to cover an emitter-forming region on the surface of the single crystalline Si-Ge layer (base region) 24a. After formation of the etching-stopping layer 25, a P + -type polycrystalline silicon layer 26 acting as a lead wire connected to the base region is formed in a manner to cover the etching-stopping layer 25 and the Si-Ge layer 24. Then, that portion of the P + -type polycrystalline silicon layer 26 which is positioned in the emitter-forming region is removed, followed by forming an insulating layer 27 in a manner to cover the P + -type polycrystalline silicon layer 26. Further, the etching-stopping layer 25 positioned within the emitter-forming region is removed, followed by forming an emitter polycrystalline silicon layer 28. Finally, a collector electrode 16, a base electrode 17, and an emitter electrode 18 are formed as shown in the drawing. The second prior art shown in Fig. 2 is of a planar type, making it possible to use the second prior art for forming an integrated circuit. In this prior art, however, the P + -type polycrystalline silicon layer leading to the base region is not self-aligned with the base layer, with the result that the base resistance is increased. Further, openings are formed in the etching-stopping layer 25 before formation of the emitter polycrystalline silicon layer 28. What should be noted is that the surface of the single crystalline Si-Ge layer is exposed to the outer atmosphere when the openings are formed in the etching-stopping layer, with the result that a natural oxide film is formed on the exposed surface. It follows that it is difficult to control the interface between the emitter polycrystalline silicon layer 28 and the base Si-Ge layer 24a. Fig. 3 shows a third example of a conventional heterojunction bipolar transistor, which is of a typical self-alignment type and further details of which are given in F. Sato et al., 1990 IEDM Tech. Dig., pp. 607-610. As shown in the drawing, an N + -type silicon buried layer 31 and an N-type silicon layer (collector region) 32 are formed in this order on a P-type silicon substrate 30, followed by forming an element separating region 33 consisting of an insulating material so as to define an element-forming region. Then, a second insulating film 34 is deposited on the substrate surface, followed by forming a P + -type polycrystalline silicon layer 35 acting as a wiring leading to a base region and subsequently forming an insulating film 36 in a manner to cover the upper and side surfaces of the polycrystalline silicon layer 35. Further, the insulating film 36 and the P + -type polycrystalline silicon layer 35 on an emitter-forming region are selectively removed to selectively expose the second insulating film 34, followed by forming a first side wall 37 consisting of an insulating film. In the next step, the exposed portion of the second insulating film 34 is removed by etching to form an opening. In this step, the opening extends sideward because of the side etching of the second insulating film 34. After the etching step, a P-type Si-Ge epitaxial layer (base region) 38 is formed within the opening thus formed. Then, the opening above the base region 38 is filled with an insulating film, followed by selectively etching the insulating film. In this step, a second side wall 39 is formed because of the side etching effect. Further, an emitter polycrystalline silicon layer 19 is formed in the opening resulting from the selective etching of the insulating film. Still further, the insulating films covering the collector region, base region and emitter region are selectively removed to form openings, followed by forming a collector electrode 16, a base electrode 17 and an emitter electrode 18 in the openings thus formed. In the third prior art shown in Fig. 3, the insulating film filling the opening positioned above the base Si-Ge layer 38 is removed by an reactive ion etching (RIE) to form the second side wall 39. What should be noted is that the thin base Si-Ge layer 38 is struck by ions during the reactive ion etching step. As a result, problems take place such as reduction in the thickness, contamination and disturbance of crystals of the base Se-Ge layer 38, leading to difficulties in the control capability and element characteristics of the device. Also, the Si-Ge base layer 38 is exposed to the outside before formation of the emitter polycrystalline silicon layer 19, as in the second prior art shown in Fig. 2. As a result, a natural oxide film is formed, making it difficult to control the interface between the emitter polycrystalline silicon layer 35 and the base Si-Ge layer 38. As described above, the conventional heterojunction bipolar transistors leave much room further improvements. To reiterate, the first prior art shown in Fig. 1. i.e., a heterojunction bipolar transistor mesa type, is not suitable for forming an integrated circuit. Also, the first prior art has a high base resistance and a high parasitic capacitance between the emitter and base regions and between the base and collector regions. When it comes to the second prior art shown in Fig. 2, i.e., a heterojunction bipolar transistor of a planar non-self-alignment type, it is certainly possible to use the bipolar transistor forming an integrated circuit. However, the second prior art has a high base resistance because the transistor is of a non-self-alignment type. Also, since the surface of the base Si-Ge layer is exposed to the outside before the step of forming the emitter layer, the exposed surface of the base layer tends to be contaminated, making it difficult to control as desired the interface between the base and emitter regions. The third prior art shown in Fig. 3, i.e., a heterojunction bipolar transistor of a planar and self-alignment type, certainly permits improving the problems inherent in the first and second prior arts to some extent. In the third prior art, however, it is necessary to form the second side wall because the transistor is of a self-alignment type. What should be noted is that the second side wall is formed by selectively removing an insulating film formed in advance. The insulating film is selectively removed by a reactive ion etching. During the reactive ion etching step, a thin base Si-Ge layer is struck by ions. As a result, mechanical damages are done to the base Si-Ge layer such as reduction in the thickness, contamination and crystal disturbance, leading to difficulties in the control capability and element characteristics. Further, the surface of the base Si-Ge layer is exposed to the air atmosphere during the manufacturing process of the heterojunction bipolar transistor, as in the second prior art shown in Fig. 2. It follows that the surface of the base Si-Ge layer tends to be contaminated. Also, it is difficult to control the interface between the emitter and base regions. The present invention has been achieved in view of the situation described above and is intended to provide an improved method of manufacturing a heterojunction bipolar transistor. According to the invention there is provided a method of manufacturing a heterojunction bipolar transistor, comprising the successive steps of: preparing a semiconductor substrate; forming first and second insulating films on said semiconductor substrate; forming a first polycrystalline silicon layer of a first conductivity type on an entire surface of the structure resulting from the preceding step; selectively removing said first polycrystalline silicon layer, thereby exposing a surface of said semiconductor substrate and defining a side wall of said first polycrystalline silicon layer; forming a nitride layer on an entire surface of the structure resulting from the preceding step in a manner to cover said side wall of said first polycrystalline silicon layer; forming a first insulating layer on the entire surface of the structure resulting from the preceding step; selectively removing said first insulating layer and said nitride layer within an area where the first polycrystalline layer has already been removed, thereby forming an opening extending to reach said semiconductor substrate, said side wall of said first polycrystalline silicon layer not being exposed by said opening, and thereby defining a side wall of said nitride layer; forming a laminate structure consisting of a first semiconductor layer of a second conductivity type, a second semiconductor layer of said first conductivity type and a third semiconductor layer of said second conductivity type by means of an epitaxial vapor growth technique, said opening being filled with said laminate structure, said third semiconductor layer being made of a material having an energy band gap larger than that of the material of the second semiconductor layer, and at least a side wall of said second semiconductor layer being in physical contact with said side wall of said nitride layer; selectively removing said insulating layer and said nitride layer, said first insulating layer and said nitride layer being not removed in the vicinity of said laminate structure, thereby allowing the remaining portions of these insulating layer and nitride layer to surround said laminate structure consisting of the first, second and third semiconductor layers; removing the remaining portion of said nitride layer, thereby forming a cavity (F) exposing at least said side wall of said second semiconductor layer; and forming a fourth semiconductor layer of said first conductivity type and being made of a material having an energy band gap which is the same as that of the material of said second semiconductor layer, by means of an epitaxial vapor growth technique, said fourth semiconductor layer covering the first polycrystalline silicon layer and the side walls of said laminate structure consisting of the first, second and third semiconductor layers exposed in said cavity (F), said cavity (F) being filled with said fourth semiconductor layer. The present manufacturing method is intended to suppress undesired mechanical damages done to the base layer such as reduction in the thickness and disturbance of crystals, and to prevent the outer surface of a base Si-Ge layer from being exposed to the air atmosphere during the manufacturing process of the heterojunction bipolar transistor so as to improve the capability of controlling the emitter-base interface. The present invention is also intended to achieve manufacture of a base-emitter structure by self-alignment technique without employing a manufacturing step requiring a technique of a particularly high level so as to diminish sufficiently the base resistance and the stray capacitance. It follows that the heterojunction bipolar transistor can be operated with a high speed. This invention will be more fully understood from the following detailed description, given by way of example, when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross sectional view showing a first conventional heterojunction bipolar transistor; Fig. 2 is a cross sectional view showing a second conventional heterojunction bipolar transistor; Fig. 3 is a cross sectional view showing a third conventional heterojunction bipolar transistor; Fig. 4 is a cross sectional view showing a heterojunction bipolar transistor manufactured in accordance with a preferred way of performing the present invention; Fig. 5 is a cross sectional view showing in a magnified fashion a gist portion of the heterojunction bipolar transistor; and Figs. 6 to 16 are cross sectional views collectively showing a method of manufacturing the heterojunction bipolar transistor according to an embodiment of the present invention, wherein Fig. 10A shows in a magnified fashion a gist portion of the structure shown in Fig. 10B, Fig. 12A shows in a magnified fashion a gist portion of the structure shown in Fig. 12B, and Fig. 14A shows in a magnified fashion a gist portion of the structure shown in Fig. 14B. Let us now describe a heterojunction bipolar transistor with reference to the accompanying drawings. Fig. 4 is a cross sectional view showing a heterojunction bipolar transistor. On the other hand, Fig. 5 shows in a magnified fashion a gist portion of the heterojunction bipolar transistor put in a circle R in Fig. 4. In the heterojunction bipolar transistor shown in Fig. 4, a laminate structure consisting of first, second and third single crystal semiconductor layers is formed on a main surface of an N - -type silicon layer 43 constituting the uppermost layer of a SOI (silicon on insulator) substrate 70. As shown in the drawings, the laminate structure noted above consists of a first single crystal semiconductor layer (N-type silicon layer) 52 of a first conductivity type, which is formed of a first semiconductor material, a second single crystal semiconductor layer (P-type Si-Ge layer) 53 of a second conductivity type opposite to said first conductivity type, which is formed of a second semiconductor material, and a third single crystal semiconductor layer (N-type silicon layer) 54 of the first conductivity type, which is formed of the first semiconductor material. The heterojunction bipolar transistor also comprises a fourth single crystal semiconductor layer (P-type single crystal Si-Ge layer) 58a which is in contact with the side wall of each of the first single crystal semiconductor layer (N-type silicon layer) 52, the second single crystal semiconductor layer (P-type Si-Ge layer) 53 and the third single crystal semiconductor layer (N-type silicon layer) 54. Figs. 6 to 16 collectivelv show how to manufacture the heterojunction bipolar transistor shown in Fig. 4 in accordance with an embodiment of the present invention. First of all, Fig. 6 shows a SOI substrate 70 included in the heterojunction bipolar transistor. As seen from the drawing, the SOI substrate 70 is prepared by forming successively a silicon oxide film 41, an N + -type silicon layer 42, and an N - -type silicon layer 43 on a silicon substrate 40. It is possible to use an ordinary epitaxial substrate or a silicon substrate as the substrate 70. However, it is desirable to use a SOI substrate as shown in the drawing so as to diminish, for example, a stray capacitance in the produced bipolar transistor. In forming the structure shown in Fig. 7, an element separating region is formed first by a trench isolation and recess method. An oxide film 44 formed in the side wall portion of a trench has a thickness of 300 nm. A buried polycrystalline silicon film 45 is not doped with an impurity and, thus, exhibits a high resistivity. An oxide film 46 in a recess separation region has a thickness of 300 nm. The thickness of each of these films 44, 45 and 46 can be determined appropriately in view of the voltage applied to the transistor, the stray capacitance of the transistor, etc. Further, a relatively thin thermal oxide film (first insulating film) 47 is formed on the surfaces of an element-forming region A and a collector take-out region B. In the structure shown in the drawing, the thermal oxide film 47 has a thickness of 50 nm. In the next step, a P-type polycrystalline silicon layer 48 acting as an electrode layer leading to a base region, which is also called an outer base region, is formed on the entire surface. The polycrystalline silicon layer 48 has a thickness of 200 nm. The polycrystalline silicon layer 48 may be doped with a P-type impurity in the step of forming the layer 48 or after formation of the layer 48. The polycrystalline silicon layer 48 thus formed is selectively removed in an element-forming region C. Incidentally, the region C is defined by the edges of the remaining portions of the polycrystalline silicon layer after the selective removing step. After the selective removing step of the layer 48, a nitride film made of silicon nitride (second insulating film) 49 and a silicon oxide film (third insulating film) 50 are successively formed on the entire surface by a CVD method. The silicon nitride film 49 has a thickness of 200 nm, and the oxide film 50 is 400 nm thick. In the next step, an opening 51 extending to reach the surface layer 43 of the substrate 70 is formed in the element-forming region by selectively removing successively the silicon oxide film (third insulating film) 50, the silicon nitride film (second insulating film) 49, and the thermal oxide film (first insulating film) 47, as shown in Fig. 9. In forming the opening 51, these insulating films are removed continuously by a reactive ion etching method using a resist block by an ordinary lithography technique. It is important to note that the opening 51 should be positioned accurately within the element-forming region C shown in Fig. 8. In other words, the side wall of the P-type polycrystalline silicon layer 48 should not be exposed to the opening 51. If the region C is made unduly large in an attempt to ensure safety, however, it is impossible to secure a connecting region to an outer base region. Even if connection to the outer base can be achieved, a difficulty is brought about that the base resistance is increased. Naturally, it is important to diminish the region C as much as the manufacturing technique permits. In the structure shown in the drawing, an allowance of 0.3 micrometre is provided in the design step between the element-forming region C and the opening 51. It is possible to avoid deterioration of the element characteristics accompanying an increase in the base resistance by providing an allowance noted above of at most 0.5 micrometre. Fig. 10A shows in a magnified fashion a region put within a circle R in Fig. 10B. As shown in Fig. 10A, formed within the opening 51 are an N-type collector silicon layer (first single crystal semiconductor layer) 52, a P-type base Si-Ge layer (second single crystal semiconductor layer) 53, an N-type emitter layer (third single crystal semiconductor layer) 54, an N + -type emitter silicon layer 55, and a metal silicide layer 56. These semiconductor layers 52, 53, 54 and 55 are successively formed by an epitaxial growth utilizing a CVD method under a reduced pressure. In other words, these semiconductor layers should be formed under a hermetically sealed condition such that these semiconductor layers should not be exposed to the air atmosphere. The thickness of each of the first to third single crystal semiconductor layers 52, 53 and 54 should be determined to permit these semiconductor layers to be in contact with the silicon nitride film 49 exposed to the opening 51. Incidentally, it is possible for the N + -type silicon layer 55 to be formed of polycrystalline silicon. The nitride layer 49 need not be restricted to a silicon nitride film as far as a polycrystalline silicon layer is not formed on the side wall in the steps of forming the N-type collector silicon layer (first single crystal semiconductor layer) 52, the P-type base Si-Ge layer (second single crystal semiconductor layer) 53, the N-type emitter silicon layer (third single crystal semiconductor layer) 54, and the N + -type emitter silicon layer 55. Also, the material of the layer 49 should be determined such that the layers surrounding the layer 49 should not be etched in the step of removing the layer 49, which will be described later with reference to Figs. 14A and 14B. After formation of the semiconductor layers 52 to 55 and the metal silicide layer 56 within the opening 51, a silicon oxide film 57 is formed on the entire surface of the substrate by a CVD method, as shown in Fig. 11. The silicon oxide film 57 should be 400 nm thick. Fig. 12A shows in a magnified fashion a portion put within a circle R shown in Fig. 12B. Naturally, the structure shown in Fig. 12 is prepared by selectively removing the silicon oxide films 57, 50 and the silicon nitride film 49 shown in Fig. 11 such that these insulating films are left unremoved in the vicinity of the opening 51 to form an element gist region D. These insulating films should be removed by a reactive ion etching. The element gist region D is formed in order to define the edge portion of an outer base lead-out region which is formed in the vicinity of the element gist region. It is necessary to diminish the region D as much as possible as in the formation of the opening 51 in the step shown in Fig. 9. In the structure shown in the drawing, an allowance of 0.3 micrometre is provided in the design step in the outer circumferential region of the opening portion C of the polycrystalline silicon layer 48 shown in Fig. 5. In the next step, the P-type polycrystalline silicon layer 48 is selectively removed except for the regions used as outer base lead-out regions, as shown in Fig. 13. Fig. 14A shows in a magnified fashion a portion put in a circle R in Fig. 14B. As seen from the drawings, the silicon nitride film (second insulating film) 49 is selectively removed by etching with a hot phosphoric acid of 130 to 160°C to form the structure shown in Fig. 14. As a result, formed is an opening F to which are exposed the side walls of the epitaxial layers 52, 53, 54 (first, second and third single crystal semiconductor layers). In other words, it is necessary to determine in advance the thickness of each of the N-type collector silicon layer 52, the P-type base Si-Ge layer 53 and the N-type emitter silicon layer 54 appropriately such that the side walls of these layers 52 to 54 are exposed to the opening F. After formation of the opening F, a P-type Si-Ge layer 58 is selectively grown to fill the opening F resulting from removal of the second insulating film 49 and to cover the P-type polycrystalline silicon layer 48, as shown in Fig. 15. In this step, a single crystal Si-Ge layer (fourth single crystal semiconductor layer) 58a is grown to form a region which is in contact with the side walls of the first to third single crystal semiconductor layers. Also, a polycrystalline Si-Ge layer 58b is grown to cover the P-type polycrystalline silicon layer 48. It follows that the base region 53 of the element portion is connected to the outer base lead-out region. Incidentally, the outer base lead-out region is formed of a laminate structure consisting of the P-type polycrystalline silicon layer 48 and the Si-Ge layer 58. It follows that the base lead-out resistance can be diminished by adjusting the resistance value of the P-type polycrystalline silicon layer 48. Incidentally, the material of the layer 58 need not be restricted to Si-Ge. It is also possible for the layer 58 to be formed of a material which is substantially equal in the energy band gap to the P-type base Si-Ge layer 53 in the case where the layer 53 is used as a base of the heterojunction bipolar transistor. In the next step, a silicon oxide film 59 is formed on the entire surface of the substrate by a CVD method, followed by smoothing the entire region of the silicon oxide film 59 by an ordinary smoothing technique and subsequently reducing the thickness of the oxide film so as to expose the emitter upper portion. Further, contact holes for the collector H and the base G are formed in the silicon oxide film 59 by a known method, as shown in Fig. 4, followed by forming a collector electrode 62, a base electrode 61 and an emitter electrode 60. In the structure described above, the opening 51 extending to reach the substrate is formed in the laminate structure formed on the main surface of the substrate, said laminate structure consisting of the first insulating film (SiO 2 ) 47, the second insulating film (SiN) 49 and the third insulating film (SiO 2 ) 50, followed by successively filling the opening 51 with the first single crystal silicon semiconductor layer 52, the second single crystal Si-Ge semiconductor layer 53, and the third single crystal silicon semiconductor layer 54 in this order by a continuous selective epitaxial growth technique so as to form the emitter-base junction and the base-collector junction performing the transistor function by self-alignment. It should be noted that these single crystal semiconductor layers are formed under a hermetically sealed condition. What should also be noted is that the interfaces between the emitter region and the base region and between the base region and the collector regions are not exposed to the air atmosphere. Also, these interfaces are not subjected to ion bombardment. It follows that the problems inherent in the prior art, which are caused by the contamination, crystal disturbance, etc. in the interfaces, do not take place in the disclosed heterojunction bipolar transistor. It should also be noted that, after formation of the emitter layer, the base layer and the collector layer performing the transistor function, the second insulating film (SiN) is selectively removed by etching with a hot phosphoric acid so as to form an opening such that the side walls of the base layer, the emitter layer and the collector layer are partly exposed to the opening. Then, the Si-Ge single crystal layer is allowed to grow in the lateral direction within the opening such that the grown layer is in contact with the exposed side walls of these base, emitter and collector layers. As a result, the opening is filled with the Si-Ge single crystal layer. Growth of a single crystalline or polycrystalline Si-Ge layer is further continued so as to form easily a base lead-out layer having a low resistance. Further, the base lead-out layer is surrounded by the first and third insulating films, etc. and does not form a junction with the collector or emitter region. It follows that the stray capacitance can be sufficiently diminished. As described above in detail, it is possible to provide an improved method of manufacturing a heterojunction bipolar transistor. To be more specific, suppressing undesired mechanical damages done to the base layer is permitted such as reduction in the thickness and disturbance of crystals, and also the outer surface of a base Si-Ge layer can be prevented from being exposed to the air atmosphere during the manufacturing process of the heterojunction bipolar transistor so as to improve the capability of controlling the emitter-base interface. It is also possible to achieve a base-emitter structure by self-alignment technique without employing a manufacturing step requiring a technique of a particularly high level so as to diminish sufficiently the base resistance and the stray capacitance. It follows that the disclosed heterojunction bipolar transistor can be operated with high speed.

Claims: A method of manufacturing a heterojunction bipolar transistor, comprising the successive steps of: preparing a semiconductor substrate (70); forming first and second insulating films (46,47) on said semiconductor substrate (70); forming a first polycrystalline silicon layer (48) of a first conductivity type on an entire surface of the structure resulting from the preceding step; selectively removing said first polycrystalline silicon layer (48), thereby exposing a surface of said semiconductor substrate and defining a side wall of said first polycrystalline silicon layer (48); forming a nitride layer (49) on an entire surface of the structure resulting from the preceding step in a manner to cover said side wall of said first polycrystalline silicon layer (48); forming a first insulating layer (50) on the entire surface of the structure resulting from the preceding step; selectively removing said first insulating layer (50) and said nitride layer (49) within an area where the first polycrystalline layer (48) has already been removed, thereby forming an opening (51) extending to reach said semiconductor substrate (70), said side wall of said first polycrystalline silicon layer (48) not being exposed by said opening (51), and thereby defining a side wall of said nitride layer (49); forming a laminate structure consisting of a first semiconductor layer (52) of a second conductivity type, a second semiconductor layer (53) of said first conductivity type and a third semiconductor layer (54) of said second conductivity type by means of an epitaxial vapor growth technique, said opening (51) being filled with said laminate structure, said third semiconductor layer (54) being made of a material having an energy band gap larger than that of the material of the second semiconductor layer (53), and at least a side wall of said second semiconductor layer (53) being in physical contact with said side wall of said nitride layer (49); selectively removing said insulating layer (50) and said nitride layer (49), said first insulating layer (50) and said nitride layer (49) being not removed in the vicinity of said laminate structure, thereby allowing the remaining portions of these insulating layer (50) and nitride layer (49) to surround said laminate structure consisting of the first, second and third semiconductor layers (52, 53, 54); removing the remaining portion of said nitride layer (49), thereby forming a cavity (F) exposing at least said side wall of said second semiconductor layer (53); and forming a fourth semiconductor layer (58) of said first conductivity type and being made of a material having an energy band gap which is the same as that of the material of said second semiconductor layer (53), by means of an epitaxial vapor growth technique, said fourth semiconductor layer (58) covering the first polycrystalline silicon layer (48) and the side walls of said laminate structure consisting of the first, second and third semiconductor layers (52, 53, 54) exposed in said cavity (F), said cavity (F) being filled with said fourth semiconductor layer (58). The method of manufacturing a heterojunction bipolar transistor according to claim 1, which further comprises the steps of: forming a fifth semiconductor layer (55) of said second conductivity type on said third semiconductor layer (54); forming a metal silicide layer (56) on said fifth semiconductor layer (55); and forming a second insulating layer (57) on an entire surface of the structure resulting from the preceding step. The method of manufacturing a heterojunction bipolar transistor according to any one of claims 1 or 2, characterised in that said semiconductor substrate has a silicon-on-insulator structure. The method of manufacturing a heterojunction bipolar transistor according to any one of claims 1, 2 or 3, characterised in that said step of removing the remaining portion of said nitride layer (49) is carried out by using hot phosphoric acid. The method of manufacturing a heterojunction bipolar transistor according to any one of claims 1 to 4, characterised in that said step of forming a laminate structure consisting of a first semiconductor layer (52), a second semiconductor layer (53) and third semiconductor layer (54) by means of an epitaxial vapor growth technique is carried out by using a low pressure CVD method. The method of manufacturing a heterojunction bipolar transistor according to any one of claims 1 to 5, characterised in that said step of forming a laminate structure consisting of a first semiconductor layer (52), a second semiconductor layer (53) and a third semiconductor layer (54) is carried out under the condition that these semiconductor layers (52, 53, 54) are not exposed to the air atmosphere.

Inventors: KIMURA KOUJI, KUMAMARU KUNIAKI, NARUSE HIROSHI, TAKA SHIN-ICHI, KIMURA, KOUJI, KUMAMARU,KUNIAKI, NARUSE, HIROSHI, TAKA, SHIN-ICHI, Kimura, Kouji, c/o Intellectual Property Div., KUMAMARU,KUNIAKI,C/O INTELLECTUAL PROPERTY DIV., Naruse, Hiroshi, c/o Intellectual Property Div., Taka, Shin-ichi, c/o Intellectual Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: H01L29
IPC codes: H01L21, H01L29