Ink-jet type recording head and monolithic integrated circuit suitable therefor

Abstract: A recording head (100) comprises a liquid emission member having an orifice through which an ink is emitted, an electro-thermal converter (32) element for generating a thermal energy which is utilized to emit the ink introduced into the liquid emission member (103), and a functional element disposed on a same substrate on which the electro-thermal converter element is disposed for driving and controlling the electro-thermal converter element (32). The functional element includes an NPN bipolar transistor for driving the electro-thermal converter element and a CMOS transistor composed of an NMOS transistor and a PMOS transisfor for controlling an operation of the bipolar transistor. The NMOS transistor being formed in a P well diffusion layer in an N⁻ type epitaxial growth layer which is grown on a surface of a P type semiconductor substrate. The PMOS transistor being formed in an N well diffusion layer in the N⁻ type epitaxial growth layer which is grown on the surface of the P type semiconductor substrate.

Description: The present invention relates to an ink-jet type recording head and a monolithic integrated circuit suitable therefor, in particular one comprising a monolithic integrated circuit suitable for an ink-jet type recording head, said circuit comprising: a semiconductor substrate; an electro-thermal converter element, for generating thermal energy to emit ink from an orifice in a recording head, integral with said substrate; and a driver circuit, for driving said element, disposed on said substrate. A monolithic integrated circuit of this type is described in US-A-5,045,870. Ink-jet recording heads which emit droplets of ink by boiling bubbles in the ink have been widely used for various kinds of recording devices such as printers or video printers which are suitable and well utilised as output terminals for copiers, facsimiles, word processors and host computers. Recording heads of this kind are constructed with an ink emitting portion having an orifice through which ink is emitted, an electrothermal converter generating thermal energy to eject ink supplied to the ink emitting portion, and a driving component for driving the electro-thermal converter are integrally consolidated on the same substrate. EP-A-0532877, published 24 March 1993, mentioned here with reference to Art. 54(3) EPC, describes a head having an electro-thermal converter which is integrated with a drive circuit, a logic circuit, a shift register and a latch circuit, on the same substrate. Fig. 1 illustrates a pattern layout disposed on a substrate 31 of an ink-jet type recording head in accordance with the above mentioned application. An electro-thermal converter 32, which is constituted as an array composed of a plurality of elements, is located along the vicinity of one side of the substrate 31 on grounds that ink is supplied from both surfaces of the one side of the substrate and that the flow resistance can be reduced if the electro-thermal converter 32 is located at the vicinity of an ink supplying chamber which is usually located near the one side of the substrate 31 thereby to accomplish high speed accessibility of ink projection. This high speed accessibility can be more improved if the electro-thermal converter 32 is located within 1,000 µm in length from the side surface of the substrate 31. Further, the closer the electro-thermal converter 32 is located toward the side surface, the more the effect is improved. There are disposed electric contacts 37, 38, 39 on both surfaces of the substrate 31 at the vicinity of another both sides thereof. The V H contact 37 constitutes a contact of a V H wiring portion 33 which supplies electric energy (pulse) to each of respective electro-thermal converters. The GND contact 38 constitutes a contact of a ground (GND) wiring portion 35 to which the supplied electric energy is grounded. The logic contact 39 constitutes a signal contact of a logic circuit 36 which is composed of a plurality of logic circuits. There is also disposed a transistor array 34 located between the V H wiring 33 and the GND wiring portion 35 and connected respectively to each of the electro-thermal converters so as to selectively drive the converters. The transistor array 34 is connected such that each of the transistors of the array 34 is controlled by the logic circuit 36. Fig. 2 shows a cross-sectional view illustrating a part of a monolithic integrated circuit chip in which a heater board is incorporated produced by way of experiment by the inventors of the above described application. There are formed in the same substrate an electro-thermal converter 11, a high voltage proof bipolar NPN transistor 7 which drives the converter 11, and a logic circuit which is constituted by a CMOS circuit composed of PMOS and NMOS transistors. An N - type epitaxial layer 5 is grown on the surface of a P type silicon substrate 1 in which an N + buried diffusion layer 2 is formed. An NPN bipolar transistor region 7, which is composed of a P - type diffusion layer 14, a P + type diffusion layer 12, and N + type diffusion layer 13 formed in, and a first layer aluminum wiring 10 formed on, an N - type epitaxial layer 5. A P well diffusion layer 4 is formed to isolate each of the composed components electrically in the epitaxial layer 5 . This reaches a P + type buried diffusion layer 3 which is also formed in the substrate 1. An NMOS transistor region 8, which is composed of an N + type diffusion layer 13 serving a source/drain, a gate electrode 15 and the first layer aluminum wiring 10, is formed in the P well diffusion layer 4. The P well diffusion layer 4 is also utilized as an isolation layer which isolates the components from the surface. A PMOS transistor region 9, which is composed of a P + type diffusion layer 12 serving a source/drain, a gate electrode 15 and the first layer aluminum wiring 10, is formed in the N - type epitaxial layer 5 on the N + type buried diffusion layer 2. In the drawing, a reference numeral 16 denotes an N + type diffusion layer; numerals 17, 18 and 19 denote a silicon dioxide (SiO 2 ) film, an insulating film and an aluminum inter-layer insulating film, respectively; a numeral 20 denotes a second layer aluminum wiring; and numerals 21 and 22 denote a surface passivation film and a tantalum surface passivation film, respectively. In the above described structure, the NPN transistor in the region 7 is formed in the relatively thicker epitaxial layer 5 having 8 to 10 µm in thickness in order to maintain high voltage proof against a power source voltage determined by an energy amount supplied to the electro-thermal converter 11. Accordingly, the P well diffusion layer 4, which serves as an isolation region on the surface of the substrate must be formed adjacent to the NPN transistor in the region 7 with a relatively large gap therebetween. As described above, the experimental structure shown in Fig. 2 incorporates the PMOS transistor in the epitaxial growth layer 5 in order to maintain high voltage proof, which requires a wide space region as the region 9 for the PMOS transistor comparing with the region 8 for the NMOS transistor. Fig. 3 shows an equivalent circuit of the integrated circuit including the portion illustrated in Fig. 2. A reference numeral 41 denotes an electro-thermal converter array; 42 and 43 a first and a second transistors; 44 a logic gate; 45 a latch logic; 46 a shift register; 47 a heater to V H connection wiring; 48 a V H wiring; 49 GND wiring; 50 an enable wiring; 51 a latch wiring; 52 a serial data wiring; and 53 a clock wiring. The above described structure has, however, following problems to be solved. In case of the layout shown in Fig. 2, it is desired to dispose the electro-thermal converter in parallel with the NPN transistor, the logic circuit, the latch circuit and the shift register all of which are used for driving the electro-thermal converter. The layout of the electro-thermal converter elements must be arrayed with a pitch determined depending on a recording density. The recording density having 360 dpi requires 70.5 µm in pitch. The NPN transistor, the logic circuit, the latch circuit and the shift register are preferably to be arrayed with the same pitch as that of the electro-thermal converter elements by enhancing the density of the array. Fig. 4 illustrates a pattern layout disposed on a substrate for a head produced by way of the experiment. The array density of the electro-thermal converter can be increased by optimizing the shape and sheet resistance of the converter. However, if the effort is made to cope with the increase of the recording density with the efficiency of the inter-layout wiring being kept high by making in the manner described above the electro-thermal converter to be in parallel with the logic circuit, the latch circuit and the shift register, the array lengths of the logic circuit, the latch circuit and the shift register will be much longer than that of the electro-thermal converter resulting in an unwanted increase in the size of the substrate and increasing manufacturing costs. In an article in the Proceedings of the IEEE 1988 Custom Integrated Circuits Conference K Tsubone et al. with the title 'A Smart BiCMOS Driver for 400 DPI Thermal Printing Heads', p. 5.2.1 - 5.2.4, 16.5.88, Rochester N.Y, there is disclosed a smart BiCMOS driver for a thermal printing head. In this integrated semiconductor circuit the P well is completely separated from the P-type substrate and is arranged within an N-type epitaxial layer. Thus the potential of the P well may be unstable. A primary concern of the present invention is to provide an ink-jet type recording head which can resolve the foregoing problems by increasing an array density to prevent a size of the substrate being increased. A further concern of the present invention is to provide a monolithic integrated circuit suitable for the above mentioned ink-jet type recording head. In accordance with the present invention there is provided a monolithic integrated circuit as set out in claim 1. Since the present invention employs a twin well structure for MOS transistors in a CMOS circuit constituting the logic circuit, the latch circuit and the shift register, all of which drive the electro-thermal converter, the array density of the components can be increased enabling to cope with the increase of the recording density without enlarging the size of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages of the invention will be more clearly understood from the following detailed description of the preferred embodiments with reference to the accompanying drawings in which: Fig. 1 shows a conventional pattern layout diagram disposed on a substrate; Fig. 2 shows a partial cross-sectional view illustrating a monolithic integrated circuit in which a heater board is incorporated produced by way of experiment; Fig. 3 shows an equivalent circuit diagram of a part of the circuit illustrated in Fig. 2; Fig. 4 shows a pattern layout diagram disposed on a substrate for a head produced by way of the experiment; Fig. 5A shows a partial cross-sectional view illustrating a monolithic integrated circuit according to the present invention in which a heater board is incorporated; Fig. 5B shows another partial cross-sectional view illustrating a monolithic integrated circuit according to the present invention in which a heater board is incorporated; Fig. 6A shows an example of a recording head to which the present invention is applied; and Fig. 6B shows an example of the recording device to which the present invention is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One preferred embodiment according to the present invention is shown in Figs. 5A and 5B. In Fig. 5A, the reference numeral 1 denotes a P type silicon substrate; 2 an N + type buried layer forming a collector region of an NPN transistor; 3 a P + type buried diffusion layer formed in the substrate to isolate each of components from the substrate; 4 a P type P well diffusion layer for the purpose of providing isolation from the surface together with formation of the NPN transistor; 5 an N - type epitaxial growth layer; and 6 an N type N well diffusion layer for the purpose of forming a PMOS transistor. Both the P well diffusion layer 4 and the N well diffusion layer 6 are formed in the N - type epitaxial growth layer 5. Fig. 5B shows an illustration that an orifice plate 102 is disposed on a head substrate 101 to form an outlet and a flow path of ink. In Fig. 5A, a region 7 denotes a bipolar NPN transistor formed in the N - type epitaxial growth layer 5 to have a P - type diffusion layer 14, a P + type diffusion layer 12, an N + type diffusion layer 13 and an aluminum wiring 10 by way of various diffusion and wiring processes. A region 8 denotes an NMOS transistor formed in the P well diffusion layer 4 to have the N + type diffusion layer 13, a gate electrode 15, the P + type diffusion layer 12 and the aluminum wiring 10 by way of various diffusion and wiring processes. A region 9 denotes a PMOS transistor formed in the N well diffusion layer 6 to have the P + type diffusion layer 12, the gate electrode 15, the N + type diffusion layer 13 and the aluminum wiring 10 by way of various diffusion and wiring processes. A reference numeral 11 denotes an electro-thermal converter element connected to the aluminum wiring line to interconnect with the collector of the bipolar NPN transistor. The converter element 11 is, for example, composed of H f B z and extended to an ink orifice, which is not shown, to emit drops of ink by heating the ink. An operation of the NPN bipolar transistor for driving the electro-thermal converter element 11 is controlled by a shift register, a latch circuit and a logic gate, all of which are constituted by CMOS transistors having NMOS and PMOS transistors. The equivalent circuit of the structure shown in Fig. 5A is same as that shown in Fig. 3. In Figs. 5A and 5B, a reference numeral 16 denotes an N + type diffusion layer; 17, 18 and 19 a silicon dioxide (SiO 2 ) film, an insulating film and an insulating film for aluminum inter-layer, respectively; 20 a second layer aluminum wiring; 21 and 22 a surface passivation film and a tantalum surface passivation film. In the structure described above, the NPN transistor in the region 7 is formed in the relatively thicker epitaxial layer 5 having 8 to 10 µm in thickness to maintain high voltage proof against the power source voltage which is determined by an energy amount supplied to the electro-thermal converter element 11. As described above, the experimental structure provides the PMOS transistor in the epitaxial growth layer 5, a thickness of which is determined by maintaining high voltage proof of the NPN transistor, thereby requiring an extremely large surface area as the region 9 where the PMOS transistor is formed as compared to the region 8 where the NMOS transistor is formed. Contrary to the above, the structure according to the present invention provides the PMOS transistor and the NMOS transistor in the N well and the P well diffusion layers, respectively, thereby keeping the respective MOS transistors with nearly same size. The shift register, the latch circuit and the logic gate which are constituted in the substrate require only the voltage proof against the power source voltage, for example 5V or less than 5V, which enables the operation of the CMOS structure circuit so that a gap length between each of the diffusion layers which constitute MOS transistors can be designed in a manner to have a permissible range in order to satisfy the above condition. When a process technology enabling to obtain a further fine structure is employed to constitute each components, the shift register, the latch circuit and the logic gate can be realized with high density. The typical structure and principle according to the present invention are preferably employed, for example, in recording heads of the kind disclosed in U.S. Patent Nos. 4,723,129 and 4,740,796. Even though the recording head according to the present invention is applicable to either "on-demand type" or "a continuous type", it is more effective to be applied to the on-demand type because at least one driving signal, which causes an abrupt temperature elevation to exceed the core boiling temperature corresponding to each recording information, is applied to the electro-thermal converter which is disposed corresponding to both the sheet preserving ink and the ink flow path in order to have the electro-thermal converter generated the heat energy. Accordingly, a film boiling occurs at the heat working surface of the recording head resulting to form bubbles in the ink which correspond to each of the driving signals. The ink are emitted through the orifice in accordance with growth and shrinkage of the bubbles to form at least one droplet. The driving signal is preferably supplied in a form of pulse trains so that the growth and shrinkage of the bubbles can be adequately performed in response to the driving signal to accomplish an excellent ink emission with particular high accessibility. The driving signal having a pulse shape can be utilized as that disclosed in the U.S. Patent Nos. 4,463,359 and 4,345,262. Further excellent recording can be achieved by employing conditions disclosed in the U.S. Patent No. 4,313,124, the invention of which relates to a temperature elevation rate of the heat working surface set forth above. The present invention is not limited to structures of a recording head, having a straight liquid flow path or a right angle liquid flow path, but is to include a structure in which the heat working portion is located at the bending region disclosed in U.S. Patent Nos. 4,558,333 and 4,459,600. In addition, the present invention is also effective if employed either structure that a common slit of plural electro-thermal converters serves as the orifice disclosed in the Japanese Laid-Open Patent Application No. 59-123670 or that an opening to absorb a pressure wave of heat energy is faced relative to the emitting portion disclosed in the Japanese Laid-Open Patent Application No. 59-138461. In other words, the recording head, whatever shape through it is, according to the present invention can surely and effectively record. The present invention is also effectively applicable to a full line type recording head having a length which corresponds to the maximum width of a recording medium of the recording device. This kind of recording heads can be constructed such that the length is satisfied either by combination of the plural recording heads or by integrally constituted as one recording head. Fig. 6A shows an example of the recording head, wherein the numeral 101 represents the head substrate illustrated in Fig. 5B; the numeral 102 an ink tank; the numeral 103 a member having a plurality of ink emitting orifices 104; and the numeral 105 an ink supplying pipe. In addition, besides the serial type recording head set forth above, other types of recording heads, i.e., one that is fixed to the body of the recording device, one that is an interchangeable chip type enabling an electrical connection with the body of the device when installed into the body of the device and enabling the ink supply from the body of the device, or one that is a cartridge type incorporating the ink tank integrally into the recording head can be effectively applied to the present invention. Fig. 6B shows a recording device, wherein the numeral 11 represents a recording medium; the numeral 112 head carrying means; and the numeral 113 a control circuit. In addition, projection recovery means 110 or preliminary supplemental means for the recording head 100 can be supplemented to stabilize more the advantage of the present invention. More concretely, capping means, pressing or absorbing means, preliminary heating means constituted by either the electro-thermal converter, other thermal elements or the combination thereof, and preliminary emission means for use of other emitting excepting the recording can be supplemented to the recording head. There can be various modifications as to the type and the number of the recording head. For example, one single recording head corresponding to a single color ink or a plurality of recording heads corresponding to a plurality of inks which reveal different recording colors and densities can be employed. In other words, the recording device can be realized not only by employing a single recording head having a single color mode which reveals a single principal color, like black, but also by employing either a recording head integrally incorporated into the body of the device or a combination of a plurality of the recording head. The present invention is effectively applied to the recording device incorporating at least one recording mode selected from a plural color mode revealing different multiple colors and a full color mode realized by mixing multiple colors. In addition, although above described embodiment according to the present invention employs liquid ink, the ink is not restricted to be liquid but can be utilized the ink which stays solid less than a room temperature and softens or becomes liquidized at the room temperature. The ink can be also utilized which is liquidized when applied a recording signal because the ink utilized under an ink-jet system is usually controlled in temperature into a range of 30°C to 70°C to keep the viscosity in a stabilized emission range. The ink, which stays normally as it is a solid state and a liquid state when heated, can be utilized in order to positively have the heat elevation energy utilized as the energy to change the ink from a solid state to a liquid state or in order to prevent evaporation of the ink. In any event, the present invention is applicable in case that is utilized the ink liquidized when applied heat energy such that liquid state ink is projected when a recording signal accompanying heat energy is applied solid state ink or that liquid state ink is solidified when it reaches to a recording medium. Above described ink, which is disclosed in the Japanese Laid-Open Patent Application No. 54-56847 or 60-71260, can be faced relative to the electro-thermal converter with preserved in either liquid state or solid state at a recess or a penetrated hole of porous sheet material. The film boiling method described above is most effectively applied to the ink described above in accordance with the present invention. Various modifications can be considered as the ink-jet type recording device to which the present invention is applied. Examples are a video signal output terminal for information processing devices such as computers, a copier in combination with readers, and a facsimile device having a transceiver function. As described above, since the present invention provides both the N type N well diffusion layer and the P type P well diffusion layer in the N type epitaxial layer which is usually utilized to form the bipolar NPN transistor and incorporates the PMOS and NMOS transistors into the N well layer and the P well layer, respectively, the formation regions of both MOS transistors can be approximately equal each other thereby improving the array density of the shift register, the latch circuit and the logic gate. Therefore, the array density of functional elements for a driving system can be well improved to cope with the multi-bit trend of the electro-thermal converter element accompanying high recording density.

Claims: A monolithic integrated circuit (101) suitable for an ink-jet type recording head (109), said circuit comprising: a semiconductor substrate (1); an electro-thermal converter element (11;41), for generating thermal energy to emit ink from an orifice (104) in a recording head, integral with said substrate; and a driver circuit (7-9; 41-53), for driving said element, disposed on said substrate; which monolithic integrated circuit is characterised in that said driver circuit comprises: a bipolar drive transistor (7;42,43) connected to said element; and a CMOS logic gate (8,9;44) composed of an NMOS transistor (8) and a PMOS transistor (9) disposed on said substrate, for controlling the operation of said bipolar drive transistor; wherein said substrate is of p-type semiconductor, an N - -type semiconductor epitaxial layer (4) is provided on the surface of said substrate, N + -type and P + -type semiconductor buried layers (2,3), respectively, are provided beneath said PMOS transistor and said NMOS transistor, at the interface of said epitaxial layer and said substrate, and said NMOS and PMOS transistors are defined in a respective P-type semiconductor well diffusion (4) and a respective N-type semiconductor well diffusion (6) formed in said epitaxial layer, which well diffusions (4,6) reach and form contact with said P + -type and N + -type semiconductor buried layers (3,2), respectively. A monolithic integrated circuit according to claim 1 wherein said driver circuit (41-53) also includes, integral with said substrate, a shift register (46) and a latch gate (45) for operating said CMOS logic gate (44). A monolithic integrated circuit according to either of claims 1 or 2 wherein an electrothermal converter element (11;41) and a driver circuit (7-9;41-53), as specified, are provided for each one of a plurality of orifices (104) of an ink-jet type recording head (100), these elements and driver circuits being integrated in parallel on the same said semiconductor substrate (1). An ink-jet type recording head having a plurality of ink orifices (104), said head comprising said monolithic integrated circuit (101) of claim 3 arranged for emitting ink from the respective ink orifices.

Inventors: FURUKAWA TATSUO, ISHINAGA HIROYUKI, IZUMIDA MASAAKI, MARU HIROYUKI, MISUMI YOSHINORI, MUROOKA FUMIO, SHIMODA JUNJI, FURUKAWA, TATSUO, ISHINAGA, HIROYUKI, IZUMIDA, MASAAKI, MARU, HIROYUKI, MISUMI, YOSHINORI, MUROOKA, FUMIO, SHIMODA, JUNJI, FURUKAWA, TATSUO, C/O CANON KABUSHIKI KAISHA, ISHINAGA, HIROYUKI, C/O CANON KABUSHIKI KAISHA, IZUMIDA, MASAAKI, C/O CANON KABUSHIKI KAISHA, MARU, HIROYUKI, C/O CANON KABUSHIKI KAISHA, Misumi, Yoshinori, c/o Canon Kabushiki Kaisha, MUROOKA, FUMIO, C/O CANON KABUSHIKI KAISHA, Shimoda, Junji, c/o CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: B41J2
IPC codes: H01L21, B41J2, H01L27