High voltage input pad protection circuitry

Abstract: An electrostatic discharge (ESD) protection device (18) for protecting a high voltage operating circuit having a high voltage input terminal (12) is disclosed. The ESD protection circuit has a substrate (20), a first diffusion region (68) formed in the substrate connected to the high voltage input terminal, a second diffusion region (70) formed in the substrate connected to ground, a field oxide layer (66) over the substrate having a thickened region (66a) extending into the substrate between the first and second diffusion regions, and a drift region (78) formed in the substrate and located between the first diffusion region and the thickened field oxide layer. These regions are so arranged to move the point of avalanche breakdown away from the first diffusion/field oxide interface, so that the avalanche breakdown voltage is lower than that of the protected circuit while simultaneously preventing avalanche included bipolar feedback in the protection device.

Description: The present invention relates generally to electrostatic discharge (ESD) protection of integrated circuits. More particularly, the invention relates to ESD protection of high voltage power (>25V) input terminals, especially for applications where power devices are used in conjunction with printing elements to form a customer replacable unit such as a printhead or print cartridge which will be handled in a wide variety of environments that are hostile to semiconductor components. Semiconductor devices have become increasingly susceptible to damage by ESD events as the scale of the devices has decreased. The increased static sensitivity has been addressed by on chip protection circuits which protect inputs to about 2 to 4 kV [as measured by the Human Body Model (HBM)] in conjunction with stringent circuit handling precautions. In a consumer environment, such as an office, ESD events of up to 10KV (HBM) are not uncommon. Such high-level ESD events are easily sufficient to destroy normal circuit components. In electronic devices, such as thermal ink jet printers or the like, which are designed to have easily replaceable electronic modules for on-site repair, high ESD hardness is necessary in order to prevent the replacement modules from being damaged as (or even before) they are installed in the electronic device. U. S. Patents 4,947,192 and 5,075,250, disclose methods for integrating printing elements with control logic and power transistors switches. Integration of control logic dramatically reduces the number of connections which need to be made to the printhead, but adds the requirement of robust static protection. Numerous conventional systems are known for ESD protection of semiconductor and MOS devices. The inputs of MOS integrated circuits are capacitors whose two electrodes are the MOS transistor device channel and the gate electrode material, usually polysilicon. The two capacitor electrodes are separated by silicon dioxide, which is usually grown on the device channel by high temperature oxidation processes. The MOS transistors use a thin silicon dioxide gate insulator to achieve high performance, and this thin oxide is susceptable to catastrophic, irreversable breakdown if the voltage across the dielectric is raised above 20 to 100 volts, depending on device fabrication details. In general, such circuits use monolithically integrated protective transistors built into the semiconductor circuit to protect the gates of the devices. These protective transistors are arranged to allow a high voltage static discharge transient to pass to ground prior to reaching the protected circuit. For example, U.S. Patent 4,990,984 to discloses a conventional protective transistor ESD protection device for an integrated circuit. Such systems have at least three disadvantages which prevent them from being applied as protection of high voltage power input terminals. First, the conventional protective transistor for the circuit has only a small current carrying capacity, so that ESD surges which are encountered in the office environment will overwhelm the protective transistor, allowing a part of the ESD surge to reach the protected circuit or causing failure of the ESD protection circuit itself. Second, conventional protective transistors are designed to protect logic input terminals, which have a low current signal input voltage of 5V. Accordingly, these protective transistors are designed to break down at 15 to 25V. Advanced VLSI technologies utilize reduced gate dielectric thickness and CMOS fabrication, so the industry trend is to reduce the voltage at which ESD input protection structures breakdown, since the gate dielectric becomes more susceptable to breakdown as it becomes thinner. Such conventional ESD protective circuits are worthless when attempting to protect high voltage (>25V) input terminals. Finally, protection circuits for logic input gates use diffused resistors which have values of several hundred ohms to slow ESD current transients. Such high impedence is not useful for power input pad applications. In U.S. Patents Nos. 5,027,252 and 4,616,243, the first disadvantage of the conventional ESD protective transistors for semiconductor circuit gates is addressed by providing a multiple stage protective circuit. US Patent No. 5 027 252 describes use of a three stage protection circuit. The first stage is a punch through device under field oxide, and is connected directly to the input pad. The second stage is isolated from the first stage by a current limiting diffused resistor and is a thick oxide device with its gate tied to the input pad. The diffused resistor is situated between the gate connection and the drain, and the device source is tied to ground. A second diffused resistor is then followed by the third stage, where a conventional n-channel device with its gate and source tied to ground is used to discharge any remaining voltage to ground. US Patent No. 4 616 243 describes techniques for protecting p-well CMOS logic inputs. A polysilicon current limiting resistor is connected to the input pad and is followed by an n-channel device which is placed in a p-well that is specifically tailored to breakdown before normal p-well transistors. The breakdown voltage is lowered by raising the doping level of the protective transistor p-well, diffusing the p-well to a shallower depth, or adding diffused features which reduce p-well breakdown by other methods. However, use of a punch-through type protection transistor with a high voltage input terminal for a MOS power driver is not practical for several reasons. First, the approach is limited to CMOS-type circuitry, while power MOS devices may employ either CMOS or NMOS architecture and circuitry. Secondly, all the proposed input circuits utilize diffused or polysilicon resistors with substantial attendent input impedence, and which would therefore seriously limit the ability of the input connection to supply a tightly regulated voltage over the range of current flows typically required for power applications. Finally, these input protection circuits breakdown at voltages which are far below that required for the present applications, as is shown in Figure 4 of U. S. Patent 4,616,243, where breakdown occurs between 10 and 15 Volts. Document EP-A-0 058 557 discloses a lateral bipolar transistor for protecting an element of a semiconductor device. It is an object of the present invention to provide an improved ESD protection circuit for high voltage input terminals. A semiconductor device according to the present invention is defined in claim 1. Figure 1 is a schematic view of a circuit containing an ESD protection device; Figure 2 is a plan view of a MOS power driver of the circuit of Figure 1; Figure 3 is a cross sectional view through plane 3-3 of Figure 2; Figure 4 is a cross sectional view of a power MOS driver through area 4-4 of Fig. 3 undergoing parasitic bipolar breakdown; Figure 5 is a flowchart showing the operation of the power MOS driver of Figure 2 through 4 during an ESD event; Figure 6a and 6b are plan views of the ESD protection device not covered by the present invention; Figures 6c and 6d are cross sectional views of an ESD protection device taken through the plane 6b,c-6b,c of Figure 6a but showing alternative metallization configurations; Figure 7 is a graph of the operation of a device; and Figure 8 is a graph of the ESD hardness of high voltage and power MOS drains as a function of spacing between metal vias and the breakdown region. Referring to Figures 1-3, a semiconductor or MOS integrated circuit 10 comprises a high voltage input terminal 12 and input impedance 16, a number of semiconductor circuit elements 14 comprising the protected circuit and an electrostatic discharge (ESD) protection device 18. The input impedance 16 represents the various parasitic resistances arising from the input terminal and the input line, and, in the illustrated arrangement, has a resistance less than 10Ω. There are a plurality of blocks of 2 or more circuit elements 14, each comprising a load 14a, such as a resistive heater element, and a power MOS driver 14b. Other alternative arrangements could utilize bipolar devices and have alternative configurations and combinations of circuit elements. In the illustrated arrangement, the load 14a is a 150 Ω resistive heating element for a thermal ink jet printer printhead. In a thermal ink jet printhead, in general, the heaters 14a of the individual power MOS drivers 14b must be heated the same amount independent of whether a particular resistor 14a is being used alone or in conjunction with other resistors 14a. That is, it is important that the same heat energy, within a few percent, be delivered whether one or more heaters are simultaneously activated by control circuitry 19. As each resistive heating element 14a is approximately 150 Ω, the lumped resistance of the circuit of Figure 1 is approximately 40 Ω. Accordingly, the input impedance 16 must be less than 100 Ω, is desirably less than 10 Ω and is preferably less than 1 Ω. In the case of a 300 spi thermal ink jet printer, the circuit elements 14 operate at a voltage of 20V-100V and a current of 200mA-800mA. In printers providing densities up to 1200 spi, the circuit elements will operate at a lower current. For example it is anticipated that a 800-1200 spi printhead will operate on a current on the order of 50 mA. While it is recognized that other printers may not require the high current sourcing of the illustrated arrangement, it is obvious that the resistance 16 of the input 12 in a power circuit must be kept low. A thermal ink jet printer may contain many blocks of circuit elements 14, such as 32 blocks (for 128 jet printheads) or 48 blocks (for 192 jet printheads). A 384 jet printhead (96 blocks) which is able to fire up to 8 circuit elements 14 at once has also been built. The circuit elements 14 are connected in parallel between the parasitic input impedance 16 and ground, while the impedance 16 is connected in serial to input pad 12. Within each circuit element 14, the load 14a is connected in series with the drain of the power MOS driver 14b. The source of the power MOS driver 14b is connected to ground and the gate of power MOS driver 14b is connected to a control circuit 19 (not shown in detail). The ESD protection device 18 is also connected in parallel with the circuit elements 14 between the impedance 16 and ground. The ESD protection device 18 is a thick oxide transistor, as shown in Figures 6a and 6b. Electrostatic discharge (ESD) events occur when a person's body becomes highly charged and the individual then touches a grounded object and discharges. The discharge is very similar to the discharge of a capacitor. It can be anticipated that ESD events depend on many variables. Electrical engineers have studied ESD events and developed a model called the "Human Body Model (HBM)". An HBM ESD event is simulated by discharging a 100 pF capacitor through 1.5 kΩ resistance, and the time constant for discharge is about 150 nsec. Therefore, the ESD event is of short duration and high current flow. ESD testing of a device would typically consist of charging up the capacitor to increasingly higher voltages and discharging it through the device until the device fails. Figures 2 and 3 show a plan and sectional view of the layout of one power MOS driver of a 300 spot per inch (SPI) thermal ink jet printhead. In a thermal ink jet printhead, and in most integrated circuit power devices, a high transistor packing density is desirable in order to minimize the chip area consumed. Therefore, the aluminum drain contacts 34 must be made close to the drift region 25, as shown in Figures 2 and 3. As shown in Figure 2, the space in between a via 34 and the gate 26 is only 7 µm. In higher resolution printheads (e.g. 400 spi), the spacing will be even closer. In order to get the most transconductance in a given chip surface area, it is common in most power MOS designs to place the vias 34 next to an active area 26. As a result, if a power MOS device undergoes an electrostatic discharge event, an ESD-induced avalanche breakdown and ensueing high current flow will occur near the metal contacts. When such a breakdown event occurs, the aluminum-silicon eutectic temperature of 575°C is reached at the contact, and aluminum will form a eutectic alloy through the n + diffusion 24 and contact the substrate region 20, thereby shorting out the drain. Figures 4 and 5 illustrate the breakdown mechanism. The breakdown mechanism is the same for both the power MOS drivers 14b and the ESD protection device 18. In an ESD event, avalanche breakdown of the drain junction caused by the ESD event will supply the initial carriers (i.e. turning the device "ON") necessary to start the feedback loop. As shown in Figure 4, during the ESD event, the drain 24, which is connected to the high voltage input pad 12 by metallization layer 30 is biased at a high voltage. The high voltage at the drain 24 depletes carriers in the drift region 25 and in the substrate region 20. The depleted boundary regions 45 are also shown. A high electric field exists at the left edge of the drift layer 25. When the field exceeds the breakdown strength of silicon, avalanche breakdown begins. Electron-hole pairs are created at the edge of the drift region and electrons enter the drain 24. Once in the substrate, the holes 43 are drawn to ground, creating a substrate hole current. Due to the resistance R sub of the substrate, a potential appears between the substrate region 20 in the vicinity of the device and ground. This causes substrate region 20 to become forward-biased with respect to the source 22, thereby injecting (emitting) electrons 47 from the source into the substrate. These electrons then flow from the source to the drain through the substrate region 20, are accelerated by a large electric field, and are collected in the drift region 25, thereby generating a bipolar conduction positive feedback loop. The sequence of steps in the feed back loop is shown in Figure 5. The n-p-n parasitic bipolar element 49 is schematically shown. The positive feedback loop will continue, heating the device as it runs, until the drain is shorted out, destroying the device. The tight packing of the power MOS devices require contacts 34 between metal 30 and diffusion 24 to be close to the avalanche region. Heat can flow from the avalanche region to the contacts during the ESD event. Figure 6a refers to the ESD protection device 18. Likewise, in the ESD protection device 18, the positive feedback loop will form between the first and second diffusion regions 68 and 70, the channel stop region 72a and the substrate 60. The bipolar feedback loop is suppressed in the power MOS circuit by locating the input protection device 18 in parallel with the power MOS drivers 14b. The protection device 18 is designed to have a lower breakdown point so that avalanche breakdown in the power MOS drivers is prevented. The ESD protection device 18 is also designed to survive the bipolar feedback loop by placing the high voltage input pad metallization via contact 30 further away from the avalanche region to prevent eutectic alloying and junction spiking from occurring. The structure of the protection device 18 is shown in Figures 6a-6c. In Figure 6a, the input terminal 62 of the metallization layer has an input contact pad 62a and a lead region 62b connected to the protected circuit 14. Region 64 of the metallization layer connects the three independent lobes of the protection circuit 18 to ground. Each lobe of the protection circuit 18 is an independent protection device for protecting multiple blocks of 2 or more circuits 14. Figure 6b shows a top view of the input terminal 12 and the protection device of one lobe of the protection circuit 18. Figures 6c and 6d show the sectional view through one lobe on the line(6b,c - 6b,c) of Figure 6a. As shown in Figure 6c, the substrate region 20 (which is a p - region) has a first n + diffusion region 68 connected to the input terminal pad 62a and a second n + diffusion region 70 connected to the ground metallization layer 64 through vias 80. Lying atop the first and second n + diffusion regions 68 and 70 is an oxide layer 66 (including regions 66a and 66b) and a phosphorosilicate glass (PSG) layer 74. The first n + diffusion region 68 is electrically isolated from the second n + diffusion region 70 by field oxide 66a and a channel stop 72 of the substrate 20. Although the diffusion region 70 is shown located in the p - region 20 of the substrate, it could be located in the substrate adjacent that region. As shown in Figure 6c, the oxide layer 66 has the first or source-drain reoxidized regions 66b when lying over the first or second n + diffusion regions 68 and 70 and has the second or field oxide regions 66a extending over the substrate 20. The regions 66a of oxide layer 66 are located to the left of first n + diffusion region 68, to the right of the second n + diffusion region 70, and in the region 72 lying between the first and second n + diffusion regions 68 and 70. In the substrate below at least the center thick field oxide layer 66a, a p region 72 is formed in the substrate region 20 as a channel stop region. Such p channel stop regions 72 may also be formed in the substrate below the left and right thickened field oxide regions 66a. The central p channel stop region 72 is separated from the first n + diffusion region 68 by a first n - drift region 78. Likewise, the leftmost p channel stop region 72 may be separated from the first n + diffusion region 68 by a second n - drift region 76. In contrast, the second n + diffusion region 70 abuts the central p channel stop region 72 and the rightmost p channel stop region 72. The spacing between the aluminum contact 80 and avalanche breakdown region 78a is shown in Figure 6c as dimension "z". Figure 8 shows the ESD hardness of the ESD protection device as a function of "z". Power MOS ESD hardness is also shown in Figure 8. It can be seen that the close via spacing in the power MOS device results in low ESD hardness, while the large via spacing in the ESD protection device provides high ESD hardness. Because the ESD protection device takes up small area, there is little penalty for the via spacing used, while there would be a large penalty paid for such a large spacing in the power MOS devices. The power MOS device(s) 14b to be protected have drains 24 made of n + diffusion. High drain breakdown is achieved by spacing the drain 24 away from the polysilicon gate electrodes 26 by a lightly doped drift region 25 (Figure 4). The drift region 25 abuts the silicon region below the gate electrode 26, where a p-type threshold adjustment implant 36 is located. The source 22 is also constructed of n + diffusion and surrounds the drain region 24. The power MOS device described here would be a "pull down" device and the source is therefore always at ground. Alternative configurations would have the same drain structure but alternative source configurations. An offset gate lateral power MOS is used here for illustration, but the concept is more generally applicable to a variety of power device designs such as DMOS, bipolar, and others. The objective is to assure that the power MOS devices 14b breakdown at a higher voltage than the ESD protection circuitry 18. This is assured by using the same n - doping for the drift layer 25 of the power MOS device 14b as for the drift layer 78 of the ESD protection circuitry 18, by making the drift layer 25 of the power MOS driver 14b have a lateral dimension equal to or greater than the lateral dimension of the drift layer 78 of the ESD circuitry 18 and by abutting the drift layer 78 of the ESD protection device 18 to a more heavily doped p-type region than the threshold adjustment doping 36 which is present in the power MOS devices. The drift region 78 of the ESD protection device 18 abuts the channel stop p-type region 72 and also the threshold adjustment implant 36 in the power MOS driver 14b. In a second arrangement, the general power MOS driver circuit is in particular a power NMOS driver circuit which is suitable for integration with an NMOS logic process architecture. In this circuit, the n - drift region 78 of the protection device 18 has a masked n-type depletion implant added to it. The depletion implant converts logic devices to be normally "ON" instead of normally "OFF". By adding the depletion implant only to the n - drift region 78, the effective drift layer becomes more highly n-type in the ESD protection circuit 18 only. This assures that the ESD protection device 18 will breakdown prior to the power MOS drivers 14b. In that second arrangement, the depletion implant extends across the entire lateral dimension of the n - drift region 78 between the first n + diffusion region 68 and the central p + channel stop region 72. In a third arrangement, the depletion implant extends only partially across the via dimension of the n - drift region 78. In this case, depletion doping is added to the half of the drift layer 78 adjacent to diffusion 68. An added advantage of the second and third arrangements is that the depletion implant can be added without any additional cost or processing time, because a depletion implant level mask is already required by the normal chip manufacturing process. Since the circuit itself requires a depletion processing step, the depletion implant can be added merely for the cost of altering the mask. In a fourth arrangement, a lower resistance n - drift region is substituted in the ESD circuit 18 for the original n - drift region 78 while the relatively higher original resistance of the drift layer 25 of the power MOS devices 14b is retained. However, this fourth arrangement has the disadvantage of requiring an additional mask and processing step, which are necessary to create the lower resistance drift region. In a fifth arrangement, the well-technology described in the previously-mentioned US Patents 5 027 252 and 4 616 243 can be incorporated into the ESD protective circuit 18 when CMOS-type power MOS drivers are used. However, that arrangement suffers the same problems as the fourth arrangement, in that additional masks and processing steps will be required. Additional masks and processing steps will undesirably raise both the cost and the complexity of chip manufacturing. In a sixth arrangement, the lateral dimension of the n - drift region 78 of the ESD protective circuit 18, represented by the dimension X of Figure 6c, is made shorter than the lateral dimension of the n - drift region 25 of the power MOS driver, as shown in Figure 3. Because power MOS drivers such as the one shown in Figure 3 operate at a high voltage, the n - drift layer 25 is several microns long. Therefore it is simple to make the n - drift region 78 of the protective circuit 18 several microns shorter. For example, in the power MOS driver, the n - drift layer 25 can be made 4-5 µm long, while the n - drift layer 78 of the protection device 18 can be made 3-4 µm. When the drift layer is made shorter, the potential gradient through it is higher and the avalanche breakdown point is lower. The drift region 78 may have a sheet resistance of at least 1 kohm/square and width of at least two microns and may surround the diffusion region 68 ( which may be degenerately doped) at least laterally. In a seventh arrangement, the metallization layer 62a, which connects the first n + diffusion region 68 to the input pad 62 is extended to lie over the n - drift layer 78. As shown in Figure 6d, this extension or field plate 64a can be easily added during the normal metallization step by simply altering the metallization layer mask. Similarly, as shown in Figure 6c, the field plate 64a can be attached to the ground connection layer 64 instead of the input terminal pad 62a. When the added metallization area 64a is connected to the input terminal pad 62a, the drift layer will accumulate and cause breakdown at a lower voltage. Accumulation of the drift layer will cause the ESD protection device to breakdown at a lower voltage, but has the undesirable effect of attracting hot electrons toward the SiO 2 interface. An alternative and preferable configuration is to repel hot electrons by attaching the field plate 64a to ground metallization 64. In an eighth arrangement, the n - drift region 78 is buried so that the peak n-type dopant concentration is below the surface level of the substrate 20. The effect of that is to move the avalanche breakdown point 78a away from the silicon-field oxide interface. Finally, a ninth arrangement, which is in accordance with the present invention uses a p + doping of the substrate to form the second diffusion region 70 instead of the n + doping used in the previous arrangements. By using a p + diffusion region 70, a Zener diode is formed rather than a bipolar transistor. As shown in Figure 7, the bipolar transistor follows the curve 102 as voltage rises above the breakdown point V A . The curve 102 is called a "snapback" curve and indicates that after breakdown, the bipolar transistor arrangements (1-8) described above have a reduced voltage drop across the protection circuit as current increases. A disadvantage of bipolar action is that the resultant ESD circuit may exhibit thermal runaway in a small region before other segments can conduct. This problem will occur, for example, if one of the three modules in 18 has a lower V A than the others. In contrast, while the Zener diode of the ninth arrangement has an identical breakdown point V A , it follows the curve 104. As the Zener diode form experiences no snapback, it is able to provide a more robust protection circuit than the bipolar transistor arrangements for the case where parasitic bipolar gain is nonuniform. However, the Zener diode requires another processing step to provide the p + doping. The p + layer may be available as a substrate contact. The ninth arrangement can be combined with any of the arrangements 3 to 8 described above to further improve the performance of the ninth arrangement.

Claims: A semiconductor device comprising an electrostatic discharge (ESD) protection device (18) including a Zener diode for protecting a power semiconductor device (14b) which is formed on a silicon substrate (20) and is connected to a high voltage terminal (12), wherein the ESD protection device is also formed on the substrate and is connected to the terminal in parallel to the power semiconductor device; and wherein the breakdown voltage of the power semiconductor device is greater than the breakdown voltage of the ESD protection device and the ESD hardness of the ESD protection device is greater than the ESD hardness of the power semiconductor device, said ESD protection device comprising: at least one lightly doped p region (20) in the substrate; an n + diffusion region (68) provided in the lightly doped p region and connected to the high voltage terminal; a p + diffusion region (70) provided in the lightly doped p region, or in the substrate adjacent the lightly doped p region, and connected to ground; a moderately doped p channel stop region (72) provided in the lightly doped p region between the n + diffusion region and the p + diffusion region and adjacent the p + diffusion region; and at least one n - drift region (78) located between the moderately doped p channel stop region and the n + diffusion region.

Inventors: HAWKINS WILLIAM G, HAWKINS, WILLIAM G.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1993
Main classification: H01L27
IPC codes: H01L27, H01L21