Method of rewriting data in EEPROM, and EEPROM card

Abstract: A memory card includes an S-RAM in addition to an EEPROM. When old data constituting part of data that has been recorded in the EEPROM is to be rewritten, the old data to be rewritten is read out of the EEPROM and applied to the S-RAM, where the old data is temporarily stored. The old data in the S-RAM is rewritten to new data, and the new data is applied to and written in the EEPROM. A comparator circuit determines whether all bits of the new data rewritten in the S-RAM and all bits of the new data written in the EEPROM coincide. If all bits coincide, this is verification that the changed data has been stored in the EEPROM correctly. Thus, the reliability with which data is rewritten in the EEPROM is improved.

Description: BACKGROUND OF THE INVENTION Field of the Invention: This invention relates to a method of rewriting data in an EEPROM (electrically erasable programmable read-only memory), as well as to an EEPROM card. Description of the Related Art: Memory cards of the type incorporating an S-RAM (static random-access memory) inside a case are disadvantageous in that battery back-up is required and the unit price per bit is high. Accordingly, the development of memory cards equipped with an EEPROM designed to eliminate these drawbacks is proceeding. Though a memory card having an internal EEPROM is advantageous in that battery back-up is unnecessary while the unit price per bit is low, the number of rewriting operations possible is on the order 10,000. In terms of reliability, therefore, a memory card of this type is inferior to the card having the internal S-RAM. From EP-A-0398654 which is the prior art from which the generic portions of claims 1 and 7 start, an apparatus for writing data into an EEPROM is known comprising an EEPROM having a plurality of storage areas for data, and a RAM for temporarily storing received data. The apparatus also comprises means for establishing a difference between data stored in a respective storage area of the EEPROM and corresponding data stored in the RAM, and for selectively updating data stored in the storage areas in the EEPROM in accordance with said corresponding data. Data for setting the operating configuration of the EEPROM and data for setting the operating configuration of the RAM are compared with one another. If the data of the EEPROM and the data of the RAM do not coincide, the data of the RAM is written into the EEPROM. From EP-A-0412039 a page printer including a print engine and a controller which includes a non-volatile memory having an EEPROM and a chip RAM is known wherein a microprocessor under programme control manages the placement of data in the EEPROM of the non-volatile memory. Said EEPROM and the associated chip RAM are structured to have a control block and a data storage portion. The control block includes pointers indicating the locations in the non-volatile memory where data is stored. If the data location becomes faulty, the value of the pointer to that location is changed so that the pointer points to a previously unused portion of the non-volatile memory. Account of the number of pages is written in a memory block, and this count is updated in accordance with the print by the printer. If a failure is detected in the memory block, the count is written in the next memory block. From EP-A-0 521 280 which is prior art in accordance with Article 54 (3) and (4) EPC, a memory card apparatus using EEPROMs in semi-conductor memories is known. Externally input data are temporarily recorded in a buffer memory and are subsequently written in the EEPROMs. Subsequently thereto, a verify processing is performed between the contents of the buffer memory and of the EEPROMs. Similarly, data read out from the EEPROMs are temporarily recorded in the buffer memory and are subsequently output to an external unit. This memory card apparatus is used for an electronic still camera which is designed to convert a photographed optical image of an object to be photographed into digital image data and record the data in a semiconductor memory. SUMMARY OF THE INVENTION It is the object of the invention to provide a reliable method with which data can be rewritten in an EEPROM, and an EEPROM card in which data can be reliably rewritten. According to the method, the object is attained by the features of claim 1. As to the EEPROM card the object is attained by the features of claim 6. Preferred embodiments of the invention are subject matter of the respective dependent claims. In accordance with the invention, the first data containing the old data to be rewritten are read out of the EEPROM and written into the RAM. The old data in the first data that has been written in the RAM are rewritten into new data, whereby second data is produced. The second data are written in the EEPROM. In an embodiment of the invention, an area of the EEPROM from which the first data are read out and an area of the EEPROM in which the second data are written are the same area. In one embodiment of the invention, when it is determined that the second data in the RAM do not coincide with the second data in the EEPROM, the second data are written in another area of the EEPROM. It is again determined whether the second data in the RAM coincide with the second data written in the other area of the EEPROM. In another embodiment of the invention, when it is determined that the second data in the RAM do not coincide with the second data in the EEPROM, the writing of the second data in the EEPROM is performed again a prescribed plurality of times until it is determined that the second data in the RAM coincide with the second data in the EEPROM. When a determination of coincidence is not obtained even when the writing of the second data in the above-mentioned area of the EEPROM is performed again the prescribed plurality of times, the second data are written in the other area of the EEPROM. In accordance with the present invention, a check is performed at all times to determine whether new data (the second data) following a change have been written in the EEPROM correctly, and therefore the reliability of the EEPROM is improved. When it is determined that writing has not been performed correctly, the writing of the second data in the same area or another area is performed again. As a result, the reliability with which data are rewritten in the EEPROM is improved. Since data in the first data other than the old data that are to be rewritten is preserved by being written in the RAM, loss of data caused by a data writing failure or by a defect in the EEPROM is prevented. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating the electrical configuration of a memory card; Fig. 2 is block diagram showing the configuration of a sequence control circuit; Fig. 3 is a block diagram showing the configuration of an address converter circuit; Figs. 4a and 4b are diagrams showing examples of a logical cluster area and examples of a physical cluster area, respectively; Figs. 5a, 6a, 7a, 8a and 9a are diagrams showing the manner in which data in the logical cluster area change; and Figs. 5b, 6b, 7b, 8b and 9b are diagrams showing the manner in which data in the physical cluster area change. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 1, which illustrates an embodiment of the present invention, is a block diagram showing the electrical circuit configuration incorporated within the case of a memory card. A memory card includes a sequence control circuit 10, by which the overall operation of the card is supervised, an address converter circuit 20 for generating addresses, an S-RAM 30, and an EEPROM 40 for storing digital data. The S-RAM 30 is used in order to perform an operation through which data are updated. Data to be written in the EEPROM 40 are stored temporarily in the S-RAM 30. In order to verify whether data have been written in the EEPROM 40 with certainty, data that have been stored temporarily in the S-RAM 30 are compared with data that have been written in the EEPROM 40. To this end, the memory card contains a comparator circuit 50. If the data stored temporarily in the S-RAM 30 coincide with the data written in the EEPROM 40, the comparator circuit 50 outputs a coincidence signal EQ, after which the data stored in the S-RAM 30 are erased. Applied to the sequence control circuit 10 from an electronic device (such as an electronic still-video camera), in which the memory card is removably loaded, are a program supply voltage VPP, a card-enable signal CE, image data (data to be written or read) or address data (which designates the location for the writing or reading of the data) D0 ∼ D7, a data identifying signal A/D that represents whether the data D0 ∼ D7 are image data or address data, a write/read signal R/W that represents the writing of image data to the memory card or the reading of image data from the memory card, and a bus clock pulse BCK. These signals arrive from the electronic device through a connector. The data D0 ∼ D7 are applied to the S-RAM 30 as well. The sequence control circuit 10 outputs a status signal RDY/BSY, which represents whether the memory card is in a state (READY) in which it is capable of sending and receiving image data or address data or in a state (BUSY) in which it is incapable of sending and receiving image data or address data. The electronic device in which the memory card has been loaded is provided with the signal RDY/BSY via the connector. Fig. 2 illustrates an example of the construction of the sequence control circuit 10. As shown in Fig. 2, the sequence control circuit 10 includes a command control circuit 11 and an address register 12. The above-mentioned data identifying signal A/D, write/read signal R/W and bus clock pulse BCK are fed into the command control circuit 11, which outputs a chip select signal CS, a memory read signal RD and a memory write signal WR. The chip select signal CS, memory read signal RD and memory write signal WR are outputted from the sequence control circuit 10 and applied to the EEPROM 40 and S-RAM 30. The command control circuit 11 outputs the status signal RDY/BSY. The command control circuit 11 also outputs a latch clock pulse, which is applied to the address register 12. The latter is provided with the data D0 ∼ D7. A logical cluster address that designates the address of a logical cluster area contained in the address converter circuit 20 is generated within the address register 12. The sequence control circuit 10 and address converter circuit 20 send and receive cluster address data to and from each other. The cluster address data include the address of a logical cluster that designates a cluster in which a data writing error has occurred, the address of a last-written cluster in which writing has been performed last, and the address of a write cluster (over-written cluster address) in which over-writing has been performed. Fig. 3 illustrates an example of the construction of the address converter circuit 20. As shown in Fig. 3, a memory contained in the address converter circuit 20 is provided with a logical cluster area 21. As shown in Fig. 4a, the logical cluster area 21 stores, in correspondence with logical cluster addresses, the physical cluster addresses designated by these logical cluster addresses. When a logical cluster address is applied, the physical cluster address designated by this logical cluster address is read out of the logical cluster area 21 and delivered as an output. This physical cluster address is applied to the EEPROM 40. When it is determined whether the data that have been stored in the S-RAM 30 coincide with the data that have been written in the EEPROM 40, these items of data are read out of the S-RAM 30 and EEPROM 40 and applied to the comparator circuit 50, as set forth above. The comparator circuit 50 compares these items of data and outputs the coincidence signal EQ when the two items of data coincide. The coincidence signal EQ is applied to the sequence control circuit 10. Figs. 4a through 9b schematically represent the cluster areas. Figs. 4a, 5a, 6a, 7a, 8a and 9a represent the logical cluster area provided in the address converter circuit 20, and Figs. 4b, 5b, 6b, 7b, 8b and 9b represent the physical cluster area provided in the EEPROM 40. The term "cluster" refers to a unit of data written to or read from the memory. The rewriting of data is carried out one cluster at a time. In terms of image data, compressed image data that represents one frame of an image is an amount of data equivalent to one cluster or several clusters. The term "physical cluster area" refers to an area in which data is actually stored in the EEPROM 40, and the term "physical cluster address" refers to an address of a location at which data is stored. The term "logical cluster area" refers to an area used in order to manage the physical cluster addresses. As illustrated in Fig. 4a, the logical cluster area stores the physical cluster addresses in correspondence with logical cluster addresses ad1 ∼ ad8 of this area. In Fig. 4a, physical cluster addresses have not yet been written (i.e., the data has been initialized to all "0"s). The address converter circuit 20 is further provided with an area for storing a last-written physical cluster address and an over-written logical cluster address. As shown in Fig. 4b, the physical cluster area stores one cluster of data, for every address, in correspondence with physical cluster addresses AD1 ∼ AD12. In Fig. 4b, data have not yet been written and the area is in a "blank state" (all "0"s). Addresses up to ad8 are shown with regard to the logical cluster area and up to AD12 with regard to the physical cluster area. However, it goes without saying that these areas may be provided with more storage locations as the need arises. When the READY signal is outputted by the sequence control circuit 10 and the writing of data in the EEPROM 40 is performed, the image data D0 ∼ D7 is applied to the memory card. The image data D0 ∼ D7 is applied to the S-RAM 30 and, via the S-RAM 30, to the EEPROM 40. The write/read signal R/W representing the writing operation is applied to the sequence control circuit 10. On the basis of this signal, the sequence control circuit 10 outputs the memory write signal WR, which is applied to the S-RAM 30 and EEPROM 40. As a result, the image data is stored in the S-RAM 30. Furthermore, the sequence control circuit 10 outputs logical cluster addresses, which are applied to the address converter circuit 20 and the S-RAM 30. As a result of applying the logical cluster addresses to the S-RAM 30, that image data, which have been stored in the S-RAM 30, designated by the logical cluster addresses are applied to the EEPROM 40. The logical cluster addresses are applied to the address converter circuit 20 and, as shown in Fig. 5a, physical cluster addresses are stored in the logical cluster area. These physical cluster addresses are applied to the EEPROM 40. As a result, the image data provided by the S-RAM 30 are stored in the physical cluster area designated by the physical cluster addresses of the logical cluster area. This state is illustrated in Fig. 5b. Data A 1 , B 1 , C 1 and D 1 is contained in one item of cluster data CLD1 stored at physical cluster address AD1. Similarly, items of cluster data from CLD2 to CLD8 respectively containing data from A 2 , B 2 , C 2 and D 2 to A 8 , B 8 , C 8 and D 8 are stored at the other physical cluster addresses from AD2 to AD8. Though it is described that eight items of cluster data are stored in the EEPROM 40 at one time, it goes without saying that an arrangement may be adopted in which the data are written one cluster at a time or a plurality of clusters at a time. Further, in the same manner as in the case of the rewriting of data described here, image data that have been stored in the S-RAM 30 and the corresponding image data that have been written in the EEPROM 40 are compared one cluster at a time in the comparator circuit 50, and it is determined whether the writing of the data in the EEPROM 40 has been performed correctly. In the case set forth above, the writing of digital data is performed when all of the storage locations of the physical cluster area are blank, and over-writing is not carried out. Therefore, data "0" are stored as the over-written logical cluster address and data "AD8" are stored as the last-written physical cluster address, as shown in Fig. 5a. Assume that rewriting of the data that have been stored at the physical cluster address AD2 is performed. In such case, the cluster data CLD2 (A 2 , B 2 , C 2 , and D 2 ) that have been stored at the physical cluster address "AD2" are read out and applied to the S-RAM 30, where the data are stored. Partial rewriting of the data (rewriting of old data D2 to new data E2) is performed in the S-RAM 30. More specifically, the data D0 ∼ D7 representing the data E2 are applied to the S-RAM 30, and these data is substituted for the old data D2. The cluster data CLD2 partially rewritten in the S-RAM 30 are applied to the EEPROM 40. The address converter circuit 20 outputs "AD2" as the data of the physical cluster address, and these data are applied to the EEPROM 40. As a result, new cluster data CLD2 (A 2 , C 2 , D 2 , and E 2 ) are stored at the storage location of the physical cluster address "AD2" in the physical cluster area. The new cluster data may thus be stored at the original storage location or at a different storage location in the physical cluster area. The item of data (the cluster data CLD2 after rewriting) temporarily stored in the S-RAM 30 and the item of data (the new cluster data CLD2) written in the EEPROM 40 are each read out and applied to the comparator circuit 50. The comparator circuit 50 compares these two clusters and outputs the coincidence signal EQ if all bits coincide. This signal is applied to the sequence control circuit 10. As a result, the sequence control circuit 10 verifies that the rewriting of the cluster data CLD2 in the EEPROM 40 has been performed correctly. If coincidence is not achieved, it is construed that the storage location of the physical cluster address "AD2" is a defective area and this location is no longer used for storage of cluster data. The new cluster data CLD 2 (A 2 , C 2 , D 2 , and E 2 ) that have been rewritten in the S-RAM 30 are written at the storage location of the "blank" physical cluster address "AD9" instead of the storage location of the physical cluster address "AD2". This state is illustrated in Figs. 6a and 6b. At this time the last-written physical cluster address is incremented and "AD9" is stored. In the description given above, the cluster data CLD2 that have been rewritten in the S-RAM 30 are written in the EEPROM 40, after which the items of cluster data are read out of the S-RAM 30 and EEPROM 40 and compared. If these items of data do not coincide, a judgment is made that the storage location of address AD2 in the EEPROM 40 is faulty. It is preferred to adopt an arrangement in which the writing of the cluster data at the storage location of address AD2 in the EEPROM 40 and the comparison of the cluster data of the S-RAM 30 with the corresponding cluster data that have been written in the EEPROM 40 be carried out repeatedly a plurality of times until a result indicative of coincidence is obtained, without judging that a storage location is faulty based upon only a single comparison. When a result indicative of coincidence is not obtained even if this processing is repeated a plurality of times, the storage location at address AD2 is judged to be defective. Operation will now be described for a case in which the cluster data CLD4 at the storage location of address AD4 are shifted to the storage location of address AD3 in the physical cluster area. First, it is necessary to shift the cluster data CLD3 at address AD3 to another location, e.g., the storage location of address AD10. As shown in Fig. 7a, the address AD10 of the physical cluster area is written to correspond to the logical cluster address ad3 in the logical cluster area. In order to store the fact that the data at this address ad3 have been over-written, "ad3" is written in as the over-write logical cluster address. The cluster data CLD3 at address AD3 in the physical cluster area are read out and stored temporarily in the S-RAM 30. Thereafter, the cluster data CLD3 are transferred from the S-RAM 30 to the storage location designated by the address AD10 of the EEPROM 40. This is the state illustrated in Fig. 7b. The last-written physical cluster address is updated to AD10. In this case also, the cluster data CLD3 that have been stored in the S-RAM 30 and the cluster data CLD3 that have been stored at address AD10 of the EEPROM 40 are compared to determine whether the writing of the cluster data in the EEPROM 40 has been performed correctly. Next, in order to shift the cluster data CLD4 at the physical cluster address AD4 to address AD3, the data at the logical cluster address ad4 are updated to AD3 and the data of over-written logical cluster address AD4 are updated to ad4 (see Fig. 8a). Once the cluster data at the physical cluster address AD4 have been transferred to and stored in the S-RAM 30, these cluster data are written in the storage location at address AD3 of the physical cluster area (see Fig. 8b). The storage location at address AD4 becomes blank. The last-written physical cluster address remains unchanged at "AD10". In a case where part of the cluster data CLD5 designated by the physical cluster address "AD5" is changed in Figs. 8a and 8b, the cluster data CLD5 (A 5 , B 5 , C 5 and D 5 ) at this address are read out and transferred to the S-RAM 30, where a partial change of the data (a change from data D 5 to data E 5 ) is performed. The changed new cluster data CLD5 (A 5 , B 5 , C 5 and E 5 ) are applied to the EEPROM 40 and written in the blank storage location at address "AD4". The new cluster data CLD5 that have been written in the storage location at address "AD4" are read out of the EEPROM 40 and applied to the comparator circuit 50. The cluster data CLD5 after the change, which data have been stored in the S-RAM 30, are also applied to the comparator circuit 50. The comparator circuit 50 performs a comparison to determine whether the cluster data CLD5 after the change read out of the S-RAM 30 and the new cluster data CLD5 read out of the EEPROM 40 coincide. If the comparison indicates non-coincidence, it is judged that the writing of the new data in the EEPROM 40 has failed. As a result, the new data are written in the blank storage area at address "AD11". In this case also, the new items of cluster data are read out of the EEPROM 40 and S-RAM 30 and the comparator circuit 50 determines whether these items of data coincide. The state in which new data have thus been written at the physical cluster address "11" is illustrated in Figs. 9a and 9b. In this case, the over-written logical cluster address is changed to "ad5" and the last-written physical cluster address is changed to "AD11", as illustrated in Fig. 9a.

Claims: A method of rewriting data in an EEPROM(40) having a plurality of storage areas which are designated by addresses, comprising the steps of: addressing a first storage area of the EEPROM in which first data that include old data to be written have been stored and reading out said first data from this storage area; writing said first data read out from the EEPROM, into a RAM(30); generating second data in the RAM by rewriting new data for said old data of said first data written into the RAM; and reading out said generated second data from the RAM, and writing said read-out second data into a second storage area of the EEPROM, characterized in that said method further comprises the steps of: performing said writing of said second data into a blank second storage area of the EEPROM in order of address by addressing a storage area of the EEPROM next to the first storage area which is designated by a memorized last address, and writing said generated and read-out second data into the addressed storage area; memorizing the last address of the second storage area of the EEPROM where said second data have been written; and reading out said second data from the RAM, reading out said second data from the EEPROM, and checking whether said second data read out from the RAM and said second data read out from the EEPROM coincide. The method according to claim 1, further comprising a step of writing said second data into another blank storage area of the EEPROM when it is determined that said second data in the RAM do not coincide with said second data in the EEPROM. The method according to claim 2, further comprising a step of checking again whether said second data in the RAM coincide with said second data that have been written into the other area of the EEPROM. The method according to claim 1, wherein when it is determined that said second data in the RAM do not coincide with said second data in the EEPROM, the writing of the second data into the EEPROM is performed again a prescribed plurality of times until it is determined that said second data in the RAM coincide with said second data in the EEPROM. The method according to claim 4, wherein when a determination of coincidence is not obtained even when the writing of said second data into the area of the EEPROM is performed again said prescribed plurality of times, said second data is written into another area of the EEPROM. An EEPROM card comprising; an EEPROM(40) having a plurality of storage areas in which data is capable of being erased and written; a RAM(30) for performing an operation through which data in said EEPROM(40) is updated; first data reading/writing means(10) for addressing a first storage area of said EEPROM(40) in which first data that include old data to be rewritten have been stored, reading out the first data from this first storage area and writing the first data, which have been read out from said EEPROM(40), into said RAM(30); data updating means(10) for generating second data by rewriting new data for the old data in the first data that have been written in said RAM(30); and data writing means(10) for reading out said second data generated by said data updating means(10) from said RAM (30) and for writing said read-out second data into a second storage area of said EEPROM(40), characterized in that said EEPROM card further comprises: said data writing means(10), which performs writing of said second data into a blank second storage area of said EEPROM(40) in order of address, by addressing said second storage area of said EEPROM next to the first storage area which is designated by a memorized last address; means (21) for memorizing the last address of the second storage area of said EEPROM(40) where said second data have been written; and discriminating means(50) for comparing said second data in said RAM(30), which data have been rewritten by said data updating means, with said second data that have been written in said EEPROM(40) by said data writing means(10), and for checking whether said rewritten second data in the RAM(30) and said second data written in said EEPROM(40) coincide. The EEPROM card according to claim 6, further comprising control means (10) for controlling said data writing means (20) in such a manner that said second data are written in another blank storage area of said EEPROM (40) when it is determined that the second data in said RAM (30) do not coincide with the second data in said EEPROM (40). The EEPROM card according to claim 6, further comprising control means for controlling said data writing means in such a manner that when it is determined that the second data in said RAM (30) generated by said data updating means do not coincide with the second data written in said EEPROM (40) by said data writing means (20), the writing of the second data in said EEPROM (40) is performed again a prescribed plurality of times until it is determined that the generated second data in the RAM (30) coincide with the second data in said EEPROM (40).

Inventors: SAITO OSAMU, SAITO, OSAMU, Saito, Osamu, c/o Fuji Photo Film Co., Ltd.
Applicants: FUJI PHOTO FILM CO LTD, FUJI PHOTO FILM CO., LTD.
Application year: 1993
Main classification: G11C16
IPC codes: G11C17, G11C16, G11C11, G06F12