Circuit structure for a memory matrix and corresponding manufacturing method

Abstract: A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including plural rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL); the bit lines (BL), moreover, are gathered into groups or bytes (9) of simultaneously addressable adjacent lines. Each cell (2) in the matrix incorporates a floating gate transistor (12) which is coupled to a control gate (8), connected to the control gate line (CG), and is connected serially to a selection transistor (5); also, the cells (2) of each individual byte (9) share their respective source areas (6), which areas are structurally independent for each byte (9) and are led to a corresponding source addressing line (SL) extending along a matrix column (7).

Description: Field of the Invention This invention relates to a circuit structure for a memory cells matrix. More particularly, the invention relates to a matrix of EEPROM memory cells being of a type which comprises a cells matrix composed of plural rows and columns, each provided with a word line and a bit line respectively, wherein the bit lines are gathered into groups or bytes of adjacent lines which are simultaneously addressable, each of said cells incorporating a floating gate transistor connected serially to a selection transistor and having an additional control gate overlaying the floating gate. Prior Art As is well known, EEPROM memory structures, while being non-volatile types, allow the information contained therein to be modified electrically at both the write and the erase phases of their operation. Furthermore, they distinguish themselves by the kind of their electric programming, which may take place in either the "page" mode or the "byte" mode. In the former mode, all the cells in one row of the matrix are addressed at one time. In the latter mode, one byte only is addressed of the several available in one row. It is also known that the state of any cell in the EEPROM memory can be altered by means of an electrons flow passing by tunnel effect through a thin layer of silicon oxide associated with the floating gate of the cell. The thin oxide region occupies a smaller area than the floating gate, whereat the electric charge is stored. There exist different types of EEPROM memory cells which are identifiable by the number of their polysilicon layers. In fact, there are cells with single, double, or treble layers of polysilicon. Most commonly employed are cells with two-level of polysilicon, known as FLOTOX cells; such cells are described, for instance, in an article "Oxide reliability criterion for the evaluation of endurance performance of electrically erasable programmable read-only memories", Journal App. Phys, 71, No. 9, 1992. Irrespective of the number of the polysilicon layers, for the write and erase phases of the cells, it is common practice to use positive voltages, applied to the diffusion underlying the tunnel region or the control gate. Such voltages vary between 8 and 18 Volts, in order to generate across the thin oxide an electric field which is sufficiently strong to positively trigger the tunnel effect. However, the use of such, comparatively high, positive voltages may result over time in the thin oxide layer being deteriorated, thereby damaging the cells and the whole memory structure beyond repair. One might think of obviating this problem by using negative voltages for programming, e.g. during the writing phase. It should not be overlooked, however, that with conventional type cells the byte mode programming is carried out by splitting the control gate into segments which are common to a single byte (e.g., eight or sixteen bits). The control gate is then selected by means of a column decoder external of the cells matrix, and is enabled by a select transistor shared by all the cells in one row. In this way, the programming will only be enabled in the selected byte. But the use of a negative voltage during this programming phase adduces some serious problems. As an example, a large integrated circuit area would have to be used for selecting a single byte, because each segment of the control gate requires the arrangement of a switch adapted to handle both the positive voltages and the negative voltages applied during the programming phase. The underlying technical problem of this invention is to provide a circuit structure for a matrix of memory cells, in particular of the EEPROM type, which has such structural and functional features as to improve the memory reliability, and extend its service life, while attenuating the deterioration of the tunnel oxide and obviating the programming problems when using negative voltages. A further object of the invention is to provide very high density integrated storage circuits which can occupy, for a given technology, a smaller circuit area than comparable circuits of conventional design. This would enable the manufacturing costs of high density storage circuits to be cut down drastically. A further object of the invention is to provide a circuit of a matrix of EEPROM memory cells wherein erasing of non addressed memory cells is avoided. In IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol.SC-17, Oct. 1982, p.833-840, which forms the basis for the preamble of claim 1, erasing of an addressed cell (cf fig.5, cell at the top-left: high programming voltage Vpp at the gate, ground at the drain) may lead to erroneous writing to a non addressed cell (cf cell at the bottom-right: gate at ground, drain at Vpp). This is avoided by providing each cell with a selection transistor (cf fig.6a) such that the drain of non addressed cells may be disconnected from Vpp. The sources of the cells are commonly connected to ground. In an improvement for current reduction (cf fig.8), the sources are pulled down to ground during read and are held floating during write/erase. EP-A-0 182 198 employs memory cells without selection transistors. The sources of the memory transistors of a byte (cf fig.5d) are connected to a common source area which is structurally independent for each byte and connected via enable transistors (129) to a source addressing line (126). During erasing, the drains of all bytes are floating, the gates of the addressed byte (BYTE 1) are set to ground, and the source area of said addressed byte is set to Vpp. Thereby, Vpp is supplied by said source addressing line (126) via an enable transistor which is switched on by Vpp applied to the word line WL2 controlling the non addressed adjacent byte (BYTE 2) in column direction. During this erasing step, there exist further non addressed bytes (BYTE 3, BYTE 4) which have set their gates to ground (BYTE 3) or to VPP (BYTE 4), and have set their common source area to an intermediate or supply voltage (5V) supplied from another source addressing line. The intermediate voltage (5V) decreases the voltage difference between the gates and the sources and thus avoids erasing of said further non addressed bytes. The aforementioned two documents, both solve the problem of avoiding erasing of non addressed memory cells but each of them solves it on a different way due to the employed different memory cells having a selection transistor or not. A combination of both would not be taken into consideration since it is not apparent which problem could be solved therewith. Summary of the Invention The solutive idea on which this invention stands is one of splitting the so-called source line into regular segments shared by the cells of a single byte (having eight or sixteen bits, for example) and decoding such segments when a desired byte is programmed. On the grounds of this solutive idea, the technical problem is solved by a circuit structure as defined in Claim 1. The features and advantages of a circuit structure according to the invention will become apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a diagramatic view of a circuit structure embodying this invention; Figure 2 is an enlarged schematic view from above of a semiconductor portion in which the inventive circuit structure is formed; Figure 3 is an enlarged schematic view in vertical section, taken along line III-III in Figure 2, of a semiconductor portion in which the circuit of this invention is formed; Figure 4 is an enlarged schematic view in vertical section, taken along line IV-IV in Figure 2, of a semiconductor portion in which the circuit of this invention is formed; Figure 5 is an enlarged schematic view in vertical section, taken along line V-V in Figure 2, of a semiconductor portion in which the circuit of this invention is formed. Detailed Description With reference to the drawing views, generally and schematically shown at 1 is a circuit structure for forming, in accordance with the invention, a matrix of memory cells 2, in particular EEPROM memory cells. The structure 1 is constructed in the form of a semiconductor integrated circuit incorporating thousands of cells 2. Shown diagramatically in Figure 1 is, however, just a portion of this circuit. The matrix provided by the structure 1 comprises a plurality of rows 3 and plurality of columns 4. Each row 3 includes a so-called word line WL and a corresponding control gate line CG. On the other hand, the columns 4 include the so-called bit lines of the matrix. According to the memory size, the bit lines BL are gathered into bytes 9, that is into groups of eight BL 0 ,...,BL 7 or sixteen adjacent lines which can be addressed simultaneously. At the crossover of a word line WL with a bit line BL, there is a selection transistor 5. In addition, a bit line BL interconnects all the drain terminals of the common selection transistors 5 on a given column 4 of the matrix. Each selection transistor 5 is associated with and connected serially to a floating gate EEPROM cell 2. Specifically, the cell 2 is of the type with a double level of polysilicon, and has a basic structure substantially of the FLOTOX type. The core of the memory cell 2 comprises a MOS transistor having a floating gate 12 where the electric charge is stored identifyings the two different, "written" or "erased", states of the cell. The floating gate is shown in Figure 2. In general, the cell 2 would include a second, or control, gate 8, which is coupled capacitively to the floating gate 12 through an intervening dielectric layer called "interpoly". A voltage is transferred through said dielectric layer to the floating gate 12 from the control gate 8 during the write and/or erase phases of the cell 2. The control terminal of the control gate 8 is shared by all the cells 2 which form any one row 3 in the structure 1. Each row 3 of the matrix 1 is provided, to that aim, with a dedicated connection line CG interconnecting the gates 8. Advantageously, according to the invention, the structure 1 further comprises plural source addressing columns 7, each associated with a corresponding byte 9. Such columns 7 are also referred to as source addressing lines SL. In the embodiment described herein by way of example, the lines SL are each connected between each pair of adjacent bytes 9, that is to say, a column 7 is provided for each group of bit lines BL forming a byte 9. Nothing forbids, however, to provide such source addressing lines SL between the bit lines BL. Each source addressing line SL connects the source terminals of a series of enable transistors A and B aligned on one column. The transistors denoted by A are provided at the crossover of each word line WL with the column 7, whereas the transistors denoted by B are provided at the crossover of each connection line CG connecting the control gates 8 to the column 7. Advantageously, according to the invention, the source terminals of all the transistors incorporated to the cells 2 of a single byte 9 are led to one and the same corresponding source line SL. In essence, it results as if the source line SL were split into segments, each in common with the source regions 6 of the cells 2 which form a single byte 9. From the practical embodiment illustrated by Figure 2, it can be appreciated that all the cells 2 of a given byte 9 would have respective source regions formed in common with a corresponding one of the source lines SL. Additionally, the source regions of the symmetrical byte with the above - - i.e. the byte in the next row 3 -- would also be in common. The enable transistors A and B present in the source addressing line SL are not strictly necessary, although their provision has the advantage of minimizing noise, as explained hereinafter. The transistors A are intended for selecting the segment of that source line SL in the row 3 which would be addressed when accessing the memory structure. Each transistor A is driven from its respective word line WL. The transistors B are basically additional enable transistors. They are driven from their respective connection line CG and should be a high-voltage type in order to withstand the voltages that are applied during the erase phase. Each transistor B only represents a small increase in the series resistance of its respective source line SL. This resistance may be minimized, if desired, by appropriate selection of the transistor B length and width, or even removed altogether by shorting the transistors with an implant or a connecting bridge of polysilicon or metal. The method for programming the memory cell of this invention will now be described. In fact, the peculiar and innovative structure of this cell 2 allows it to be programmed in quite a novel manner. In conventional storage circuits, positive voltage pulses are usually employed for writing and erasing a given cell, which pulses are applied to the cell terminals such that a sufficient electric field is generated to induce a flow of current through the tunnel oxide layer. By contrast, the memory structure of this invention provides for the use of a negative voltage, to be applied to the control gate 8 of each predetermined cell 2 during the write phase. Specifically, during the write phase, to a selected byte is applied, at the various terminals, the voltages shown in the following Table I. Throughout the following Tables, there are shown -- for each write, erase, or read phase -- the voltage values on the source line SL, the bit line BL (drain contact), the word line WL (gate of the select transistor 5), and the control gate 8. The voltage at the control gate 8 is decoded by rows, as is that applied to the gate of the selection transistor 5. The voltage at the drain terminal is on the contrary decoded by columns, as is that at the source terminals of the line SL. The erase and read phases for the selected byte are run in a similar manner, with the difference that no negative voltages are applied here to the various terminals. If no enable transistors A and B are provided, the voltage on the word line during the erase phase may be zero. Table II, on the other hand, shows the voltage values being applied to a byte which has not been selected but is present in the same row as the selected byte. Likewise, Table III shows the voltage levels being applied to a byte which has not been selected but is present in the same column as the selected byte. Selected byte V SOURCE [V] V DRAIN [V] WL select tr. [V] V CG [V] WRITE float 5 6 -8 ERASE 0 float 6 16 READ 0 1 5 3 Unselected byte in the same row as the selected byte (same WL and CG.) V SOURCE [V] V DRAIN [V] WL select tr. [V] V CG [V] WRITE float float 6 -8 ERASE 5 float 6 16 READ float float 5 3 Unselected byte in the same column as the selected byte. (Same decoding as the source V SOURCE [V] V DRAIN [V] WL select tr. [V] V CG [V] WRITE float 5 0 0 ERASE 0 float 0 0 READ float float 0 0 Unselected byte in different row and column from the selected byte. V SOURCE [V] V DRAIN [V] WL select tr. [V] V CG [V] WRITE float float 0 0 ERASE 5 float 0 0 READ float float 0 0 In either cases, the polarizations applied to the various terminals are transferred in the same way as previously described; that is to say, the control gate decoding is carried out by rows, whereas the decoding of the drain and the source terminals is carried out by columns. Thus, it can be once more appreciated that the write phase is characterized by the use of a negative voltage at the control gate 8 and a positive voltage at the drain terminal of the cell 2; this allows generation of a sufficiently strong electric field to draw electrons from the floating gate 12. However, this operation does impose some noise on all the cells in one row 3. In fact, the negative voltage would also be applied to their control gate 8, which is in common with the line CG for all the cells in the same row 3. This noise may be difficult to suppress in the byte programming mode; but the effect of the noise can be minimized by appropriate adjustment of the values of the applied voltages. During the erase phase, the voltage Vs=0 on the source column SL is taken from that column to the source terminals of the cells 2 which belong to the selected byte 9. In fact, both the transistor A and the transistor B are conducting, and each cell 2 of the selected byte 9 is injected by electrons at the floating gate 12 through the channel region. However, in order to prevent erasing of bytes not yet selected but placed in the same row 3, the source lines SL of the unselected columns 7 are brought to a voltage of 5 Volts. Here again, the voltage is transferred to all the source segments related to each byte because the transistors A and B are conducting. In this way, the electric field across the tunnel oxide will not be sufficiently strong to significantly trigger a Fowler-Nordheim conduction mechanism, and accordingly, the information stored in the cells of these unselected bytes is left unaltered. Additionally, all the bytes in rows other than the selected one will be unaffected by the erase and write operations because to their control gates no voltage are applied with a sufficiently high (whether positive or negative) value. It matters to observe that no noise from the comparatively low voltage applied to the source columns SL during the erase phase would appear on the bytes of the unselected rows, because the transistor A is cut off during this phase and no voltage is transferred to the source terminals, thereby allowing them to float. The read phase is run in quite a conventional manner. With reference in particular to the examples of Figures 2 to 5, the steps of the manufacturing method which lead to the formation of a semiconductor integrated device incorporating the circuit structure of this invention will now be described. Specifically, the process steps will be described herein below leading to a circuit also incorporating the transistors A and B for the source addressing line SL. The cells 2 in the matrix 1 are implemented in the MOS technology, starting with a P-doped semiconductor substrate 10, which has been formed with either N-type or P-type wells. Thus, the description to follow will begin with the step of photolithographically defining active area regions on the substrate 10. Among these active areas, the common source regions 6 of cells 2 in the same byte 9 are structurally and electrically separate from those of the adjacent bytes, as brought out by Figure 5. The growth of field oxide 22 allows such regions 6 to be demarcated. Then, the gate oxide is formed to different depths according to the different transistor types. For instance, a tunnel oxide 24 thickness of about 9 nm is preferred for the floating gate cells 2, while a thickness of about 20 nm would be appropriate for the selection transistors 5. As for the transistors A and B of the source addressing line SL, the former may have a gate oxide 26 formed to either a thickness of 20 nm or 30 nm, that is, for a low or a high voltage, whilst the latter transistor B is to expressedly withstand high voltages and requires a thickness of about 30 nm for the gate oxide 16. In order to provide thicknesses so markedly different from one another, one can proceed in steps, such as by growing a first oxide layer of about 24 nm onto the surface of the substrate 10. This first layer would be masked with a resist and etched in those areas where the low-voltage oxide is to be grown. The resist is then removed, and a second oxide layer of about 18 nm grown. During this second growth, the depth of the first layer would also be increased. A subsequent masking step with a resist will enable the high- and low-voltage oxide 16, 26 areas to be protected, and the oxide layer etched away in the tunnel areas. Removal of the resist and subsequent growth of the tunnel dielectric 24 bring to completion the thickness of the low- and high-voltage oxides 16 and 26 as well. Nothing forbids, of course, that a different procedure be used to provide such different oxide thickness. The process continues with the deposition, doping, and photolithographic definition of the first polycrystalline silicon (polysilicon) layer 20 for the floating gates 12 of the cells 2. A so-called interpoly dielectric layer 25 is formed over the first polysilicon layer 20. This interpoly layer 15 is removed, however, along the source addressing line SL shown in Figure 3 to later obtain standard transistors A and B having no floating gates. The other areas of the matrix 1 are protected with a photoresist during this operation. Moreover, the deposition and doping of a second polysilicon layer 21 will allow the formation of the control gates 8 and those of the selection transistors 5, as well as the gates of the enable transistors A and B. Thereafter, the source and drain implantations are carried out for the cells 2, the selection transistors 5, and the active areas 15 of the transistors A and B, using at least one species of the N type. The process is completed by subsequent steps, known per se, which will provide: so-called spacers 19; N- and P-channel transistors for the circuitry associated with the matrix 1; and an intervening dielectric 17 and a terminating metallization layer 18. On the whole, the process just described has a major advantage in that it can be completed using no additional steps with respect to conventional methods. The circuit structure of this invention, as obtained with the process described hereinabove, does solve the technical problem and afford a number of advantages as follows. First, this solution allows the programming to be handled for each individual byte even where negative voltages are used during the write phase. The use of a negative voltage at the control gate 8 allows the voltage applied to the drain terminal to be lowered while maintaining, across the thin oxide, an electric field which is the equal of that provided in conventional cells. Thus, the deterioration of the thin tunnel oxide can be greatly reduced. In addition, the use of a negative voltage at the control gate 8 of the cells 2 during the write phase, allows the voltage requirement across the tunnel oxide for obtaining a desired programming current to be distributed. The circuit of this invention can be integrated within a smaller area than a conventional cell of equal technology. Since the inventive cell works on the basis of a Fowler-Nordheim tunnel effect, and its intrinsic threshold may be selected close to zero, this structure would suit in particular low-voltage supply applications. Understandably the memory cell herein described and illustrated may be altered and modified in many ways without departing from the invention scope as defined in the appended claims.

Claims: A circuit of a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including a plurality of rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL), said bit lines (BL) being gathered into groups of simultaneously addressable adjacent lines, thereby grouping said matrix cells into bytes (9), and the matrix cells (2) incorporating each a floating gate transistor (12) which is coupled to a control gate (8) connected to the control gate line (CG) and is connected with the drain serially to a selection transistor (5), characterized in that: the cells (2) of each individual byte (9) have a common source area (6), such area being structurally independent for each byte (9) and being led to a corresponding source addressing line (SL) extending along a matrix column (7) to avoid erasing of non addressed bytes by applying a voltage to said source area which reduces the voltage difference between control gate and source area of said non addressed bytes. A circuit according to Claim 1, characterized in that said source addressing line (SL) is split substantially into segments shared by the cells (2) of each individual byte (9). A circuit according to Claim 1, characterized in that said source addressing line is decoded when selecting a desired byte (9). A circuit according to Claim 2, characterized in that each segment (6) is individually addressable, and is decoded when accessing or programming the desired byte (9). A circuit according to Claim 1, characterized in that said source addressing line (SL) comprises at least one enable transistor (A) connected to the source regions (6) of the cells (2) of one and the same byte (9). A circuit according to Claim 5, characterized in that said enable transistor (A) is provided at the crossover of each word line (WL) with the source line (SL). A circuit according to Claim 1, characterized in that said source addressing line (SL) comprises at least a pair of enable transistors (A,B) connected to the source regions (6) of one and the same byte (9). A circuit according to Claim 7, characterized in that the former (A) of said enable transistors (A,B) is provided at the crossover of each word line (WL) with the source addressing line (SL). A circuit according to Claim 7, characterized in that the latter (B) of the enable transistors is provided at the crossover of each control gate (8) line (CG) with the source addressing line (SL). A method for making, in MOS technology, a matrix (1) of memory cells (2) of a type formed, in MOS technology, on a semiconductor substrate (10), the cells (2) comprising floating gate (12) transistors having active source (6) and drain areas and being each connected with the drain serially to a respective selection transistor (5), characterized in that it provides for the formation of a plurality of addressing lines (SL) for said active source areas (6), said addressing lines extending along columns (7) of the matrix (1) and each including enable transistors (A,B) formed concurrently with the floating gate transistors and the selection transistors (5), that it provides for the formation of a structurally independent and common source area (6) for the cells (2) of each individual byte (9) and that it provides to connect said common source area to said enable transistor. A method according to Claim 10, characterized in that the active source areas (6) of the transistors incorporated into the cells (2) of a given byte (9) are formed in common with one and the same corresponding source addressing line (SL). A circuit according to Claim 1, characterized in that the source terminals of the transistors incorporated into the cells (2) of a predetermined byte (9) are connected to one and the same corresponding source addressing line (SL).

Inventors: LUCHERINI SILVIA, PIO FEDERICO, RIVA CARLO, LUCHERINI, SILVIA, PIO, FEDERICO, RIVA, CARLO, LUCHERINI, SILVIA C/O SGS-THOMSON
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C16
IPC codes: H01L29, H01L27, H01L21, G11C16