SUPERSCALAR RISC INSTRUCTION SCHEDULING

Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Description: DESCRIPTION SUPERSCALAR RISC INSTRUCTION SCHEDULING CROSS-REFERENCE TO RELATED APPLICATIONS The following are commonly owned, co-pending applications: * "Semiconductor Floor Plan and Method for a Register Renaming Circuit", Serial No. 07/860,718, filed 3/31/92 concurrently filed with the present application (Attorney Docket No. SP041); * "High Performance RISC Microprocessor Architecture", Serial No. 07/817,810, filed 1 8/92 (Attorney Docket No. SP015); * "Extensible RISC Microprocessor Architecture", Serial No. 07/817,809, filed 1/8/92 (Attorney Docket No. SP021). The disclosures of the above applications are incorporated herein by reference. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to superscalar reduced instruction set computers (RISC), more particularly, the present invention relates to instruction scheduling including register renaming and instruction issuing for superscalar RISC computers. 2. Related Art A more detailed description of some of the basic concepts discussed in this application is found in a number of references, including Make Johnson, Superscalar Microprocessor Design (Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1991); John L. Hennessy et al., Computer Architecture - A Quantitative Approach" (Morgan Kaufmann Publishers, Inc., San Mateo, California, 1990). Johnson's text, particularly Chapters 2, 6 and 7 provide an excellent discussion of the register renaming issues addressed by the present invention. A major consideration in a superscalar RISC processor is to how to execute multiple instructions in parallel and out-of-order, without incurring data errors due to dependencies inherent in such execution. Data dependency checking, register l - -renaming and instruction scheduling are integral aspects of the solution. 2.1 Storage Conflicts and Register Renaming True dependencies (sometimes called "flow dependencies" or "write-read" dependencies) are often grouped with anti-dependencies (also called "read-write" dependencies) and output dependencies (also called "write-write" dependencies) into a single group of instruction dependencies. The reason for this grouping is that each of these dependencies manifests itself through use of registers or other storage locations. However, it is important to distinguish true dependencies from the other two. True dependencies represent the flow of data and information through a program. Anti- and output dependencies arise because, at different points in time, registers or other storage locations hold different values for different computations. When instructions are issued in order and complete in order, there is a one-to-one correspondence between registers and values. At any given point in execution, a register identifier precisely identifies the value contained in the corresponding register. When instructions are issued out of order and complete out of order, correspondence between registers and values breaks down, and values conflict for registers. This problem is severe when the goal of register allocation is to keep as many values in as few registers as possible. Keeping a large number of values in a small number of registers creates a large number of conflicts when the execution order is changed -fro the order assumed by the register allocator. Anti- and output dependencies are more properly called "storage conflicts" because reusing storage locations (including registers) causes instructions to interfere with one another even though conflicting instructions are otherwise independent. Storage conflicts constrain instruction issue and reduce performance. But storage conflicts, like other resource conflicts, can be reduced or eluninated by duplicating the troublesome resource. 2.2 Dependency Mechanisms Johnson also discusses in detail various dependency mechanisms, including: software, register renaming, register renaming with a reorder buffer, register renaming with a future buffer, interlocks, the copying of operands in the instruction window to avoid dependencies, and partial renaming. A conventional hardware implementation relies on software to enforce dependencies between instructions. A compiler or other code generator can arrange the order of instructions so that the hardware cannot possibly see an instruction until it is free of true dependencies and storage conflicts. Unfortunately, this approach rims into several problems. Software does not always know the latency processor operations, and thus, cannot always know how to arrange instructions avoid dependencies. There is the question of how the software prevents the hardwa from seeing an instruction until it is free of dependencies. In a scalar processor wit low operation latencies, software can insert "no-ops" in the code to satisfy da dependencies without too much overhead. If the processor is attempting to fetc several instructions per cycle, or if some operations take several cycles to complet the number of no-ops required to prevent the processor from seeing depende instructions rapidly becomes excessive, causing an unacceptable increase in co size. The no-ops use a precious resource, the instruction cache, to enco dependencies between instructions. When a processor permits out-of-order issue, it is not at all clear what mechanis software should use to enforce dependencies. Software has little control over t behavior of the processor, so it is hard to see how software prevents the process from decoding dependent instructions. The second consideration is that no existin binary code for any scalar processor enforces the dependencies in a superscal processor, because the mode of execution is very different in the superscal processor. Relying on software to enforce dependencies requires that the code b regenerated for the superscalar processor. Finally, the dependencies in the code ar directly determined by the latencies in the hardware, so that the best code for eac version of a superscalar processor depends on the implementation of that version. On the other hand, there is some motivation against hardware dependenc techniques, because they are inherently complex. Assuming instructions with tw input operands and one output value, as holds for typical RISC instructions, the there are five possible dependencies between any two instructions: two tru dependencies, two anti-dependencies, and one output dependency. Furthermore, th number of dependencies between a group of instructions, such as a group instructions in a window, varies with the square of the number of instructions in th group, because each instruction must be considered against every other instruction. Complexity is further multiplied by the number of instructions that the processo attempts to decode, issue, and complete in a single cycle. These actions introduc dependencies. The only aid in reducing complexity is that the dependencies can b determined incrementally, over many cycles to help reduce the scope and complexit of the dependency hardware. One technique for removing storage conflicts is by providing additional register that are used to reestablish the correspondence between registers and values. Th additional registers are conventionally allocated dynamically by hardware, and th registers are associated with values needed by the program using "registe renaming." To implement register renaming, processors typically allocate a ne register for every new value produced (i.e., for every instruction that writes a register). An instruction identifying the original register, for the purpose of reading its value, obtains instead the value in the newly allocated register. Thus, hardware renames the original register identifier in the instruction to identify the new register and correct value. The same register identifier in several different instructions may access different hardware registers, depending on the locations of register references with respect to register assignments. Consider the following code sequence where "op" is an operation, "Rn" represents a numbered register, and ":=" represents assignment: R3b := R3a op R5a (1) R4b := R3b + 1 (2) R3c := R5a + 1 (3) R7b := R3c op 4b (4) Eac assignment to a register creates a new "instance" of the register, denoted by an alphabetic subscript. The creation of a new instance for R3 in the third instruction avoids the anti- and output dependencies on the second and first instructions, respectively, and yet does not interfere with correctly supplying an operand to the fourth instruction. The assignment to R3 in the third instruction supersedes the assignment to R3 in the first instruction, causing R3c to become the new R3 seen by subsequent instructions until another instruction assigns a value to R3. Hardware that performs renaming creates each new register instance and destroys the instance when its value is superseded and there are no outstanding references to the value. This removes anti- and output dependencies and allows more instruction parallelism. Registers are still reused, but reuse is in line with the requirements of parallel execution. This is particularly helpful with out-of-order issue, because storage conflicts introduce instruction issue constraints that are not really necessary to produce correct results. For example, in the preceding instruction sequence, renaming allows the third instruction to be issued immediately, whereas, without renaming, the instruction must be delayed until the first instruction is complete and the second instruction is issued. Another technique for reducing dependencies is to associate a single bit (called a "scoreboard bit") with each register. The scoreboard bit is used to indicate that a register has a pending update. When an instruction is decoded that will write a register, the processor sets the associated scoreboard bit. The scoreboard bit is reset when the write actually occurs. Because there is only one scoreboard bit indicating whether or not there is a pending update, there can be only one such update for each register. The scoreboard stalls instruction decoding if a decoded instruction will update a register that already has a pending update (indicated by the scoreboard bit being set). This avoids output dependencies by allowing only one pending update to register at any given time. Register renaming, in contrast, uses multiple-bit tags to identify the variou uncomputed values, some of which values may be destined for the same processo register (that is, the same program-visible register). Conventional renaming require hardware to allocate tags from a pool of available tags that are not currentl associated with any value and requires hardware to free the tags to the pool once th values have been computed. Furthermore, since scoreboarding allows only on pending update to a given register, the processor is not concerned about which updat is the most recent. A further technique for reducing dependencies is using register renaming with "reorder buffer" which uses associative lookup. The associative lookup maps th register identifier to the reorder buffer entry as soon as the entry is allocated, and, t avoid output dependencies, the lookup is prioritized so that only the value for th most recent assignment is obtained if the register is assigned more than once. A ta is obtained if the result is not yet available. There can be as many instances of given register as there are reorder buffer entries, so there are no storage conflict between instructions. The values for the different instances are written from th reorder buffer to the register file in sequential order. When the value for the fina instance is written to the register file, the reorder buffer no longer maps the register the register file contains the only instance of the register, and this is the most recen instance. However, renaming with a reorder buffer relies on the associative lookup in th reorder buffer to map register identifiers to values. In the reorder buffer, th associative lookup is prioritized so that the reorder buffer always provides the mos recent value in the register of interest (or a tag). The reorder buffer also write values to the register file in order, so that, if the value is not in the reorder buffer, th register file must contain the most recent value. In a still further technique for reducing dependencies, associative lookup can b eliminated using a "future file." The future file does not have the properties of th reorder buffer discussed in the preceding paragraph. A value presented to the future file to be written may not be the most recent value destined for the correspondin register, and the value cannot be treated as the most recent value unless it actuall is. The future file therefore keeps track of the most recent update and checks tha each write corresponds to the most recent update before it actually performs th write. When an instruction is decoded, it accesses tags in the future file along with th operand values. If the register has one or more pending updates, the tag identifies the update value required by the decoded instruction. Once an instruction is decoded, other instructions may overwrite this instructions's source operands without bein constrained by anti-dependencies, because the operands are copied into th instruction window. Output dependencies are handled by preventing the writing as result into the future file if the result does not have a tag for the most recent value Both anti- and output dependencies are handled without stalling instruction issue. If dependencies are not removed through renaming, "interlocks" must use t enforce dependencies. An interlock simply delays the execution of an instruction unti the instruction is free of dependencies. There are two ways to prevent an instructio f om being executed: one way is to prevent the instruction f om being decoded, an the other is to prevent the instruction from being issued. To improve performance over scoreboarding, interlocks are moved from th decoder to the instruction window using a "dispatch stack." The dispatch stack is a instruction window that augments each instruction in the window with dependenc counts. There is a dependency count associated with the source register of eac instruction in the window, giving the number of pending prior updates to the sourc register and thus the number of updates that must be completed before all possibl true dependencies are removed. There are two similar dependency counts associate with the destination register of each instruction in the window, giving both th number of pending prior uses of the register (which is the number of anti dependencies) and the number of pending prior updates to the register (which is th number of output dependencies). When an instruction is decoded and loaded into the dispatch stack, th dependency counts are set by comparing the instruction's register identifiers with th register identifiers of all instructions already in the dispatch stack. As instruction complete, the dependency counts of instructions that are still in the window ar decremented based on the source and destination register identifiers of completin instructions (the counts are decremented by a variable amount, depending on th number of instructions completed). An instruction is independent when all of it counts are zero. The use of counts avoids having to compare all instructions in th dispatch stack to all other instructions on every cycle. Anti-dependencies can be avoided altogether by copying operands to th instruction window (for example, to the reservation stations) during instructio decode. In this manner, the operands cannot be overwritten by subsequent registe updates. Operands can be copied to eliminate anti-dependencies in any approach independent of register renaming. The alternative to copying operands is to interloc anti-dependencies, but the comparators and/or counters required for these interlock are costly, considering the number of combinations of source and result registers t be compared. A tag can be supplied for the operand rather than the operand itself. This tag i simply a means for the hardware to identify which value the instruction requires, s that, when the operand value is produced, it can be matched to the instruction. there can be only one pending update to a register, the register identifier can serve a tag (as with scoreboarding). If there can be more than one pending update to register (as with renaming), there must be a mechanism for allocating result ta and insuring uniqueness. An alternative to scoreboarding interlocking is to allow multiple pending update of registers to avoid stalling the decoder for output dependencies, but to handle an dependencies by copying operands (or tags) during decode. An instruction in th window is not issued until it is free of output dependencies, so the updates to eac register are performed in the same order in which they would be performed with i order completion, except that updates for different registers are out of order wit respect to each other. This alternative has almost all of the capabilities of registe renaming, lacking only the capability to issue instructions so that updates to th same register occur out of order. There appears to be no better alternative to renaming other than with a reorde buffer. Underlying the discussion of dependencies has been the assumption that th processor performs out-of-order issue and already has a reorder buffer for recoverin from mispredicted branches. Out-of-order issue makes it unacceptable to stall th decoder for dependencies. If the processor has an instruction window, it i inconsistent to limit the look ahead capability of the processor by interlocking th decoder. There are then only two alternatives: implement anti- and outp dependency interlocks in the window or remove these altogether with renaming. SUMMARY OF THE INVENTION The present invention is directed to instruction scheduling including registe renaming and instruction issuing for superscalar RISC computers. A Registe Rename Circuit (RRC), which is part of the scheduling logic allows a computer' Instruction Execution Unit (IEU) to execute several instructions at the same tim while avoiding dependencies. In contrast to conventional register renaming, th present invention does not actually rename register addresses. The RRC of th present invention temporarily buffers the instruction results, and the results of ou of-order instruction execution are not transferred to the register file until all previou instructions are done. The RRC also performs result forwarding to provid temporarily buffered operands (results) to dependant instructions. The RR contains three subsections: a Data Dependency Checker (DDC), Tag Assign Logi (TAL) and Register file Port MUXes (RPM). The function of the DDC is to locate the dependencies between the instructions fo a group of instructions. The DDC does this by comparing the addresses of the sourc registers of each instruction to the addresses of the destination registers of eac previous instruction in the group. For example, if instruction A reads a value from register that is written to by instruction B, then instruction A is dependent upo instruction B and instruction A cannot start until instruction B has finished. The DDC outputs indicate these dependencies. The outputs of the DDC go to the TAL. Because it is possible for an instruction to be dependent on more than one previous instruction, the TAL must determine whic of those previous instructions will be the last one to be executed. The presen invention automatically maps each instruction a predetermined temporary buffe location; hence, the present invention does not need prioritized associative look-up as used by convention reorder buffers, thereby saving chip area/cost and execution speed. Out-of-order results for several instructions being executed at the same time are stored in a set of temporary buffers, rather that the file register designated by the instruction. If the DDC determines, for example, that a register that instruction 6's source is written to by instructions 2, 3 and 5, then the TAL will indicate that instruction 6 must wait for instruction 5 by outputting the "tag" of instruction 5 for instruction 6. The tag of instruction 5 shows the temporary buffer location where instruction 5's result is stored. It also contains a one bit signal (called a "done flag") that indicates if instruction 5 is finished or not. The TAL will output three tags for each instruction, because each instruction can have three source registers. If an instruction is not dependent on any previous instruction, the TAL will output the register file address of the instruction's input, rather an a temporary buffer's address. The last part of the RRC are the RPMs or Register file Port MUXes. The inputs of the RPMs are the outputs of the TAL, and the select lines for the RPMs come from another part of the IEU called the Instruction Scheduler or Issuer. The Instruction Scheduler chooses which instruction to execute (this decision is based partly on the done flags) and then uses the RPMs to select the tags of that instruction. These tags go to the read address ports of the computer's register files. In the previous example, once instruction 5 has finished, the Instruction Scheduler will start instruction 6. It will select the RPM so that the address of instruction 5's result (its tag) is sent to the register file, and the register file will make the result of instruction 5 available to instruction 6. The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be better understood if reference is made to the accompanyin drawings. FIG. 1 shows a representative high level block diagram of the register renamin circuit of the present invention. FIG. 2 shows a representative block diagram of the data dependency check circui of the present invention. FIG. 3 shows a representative block diagram of the tag assignment logic of th present invention. FIG. 4 shows a representative block diagram of the register port file multiplexer of the present invention. FIG. 5 is a representative flowchart showing a data dependency check method fo IXS1 and IYS/D in accordance with the present invention. FIG's. 6A and 6B are representative flowcharts showing a tag assignmen method in accordance with the present invention. FIG. 7 shows a representative block diagram which compares an instruction Y source/destination operand with each operand of an instruction X in accordance wit an embodiment of the present invention. FIG. 8 shows a representative circuit diagram for comparator block 706 of FIG. 7 FIG. 9 shows a representative block diagram of a Priority Encoder in accordanc with an embodiment of the present invention. FIG. 10 shows a representative block diagram of the instruction scheduling logi of the present invention. DETAILED DESCRIPTION FIG. 1 shows a representative high level block diagram of an Instructio Execution Unit (IEU) 100 associated with the present invention. The goal of IE 100 is to execute as many instructions as possible in the shortest amount of time There are two basic ways to accomplish this: optimize IEU 100 so that eac instruction takes as little time as possible or optimize IEU 100 so that it can execut several instructions at the same time. Instructions are sent to IEU 100 from an Instruction Fetch Unit (IFU, no shown) through an instruction FIFO (first-in-first-out register stack storage device 101 in groups of four called "buckets." IEU 100 can decode and schedule up to tw buckets of instructions at one time. FIFO 101 stores 16 total instructions in fou buckets labeled 0-3. IEU 100 looks at the an instruction window 102. In on embodiment of the present invention, window 102 comprises eight instruction (buckets 0 and 1). Every cycle IEU 100 tries to issue a maximum number o instructions from window 102. Window 102 functions as a instruction buffer registe Once the instructions in a bucket are executed and their results stored in th processor's register file (see block 117), the bucket is flushed out a bottom 104 and new bucket is dropped in at a top 106. In order to execute instructions in parallel or out of order, care must be taken s that the data that each instruction needs is available when the instruction needs i and also so that the result of each instruction is available for any future instruction that might need it. A Register Rename Circuit (RRC), which, is part of the schedulin logic of the computer's DϋU performs this function by locating dependencies betwee current instructions and then renaming the sources (inputs) of the instruction. As noted above, there are three types of dependencies: input dependencies, outpu dependencies and anti-dependencies. Input dependencies occur when an instruction call it A, that performs an operation on the result of a previous instruction, call it B Output dependencies occur when the outputs of A and B are to be stored in the sam place. Anti-dependencies occur when instruction A comes before B in the instructio stream and B's result will be stored in the same place as one of A's inputs. Input dependencies are handled by not executing instructions until their input are available. RRC 112 is used to locate the input dependencies between curren instructions and then to signal an Instruction Scheduler or Issuer 118 when al inputs for a particular instruction are ready. In order to locate these dependencies RRC 112 compares the register file addresses of each instruction's inputs with th addresses of each previous instruction's output using a data dependency circui (DDC) 108. If one instruction's input comes from a register where a previou instruction's output will be stored, then the latter instruction must wait for th former to finish. This implementation of RRC 112 can check eight instructions at the same time so a current instruction is defined as any one of those eight from window 102. I should become evident to those skilled in the art that the present invention can easil be adapted to check more or less instructions. In one embodiment of the present invention, instructions can have from 0 to inputs and 0 or 1 outputs. Most instructions' inputs and outputs come from, or ar stored in, one of several register files. Each register file 117 (e.g., separate intege floating and boolean register files) has 32 real entries plus the group of 8 temporar buffers 116. When an instruction completes, (The term "complete" means that th operation is complete and the operand is ready to be written to its destinatio register.) its result is stored in its preassigned location in the temporary buffers 116 Its result is later moved to the appropriate place in register file 117 after all previou instructions' results have been moved to their places in the register file. Thi movement of results from temporary buffers 116 to register file 117 is calle "retirement" and is controlled by termination logic, as should become evident to thos skilled in the art. More than one instruction may be retired at a time. Retiremen comprises updating the "official state" of the machine including the computer' Program Counter, as will become evident to those skilled in the art. For example, i instruction 10 happens to complete directly before instruction II, both results can b stored directly into register file 117. But if instruction 13 then completes, its resul must be stored in temporary buffer 116 until instruction 12 completes. By havin IEU 100 store each instruction's result in its preassigned place in the temporar buffers 116, IEU 100 can execute instructions out of program order and still avoi the problems caused by output and anti-dependencies. RRC 112 sends a bit map to an Instruction Scheduler 118 via a bus 12 indicating which instructions in window 102 are ready for issuing. Instruction decod logic (not shown) indicates to Issuer 118 the resource requirements for eac instruction over a bus 123. For each resource in IEU 100 (e.g., each functional uni being an adder, multiplier, shifter, or the like), Issuer 118 scans this information an selects the first and subsequent instructions for issuing by sending issue signals ove bus 121. The issue signals select a group of Register File Port MUXes (RPMs) 12 inside RRC 112 whose inputs are the addresses of each instruction's inputs. Because the results may stay in temporary buffer 116 several cycles before goin to register file 117, a mechanism is provided to get results from temporary buffer 11 before they go to register file 117, so the information can be used as operands fo other instructions. This mechanism is called "result forwarding," and without it Issuer 118 would not be able to issue instructions out of order. This result forwardin is done in register file 117 and is controlled by RRC 112. The control signal necessary for performing the result forwarding will be come evident to those skilled i the art, as should the random logic used for generating such control signals. If an instruction is not dependent on any of the current instructions resul forwarding is not necessary since the instruction's inputs are already in register fil 117. When Issuer 118 decides to execute that instruction, RRC 112 tells register fil 117 to output its data. RRC 112 contains three subsections: a Data Dependency Checker (DDC) 108 Tag Assign Logic (TAL) 122 and Register File Port MUXes (RPM) 124. DDC 10 determines where the input dependencies are between the current instructions. TA 122 monitors the dependencies for Issuer 118 and controls result forwarding. RP 124 is controlled by Issuer 118 and directs the outputs of TAL 122 to the appropriat register file address ports 119. Instructions are passed to DDC 108 via bus 110. Al source registers are compared with all previous destination registers for eac instruction in window 102. Each instruction has only one destination, which may be a double register in one embodiment. An instruction can only depend on a previous instruction and may have up to three source registers. There are various register file source and destination addresses that need to be checked against each other for any dependencies. As noted above, the eight bottom instructions corresponding to the lower two buckets are checked by DDC 108. All source register addresses are compared with all previous destination register addresses for the instructions in window 102. For example, let's say a progra has the following instruction sequence: addR0, Rl, R2 (0) add 0, R2, R3 (1) add R4, R5, R2 (2) add R2, R3, R4 (3) The first two registers in each instruction 0-3 are the source registers, and the last listed register in each instruction is the destination register. For example, R0 and Rl are the source registers for instruction 0 and R2 is the destination register. Instruction 0 adds the contents of registers 0 and 1 and stores the result in R2. For instructions 1-3 in this example, the following are the comparisons needed to evaluate all of the dependencies: I1S1, 11S2 vs. I0D I2S1, 12S2 vs. I1D, I0D I3S1, 13S2 vs. I2D, I1D, I0D The key to the above is as follows: IXRS1 is the address of source (input) number 1 of instruction X; IXRS2 is the address of source (input) number 2 of instruction X; and DGD is the address of the destination (output) of instruction X. Note also that RRC 112 can ignore the fact that instruction 2 is output dependent on instruction 0, because the processor has a temporary buffer where instruction 2's result can be stored without interfering with instruction 0's result. As discussed before, instruction 2's result will not be moved from temporary buffers 116 to register file 117 until instructions 0 and l's results are moved to register file 117. The number of instructions that can be checked by RRC 112 is easily scaleable. In order to check eight instructions at a time instead of four, the following additional comparisons would also need to be made: I4S1, 14S2 vs I3D, I2D, I1D, I0D I5S1. I5S2 vs I4D, I3D, I2D, I1D, I0D I6S1, 16S2 vs I5D, I4D, I3D, I2D, I1D, I0D I7S1, 17S2 vs I6D, I5D, I4D, I3D, I2D, I1D, I0D There are several special cases that RRC 112 must handle in order to do the dependency check. First, there are some instructions that use the same register as an input and an output. Thus, RRC 112 must compare this source/destination register address with the destination register addresses of all previous instructions. So for instruction 7, the following comparisons would be necessary: I7S1,I7S2,I7S D vs. I6D,I5D,I4D,I3D,I2D,I1D,I0D. Another special case occurs when a program contains instructions that genera 64 bit outputs (called long-word operations). These instructions need two registers i which to store their results. In this embodiment, these registers must be sequentia Thus if RRC 112 is checking instruction 4's dependencies and instruction 1 is a lon word operation, then it must do the following comparisons: I4S1,I4S2 vs. I3D,I2D,I1D,I1D+1,I0D Sometimes, instructions do not have destination registers. Thus RRC 112 mu ignore any dependencies between instructions without destination registers and an future instructions. Also, instructions may not have only one valid source register, RRC 112 must ignore any dependencies between the unused source register (usuall S2) and any previous instructions. RRC 112 is also capable of dealing with multiple register files. When usin multiple register files, dependencies only occur when one instruction's source regist has the same address and is in the same register file as some other instruction' destination register. RRC 112 treats the information regarding which register file particular address is from as part of the address. For example, in an implementatio using four 32 bit register files, RRC 112 would do 7 bit compares instead of 5 b compares (5 for the address and 2 for the register file). Signals indicating which instructions are long-word operations or have invali source or destination registers are sent to RRC 112 from Instruction Decode Log (IDL; not shown). IDL also tells RRC 112 which register file each instruction' sources and destinations will come from or go to. A block diagram of DDC 108 is shown in FIG. 2. Source address signals arri from IFIFO 101 for all eight instructions of window 102. Additional inputs inclu long-word load operation flags, register file decode signals, invalid destination regist flags, destination address signals and addressing mode flags for all eight instructions. DDC 208 comprises 28 data dependency blocks 204. Each block 204 is describe in a KEY 206. Each block 204 receives 3 inputs, IXSl, IXS2 and IXS D. IXSl is t address of source (input) number 1 of instruction X, IXS2 is the address of sourc (input) number 2 of instruction X; and IXS D is the address of the source/destinatio (input) of instruction X. Each block 204 also receives input IYS D, which is th destination register address for some previous instruction Y. A top row 208, f example, receives I0S/D, which is the destination register address for instruction Each block 204 outputs the data dependency results to one of a corresponding b line 114. For example, the address of I2S D must be checked with operand address SI, S2 and S D of instructions 7, 6, 5, 4, and 3. Each block 204 performs the three comparisons. To illustrate these comparisons, consider a generic block 700 shown in FIG. 7, which compares instruction Ys source/destination operand with each operand of instruction X. In this example, the three following comparisons must be made: IXSl = IYS D IXS2 = IYS D IXS D = IYS D These comparisons are represented by three comparator blocks 702, 704 and 706, respectively. One set of inputs to comparator blocks 702, 704 and 706 are the bits of the IYS/D field, which is represented by number 708. Comparator block 702 has as its second set of inputs the bits of the IXSl. Similarly, comparator block 704 has as its second set of inputs the bits of the IXSl, and comparator block 706 has as its second set of inputs the bits of the IXS D. In a preferred embodiment, the comparisons performed by blocks 702, 704 and 706 can be performed by random logic. An example of random logic for comparator block 706 is shown in FIG. 8. Instruction Ys source/destination bits [6:0] are shown input from the right at reference number 802 and instruction X's source/destination bits [6:0] are shown input from the top at reference number 804. The most significant bit (MSB) is bit 6 and the least significant bit (LSB) is bit 0. The corresponding bits from the two operands are fed to a set of seven exclusive NOR gates (XNORs) 806. The outputs of XNORs 806 are then ANDed by a seven input AND gate 808. If the corresponding bits are the same, the output of XNOR 806 will be logic high. When all bits are the same, all seven XNOR 806 outputs are logic high and the output of AND gate 808 is logic high, this indicates that there is a dependency between JXS/D and IYS D. The random logic for comparator blocks 702 and 704 will be identical to that shown in FIG. 8. The present invention contemplates many other random logic circuits for performing data dependency checking, as will become evident to those skilled in the art without departing from the spirit of this example. As will further become evident to those skilled in the art, various implementation specific special cases can arise which require additional random logic to perform data dependency checking. An illustrative special data dependency checking case is for long word handling. As mentioned before, if a long word operation writes to register X, the first 32 bits are written to register X and the second 32 bits are written to register X+l. The data dependency checker therefore needs to check both resisters when doing a comparison. In a preferred embodiment, register X is an even register, X+l is an odd register and thus they only differ by the LSB. The easiest way to check both registers at the same time is to simply ignore the LSB. In the case of a store long (STLG) or load long (LDLG) operation, if X and Y only differ by the LSB bit [0], th logic in FIG. 8 would cause there to be no dependency, when there really is dependency. Therefore, for a long word operation the STLG and LDLG flags must b ORed with the output of the [0] bit XNOR to assure that all dependencies ar detected. A data dependency check flowchart for IXSl and IYS/D is shown in FIG. 5. DD 108 first checks whether IXSl and IYS D are in the same register file, as shown at conditional block 502. If they are not in the same register file there is no dependenc This is shown at block a 504. If there is a dependency, DDC 108 then determine whether IXSl and IYS/D are in the same register, as shown at a block 506. If the are not in the same register, flow proceeds to a conditional block 508 where DDC 10 determines whether IY is a long word operation. If IY is not a long word operatio there is no dependency and flow proceeds to a block 504. If IY is a long wor operation, flow then proceeds to a conditional statement 510 where DDC 10 determines whether IXSl and IYS/D+1 are the same register. If they are not, ther is no dependency and flow proceeds to a block 504. If DG31 and IYS/D+1 are th same register, flow proceeds to a conditional block 512 where DDC 108 determines i IY has a valid destination. If it does not have a valid destination, there is n dependency and flow proceeds to block 504. If IY does have a valid destination, flo proceeds to a conditional block 514 where DDC 108 determines if IXSl has a vali source register. Again, if no valid source register is detected there is no dependenc and flow proceeds to a block 504. If a valid source register is detected, DDC 108 ha determined that there is a dependency between DG31 and IYX/D, as shown at a bloc 516. A more detailed discussion of data dependency checking is found in commonl owned, copending application Serial No. 07/860,718 (Attorney Docket No. SP041 the disclosure of which is incorporated herein by reference. Because it is possible that an instruction might get one of its inputs from register that was written to by several other instructions, the present inventio must choose which one is the real dependency. For example, if instructions 2 and write to register 4 and instruction 7 reads register 4, then instruction 7 has tw possible dependencies. In this case, it is assumed that since instruction 5 came afte instruction 2 in the program, the programmer intended instruction 7 to us instruction 5's result and not instruction 2's. So, if an instruction can be dependen on several previous instructions, RRC 112 will consider it to be dependent on th highest numbered previous instruction. Once TAL 122 has determined where the real dependencies are, it must locate th inputs for each instruction. In a preferred embodiment of the present invention, th inputs can come from the actual register file or an array temporary buffers 116 RRC 112 assumes that if an instruction has no dependencies, its inputs are all in the register file. In this case, RRC 112 passes the IXSl, IXS2 and DSD addresses that came from IFIFO 102 to the register file. If an instruction has a dependency, then RRC 112 assumes that the data is in temporary buffers 116. Since RRC 112 knows which previous instruction each instruction depends on, and since each instruction always writes to the same place in temporary buffers 116, RRC 112 can determine where in temporary buffers 116 an instruction's inputs are stored. It sends these addresses to register file read ports 119 and register file 117 outputs the data from temporary buffers 116 so that the instruction can use it. The following is an example of tag assignments: 0:addr0,rl,r2 I:addr0,r2,r3 2:addr4,r5,r2 3:addr2,r3,r4 The following are the dependencies for the above operations (dependencies are represented by the symbol "#"): I1S2#I0S/D I3S1#I0S/D I3S1#I2S/D I3S2#I1S/D First, look at 10; since it has no dependencies, its tags are equal to its original source register addresses: I0SlTAG = I0Sl = r0 I0S2TAG = I0S2 = rl I0SDTAG = I0SD = r2 11 has one dependency, and its tags are as follows: IlSlTAG = IlSl = rO I1S2 TAG = I0S/D = tO where: (tO = inst.0's slot in temporary buffer) IlSDTAG = IlSD = r3 12 is also independent: I2SlTAG = I2Sl = r4 I2S2TAG = I2S2 = r5 I2SD TAG = I2SD = r2 I3S1 has two possible dependencies, I0SD and 12SD. Because TAL 122 must pick the last one (highest numbered one), I2SD is chosen. I3S1TAG = I2SD = t2 I3S2TAG = I1S/D = tl I3S/D TAG = I3S D = r4 These tags are then sent to RPM 124 via bus 126 to be selected by Issuer 118 At the same time TAL 122 is preparing the tags, it is also monitoring the outputs o DCL 130 and passing them on to Issuer 118 using bus 120. TAL 122 chooses th proper outputs of DCL's 130 to pass to Issuer 118 by the same method that i chooses the tags that it sends to RPM 124. Continuing the example, TAL 122 sends the following ready signals to Issuer 118: I0S1 INFO = 1 (Inst 0 is independent so it can start immediately) I0S2 INFO = 1 I0S D INFO = 1 I1S1 INFO = 1 I1S2 INFO= DONE[0] (DONE[0] = 1 when 10 is done) I1S/D INFO = 1 I2S1 INFO = 1 I2S2 INFO = 1 I2S D INFO = 1 1351 INFO = DONE[2] 1352 INFO = DONE[l] I3SZD READ = 1 (The DONE signals come from DCL 130 via a bus 132. In connection with th present invention, the term "done" means the result of the instruction is in temporary buffer or otherwise available at the output of a functional unit. Contrastingly, the term "terminate" means the result of the instruction is in th register file.) Turning now to FIG. 3, a representative block diagram of TAL 122 will b discussed. TAL 122 comprises 8 tag assignment logic blocks 302. Each TAL bloc 302 receives the corresponding data dependency results via buses 114, as well a further signals that come from the computer's Instruction Decode and control logi (not shown). The BKT bit signal forms the least significant bit of the tag. DONE[X flags are for instructions 0 through 6, and indicate if instruction X is done. DBLREG[X] flags indicates which, if any, of the instructions is a double Gong) word. Each TAL block 302 also receives its own instructions register addresses as inputs. The Misc. signals, DBLREG and BKT signals are all implementation dependen control signals. Each TAL block 302 outputs 3 TAGs 126 labeled IXSl, IXS2 an IXS/D, which are 6 bits. TAL 122 outputs the least significant 5 bits of each TA signal to RPMs 124 and the most significant TAG to Issuer 118. Each block 302 of FIG. 3 comprises three Priority Encoders (PE), one for SI, on for S2 and one for S/D. There is one exception however. 10 requires no tag assignment. Its tags are the same as the original SI, S2 and S/D addresses, because 10 is always independent. An illustrative PE is shown in FIG. 9. PE 902 has eight inputs 904 and eight outputs 906. Inputs 904 for PE 902 are outputs 114 from DDC 108 which show where dependencies exist. For example, in the case of source register 1 (SI), I7S1 tag assign PE 902's seven inputs are the seven outputs 114 of DDC 108 that indicate whether I7S1 is dependent on I6D, whether I7S1 is dependent on I5D, and so on down to whether I7S1 is dependent on I0D. An eighth input, shown at reference number 908, is always tied high because there should always be an output from PE 902. As stated before, if an instruction depends on several previous instructions, PE 902 will select and output only the most previous instruction (in program order) on which there is a dependency. This is accomplished by connecting the signal showing if there is a dependency on the most previous instruction to the highest priority input of the PE 902 and the signal showing if there is a dependency on the second most previous instruction to the input of PE 902 with the second highest priority and so on for all previous instructions. The input of the PE 902 with the lowest priority is always tied high so that at least one of PE 902's outputs will be asserted. Outputs 906 are used as select lines for a MUX 910. MUX 910 has eight inputs 912 to which the tags for each instruction are applied. To illustrate this, assume that 17 depends on 16 and 15, then, since 16 has a higher priority than 15, the bit corresponding to 16 at outputs 906 of PE 902 will be high. At the corresponding input 912 of MUX 910 will be I6's tag for Si (recall PE 902 is for I7S1). Because 17 is dependent on 16, the location of I6's result must be output from MUX 910 so that it can be used by 17. I6's tag will therefore be selected and output on an output line 914. I6's done flag, DONE[6] must also be output from MUX 910 so that Issuer 118 will know when I7's input is ready. This data is passed to Issuer 118 via bus 120. Since an instruction can have up to three sources, TAL 122 monitors up to three dependencies for each instruction and sends three vectors for each instruction (totalling 24 vectors) to Issuer 118. If an instruction is independent, TAL 122 signals to Issuer 118 that the instruction can begin immediately. The MSB of the tag outputs which are sent to RPMs 124 is used to indicate if the address is a register file address or a temporary buffer address. If an instruction is independent, then the five LSB outputs indicate the source register address. For instructions that have dependencies: the second MSB indicates that the address is for a 64 bit valve; the third through fifth MSB outputs specify the temporary buffer address; and the LSB output indicates which bucket is the current bucket, which is equal to the BKT signal in TAL 122. Like DDC 108, TAL 122 has numerous implementation dependent, (i.e., special cases) that it handles. First, in an embodiment of the present invention, registe number 0 of the register file is always equal to 0. Therefore, even if one instructio writes to register 0 and another reads from register 0, there will be no dependenc between them. TAL 122 receives three signals from Instruction Decode Logic (IDL not shown) for each instruction to indicate if one of that instruction's sources i register 0. If any of those is asserted, TAL 122 will ignore any dependencies for tha particular input of that instruction. Another special case occurs because under some circumstances, an instruction i bucket 0 will be guaranteed to not have any of the instructions in bucket 1 dependen on it. A four bit signal called BKTl_NODEP_ is sent to RRC 112 from the IE control logic (not shown) and if BKTl_NODEP[X] = 1 then RRC 112 knows to ignor any dependencies between instructions, 4,5,6 or 7 and instruction X. An example for TAG assignment of instruction 7's source 1 (I7S1) is shown in flowchart in FIG's. 6A-6B. TAL 122 first determines whether I7S1 is register 0, a shown at a conditional block 602. If the first source operand for 17 is register 0, th TAG is set equal to zero, and the I7Sl's INFO flag is set equal to one, as shown in block 604. If the first source operand (SI) for 17 is not register 0, TAL 122 the determines if I7S1 is dependent on I6S/D, as shown at a conditional block 606. I I7S1 is dependent on I6S D flow then proceeds to a block 610 where I7Sl's TAG i set equal to {1,DBLREG[6],0,1,0,BKT} and I7Sl"s INFO flag is set equal to DONE[6] as shown at a block 610. If either of the condition tested at a conditional block 606 i not met, flow proceeds to conditional block 612 where TAL 122 determines if I7S1 i dependent on I5S/D. If there is a dependency, flow then proceeds to block 616 wher TAL 122 sets I7Sl's TAG equal to {1,DBLREG[5],0,0,1,BKT} and I7Sl's INFO fla is set equal to DONE[5]. If the condition tested at block 612 is not met, flow proceed to a block 618 where TAL 122 determines if I7S1 is dependent on I4S D. As evident by inspection of the remaining sections of FIG's. 6A and 6B, simila TAG determinations are made depending on whether I7S1 is dependent on I4S/D I3S/D, I2S D, I1S/D and I0S/D, as shown at sections 620, 622, 624, 626 and 628 respectively. Finally, if instruction 7 is independent of instruction 0 or if al instructions in bucket 1 are independent of instruction 0 (i.e., if BKT1_NODEP[0] ■ 1), as tested at a conditional block 630, the flow proceeds to block 632 where TA 122 sets I7Sl's TAG equal to {0,I7S1} and I7Sl's INFO flag equal to 1. It should b noted for the above example that I7S1 TAG signals are forwarded directly th register file port MUXes of register file 117. The I7S1 INFO signals are sent Issuer 118 to tell it when I7's SI input is ready. A representative block diagram of Issuer 118 is shown in FIG. 10. In a preferre embodiment, Issuer 118 has one scanner block 1002 for each resource (functiona unit) that has to be allocated. In this example, Issuer 118 has scanner blocks FU1 FU2, FU3, FU4 through FU/i. Requests for functional units are generated from instruction information by decoding logic (not shown) in a known manner, which are sent to scanners 1002 via bus 123. Each scanner block 1002 scans from instruction 10 to 17 and selects the first request for the corresponding functional unit to be serviced during that cycle. a the case of multiple register files (integer, floating and/or boolean), Issuer 118 is capable of issuing instructions having operands stored in different register files. For example, an ADD instruction may have a first operand from the floating point register file and a second operand from the integer register file. Instructions with operands from different register files are typically given higher issue priority (i.e., they are issued first). This issuing technique conserves processor execution time and functional unit resources. In a further embodiment in which IEU 100 may include two ALU's, ALU scanning becomes a bit more complicated. For speed reasons, one ALU scanner block scans from 10 to 17, while the other scanner block scans from 17 to 10. This is how two ALU requests are selected. With this scheme it is possible that an ALU instruction in bucket 1 will get issued before an ALU instruction in bucket 0, while increasing scanning efficiency. Scanner outputs 1003 are selected by MUXing logic 1004. A set of SELect inputs 1006 for MUX 1004 receive three 8-bit vectors (one for each operand) from TAL 122 via bus 120. The vectors indicate which of the eight instructions have no dependencies and are ready to be issued. Issuer 118 must wait for this information before it can start to issue any instructions. Issuer 118 monitors these vectors and when all three go high for a particular instruction, Issuer 118 knows that the inputs for that instruction are ready. Once the necessary functional unit is ready, the issuer can issue that instruction and send select signals to the register file port MUXes to pass the corresponding instructions outputs to register file 117. In a preferred embodiment of the present invention, after Issuer 118 is done it provides two 8-bit vectors per register file back to RRC 112 via MUXOUTputs 1008 to bus 121. These vectors indicate which instructions are issued this cycle, are used a select lines for RPMs 124. The mpYiTrmm number of instructions that can be issued simultaneously for each register file is restricted by the number of register file read ports available. A data dependency with a previous uncompleted instruction may prevent an instruction from being issued. In addition, an instruction may be prevented from being issued if the necessary functional unit is allocated to another instruction. Several instructions, such as load immediate instructions, Boolean operations and relative conditional branches, may be issued independently, because they may not require resources other than register file read ports or they may potentially have no dependencies. The last section of RRC 112 is the register file port MUX (RPM) section 124. The function of RPMs 124 is to provide a way for Issuer 118 to get data out of register files 117 for each instruction to use. RPMs 124 receive tag information via bus 126, and the select lines for RPMs 124 come from Issuer 118 via a bus 121 and also from the computer's IEU control logic. The selected TAGs comprise read addresses that are sent to a predetermined set of ports 119 of register file 117 using bus 128. The number and design of RPMs 124 depend on the number of register files and the number of ports on each register file. One embodiment of RPMs 124 is shown in FIG. 4. In this embodiment, RPMs 124 comprises 3 register port file MUXes 402, 404 and 406. MUX 402 receives as inputs the TAGs of instructions 0-7 corresponding to the source register field SI that are generated by TAL 122. MUX 404 receives as inputs the TAGs of instructions 0-7 corresponding to the source register field S2 that are generated by TAL 122. MUX 406 receives as inputs the TAGs of instructions 0-7 corresponding to the source/destination register field S/D that are generated by TAL 122. The outputs of MUXes 402, 404 and 406 are connected to the read addresses ports of register file 117 via bus 128. RRC 112 and Issuer 118 allow the processor to execute instructions simultaneously and out of program order. An IEU for use with the present invention is disclosed in commonly owned, co-pending application Serial No. 07/817,810 (Attorney Docket No. SP015/1397.0280001), the disclosure of which is incorporated herein by reference. While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. Thus the breadth and scope of the present invention should not be Umited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims: CLAIMS What is claimed is: 1. A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands, the system comprising: (a) data dependance check means for determining data dependencies between the instructions; (b) tag assignment means for generating one of more tags to specify the location of operands, based on said data dependencies determined by said data dependance check means; and (c) register file port means for selecting said tags generated by said tag assignment means and passing said tags onto the read address ports of the register file for storing execution results. 2.The system of claim 1, wherein said data dependance check means determines said data dependencies by comparing the addresses of the source register field of each instruction to the addresses of the destination register fields. 3.The system of claim 1, further comprising temporary storage means for temporarily storing out-of-order execution results, wherein said out-of-order execution results are passed to the register files in order after execution of the set of instructions is completed. 4. A register renaming method for performing out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands, the method comprising the steps of: (1) determining data dependencies between the instructions; (2) performing at least one of in-order and out-of-order issuing of two or more of the instructions in the instruction execution unit; (3) storing, temporarily, any out-of-order results in temporary storage means; (4) generating one or more tags to specify the location of said out-of- order results based on said data dependencies; (5) selecting appropriate ones of said tags corresponding to the issued instruction; and (6) passing said selected tags onto the read address ports of the register file for one of: (i) accessing said out-of-order results; and (ii) storing execution results. δ.The method of claim 4, wherein said determining step further comprises the step of comparing the addresses of the source register field of each instruction to the addresses of the destination register fields. β.The method of claim 4, further comprising the step of storing in-order results in the register file and the temporary storage means. 7.The method of claim 4, further comprising the step of passing said out-of-order results to the register files in-order after execution of the set of instructions is completed. 8.A method for issuing instructions in a superscalar reduced instruction set computer having an instruction issuer system capable of issuing a plurality of instructions in a single cycle, the system having more than one register file sets, the method comprising the steps of: prioritizing instructions to be issued according to the number of different register file sets furnishing operands to the instruction; and issuing instructions according to said prioritizing step. 9.The method according to claim 8, wherein said prioritizing step assigns a higher priority to those instructions having operands furnished from the greater number of register file sets. 10.An instruction issuer system in a superscalar reduced instruction set computer, the system capable of issuing a plurality of instructions in a single cycle, the system having more than one set of register files, the system comprising: first means for prioritizing instructions to be issued according to the number of different register files furnishing operands to the instruction; and second means, responsive to said first means, for issuing instructions according to said priority. 11. The system according to claim 10, wherein said first means further assigns a higher priority to those instructions having operands furnished from the greater number of register files.

Inventors: GARG SANJIV, IADONATO KEVIN RAY, GARG, SANJIV, IADONATO, KEVIN, RAY
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1993
Main classification: G06F9
IPC codes: G06F9