Amplifier output stage

Abstract: An audio amplifier output stage comprises first and second solid state devices, each having a controlled current conducting path comprising first and second terminals and a controlling current conducting path, comprising at least a third terminal. The output stage also includes an uncontrolled current conducting path in antiparallel relation with each of the devices' controlled current conducting paths. A saturable reactor is positioned in series with the uncontrolled current conducting path to limit current flow therethrough during the switching of current flow from the controlled current conducting path of one of the devices to the uncontrolled current conducting path occasioned by operation of the amplifier.

Description: This invention related to improved amplifiers, especially Class D amplifiers. It is disclosed in the context of a class D audio amplifier. Class D amplifiers have many advantages such as small size, light weight, low cost, high efficiency, and reduced heat generation. However, undesirable radio frequency emissions can occur in the operation of such amplifiers. The emissions are a product of the rapid switching of substantial currents and voltages which are inherent in class D operation. These emissions can interfere with radio communication. A push pull amplifier is described in the paper by Hässig and Zoller in Elektronik 38 (1989), May 12, No. 10 (Munich). The preamble of claim 1 is based upon the disclosure of this paper. According to the present invention, there is provided a push-pull amplifier output stage comprising: first and second solid state devices, each having a controlled current conducting path comprising first and second terminals and a controlling current conducting path comprising at least a third terminal; a first uncontrolled current conducting path in antiparallel relation with one of said devices' controlled current conducting paths; and a reactor; characterised in that said output stage is an audio amplifier output stage; and in that said reactor is a saturable reactor in series with said first uncontrolled current conducting path to limit current flow therethrough during the switching of current flow from the controlled current conducting path of one of said devices to said first uncontrolled current conducting path occasioned by operation of said amplifier, said saturable reactor going into and out of saturation during operation of said amplifier. According to an illustrative embodiment of the invention, uncontrolled current conducting paths are provided in antiparallel relation with both of the devices' controlled current conducting paths, and saturable reactors are provided in series with both of the uncontrolled current conducting paths to limit current flow therethrough during the switching of current flow from both of the controlled current conducting paths to both of the uncontrolled current conducting paths occasioned by operation of the amplifier. Illustratively, the devices are first and second field effect transistors (FETs), respectively. The first and second terminals are drain and source terminals of the FETS. The third terminals are gate terminals of the FETs. The source terminal of the first FET is coupled to the drain terminal of the second FET and to a load of the audio amplifier. Further illustratively, the uncontrolled current conducting paths comprise first and second diodes. The anodes of the first and second diodes are coupled to the sources of the first and second FETs, respectively, and the cathodes of the first and second diodes are coupled to the drains of the first and second FETs, respectively. Additionally illustratively, the first and second diodes are first and second body diodes incorporated into the bodies of the first and second FETs, respectively, during manufacture of the first and second FETs. Illustratively according to the invention, an RC circuit is situated in parallel with each of the diodes. Illustratively, the audio amplifier is a class D audio amplifier. Further illustratively according to the invention, the saturable reactor comprises a bead having a passageway therethrough for receiving a conductor which is in series with the uncontrolled current conducting path. The invention may best be understood by referring to the following descriptions and accompanying drawings which illustrate the invention. In the drawings: Fig. 1 illustrates a partly block and partly schematic diagram of a class D amplifier driver and output stage according to an aspect of the invention; Fig. 2 illustrates a more detailed block and schematic diagram of part of an embodiment of the invention; and, Fig. 3 illustrates a more detailed block and schematic diagram of part of an embodiment of the invention. Referring now to Fig. 1, class D amplifiers typically employ push-pull output stages. Each FET in a push-pull configuration of the illustrated type is actually a combination of an FET switch and a diode coupled in antiparallel relation. During switching, the switch which is closing is often trying to impress a reverse voltage across a forward-biased diode opposite the switch. Stored charge in the diode momentarily causes the diode to look like a short circuit, supporting a very large reverse "shoot-through" current until the charge is swept from the diode. When the charge is dissipated, the large current "snaps off" very quickly, transmitting radio frequency energy. This energy is a primary cause of undesirable radio frequency interference (RFI) which attends the operation of such circuits. To alleviate this problem, the class D amplifier of Fig. 1 employs an ultra high permeability saturable reactor bead, such as the Toshiba Amobead™, on each switching MOSFET's drain lead. This places a saturable reactor in series with each switch/diode combination. In operation, during most of the switching cycle the ultra high permeability saturable reactors either are exposed to zero current or are in saturation and thus are not effectively in circuit. However, as either of the diodes goes from forward conduction, through zero current, and toward reverse biased, its series ultra high permeability saturable reactor comes out of saturation and momentarily provides a sufficient impedance in the path of would-be shoot through current to permit the diode's stored charge to be dissipated under lower current conditions. RFI is reduced dramatically. The addition of a small RC snubber further damps any remaining ringing tendencies. By substantially reducing the generation of RFI-producing energy, this technique provides excellent RFI performance without shielded metal enclosures and feedthrough capacitors which previously have been used in class D audio amplifiers. Turning now to Fig. 1, a basic amplifier 32 according to the present invention receives appropriately preamplified and otherwise processed signals from a logic drive source 50. The driver stage of amplifier 32 includes a final driver inverting amplifier 52 and a pair of output MOSFET switches 54, 56. Switches 54, 56 illustratively are Motorola MTP 50N06E MOSFETs. Switches 54, 56 are coupled in push pull configuration, with the inverting amplifier 52 inverting the signal which is coupled to the gate of switch 54 and providing this inverted drive signal to the gate of switch 56. Each switch 54, 56 is provided with a body diode 58, 60, respectively. Diodes 58, 60 are formed on the material from which switches 54, 56 are fabricated at the time of fabrication of the switches 54, 56 so that devices 54, 58 are in the same package and devices 56, 60 are in the same package and there are no external leads between devices 54, 58 or between devices 56, 60. The drain lead of MOSFET 54 and cathode of diode 58 are coupled by a suitable conductor 62 to the +V, supply terminal. The source lead of MOSFET 54 and anode of diode 58 are coupled through the series inductor 34 to the parallel combination of capacitor 36 and load 38. The source lead of MOSFET 54 and anode of diode 58 are also coupled to the drain lead of MOSFET 56 and cathode of diode 60 by a suitable conductor 64. The source lead of MOSFET 56 and anode of diode 60 are coupled to the -V, supply terminal. A high magnetic permeability bead 66 is placed on each of conductors 62, 64. During switching of MOSFETs 54, 56, as the polarities of the voltages across diodes 58, 60 reverse and the carriers begin to be swept out of the diodes 58, 60 as a result of this reversal, the tendency of the currents in diodes 58, 60 to surge uncontrolled in conductors 62, 64 is buffered by the saturable reactors 66. Since the reactors 66 saturate at relatively low current flows, the only times they affect the currents in conductors 62, 64 is during this reversal of the direction of current flow in conductors 62, 64. The rest of the time, that is, during periods of high current flow or no current flow in conductors 62, 64, saturable reactors 66 are invisible to the circuit of Fig. 1. Turning now to the more detailed schematic diagram of Fig. 2, the various illustrated pin numbers on the illustrated integrated circuits and devices refer to the specific integrated circuits and devices which have already been identified or will be identified herein. However, that does not constitute a representation, nor should any such representation be inferred, that there are no integrated circuits or devices other than those identified herein that will perform the functions performed by the identified integrated circuits and devices. Common mode noise rejection in the input signal V i is achieved by an input difference amplifier 80 which illustratively is one half of a National Semiconductor LM833. V i is coupled across the + and - input terminals of difference amplifier 80. Identical 10 K input resistors 12' are provided in series between the V i terminals and the respective + and - input terminals of amplifier 80. A feedback network including a parallel 22.1K resistor and a 47pF capacitor is coupled between the output terminal of amplifier 80 and its - input terminal. An identical parallel RC network is coupled between the + input terminal of amplifier 80 and the signal common. The output terminal of amplifier 80 and the signal common are coupled through identical 3.65K resistors to the - and + input terminals, respectively, of integrating difference amplifier 10. As previously noted, amplifier 10 illustratively is also half of an LM833 and illustratively is the other half of the same LM833 of which amplifier 80 is half. Consequently, +V s is illustrated connected to pin 8 of amplifier 80 and -V s , which in the illustrated embodiment is the chassis voltage of the circuit, is illustrated connected to pin 4 of amplifier 10. The remaining power supply connections to these amplifiers are made on the integrated circuit chip on which they are realized. A .0033 µ F integrating capacitor 14 is coupled between the output terminal of amplifier 10 and its - input terminal. The + input terminal of amplifier 10 is coupled through a .0015 µ F capacitor to the - input terminal of difference amplifier 16, and through a .0015 µ F capacitor to the circuit common. The output terminal of amplifier 10 is coupled to the + input terminal of difference amplifier 16 and to the - input terminal of difference amplifier 18. The + input terminal of amplifier 18 is coupled to the circuit common. Again, difference amplifiers 16, 18 are configured as a window comparator 22, and are realized on a National Semiconductor LM319 integrated circuit whose power supply terminals, pins 11 on the one hand and 3, 6 and 8 on the other, are coupled across the +V s and -V s (chassis) supply terminals. The output terminals 24 and 26, respectively, of amplifiers 16, 18 are coupled to the S and R input terminals, respectively, of SR flip flop 28. Flip flop 28 is realized by two, 84, 86, of the two-input NAND gates of an RCA CD4011B quad, two-input NAND gate integrated circuit. 3K pull up resistors couple the S and R input terminals, pins 6 and 1, respectively, of flip flop 28 to switched +V s . Pin 14 of flip flop 28 is also coupled to switched +V s . Pin 7 of flip flop 28 is coupled to -V s (chassis). The output terminal of NAND gate 84 is coupled to the remaining input terminal of NAND gate 86 and the output terminal of NAND gate 86 is coupled to the remaining input terminal of NAND gate 84. Both input terminals of each of the two remaining NAND gates on the CD4011B are coupled to -V s and their output terminals are left open. The drive for the output FETs is provided,by two identical output driver circuits 88, 90, only one of which will be described in further detail here. The Q output, pin 4, of flip flop 28 is coupled to the gate electrode of an FET 92, which illustratively is a type 2N7000 FET. The source of FET 92 is coupled to -V s and its drain is coupled through a 1K resistor to +3V s which is generated as will be described hereinafter. The drain of FET 92 is also coupled through an 82 Ω resistor to the joined bases of complementary NPN and PNP transistors 94, 96 which illustratively are types 2N4401 and 2N4403 transistors, respectively. The collector of transistor 94 is coupled to +3V s . The collector of transistor 96 is coupled to -V s . Their emitters are joined and form the output terminal 98 of driver circuit 88. The corresponding output terminal of driver circuit 90 is identified by the reference number 100. Each output transistor 54, 56 and its associated flyback diode 58,60, respectively, in the embodiment of Fig. 1 are realized in the embodiment of Fig. 2 by a pair of FETs 54-1, 54-2; 56-1, 56-2, respectively. As previously noted, the flyback diodes are incorporated into the FETs during the manufacture of the FETs. FETs 54-1 and 54-2 serve to provide a pathway for the charging of a .01 µ F capacitor 102 in a first sense (source of FET 54-1 going more positive with respect to drain of FET 54-2) between the +V s and -V s terminals. FETs 56-1 and 56-2 serve to provide a pathway for discharging capacitor 102 in the first sense or charging it in a second, opposite sense (source of FET 56-2 going more positive with respect to drain of FET 56-1) between the +V s and -V s terminals. The drains of FETs 54-1 and 56-2 are coupled to +V s . The sources of FETs 54-2 and 56-1 are coupled to -V s . The source and drain, respectively, of FETs 54-1 and 56-1 are coupled through capacitor 102 and a series 1Ω ring damping resistor 104 to the drain and source, respectively, of FETs 54-2 and 56-2, respectively. The gates of FETs 54-1 and 54-2 are coupled to terminal 100. The gates of FETs 56-1 and 56-2 are coupled to terminal 98. FETs 54-1, 54-2, 56-1 and 56-2 thus drive the voltage across capacitor 102 up and down between the +V s and -V s supply terminals based upon the switching voltages at the Q and Q terminals, pins 4 and 3, respectively, of flip flop 28. Feedback is provided from the source of FET 54-1 and the drain of FET 54-2 through 10K feedback resistors 39', 39' to the + and - input terminals, respectively, of amplifier 10. The speaker 38 and its associated circuitry 106 are coupled in parallel with the series RC combination 102, 104. The associated circuitry 106 includes a single turn saturable reactor 66 in series with the drain of each of FETs 54-2, 56-2. Reactors 66 are oriented in opposite senses so that, upon any change in current flow in circuit 106, the fields in reactors 66 cancel each other. A nine-turn inductor 34-1, 34-2 is in series between each reactor 66 and a respective terminal of speaker 38. A pair of .39 µ F capacitors 36-1 and 36-2 in series are coupled across the speaker 38 terminals. A 2.2 µ F capacitor 36-3 is coupled in parallel with series capacitors 36-1 and 36-2. The junction of capacitors 36-1 and 36-2 is coupled to the -V s terminal. Switching pulses appear across the RC series combination 102, 104 during operation, owing to the recovery of energy stored in the magnetic fields of inductors 34-1 and 34-2. These pulses are coupled through 18 µ F, 35 VDC capacitors 114, 116 to a full wave diode bridge rectifier 117 which is coupled through a 20Ω resistor to the switched +V s terminal. Rectifier 117 rectifies these pulses to provide a +3V s source. They are filtered and stored by a 120 µ F, 35 VDC capacitor 118 from which +3V s is supplied to driver circuits 88, 90. A K 2 (V s + V i ) (V s - V i ) hysteresis generator 42 includes an operational transconductance amplifier 120 of, for example, a ROHM BA6110 integrated circuit 122. The I abc terminal, pin 4, of integrated circuit 122 is coupled through a 10K series resistor to the output terminal of amplifier 80 to receive the V i signal. V i is also coupled from the output terminal of amplifier 80 through a 10K series resistor to the + input terminal, pin 1, of integrated circuit 122. + V s is coupled through a 10K series resistor to the I d terminal, pin 3, of integrated circuit 122 and through the series combination of two forward biased diodes, illustratively type 1SS133 diodes, and a 10K series resistor to the - input terminal, pin 2, of integrated circuit 122. +V s is also coupled to pins 7 and 9 of integrated circuit 122. -V s is coupled to pin 5 of integrated circuit 122. Pin 6, the output terminal of operational transconductance amplifier 120, is coupled through a 15K resistor to the circuit common, through a 220pF capacitor to -V s (chassis), through a 300K resistor to +V s , and to the + input terminal of a difference amplifier 124 which is configured as a unity gain buffer amplifier. That is, the output terminal of amplifier 124 is coupled to its - input terminal. The output signal from amplifier 124 is coupled to the - input terminal of amplifier 16. Amplifier 124 illustratively is one fourth of a Motorola type MC34074 quad integrated circuit operational amplifier. Muting transistors are provided at appropriate locations throughout the circuit of Fig. 2. These include transistor 126, the collector and emitter of which are coupled across capacitor 14, and the base of which is coupled through a 10K resistor to a suitable source of muting signal. The presence of muting signal on the base of transistor 126 shorts the voltage across capacitor 14. The collector of a muting transistor 128 is coupled to the I abc terminal of operational transconductance amplifier 120. The base of transistor 128 is coupled through a 100K resistor to the muting signal source and through a .047 µ F capacitor to -V s . The emitter of transistor 128 is also coupled to -V s . A muting signal on the base of transistor 128 shorts the I abc signal on pin 4 of the operational transconductance amplifier 120 to -V,. Transistors 126, 128 illustratively are type 2N3904 transistors. The collector of an additional muting transistor 130 is coupled through a suitable diode, illustratively a type 1SS133, to the drain terminal of FET 92 in each of driver circuits 88, 90. The emitter of transistor 130 is coupled to -V s . The base of transistor 130 is coupled through a 10K resistor to the muting signal source. The muting signal shorts the drive signal for transistors 94, 96 in each of circuits 88, 90 to -V s . Transistor 130 illustratively is a type 2N4401 transistor. A suitable power supply for the amplifier of Fig. 2 is illustrated in Fig. 3. A multiple section LC filter 132 is coupled across a 2V, source, such as a 12VDC vehicle battery. The more negative terminal of the source is denominated -V,. Filter 132 includes a .047 µ F capacitor 134 across the source, a series 100 µ H inductor 136 and 1500 µ F, 16VDC capacitor 138 across capacitor 134, and a series 10 µ H inductor 140 and 3000 µ F, 16VDC capacitor 142 across capacitor 134. The voltage which appears at the common terminal of inductor 140 and capacitor 142 is denominated +V s . Overvoltage protection is provided by the series combination of a 1K resistor 144 and a zener diode 146 (illustratively a type 1N5246B) across the common terminal of inductor 140 and capacitor 142 and -V s . The junction of resistor 144 and zener diode 146 is coupled through a 1K resistor to the base of a PNP transistor 148. Transistor 148 illustratively is a type 2N3906. The emitter of transistor 148 is coupled to +V s and its collector is coupled to the base of a PNP transistor 150, illustratively a Motorola type MPS-A56. The emitter of transistor,150 is coupled to +V s . The base of transistor 150 is also coupled to +V s through a 2K resistor, and to the collector of an NPN transistor 152 through a 2K resistor. The emitter of transistor 152 is coupled to -V s . The base of transistor 152 is coupled through a 10K resistor to an on/off signal source. Transistor 152 illustratively is a Motorola type MPS-A06. The collector of transistor 150 forms the switched +V s supply. The collector of transistor 150 is coupled through series 33.2K and 68.1K resistors 156, 158, respectively, to -V s , the amplifier chassis. The common terminal of resistors 156, 158 is coupled to the - input terminal of a difference amplifier 160, the output terminal of which is coupled through a 680pF capacitor to its - input terminal to provide feedback thereto. Series 1K and 5.1K resistors 162, 164, respectively, couple the collector of transistor 150 to the output terminal of amplifier 160. The emitter of a transistor 166 (illustratively a type 2N4403) is coupled to the collector of transistor 150. The base of transistor 166 is coupled to the common terminal of resistors 162, 164. The collector of transistor 166 is coupled through a series voltage divider including a 120K resistor 165 and a 2.7K resistor 167 to -V s . The junction of resistors 165, 167 is coupled to the base of transistor 152. The collector of transistor 166 is also coupled through four series forward-biased diodes 168 (illustratively, type 1SS133s) and a 5.1K resistor 170 to - V s . The common terminal of diodes 168 and resistor 170 is coupled to the + input terminal of amplifier 160. The collector of transistor 166 forms the regulated +V s terminal of the supply of Fig. 3. Identical parallel RC networks 171, each including a 10K resistor 172 and a .047 µ F capacitor 174, are coupled in series across the regulated +V s and -V s terminals. The common terminal of these two RC networks 171 is coupled to the + input terminal of a difference amplifier 176. Networks 171 divide in half the +V s to -V s voltage. This voltage is buffered by amplifier 176, which is configured as a unity gain amplifier, to provide at the output terminal of amplifier 176 the signal common for the circuits of Figs. 2-3. The muting signals for transistors 126, 128 and 130 of Fig. 2 are developed from the regulated +V s supply through a series RC time constant circuit including 4.7M resistor 180 and a .33 µ F capacitor 182. This series circuit is coupled across the regulated +V s and -V s terminals, and the common terminal of resistor 180 and capacitor 182 is coupled to the + input terminal of a difference amplifier 184. Signal common is coupled to the - input terminal of amplifier 184. The output terminal of amplifier 184 is coupled through a series resistive voltage divider including a 10K resistor 186 and a 1K resistor 188 to -V s . The common terminal of resistors 186, 188 is coupled to the base of an NPN transistor 190, which illustratively is a type 2N3904. The emitter of transistor 190 is coupled to -V s . The muting signal is formed on the collector of transistor 190, which is coupled to the +3V s supply (Fig. 2) through a 5.1K resistor. Amplifiers 160, 176 and 184 illustratively are three fourths of the Motorola type MC34074 quad operational amplifier integrated circuit from which buffer amplifier 124 (Fig. 2) was realized.

Claims: A push-pull amplifier output stage (32) comprising: first and second solid state devices (54,56), each having a controlled current conducting path comprising first and second terminals and a controlling current conducting path comprising at least a third terminal; a first uncontrolled current conducting path (58;60) in antiparallel relation with one of said devices' controlled current conducting paths; and a reactor (66); characterised in that said output stage is an audio amplifier output stage; and in that said reactor is a saturable reactor (66) in series with said first uncontrolled current conducting path (58;60) to limit current flow therethrough during the switching of current flow from the controlled current conducting path of one (54;56) of said devices to said first uncontrolled current conducting path (58;60) occasioned by operation of said amplifier (32), said saturable reactor going into and out of saturation during operation of said amplifier. The apparatus of claim 1 further comprising a second uncontrolled current conducting path (58;60), in antiparallel relation with the other of said devices' controlled current conducting paths. The apparatus of claim 2, further comprising a second saturable reactor (66) in series with said second uncontrolled current conducting paths (58;60) to limit current flow therethrough during the switching of current flow from the controlled current conducting path of the other of said devices to said second uncontrolled current conducting path (58;60) occasioned by operation of said amplifier (32). The apparatus of any one of the preceding claims, further comprising an RC circuit (102,104) in parallel with the or both uncontrolled current conducting paths (58,60). The apparatus of any one of the preceding claims, further characterized in that one or both of the devices (54,56) comprise(s) field effect transistors (FETs), the first and second terminals are drain and source terminals of the FET or FETs (54,56), the third terminal or terminals is or are a gate terminal or gate terminals of the FET or FETS (54,56), and the source terminal of the first FET (54) is coupled to the drain terminal of the second FET (56), where present, and to a load (34, 36, 38) of the audio amplifier. The apparatus of claim 5, further characterized in that the uncontrolled current conducting path or paths (58,60) comprise first (58) and, where present, second (60) diodes, the anode or anodes of which is or are coupled to the source or sources of the first and, where present, second FETs (54,56), respectively, and the cathode or cathodes of which is or are coupled to the drain or drains of the first, where present, and second FETs (54,56), respectively. The apparatus of claim 6, further characterized in that the first and, where present, second diodes (58,60) are first and, where present, second body diodes (58,60) incorporated into the body or bodies of the first and, where present, second FETs (54,56), respectively, during manufacture of the first and, where present, second FETs (54,56). The apparatus of any preceding claim, further characterized in that the audio amplifier (32) is a class D audio amplifier. The apparatus of any one of the preceding claims, further characterized in that the or each saturable reactor (66) comprises a bead having a passageway therethrough for receiving a conductor (62,64), which conductor (62,64) is in said series with said uncontrolled current conducting path (58,60).

Inventors: MCCORKLE DAVID P, MCCORKLE, DAVID P.
Applicants: HARMAN INT IND, HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED
Application year: 1993
Main classification: H03F3
IPC codes: H03F3