APPARATUS AND METHOD FOR CONTROLLING CURRENT OF VARIABLE SPEED DRIVER

Abstract: In a PWM inverter using a three-arm modulation method, the apparatus and method are for controlling the current without missing the zero vector by switching the method to a two-arm modulation method near the voltage saturation. A PWM inverter using a three-arm modulation method comprises a timing data generating unit (32) which generates the timing data for the three-arm modulation based on the voltage vector times Tλ, Tµ, and T₀ from a PWM pattern operating unit (31), a timing change-over switch (33) which switches over this timing data to each phase time, and a timing data generating unit (41) which generates the timing data for the two-arm modulation from the voltage vector times. The zero vector time T₀ is compared with the set value K.Tdly for the dead time compensation by a comparison circuit (45) having the so-called hysteresis. Thus, if the zero vector time becomes short, the data generated by the timing data generating unit (41) are output to the timing change-over switch (33) by a modulation change-over switch (47) so that the PWM pattern is for the two-arm modulation method.

Description: TECHNICAL FIELD The present invention relates to an apparatus in accordance with the preamble of claim 1 for carrying out a current control for a so-called variable speed driving system (hereinafter, referred to as a variable speed driver), which improves a current control characteristic in a proximity to a voltage saturation in an electric current control system of a voltage type PWM inverter, and to a method in accordance with the preamble of claim 4 for carrying out the current control therefor. BACKGROUND ART An apparatus and a method of the kind set forth in the preambles of claims 1 and 4 are known from DE-A-38 17 338, which describes a method and an apparatus for switching from a three-phase modulation to a two-phase modulation in dependence on the magnitude of the desired value of the voltage vector V. A discussion of the prior art will now be given with reference to Fig. 1, which shows a structure of a variable speed driver using a voltage type PWM (Pulse Width Modulation) inverter disclosed in a Japanese Patent Application No. Heisei-2-7983 filed on January 17, 1990. In Fig. 1, numeral 1 denotes a vector control section using data on a speed or torque instruction and speed detection and so forth, numeral 2 denotes an ACR (current) control section which carries out current control calculations in response to a current instruction derived from the vector control section, numeral 3 denotes a PWM pattern generator which calculates a three-phase PWM pattern according to a voltage amplitude of a voltage space vector and phase instruction derived from the ACR control section and issues a PWM instruction on the basis of the calculated PWM pattern, numeral 4 denotes a dead time compensator, numeral 5 denotes a gate signal circuit, numeral 6 denotes a drive circuit, numeral 7 denotes an inverter circuit, and numeral 8 denotes an induction motor. Furthermore, in Fig. 1, numeral 9 denotes a voltage detector, numeral 10 denotes a current detector, numeral 11 denotes a speed detector, numeral 12 denotes a sample hold circuit which holds an instantaneous output current in synchronization with an intermediate sample hold signal of a 0 (zero) vector from the PWM pattern generator until an A/D conversion is carried out, numeral 13 denotes an A/D converter, numeral 22 denotes an adder which derives a power supply speed ω o from a rotor speed ω r of the speed detector 11 and a slip angular velocity ω s . Fig. 5 shows a circuit block of the PWM pattern generator 3. In Fig. 5, numeral 31 denotes a PWM pattern calculation block which receives a voltage instruction V| derived from the ACR control section 1, an output voltage phase  restricted between 60° from an output voltage phase instruction v, a DC power supply voltage Vdc, and PWM carrier wave period (PWM time) Tc. The PWM pattern calculation block calculates the PWM pattern using a circle approximation method, and outputs voltage vector times T λ and T µ whose phases are mutually different by 60°, and 0 vector time To. Next, numeral 32 denotes a three-arm modulating time data preparation section which prepares time data such that 0 vector time To is divided into half To/2 to both sides of the voltage vector times T λ and T µ during a half PWM time Tc/2 as shown in Fig. 6 and outputs time data of T 1 , T 2 , and T 3 In addition, numeral 33 denotes a time changeover switch which converts the time data of T 1 , T 2 , and T 3 into each phase voltage time Tu, Tv, and Tw, and numeral 34 denotes an ON/OFF switching circuit which performs the switching of Tu, Tv and Tw and outputs each phase voltage signal Vu, Vv, and Vw (PWM pattern). It is noted that, in Fig. 5, numeral 35 denotes a mode selection circuit for every 60° of the output voltage phase v from the ACR control section, numeral 36 denotes a reference phase output table which receives the output signal of the every-60° mode circuit 35 and outputs a reference phase ψλ for every 60°, numeral 37 (namely, a symbol ±0 in Fig. 5) denotes a subtractor which subtracts the reference phase ψλ for every 60° from the output voltage phase v and outputs the output voltage phase  restricted between 60° to the PWM pattern calculation block 31, numeral 38 denotes a switch selection table which controls the time changeover switch 33 according to the output of the every-60° mode selection circuit 35 for every 60° and numeral 39 denotes a switching ON/OFF control circuit which controls the ON/OFF switching circuit according to the PWM time Tc and performs the sampling operation for the current. Anyway, the above-described PWM pattern is calculated using the circle approximation method with 0 vector time To being divided into half To/2 to be inserted into both sides of the times Tλ and Tµ to output the time data and with the current being coupled at an interval point of the PWM pattern (this is hereinafter referred to as a three-arm modulation method) . This method results in a situation such that as the output voltage becomes higher, a width of 0 vector becomes narrower. As the width of 0 vector becomes narrower, a defect (hereinafter, referred to simply as 0 vector defect) occurs due to a dead time compensation. At this time, a locus of a current vector is moved toward a direction at which a radius becomes larger. Figs. 7 (A) and 7 (B) show vectors before 0 vector defect and those after 0 vector defect. As shown in Fig. 7 (B), 0 vector interval of time at a point B is moved to a point D due to the dead time compensation. In a case where 0 vector is defected at the point of B and 0 vector appears earlier at the point of D, a locus of the current vector is as shown in Fig. 8. In this case, the locus of the current vector is the same at points of [1] and [2] but the locus thereof becomes long in time at a point of [3]. Therefore, a large movement of the current vector occurs. Since the current vectors of points of [5] and [6] remain unmoved, the current vector is present at a position translated from the points of [5] and [6] by an interval elongated at the point of [3] as compared with a locus of a current vector (not shown) in the case of Fig. 7 (A) in which 0 vector is not defected. The interval of time of the vector at a point of [7] becomes shorter by the increase in the 0 vector. The 0 vector interval at a point of [8] becomes longer by 0 vector interval which should be in the interval of [3]. Consequently, an end of [9] coincides with a point of the beginning of [1]. In other words, if 0 vector defect occurs, a point of the final locus of the current vector becomes equal to a part wherein 0 vector is not present. However, the locus during that interval is translated toward a direction at which the current radius becomes large. Therefore, an integrated value of the current at that interval becomes larger than that of the current in which 0 vector defect is not present. Consequently, the current becomes different according to the position at which 0 vector is inserted even, though the PWM pattern is generated with the same voltage component. With the above-described problem in mind, it is an object of the present invention to provide an apparatus and method for carrying out a current control for a variable speed driver which improve the ACR control characteristic at a position placed in a proximity to a voltage saturation by exchanging the PWM pattern from the three-arm modulation method to the two-arm modulation method at a vicinity to the voltage saturation, the ACR control system being unchanged. DISCLOSURE OF TEE INVENTION The apparatus according to the present invention for carrying out a current control for the variable speed driver including a PWM inverter comprises: a) a PWM pattern calculation section which calculates a three-phase PWM pattern from the voltage instruction of a current control section and an output voltage phase; b) a three-arm modulation time point data preparing section which prepares a three-arm modulation time point data from voltage vector times including 0 vector time calculated by the PWM pattern calculation section; c) a time changeover switch which performs the switching of the time point data for respective time phases; d) a two-arm modulation time point data preparing section which prepares time point data in a two-arm modulation method from said voltage vector times; and e) a modulation changeover switch which is so constructed as to switch said three-arm modulation time point data and said two-arm modulation time point data in response to the switching signal and output a signal indicative of the modulation switching to said time changeover switch f) a comparator which is os constructed as to compare said 0 vector time and dead time compensation set value and to produce a three-arm/two-arm switching signal when the 0 vector time becomes shorter, whereby the three-arm and two-arm modulation methods can be switched according to a magnitude of the voltage instruction. In addition, the comparator may alternatively have a characteristic of, the so-called, hysteresis or window type (two threshold levels of the comparator are changed according to the input direction of signal). Furthermore, The comparator may alternatively compare the 0 vector time and a time which is proportional to the dead time compensation set value. In addition, the method for carrying out the current control for the variable speed driver comprises the following steps: a) calculating a three-phase PWM pattern from a voltage instruction V and output voltage phase  of a current control section; b) preparing the time point data for a three-arm modulation mode from voltage vector times including 0 vector time To during the calculation of the three-arm PWM pattern; c) performing each phase time of the time point data using a time changeover switch; d) preparing the time point data of the two-arm modulation method from said voltage vector times; e) switching between the three-arm modulation time point data and two-arm modulation point data in response to a three-arm/two-arm modulation switching signal so as to use a modulation switch to output to the time changeover switch, characterized in that said 0 vector time and a dead time compensation set value are compared, said three-arm/two-arm modulation switching signal is output when 0 vector time becomes shorter, whereby the switchings between three-arm modulation method and two-arm modulation method are carried out according to a magnitude of the voltage instruction. f) said 0 vector time and a dead time compensation set value are compared, said three-arm/two-arm modulation switching signal is output when 0 vector time becomes shorter; BRIEF DESRIPTION OF THE DRAWINGS Fig. 1 is a circuit block diagram of a variable speed driver disclosed in the above-identified Japanese Patent Application No. Heisei 2-7983. Fig. 2 is a functional block diagram of a PWM pattern generator indicating a preferred embodiment according to the present invention. Fig. 3 is an explanatory view of a 0 vector arrangement in the preferred embodiment of the PWM pattern generator shown in Fig. 2. Fig. 4 is an explanatory view of a locus of a current vector in the preferred embodiment of the PWM pattern generator shown in Fig. 2. Fig. 5 is a functional block diagram of a conventional PWM pattern generator related to Fig. 1. Fig. 6 is an explanatory view of a time data and time point data in a three-arm modulation method. Fig. 7 is an explanatory view of movement of 0 vector. Fig. 8 is an explanatory view of the current vector locus when the 0 vector is moved. BEST MODE FOR CARRYING OUT THE INVENTION: Hereinafter, reference will be made to the drawings in order to facilitate a better understanding of the present invention. Fig. 2 shows a PWM pattern generator in a preferred embodiment according to the present invention. It is noted that the same reference numerals as those shown in Fig. 5 designate the corresponding elements and the explanation of the same elements as those shown in Fig. 5 will be omitted here. In Fig. 2, numeral 32 denotes a three-arm modulation time data preparing section, numeral 41 denotes a two-arm modulation time data preparing section constituted by first and second times data preparing sections denoted by numerals 42 and 43. Numeral 42 denotes a time data preparing section which receives voltage vector times Tλ and Tµ and 0 vector time To from the PWM pattern calculation block 31, which concentrates the 0 vector time To into positions behind the times Tλ and Tµ and which outputs the times data of T1, T 2 , and T 3 . Numeral 43 denotes a time point data preparing section which receives the times Tλ, Tµ, and To and outputs the time point data of T 1 , T 2 , and T 3 with the 0 vector time To concentrated into positions before the times Tλ and Tµ. In addition numeral 45 denotes a comparator of a so-called hysteresis (window-formed) type which receives both a value K•Tdly in which a dead time compensation set value Tdly is multiplied by a coefficient K at a percentage circuit block 44 and the 0 vector time interval To and outputs a three-arm/two-arm modulation switching signal when To < K•Tdly. Furthermore, numeral 46 denotes a switching selection table which receives outputs of the three-arm/two-arm modulation switching signal circuit (comparator) 45, of the every-60° mode selection circuit 35, and of the switching ON/OFF control circuit 39, and outputs the three-arm/two-arm modulation switching data. In addition, numeral 47 denotes a modulation changeover switch controlled by the data on the switching selection table 46. At the time of the three-arm modulation mode, the modulation changeover switch 47 directly outputs the time point data T 1 , T 2 , and T 3 derived at the time point data preparing section 32 in the form of T' 1 , T' 2 , and T' 3 Thus, the three arm-modulation mode, the modulation changeover switch 47, permits the PWM pattern generated in the three-arm modulation method to be output from the ON/OFF switching circuit 34. On the other hand, at the time of the two-arm modulation mode, the time (point) data preparing sections 42 and 43 modify the time point data T 1 , T 2 , and T 3 , as shown in Fig. 3, relative to the three-arm modulation mode in which the 0 vector time interval To during the conventional PWM half period is divided into half To/2 and To/2 is distributed into both sides before and after the voltage vector intervals Tλ, Tµ. That is to say, the following modifications are made in the two-arm modulation mode: (1) The 0 vector time during the half PWM period To/2 is directly set to either ends of time Tλ or Tµ. (2) The time point data T 1 , T 2 , and T 3 is determined such that the half PWM period To/2 is determined in which side of the times Tλ and Tµ the half PWM period lies so that the 0 vector time continues during the next half PWM period 0 vector time. (3) Points collecting 0 vector time To are modified for each output voltage phase 60° interval from the points to be objective thereof. These steps (1) through (3) are switched according to the data of the switch selection table 46, the time point data T' 1 , T' 2 , and T' 3 are output so that the two-arm modulation method PWM pattern from the ON/OFF switching circuit 34 is output (corresponds to the two-arm modulation which is described an Page 809 of Electric Engineering paper, volume D. 109, No. 11 published on 1989). At time time, the current sampling may be carried out for each PWM half period conventionally. A weight center between one 1 PWM period of the current locus as shown in Fig. 4 is sampled. Hence, the ACR control system of Fig. 1 (disclosed in Japanese Patent Application No. Heisei 2-7983) can directly be applied to the current sampling. INDUSTRIAL APPLICATION POSSIBILITY As described hereinabove, in the apparatus and method for carrying out the current control of the variable speed driver according to the present invention, when the output voltage becomes high and width of the 0 vector becomes narrower, a 0 vector defect will occur on the PWM pattern in the three-arm modulation method. To overcome this, the comparator compares the 0 vector time from the PWM pattern calculation section with the dead time compensation set value. Before the occurrence in the 0 vector defect, the switching signal is transmitted to the modulation change-over switch. The modulation changeover switch changes the time data in the case of the three-arm modulation method to the time data in the case of the two-arm modulation method, outputs it to the time changeover switch so that the current control by means of to the PWM pattern of the two-arm modulation method can appropriately be switched. Although the two-arm modulation method has about twice the current ripple as compared with the three-arm modulation method, the width of the 0 vector interval is twice that at the time of the three-arm modulation method so that the current control without 0 vector defect at the proximity to the voltage saturation can be achieved even though the output voltage becomes higher. In addition, since the, so-called, hysteresis (window form) characteristic is provided for the comparator, frequent repetitions between the two-arm modulation and three-arm modulation can no longer be achieved in the proximity to the voltage saturation. Furthermore, since the time to be compared with the 0 vector time is a value in which the rate or percentage is multiplied by the dead time compensation value, the percentage is so modified that the switching timing between the three-arm modulation mode and the two-arm modulation time can be adjusted in response to the voltage instruction. As described hereinabove, the present invention can have various superior applications in the industrial field.

Claims: An apparatus for carrying out a current control including a PWM inverter, comprising: a) a PWM pattern calculation section which calculates a three-phase PWM pattern (Vu, Vv, Vw) from the voltage instruction (/V/) of a current control section (2) and an output voltage phase () ; b) a three-arm modulation time point data preparing section which prepares a three-arm modulation time point data (T 1 , T 2 , T 3 ) from voltage vector times (Tλ-, Tµ, To) including 0 vector time (To) calculated by the PWM pattern calculation section (31); c) a time changeover switch (33) which performs the switching of the time point data for respective time phases; d) a two-arm modulation time point data preparing section (31, 41) which prepares time point data (T 1 , T 2 , T 3 ) in a two-arm modulation method from said voltage vector times (Tλ-, Tµ, To); and e) a modulation changeover switch (47) which is so constructed as to switch said three-arm modulation time point data and said two-arm modulation time point data in response to the switching signal and output a signal indicative of the modulation switching to said time changeover switch (33), characterized in that said apparatus further comprises: f) a comparator (45) which is so constructed as to compare said 0 vector time (To) and dead time compensation set value (K•Tdly) and to produce a three-arm/two-arm switching signal when the 0 vector time (To) becomes shorter, whereby the three-arm and two-arm modulation methods can be switched according to a magnitude of the voltage instruction. An apparatus for carrying out a current control including a PWM inverter as set forth in claim 1, wherein said comparator (45) has a window-formed characteristic. An apparatus for carrying out a current control including a PWM inverter as set forth in claim 1 or claim 2, wherein a time to be compared with the 0 vector time by means of said comparator (45) is a value in which a percentage (K) is multiplied by a dead time compensation set value Tdly). A method for carrying out a current control including a PWM inverter, comprising the steps of: a) calculating a three-phase PWM pattern from a voltage instruction (V) and output voltage phase () of a current control section; b) preparing the time point data (T 1 , T 2 , T 3 ) for a three-arm modulation mode from voltage vector times (Tλ, Tµ, To) including 0 vector time (T)o during the calculation of the three-arm PWM pattern; c) performing each phase time (Tu, Tv, Tw) of the time point data (T 1 , T 2 , T 3 ) using a time changeover switch (33); d) preparing the time point data (T 1 , T 2 , T 3 ) of the two-arm modulation method from said voltage vector times (Tλ-, Tµ, To); and e) switching between the three-arm modulation time point data (T 1 , T 2 , T 3 ) and two-arm modulation point data (T 1 , T 2 , T 3 ) in response to a three-arm/two-arm modulation switching signal so as to use a modulation switch (47) to output to the time changeover switch (33), characterized in that said 0 vector time and a dead time compensation set value are compared, said three-arm/two-arm modulation switching signal is output when 0 vector time becomes shorter, whereby the switchings between three-arm modulation method and two-arm modulation method are carried out according to a magnitude of the voltage instruction. f) said 0 vector time and a dead time compensation set value (K•Tdly) are compared, said three-arm/two-arm modulation switching signal is output when 0 vector time becomes shorter.

Inventors: YAMAMOTO YASUHIRO, YAMAMOTO, YASUHIRO, YAMAMOTO, YASUHIRO, KABUSHIKI KAISHA MEIDENSHA
Applicants: MEIDENSHA ELECTRIC MFG CO LTD, KABUSHIKI KAISHA MEIDENSHA
Application year: 1993
Main classification: H02P5
IPC codes: H02M7, H02P27