AN APPARATUS FOR TRANSFERRING INFORMATION FROM A FIRST TO A SECOND ELECTRONIC UNIT

Abstract: An arrangement for transmission of information from a first electronic unit (1), transmitter, to a second electronic unit (2), receiver, on a balanced two-wire link (3, 4). In the arrangement the voltage difference between the two wires (3, 4) can assume three different values and each change between these values leads to a transmission of a binary symbol whose value is distinctly determined by the change. The information signal, which is transmitted via the two-wire link, is self-clocked which means that it contains both the data signal and the clock signal. Preferably, the transmitter (1) comprises one encoder for encoding the clock signal and data signal and the receiver (2) comprises two comparators, one clock extracting circuit and one decoder. Preferably, the arrangement can be used in communication e.g. between chips or in local networks.

Description: AN APPARATUS FOR TRANSFERRING INFORMATION FROM A FIRST TO A SECOND ELECTRONIC UNIT. TECHNICAL AREA The invention refers to an arrangement for transmission of information from a first electronic unit to a second electronic unit on a balanced two-wire link, mainly be¬ tween chips, multi-chip-modules or other modules that together constitute an electronic system. BACKGROUND Data rates and clock frequencies are continuously in¬ creasing in modern systems. An important consequence of this is that the signal delay between chips becomes co - parable to or larger than the clock cycle. This calls for arrangements that utilize asynchronous communication which in principle can be carried out in two different ways. One way is to use so-called handshaking which leads to a quite low data rate since the handshaking signals have to be awaited between each bit of information. The other way is to use a so-called selfclocked signal which contains both data and clock. The best known self¬ clocked protocol is the Manchester code which is used in, for example, magnetic recording, see for instance B. Sklar, "Digital communication", Prentice Hall, Englewood Cliffs, NJ 1988. The Manchester code can only use a data rate which is about half the bandwidth of the communication link where the communication link includes transmitter, interconnection line and receiver. The rea¬ son for this is that up to two edges per bit of informa¬ tion are needed in order to ensure the recovery of the clock for any data sequence. More sophisticated codes can be more efficient but need more complex encoding/decoding circuitry. Also, the Manchester code as well as other pulse code modulated (PCM) codes needs some kind of time reference or phase locked oscillator at the receiver end. Another important consequence of the increased data rate is the large power consumption in the transmitters. A common way to circumvent this problem is to reduce the output voltage swing which leads to a reduced noise mar¬ gin. This normally calls for a balanced two-wire connec¬ tion, see C. Svensson and J. Yuan, "High-speed CMOS chip- to-chip communications circuit", Proceedings of 1991 In- ternational Symposium on Circuits and Systems, pp. 2228— 2231. THE PURPOSE OF THE INVENTION The purpose of the invention is to achieve an arrangement for transmission of information from a first to a second electronic unit on a balanced two-wire link which in¬ creases the transmission rate and decreases the noise margin and, also, solves the problem of synchronization without any demands on insertion of extra edges in the signal, insertion of a memory of more than one time slot at the receiver or insertion of any knowledge at the receiver about the transmission rate at the transmitter. SUMMARY The basis of the invention is the understanding that the above mentioned objectives can be attained by efficiently utilize the two-wire link at which this is not only used for data transmission but also for solving the problem of synchronization. This is ordinarily solved by using a 3-level asynchronous protocol. The particular characteristics of the kind of arrangement mentioned in the first paragraph are, according to the invention, that the voltage difference between the two wires can assume three different values and that each transition between the values mentioned leads to the transmission of a binary symbol whose value distincively is determined by the transition mentioned. When using such an arrangement one can, according to the invention, attain a fast and reliable data transmission which, when exploiting selfclocking, can utilize the full bandwidth of the two-wire link. Other characteristics of the invention will be evident from the subsequent patent claims. BRIEF DESCRIPTION OF THE FIGURES The invention will be further described as an example, with reference to the enclosed figures, in which: Fig. 1 gives an overview of the arrangement according to the invention, Fig. 2 gives an overview of a first electronic unit according to the invention, Fig. 3 shows a state diagram for the different states possible in the arrangement, Fig. 4 shows different voltage signals representing states in the arrangement according to the invention, Fig. 5 shows the encoder in Fig. 2 in further detail, Fig. 6 shows a driving stage of the unit in Fig. 2, Fig. 7 shows a second electronic unit according to the invention, Fig. 8 shows the signals of the second electronic unit in Fig. 7, Fig. 9 shows a state diagram used when encoding the transmitted signal, Fig. 10 shows an implementation of a clock extracting circuit, which is part of Fig. 7, in further detail, Fig. 11 shows an additional state diagram used in signal extraction, Fig. 12 shows an implementation of the decoder in Fig. 7 in further detail. IMPLEMENTATION EXAMPLES Fig. 1 shows the entire arrangement, according to the invention, comprising a first electronic unit 1, a trans¬ mitter, a second electronic unit 2, a receiver and an intermediate two-wire link 3, 4. The transmitter is sup¬ plied with a clock signal on wire 5 and a data signal on wire 6 and from the receiver an extracted clock signal on wire 7 and a decoded data signal on wire 8 are obtained. In Fig. 2 the transmitter 1, which comprises an encoder 10 and two driving stages 11, 12, is shown. The encoder transforms the clock signal and the data signal into a code that controls the driving stages. These output sig¬ nals to the driving stages can, in this example, repre¬ sent the values (0,1), (1,0) and (0,0) which correspond to the states S,, S 2 and S 3 , respectively see Fig. 3. The output signals from the driving stages to the two-wire link are denoted Oj and 0 2 . Each time a data bit is to be sent, e.g. at a positive clock edge, a change of state occurs. If a logical one is to be transmitted the state is moved one step clockwise in the state diagram in Fig. 3, i.e. from S.- to S-.,, where¬ as a logical zero is transmitted by changing the state one step counter-clockwise, i.e. from S ; to S i+1 . Here i can assume the integers 1, 2 and 3 and is cyclic. In Fig. 4 an example of the signals 0 1 and 0 2 on the two- wire link, obtained from the driving stages 11, 12, and, also, the differential signal 0,-0 2 are shown. Here O, and 0 2 can assume the voltage levels of V 0 and V 0 +V, and, thus, the resulting differential signal can assume the values of +Vι, 0 and -V,. The data stream exemplified in Fig. 4, 111000, is repre¬ sented by transitions between the states shown in Fig. 3. For example, the first data bit, a logical one, is repre¬ sented by a transition from S 3 to S 2 , whereas the second and third data bits, also logical ones, are represented by transitions from S 2 to S, and S, to S 3 , respectively. Common to all these transitions is that they are execu¬ ted in a clockwise manner in the state diagram, i.e. they represent logical ones. The succeeding three transitions are executed in an counter-clockwise manner as shown and, hence, represent logical zeros. Fig. 2 shows a simple and efficient way of implementing the encoder 10 at which a bi-directional register ring 13 is used. The register ring 13 comprises three registers 14, 15, 16 of which each includes one information element and an input i and an output o. Each register output is connected to the inputs of the other two registers via connections which include switches. For instance, the output of register 14 is connected via connections 17, 18. These connections are arranged such that when the data signal represents a first value the output is con¬ nected to the first of the other two registers, in this case to register 15 via the full line connection 17, whereas if the data signal represents a second value the output is connected to the second of the other two regis- ters, in this case to register 16 via the broken line connection 18. The outputs of the remaining registers are connected in a similar way. In this fashion the content of the registers at every occasion of transmission is moved clockwise or counter¬ clockwise depending on the current data signal. The con¬ tent of the registers 14, 15 is applied to the driving stages 11, 12, respectively, in order to create the states for (O,, 0 2 ) , i.e. (0,1), (1,0) and (0,0). The edges of the output signals are synchronized by the re¬ gister clock and delay-balanced drivers in the driving stages 11, 12 ensure a very small skew at the outputs of the driving stages. In Fig. 5 the encoder is shown in further detail. Here, the encoder is designed in so-called precharged logic which is described in e.g. Weste and Eshragian, "Prin¬ ciples of CMOS VLSI design", Addison-Wesley, 1985. In the figures the transistors with an inverting ring at the gate denote p-transistors and the ones without such a ring denote n-transistors. Every register is constituted by a p-block, in which p-transistors are in majority, and an n-block, in which n-transistors are in majority. The registers are connected to one another, as illustrated at the bottom of the figure, and have in this implementation both the function of logic and latch. All p- and n-blocks are connected to preceding and suc- ceeding n- and p-blocks, respectively, and are controlled by forward clock signals, § PF and i^,, and backward clock signals, Φ PB and Φ m . In the upper middle part of the figure a register, comprising a p-block 27 and an n-block 28, is shown. The clock signals supplied to the blocks are generated in a local clock generating circuit 24 from the global clock signal Φ and the input data, D P and D N . D P and D N are each other's inverses, i.e. when the data signal is high, D P is high and D N is low, and vice versa. From the circuit diagram it is evident that the forward clock is active when D P is high and the backward clock is active when D N is high. The clock signals are fed to the registers in order to transfer the register information forward or backward in the ring. The output signals 0, and 0 2 are obtained from the signals Opj and 0 N1 and, also, 0 P1 and 0 N2 from n-block 1, 2 and, also, p-block 3, 1, respectively. These signals are fed to two evaluation circuits 25, 26, one intended for O, and another for 0 2 , with a doubled data rate, i.e. half a clock cycle per data. From these evaluation circuits the resulting signals are fed to the driving stages. With the support of external logic, in the figure this is represented by two p- and two n-transistors, 20, 21 and, also, 22, 23, respectively, the circuit can automatically initiate and keep a circulating pattern going, in this case the pattern is 0-0-1. An implementation of the driving stages is shown in Fig. 6, an implementation that corresponds to the two driving stages 11, 12 in Fig. 2. At the input there are balanced pre-drivers 29. These are used since the output signals O, and 0 2 have to change simultaneously. The output is made up of a conventional transistor-resistor circuit that is producing both output signals. The driving stages can be implemeneted as any kind of binary driving stages that can assume two different vol- tage levels, V 0 and V 0 +V,. At high data rates it is pre¬ ferred to match their output impedance to the charac- teristic impedance of the two-wire link connection. The binary driving stages usually have a state that con¬ sumes less power than the other does and by using this state in both driving stages when the same voltage should be present on both connections the power consumption of the driving stages is reduced with about 1/3 due to the code with three levels. The connection of the two-wire link consists of the two connections 3, 4, e.g. in the form of two printed wires in a multi-chip module or on a circuit board, in the form of two striplines on a circuit board or in the form of two coaxial cables. The two wires must be designed such that both wires essentially have the same length and the same properties in other respects. The signals that are transmitted should be truly balanced, i.e. the three states can only be distinguished by observing the voltage difference between the two wires, a difference that should be independent of noise voltages between the two- wire link and ground. By the change of states on the two-wire link the receiver can both detect that a data bit is sent and which value this data bit represents. Fig. 7 shows the receiver including two comparators 30, 31, a clock extraction circuit 32 and, also, a decoder 33. The last two circuits are suitably designed as asyn¬ chronous finite state machines, AFSM. The comparators 30, 31 detect the difference between the voltages on the two wires 3, 4 in the two-wire link and produce as output voltage the signals C, and C 2 , respectively. The compa¬ rators are designed such that the first has an offset voltage corresponding to a voltage difference that is larger than 0 V, for noise immunity reason preferably +V,/2, and the second has an offset voltage corresponding to a voltage difference that is less than 0 V, preferably -V,/2. In the presented implementation two comparators are cross connected to the two-wire link so that they detect both voltage differences, +V,/2 and -V,/2. An example of waveforms generated by this implementation is shown in Fig. 8 which corresponds to the example of Fig. 4 where waveforms generated by the transmitter 1 are shown. Here it can be seen that the output signal of the first compa¬ rator, C,, goes high only when the voltage difference 0,-0 2 is high, i.e. above +V,/2, while the output signal of the second comparator, C 2 , goes high only when the voltage difference 0,-0 2 is low, i.e. below -V,/2. From the resul¬ ting data signal D it can be concluded that the trans¬ mitted binary information 111000 has been recovered. Note that the extracted information is available with two bits of information per clock cycle. Fig. 9 shows a table for extracting the clock from a logical AND-operation on the signals C, and C 2 at which a control signal is generated and, at some transistions, inverted. From the table it is clear that C, can be used as a trigger signal for the control signal when the state transitions are executed forwardly, i.e. to the right in the table. In the same way C 2 can be used when the state transitions are executed backwardly, i.e. to the left in the table. When the transitions are executed back and forth in the zone between two borders positive edges will be produced on C, and C 2 and these positive edges have to be suppressed in order to have correct function. The clock extracting circuit 32 in Fig. 7, whose inputs are connected to the outputs of the comparators, can be syntesized by using a systematic method, e.g. the one described in "Digital design fundamentals" by K. J. Breeding, Prentice Hall, Englewood Cliffs, NJ, 1989. In Fig. 10 such a synthesis of the clock extracting circuit is shown in further detail, a circuit that is fulfilling the requirements of detecting the borders at which the control signal is inverted. Two positive edge triggered flip-flops 40 and 41 are used to separately take care of the clockwise and counter-clockwise state transitions. The flip-flops are triggered by the signals T, and T 2 that are generated from C, and C 2 from the comparators, each by one of the trigger generators 42, 43. In the first gene¬ rator the output signal T, is based on C, but the back¬ ward-going positive edges are suppressed by a signal Y, which is produced from a logical combination of C, and C 2 according to the table in Fig. 11. In the second genera¬ tor the output signal T 2 is based on C 2 but the forward- going positive edges are suppressed by a signal Y 2 which is produced in a similar way to Y,. The outputs of the two flip-flops are connected to each other so that when one output changes signal a change is forced onto the output of the other flip-flop as well. This is possible since only the triggered flip-flop can drive the output. The output signal is fed to an exclusive OR-gate, XORgate 44, to control the sign of Cj+C 2 . Thus, the clock is ex¬ tracted at the output of the XOR-gate 44. A completely dynamic flip-flop can not be used in this position since states can change back and forth in the zone between two borders during a long time and the trigger signals T, and T 2 will be stable. For this reason the shown flip-flops are half-dynamic, see J. Yuan, "Efficient CMOS counter circuits", Electronic Letters, vol. 24, pp. 1311-1313, October 1988. When both trigger signals, T, and T 2 , are low the flip- flops become static since the five minimum-sized transis¬ tors at each output plus the bottom transistor in the output latch and the first stage in each flip-flop form a loop 45, 46 to lock the output. Both loops will be broken whenever one of the trigger signals goes high and the output will be refreshed. After the clock is recovered the signal can be decoded. According to Fig. 7 this takes place in the decoder 33 which is shown in Fig. 12 in further detail. This decoder is connected to the outputs of the comparators 30, 31 as well as to an output of the clock extracting circuit 32. The data information has to be extracted according to the changes of codes which means that both the present and the previous information is needed. This extraction can e.g. be carried out using a hysteresis principle, which is also employed in the clock extracting circuit, with a state diagram according to Fig. 11. For the 3-levels code used six different patterns are needed to describe both forward changes, in this case zeros, and backward changes in this case ones. Thus, there is a need for a third hysteresis signal Y 3 which is generated in a generator 50 similar to the trigger generators 42, 43 in Fig. 9. In the table in Fig. 11 the memorized hysteresis states are indicated by bold figures. Since these states are always refreshed in Y,, Y 2 and Y 3 by successive codes dynamic memory can be used. Three forward and three back- ward combinations of Y,, Y 2 and Y 3 are completely different and can be used to determine three zeros and three ones. The extraction logic for the data signal is identical to the sum computation in an adder. Three XOR-gates 51, 52, 53 are used for this purpose. Hence, the total delay for the clock recovery and for the data extraction are approximately equal. In an alternative implementation of the receiver the decoder is implemented as two parallel units where each is operating at half of the full data rate. The two de¬ coder parts are implemented as synchronous finite state machines and can be implemented in conventional logic, e.g. the kind of logic described in Yuan and Svensson, Journal of Solid State Circuits, vol. 24, pp. 62-70, 1989. An arrangement according to the above mentioned can prove useful in many circumstances, e.g. when transmitting data serially in local networks or when transmitting data in twisted wire pairs over fairly long distances when e.g. optical transmission is more expensive. Nor must the .invention be considered to be limited by the above description. For instance, a bi-directional commu¬ nication could be arranged or a system could comprise more than one receiver at which the information is trans¬ mitted on a bus-like connection. Of course, also the relationship between direction of change and binary value in Fig. 3 can be re-arranged and the state of 0,0 can be replaced by 1,1 if desired. As an alternative to representing the binary symbols with changes in one or another direction, see Fig. 3, a tran¬ sition between a first state S, and a second state S 2 can imply a transmission of a first binary symbol, a transi- tion between the first state S, and a third state S 3 can imply a transmission of a second binary symbol and a transition between the second state S 2 and the third state S 3 can imply a transmission of the first or the second binary symbol depending on in which direction the transi- tion is executed. The shown implementations present a realization of the invention in n-MOS and p-MOS technique. Also other tech¬ niques can be used such as CMOS techniques and emitter- coupled logic, ECL, field-effect transistor logic in e.g. GaAs or other techniques that are useful to the realiza¬ tion of logic.

Claims: CLAIMS l. An arrangement for transmission of information from a first electronic unit to a second electronic unit on a balanced two-wire link over which the voltage difference can assume three different values, each of which repre¬ sents one of three different states (S,, S 2 , S 3 ) c h a r - a c t e r i z e d in that only changes between the states mentioned lead to transmission of binary symbols, in that each change represents one single symbol and in that the value of the symbol distinctly is determined by from which state and to which state the transition is execu¬ ted. 2. An arrangement according to claim 1 c h a r a c ¬ t e r i z e d in that the voltage of each wire (0,, 0 2 ) can assume two different voltage levels, V0 and V 0 +V,, respectively. 3. An arrangement according to claim 1 or 2 c h a r a c t e r i z e d in that the second electronic unit comprises two comparators, connected to the two-wire link and used for detecting the states, at which the first comparator has an offset voltage corresponding to a voltage difference larger than 0 V, preferably V,/2, and the second comparator has an offset voltage corresponding to a voltage difference less than 0 V, preferably -V,/2. 4. An arrangement according to any one of claims 1-3 c h a r a c t e r i z e d in that a transition from S.- to S iA leads to a transmission of a binary symbol with a first value and a transition from S; to S i+1 leads to a transmission of a binary symbol with a second value at which i can assume the integers 1, 2 and 3 and is cyclic. 5. An arrangement according to any one of claims 1-3 c h a r a c t e r i z e d in that a transition between a first state S- and a second state S 2 leads to a transmis¬ sion of a binary symbol with a first value, a transition between the first state S, and a third state S 3 leads to a transmission of a binary symbol with a second value and a transition between the second state S 2 and the third state S 3 leads to a transmission of a binary symbol with the first or the second value depending on in which direction the transition is executed. 6. An arrangement according to any one of claims 1-5 c h a r a c t e r i z e d in that the first electronic unit comprises an encoder, to which a clock signal and a data signal are fed, and two driving stages which are connected to the encoder and whose respective output is connected to one of the wires in the two-wire link. 7. An arrangement according to claim 6 c h a r a c - t e r i z e d in that the encoder comprises a bi-direc¬ tional register ring. 8. An arrangement according to any one of claims 1-7 c h a r a c t e r i z e d in that the second electronic unit comprises a clock extracting circuit which extracts a clock signal from the changes in the voltage diffe¬ rence. 9. An arrangement according to any one of claims 1-8 c h a r a c t e r i z e d in that the second electronic unit comprises a decoder for the decoding of the informa¬ tion transmitted over the two-wire link, which decoder is dependent on both current and previous state.

Inventors: SVENSSON CHRISTER, YUAN JIREN, SVENSSON, CHRISTER, YUAN, JIREN
Applicants: SVENSSON CHRISTER, UNI I LINKOEPING, YUAN JIREN, UNIVERSITET I LINKOEPING
Application year: 1993
Main classification: H04L7
IPC codes: H04L7, H04L25