Transistor circuit for holding peak/bottom level of signal

Abstract: A transistor circuit for detecting and holding a peak or bottom level of an input voltage (Vin) comprises a first transistor (Q1) connected between a first power line and an output terminal, a capacitor (C) connected between the output terminal and a second power line, a second transistor (Q2) supplied with the input voltage (Vin) and producing a current responsive to the input voltage (Vin), and a current mirror circuit (1) supplied with the current from the second transistor (Q2) as an input current and discharging the capacitor (C) with an output current. The output current of the current mirror circuit (1) is preferably designed to be smaller than a charging current to the capacitor (C) from the first transistor (Q1).

Description: BACKGROUND OF THE INVENTION The present invention relates to a transistor circuit and, more particularly, to a peak/bottom level hold circuit constituted of insulated gate field effect transistors (called hereinafter "MOS transistors" A level hold circuit is widely employed in an electronic system to detect and hold the level or amplitude of a signal voltage. Such circuit is composed of a MOS transistor and a capacitor in general. Referring to Fig. 1, a peak hold circuit according to a prior art includes an N-channel MOS transistor Q1 and a capacitor C connected in series between a first power line Vcc and a second, ground power line GND. A resistor R is connected in parallel to the capacitor C. The transistor Q1 has a threshold voltage of substantially zero (0 v). An input signal voltage Vin is supplied to the gate of the transistor Q1, and a voltage across the capacitor C is derived as an output voltage Vout. In such a construction, when the input voltage Vin is larger than the output voltage Vout, the transistor Q1 is turned ON to charge the capacitor C. The output voltage Vout ist thereby made large. When the input voltage Vin becomes smaller than the output voltage Vout, the transistor Q1 is turned OFF. The capacitor C is thereby discharged through the resistor R to lower the output voltage Vout. Thus, the output voltage Vout varies as shown by a dated line in Fig. 2 in response to change in level of the input voltage Vin indicated by a solid line. That is, this circuit functions as a peak level hold circuit. However, the cycle period of the input voltage Vin is not always constant, but sometimes changes as shown in Fig. 3. In that case, a certain peak level as indicated by a reference numeral 10 or 11 in Fig. 3 is not detected by the circuit shown in Fig. 1. Moreover, when the cycle period of the input voltage Vin is prolonged, the peak level represented by the output voltage Vout is not held, but discharged to the ground level. JP-A 60 124 119 discloses a peak value detecting circuit comprising a first transistor supplied with an input voltage via a second transistor connected between a first and first power supply line and an output terminal; a capacitor connected between said output terminal and a second power supply line, said first transistor charging, when rendered conductive, said capacitor with a first current; said second transistor being supplied with said input voltage and producing a second current responsive to said input voltage; and a current circuit coupled to receive said second current and discharging said capacitor with a third current being determined by the current of a current source included in said current circuit. The current circuit according to this document comprises a comparator which is constituted by two transistors and which requires said current source and a reference voltage for operation. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved transistor circuit for holding peak/bottom level of an input voltage. It is another object of the present invention to provide a transistor circuit for detecting and holding the peak or bottom level of a pulse-wise input voltage having an inconstant cycle period. A transistor circuit according to the present invention is defined in claim 1. Further embodiments are defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 ia a circuit diagram illustrative of the prior art; Fig. 2 is a timing chart for explaining an operation of the circuit shown in Fig. 1; Fig. 3 is another timing chart for explaining another operation of the circuit shown in Fig 1; Fig. 4 is a circuit diagram illustrative of an embodiment of the present invention; Fig. 5 is a timing chart for explaining an operation of the circuit shown in Fig. 4; Fig. 6 is a circuit diagram illustrative of another embodiment of the present invention; and Fig. 7 is a timing chart for explaining an operation of the circuit shown in Fig. 6. DETAILED DESCRIPTION OF THE EMBODIMENTS Referring now to Fig. 1, a transistor circuit according to an embodiment of the present invention operates as peak level hold circuit and includes an N-channel MOS transistor Q1 supplied at its gate with an input voltage Vin. This transistor Q1 is connected in series to a capacitor C between a power supply line Vcc and a ground supply line GND. A voltage across the capacitor C is derived as an output voltage Vout. An N-channel MOS transistor Q2 and a current mirror circuit 1 are further provided in accordance with the present invention. The transistor Q2 receives at its gate the input voltage Vin and connected between the power supply line Vcc and an current input node of the current mirror circuit 1 which has a current output node connected to the connection point of the transistor Q1 and the capacitor C, i.e. an output terminal. The current mirror circuit 1 is composed of an N-channel MOS transistor Q3 and an N-channel MOS transistor Q4. The gate of the transistor Q3 is connected to its drain (i.e., the current input node) and further to the gate of the transistor Q4 having its drain serving as the current output node. In this embodiment, each of the threshold voltage of the transistors Q1-Q4 are designed to be substantially zero (0 v). The current mirror circuit 1 has a current gain designed to be 1. Accordingly, the output current derived from the circuit 1 is equal to a current flowing through the transistor Q1. If desired, another current gain can be designed for the current mirror circuit 1. However, the output current from the mirror circuit 1 is designed to be sufficiently smaller than a current flowing through the transistor Q1. For this purpose, the transistor Q1 is made with a large area to have a high conductance, as compared to the conductance of each of the transistors Q2-Q4. In the circuit thus constructed, when the input voltage Vin is higher than the output voltage Vout, the transistor Q1 is rendered conductive to charge the capacitor with a relatively large current. As to the transistor Q2, it is in a conductive state so long as the input voltage Vin is higher than the threshold voltage thereof. Accordingly, the current mirror circuit 1 produces the current to discharge the capacitor C. However, the current from the mirror circuit 1 is very smaller than the current from the transistor Q1, and therefore, the capacitor is charged up to the peak level of the input voltage Vin to allow the output voltage Vout to represent the peak level of the input voltage Vin, as shown in Fig. 5. When the input voltage returns to the ground level from the peak level, the transistor Q1 is turned OFF. The transistor Q2 is also turned OFF. Thus, the detected peak level is held by the capacitor C as the output voltage Vout (see Fig. 5). When the input voltage raises again, the transistor Q2 is rendered conductive. The current mirror circuit 1 thereby discharge the capacitor C to lower the output voltage Vout. At a time when the output voltage Vout thus lowered becomes equal to the input voltage Vin, the transistor Q1 is turned ON to charge the capacitor C. Thus, as shown in Fig. 5, even when the time interval between the adjacent two peaks is relatively short, each peak level is surely detected and held. Moreover, even in the case where the next peak does not appear for a relatively long time, the detected peak level continues to be held. The input voltage often includes noise voltages. In that case, it is preferable that the threshold voltage of the transistor Q2 is made large. Accordingly, the transistor does not respond to the noise voltages. The generation of an undesired discharge current from the current mirror circuit 1 is thereby prevented. The threshold voltages of the transistors Q3 and Q4 may be higher than the ground level. Turning to Fig. 6, a transistor circuit according to another embodiment of the present invention includes four P-channel MOS transistors Q11-Q14 and a capacitor CC which are connected as shown. The transistors Q13 and Q14 constitute a current mirror circuit 5. This circuit thus functions as a bottom level detecting and holding circuit for an input voltage Vin, as shown in Fig.7. Since the circuit operation of this circuit is the substantially same as that of the circuit of Fig.4, the further description thereof will be omitted. It is apparent that the present invention is not limited to the above embodiments but may be modified and changed without departing from the scope of the invention as defined in the appended claims.

Claims: A transistor circuit comprising a first transistor (Q1) supplied with an input voltage (Vin) and connected between a first power supply line (Vcc) and an output terminal (Vout), a capacitor (C) connected between said output terminal and a second power supply line (GND), said first transistor charging, when rendered conductive, said capacitor with a first current, a second transistor (Q2) supplied with said input voltage and producing a second current responsive to said input voltage, and a current mirror circuit (1) having an input node connected to said second transistor and an output node connected to said output terminal to receive said second current and discharging said capacitor with a third current relative to said second current, said third current being smaller than said first current. A transistor circuit according to claim 1, wherein said first and second transistors have the same threshold voltage as each other. A transistor circuit according to claim 1, wherein the threshold value of said first transistor (Q1) is smaller than the threshold value of said second transistor (Q2). A transistor circuit according to any of the preceding claims, wherein said current mirror circuit (1) comprises a third transistor (Q3) and a fourth transistor (Q4), the gate of said third transistor being connected to its drain serving as the current input node and, further, to the gate of said fourth transistor having its drain serving as the current output node. A transistor circuit according to any of the preceding claims, wherein said transistors (Q1, Q2, Q3, Q4) comprise N-channel MOS transistors. A transistor circuit according to claim 4 or 5, wherein each of the threshold voltages of said transistors (Q1-Q4) are designed to be substantially zero and the current gain of said current mirror circuit (1) is designed to be 1. A transistor circuit according to any of the preceding claims, wherein said first transistor (Q1) is made with a large area to have a high conductance as compared to the conductance of each of said remaining transistors (Q2-Q4).

Inventors: NARAHARA TETSUYA, NARAHARA, TETSUYA, NARAHARA, TETSUYA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H03K5
IPC codes: G11C27, G01R19