A METHOD AND A DEVICE FOR GENERATING A CLOCK SIGNAL IN A MULTIPLEXING SYSTEM

Abstract: The invention relates to a method and a device for generating a clock signal in a multiplexing system, to which are applied several incoming signals, whereby the clock frequency of each signal may be a specific basic frequency or a multiple thereof. According to the method the clock frequency of one incoming signal is selected to be a source of a new clock frequency to be generated, and a second clock signal depending on the selected incoming signal is applied to a phase-locked loop (23) acting as a frequency multiplier, whereby the desired clock signal is generated by multiplying said second clock signal by means of the phase-locked loop by a desired multiplier. To make it possible to synchronize the output signal with signals in a wide frequency range in such a way that the accuracy of the frequency of the output signal is independent on the clock frequency of the signal with which the output signal each time is synchronized, said second clock signal is generated, in response to the selection made, by dividing (22) the clock signal corresponding to the selected incoming signal by a factor equal to the ratio of the clock frequency of the selected incoming signal to said basic frequency.

Description: A method and a device for generating a clock signal in a multiplexing system The invention relates to a method according to the prior art portion of the attached claim 1 and a device according to the prior art portion of the at¬ tached claim 3 for generating a clock signal in a multiplexing system. At present a clock signal of a multiplexing system is generated typically in such a way that the frequency of an incoming clock signal of a multiplex¬ ing unit is multiplied by means of a phase-locked loop by a number providing a clock frequency desired. For instance, when multiplexing 64 kbit/s channels into a basic 2,048 bit/s multiplexing system, the frequency (64 kHz) of an incoming clock signal of the multiplexing unit is multiplied by 32 in order to be able to generate a clock signal at a desired frequen¬ cy for the multiplexing system, which signal is phase-locked to the incoming clock signal. Because, however, the transmission devices sending the signals to be multiplexed are capable of transmitting data at very many different frequencies, it would be desirable to provide a method by means of which it is possible to generate a new clock signal phase-locked to the incoming clock signal, irrespec¬ tive of the frequency of the incoming clock signal. It is also generally known to use phase-locked loops as frequency synthetizers. A new output fre- quency is provided by loading a programmable divider in a feedback loop of the phase-locked loop with a new division factor. Due to the new division factor, the loop becomes unlocked and tries to lock to a new frequency, which is determined on the basis of the new division factor. It would be conceivable to use such a solution known per se for achieving the above object as well. However, a drawback of the solution is that the accuracy of the new clock signal generat¬ ed in this way is dependent on the selected incoming clock signal. The object of the present invention is thus to achieve the aim described above in such a manner that the accuracy of the new clock signal remains unchang¬ ed irrespective of the selected incoming signal. This is achieved by means of the method of the invention, which is characterized in what is set forth in the characterizing portion of the attached claim 1. The device according to the invention is, in turn, char¬ acterized in what is set forth in the characterizing portion of claim 3. The idea of the invention is to use a program¬ mable divider at the input of a phase-locked loop (in addition to the fact that a fixed division factor is used at the feedback of the loop) in such a manner that the frequency of a signal to be applied to the phase-locked loop is always the same, irrespective of the clock frequency of the signal to which the phase is locked. Thanks to the solution according to the inven- tion, it is possible to generate from signals within an even very wide frequency range a signal phase- locked to these signals, the accuracy of the frequen¬ cy of which signal is, as described above, indepen¬ dent on which signal is selected each time. Due to the solution of the invention, it is also possible to reduce the jitter of the generated phase-locked sig¬ nal. In the following the invention will be ex¬ plained in more detail with reference to examples according to the attached drawing, in which Figure 1 shows the operating environment of a method and a device according to the invention and Figure 2 shows a device according to the inven¬ tion to be applied to a multiplexing unit shown in Figure 1, in which device a clock signal is generated for a multiplexing system. Figure 1 shows the operating environment of a method and a device according to the invention. By means of multiplexing units 10 known per se, a basic 2,048 Mbit/s multiplexing system is provided, which system transmits signals sent by or to one or several transmission devices 11, as e.g. a modem. A transmis¬ sion device 11 can transmit or receive data at speeds typically in the range (1...31) x 64 kbit/s. The mul- tiplexing unit 10 comprises an interface unit 12 re¬ ceiving/sending the signals of the transmission de¬ vices and a multiplexer 13 connecting a multiplexed signal to a transmission path. The interface unit receives from the transmission device the actual data for each channel and a clock signal CLK of the chan¬ nel in question, the frequency of which signal may be in the range (1...31) x 64 kHz, as per above. From one such clock signal is generated according to the invention an external clock signal for the multiplex- ing unit 10, with which signal a 2,048 Mbit/s trans¬ mission connection and the entire network can be syn¬ chronized. Said new clock signal is generated in a synchronization unit of the interface unit 12, to the input of which synchronization unit are brought the clock signals of the different channels. Figure 2 shows the structure of said synchro¬ nization unit in more detail. Clock signals CLK 1... CLK N of channels entering the multiplexing unit, the frequencies of which signals may be in the range n x 64 kHz, are brought to a selector 21, which selects, under the control of a processor (not shown) control¬ ling the device, the very clock signal selected by the user to be the signal from which a new clock sig¬ nal for the multiplexing system is generated. The selector 21 is a multiplexer known per se. The selec¬ ted clock signal is applied to a programmable divider 22 dividing the frequency of the clock signal by a division factor equal to the ratio of the frequency of said clock signal to the frequency 64 kHz. Over a bus 28 the processor provides a correct division fac¬ tor depending on which clock signal has been selected each time. Accordingly, the frequency of the output signal of the divider 22 is always 64 kHz, irrespective of which one of the clock signals CLK 1...CLK N has been selected each time. This signal is applied to a phase-locked loop 23, comprising in a manner known per se a phase comparator 24, the input 24a of which forms the input of the loop, a loop filter 25 of low- pass type, a voltage-controlled oscillator 26 and a divider 27 in a feedback line, which divider divides the output signal of the loop in this case by a fixed number 32. The output of the divider 27 is connected to a reference input 24b of the phase comparator. As known, the phase-locked loop acts as a frequency mul¬ tiplier in such a way that the frequency of its out¬ put signal is equal to the frequency of the input signal of the loop multiplied by the division factor of the divider 27. Accordingly, the frequency f out of the output signal is in this case 32 x 64 kHz = 2,048 MHz. The phase comparator 24 compares the phase of a 64 kHz signal to be applied to the comparator input with the phase of a reference signal generated from an outgoing 2,048 MHz signal by the divider 27. A pulse is generated at the output of the phase compa- rator, the length of which pulse is proportional to a phase error. This pulse is low pass filtered by the loop filter 25, which is a so-called lag lead filter known per se. The low pass filtered signal to be re- ceived from the output of the loop filter controls the frequency of the voltage-controlled oscillator 27 to be such that there is no phase difference between the signals applied to the inputs of the phase com¬ parator. In this way, the outgoing 2,048 MHz signal is phase-locked to the clock signal selected by the selector 21 each time. Since the frequency of the signal to be applied to the phase-locked loop is always the same, the phase-locked loop and especially the loop filter al- ways operate in the same way. Due to this, the accu¬ racy of the frequency of the output signal does not depend on the clock signal selected. The programmable divider 22 serves as an additional jitter filter as well, which partly reduces the jitter of the output signal. Though the invention has above been described referring to the examples according to the attached drawings, it is clear that the invention is not re¬ stricted to that, but it may be modified in many ways within the scope of the inventive idea described above and in the attached claims. For instance, transmission devices of different types are possible and the desired output frequency may differ from the clock frequency of the basic multiplexing system pre- sented above.

Claims: Claims : 1. A method of generating a clock signal in a multiplexing system, to which are applied several incoming signals, whereby the clock frequency of each signal may be a specific basic frequency or a multi¬ ple thereof, according to which method - the clock frequency of one incoming signal is selected to be a source of a new clock frequency to be generated, and - a second clock signal depending on the se¬ lected incoming signal is applied to a phase-locked loop (23) acting as a frequency multiplier, whereby the desired clock signal is generated by multiplying said second clock signal by means of the phase-locked loop by a desired multiplier, c h a r a c t e r i z¬ e d in that said second clock signal is generated, in response to the selection made, by dividing (22) the clock signal corresponding to the selected incom- ing signal by a factor equal to the ratio of the clock frequency of the selected incoming signal to said basic frequency. 2. A method according to claim 1, c h a r ¬ a c t e r i z e d in that an external clock signal for a 2,048 Mbit/s basic multiplexing system is gen¬ erated by means of this method by dividing the fre¬ quency of an external clock signal of one channel, before applying it to the phase-locked loop (23), by a factor which is equal to the ratio of the frequency of the clock signal of said channel to the frequency 64 kHz, said multiplier being 32. 3. A device for generating a clock signal in a multiplexing system, to which are applied several in¬ coming signals, whereby the clock frequency of each signal may be a specific basic frequency or a multi- pie thereof, the device comprising a phase-locked loop (23), a feedback loop of the loop including a divider (27) with a fixed division factor, c h a r¬ a c t e r i z e d in that it comprises: - selecting means (21) for selecting a signal to be applied each time to the phase-locked loop (23) among several clock signals, whereby the frequency of each clock signal may be a specific basic frequency or a multiple thereof, and - a frequency divider (22) responsive to the selecting means (21), the division factor of which divider is, in response to each selected signal, ad¬ justed to be a factor equal to the ratio of the fre¬ quency of the selected clock signal to said basic frequency.

Inventors: PELTOLA SEPPO, RAAPPANA KARI, VAEHAEKANGAS JUHA, PELTOLA, SEPPO, RAAPPANA, KARI, VAEHAEKANGAS, JUHA
Applicants: NOKIA TELECOMMUNICATIONS OY, PELTOLA SEPPO, RAAPPANA KARI, VAEHAEKANGAS JUHA
Application year: 1993
Main classification: H03L7
IPC codes: H03L7