COMPUTER-AIDED DESIGN METHODS AND APPARATUS FOR MULTILEVEL INTERCONNECT TECHNOLOGIES

Abstract: A computer-aided method of designing semiconductor interconnect structures for multilevel device interconnects in VLSI integrated circuits. The method integrates a batch-mode computation procedure (100) that combines a finite difference numerical simulation and a fast interpolation algorithm, an interactive design procedure (200), an interactive SPICE subcircuit generator (22) and simulator (300), and a spreadsheet-style graphical user interface (500). The method includes selecting a semiconductor interconnect construction type, displaying a first spreadsheet (502) of semiconductor construction parameters for the selected type, accessing a stored database (402, 404, 408) to read electrical characteristics of the selected type, displaying a second spreadsheet (520) of electrical performance data of the selected type, providing (222) desired electrical performance goals, and displaying a third spreadsheet (530) of construction data that matches the performance goals.

Description: COMPUTER-AIDED DESIGN METHODS AND APPARATUS FOR MULTILEVEL INTERCONNECT TECHNOLOGIES Field of the Invention This invention generally relates to data processing methods and computer display systems for computer aided design and electrical performance prediction of multilevel device interconnect technologies. The invention specifically relates to parameterized graphical display and computation tools for calculation and display of capacitance and other electrical characteristics of multilevel VLSI interconnects, as well as PCB and MCM interconnects. Background of the Invention VLSI integrated circuits ("VLSI chips") are expensive to design, prototype, and test. It is impractical to construct a new VLSI chip simply to test its electrical characteristics or performance. Therefore, VLSI chip designers use computers and computer-aided engineering software to design new VLSI chips, using a high-resolution graphics workstation to display a schematic and physical layout of the VLSI chip. Software is commercially available for simulating electrical performance of complex VLSI chips. This software includes SPICE (originally developed by the University of California, Berkeley) , and enhanced by Hewlett-Pachard Co. and described in "HSPICE User's Manual," part number 5955-5528, commercially available from Hewlett-Packard Company, Circuit Technology Group, 5301 Stevens Creek Boulevard, Santa Clara, California 95052 USA. For proper operation SPICE requires input in the form of a SPICE subcircuit data file, known in the art as a "SPICE deck," which numerically describes the location and type of every conductor and component of the VLSI chip. Generation of SPICE decks to describe VLSI circuits is extremely tedious and time-consuming. One difficult problem faced by VLSI chip designers iε design of conductor interconnections between two VLSI chip devices such as transistors. Some conductor interconnects are three-dimensional and follow a non-linear path, since VLSI chips often are constructed with several overlapping layers of metal, polysilicon, and dielectric materials. The electrical characteristics (such as resistance, inductance, and capacitance) of these multilevel interconnects are determined by a complex relationship of numerous physical variables, including metal thickness, insulator thickness, dielectric constant, line width, inter-line spacing, and coupled line length between devices. The relationship between capacitance and interline spacing is non-linear. Also, the variables listed above result in a large number of possible values for resistance, inductance and capacitance depending on the physical size, type, and combination of metals, or insulators selected by the designer. Accordingly, VLSI circuit designers desire to have a computer system for generating resistance, inductance, and capacitance models for all possible interconnect layout patterns. Since such models for multilevel interconnects require much computation, VLSI circuit designers desire a computer system which can execute such computation in advance in an off-line batch mode. VLSI chip designers also desire a computer system capable of computing the non-linear relationship of capacitance to interline spacing, given trace width and trace spacing, using polynomial or cubic spline curve fitting and interpolation. VLSI chip designers further desire a computer system which can quickly generate parameterized SPICE subcircuit data files for interconnects after computing capacitance. VLSI chip designers also desire a computer system which can interpolate on-chip capacitance values rapidly given the type of integrated circuit ("IC") fabrication process, trace width, and trace spacing, using linear polynomial or cubic spline curve fitting. VLSI chip designers also desire a computer system which can rapidly generate high-level parameterized SPICE subcircuit and circuit data files based on linear polynomial or cubic spline curve fitting given an IC process, rise time, trace width, trace spacing, and line coupling length. VLSI chip designers also desire a computer system with an automatically updated spreadsheet display for viewing performance data and for displaying such data in response to variable changes entered by the designer, thereby enabling rapid evaluation of design changes and trade-offs. When fast clock frequency is used in VLSI chips, transmission line effects will appear on long on-chip interconnects, creating numerous design problems. As is known in the art, signals with 0.5 nanosecond (ns) rise time will incur transmission line effects when the interconnect length is equal to or longer than 3.0 cm. Current VLSI chip die size cannot be dramatically increased due to defect density concerns. Therefore, uniform on-chip interconnect segments to be represented by parameterized subcircuit calls will not approach 3.0 cm for the near future. However, the rise time requirement for full-custom chips will be well below 0.5 nanosecond very soon. Accordingly, VLSI chip designers desire circuit simulators which can import multi-line R, L, C models for lossy, high- density sub-micron interconnect (SMI) transmission line simulations. However, the differences between distributed R,C line and transmission line effects indicate that a straightforward extension of conventional R,C line modeling is not enough for on-chip transmission line modeling. Therefore, designers would appreciate a circuit data file generator which can automate the determination of maximum length of each section for on-chip interconnects based on rise time. To generate SPICE decks, most designers rely on schematic capture programs during pre-layout design and circuit extractors during physical layout. As is known in the art, a SPICE deck iε a file of circuit definition data which is fed to the SPICE circuit simulator program. Use of a parameterized model library can relieve designers of all the interconnect modeling and most of the SPICE deck generation effort. Accordingly, deεignerε would appreciate an automated SPICE deck generator for VLSI interconnectε which can use parameterized libraries to increase the speed of generating SPICE deckε. Metal materialε εuch aε copper, tungεten, or their alloys have been proposed to replace aluminum alloys in some or all metal levels to εatisfy future speed, reliability, and manufacturing requirements. Since the metal profiles and resistivities of these proposed metals differ from those of aluminum, interconnect R,C models must be resimulated. Accordingly, circuit designerε desire to have a parameterized model library generator to provide accurate and efficient interconnect models for evaluating the impact of material changes on electrical performance. Signal propagation delays caused by interconnects form a large percentage of total signal delays in VLSI chips. However, for multi-level interconnect technology (MLIT) modeling in the IC/packaging industry, few CAD tools are available to increase productivity. Three-dimensional structures εuch aε dual signal stripline, via, lead attachmentε, and trace bends require 3-D numerical simulations for accurate computation of impedance, noise margin and delay. Such si ulationε are time-consuming and tedious. Therefore, MLIT designers would appreciate accurate and immediate performance information. High-speed chip designs also demand that engineers consider every combination of technologies from all packaging categories (i.e., IC procesεeε, metal capacitance models (MCM) , printed circuit boards (PCB) , via, and lead attachment technologies) to determine which will satisfy chip performance specifications, such as delay and noise margin requirements. A data processing system for interconnect modeling is therefore needed to integrate and optimize chip design and packaging selection. MLIT designε alεo require knowledge of material science, electrical engineering, and mechanical engineering. Designers must consider each area of engineering in the search for an optimum design. Therefore, designers would appreciate a data processing system which can assist in evaluating cost-performance trade-offs among all different requirements. Summary of the Invention This invention provideε data processing methods and computer display syεtemε for computer aided design and electrical performance prediction of multilevel device interconnects in VLSI integrated circuits, as well as PCB and MCM technologies. The invention specifically relates to parameterized graphical display and computation tools for calculation and display of capacitance and other electrical characteristics of multilevel VLSI interconnects. Four subsyεte ε are integrated: (a) a batch-mode computation module that combines a 2-D/3-D finite difference numerical simulation and a fast interpolation algorithm; (b) an interactive design package with performance browsing, goal-directed synthesis, and on- line performance evaluation; (c) an interactive SPICE subcircuit generator and simulator; and (d) a spreadsheet- style graphical user interface. First, for completeness and speed, combinations of parameters (e.g. width, εpacing) for possible interconnect configurations are numerically simulated or interpolated in a batch mode and are saved into a data file for each MLIT. Batch mode simulation for a new interconnect configuration can be easily set up and run. Results are then automatically added to the existing database. Second, optimization of an interconnect design is done interactively through goal-directed interconnect synthesis given performance goals, flexible X-Y graphing, and fast on-line performance evaluation for arbitrary layer assignment of an interconnect structure with user-specified risetime, number of coupled traces, temperature, width, spacing, and coupling length. Third, using the invention complete SPICE subcircuit/circuit generation and simulation for an interconnect structure design, including the layer assignment, risetime, width/spacing, and coupling length, can be generated and simulated automatically for εignal integrity analyεiε. Study of the chip-to-chip communication for optimizing driver, interconnect, and receiver design in terms of total delay, noise margin, and other goals can be done more easily and quickly than with other methods. Thus, the invention provides engineers with accesε to interconnect models for all MLITε, and makes different levels of packaging design more compatible and eases the task of system interconnect simulation. The invention drastically improves the productivity of circuit designers because accurate interconnect models can be specified easily without time-consuming capacitance simulations. The model library is designed to free chip deεignerε from the detailε of both interconnect geometry and process variations and provide them with a direct SPICE link. Errors commonly found during manual SPICE deck generations can be reduced significantly. A commercial SPICE circuit simulator can be used without modification. Brief Description of Drawings FIG. la is a block diagram showing interconnections of a data procesεing method and data fileε of the preεent invention; FIG. lb is a block diagram of spreadεheet diεplayε generated by the present invention; FIGε. 2a, 2b, and 2c are graphε of capacitance versus interline spacing; FIG. 3 is a cross section view of a three-line stripline-type multilevel VLSI interconnect; FIG. 4 is a schematic diagram showing resistance, capacitance, and inductance relationships of the materials shown in FIG. 3; and FIG. 5 is a schematic diagram of an exemplary εtripline interconnect. Detailed Description of Preferred Embodiments 1 Introduction and Overview The present invention integrates four setε of data processing methods to enable fast computer aided deεign of complex three-di enεional interconnect εtructureε. In general, the data proceεεing ethodε receive input of layout parameterε and technology parameters identifying the circuit to be designed, and generate output data files for the SPICE circuit simulator. The four data proceεsing methods include (a) a batch-mode computation processing method that combines a 2-D/3-D finite difference numerical simulation and a fast interpolation algorithm; (b) an interactive design procesεing method with performance browεing, goal-directed εynthesis, and on-line performance evaluation; (c) an interactive SPICE subcircuit generator and simulator; and (d) a εpreadsheet-εtyle graphical user interface. The invention thus assiεtε uεers in εelecting interconnect technologieε for deεign-for-performance goals and also in optimizing interconnect performance designs for different types of chip packaging. By changing parameters and constants entered into the spreadεheets provided by the invention, designers can cuεtomize the operation of the invention for other variableε such aε reliability, thermal effectε, and cost effectε. The batch mode element of the invention can be implemented by programming a general purpoεe data proceεsor using standard equations in any suitable programming language. The inventorε have implemented thiε element in the C programming language. The εpreadεheet elements of the invention can be implemented using any of several commercially available spreadsheet computer programs. The inventorε have implemented theεe elementε uεing the commercially available WINGZ εpreadεheet running under control of the UNIX operating εystem on a Hewlett-Packard workstation. FIG. 1 shows main operational modes, process elements, and data files of the invention. The invention operates in three modes, batch mode 100, analyεiε mode 200, and design/simulation mode 300. In FIG. 1, procesε εteps corresponding to each of the three modes are labeled with reference numerals corresponding to the reference numeral used for each mode. Operation of the invention can begin either in the batch mode 100 or the analysis mode 200. The batch mode 100 is used to prepare data files for a new VLSI chip/MCM/PCB construction technique, and therefore is used less frequently. Ordinarily a chip designer uses existing construction techniques and begins with analysis mode 200. Each mode is discusεed below. 2 Batch Mode Batch mode 100 co priεeε εtepε 110, 112, 114 and 212 of FIG. la. The batch mode haε been implemented in a C language computer program. 2.1 Interconnect Parameterε Initially, the program receiveε VLSI chip manu- facturing process parameters entered 110 by a user and stored in technology parameter file 400. Then the program calls a numerical method-based capacitance simulator 112 repeatedly for a plurality of interconnect configurations with two widths and a range of inter-line spacings. The resulting numerical capacitance databaεe 402 iε called CapFile. In one preferred embodiment of the invention, thirty-three interconnect configurations, listed in Table 1, are embedded in the capacitance simulator ("CapSim") program 112. 1. Ml lines above Poly under M2 2. Ml lines above Substrate under M2 3. Ml lines above Silicide under M2 4. Ml lines above Poly under M3 5. Ml lines above Substrate under M3 6. Ml lines above Silicide under M3 7. Ml lines above Poly 8. Ml lines above Substrate 9. Ml lines above Silicide 10. M2 lines above sparse Ml and Poly 11. M2 lines above sparse Ml and Substrate 12. M2 lines above Ml 13. M2 lines above sparse Ml and Poly under M3 14. M2 lines above sparse Ml and Substrate under M3 15. M2 lines above Ml under M3 16. M2 lines above Poly under M3 17. M2 lines above Substrate under M3 18. M2 lines above Silicide under M3 19. M2 lines above Poly 20. M2 lines above Substrate 21. M2 lines above Silicide 22. M3 lines above sparse Ml and Poly 23. M3 lines above sparse Ml and Substrate 24. M3 lines above sparse M2 25. M3 lines above Ml 26. M3 lines above M2 27. M3 lines above Poly 28. M3 lines above Substrate 29. M3 lines above Silicide 30. Poly lines above Substrate under Ml 31. Poly lines above Substrate under M2 32. Poly lines above Substrate under M3 33. Poly lines above Substrate Table 1 — Interconnect Configurations One of ordinary skill in the art will recognize the abbreviationε in the above table as "Ml" for metal 1, "M2" for metal 2, "M3" for metal 3, and "poly" for polysilicon. The above interconnect configurations are for planarized SMI technologies that have three metals and one polysilicon. One of skill in the art will recognize that the twenty configurations can be extended for future SMI technologies having more than three metal levels. CapFile conεiεts of tableε representing two line widths for each of the configurations εhown in Table 1. The configurationε of FIG. 1 apply to integrated circuitε; other modelε are uεed for PCB/MCM. Each table comprises one row for each configuration. Each row correspondε to an interline spacing in microns. A typical table has rows for spacings of 0 microns to 15 microns in 1 micron increments. Each row comprises columns for the interline spacing in micronε, the RC conεtant in ns per cm, total capacitance (Ct) , interline capacitance (Ci) , ground capacitance between two lines (Cgl2) , ground capacitance from one line to substrate (Cglp) and a constant F (2Ci/Ct) . Some configurationε do not have C„ 2 for lack of an upper metal, e.g., configurationε 5 and 6. Subεtrate iε conεidered as a conductor, so C gl always existε. Computation of table valueε iε deεcribed below. 2.2 Curve Fitting Using the Equationε Each row of the CapFile tableε is computed using a curve fitting method shown in block 212. The method has been implemented in a C language computer program called CurveFit, which uses the leaεt-εquare method known in the art to model the capacitance changeε between minimum spacing (0 microns) and 15 μm. Polynomials of degree six are used to curve-fit the non-linear relationship so that the maximum interpolation error can be within 5%. Cubic spline interpolation also can be used for curve-fitting. The CurveFit program alεo readε a reεistance file 404 which contains the sheet rho data for polysilicon, metal 1, metal 2 , and metal 3. The result of CurveFit is an equation file 406 containing curve-fit and linear-fit fileε, reεpectively shown in Table 2 and Table 3, with equations for C- , C gl , C g2 , and R-, arranged in SPICE format. * file-name = curve-fit-mlm2sb •param wid min=0.8 π * ax=10 .param i no=-0.436957 nl=0.778796 n2=-0.408766 n3=0.0727845 + n4=0.00391275 n5=-0.000890772 n6=3.32038e-5 + w0=-p.475644 l=0/865993 w2=-0.481429 w3=0.100322 + w4=-0.00106627 w5=-o.000528231 w6=2.37069e-5 .param g2 n0=32.3302 nl=37.83 n2=-11.5503 n3=l.81954 + n4=-0.155456 n5=0.00683289 n6=-0.000120965 + w0=354.143 l=38.569 w2=-11.8872 w3=l.89499 + 4=-0.163779 w5=0.00726997 6=-0.000129721 .param gl n0=30.197 nl=36.7249 n2=-11.1805 n3=l.75704 + n4=-0.149826 n5=0.00657539 n6=-0.000116269 + w0=334.961 l=37.212 w2=-11.3805 w3=l.80057 + w4=-0.154565 w5=0.00682105 w6=-0.000121114 .param t min=25 max=110 •param r min=69 max=87 .param v Ci=l/(i.n0*(s*le6)**0+i.nl*(s*le6)**l+i.n2*(s*le6)**2+ + i.n3*(s*le6)**3+i.n4*(s*le6)**4+i.n5*(sle6)**5+ + i.n6*(s*le6)**6)+(w*le6-wid.min) / (wid.max-wid.min)* + (l/(i.w0*(s*le6)**0+i.wl*(s*le6)**l+i.w2*(s*le6)**2+ + i.w3*(sle6)**3+i.w4*(s*le6)**4+i.w5*(s*le6)**5+ + i.w6*(s*le6)**6)-l/(i.n0*(s*le6)**0+i.nl*(s*le6)**l+ + i.n2*(s*le6)**2+i.n3*(s*le6)**3+i.n4*(s*le6)**4+ + i.n5*(s*le6)**5+i.n6*(s*le6)**6) ) rw=(r.min+(temp-t.min)/(t.max-t.min)* (r.max-r.min) )/w Table 2 — A Curve Fit File * file-name = linear-fit-mlm2sb •param wid min = 0.8 max = 10 .param gl narrow = 7.9393e+01+(s*le6-15)/(50-15)*(7.9421e+01- 7.9393e+01) wide = 3.8482e+02+(s*le6-15)/(50-15)*(3.8484e+02- 3.8482e+02) .param g2 narrow = 8.2847e+01+(s*le6-15)/(50-15)*(8.2866e+01- 8.2847e+01) wide = 4.0543e+02+(s*le6-15)/(50-15)*(4.0544e+02- 4.0542e+02) .param i narrow = 1.6462e-02+(s*le6-15)/(50-15)*(1.1095e-03- 1.6462e-02) wide = 1.8427e-02+(s*le6-15)/(50-15)*(1.2860e-03- 1.8427e-02) .param t min = 25 max = 110 .param r min = 69 max = 87 .param v cgl = gl.narrow+(w*le6-wid.min)/(wid.max-wid.min)*(gl.wide- gl.narrow) cg2 = g2.narrow+(w*le6-wid.min)/(wid.max-wid.min)* (g2.wide- g2.narrow) ci = i.narrow+(w*le6-wid.min)/(wid.max-wid.min)*( i.wide- i.narro ) rw = (r.min+(temp-t.min)/(t.max-t.min)* (r.max-r.min) )/w Table 3 — A Linear-Fit File If the inter-line εpacing iε narrower than 15 μm, curve-fit fileε are uεed. If the inter-line spacing is wider than 15 μm, linear-fit files are used. Since each configuration in Table 1 haε one curve-fit file and one linear-fit file, the reεulting equation file 406 preferably has sixty-six such fileε. High-density VLSI designerε may use curve-fit files most of the time since C,, C gl , and C g2 do not change much after the spacing is wider than 15 μm. 2.3 Capacitance Calculations for the Tables Since several VLSI technologies use multiple conductors with different thickness and multiple insulatorε with different dielectric constantε, those of skill in the art prefer numerical method-based capacitance simulators for accurate modeling of VLSI interconnect capacitance. Empirically derived equations having multiple parameters, such as line width, inter-line εpacing, conductor thickneεε and dielectric thickness are known in the art for interconnect modeling. Such equationε cannot cover VLSI chip layout configurations with multiple dielectrics and various metal thickness. Furthermore, the ranges of line width and inter-line spacing that can be applied to the multi-parameter equations are limited. FIG. 3 is a schematic cross εection of an exemplary VLSI chip εection 30 constructed with Metal 1 arrays under a Metal 2 plane above Substrate. A low-temperature oxide layer 36 (TEOS, e r =4.1) exists between metal 2 (reference numeral 34) and a plurality of conductor lines 38a, 38b, 38c comprising metal 1. Insulators between metal 1 and substrate 40 include phosilicate glasε 44 (PSG, e r =4.0) and field oxide 46 (FOX, e r =3.9). An inεulation layer 32 coverε the metal layer 34. Three capacitance relationεhips exist related to the center metal 1 line 38b. Two ground capacitances (C gl and C„ 2 ) are developed between line 38b and metal 2 and the substrate, respectively. A one-sided inter-metal-1-line capacitance (C iε developed between line 38b and either of lineε 38a, 38c. If there iε no metal 2 (34) above the metal lineε 38a, 38b, 38c, then no ground capacitance exiεts. The relation of the three capacitance componentε and the commonly uεed total capacitance (C t ) iε expreεεed in Equation 1: C t (aF/μm) = 2 x C; + C gI + C g2 The units of C;, C„,, and C g2 are faradε per micron (F/μm) . In the known art, C, iε calculated and then εectioned for diεtributed εingle-line R,C circuit simulation. It is valid when the two adjacent lineε 38b, 38c remain in a quiet εtate. Due to electrical coupling in high-density interconnects, non-switching and long interconnect lines adjacent to an active line often are not quiet. The effective RC-delay, and croεε-talk muεt be simulated with distributed multi-line R,C models. On the other hand, interconnects on different levels are required by design to run in perpendicular directions, so the coupling between different levels iε εmall. Non-active conductor levels, e.g., power supplies, are considered as quiet. A particular chip technology for VLSI design is affected by three layout parameterε (line width, line length, and inter-line εpacing of an interconnect line) , and technology parameterε (εuch as conductor thickness, dielectric thicknesε, dielectric conεtantε, and tolerance values) . The layout parameters are user-adjuεtable but the technology parameters are fixed and cannot be changed by designers. During VLSI layout, the values of C ; , C gl , and C g2 are affected by the three layout parameterε. The inter¬ line εpacing affectε the capacitance in a non-linear manner. FIG. 2a containε a graph 2 εhowing the non-linear relationεhip of interline εpacing to capacitance. Line width is fixed at .9 microns and the construction is Ml arrays above substrate. Vertical scale 4 indicates farads per micron. Horizontal scale 6 indicateε interline spacing from 1 to 5 microns. Line 8 represents total capacitance, line 10 indicates interline capacitance, line 12 is ground capacitance, and line 14 roughly indicates crosstalk noise. FIG. 2c illustrates the non-linear capacitance relationship versus spacing, when metal 1 line width is fixed at 0.8 μm while the spacing is changed from 1.0 μm to 15 μm. Line 20 represents interline c,, line 22 represents C gl , and line 24 represents C„ 2 . The same phenomena can be found in other conductor levels εuch aε polyεilicon, metal 2, and metal 3. Since capacitance is non-linear in relation to inter¬ line spacing but linear in relation to line width and line length, polynomialε can be uεed to model capacitance as a function of inter-line spacing, aε εhown below: 6 c w i dth ( s ) (a^/μm) = ∑ a t x s 1 i=0 The C wjdlh (ε) iε capacitance per unit length εimulated with a fixed line width and ε iε a variable repreεenting the inter-line εpacing. A least-square method known in the art can be used to curve-fit the non-linearity and generate coefficients for the above polynomial of degree six. The three capacitance curves, C if C gl , C g2 in FIG. 2c, are modeled as three polynomials: C i in (ε) , C glmin (ε) , and C g2min (s) , where min stands for the minimum width specified by the design rule. A reasonably wide width of 10 μm is chosen for polysilicon, metal 1, and metal 2; 20 μm is chosen for metal 3. The coefficients of the six polynomialε are embedded in a SPICE-format file shown in Tableε 2 and 3. Interconnect line width affects capacitance of a line in a linear manner, so the capacitances can be modeled in the form of the following three equations: C i (w,s)(αF/ l x,n) = C. nin(..) + ( w - wid m J. /( W id uα - wi ^J X (Q S)) C g ,(w,s)(αF/μm) -__ C fl Js) + ( w - .vid, n /(wid, ^ - wid ιnin )x(C s , s) - C gl Js)) C !2 (w,s)(αF/μιn) = C.^(s) + (w - wid, α J/(wid l∞I - wid^j fC^fs)) In these equations, wid mil - is the minimum width and wid jn j- is the reasonably wide width; w(in μm) is the line width variable. The Ci(w,s), C gl (w,s) and C g2 (w,s) above are to be multiplied by the length parameter inεide the SPICE subcircuitε. In this way, interconnect capacitanceε are parameterized with layout parameters for a selected technology. Changes in line resiεtance are linearly proportional to the temperature, the line length, and the inverεe of the line width, εo the reεistance per unit length can be calculated by: Rw(W)(ιnQ/μm) = (R nm + (Te,np - T ιm J/(T ma - T ^ X fR ^ - R m J)/w (6) where R ^ , is wire resistance per micron length, w (in μm) is the line width variable, T mιn is the minimum temperature, R mm iε the εheet rho (mΩ/D) at T nιιn , T max , and temp iε the operating temperature of the chip. Temp iε alεo a parameter but it iε a global variable in SPICE and need not be specified for each interconnect segment. The R ^ above iε to be multiplied by the length parameter inεide the SPICE εubcircuit as well. Since C,, C gl , C„ 2 , and R,„ can be polynomial-fitted as functions of interconnect dimension, their distributed R,C effects are modeled by a three-line π3 R,C circuit model known in the art, and consiεtε of three caεcaded π R,C models to represent a distributed single-line interconnect for circuit simulation. Considering the increased coupling among submicron interconnects, we extend the single-line π3 model to a three-line π3 model for accurate SMI RC-delay and cross-talk simulation. 2.4 Interfacing Models to SPICE The electrical characteristics of VLSI interconnects are simulated using SPICE by creating a SPICE εubcircuit representation of each interconnect. FIG. 4 is a schematic representation of electrical characteristicε of two lineε of the interconnect of FIG. 3. The interconnect 50 of FIG. 4 has two input points 52, 54 which correspond to terminalε of lineε 38b, 38c of FIG. 3. Each line 38b, 38c has an impedance represented respectively by resiεtorε 56, 58. Inductance of the two lines 38b, 38c iε εhown by inductors 60. Capacitor 62 interconnects the lines and represents the interline capacitance of FIG. 3. Ground capacitances are respectively represented by capacitors 64, 66. A SPICE εubcircuit call statement εpecifying two lineε, 1.0-cm-long metal 1 arrayε, line width of 4 μm and inter-line εpacing of 2 μ would appear aε followε: XI %inl %in %in2 %outl % out % out! 0 lmlsb (4u 2u lOOOu) where XI is the name of the metal 1 arrays to be modeled. A three-line model requires seven external node names specified to connect the three inputs, three outputs, and ground to adjacent circuits. After the node name specification, the above call statement specifieε the subcircuit being called, mlm2sb, and the three layout parameterε, width, spacing, and length (inside the parentheses) . "mlm2εb" is the acronym for "Metal 1 arrayε under Metal 2 above Substrate." For 2.0-cm-long metal 1 arrays, the εpecification iε: X2 %inl %in %in2 %outl 7c on t % out 2 0 mlιn2sb (4u 2u 20000u) The following specification will give better accuracy, however, because the number of sections is increased from three to six: X21 %/«/ %in %iιι2 %tnψl %tnφ % ψ2 0 mim2sb (4u 2u lOOOOu) X22 %ttnpl %tιnp %tnψ2 Ψcoutl %out %our2 0 miιn2sb (4u 2u lOOOOu) With more sectionε, the total number of nodeε to be proceεεed by SPICE will be increased and the execution time will be longer. For on-chip tranεmiεεion line modeling, the length of each εubcircuit call εtatement should be determined by the rise time. The batch-mode computation algorithm is derived from the "HIVE" algorithm as disclosed in the following papers: (1) K-J Chang et al . , "HIVE: An Expreεε and Accurate Interconnect Capacitance Extractor For Submicro Multilevel Conductor Systems," presented at the VMIC Conference, 11-12 June 1991; (2) K-J Chang et al . , "HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs," presented at ICCAD, November 1991; and (3) S-Y Oh et al . , "Phyεical and Technological Limitationε and Their Optimization in Submicron ULSI Interconnect," presented at the ICVC '91 conference, Seoul, Korea. The HIVE algorithm computes selective lateral and vertical capacitances of sub-micron IC interconnects using finite-difference methods. The non-calculated capacitances can then be obtained through faεt interpolation. The assumptions which are used for extracting submicron on-chip interconnect capacitances as reported in the above paperε are also valid for MCM and PCB. These asεumptionε include the following. Firεt, interline ("Cil") and vertical ("Cg") capacitances linearly vary with trace width when the interline spacing is fixed. Second, with enough points for numerical simulation of capacitances in which interline spacing is varying and width fixed, other capacitances for any spacingε bounded by the simulated spacings can be interpolated. Capacitance values can be computed using the FCAP2 and FCAP3 algorithms which are known in the art and available in commercial C language libraries for numerical simulation; these algorithms are described in the following references: Kit Cham et al . , Computer-Aided Design and VLSI Device Development (2nd Edition) , Lower Academic Publishers, Norwell, Massachusettε, 1988, pp. 348-351, and Ken Lee, "Three-Di enεional Modeling of Interconnect Capacitance and Inductance", Workshop on Interconnect Modeling and Technology , IEEE Solid-State Circuitε & Technology Committee, San Diego, California, May 1989. For example, the changes of both "Cil" and "Cg" of a stripline for a thin-film MCM behave linearly when the width is changed but the εpacing iε fixed. Therefore, for a fixed spacing, only two capacitances need be calculated using numerical simulation; capacitance values for different widths can be interpolated. However, due to the slight non-linearity of capacitance curves versus spacing when the width is fixed as shown in FIG. 2c, more points are needed using numerical simulation. This permits uεe of linear, polynomial, or cubic εpline interpolation for different spacings depending on the accuracy desired. In either way, the interpolated capacitances are carefully checked to ensure that the maximal induced error is around 3% of the capacitance. 3 Analysis Mode 200 The analysiε mode 200 co priεeε steps 210, 214, 216, 218 and 220 of FIG. la. The mode can be implemented by programming a spreadsheet to display a menu tree and a spreadsheet worksheet having a plurality of rows and columns, εo that each row comprises a plurality of cells for text or numeric information. Any general purpose spreadsheet can be used but in a preferred embodiment, the WINGZ spreadεheet is used, which is commercially available from Informix Software, Inc. , Sales & Information, 913-599- 7100. One of skill in the art will recognize that the invention could also be implemented using a general purpose relational databaεe εyεtem. Preferably the εpreadsheet is programmed to present the user with a plurality of menu choices organized aε shown in Table 4. Each menu option is discusεed εeparately below. Performance .. Performance Browse or Create .. Database .. Delete database for a construction .. Check existing models .. Generate all traces database .. Generate chosen trace database Plot . width ... spacing . width with spacing contour . spacing with width contour .. Synthesis ... Synthesis Setup ... Goal-Directed Synthesis Evaluation .. Evaluation Setup .. Model Evaluation .. Performance Evaluation SPICE .. SPICE Setup .. SPICE Create Window (moves among windows on workstation screen) Menu .. Main Menu .. Restart Table 4 — Spreadsheet Menu Choices FIG. lb εhowε a compressed representation of a main spreadsheet 500 of the invention. The main spreadsheet 500 is divided into a user parameter worksheet 502, a performance assumptions worksheet 520, and a construction databaεe workεheet 530. A εeparate conεtruction εetup worksheet 540 is coupled to the construction database worksheet 530. Each of the worksheets comprises a plurality of interrelated cells. As iε known in the art, each cell can be programmed with a numeric formula so that a change to one cell results in rapid calculation and redisplay of related cells. One of skill in the art will recognize that the cells and worksheets can be represented in a conventional computer memory or uεing a relational database εyεtem. Preferably the workεheets are stored on a conventional mass storage device, such as a hard disk drive, to enable long-term εtorage of the data therein. The user parameter worksheet 502 preferably comprises a plurality of rows 504 each having cells 506, 508, 510 and 512 for entry of text or numeric data. In a preferred embodiment of the invention, the worksheet 502 has three rows 504. The firεt row acceptε uεer entry of a line width range in micronε, εuch aε 10 microns, 20 microns, etc. The second row accepts uεer entry of a line spacing range in microns, such as 40 microns, 50 microns, etc. The third line displayε available metallization modelε which are abbreviated by acronyms known in the art, such as SM, BMO, SL, DSS, etc. Thus, using the user parameter worksheet, a user can enter preferred interconnect line width and spacing for use by other elements of the invention. Preferably the asεumptionε worksheet 520 has a plurality of cells 522, 524, 526 for display and entry of technology parameters relating to the chip under development. Preferably, the assumptions worksheet cells include cells for entry or display of signal rise time in ns, chip operating temperature in centigrade, coupled length in incheε or centimeters, and a plurality of columnε for entry or diεplay of εoldermask data. Each soldermask column comprises a plurality of cells in the column for entry or display of soldermaεk name, εoldermask thickness in microns, soldermaεk dielectric coefficient, metallization type (such as copper or aluminum) , and metal resistivity in ohms per meter. Preferably the construction worksheet 530 comprises a plurality of spreadεheet cellε 532, 534, 536 containing data relating to electrical and phyεical characteristics of different parameters of a particular chip construction. Each row of the construction worksheet 530 contains all parameters relating to one particular construction type. Each column identifies a parameter. Table 5 lists preferred data types and units for each column. Coupled to the asεumptionε workεheet 520 is a separate performance database worksheet 550. Preferably the performance worksheet 550 compriseε a plurality of rowε, each having a plurality of column cellε repreεenting electrical performance characteristics of a particular construction for a particular number of traces, trace width, and trace spacing. The performance worksheet is activated by selecting the PERF BROWSE option, which causes the data procesεor to load and display a performance worksheet. Table 6 listε preferred data typeε for each column of a row, including unitε and εpreadεheet formulas by which the column cells are computed, for a five-line model. As indicated, the performance worksheet contains performance values computed according to all the other entered data. Table 6 — Performance Worksheet Data Types Thus, each interconnect conεtruction iε εpecified with a common set of characteristic parameterε, εuch as number of layers, dielectric conεtantε, dielectric thicknesses. conductor type, soldermaεk or overcoat dielectric constant and thickneεε, outer layer and inner layer conductor thicknesses, and number of coupling traces. Since different interconnect domains have different sets of characteristic parameterε, in the preferred embodiment three separate construction worksheets are maintained for IC, MCM thin film, and PCB/MCM thick film constructions. The performance worksheet containε representative data points for interconnect capacitances which are extracted numerically for all the conceivable models of a new construction in the batch mode. For example, a 4-layer MCM construction can have models εuch aε stripline (SL) , dual stripline (DSS) , εurface microεtrip (SM) , and buried microstrip outer (BMO) . A linear interpolation algorithm can then be applied to generate any other points bounded by the width/spacing ranges of the simulated points. The simulated capacitances are subεequently used to derive inductances L and transmiεsion line properties, including Z 0 , Z e , Z eff (odd, even effective mode impedances) ; Pd 0 , Pd e , Pd tff (odd, even effective propagation delays) ; and V B , V F (backward, forward crosstalkε) for all the interconnect models. The formulas uεed for these derivations are known in the art and are discussed, for example, in the following references: H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI , Addison-Wesley, Reading, Massachuεettε, 1990; A. Feller et al . , "Croεεtalk and Reflectionε in High-Speed Digital Syεtemε," Proceedings of Fall Joint Computer Conference , 1965; J. Buchanan, BiCMOS/CMOS Systems Design , McGraw-Hill, Inc., 1991. 4. Interactive Design Functions (Goal Directed Svnthesiε and Evaluation Panel) Goal-directed interconnect εynthesis helps userε to narrow down possible interconnect designs quickly. The domain of search is all processes/technologies that have been simulated in the batch mode. The invention extracts a subset of designs that satisfy multiple performance goals, εuch aε impedance and noiεe margin, εpecified by the user. The user can alεo look at the effect of changing trace width/spacing on any performance variable by using the graphing facility of the invention discussed below. This is done by showing any performance variable versus trace width and/or trace spacing. An arbitrary number of graphs can be generated, so a user can simultaneouεly visualize trade-offs for different trace width/εpacing deεignε aε well aε their impact on εeveral performance variableε. To accompliεh goal-directed εyntheεis, the user selects SYNTHESIS from the spreadsheet menu tree. The SYNTHESIS SETUP option is selected, causing the data procesεor to display a setup window on the workεtation. Preferably the setup window is a spreadεheet worksheet comprising five columnε entitled PARAMETER, UNIT, RELATIONSHIP, MINIMUM VALUE, MAXIMUM VALUE, and INPUT. Preferably the workεheet has ten rows identified with nameε in the PARAMETER column. The rowε repreεent model name, layerε in the interconnect, trace width (milε) , trace spacing (mils) , impedance (Ohms) , signal propagation delay (picosecondε/inch) , noiεe margin (mV/V) , lateral crosstalk (mV/V) , vertical crosεtalk (mV/V) , and coupling coefficient. The parentheεized unit identifiers are depicted in the UNITS column. In the RELATIONSHIP column the data procesεor displays reference text such as noise margin data. The worksheet accepts user entry in the MINIMUM VALUE and MAXIMUM VALUE columnε. Syntheεis setup iε then complete. Next, the user selects the GOAL-DIRECTED SYNTHESIS option - from the spreadεheet menu. In response, the data processor displayε a window of performance data for constructions meeting the criteria specified in the setup window. The displayed data is selected from the performance data worksheet 550 by comparing values therein with MINIMUM VALUE and MAXIMUM VALUE entries provided by the user. An evaluation panel is provided for users to do stackup design. Stackup design involveε assigning signal or reference planes to each layer of an interconnect construction. Once a user εpecifieε layer assignment for a selected construction, the invention can determine layer models for each layer. Furthermore, on-line performance evaluation can be done for each signal layer given an arbitrary trace width and εpacing within the interpolation range. Evaluation is initiated by selecting the EVALUATION SETUP spreadsheet option from the menu. In response, the data processor displays a spreadεheet worksheet containing a plurality of layer rows, each row corresponding to a layer of the construction type under analysis. The worksheet further includes a plurality of layer cells in each row corresponding to different parameters which characterize each layer. Preferably, the layer cellε permit entry of data for layer type (soldermask or active layer) , layer aεsignment (mask, signal, blank signal, or reference) , and layer model (surface microstrip, stripline, etc.). When these values are entered, evaluation setup is complete. Next, the user selects MODEL EVALUATION. In response, the data processor computes and fillε in data for each cell of the performance workεheet, identified above in Table 6. Thus, by choosing a specific εignal layer from the evaluation worksheet, the user can generate and simulate SPICE subcircuitε through the interactive SPICE setup worksheet and SPICE window and thereby evaluate performance of different layers. 5 SPICE Subcircuit Generator If the test of step 216 is true, control iε passed to step 220 in which the invention will generate a SPICE deck or file for the interconnect being analyzed. Passage of control to step 220 iε uεually accomplished by the user moving the mouse of the workεtation to the SPICE spreadsheet menu option. In responεe, the data processor displays two sub-options: SPICE SETUP and SPICE CREATE. When the user selectε SPICE SETUP, the data processor displays a SPICE SETUP spreadεheet workεheet. The worksheet displays setup conditions for SPICE simulation of coupling of specified traces. Traces can be specified as active or inactive, where active means connecting the input of the trace to a pulse that has a user-specified rise time. The user can specify the termination of a trace by providing a characteristic impedance in ohmε or by specifying open termination. Preferably a first area of the worksheet contains cells for input of a default characteristic impedance, and for rise time, pulse width, and period of active trace input signals. A second area of the SPICE SETUP worksheet contains a plurality of rows, each row corresponding to an interconnect trace. Each trace row compriseε a plurality of cellε to εtore data representing the trace number, whether the trace is active or inactive, input impedance, whether ground is present, names of input and output nodes connected by the interconnect, and a characteristic termination impedance. Each cell iε filled by the uεer with numeric data for use by the SPICE CREATE option. When the user selects SPICE CREATE, in step 220, the method of the invention causes a data processor to read the equation file 406 and generate parameterized three-line π3 circuit models for distributed R,C circuit simulation. The resulting SPICE deck is written to a parameterized model file 420. To form the SPICE deck, C gl , and C g2 read from the equation file are added to form C g . Then C g , C i t and R ^ , are multiplied by the line length of the interconnect and divided by three, respectively, to become three εeparate circuit elements. The capacitances on the boundary must be further divided by two. For each configuration in Table 1, a curve-fit R,C file and a linear-fit R,C file is generated. The resulting parameterized model library haε forty distributed R,C SPICE subcircuits. The parameters for each subcircuit are line width, inter-line spacing, and line length. Chip operating temperature is also a parameter but it can be accessed in a global manner and need not be specified in each subcircuit call statement. After creation of a SPICE deck, the user can activate the SPICE program using a separate workstation window, and specify the just-created SPICE deck aε input. All known and ordinary SPICE functions can be executed. 6 Plotting Graphs Once the performance database iε built, the user can use the invention's performance browser and graphics capability to look at different curveε of intereεt. To plot a graph, the uεer first moves the workstation cursor to any single cell in the performance worksheet. Then the user selects the PERFORMANCE PLOT option from the spreadsheet menu. Four options called WIDTH, SPACING, WIDTH WITH SPACING CONTOUR, and SPACING WITH WIDTH CONTOUR are available to plot capacitance versus trace width or trace spacing. The selected option generates a graph based on the data in the previously selected cell. Graphε are generated uεing the public-domain XGRAPH program developed by U.C. Berkeley. FIG. 2b εhowε a typical graph 630 of effective impedance verεus interline εpacing which can be produced in a workstation window by the invention. The vertical scale 632 shows effective impedance and the horizontal scale 634 shows interline spacing in microns. Lines 636, 638, and 640 represent effective impedance of traceε of 40, 50, and 60 micronε in width, respectively. Other graphs produced by the invention show crosεtalk verεuε impedance. 7 Databaεe and Miεcellaneous Functions The spreadsheet menu preferably includes a plurality of database function menu options. The DATABASE DELETE function enables deletion of data in a worksheet. The DATABASE CHECK EXISTING MODELS function performε a search of a worksheet and finds all models matching a chosen construction. For example, when the CHECK EXISTING MODELS option is selected, after user entry of layer number, construction technique, and core thicknesε, the data processor will search the conεtruction databaεe to locate construction models matching the selected criteria. The WINDOWS option enables the user to rapidly enter a currently active window for the PERFORMANCE, SYNTHESIS, EVALUATION, or SPICE functions. The MENU option has two sub-optionε to return the user to a main menu and to restart the syεtem of the invention. 8 Example: Clock Tree Deεign Table 7 below εhows a parameterized SPICE circuit interconnect specification for an exemplary clock tree. The clock signal is distributed from the center, %cntr, to the eight cells through fourteen metal 2 interconnect segments. Each segment is described by a parameterized interconnect subcircuit call statement starting with "X". The subcircuit names being called in each statement, e.g., m2mlpy and m2m3sb, start with m2 becauεe the active level is metal 2. The seven interconnect εegmentε X2, X5, X6, Xll, X12, X13, and X14, are under denεe metal 3 power/ground buεes. Therefore, the corresponding called subcircuits have m3 in the middle of their nameε. The clock skew between nodes %lul and %rur is 0.5 nanosecond. After the trace widths of Xll to X14 are increased to 1.0 μm, the clock skew is decreased to 0.2 nanosecond. If this is still not tolerable. Each SPICE input adjustment takes less than ten seconds. If the interconnect is not parameterized, circuit deεignerε must run time-consuming capacitance simulatorε εeveral timeε. Furthermore, manual conversion of the capacitance values into distributed R,C SPICE subcircuits is tediouε and error prone. A SPICE input representing a clock distribution in H- tree is arranged by using the parameterized subcircuits for clock-skew simulationε. Table 8 provides a listing of the interconnect portion of the H-tree of this example. The clock signal is transmitted by metal 2 from %cntr to the eight cells. The four cells on the right side are under a dense distribution of metal 3 power/ground buses. Each segment of the H-tree iε repreεented by a subcircuit starting with X. Each subcircuit consists of three lines. The center line represents the clock line for worst-case design. So seven nodes are needed for each subcircuit representing three inputs, three outputs and the ground node. At firεt, the trace width of Xb to Xe εubcircuitε is 0.8 μm, the same as that of X7 to Xa. Since the metal 3 affects the interconnect capacitance and it is primarily on the right-hand εize, it cauεeε the εymmetric H-tree to have 0.5 nanosecond clock skew. This is done by comparing the delay of %lul with that of %rur. When the trace width of Xb to Xe is increased to 1.0 μm, the skew iε decreased to 0.2 nanosecond. The SPICE input can be adjusted in this way until the clock skew is tolerable. Each SPICE input change takes lesε than ten εeconds. If the SPICE deck is not parameterized, VLSI designers have to do 2-D/3-D simulations for times to come up with a new SPICE deck. It takes at least two hourε to make one trace width change since the 3-D capacitance εimulation of each of the four subcircuits needs at least fifteen minutes. The arrangement of the new simulated capacitance into SPICE deck is tedious and takes about an hour. 9 Example: Signal Communication Optimization A εimplified chip-to-chip εignal communication optimization problem demonεtrates how the invention helps designers analyze and optimize the interconnect design. In this example, shown in FIG. 5, a signal 72 transmits from an output driver pad to a receiver pad 82 through a multi¬ line transmission line 78, 80 on an MCM, ignoring solder bumps required between the chips and the MCM. To further simplify the example, the output driver signal 72 is represented by a single low-to-high pulse with 0.2 ns risetime and 40 Ω source resiεtance. The receiver is assumed to have a high input impedance. The distance between driver and receiver is required to be 8 cm on a MCM. Interconnect choices include stripline or microstrip coupler configuration on εeveral MCMε with different dielectric thickneεses and with or without coatings. The goal is to achieve minimum delay and crosstalk possible and no more than 1 ns delay and 100 mV/V crosstalk. To use the invention to optimize the design in this case, first, a user runs batch-mode simulations for possible interconnect design configurations. Several construction choices for the MCMs are reviewed from the list in Table 1. Three are polyamide and ceramic materials with dielectric constants of 4.0 and 9.0, respectively. Coatings of various thicknesses are available for microstrips. Alεo, trace width ranges from 10 to 60 μm, and trace spacing ranges from 40 to 500 μm. The result of the batch-mode εimulation iε the interconnect R,L,C, impedance, propagation delay, and crosstalk information in the database for εurface microstrip, buried microstrip outer (with coating) , and stripline configurationε for various technologies. Next the designer can enter impedance and noise margin goals in the synthesis worksheet and the invention will return all the choiceε that satisfy the requirements. The user can then use the evaluation worksheet to do more detailed design by εpecifying layer aεsignments for the chosen MCM technology. Arbitrary choices of trace width/spacing, coupling length, and risetime can be specified, and performance information can subsequently be derived. Thus, the invention helps designerε to analyze and optimize interconnect deεignε in an interactive way. There are other design constraints, such as cost, thermal management, power consumption, and manufacturability, that determine the final choice of a certain technology. For this application example, an open-ended termination coupler has less power consumption than a well-terminated coupler. The cost of 9.0 dielectric material is lesε than that of 4.0 dielectric material, and the cheaper material may satisfy performance requirements as well. Microstrip with coating iε more manufacturable than εtrip-lines. It would be difficult to know all the constraints up front before exploring possible alternatives. Since the example has a driver with 0.2 ns risetime and 40 Ω source resistance, an open-ended termination microstrip (with coating) coupler with length of 8 cm is used on a 4.0 dielectric material with T/W + 40 μm, T\S + 60 μm, and dielectric thickness of 20 μm. • For this choice, the final performance result are 0.54 ns delay, and 31 and 61 mV/V reduced noise margin due to crosstalk and reflection for near and far ends, respectively. The invention database can also be uεed not only for pre-layout εystem-level cost-performance analysis but also for schematic capturing and post-layout parasitic circuit extraction. However, both the database format and the layout extraction methodε for the IC/MCM/PCB tools must be modified before the interconnect performance extraction routines and database can be integrated and used. 10 Conclusionε and Further Technical References Thus, this invention provides an interconnect modeling system with many significant advantageε. The invention improves the productivity of VLSI designerε through efficient SPICE deck generations for interconnect designs. The invention allows VLSI designers to specify accurate interconnect models as easy as transistor models without any 2-D/3-D simulations. Existing SPICE simulator software is used unmodified. The invention isolates the chip designer from the details of SMI geometry and process variations. Errors which are commonly found during manual SPICE deck generations are reduced significantly. Submicron VLSI circuits can be easily optimized by using the non-linear multi-variable optimizer and SPICE since both the transistors and the interconnects are parameterized. One of ordinary skill in the art will recognize that this invention could easily be used for interconnect modeling of multi-chip modules, hybrid packaging, and printed circuit boards. The invention provides immediate results to the user and the average execution times of the three functions in an HP/Apollo 720 workstation are within 1 second while 2-D/3-D ad-hoc simulationε take about 20- 1000 seconds. Therefore, the time required for an embodiment of the invention to calculate tens to hundreds of data points for all the user-specified models for a construction is much less than the time needed for 2-D/3-D ad-hoc simulations, which provide a single data point for a specified geometry. Further technical background relating to the technology disclosed herein may be found in the following publications: (a) Al Barber et al . , "Modeling and Analysis of High Speed VLSI Interconnects for Digital Applications," HP Labs Report HPL-02-03 , January 1992. (b) L. Barford et al . , "Parametric Design Assistant and its Application to PCB Construction," HP DTC, May 1991. (c) Kit Cham et al . , "CMOS14/BiCMOS14 Process and Performance," Proceedings of HP DTC, pp. 429-436, May 1991. (d) W. H. Chang, "Analytical IC Metal-Line Capacitance Formulas," IEEE Trans . Microwave Theory and Technique, pp. 608-611, Sep. 1976. (e) J. H. Chern et al . , "Multilevel Metal Capacitance Models for CAD Design Syntheses Systems," IEEE Electron Device Letters, vol. EDL-33, pp.32-34, Jan 1992, (f) Informix Software, Inc., Wingz Reference Manual , 1991, (g) IPC, Design Guidelines for Electronic Packaging Utilizing High-speed Techniques , IPC-D-317 Report, American National Standards Institute, 1991. (h) N.P. van der Meijs et al . , "An Efficient Finite Element Method for Submicron IC Capacitance Extraction," 26th ACM/ IEEE Design Automation Conference , pp. 678-681, June 1989. (i) Larry L. Moreεco, "Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints," IEEE Trans . Comp. , Hybrids, Manuf . Technol . , vol. 11, pp. 494-508, September 1990. (j) Olgierd A. Palusinεki et al . , "Modeling of Performance-Related Design Trade-offs in Multiple-Chip Assemblies," Proceedings of IEEE/CHMT IEMT Symposium, pp. 333-336, March 1991. (k) Vivek Raghavan et al . , "A New Nonlinear Driver Model for Interconnect Analysiε," 28th ACM/IEEE Design Automation Conference , pp. 561-566, June 1991. (1) T. Sakurai et al . , "Simple Formulaε for Two- and Three-Dimensional Capacitances," IEEE Trans . Electron Devices , pp. 183-185, Feb 1983. (m) Peter A. Sandborn, "A Software Tool for Technology Trade-off Evaluation in Multichip Packaging," IEEE/CHMT IEMT Symposium , pp. 337-340, 1991, (n) TMA, Inc., TMA Raphael User ' s Manual , Oct. 1991. (o) Rick Walker et al . , "Circuit Optimization Using the Simplex Algorithm," Proceedings of HP DTC, pp. 390-397, May 1989.

Claims: CLAIMS 1. A computer-aided method of designing semiconductor interconnects, the method comprising the stepε of: selecting a semiconductor interconnect construction type; operating (200) a general purpose data processor to display a first spreadsheet (502) of semiconductor construction parameters for the selected construction type; accessing a stored database (402, 404, 408) to read electrical characteristicε of the εelected conεtruction type; operating the data proceεεor to display a second spreadsheet (520) of electrical performance data for the selected construction type based on the εtored database; providing (222) the data processor with desired electrical performance goal data; and operating the data procesεor to display a third spreadsheet (530) of construction data matching the goal data; wherein each of the εpreadεheetε compriεeε a plurality of automatically updated spreadsheet cells (506, 524, 534) organized in a matrix of rows (504) and columns. 2. A method as in claim 1 wherein the step of providing (222) the data proceεεor with deεired electrical performance goal data compriεeε: providing maximum and minimum goal valueε for at least one parameter choεen from the group of trace width, trace spacing, impedance, εignal propagation delay, noise margin, and crosstalk, and operating the data procesεor to diεplay the goal values in a synthesis setup workεheet that haε a plurality of synthesis cells organized in a matrix of rows and columns. 3. A method as in claim 1 wherein each row of the third spreadsheet relates to a single construction type and each column of the firεt workεheet containε parameter data representing a unique physical characteristic of the selected construction type. 4. A method aε in claim 1 and further comprising the steps of: operating the data processor to display and receive data in an evaluation setup worksheet having a plurality of rows each corresponding with a layer of the selected construction type, and specifing a layer asεignment for each εaid layer. 5. A method aε in claim 1 and further comprising the step of operating (220) the data procesεor to write a file of SPICE subcircuit data corresponding to the selected construction type. 6. A method as in claim 5 and further comprising the step of operating the data processor to display and receive data in a SPICE setup worksheet having a plurality of rows each corresponding with a trace of the selected construction type and a plurality of columns for entry of driving εignal data and characteriεtic impedance of each row. 7. A method as in claim 1 wherein the step of accessing the stored databaεe comprises interpolating electrical performance data for performance characteristics not present in the stored database. A method as in claim 7 wherein interpolating electrical performance data compriseε: reading a plurality of material configuration values corresponding with a plurality of semiconductor trace line width valueε from a capacitance data file (402) ; and iteratively computing, for a plurality of trace line widthε of the selected construction type, electrical performance characteriεticε of εaid εelected construction type, said electrical performance characteristics including an interline capacitance value and a ground capacitance value. 9. A method as in claim 8 wherein the material configuration values comprise (a) total capacitance and (b) data corresponding to at leaεt two layout parameters relating to the selected construction type, the layout parameters selected from the set of line width, line length and interline εpacing. 10. A method as in claim 7 wherein interpolating electrical performance data compriseε: reading a databaεe table containing capacitance values for a multiple-trace interconnect, and setting one of the electrical performance characteristics of the selected construction type equal to a capacitance value of said multiple-trace interconnect.

Inventors: CHANG KEH-JENG, CHANG NORMAN H, LEE KEUNMYUNG, OH SOO-YOUNG, CHANG, KEH-JENG, CHANG, NORMAN, H., LEE, KEUNMYUNG, OH, SOO-YOUNG
Applicants: HEWLETT PACKARD CO, HEWLETT-PACKARD COMPANY
Application year: 1993
Main classification: G06F15
IPC codes: G06F17, H01L23