Superheterodyne receiver

Abstract: The present invention provides a superheterodyne receiver apparatus using a PLL synthesizer technique, wherein: a receiver circuit adopting the superheterodyne technique is formed into a single semiconductor chip comprising a pseudo band-pass filter employing components equivalent to those of an intermediate-frequency filter of the receiver circuit and an oscillation circuit employing the pseudo band-pass filter as a feedback path thereof; and the oscillation circuit oscillates at a frequency equal in value to the centre frequency of the intermediate-frequency filter. The semiconductor chip is further equipped with a PLL circuit allowing the frequency-division ratio of a variable frequency-division circuit to be varied in order to control a reception frequency, and the oscillation frequency of the oscillation circuit is monitored. Data representing the reception frequency is derived from the monitored oscillation frequency and the value of the frequency-division ratio of the variable frequency-division circuit" and then output to a display element to display the reception frequency.

Description: The present invention relates to a superheterodyne radio receiver which uses a PLL synthesizer technique. When integrating a radio receiver using a superheterodyne technique into a single-chip IC, using a ceramic filter as an intermediate-frequency filter makes it impossible to build the intermediate-frequency filter into a single monolithic IC. Therefore, configuring an intermediate-frequency filter as an active filter comprising resistors, capacitors and an operational amplifier has been taken into consideration. With such an active filter, however, setting the intermediate frequency to the standard value of 450 kHz will make the area of the semiconductor chip of the IC occupied by the active filter large and, hence, undesirable. As another alternative, the intermediate frequency can be lowered to a value of typically 55 kHz, a value considered to be sufficiently below the frequencies in the reception band, in order to solve the above problem. A typical radio receiver and a typical IC employed therein are shown in Fig. 5 of the accompanying drawings. A portion 10 enclosed by a dotted dashed line in the figure is a monolithic IC for a single-chip AM receiver. Notations T1 to T8 are its external pins. The pin T3 is a power-supply pin whereas the pin T4 is a ground pin. Components outside the dotted dashed line are parts or circuits. Reference numeral 1 denotes an antenna tuning circuit and reference numeral 2 is a resonant circuit for exciting local oscillation. The antenna tuning circuit 1 further comprises a bar antenna (antenna tuning coil) L1 and a variable capacitor VC1 while the resonance circuit 2 comprises a local oscillation coil L2 and a variable capacitor VC2 which is interlocked with the variable capacitor VC1. In addition to the components cited above, the radio receiver further comprises a power-supply switch SW, a power-supply battery BATT having a voltage of typically 3 V, a variable resistor VR for volume adjustment and a speaker SP. The antenna tuning circuit 1 selects and extracts a broadcast-wave signal Sr which is expressed by the following equation: Sr = Er ·sin ωrt where ωr = 2πfr Thereafter, the signal Sr is processed by the radio receiver. In the processing of an incoming signal, only relative relations of amplitude and phases are of interest. Therefore, the initial phase of each signal is omitted from the above equation and the following description. The signal Sr is then supplied to a high-frequency amplifier 11 through the pin Tl of the IC 10. The signal Sr amplified by the high-frequency amplifier 11 is subsequently output to first and second mixer circuits 12A and 12B. Connected to the resonance circuit 2 through the pin T2, a local-oscillation circuit 13 generates a local-oscillation signal So. The oscillation frequency of the oscillation signal So has a value of 2fo which is given by the following equation: 2fo = (fr + fi) x2[kHz] where fi is an intermediate frequency having a value of typically 55 kHz. The local-oscillation signal So is supplied to a frequency-division circuit 14 where it is split into different local-oscillation signals Soa and Sob each having a frequency equal to half the frequency of the local-oscillation signal So. The difference in phase between the local-oscillation signals Soa and Sob is 90 degrees. The local-oscillation signals Soa and Sob are expressed as follows: Soa = Eo · cos ωo t Sob = Eo · sin ωo t where ωo = 2πfo The local-oscillation signals Soa and Sob are multiplied by the broadcast-wave signal Sr and then supplied to the first and second mixer circuits 12A and 12B respectively to result in signals Sia and Sib as follows: Sia = Sr · Soa = Er · sin ωr t · Eo · cos ωo t = α {sin (ωr + ωo ) t+ sin (ωr - ωo ) t} Sib = Sr · Sob = Er · sin ωr t · Eo · sin ωo t = α {-cos(ωr + ωo ) t+ cos (ωr - ωo ) t} α = Er·Eo/2 Signal components having a frequency of (ωr + ωo) are eliminated from the signals Sia and Sib while those with a frequency of (ωr - ωo) are used as an intermediate-frequency signal as will be described later. Elimination of the signal components having a frequency of (ωr + ωo) yields the intermediate-frequency signals as follows: Sia = α · sin (ωr - ωo ) t Sib = α· cos (ωr - ωo ) t Here, let an image signal Sm be given by the following equation: Sm = Em ·sin ωm t where ωm = ωo +ωi ωi = 2πfi Since the broadcast-wave signal Sr from the tuning circuit 1 conveys the image signal Sm, the signals Sia and Sib can then be expressed as follows: Sia = α · sin (ωr - ωo ) t+ β · sin (ωm -ωo ) t Sib = α · cos (ωr - ωo ) t+ β · cos (ωm -ωo ) t where β = Em · Eo/2 In addition, since the relation ωr < ωo < ωm holds true, the above two equations can be rewritten into the following: Sia = α · sin (ωr - ωo ) t+ β · sin (ωm -ωo ) t = -α ·sin (ωo - ωr ) t+ β · sin (ωm -ωo ) t Sib = α · cos (ωr - ωo ) t+ β · cos (ωm -ωo ) t = α · cos (ωo - ωr ) t+ β · cos (ωm -ωo ) t These signals Sia and Sib are supplied to first and second phase-shifting circuits 15A and 15B respectively. The first and second phase-shifting circuits 15A and 15B are each an active filter which typically comprises capacitors, resistors and an operational amplifier. The first phase-shifting circuit 15A shifts the phase of the signal Sia by  degrees whereas the second phase-shifting circuit 15B shifts the phase of the signal Sib by ( + 90) degrees. Accordingly, in the band 45 to 65 kHz, the difference in phase between the two shifted signals Sia and Sib is in the range 89 to 91 degrees. In this way, the first and second phase-shifting circuits 15A and 15B cause the phase of the signal Sib to lead ahead of that of the signal Sia as expressed by the following equations: Sia = -α ·sin (ωo - ωr ) t+ β · sin (ωm -ωo ) t Sib = α · cos {(ωo - ωr ) t+ 90°} + β · cos {(ωm - ωo ) t+ 90°} = -α ·sin (ωo - ωr ) t- β · sin (ωm -ωo ) t The shifted signals Sia and Sib are summed up by an adder 16 to give a total signal Si as follows: Si = Sia+Sib = -α ·sin (ωo - ωr ) t+ β · sin (ωm -ωo ) t + {-α ·sin (ωo - ωr ) t- β · sin (ωm -ωo ) t} = -2a ·sin (ωo - ωr ) t where ωo - ωr = 2π(fo-fr) = 2πfi It is thus seen that the signal Si given above is the desired intermediate-frequency signal. It is also obvious from the above equation that signal components caused by the image signal Sm are eliminated from the intermediate-frequency signal Si even if the broadcast-wave signal Sr from the tuning circuit 1 includes the image signal Sm. In this way, the signal Si converted from the broadcast-wave signal Sr (as well as a signal component having an angular frequency of (ωr + ωo) and the like) can be extracted out off the adder 16. The intermediate-frequency signal Si is then supplied to a band-pass filter 17 which serves as an intermediate-frequency filter. As shown in Fig. 7, the band-pass filter 17 is typically a biquad-type active filter that comprises capacitors C11 and C12, resistors R11 to R16 and inverting amplifiers A11 to A13. The band-pass filter 17 has a passing centre frequency f17 of 55 kHz and a passing bandwidth of 6 to 8 kHz. The band-pass filter 17 removes unnecessary signal components, leaving only the intermediate-frequency signal Si. The intermediate-frequency signal Si output by the band-pass filter 17 is then supplied to an AM-wave detecting circuit 22 through an amplifier 21 to give an audio signal Ss (and a direct-current component V22 at a level corresponding to that of the intermediate-frequency signal Si). Subsequently, the audio signal Ss is fed to an audio amplifier 23 having differential inputs before being supplied to the speaker SP through the pin T8 and a capacitor C5. The signal Sib coming from the second mixer 12B is fed to an AGC-voltage forming circuit 18 to produce an AGC voltage which is supplied to the amplifier 11 as a signal controlling the gain thereof. The amplifier 11 thereby carries out automatic gain control on the signals Sia and Sib. It should be noted that the AGC-voltage forming circuit 18 is connected to a capacitor C3 for smoothing the AGC voltage through the pin T5. The AGC voltage is also fed to the operational amplifiers of the first and second shifting circuits 15A and 15B as well as the operational amplifier of the band-pass filter 17 as a reference voltage. The detection output of the AM-wave detecting circuit 22 is supplied to the AGC-voltage forming circuit 24 to produce an AGC voltage which is fed to the amplifiers 11 and 21 as a signal controlling the gains thereof. The amplifiers 11 and 21 thereby perform automatic gain control on the intermediate-frequency signals Sia, Sib and Si. The AGC-voltage forming circuit 24 is connected to a capacitor C4 for smoothing the AGC voltage through the pin T6. The capacitor C4 serves as a low-pass filter for producing a direct-current voltage V22 from the detection output. The AGC voltage is, in fact, generated from the direct-current voltage V22. In addition, the direct-current voltage V22 is also fed to one of the differential inputs of the amplifier 23. In this way the direct-current voltage V22, in effect, neutralizes the direct-current component V22 which is supplied to the other differential input of the amplifier 23 along with the audio signal Ss from the AM-wave detecting circuit 22. The amplifier 23 is also connected to the variable resistor VR through the pin T7. The resistance value of the variable resistor VR is changed to control the gain of the amplifier 23. The variable resistor VR is thus used for adjusting the volume. It should be noted that a capacitor C6 is used for by-passing signal components other than the audio signal Ss. In this IC 10, the intermediate frequency fi is a frequency having a value sufficiently lower than that of the ordinary intermediate frequency and those of frequencies in the reception band. Accordingly, the area occupied by each stage of the band-pass filter (intermediate-frequency filter) 17 is large. However, the number of stages for obtaining a required selectivity characteristic can be reduced. As a result, the total area on the IC 10 occupied by the band-pass filter 17 can be made smaller, justifying the integration of the circuits into an IC chip described above. Reference numeral 30 shown in the figure is a PLL circuit. A local-oscillation signal So obtained from the resonance circuit 2 is supplied to a variable frequency-division circuit 32 through an amplifier 31. The variable frequency-division circuit 32 outputs a signal S32 with a frequency 1/N times that of the local-oscillation signal So. The signal S32 is supplied to one of inputs of a phase comparing circuit 33. An oscillation signal S34 output by an oscillation circuit 34 at a reference frequency of 2 kHz is fed to the other input of the phase comparing circuit 33. A signal output by the phase comparing circuit 33 is supplied to the variable-capacitance diodes VC11 and VC12 through a low-pass filter 35 and buffer resistors R31 and R32 as their control voltages. In a steady state, the frequency of the frequency-division signal S32 is equal to that of the oscillation frequency S34 which has a value of 2 kHz. Accordingly, the oscillation frequency 2fo of the local-oscillation signal So is given by the following equation. 2fo = 2·N [kHz] As above, the oscillation frequency 2fo is expressed by Eq. (2) as follows. 2fo = (fr + fi) x 2 [kHz] From Eqs. (1) and (2), it can be stated that the following relation holds true. (fr + fi) x 2 = 2·N Modifying the above equation results in the following. fr + fi = N Accordingly, ∴ fr = N - fi where the frequencies fr and fi are expressed in terms of kHz. By changing the frequency-division ratio N of the frequency-division circuit 32 in units of unity across the range typically from 586 to 1666, the oscillation frequency 2fo of the local-oscillation signal So changes in 2-kHz units in the range 1172 to 3332 kHz. Accordingly, the reception frequency fr changes in 1kHz-units across the range 531 to 1611 kHz. As an alternative, the frequency-division ratio N can be changed in units of 9 to give a reception frequency fr changing in 9-kHz units. Reference numeral 40 shown in Fig. 6 denotes a microcomputer for controlling the system whereas reference numeral 51 is a variety of operation keys. Reference numeral 52 denotes display devices such as LCDs. A desired reception frequency fr can be specified via the operation keys 51. The specified reception frequency fr is converted by the microcomputer 40 into a frequency-division ratio N which is then set into the frequency-division circuit 32. In this way, a broadcast station having a frequency fr can be selected by manipulating the operation keys 51. At the same time, the microprocessor 40 further forms numerical data (N - fi) from the frequency-division ratio N to represent the reception frequency fr in terms of kHz in accordance with Eq. (3). The numerical data (N - fi) is then converted into character data fo displaying the reception frequency fr. The character data is finally supplied to the LCDs 52 where the reception frequency fr is displays in digital form. As described above, the band-pass filter 17 of the IC 10 is typically configured as a biquad-type active filter as shown in Fig.7 with a centre frequency f17 of 55 kHz. The centre frequency f17 is, by the way, determined by a product of values of the capacitors C11 and C12 and the resistors R11 to R16 which constitute the band-pass filter 17. In general, however, it is impossible to create a capacitor or a resistor in an IC with a high degree of accuracy. That is to say, errors of the order of 5% and 20% occur for a capacitor and a resistor, respectively. In the case of the band-pass filter 17 shown in Fig. 7, the value of the centre frequency f17 thus has an error of the order of 25%, or varies across the range f17-14 to f17+14 kHz. In the case of the IC 10, the centre frequency f17 of the band-pass filter 17 becomes an actual intermediate frequency fi. Accordingly, when the centre frequency f17 of the band-pass filter 17 deviates from a nominal value of 55 kHz due to the errors described above, a discrepancy between the actual reception frequency fr and the displayed frequency value is resulted in. Here, let the local-oscillation frequency fo be 2110 kHz. In the case of a centre frequency f17 of the band-pass filter 17 equal to a normal value of 55 kHz, the reception frequency fr and the frequency-division ratio N are found from Eqs. (1) and (3) to be 1000 kHz and 1055 respectively as shown in the second column of Fig. 4. The microcomputer 40 further subtracts the intermediate frequency fi having a correct value of 55 from the frequency-division ratio N having a value of 1055 in accordance with Eq. (3), with all quantities in the subtraction expressed in terms of kHz, to give a result of 1000. The subtraction result having a value of 1000 is converted into character data which is then supplied to the LCDs 52. A value of 1000 kHz is finally displayed by the LCDs 52 in digital form to represent the reception frequency fr. In the above case, the reception frequency fr and the frequency value displayed on the LCDs 52 match each other with both having a value of 1000 kHz. Therefore, no problems are encountered whatsoever. The third column of Fig. 4, however, shows a case in which the centre frequency f17 of the band-pass filter 17 deviates from the normal value to a value of, say, 50 kHz. In this case, the reception frequency fr and the frequency-division ratio N are found from Eqs. (1) and (3) to be 1005 kHz and 1055 respectively as shown in the third column of Fig. 4. That is to say, the reception frequency fr changes but the frequency-division ratio N does not. The microcomputer 40 further subtracts the intermediate frequency fi having a correct value of 55 from the frequency-division ratio N having a value of 1055 in accordance with Eq. (3) to give a result of 1000 with all quantities in the subtraction expressed in terms of kHz. The subtraction result having a value of 1000 is converted into character data which is then supplied to the LCDs 52. A value of 1000 kHz is finally displayed by the LCDs 52 in digital form to represent the reception frequency fr. In this case, the reception frequency fr thus does not agree with the frequency value displayed on the LCDs 52 with the former having a value of 1005 kHz while the latter having a value of 1000 kHz. As described above, if the centre frequency f17 of the band-pass filter 17 deviates from the normal value, there is a discrepancy between the reception frequency fr and the frequency value displayed on the LCDs 52. To be more specific, if the centre frequency f17 of the band-pass filter 17 deviates from the normal value by Δf, the frequency value displayed on the LCDs 52 is smaller than the reception frequency fr by the frequency deviation Δf, where Δf = Frequency deviation of the centre frequency f17 of the band-pass filter 17 from the normal value Normal value - f17 (where the normal value is 55 kHz) In other words, the reception frequency fr is larger than the frequency value displayed on the LCDs 52 by the frequency deviation Δf. In general, the pass bandwidth of the intermediate-frequency filter (the band-pass filter 17) is 6 to 8 kHz with the frequency of the medium-wave broadcast taken as the centre of the band. In this case, permissible values of the frequency deviation of the tuned frequency (reception frequency fr) are of the order of 1 to 1.5 kHz. As described above, however, the frequency deviation Δf of the centre frequency f17 of the band-pass filter f17 is in the range 0 to a value of the order of 14 kHz in both the negative and positive directions. The frequency deviation Δf appears as it is as a shifted amount of frequency Δf of the reception frequency fr relative to the frequency value displayed on the LCDs 52. Accordingly, the frequency deviation Δf of the reception frequency fr relative to the frequency value displayed on the LCDs 52 exceeds the permissible values of the order of 1 to 1.5 kHz. Selecting a broadcasting station in accordance with a frequency displayed on the LCDs 52 may thus result in an untuned state with a frequency deviation exceeding the permissible limit, giving rise to reproduced sound that is very difficult to hear. In other words, an operation to tune the radio receiver while listening to reproduced sound may result in a displayed frequency value deviating from the reception frequency fr. In the case of an IC 10 with resonance circuits 1 and 2 connected thereto employing variable capacitors VC1 and VC2 as shown in Fig. 5 the reception frequency fr is displayed by means of a dial needle which is interlocked with the variable capacitors VC1 and VC2 as well as a tuning button. Accordingly, the dial needle cannot display the reception frequency fr with a sufficiently high degree of accuracy. Actually, the dial needle is therefore generally used only for roughly adjusting the radio receiver to a reception frequency fr and fine tuning is then performed by listening to the reproduced sound. In this way, no serious problem is encountered even if the displayed frequency value deviates from the reception frequency fr. With the radio receiver adopting the PLL synthesizer technique as shown in Fig. 6, however, the reception frequency fr can be displays with a sufficiently high degree of accuracy. Therefore, a discrepancy between the reception frequency fr and the displayed frequency value is to be regarded as an unacceptable problem which remains to be solved. Assume that the local-oscillation frequency 2fo is 1000 kHz and the centre frequency f17 of the band-pass filter 17 deviates from a normal value of 55 kHz to a value of, say, 50 kHz as shown in the thin column of Fig. 4. In this case, the reception frequency fr and the frequency-division ratio N are found from Eqs. (1) and (3) to be 1005 kHz and 1055 respectively as shown in the third column of Fig. 4. If a value of 50 is subtracted from the frequency-division ratio N having a value of 1055 by the microcomputer 40, however, the result is 1005 which is equal in value to the reception frequency fr which is also 1005. It should be noted that, in general, the centre frequency of the band-pass filter 17 is equal in value to the frequency f17 as shown in the fifth column of Fig. 4. In this case, the reception frequency and the frequency-division ratio are found from Eqs. (1) and (3) to be the frequency value fo - f17 and the value N respectively as also shown in the fifth column of Fig. 4. That is to say, the centre frequency of f17 of the band-pass filter 17 becomes equal in value to the intermediate frequency fi as expressed by the following equation: fi - f17 By expressing the frequencies fr, fo, fi and f17 in terms of kHz, the following is derived from Eq. (3) : fr = N - fi = N - f17 It is obvious from Eq. (4) that subtracting the value f17 expressed in terms of kHz from the frequency-division ratio N gives the value fr. When expressed in terms of kHz, the value fr is equal to the reception frequency fr. Making use of the above relation, the present invention detects the centre frequency f17 of the band-pass filter 17, providing an offset based on the detected centre frequency f17 to the frequency-division ratio N in order to calculate data used for displaying the reception frequency fr. The same reference numerals are used in drawings of embodiments to be described later for denoting components having corresponding functions to those shown in the figures discussed so far. EP-A-0,252,272 discloses a radio receiver in which the intermediate frequency signal for mixing with the receiver signal before passing through the band pass filter, is generated by an oscillator controlled in a phase-locked loop, itself controlled by a microprocessor which is connected to an LCD for displaying the received frequency. EP-A-0,252,272 acknowledges that the band pass filter's intermediate frequency might vary for particular ceramic filters used and further discloses having a test mode in which the actual intermediate frequency is measured by applying a signal of known frequency to the radio receiver's input and taking into consideration the known oscillator frequency. DE-A-2,933,416 discloses a method of correcting for variation in the intermediate frequency of the band-pass filter cf a superheterodyne radio receiver. The correction is made by having a test mode in which the input circuits are switched off and the oscillator frequency signal is supplied across a range of frequencies to determine the point at which the maximum output occurs, which point is used as the intermediate frequency. Effectively the central frequency of the band pass filter is measured and the local oscillator frequency is varied to match. According to the present invention there is provided a superheterodyne receiver using a PLL synthesizer technique, wherein: at least part of a receiver circuit of said superheterodyne receiver is formed in a semiconductor chip; and a band-pass filter circuit serving as an intermediate-frequency filter of said receiver circuit is formed in said semiconductor chip; and characterised in that: a second band-pass filter circuit comprising components equivalent to elements employed in said band-pass filter circuit is formed in said semiconductor chip; and an oscillation circuit employing said second band-pass filter circuit as a feedback path thereof, in use, oscillates at a frequency equal in value to a centre frequency of said intermediate-frequency band-pass filter circuit. The present invention provides, in one embodiment to be described, a single semiconductor chip IC 10 comprising at least a band-pass filter 17 serving as an intermediate-frequency filter, a pseudo band-pass filter 27 comprising components equivalent to those of the band-pass filter 17 and an oscillation circuit 25, wherein the pseudo band-pass filter 27 serves as a feedback path of an oscillation circuit 25 and the oscillation circuit 25 oscillates at a frequency equal in value to the centre frequency of the band-pass filter 17 The IC 10 is further equipped with a PLL variable frequency-division circuit 32 for dividing the local-oscillation frequency of a local-oscillation signal output by a local-oscillation circuit 13, a phase comparing circuit 33 for comparing the phase of the frequency-division output of the PLL variable frequency-division circuit 35 for filtering a comparison result output by the phase comparing circuit 33 and a display element 52 for displaying a reception frequency. A PLL circuit 30 is formed by supplying the output of the low-pass filter 35 to the local-oscillation circuit 13 as a signal for control the local-oscillation frequency thereof. The frequency-division ratio the PLL variable frequency-division circuit 32 is varied in order to control the reception frequency, and the oscillation frequency of the oscillation circuit 25 is monitored. Data representing the reception frequency is derived from the monitored oscillation frequency and the value of the frequency-division ratio of the PLL variable frequency-division circuit 32, and then output to the display element 52 to display the reception frequency. The invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which:- Fig. 1 is a system diagram showing an embodiment implementing a receiver circuit apparatus in accordance with the present invention; Fig. 2 shows an oscillation circuit employed in the embodiment shown in Fig. 1; Fig. 3 shows a simplified oscillation circuit employed in the embodiment shown in Fig. 1; Fig. 4 is a table showing relations between the reception frequency fr and the displayed frequency value; Fig. 5 is a system diagram showing another typical application of the single-chip IC shown in Fig. 5 to a radio receiver; and Fig. 6 is a system diagram showing another typical application of a single-chip IC shown in Fig. 5 to a radio receiver; and Fig. 7 is a connection diagram of a typical portion of the single-chip IC to a radio receiver shown in Fig. 5. As shown in Fig. 1, a band-pass filter 17 serving as an intermediate frequency filter and a pseudo band-pass filter 27 having the same passing characteristic as the band-pass filter 17 are created in an IC 10. The pseudo band-pass filter 27 and a phase-inverting amplifier 26 connected thereto form an oscillation circuit 25. An oscillation signal S25 produced by the oscillation circuit 25 is supplied to a frequency counter 28. The number of cycles of the oscillation signal S25 is counted by the frequency counter 28 periodically for every period of time of 1 msec. A count signal S28 representing the cycle count is supplied to a microcomputer 40 through a pin T9 for use as an offset when computing character data for displaying a reception frequency fr from a frequency-division ratio N. It should be noted that the pseudo band-pass filter 27 is created in the semiconductor IC chip 10 containing other reception circuits using a semiconductor monolithic manufacturing process in the same way and at the same time as the band-pass filter 17. It is needless to say that the phase-inverting amplifier 26 and the frequency counter 28 are also created in the same chip and in the same way as the pseudo band-pass filter 27 and the band-pass filter 17. A typical pseudo band-pass filter 27 and a typical phase-inverting amplifier 26 are shown in Fig. 2. As shown in the figure, the pseudo band-pass filter 27 comprises capacitors C21 and C22, resistors R22 to R26 and inverting amplifiers A21 to A23. Much like the band-pass filter 17 shown in Fig. 7, the pseudo band-pass filter 27 is configured into a biquad-type active filter. The phase-inverting amplifier 26, on the other hand, comprises a differential amplifier 261, an output current mirror circuit 262 and another current mirror circuit 263 which serves as a constant-current supply. The outputs of the amplifiers A21 and A22 employed by the pseudo band-pass filter 27 are supplied to the differential amplifier 261 and the outputs of the differential amplifier 261 and the current mirror circuit 262 are fed to the amplifier A21 so as to form the oscillation circuit 25. The output of the amplifier A22 is obtained as an oscillation signal S25. In this configuration, the pseudo band-pass filter 27 is created at the same time, forming the same configuration as the band-pass filter 17 into the IC 10 as described earlier. Accordingly, the pseudo band-pass filter 27 has a centre frequency equal in value to the centre frequency f17 of the band-pass filter 17. As a result, when the centre frequency f17 of the band-pass filter 17 deviates from the normal value, that of the pseudo band-pass filter 27 also deviates as well. The pseudo band-pass filter 27 and the phase-inverting amplifier 26 connected thereto form the oscillation circuit 25. The oscillation circuit 25 thus oscillates at a frequency equal in value to the centre frequency f17 of the pseudo band-pass filter 27. That is to say, the frequency of the oscillation signal S25 is equal in value to the centre frequency 17 of the band-pass filter 17. The oscillation signal S25 produced by the oscillation circuit 25 is supplied to the frequency counter 28. The number of cycles of the oscillation signal S25 is counted by the frequency counter 28 periodically for every period of time of 1 msec. The count signal S28 thus represents the centre frequency f17 of the signal S25 expressed in terms of kHz and the value f17 expressed in terms of kHz is equal to the value f17 of Eq. (4). The microcomputer 40 then subtracts the value f17 expressed in terms of kHz from the frequency-division ratio N to give a result of N - f17 . Subsequently, the subtraction result N - f17 is converts into character data which is finally supplied to the LCDs 52. In this way, the LCDs 52 display the character data having a value of N- f17 in a digital form to represent the reception frequency. As indicated by Eq. (4), the value N - f17 is not other than a broadcasting reception frequency fr expressed in terms of kHz. Accordingly, the reception frequency fr is always correctly displayed in a digital form on the LCDs 52 even if the centre frequency f17 of the band-pass filter 17 deviates from the normal value. According to the present invention, the centre frequency f17 of the band-pass filter 17 is monitored and the frequency-division ratio N used in the calculation of the displayed frequency value is compensated as described above. Accordingly, no discrepancy is resulted in between the reception frequency fr and the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 deviates from the normal value. As a result, transmission from a desired broadcasting station can be normally received without a tuning error even if the broadcasting station is selected in accordance with a frequency displayed on the LCDs 52. In addition, the value N - f17 displayed to represent the reception frequency fr is always obtained from the values N and f17. Accordingly, it is not necessary to adjust compensation of the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 is shifted during the process of manufacturing the receiver circuit. At the same time, no discrepancy is resulted in between the reception frequency fr and the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 deviates from the normal value due to environmental changes such as variations in temperature. An IC 10 was prototyped and a receiver circuit was built by using the prototype of the IC 10. Experiment results indicate that discrepancies between the reception frequency fr and the displayed frequency value are in the range -500 to +500 Hz, fully satisfying the permissible values of 1 to 1.5 kHz given above. A simplified typical oscillation circuit 25 is shown in Fig. 3. As shown in the figure, a positive-feedback circuit of the differential amplifier 261 comprises capacitors C21 and C22 as well as resistors R21 and R22 to form the oscillation circuit 25. As described earlier, the value N - f17 for use in displaying the reception frequency fr is always obtained from the frequency-division ratio N and the centre frequency f17. At power-on, for example, the value f17 is obtained either at the time a station is selected or periodically based on the signal S28, and stored in a memory unit of the microcomputer 40. Likewise, the reception frequency fr can then be displayed using the stored value f17. Also in this case, it is not necessary to adjust the compensation of the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 deviates from the normal value during the process of manufacturing the receiver circuit. At the same time, no discrepancy is resulted in between the reception frequency fr and the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 deviates from the normal value due to environmental changes such as variations in temperature. As an alternative, the value f17 is obtained from the signal S28 and written into non-volatile memory of the microcomputer 40 during the process of manufacturing the receiver circuit. Likewise, the reception frequency fr can then be displayed using the value f17 stored in the non-volatile memory. In addition, the frequency counter 28 can also be added externally to the IC 10 or even embedded in the microcomputer 40 instead of being integrated in the IC 10. Furthermore, even the PLL circuit 30 can also be embedded in the microcomputer 40 or the IC 10 as well. According to the present invention, the centre frequency f17 of the band-pass filter 17 is detected and the detected centre frequency f17 is used for correcting the frequency-division ratio N. Accordingly, no discrepancy is resulted in between the reception frequency fr and the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 deviates from the normal value. As a result, transmission from a desired broadcasting station can be normally received without a tuning error even if the broadcasting station is selected in accordance with a frequency displayed in the LCDs 52. In addition, the value N - f17 displayed to represent the reception frequency fr is always obtained from the values N and f17. Accordingly, it is not necessary to adjust compensation of the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 is shifted during the process of manufacturing the receiver circuit. At the same time, no discrepancy occurs between the reception frequency fr and the displayed frequency value even if the centre frequency f17 of the band-pass filter 17 deviates from the normal value due to environmental changes such as variations in temperature. An IC 10 was prototyped and a receiver circuit was built by using the prototype of the IC 10. Experiment results indicate that discrepancies between the reception frequency fr and the displayed frequency value are in the range -500 to +500 Hz, fully satisfying the permissible values of 1 to 1.5 kHz given above.

Claims: A superheterodyne receiver using a PLL synthesizer technique, wherein: at least part of a receiver circuit of said superheterodyne receiver is formed in a semiconductor chip (10); and a band-pass filter circuit (17) serving as an intermediate-frequency filter of said receiver circuit is formed in said semiconductor chip (10); and characterised in that: a second band-pass filter circuit (27) comprising components equivalent to elements employed in said band-pass filter circuit (17) is formed in said semiconductor chip (10); and an oscillation circuit (25) employing said second band-pass filter circuit (27) as a feedback path thereof, in use, oscillates at a frequency (f17) equal in value to a centre frequency (fi) of said intermediate-frequency band-pass filter circuit (17). A semiconductor chip (10) incorporating a superheterodyne receiver according to claim 1, wherein the chip further comprises at least a mixer circuit (12) and a local-oscillation circuit (13), said first-mentioned band-pass filter circuit (17) serves as an intermediate-frequency filter, and said second band-pass filter circuit (27) and said oscillation circuit (25) employ said second band-pass filter circuit (27) as a feedback path thereof. A superheterodyne receiver according to claim 1, wherein: at least a mixer circuit (12), a local-oscillation circuit (13) for generating a local-oscillation signal (So), and a wave detecting circuit (1) are further formed in said semiconductor chip; said superheterodyne receiver further comprises a variable frequency-division circuit (32) for dividing a local-oscillation frequency (fo) of said local-oscillation signal (So) output by said local-oscillation circuit (13), a phase-comparing circuit (33) for comparing the phase of a frequency-division output of said variable frequency-division circuit (32) to the phase of a reference signal (S34) output by a reference oscillation circuit (34), a low-pass filter (35) for filtering a comparison result output by said phase-comparing circuit (33), and a display element (52) for displaying a reception frequency (fr); a PLL circuit is formed by supplying an output of said low-pass filter (35) to said local-oscillation circuit (13) as a signal for controlling said local-oscillation frequency (fo) thereof; and a frequency-division ratio (N) of said variable frequency-division circuit (32) is varied in order to control said reception frequency (fr), and characterised in that: said oscillation circuit (25) employing said second band-pass filter circuit (27) as a feedback path thereof is formed in said semiconductor chip; and said superheterodyne receiver further comprises means for monitoring said oscillation frequency (f17) of said oscillation circuit (25) and means for deriving data representing said reception frequency (fr) from said monitored oscillation frequency (f17) and said frequency-division ratio (N) of said variable frequency-division circuit (32) and for outputting said data to said display element (52) in order to display said reception frequency (fr). A superheterodyne receiver according to claim 3, wherein said variable frequency-division circuit (32), said phase comparing circuit (33), and said low-pass filter (35) are formed in said semiconductor chip.

Inventors: OKANOBU TAIWA, OKANOBU, TAIWA, OKANOBU, TAIWA, SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H03J1
IPC codes: H03J1, H03L7, H04B1