Display control apparatus

Abstract: A display control apparatus includes a display data memory for storing display data, a display controller capable of sequentially reading out the display data stored in the memory and transferring the readout display data to the display device at a predetermined period and capable of performing a partial rewrite operation of the display data stored in the memory, a rewrite detector for detecting an address for accessing the display data memory to cause the display controller to perform the partial rewrite operation, and a transfer permitting unit for reading the address detected by the rewrite detector and permitting transfer of only the display data of the read address to the display controller.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a display control apparatus and, more particularly, to a display control apparatus for a display device having a display element which uses, e.g., a ferroelectric liquid crystal as an operating medium for updating a display state and can hold an updated display state upon application or the like of an electric field. Related Background Art A display device used as an information display means for achieving a visual information representing function is used in an information processing system or the like. A CRT display device (to be referred to as a CRT hereinafter) is generally used as such a display device. Various information processing systems such as so-called personal computers are available in accordance with hardware, software, and signal transmission schemes. In this case, CRT display control apparatuses (CRTC) unique to various systems are used. Such CRTCs are exemplified by a VGA81 (available from IBM) as a VGA (Video Graphics Array) dedicated for an information processing system PC-AT (available from IBM) and an 86C911 (available from S3) as an SVGA (Super VGA) obtained such that an accelerator function for displaying predetermined images such as a circle and a rectangle is added to the VGA. Fig. 1 is a block diagram showing an SVGA arrangement used in a CRTC. When the host CPU of an information processing system partially rewrites a display memory window area in a host memory space, the rewritten display data is transferred to a VRAM 3 through a system bus 40 and a SVGA 1. The SVGA 1 generates a VRAM address on the basis of the address of the display memory window area and rewrites the display data in the VRAM 3 which is located at this VRAM address. Meanwhile, the SVGA 1 accesses the VRAM 3 at the same period as the scan period of the CRT and sequentially reads out display data developed in the VRAM 3. The readout data are transferred to a RAMDAC 2. The RAMDAC 2 sequentially converts the input display data into R, G, and B analog signals and transfers the converted analog signals to a CRT 4. The SVGA used as the CRT display control apparatus functions to unconditionally transfer the display data at a predetermined period to the CRT. In the above CRT display control, since the VRAM 3 comprises a dual port RAM, the VRAM 3 can independently perform an operation of writing display data in the VRAM to update the display information and an operation of reading out the display data from the VRAM. For this reason, the host CPU need not consider display timings and the like at all. Desired display data can be advantageously written at an arbitrary timing. A CRT requires particularly a length in the direction of thickness of the display screen and has a large volume. It is difficult to obtain a compact CRT as a display device as a whole. This limits the degree of freedom of an information processing system using a CRT as a display. That is, the degrees of freedom in installation locations and portability are decreased. A liquid crystal display (to be referred to as an LCD hereinafter) can be used as a display device which can compensate for the above drawbacks. More specifically, an LCD can achieve compactness (particularly, a low-profile configuration) of the display device as a whole. Of such LCDs, a display using a liquid crystal cell containing a ferroelectric liquid crystal (to be referred to as an FLC) is available. This display will be referred to as an FLCD hereinafter. One of the characteristic features of the FLCD lies in that the display state of the liquid crystal cell is preserved upon application of an electric field. That is, its liquid crystal cell is sufficiently thin, the elongated FLC molecules in the cell are aligned in the first or second stable state in accordance with an electric field application direction, and the aligned state of the molecules is maintained after the electric field is withdrawn. The FLCD has a memory function due to the above bistable operations of the FLC molecules. The details of the FLC and FLCD are described in U.S.P. No. 4,964,699. Although the FLCD has the above memory function, it has a low FLC display updating speed. The FLCD cannot follow up with changes in display information which must be instantaneously updated. Such operations are exemplified by cursor movement, a character input, and scrolling. In FLCDs having the above characteristics, various display drive modes which have originated from these characteristics or compensate for these characteristics are available. More specifically, in refresh driving for sequentially and continuously driving scan lines on the display screen as in a CRT and any other liquid crystal display, a relatively large time margin is available in its drive period. In addition to this refresh driving, partial rewrite driving for updating the display state of a part (line) subjected to a change on the display screen and interlace driving for interlacing and driving scan lines on the display screen are also proposed. The display information change speed can be increased by the partial rewrite driving or the interlace driving. If display control of the FLCD having the above advantages can be performed using an existing CRT display controller, an information processing system using an FLCD as a display device can be arranged at a relatively low cost. Documents EP-A-0 361 471 and EP-A-0 368 117 disclose display control apparatuses for an FLCD display device, comprising display data memory means for storing display data and an FLCD display controller. According to the EP-A-0 361 471, the display controller itself performs partial rewriting with a priority control function. To achieve this, the display controller is adapted to check the display priority level of a partial rewrite demand and to permit partial rewrite demands of higher priority levels, while partial rewrite operations of lower priority levels are interrupted. Thus, the permission of display data transfer is performed in dependence on the priority level of the partial rewrite demand. It is an object of the present invention to provide a display control apparatus and method having a partial rewrite function at low cost. This object is achieved by a display control apparatus and method as claimed in claims 1 and 8, respectively. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a conventional display control apparatus; Fig. 2 is a block diagram showing an information processing system according to the first embodiment of the present invention; Fig. 3 is comprised of Figs. 3A and 3B illustrating block diagrams showing a display control apparatus according to the first embodiment of the present invention; Fig. 4 is a block diagram showing the detailed arrangement of an SVGA shown in Fig. 3A and Fig. 3B; Fig. 5 is a view for explaining conversion from a VRAM address into a line address according to the first embodiment of the present invention; Fig. 6 is a view illustrating a relationship between a rewrite display pixel and a rewrite line flag register according to the first embodiment of the present invention; Fig. 7 is a view illustrating an FLCD display screen according to the first embodiment of the present invention; Figs. 8A and 8B are views illustrating data formats of display data according to the first embodiment of the present invention; Fig. 9 is a block diagram showing a process flow of display data according to the first embodiment of the present invention; Fig. 10 is a flow chart showing the process flow of the display control apparatus according to the first embodiment of the present invention; Fig. 11 is a timing chart showing the process of the display control apparatus according to the first embodiment of the present invention; Fig. 12 is comprised of Figs. 12A and 12B illustrating block diagrams showing a display control apparatus according to the second embodiment of the present invention; Fig. 13 is a block diagram showing the detailed arrangement of an SVGA shown in Fig. 12A and Fig. 12B; Fig. 14 is a flow chart showing the process flow of the display control apparatus according to the second embodiment; Fig. 15 is comprised of Figs. 15A and 15B illustrating block diagrams showing a display control apparatus according to the third embodiment of the present invention; Fig. 16 is a block diagram showing the detailed arrangement of an SVGA shown in Fig. 15A and Fig. 15B; Fig. 17 is a flow chart showing the process flow of the display control apparatus according to the third embodiment; Fig. 18 is a flow chart showing the process flow of a display control apparatus according to the fourth embodiment of the present invention; Fig. 19 is a view illustrating an FLCD display screen used to explain the format of line address data according to the fifth embodiment of the present invention; Figs. 20A and 20B are views showing two data formats, respectively; Figs. 21A and 21B are views for explaining other two data formats; Figs. 22A and 22B are views for explaining line address transfer of this embodiment and the conventional line address transfer; Fig. 23 is comprised of Figs. 23A and 23B illustrating block diagrams showing a display control apparatus according to the sixth embodiment of the present invention; Fig. 24 is a block diagram showing the detailed arrangement of an SVGA shown in Fig. 23A and Fig. 23B; Fig. 25 is a view illustrating a refresh mode table shown in Fig. 23; Fig. 26 is a block diagram showing the interlace line address generator according to the sixth embodiment of the present invention; Fig. 27 is a block diagram showing the detailed arrangement of a timing generator shown in Fig. 26; Fig. 28 is a view for explaining a decoding relationship of a decoder shown in Fig. 27; Fig. 29 is a waveform chart showing count-up enable time generated by the timing generator; Fig. 30 is a flow chart showing the sequence flow of an interlace line address generator shown in Fig. 26; Fig. 31 is a block diagram showing another arrangement of the interlace line address generator; and Fig. 32 is a timing chart showing operations in the generator shown in Fig. 31. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Fig. 2 is a block diagram of an information processing system in which an FLC display device having a display control apparatus according to an embodiment of the present invention is used as a display device for displaying various characters and image information. Referring to Fig. 2, the information processing system includes a CPU 21, a ROM 22, a main memory 28, a DMA controller (Direct Memory Access Controller; to be referred to as a DMAC hereinafter) 23, a LAN (Local Area Network) interface 32, a hard disk device & I/F 26, a LAN 37, a floppy disk device & I/F 27, a printer 36, a parallel I/F 31, a keyboard & controller 29, a communication modem 33, a mouse 34, an image scanner 35, a serial I/F 30, an interrupt controller 24, a real time clock 25, an FLC display device (to be also referred to an FLCD hereinafter) 20, an FLCD interface 10, a system bus 40. The CPU 21 controls the overall information processing system. The ROM 22 stores programs executed by the CPU 21. The main memory 28 is used as a work area or the like in execution of programs. The DMAC 23 transfers data between the main memory 28 and the respective components constituting this system without control of the CPU 21. The LAN I/F 32 serves as an interface between the LAN 37 such as Ethernet (available from XEROX) and this system. The printer 36 can be constituted by an ink-jet or laser beam printer capable of performing recording at a relatively high resolution. The parallel I/F 31 connects signals between the printer and this system. The keyboard & controller 29 inputs information such as character information (e.g., various characters) and control information. The communication modem 33 performs signal modulation between the communication line and this system. The mouse 34 serves as a pointing device. The image scanner 35 reads an image or the like. The communication modem 33, the mouse 34, and the image scanner 35 exchange signals with this system through the serial I/F 30. The interrupt controller 24 controls an interrupt operation in execution of a program. The real time clock 25 controls a timepiece function in this system. The display operation of the FLCD 20 is controlled by the FLCD interface 10 serving as the display control apparatus of this embodiment. The FLCD 20 has a display screen using the ferroelectric liquid crystal as a display operating medium. A display memory window area which can be accessed by the CPU 21 is also developed in the FLCD I/F 10. The system bus 40 comprises a data bus, a control bus, and an address bus to connect signals between the respective components. In the information processing system in which the above components are connected, a user generally performs operations in correspondence with various kinds of information displayed on the display screen of the FLCD 20. More specifically, character information and image information which are supplied from an external device connected to the LAN 37, the hard disk device & I/F 26, the floppy disk device & I/F 27, the scanner 35, the keyboard & controller 29, and the mouse 34, and operation information stored in the main memory 28 upon operations of the user for the system are displayed on the display screen of the FLCD 20. The user performs information editing and operations for instructing the system while observing the display contents on the FLCD 20. The above components constitute a display information supply means for the FLCD 20. First Embodiment Figs. 3A and 3B are block diagrams showing the detailed arrangement of the FLCD I/F 10 according to the first embodiment of the present invention. Referring to Figs. 3A and 3B, an SVGA 1 using the exiting SVGA serving as a CRT display controller is used in the FLCD I/F 10, i.e., the display control apparatus. The arrangement of the SVGA 1 will be described with reference to Fig. 4. Referring to Fig. 4, rewrite display data accessed by the host CPU 21 (Fig. 2) to perform a rewrite operation in the display memory window area of the FLCD I/F 10 (Fig. 2) is transferred through the system bus 40 and temporarily stored in a FIFO 101. Bank address data for mapping the display memory window area on an arbitrary area of a VRAM 3 is also transferred through the system bus 40. Display data has a form of 24 bits for expressing 256 gradation levels for each of the R, G, and B components. Control information such as a command and the bank address data from the CPU 21 is transferred in the form of register set data. Register get data for allowing the CPU 21 to detect the state on the SVGA side is transferred to the CPU 21. The register set data and the display data which are stored in the FIFO 101 are sequentially input, so that the registers in a bus I/F unit 103 and a VGA 111 are set in accordance with the output data. The VGA can know a bank address, its display data, and a control command in accordance with the set states of these registers. The VGA 111 generates a VRAM address for the VRAM 3 on the basis of the address of the display memory window area and the bank address. At the same time, the VGA 111 transfers strobe signals RAS and CAS, a chip select signal CS, and a write enable signal WE, all of which serve as memory control signals, to the VRAM 3 through a memory I/F unit 109, thereby writing the display data at the VRAM address. At this time, the display data to be rewritten is transferred to the VRAM 3 through the memory I/F unit 109. On the other hand, in response to a line data transfer enable signal transferred from a line address generator 7 (Figs. 3A and 3B), the VGA 111 reads out the display data from the VRAM 3 which is specified by a request line address transferred from the line address generator 7. The VGA 111 then stores the readout data in a FIFO 113. The display data is sent from the FIFO 113 to the FLCD side in the display data storage order. The SVGA 1 comprises a data manipulator 105 and a graphics engine 107, both of which provide the accelerator function as previously described, in addition to the cursor display circuit. For example, when the CPU 21 sets data associated with a circle, its center, and its radius in the registers of the bus I/F unit 103 to instruct drawing of the circle, the graphics engine 107 generates circle display data, and the data manipulator 105 writes the resultant data in the VRAM 3. The SVGA 1 described with reference to Fig. 4 can be obtained by slightly modifying the VGA portion of the existing CRT SVGA. Referring back to Figs. 3A and 3B, a rewrite detector/flag generator 5 monitors a VRAM address generated by the SVGA 1 and fetches a VRAM address upon rewriting (writing) of the display data of the VRAM 3, i.e., a VRAM address obtained when the write enable signal and the chip select signal CS go to level "1". The rewrite detector/flag generator 5 calculates a line address on the basis of this VRAM address and data (i.e., a VRAM address offset, the total number of lines, and the total number of line bits) obtained from a CPU 9. The concept of this computation is shown in Fig. 5. As shown in Fig. 5, a pixel represented by an address X in the VRAM 3 corresponds to a line N on the FLCD screen. One line comprises a plurality of pixels, and each pixel is constituted by a plurality (n) of bytes. At this time, the line address (line number N) is computed as follows. Line No. N = (VRAM Adress X) - (Image Data Start Address) (Number of Pixels per Line) x (Number of Bytes per Pixel) + 1 The rewrite detector/flag circuit 5 sets its internal partial rewrite line flag register in accordance with the computed line address. This state is shown in Fig. 6. As is apparent from Fig. 6, when the address display corresponding to a letter, e.g., "L" in the VRAM 3 is rewritten to display the letter "L", the line address rewritten by the above computation is detected, and a flag is set ("1") in a register corresponding to this address. The CPU 9 reads the contents of the rewrite line flag register in the rewrite detector/flag generator 5 and sends the line address, the flag of which is set, to the SVGA 1. At this time, the line address generator 7 sends out a line data transfer enable signal corresponding to the line address data and transfers the display data at the above address from the SVGA 1 (of the FIFO 113) to a halftone processor 11. The halftone processor 11 converts multi-value (256 gradation levels) data expressed by 8-bit R, G, and B data into binary pixel data corresponding to each pixel on the display screen of the FLCD 20. As shown in Fig. 7, one pixel on the display screen has display cells having different areas for the respective colors, and data corresponding to one pixel has two bits for each color (R1, R2, G1, G2, B1, and B2). Therefore, the halftone processor 11 converts 8-bit display data into binary data having two bits for each color (i.e., four-value data for each color). The schematic data flow until data is converted into FLCD display pixel data as described above is shown in Fig. 9. As is apparent from Fig. 9, display data in the VRAM 3 are stored as 8-bit multi-value data for each of the R, G, and B components. When these data are to be read out and displayed, they are binarized. The host CPU 21 (Fig. 2) can access the FLCD 20 in the same manner as in use of the CRT, thereby assuring compatibility with the CRT. A technique used in halftone processing can be a known technique such as an error diffusion method, a mean density method, or a dither method. Referring to Figs. 3A and 3B, a boarder generator 13 generates pixel data of a border portion on the display screen of the FLCD. More specifically, as shown in Fig. 7, the display screen of the FLCD 20 has 1,024 lines each consisting of 1,280 pixels. The boarder portion of the display screen which does not contribute to display is formed to surround the remaining display screen portion. The format of pixel data transferred to the FLCD 20 is defined as the one shown in Fig. 8A or 8B due to the presence of this boarder portion. Fig. 8A is the data format of a display line A (Fig. 7), i.e., all display lines included in the boarder portion. Fig. 8B is the data format of a display line B (Fig. 7), i.e., lines used for display. The data format of the display line A starts with a top line address, and boarder pixel data follows the top line address. To the contrary, since two end portions of the display line B are included in the boarder portion, its data format starts with a line address, and boarder pixel data, pixel data, and boarder pixel data follow the line address in the order named. The boarder pixel data generated by the boarder generator 13 is serially synthesized with pixel data from the halftone processor 11 in a synthesizing circuit 15. The synthesized data is further synthesized with the display line address from the line address generator 7 by a synthesizing circuit 17. The resultant data is sent to the FLCD 20. The CPU 9 performs the overall operations described above. More specifically, the CPU 9 receives various kinds of information, i.e., the total number of lines of the display screen, the total number of line bits, and the cursor information from the host CPU 21 (Fig. 2). The CPU 9 sends out various data, i.e., the VRAM address offset, the total number of lines, and the total number of line bits to the rewrite detector/flag generator 5 and initializes the line flag register. The CPU 9 also sends out the display start line address, the continuous number of display lines, the total number of lines, the total number of line bits, and boarder area information to the line address generator 7 and receives partial rewrite line flag information from the line address generator 7. The CPU 9 further sends out data, i.e., a band width, the total number of line bits, and a process mode to the halftone processor 11 and the boarder pattern data to the boarder generator 13. The CPU 9 receives status signals (e.g., temperature information and a Busy signal) from the FLCD 20 and sends out a command signal and a reset signal to the FLCD 20. Partial rewrite display control of the FLCD I/F 10 described with reference to Figs. 3A and 3B will be described below. Fig. 10 is a flow chart showing the flow of a partial rewrite process, and Fig. 11 is a timing chart of the respective signals and data. Partial rewrite display control will be described with reference to Figs. 10 and 11. When the host CPU 21 writes display data in the VRAM 3 (step S101 in Fig. 19; only the step numbers are designated hereinafter), or the host CPU 21 sends a drawing instruction to the accelerator of the SVGA 1 (step S121) to cause the accelerator to write the display data in the VRAM 3 (step S122), a write enable signal WE and a chip select signal CS which are generated by the SVGA 1 are set at "1". The write detector/flag generator 5 detects this (time 1 ○ in Fig. 11; only the time is represented hereinafter) to get the rewritten VRAM address. In step S103, a rewrite line address is computed on the basis of this rewrite VRAM address (time 2 ○ ). In step S104, the rewrite line flag is set (time 3 ○ ). The SVGA 1 outputs a signal V-sync to the rewrite detector/flag generator 5 at a predetermined period (time 4 ○ ), and the rewrite detector/flag generator 5 outputs rewrite line flag information. In step S105, the CPU 9 writes the rewrite line flag information through the line address generator 7 (time 5 ○ ). As is apparent from Fig. 11, the flag set prior to generation of the signal V-sync is read by this signal V-sync. The CPU 9 selects a display line corresponding to the priority of the cursor information or the like on the basis of the rewrite line flag information sent through the line address generator 7 (step S106). A display start line address and the continuous number of display lines which correspond to this display line are designated to the line address generator 7 (step S107). In response to this, in step S108, the line address generator 7 sends the rewrite line address to the SVGA 1 (time 6 ○ ) and also sends a line data transfer enable signal (time 7 ○ ), thereby requesting display data transfer. In response to this request, in step S109, the rewrite detector/flag generator which has received the line data transfer enable signal clears a rewrite line flag corresponding to the requested line address (time 9 ○ ), and the SVGA 1 reads out the display data at the requested line address from the VRAM 3. The readout display data is sent to the halftone processor 11 (time 8 ○ ). In step S111, the halftone processor 11 converts the transferred display data into pixel data (time ). In step S112, boarder pixel data is added to this pixel data. In addition, in step S113, line address data is added to the resultant data (time ). The FLCD 20 displays information on the basis of this rewrite line data (step S114). As described above, only when the host CPU accesses the VRAM to perform a display rewrite operation, the FLCD I/F serving as the display controller of this embodiment transfers the rewrite line address and the line data transfer enable signal to the SVGA, and the display data can be sent to the FLCD, thereby performing the partial rewrite operation. The arrangement for causing the SVGA to access to the VRAM to read out and transfer the display data only when the line data transfer enable signal is transferred can be obtained by slightly modifying the SVGA as follows. More specifically, the SVGA 1 has a function of reading out the display data from the VRAM in synchronism with the scan period of the CRT so as to perform CRT display. This function can be performed by an address counter arranged in the SVGA. In this embodiment, the SVGA is modified such that this address counter performs a count-up operation only when the line data transfer enable signal is set at "1". In the above arrangement using the line data transfer enable signal and the address counter, display control such as refresh control and interface control is performed as follows. The CPU 9 sets a refresh mode when a predetermined number of read rewrite flags are continuously set. For example, the first line of the FLCD display screen is defined as a display start line address, and the continuous number of display lines is defined as the total number of lines (1,024 lines). Therefore, the line address generator 7 transfers the line data transfer enable signal at the same period as the VRAM read period unique to the SVGA 1. In an interlace display mode, the number of lines to be interlaced is determined in accordance with temperature information from the FLCD 20 or trimmer information desired by a user. However, when the CPU 9 appropriately sets the above display start line address and the continuous number of display lines to perform interlace display. The above refresh display can be performed at a predetermined period except that the host CPU accesses the VRAM to perform a rewrite operation. According to this, a slight shift in alignment of the liquid crystal molecules, which is caused by an electric field generated by a common electrode of the FLCD display panel, can be corrected, and a good display state can be maintained. Second Embodiment Figs. 12A and 12B are block diagrams showing the arrangement of an FLCD I/F according to the second embodiment of the present invention. Fig. 13 is a block diagram showing the detailed arrangement of an SVGA 1A shown in Figs. 12A and 12B. The same reference numerals as in the first embodiment shown in Figs. 3A, 3B and 4 denote the same parts in the arrangements shown in Figs. 12A, 12B and 13, and a detailed description thereof will be omitted. The second embodiment is different from the first embodiment in that a rewrite detector/line address generator 115 is arranged in the SVGA 1A, and that a flag generator 5A sets a rewrite line flag of a flag register in accordance with a rewrite line address generated by the rewrite detector/line address generator 115 (step S202 in Fig. 14). With the above arrangement, the number of signal lines for connecting the SVGA 1A and the flag generator 5A can be reduced by the number of control signal lines as compared with the first embodiment. Third Embodiment Figs. 15A and 15B are block diagrams showing the arrangement of an FLCD I/F according to the third embodiment of the present invention, and Fig. 16 is a block diagram showing the detailed arrangement of an SVGA 1B shown in Figs. 15A and 15B. The same reference numerals as in the first embodiment shown in Figs. 3A, 3B and 4 denote the same parts in the arrangements shown in Figs. 15A, 15B and 16, and a detailed description thereof will be omitted. The third embodiment is different from the first embodiment in that a rewrite detector/flag generator 117 and a rewrite line flag register 119 are arranged in the SVGA 1B. In step S302 in Fig. 17, the SVGA 1B itself finally sets the rewrite line flag, and a CPU 9 can get rewrite line flag information from the SVGA 1B through a line address generator 9. With the above arrangement, a signal output from the SVGA 1B to the FLCD side is only rewrite line flag information, and the number of signal lines can be further reduced as compared with the second embodiment. Fourth Embodiment In each embodiment described above, a host CPU monitors an address for accessing a VRAM to perform a display rewrite operation. A rewrite portion is specified on the basis of this address, and only the specific portion is rewritten. The operating temperature of the FLCD display element is changed with a change in ambient temperature. In the arrangement of Figs. 3A and 3B, for example, the speed of the FLCD 20 which receives pixel data and the like and displays information on the basis of the pixel data is changed in accordance with a change in temperature. For this reason, in this embodiment, for example, in Figs. 3A and 3B, the FLCD 20 generates a Busy signal as a status signal, and the CPU 9 monitors the period of this Busy signal. The transfer period of the pixel data is determined in accordance with this monitor period. Note that the temperature information may be directly received to change the transfer period on the basis of the temperature information in place of the Busy signal. Fig. 18 is a flow chart showing the above process. The period of a Busy signal is received in step S401. It is determined in step S402 whether this period is shorter or longer than a predetermined period. If the received period is longer than the predetermined period, a period M is set in an interval register arranged in, e.g., a line address generator in step S403. However, if the received period is shorter than the predetermined period, a shorter period N is set in step S404. In step S405, display data is transferred from the SVGA 1 at the period M or N. In this case, when the display data is to be transferred at the period M or N, the display data at line addresses corresponding to the flags set in a rewrite flag register during this period must be transferred in accordance with a preferential order. That is, the address generator sends the line address at which a rewrite flag is set, and its data transfer enable signal. According to this embodiment, the total time required to cause the SVGA to read out the display data from the VRAM and to transfer the readout image data to the FLCD side can be reduced with respect to tile total process time of the SVGA. When the FLCD side is to receive display data or the like, the time for waiting for transferring the display data during the period of the Busy signal can be shortened. The SVGA can use process time for writing data in the VRAM and exchanging data with the host CPU. In addition, since the waiting time can be shortened, the line buffer can be reduced. As can be apparent from the above description, according to the present invention, when the display controller rewrites display data, the address of this display data is detected, and only the display data at the detected address is read out and transferred to the display device by the display controller. Even if a display controller such as a VGA or SVGA which has a function of reading out and transferring display data at, e.g., the predetermined CRT period is used, a partial rewrite operation in the display device constituted by a ferroelectric liquid crystal can be properly performed. Fifth Embodiment In this embodiment, a request line address is sent from a line address generator 7 (see Figs. 3A and 3B) to an SVGA 1 in units of of blocks. The output of this request line address will be described below. Fig. 19 is a view illustrating the display screen of an FLCD 20. The six upper lines on the display screen are not rewritten, eight lines from the seventh line can be rewritten, and the subsequent lines are not rewritten. In this case, Fig. 20A shows a data format of a request line address transferred from the line address generator 7 to the SVGA 1. As shown in Fig. 20A, this data has start bits representing the start of data. A predetermined number a of bits of the start bits are set at "0"s, and the subsequent predetermined number b of bits are set at "1"s. After the start bits, six bits corresponding to the six lines which are not rewritten are set at "0"s, and eight bits corresponding to the eight lines which can be rewritten are set at "1"s. The subsequent n bits which cannot be rewritten are set at "0"s. Fig. 20B is a view showing another data format of the request line address shown in Fig. 20A. In this format, after the start bits, codes corresponding to a predetermined number of lines are sent in accordance with a communication scheme. That is, a code corresponding to the six lines which are not rewritten is sent, a code corresponding to eight rewrite lines is sent, and a code corresponding to n lines which are not rewritten is then sent. More specifically, in this format, the code sent first after the start bits represents the number of lines which are not rewritten, and the number represented by the next code represents the number of lines which are rewritten. Therefore, if a rewrite operation is started from the first line of the FLCD screen, the first code represents zero. Figs. 21A and 21B are formats each having two portions which are to be rewritten on the FLCD screen. Referring to Fig. 21A, the number of bits of logic "0" represents the number of lines which are not rewritten, and the number of bits of logic "1" represents the number of lines which are rewritten, as in Fig. 20A. The data format shown in Fig. 21B is similar to that of Fig. 20B. However, the number represented by the first code next to the start bits represents the number of portions which are rewritten, i.e., the number of blocks of rewrite lines. In this embodiment, since two blocks are to be rewritten, a code representing 2 is sent. A code sent next to this code represents the number of lines which are not rewritten on the FLCD screen, and number of "8" represented by the next code represents the number of lines which are rewritten, as in Fig. 20B. Similarly, the next code of "12" represents the number of lines which are not rewritten, and the next code of "10" represents the number of lines which are rewritten. According to the request line address data formats described above, the following effects can be obtained as compared with a conventional data format. Fig. 22A and 22B are views for explaining the address request of this embodiment, a conventional address request, and corresponding data transfer states. In the conventional request shown in Fig. 22B, address data is sent every line to obtain display data of a given rewrite block, and the display data is obtained on the basis of the address data. According to this scheme, an SVGA which has received the address data accesses the VRAM every line to read out the display data. The readout display data is transferred to the FLCD side. A total time from address data generation to display data transfer of all the rewrite lines is relatively prolonged. To the contrary, according to the data format of this embodiment, as shown in Fig. 22A, all rewrite line address data are sent in units of blocks, and read access and transfer of the display data by the SVGA can be continuously performed in units of blocks. For this reason, as compared with the conventional scheme, a total time from address data generation to display data transfer can be shortened. As can be apparent from the above description, according to the present invention, when the display controller is permitted to read and transfer display data, the addresses of a plurality of display data in read access can be sent in units of blocks. As a result, the total time for accessing the display data memory means to read out the display data and transferring the readout data to the display device side can be shortened, thereby providing a display control apparatus having a high process speed. Sixth Embodiment Figs. 23A and 23B are block diagrams showing the detailed arrangement of an FLCD I/F 10 according to the sixth embodiment of the present invention; Referring to Figs. 23A and 23B, an SVGA 1 using the exiting SVGA serving as a CRT display controller is used in the FLCD I/F 10, i.e., the display control apparatus. The arrangement of the SVGA 1 will be described with reference to Fig. 24. Referring to Fig. 24, rewrite display data accessed by the host CPU 21 (Fig. 2) to perform a rewrite operation in the display memory window area of the FLCD I/F 10 (Fig. 2) is transferred through the system bus 40 and temporarily stored in a FIFO 101. Bank address data for mapping the display memory window area on an arbitrary area of a VRAM 3 is also transferred through the system bus 40. Display data has a form of 24 bits for expressing 256 gradation levels for each of the R, G, and B components. Control information such as a command and the bank address data from the CPU 21 is transferred in the form of register set data. Register get data for allowing the CPU 21 to detect the state on the SVGA side is transferred to the CPU 21. The register set data and the display data which are stored in the FIFO 101 are sequentially input, so that the registers in a bus I/F unit 103 and a VGA 111 are set in accordance with the output data. The VGA can know a bank address, its display data, and a control command in accordance with the set states of these registers. The VGA 111 generates a VRAM address for the VRAM 3 on the basis of the address of the display memory window area and the bank address. At the same time, the VGA 111 transfers strobe signals RAS and CAS, a chip select signal CS, and a write enable signal WE, all of which serve as memory control signals, to the VRAM 3 through a memory I/F unit 109, thereby writing the display data at a position designated by the VRAM address. At this time, the display data to be rewritten is transferred to the VRAM 3 through the memory I/F unit 109. On the other hand, in response to a line data transfer enable signal transferred from a line address generator 7 (Figs. 23A and 23B), the VGA 111 reads out the display data from the VRAM 3 which is specified by a request line address transferred from the line address generator 7. The VGA 111 then stores the readout data in a FIFO 113. The display data is sent from the FIFO 113 to the FLCD side in the display data storage order. The SVGA 1 comprises a data manipulator 105 and a graphics engine 107, both of which provide the accelerator function as previously described, in addition to the cursor display circuit. For example, when the CPU 21 sets data associated with a circle, its center, and its radius in the registers of the bus I/F unit 103 to instruct drawing of the circle, the graphics engine 107 generates circle display data, and the data manipulator 105 writes the resultant data in the VRAM 3. A rewrite detector/flag generator 117 monitors a VRAM address generated by the SVGA 111 and fetches a VRAM address upon rewriting (writing) of the display data of the VRAM 3, i.e., a VRAM address obtained when the write enable signal and the chip select signal CS go to level "1". The rewrite detector/flag generator 5 calculates a line address on the basis of this VRAM address and data (i.e., a VRAM address offset, the total number of lines, and the total number of line bits) obtained from a CPU 9. The concept of this computation is shown in Fig. 5. A circuit (to be described later) for generating an interlace line address corresponding to an interlace value from the CPU 9 is arranged in part of the rewrite detector/flag generator 117. As shown in Fig. 5, a pixel represented by an address X in the VRAM 3 corresponds to a line N on the FLCD screen. One line comprises a plurality of pixels, and each pixel is constituted by a plurality (n) of bytes. At this time, the line address' (line number N) is computed as follows. Line No. N = (VRAM Address X) - (Image Data Start Address) (Number of Pixels per Line) x (Number of Bytes per Pixel) + 1 The rewrite detector/flag generator 117 sets the flag of its internal partial rewrite line flag register 119 in accordance with the computed line address. This state is shown in Fig. 6. As is apparent from Fig. 6, when the address display corresponding to a letter, e.g., "L" in the VRAM 3 is rewritten to display the letter "L", the line address rewritten by the above computation is detected, and a flag is set ("1") in a register corresponding to this address. Referring back to Figs. 23A and 23B, the CPU 9 reads the contents of the rewrite line flag register in the rewrite detector/flag generator 117 and sends the line address, the flag of which is set, to the SVGA 111. At this time, the line address generator 117 sends out a line data transfer enable signal corresponding to the line address data and transfers the display data at the above address from the SVGA 111 (of the FIFO 113) to a halftone processor 11. The halftone processor 11 converts multi-value (256 gradation levels) data expressed by 8-bit R, G, and B data into binary pixel data corresponding to each pixel on the display screen of the FLCD 20. As shown in Fig. 7, one pixel on the display screen has display cells having different areas for the respective colors, and data corresponding to one pixel has two bits for each color (R1, R2, G1, G2, B1, and B2). Therefore, the halftone processor 11 converts 8-bit display data into binary data having two bits for each color (i.e., four-value data for each color). The schematic data flow until data is converted into FLCD display pixel data as described above is shown in Fig. 9. As is apparent from Fig. 9, display data in the VRAM 3 are stored as 8-bit multi-value data for each of the R, G, and B components. When these data are to be read out and displayed, they are binarized. The host CPU 21 (Fig. 2) can access the FLCD 20 in the same manner as in use of the CRT, thereby assuring compatibility with the CRT. A technique used in halftone processing can be a known technique such as an error diffusion method, a mean density method, or a dither method. Referring to Figs. 23A and 23B, a boarder generator 13 generates pixel data of a boarder portion on the display screen of the FLCD. More specifically, as shown in Fig. 7, the display screen of the FLCD 20 has 1,024 lines each consisting of 1,280 pixels. The boarder portion of the display screen which does not contribute to display is formed to surround the remaining display screen portion. The format of pixel data transferred to the FLCD 20 is defined as the one shown in Fig. 8A or 8B due to the presence of this boarder portion. Fig. 8A is the data format of a display line A (Fig. 7), i.e., all display lines included in the boarder portion. Fig. 8B is the data format of a display line B (Fig. 7), i.e., lines used for display. The data format of the display line A starts with a top line address, and boarder pixel data follows the top line address. To the contrary, since two end portions of the display line B are included in the boarder portion, its data format starts with a line address, and boarder pixel data, pixel data, and boarder pixel data follow the line address in the order named. The boarder pixel data generated by the boarder generator 13 is serially synthesized with pixel data from the halftone processor 11 in a synthesizing circuit 15. The synthesized data is further synthesized with the display line address from the line address generator 7 by a synthesizing circuit 17. The resultant data is sent to the FLCD 20. The CPU 9 performs the overall operations described above. More specifically, the CPU 9 receives various kinds of information, i.e., the total number of lines of the display screen, the total number of line bits, and the cursor information from the host CPU 21 (Fig. 2). The CPU 9 sends out various data, i.e., the VRAM address offset, the total number of lines, and the total number of line bits to the rewrite detector/flag generator 117 and initializes the line flag register. The CPU 9 also sends out the display start line address, the continuous number of display lines, the total number of lines, the total number of line bits, and boarder area information to the line address generator 7 and receives partial rewrite line flag information from the line address generator 7. The CPU 9 further sends out data, i.e., a band width, the total number of line bits, and a process mode to the halftone processor 11 and the boarder pattern data to the boarder generator 13. The CPU 9 receives status signals (e.g., temperature information, trimmer information, and a Busy signal) from the FLCD 20 and sends out a command signal and a reset signal to the FLCD 20. In addition, interlace refresh display control (to be described later) is performed with reference to a refresh mode table 9A. Interlace refresh display control by the FLCD I/F 10 described with reference to Figs. 23A, 23B and 24 will be described below. Fig. 25 is a view illustrating the refresh mode table shown in Figs. 23A and 23B. The refresh display is started when a partial rewrite operation is not performed within a predetermined period of time. A ratio of partial rewriting to refreshing shown in Fig. 25 is determined in accordance with the above interlace value. In the table, the interlace value, i.e., the number of lines to be interlaced, is obtained with reference to the temperature information and the trimmer information from the FLCD 20. In general, when the temperature of the FLCD 20 is high and its operating speed is high, the refresh ratio is increased with a small interlace value. To the contrary, when the temperature is low and the operating speed is also low, the partial rewrite ratio is high with a relatively interlace value. The table is set as described above. Fig. 26 is a block diagram showing the interlace line address generator arranged in the rewrite detector/flag generator 117. Referring to Fig. 26, the interlace value obtained by the CPU 9 with reference to the table 9A is held in an interlace latch 121. A timing generator 123 generates a count-up enable time of an Hsync counter 125 in accordance with the interlace value held in the interlace latch 121. Fig. 27 is a detailed block diagram of the timing generator. Referring to Fig. 27, a decoder 1231 outputs a decoded signal having a relationship shown in Fig. 28 in accordance with the interlace value. Each output from the decoder 1231 is input to one input terminal of a corresponding one of AND gates. The other terminal of each of the AND gates 133 receives each bit signal from a shift register 1233 for performing a shift operation in synchronism with a clock. As a result, the timing generator 123 outputs a count-up enable signal (time) having a length corresponding to each interlace value shown in Fig. 29. The Hsync counter 125 performs a count-up operation in synchronism with the clock during the count-up enable time. The resultant count value is held in an address latch 127 at a predetermined timing. An initial register 131 holds an initial value (start address) of the Hsync counter 125. A comparator 129 compares the value of the interlace latch 121 with the value of the initial register 131. If these input values are equal to each other, the comparator 129 clears the value of the initial register 131. Fig. 30 is a flow chart showing a process flow of the interlace line address generator shown in Fig. 26. The initialization of the counter 125 is performed in step S11. In step S12, the value of the interlace latch is decoded by the decoder 1231. In steps S13 and S14, every time the signal Hsync goes to "1", the count-up operation is performed during the count enable time determined by the decoded interlace value. The address latch 128 latches the count value at the fall of this enable time. The latched count value is transferred as display line address data for interlace display to the line address generator 7. That is, the display lines are interlaced in accordance with the count value. In step S15, steps S13 and S14 are repeated until the number of display lines of the FLCD 20 becomes 1,024 or 0. If the number of display lines becomes equal to 1,024 or 0, the initial address of the initial register 131 is incremented by one in step S16. It is determined in step S17 that the initial address becomes equal to the interlace value, the initial address of the initial register 131 is initialized in step S19. The initialized value is set as the initial value of the Hsync counter 125. If the initial address does not reach the interlace value, this value is defined as the initial value of the counter 125 in step S18. Fig. 31 is a block diagram showing another arrangement of the interlace line address generator, and Fig. 32 is a timing chart thereof. An Hsync counter 203 counts up a signal Hsync , and a latch 204 latches this count value in response to any one of timing signals 1 to 4 transferred from a timing generator 202 through a selector 201. For example, assume the timing signal 1. As shown in Fig. 32, when the first timing signal 1 is set at "1", the counter value is zero. The display line address becomes zero. When the next timing signal 1 is set at "1", the counter value is 2, and the display line address becomes 2. In this case, one-interlace display is performed. The signals 1 to 4 from the timing generator 202 are also input to a mask timing generator 205 through the selector 201. An output mask timing signal is input to a data mask circuit 206, thereby masking the display data from the VRAM when the mask is set at "0". As is apparent from the above description, according to the present invention, an address corresponding to an interlace value set by the interlace generator arranged in the display controller is generated. Interlace display is performed on the basis of the display data of this address.

Claims: A display control apparatus for a display device (20) capable of performing updating of a display state for a display element subjected to a change in display and having a memory function, comprising: a) display data memory means (3) for storing display data; characterized by b) a CRT display controller (1) arranged to sequentially read out the display data stored in said memory means (3) and to transfer the readout display data to said display device (20) at a predetermined period and capable of performing a partial rewrite operation of the display data stored in said memory means (3) ; c) rewrite detecting means (5) for detecting an address used by said display generator (1) in order to access said display data memory means (3) and to perform the partial rewrite operation; and d) transfer permitting means (9) for reading the address detected by said rewrite detecting means (5) and permitting transfer of the display data of the detected address to said display device (20) . An apparatus according to claim 1, characterized in that said rewrite detecting means (5) has a flag register corresponding to the address of the display data in said display data memory means (3) and sets a flag of the detected address, and said transfer permitting means (9) reads the address for detection in accordance with a state of the flag of said flag register. An apparatus according to claim 1, characterized in that said transfer permitting means (9) permits the transfer at a period corresponding to the period of display driving of said display device (20) . An apparatus according to claim 1, characterized in that said transfer permitting means (9) permits the transfer at a period corresponding to a temperature of said display device (20) . An apparatus according to claim 1, characterized in that the display data stored in said display data memory means (3) are multi-value data having a number of values larger than two values and are binarized when being read out by said display controller (1) and transferred to said display device (20) . An apparatus according to claim 1, characterized by specific pattern rewrite detecting means (117) for detecting an address of the display data subjected to a rewrite operation of a specific pattern in said display data memory means (3) , wherein said transfer permitting means (9) is arranged to transfer the read address in units of blocks. An apparatus according to claim 1, characterized in that an interlace address generator (117) for generating an address corresponding to a set interlace value is provided in said display controller (1) , and that a line address generating means (7) is provided for transferring the address generated by said interlace address generator (117) to said display controller (1) and transferring display data of the transfer address to said display device (20) . A control method for a display device (20) capable of performing updating of a display state for a display element subjected to a change in display and having a memory function, comprising the step of: a) storing display data; characterized by the steps of b) sequentially reading out the stored display data and transferring the readout display data to said display device (20) at a predetermined period and performing a partial rewrite operation of the display data; c) detecting an address used to access said display data and performing the partial rewrite operation; and d) reading the detected address and permitting transfer of the display data of the detected address to said display device (20) . A method according to claim 8, characterized by setting a flag of the detected address in a flag register corresponding to the detected address of the display data, and reading the address for detection in accordance with a state of the flag. A method according to claim 8, characterized in that permitting the transfer at a period corresponding to the period of display driving of said display device (20) . A method according to claim 8, characterized by permitting the transfer at a period corresponding to a temperature of said display device (20) . A method according to claim 8, characterized by storing the display data as multi-value data having a number of values larger than two values and binarizing it when being read out and transferred to said display device (20) . A method according to claim 8, characterized by detecting an address of the display data subjected to a rewrite operation of a specific pattern, and transferring the read address in units of blocks. A method according to claim 8, characterized by generating an address corresponding to a set interlace value, and transferring display data of the generated address to said display device (20) .

Inventors: MATSUZAKI EIICHI, MORIMOTO HAJIME, NOBUTANI TOSHIYUKI, ONO KENICHIRO, SAKASHITA TATSUYA, SHIMAKURA MASAMI, TANAHASHI JUNICHI, MATSUZAKI, EIICHI, MORIMOTO, HAJIME, NOBUTANI, TOSHIYUKI, ONO, KENICHIRO, SAKASHITA, TATSUYA, SHIMAKURA, MASAMI, TANAHASHI, JUNICHI, MATSUZAKI, EIICHI, C/O CANON KABUSHIKI KAISHA, MORIMOTO, HAJIME, C/O CANON KABUSHIKI KAISHA, NOBUTANI, TOSHIYUKI, C/O CANON KABUSHIKI KAISHA, ONO, KENICHIRO, C/O CANON KABUSHIKI KAISHA, SAKASHITA, TATSUYA, C/O CANON KABUSHIKI KAISHA, SHIMAKURA, MASAMI, C/O CANON KABUSHIKI KAISHA, TANAHASHI, JUNICHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: G09G3
IPC codes: G09G3, G09G5