Method of manufacturing a semiconductor memory device

Abstract: After an insulator film has been formed on an upper layer of a capacitor constituting a memory cell, the insulator film is wet etched using a photo resist covering only a peripheral circuit portion as a mask and using a plate electrode covering the whole of a memory cell array portion as a stopper. For this reason, a step between the memory cell array portion and the peripheral circuit portion, originating from the formation of the capacitor, is moderated by the insulator film retained only in the peripheral circuit portion.

Description: FIELD OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device according to the preamble of claim 1. BACKGROUND OF THE INVENTION Patent Abstracts of Japan, volume 16, number 303, JP-A-4 082 263 discloses such a method of manufacturing semiconductor memory device in conformity with the prior art portion of claim 1. In this method the first insulator film is used to moderate a step between the memory cell array portion and the peripheral circuit portion. The first insulator film is removed from that memory cell portion using the photo resist as a mask covering the first insulator film provided on the peripheral circuit portion. The second insulator film covers the first insulator film and plate electrodes of the memory cell capacitors so as to form a smooth surface. The second insulator film is formed with substantially equal thickness. US-A-5 077 234 discloses a planarization method utilising three resist layers. In this method trenches with a varying width formed in a substrate and filled with an oxide layer are equalized with the outer surface of a substrate by successively covering the substrate with the resist layers and subsequent etching. Wide spacings are filled with a separate plug forming the first resist layer. Narrow trenches are filled with photo resists of a second layer which has covered the oxide layer in the region of the narrow trenches as well as the plug and has been etched with exception of the remaining trench-filling parts. A third planar photo resist is formed over the protecting part of the oxide layer, the trench-filling remaining second layer parts and the plug filling wide-spaced trenches. By removing all layers covering the upper surface of the substrate a complete filling of the trenches with the oxide layer with a smooth overall surface is achieved. US-A-4 642 162 discloses a planarization method for a semiconductor device structure by way of a two-stage planarization process. A first dielectric layer covering projecting parts of a substrate is coated with an organic layer. The organic layer is removed applying a plasma etching process with arbitrary selectivity between the organic planarization layer and the underlying dielectric layer in order to expose raised portions of the first dielectric layer. Though the selectivity between the organic planarization layer and the dielectric layer is arbitrary, it is preferred that the organic layer be etched faster than the dielectric layer to prevent overhanging ledges of dielectric material. This results in a complete etching of the organic planarization layer except in the region of trenches. In a subsequent plasma etching process the dielectric layer is removed faster than the organic planarization layer to remove substantially all of the exposed dielectric layer. This leaves peaks or ridges and valleys or trenches in the dielectric layer. Next the organic planarization layer is completely removed applying plasma etching or solvent stripping. In the last step a second insulating dielectric layer is formed by employing bias sputtering techniques which erode the peaks so as to form an uniform dielectric thickness. Fig. 15 shows a stacked capacitor DRAM manufactured by a first conventional method. As shown in Fig. 15, with increasing an integration level in a stacked capacitor DRAM, there is a trend that a storage node electrode 12 and a plate electrode 13 of a capacitor 11 are increasingly three-dimensionalized such as to secure a required memory cell capacitance in spite of a small plane surface area of the memory cell. In the first conventional method as shown in Fig. 15, however, the height of the memory cell is increased by the three-dimensionalized storage node electrode 12, which result in an increase in the step 23 between the memory cell array portion 15 and the peripheral circuit portion 16. For this reason, a focus margin is small during a light exposure in a lithography process after the capacitor 11 has been formed. I t causes the difficulty of patterning of a fine bit line 24, and an Aluminum wiring 25, or manufacturing of a DRAM with high yield was not feasible hitherto. Fig. 16 shows a stacked capacitor DRAM manufactured by a second conventional method. In this second method, the surface of an silicon substrate 14 in the memory cell array portion 15 is lowered relative to that in the peripheral circuit portion 16. In order to achieve this structure, first, an oxidation is carried out under a condition that the peripheral circuit portion 16 is covered with an oxidation-resistant SiN (Silicon nitride) film 17. Thus, as shown Fig. 17, a thick SiO 2 (Silicon dioxide) film 18 is formed on the surface of the memory cell array portion 15. Next, as shown in Fig. 18, both the SiN film 17 and the SiO 2 film 18 are removed so that the surface of the memory cell array portion 15 is lowered relative to that of the peripheral circuit portion 16. Thereafter, another oxidation is carried out under a condition that an active region of the memory cell array portion 15 and the peripheral circuit portion 16, respectively, is covered with an SiN film 21 so that an SiO 2 film 22 for an isolation is formed. In the second conventional method, the step between the memory cell array portion 15 and the peripheral circuit portion 16 after the formation of the capacitor 11 can be moderated, compared to the first conventional method. However, as shown in Fig. 16, an excessive film thickness of the SiO 2 film 18 to sufficiently moderate the step will increase a step 26 between the memory cell array portion 15 and the peripheral circuit portion 16 before the formation of the capacitor 11. For this reason, a focus margin is too small during light exposure in a lithography process on patterning of the SiO 2 film 22, a gate electrode 27 and the like. Therefore, manufacturing of a DRAM with high yield was not feasible according to the second conventional method, too. On the other hand, since the storage node electrode 12 and the plate electrode 13, both constituting the capacitor 11, are formed only in the memory cell array portion 15, patterning of these is uninfluenced by the steps 23 and 26 and hence relatively easy by nature. A known method of manufacturing semiconductor memory device includes steps described below. A first insulator film is formed on the whole of a substrate on which transistors and capacitors are provided. A photo resist is formed on the first insulator film which corresponds to a peripheral circuit portion. The first insulator film provided on a memory cell portion is removed by using the photo resist as a mask. A second insulator film is formed on a plate electrodes of the capacitor and the first insulator film of the peripheral circuit portion. The step between the memory cell array portion and the peripheral circuit portion, originating from the formation of the capacitor, is moderated by the insulator film retained only in the peripheral circuit portion. For this reason, a sufficiently large focus margin is secured during light exposure in a lithography process after the capacitor has been formed so that patterning of fine wiring is easily feasible. Moreover, since the insulator film is etched using a stopper covering the whole of the memory cell array portion, the insulator film of the memory cell array portion can easily be removed and thus the step between the memory cell array portion and the peripheral circuit portion can easily be moderated. However, in the above-described process there might arise an unwanted step portion which is described in more detail in Figs. 7 and 8. It is an object of the present invention to avoid the formation of this step portion. According to the present invention, the first photo resist can be formed in self-aligning fashion at the step portion of the insulator film by a whole surface etching-back or the like of the first photo resist formed on the insulator film. Therefore, if the edge of the second photo resist is only located on the first photo resist, only a memory cell array portion having higher step within the insulator film can be precisely removed. Therefore, an overlay margin is large on patterning the first and second photo resists, and the step between the memory cell array portion and the peripheral circuit portion can be easily moderated. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more readily understood with reference to the accompanying drawings, wherein: Fig. 1 is a sectional view of a DRAM at the initial stage of its manufacturing steps according to a first Example; Fig. 2 is a sectional view of the DRAM at the middle stage of its manufacturing steps according to the first Example; Fig. 3 is a sectional view of the DRAM at the final stage of its manufacturing steps according to the first Example; Fig. 4 is a sectional view of a DRAM at the initial stage of its manufacturing steps according to a second Example; Fig. 5 is a sectional view of the DRAM at the middle stage of its manufacturing steps according to a second Example; Fig. 6 is a sectional view of the DRAM at the final stage of its manufacturing steps according to the second Example; Fig. 7 is a sectional view of a DRAM at a possibly problematic stage of its manufacturing steps according to the first and second Examples; Fig. 8 is a sectional view of the DRAM at a stage following that of Fig. 7; Fig. 9 is a sectional view of a DRAM at the initial stage of its manufacturing steps according to a first embodiment of the present invention; Fig. 10 is a sectional view of the DRAM at the middle stage of its manufacturing steps according to the first embodiment of the present invention; Fig. 11 is a sectional view of the DRAM at the final stage of its manufacturing steps according to the first embodiment of the present invention; Fig. 12 is a sectional view of a DRAM at the initial stage of its manufacturing steps according to a second embodiment of the present invention; Fig. 13 is a sectional view of the DRAM at the middle stage of its manufacturing steps according to the second embodiment of the present invention; Fig. 14 is a sectional view of the DRAM at the final stage of its manufacturing steps according to the second embodiment of the present invention; Fig. 15 is a sectional view of a DRAM manufactured according to the first conventional method; Fig. 16 is a sectional view of a DRAM manufactured according to the second conventional method; Fig. 17 is a sectional view showing the initial stage of the manufacturing steps according to the second conventional method; and Fig. 18 is a sectional view showing a stage following that of Fig. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The Examples and the preferred embodiments of the present invention will be described in detail by referring to Figs. 1 to 14. In these drawings, the same reference numerals are utilized as shown in Figs. 15 to 18 so far as the same portions are referred. Figs. 1 to 3 show the first Example applied for manufacturing a stacked capacitor DRAM in which a bit line is formed after formation of a capacitor. In the first Example, as shown in Fig. 1, an SiO 2 film 22 for isolation is grown on a surface of a silicon substrate 14 by the LOCOS (LOCal Oxidation of Silicon) method or the like and, thereafter, an SiO 2 film 28 as a gate oxide is formed on a surface of an active region surrounded by the SiO 2 film 22. Subsequently, a gate electrode 27 serving as a word line in the memory cell array portion 15 is formed with a tungsten polycide film or the like. Thereafter, using the gate electrode 27 and the SiO 2 film 22 as a mask, N - -type diffused layers 31a to 31d are formed by an ion implantation of N type impurities into the silicon substrate 14 such that the concentration of the N type impurities at the surface of the active region falls into the range of 10 17 to 10 19 cm -3 . A transistor 32 constituting a memory cell in the memory cell array portion 15 is completed by the steps as mentioned above. Thereafter, by depositing according to a CVD (Chemical Vapor Deposition) method and subsequent etching-back of an SiO 2 film, an SiN film or a polycrystalline silicon film or the like, a sidewall 33 comprising these films is formed at the side part of the gate electrode 27. Then, using the gate electrode 27, the sidewall 33 and the SiO 2 film 22 as a mask, N + -type diffused layers 34a and 34b are formed by an ion implantation of N type impurities into the silicon substrate 14 followed by a subsequent annealing. The concentration of the N type impurities at the surface of the active region in the peripheral circuit portion 16 becomes greater than 10 19 cm -3 . A transistor 35 in the peripheral circuit portion 16 is completed by the steps as mentioned above. Thereafter, an interlayer insulator 36 is formed by depositing an SiO 2 film containing no impurities, a PSG (Phospho silicate glass) film, a BPSG (Boro Phospho silicate glass) film, an SiN film or a combined film of them according to a CVD method, and then a contact hole 37 reaching the diffused layer 31b is formed in the interlayer insulator 36. By patterning a polycrystalline silicon film having a thickness in the order of several hundreds nm to 1 µ and containing N type impurities greater than 10 19 cm -3 , a storage node electrode 12 is formed such as to be in contact with the diffused layer 31b through the contact hole 37. The storage node electrode 12 can be shaped not only as a nearly rectangular parallelepiped shown in Fig. 1 but also as a fin, a cylinder or the like. Thereafter, the resultant structure is further treated by depositing a dielectric film 38 like an SiO 2 film, an SiN film, a Ta 2 O 5 film or the like according to a CVD method, a sputtering method or the like. Subsequently, by depositing a polycrystalline silicon film on the dielectric film 38 and then by introducing impurities into the polycrystalline silicon film. By patterning these, a plate electrode 13 comprising the polycrystalline silicon film containing impurities is formed. A capacitor 11 constituting the memory cell in the memory cell array portion 15 is completed by the steps as mentioned above. It is to be noted that, by the above-mentioned patterning, segments in a contact between the diffused layer 31a and the bit line are not removed, and hence the plate electrode 13 covers the whole of the memory cell array portion 15. As is apparent from Fig. 1, the sum of the film thickness of the storage node electrode 12 and the plate electrode 13 is equal to the step 23 after the capacitor 11 has been formed. Next, as shown in Fig. 2, an insulator film 41 is formed by depositing an SiO2 film containing no impurities, a PSG film, a BPSG film or a combined film of them according to a CVD method. Then a photo resist 42 is coated on the insulator film 41 which corresponds to the peripheral circuit portion 16. The film thickness of the insulator film 41 is adjusted to fall into the range of several hundreds nm to several µm, approximately equaling to the step 23. Using the resist 42 as a mask and using the plate electrode 13 as a stopper, the insulator film 41 is wet-etched by a solution containing a hydrofluoric acid. As an alternative stopper for the wet etching, an SiN film (not shown) which has been deposited on the plate electrode 13 can also be used. Next, as shown in Fig. 3, an another insulator film 43 is formed by depositing an SiO 2 film containing no impurities, a PSG film, an SiN film or a combined film of them and a BPSG film according to a CVD method, after a removal of segments in the contact between the diffused layer 31a and a bit line out of the plate electrode 13. Then, after planarizing the insulator film 43 by flowing the BPSG film through a high temperature annealing, contact holes 44 and 45 reaching the diffused layers 31a and 34b are formed in the insulator film 43. Thereafter, an interlayer insulator 46 is formed by depositing an SiO2 film containing no impurities, a PSG film, an SiN film or a combined film of them and a BPSG film according to a CVD method, after forming a bit line 24 contacting the diffused layers 31a and 34b through the contact holes 44 and 45 by patterning of a film of W, Mo, Ti, Ta or their silicide or polycide. Then, after planarizing the interlayer insulator 46 by flowing the BPSG film through a high temperature annealing, a contact hole 47 reaching the bit line 24 is formed in the interlayer insulator 46. Thereafter, by patterning of an Aluminum wiring 25 which is a composite film of AlSi or AlSiCu with Ti or TiON and by forming a passivation film 48 with an SiN film, an SiON film or the like, a DRAM is completed. In this DRAM, the Aluminum wiring 25 is of single layer while a multiple-layered Aluminum wiring may also be applied. In the first Example as explained above, the step 23 originating from both the storage node electrode 12 and the plate electrode 13 of the capacitor 11 is moderated by the insulator film 41 retained in the peripheral circuit portion 16. For this reason, even when the step 23 is increased up to about 1.0 µm by three-dimensionalizing the storage node electrode 12, a sufficiently large focus margin is secured during light exposure in a lithography process for patterning the bit line 24 and the Aluminum wiring 25 so that their patterning is easily feasible. Figs. 4 to 6 show the second Example of the present invention applied for manufacturing a stacked capacitor DRAM of so-called shielded bit line type wherein a capacitor 11 is formed after the formation of a bit line 24. In the second Example, essentially the same steps are carried out as in the first Example as explained above except that a capacitor 11 is formed after the formation of a bit line 24. In the second Example, however, as shown in Fig.6, since an aspect ratio of the contact hole 47 for the Aluminum wiring 25 gets larger because the contact hole 47 is exposed to the influence of the step 23, the contact hole 47 is filled up with a tungsten plug 51. By the way, in the above-mentioned first and second Examples as shown in Figs. 1 to 3 and Figs. 4 to 6, respectively, the resist 42 serving as a mask on wet etching of the insulator film 41 is not subjected to a patterning in self-aligning fashion. As shown in Fig. 7, therefore, the pattern of the resist 42 can possibly be shifted relative to that of the underlaying field, e.g., in the direction of the memory cell array portion 15. As a result of this, as shown in Fig. 8, a projection 41a is formed on the insulator film 41 at the boundary between the memory cell array portion 15 and the peripheral circuit portion 16. Due to this projection 41a, a step portion is formed. For this reason, patternings of wiring of the bit line 24 and the like on an upper layer placed above the capacitor 11 become difficult. Figs. 9 to 11 show the first embodiment of the present invention, wherein the above-mentioned problem is solved in the manufacturing of a stacked capacitor DRAM in which a bit line is formed after the formation of a capacitor. In the first embodiment also, as shown in Fig. 9, approximately the same steps as those in the above-mentioned first Example are carried out up to the formation of the insulator film 41. It is to be noted here, however, that the insulator film 41 may be formed by an SiN film, and that a segment in the contact between the diffused layer 31a and the bit line out of the plate electrode 13 is removed. Thereafter, a resist 52 is coated in a thickness of several hundreds nm to several m, and the resist 52 then is etched back using O 2 or CF 4 + O 2 such that the resist 52 is retained only at step portions in self-aligning fashion. A polyimide resin or the like can be used instead of the resist 52. Next, as shown in Fig. 10, the resist 42 is patterned such that the resist 42 covers only the peripheral circuit portion 16 and an edge of the resist 42 is located on the resist 52. If the edge of the resist 42 is only located on the resist 52, the pattern of the boolean ADD of the resists 42 and 52 will not be position-shifted even when the resist 42 is position-shifted. Therefore, when the insulator film 41 is anisotropically dry etched using the resists 42 and 52 as a mask, only segments having higher steps on the capacitor 11 within the insulator film 41 are precisely removed. While the contact between the diffused layer 31a and the bit line 24 is also filled up with the insulator film 41 such that the whole including both the memory cell array portion 15 and the peripheral circuit portion 16 is planarized. Subsequently, as shown in Fig. 11, after similar steps to those for the first Example have been applied, a DRAM is completed. Figs. 12 to 14 show the second embodiment of the present invention applied for manufacturing a stacked capacitor DRAM of so-called shielded bit line type wherein the capacitor 11 is formed after the formation of the bit line 24. In the second embodiment, for a removal of the insulator film 41 in the memory cell array portion 15, resists 42 and 52 are used as masks similar to those in the first embodiment as is shown in Figs. 9 to 11, and the wet etching is effected using the plate electrode 13 as a stopper, similar to that in the second Example as is shown in Figs. 4 to 6. While specific embodiments of the invention have been shown and disclosed, it is to be understood that numerous changes and modifications may be made by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims: A method of manufacturing a semiconductor memory device having a memory cell array portion (15) and a peripheral circuit portion (16) wherein each memory cell comprises a memory cell transistor and a memory cell capacitor (11), comprising steps of: forming said memory cell transistors (32) on a semiconductor substrate (14); forming said memory cell capacitors (11) on said substrate (14) of said memory cell array portion, each capacitor (11) comprising a storage node electrode (12) and a plate electrode (13) provided on said node electrode (12); forming a first insulator film (41) on the whole of said substrate (14); characterized by the steps of forming layered photoresist consisting of a first photo resist (52) formed only at a step portion of said first insulator film (41) in self-aligning fashion and a second photo resist (42) such that an edge of said second photo resist (42) is located on said first photo resist (52); removing said first insulator film (41) provided on said memory cell portion (15) by using said first (52) and second photo resist (42) as a mask; and forming a second insulator film (43) on said plate electrodes (13) of said memory cell capacitors (11) and said first insulator film (41) of said peripheral circuit portion (16). A method of manufacturi'ng semiconductor memory device according to claim 1, wherein said first insulator film (41) of said memory cell array portion (15) is removed by wet etching. A method of manufacturing semiconductor memory device according to claim 1, wherein said first insulator film (41) of said memory cell array portion (15) is removed by an isotropic dry etching. A method of manufacturing semiconductor memory device according to claim 1, wherein said first insulator film (41) of said memory cell array portion (15) is removed by using said plate electrodes (13) provided on the whole of said memory cell array portion (15) as an etch stopper. A method of manufacturing semiconductor memory device according to claim 1, comprising step of; forming a silicon nitride film on said each plate electrode (13), wherein said first insulator film (41) of said memory cell array portion (15) is removed by using said silicon nitride films as an etch stopper.

Inventors: KURODA HIDEAKI, KURODA, HIDEAKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H01L27
IPC codes: H01L27, H01L21