Method of erasing data on non-volatile semi-conductor memory

Abstract: In order to suppress dispersion of threshold level voltages upon erasure of a large number of cells constituted from FETs having a floating gate electrode, drain electrode D, source electrode S and substrate Sub of each memory cell, all of the above electrodes are set to 0 V while a pulse of -19 v and a pulse width of 0.01 second is applied to control gate electrode CG to remove electrons accumulated in floating gate electrode FG by an F-N tunnel current. Then, while drain electrode D, source electrode S and substrate Sub are kept set to 0 V, another pulse of 14 V and a pulse width of 0.1 second is applied to control gate electrode CG to effect injection of electrons into floating gate electrode FG by the F-N tunnel current.

Description: BACKGROUND OF THE INVENTION Field of the Invention: This invention relates to a method of erasing data on a non-volatile semi-conductor memory, and more particularly to a method of erasing data on a non-volatile semi-conductor memory wherein a large number of field effect transistors each having a floating gate electrode are arrayed as memory cells. Description of Related Art: Fig. 1(A) is a circuit diagram of a memory cell of a non-volatile semi-conductor memory wherein a large number of field effect transistors (hereinafter referred to as FETs) each having a floating gate electrode are arrayed as memory cells, and Fig. 1(B) is a sectional view showing the structure of the memory cell. The memory cell shown in Figs. 1(A) and 1(B) includes P-type silicon substrate 1, tunnel oxide film 2 formed by using a silicon thermal oxidation technique, a thin film forming technique based on the CVD (chemical vapour deposition) method, a photolithography technique, a thin film dry etching technique or some other suitable technique, floating gate electrode FG of polycrystalline silicon, interlayer insulator film 3, a gate electrode portion of the two polycrystalline silicon layer type, and source electrode S and drain electrode D of a diffused layer formed by using an ion implantation technique of phosphor or arsenic. In the non-volatile memory, electrons are accumulated into floating gate electrode FG through tunnel oxide film 2 to raise the threshold level voltage of the FET memory cell at control gate electrode CG in order to write data, and the electrons are removed from floating gate electrode FG through tunnel oxide film 2 to lower the threshold level voltage in order to erase the data. In the non-volatile memory described above, it is known that the threshold levels of the memory cells after erasure of data disperse within a range of several volts due to dispersion in film thickness, film quality or working accuracy of tunnel oxide film 2 of the memory cells. As one countermeasure for suppressing dispersion, a method which makes use of injection of hot carriers into the floating gate electrodes arising from the drain avalanche phenomenon is conventionally known (Seiji Yamada, Technical Digest of 1991 International Electron Devices Meeting, pp.307-310). An outline of the method is described with reference to Fig. 5. Fig. 5 is a diagram showing the relationship of gate current I g to floating gate voltage V fg * and control gate voltage V cg when floating gate electrode FG is charged positively. When the relationship between source-drain voltage V ds and floating gate voltage V fg is V ds > V fg , hot carriers generated by the source-drain current are injected into floating gate electrode FG. The types of hot carriers depend upon the floating gate voltage, and are classfied, from the low voltage side as, hot holes (in the area of (H.H.) in Fig. 5) originating in a drain avalanche phenomenon, hot electrons (in the area of (H.E.) in Fig. 5) originating from a drain avalanche phenomenon, and channel hot electrons (in the area of (C.H.E.) in Fig. 5). It is important here that, when the floating gate voltage increases to the level indicated by V fg * in Fig. 5, hot carriers are not injected into floating gate electrode FG any more and the polarity of the carrier charge is reversed. As a result, when, for example, the floating gate voltage is higher than V fg * and the relationship of V ds > V fg is satisfied, a feedback mechanism in which injection of hot electrons into floating gate electrode FG drops the floating gate voltage and the drop of the floating gate voltage reduces the injection amount of hot electrons is formed between the floating gate voltage and the hot electron injection amount, so that the floating gate voltage converges to V fg *. Timings of voltage application to the electrodes in order to actually erase data are described with reference to Fig. 6. First, drain electrode D is set to 0 volt and -13 V is applied to control gate electrode CG while a pulse of 5 V is applied for 0.1 second to source electrode S to remove electrons accumulated in floating gate electrode FG by an F-N (Fowler-Nordhein) tunnel current, and then so-called excessive erasure is performed to accumulate positive holes to charge floating gate electrode 3 to V fg * = 2.0 V or more. Then, control gate electrode CG is set to 0 V, and a pulse of 5.0 V is applied for 0.5 seconds to source electrode S. As a result of the disposition, the feedback mechanism between the floating gate electrode and the hot electron injection amount described above operates so that the floating gate voltage converges to 2.0 V. As a result, the threshold level of control gate electrode CG after data erasure also converges to a fixed value, which can suppress possible fluctuation of the threshold levels of the memory cells. In fact, the threshold level voltage can be controlled within a range of about 0.7 V depending upon the dispersion of the configuration of source electrode S or some other factor. With the conventional method of erasing data on a non-volatile semi-conductor memory described above, however, since the drain avalanche phenomenon is used for erasure, there is a problem in that source electrode S and drain electrode D suffer from some damage, resulting in degradation of the voltage-withstanding property of the junction between the diffused layer of the electrodes and the substrate. Further, in order to make the threshold voltages of the memory cells uniform after an erasure, positive holes are injected into floating gate electrode FG so as to effect excessive erasure upon each erasure. Accordingly, since the injection of positive holes accelerates degradation of tunnel oxide film 2, there is another problem that the switching characteristic between writing and erasure is degraded by the degradation of tunnel oxide film 2. Furthermore, in order to make the threshold voltages uniform after erasure of data, the source-drain current for causing the drain avalanche phenomenon is required, in addition to electrons to flow into floating gate electrode FG. Accordingly, there is a further problem in that the disposition to make the threshold voltages uniform after erasure of data results in higher power dissipation. US-A-5,132,935 describes a method for eliminating reading errors caused by over-erased cells by subsequently applying alternating erasing and programming pulses to the cells of an EEPROM array, starting with relatively high-energy-level erasing and programming voltages and decreasing the energy-level of each of the alternating erasing and programming voltages. As the energy-levels are decreased, the threshold voltage range of the memory cells is compacted, the final threshold voltages being distributed within a preselected narrow range of positive values that are less than a predetermined wordline select voltage. SUMMARY OF THE INVENTION It is the first object of the present invention to provide a data erasing method which does not depend upon the drain avalanche phenomenon. It is a second object of the present invention to provide a data erasing method which does not cause degradation of a tunnel oxide film arising from excessive erasure performed for a floating gate upon erasure of data. It is a third object of the present invention to provide a data erasing method which is low in power dissipation. In a first aspect, the present invention provides a method of erasing data on a non-volatile semi-conductor memory on which a plurality of n- or p-type fidd effect transistors each having a source electrode, a drain electrode, a floating gate electrode and a control gate electrode are arrayed on a semi-conductor substrate as non-volatile memory cells and wherein a low threshold voltage state is defined as an erasing state and a high threshold voltage state is defined as a writing state, comprising the step of applying, to each of the n-type field effect transistors, a negative first voltage, or to each of the p-type field effect transistors, a positive first voltage at the control gate electrode, with respect to the source and the drain electrode for a first application time to erase the cells by a Fowler-Nordheim tunnel current, characterised in that the threshold voltage of the field effect transistor having the lowest data erasing operation speed becomes a predetermined value nearest to a value in the writing state, from a range of values in the data erasing state; the method further comprising the step of applying, to each of the n-type field effect transistors, a positive second voltage, or to each of the p-type field effect transistors, a negative second voltage to the control gate electrode, with respect to the potential at the source and the drain electrode for a second application time to write the cells by a Fowler-Nordheim tunnel current so that the threshold voltage of the field effect transistor having the highest data writing operation speed becomes said predetermined value. In a second aspect, the present invention provides a method of erasing data on a non-volatile semi-conductor memory on which a plurality of n- or p-type field effect transistors each having a source electrode, a drain electrode, a floating gate electrode and a control gate electrode are arrayed on a semi-conductor substrate as non-volatile memory cells and wherein a low threshold voltage state is defined as a writing state and a high threshold voltage state is defined as an erasing state, comprising the step of applying, to each of the n-type field effect transistors, a positive first voltage, or to each of the p-type field effect transistors, a negative first voltage to the control gate electrode, with respect to the potential at the source electrode and the drain electrode for a first application time to erase the cells by a Fowler-Nordheim tunnel current, characterised in that the threshold voltage of the field effect transistor having the lowest data erasing operation speed becomes a predetermined value nearest to a value in the writing state, from a range of values in the data erasing state; the method further comprising the step of applying, to each of the n-type field effect transistors, a negative second voltage, or to each of the p-type field effect transistors, a positive second voltage to the control gate electrode, with respect to the potential at the source electrode and the drain electrode, for a second application time to write the cells by a Fowler-Nordheim tunnel current so that the threshold level voltage of the field effect transistor having the highest data writing operation speed becomes the predetermined value. In particular, the first application time is preferably 0.01 second, the first voltage is 19 volts, the second applicaion time is 0.1 second and the second voltage is 14 volts. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1(A) and 1(B) are a circuit diagram of a memory cell of a non-volatile semi-conductor memory as an object for erasure of data and a sectional view showing the structure of the memory, respectively; Figs. 2(A) and 2(B) are a circuit diagram of the memory cell of a first embodiment of the present invention and a timing chart illustrating application of voltages to the electrodes of the memory cell upon erasure of data, respectively; Fig. 3 is a characteristic diagram illustrating variations with respect to time of the memory cell threshold voltage upon erasure of data by the F-N tunnel current and upon injection of electrons into the floating gate; Fig. 4 is a timing chart of application of voltages to the electrodes upon erasure of data of a memory cell of a second embodiment of the present invention; Fig. 5 is a characteristic diagram of the gate current with respect to the floating gate voltage and the control gate voltage of a memory cell according to a method of erasing data on a conventional non-volatile semi-conductor memory; and Fig. 6 is a timing chart of application of voltages to the electrodes upon erasure of data of a memory cell of a conventional non-evaporate semiconductor memory. DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, embodiments of the present invention are described with reference to the drawings. Figs. 2(A) and 2(B) are a circuit diagram of a memory cell illustrating a first embodiment of the present invention and a timing chart of applying voltages to the electrodes of the memory cell upon erasure of data, respectively. In the following description, the first embodiment is described in accordance with the progress of the disposition upon erasure of data. It is to be noted that the structure of the memory cell is the same as that of the conventional memory cell shown in Figs. 1(A) and 1(B). First, drain electrode D, source electrode S and substrate Sub of each memory cell are set to 0 V while a pulse of -19V and a pulse width of 0.01 second is applied to control gate electrode CG to remove electrons accumulated in floating gate electrode FG by an F-N tunnel current. The fluctuation with respect to application time of the threshold voltage of the memory cell upon erasure of data by the F-N tunnel current is indicated by curves C1 and C2 in Fig. 3. All the memory cells are designed as same characteristics. However, actual memory cells easy to have different characteristics. Therefore, data erasing operation speed fluctuates in every memory cells. In case of a memory cell having lowest data erasing operation speed, a threshold voltage is lowered as the curve C1. When the application time is equal to 0.01 second, the threshold voltage becomes equal to 3 V which is the upper limit value (value nearest to that in the writing state) within the range of the threshold voltage set for the data erasing condition. Meanwhile, the threshold voltage of another memory cell having highest erasing operation speed is lowered as the curve C2. When the application time is equal to the 0.01 second, the threshold votage becomes equal to 1 V. As a result, the threshold level voltages fluctuate within the range of 2 V. It should be noted that in case of the memory cell having highest erasing speed, the highest F-N tunnel current flows through tunnel oxide film 2 per unit time. In addition, the memory cell exhibits a higher injection speed than any other memory cell when a positive voltage is applied between the control gate electrode and the substrate to inject electrons into the floating gate electrode. If the threshold voltage is sufficiently low, the variation of the threshold voltage upon injection is raised in accordance with curve C4 in Fig. 3. Meanwhile, in case of the memory cell having lowest erasing speed, the lowest F-N tunnel current flows through tunnel oxide film 2 per unit time. The memory cell exhibits a lower injection speed than any other memory cell. If the threshold voltage is sufficiently low, the threshold voltage upon injection is raised in accordance with curve C3 in Fig. 3. Therefore, following erasure of data by the F-N tunnel current described above, while drain electrode D, source electrode S and substrate Sub are kept set to 0 V, a pulse of 14 V and a pulse width of 0.1 second is applied to control gate electrode CG to inject electrons into floating gate electrode FG by the F-N tunnel current. The required condition for the injection is that the threshold voltage of the memory cell having highest injecting operation speed is raised to 3 V which is the upper limit value within the range of data erasing condition. In this instance, the threshold level voltage of the memory cell having highest erasing operation speed becomes equal to 3 V in accordance with curve C4 in Fig. 3. However, the threshold voltage of the memory cell having lowest erasing operation speed is already equal to 3 V, and in this instance, even if a pulse of 14 V and 0.1 second is applied to control gate electrode CG, the threshold level voltage of the memory cell remains equal to 3 V, because injection of electrons into floating gate electrode FG by the F-N tunnel current does not take place unless the pulse width is longer than 0.1 second (refer to curve C3 in Fig. 3). Consequently, the threshold voltages converge approximately to 3 V, and dispersion of the threshold level voltages is suppressed. Fig. 4 is a timing chart of application of voltages to the electrodes upon erasure of data of a memory cell of a second embodiment of the present invention. The second embodiment is described below in accordance with the procedure of the disposition upon erasure of data. First, drain electrode D, source electrode S and substrate Sub of each memory cell are set to 5 V while a pulse of -14 V and a pulse width of 0.01 second is applied to control gate electrode CG to remove electrons accumulated in floating gate electrode FG by the F-N tunnel current. Following the erasure of data by the F-N current, drain electrode D, source electrode S and substrate Sub are set to -5 V while a pulse of 9 V and a pulse width of 0.1 second is applied to control gate electrode CG to inject electrons into floating gate electrode FG by the F-N tunnel current. In the present embodiment, the absolute values of the voltages applied to the electrodes are different from those in the first embodiment, but the effective bias voltages between the control gate electrode and the source, drain and substrate electrodes, as well as the effects are exactly the same as those of the first embodiment. However, with the second embodiment, since the absolute values of the voltages applied to the electrodes are lower than those in the first embodiment. Therefore the second embodiment is more advantageous in terms of the voltage withstanding property and the required power supply. While a P-type silicon substrate is employed as the semi-conductor substrate in the embodiments described above, a different semi-conductor substrate may be employed instead. Further, other voltage values may be employed as the voltage values to be applied to the electrodes if erasure of data and suppression of the dispersion of the threshold voltages by the F-N tunnel current after erasure of data are performed. As described above, according to the present invention, since it is constructed so that injection of electrons into floating gate electrode 3 using the F-N tunnel current is performed for a predetermined period of time after erasure of data, there is an advantage in that possible dispersion of the threshold level voltages after erasure of data can be suppressed. Further, since only the F-N tunnel current is used in order to control the threshold voltages to a fixed value, there is another advantage in that the voltage withstanding property of the junction between each diffused layer and the substrate is not degraded at all. Further, since the current which is produced when the threshold level voltages are controlled to a fixed value after erasure of data involves only electrons flowing into the floating gate electrode, there is a further advantage in that power dissipation can be reduced.

Claims: A method of erasing data on a non-volatile semi-conductor memory on which a plurality of n- or p-type field effect transistors each having a source electrode (S), a drain electrode (D), a floating gate electrode (FG) and a control gate electrode (CG) are arrayed on a semi-conductor substrate (Sub) as non-volatile memory cells and wherein a low threshold voltage state is defined as an erasing state and a high threshold voltage state is defined as a writing state, comprising the step of: applying, to each of the n-type field effect transistors, a negative first voltage, or to each of the p-type field effect transistors, a positive first voltage at the control gate electrode, with respect to the source and the drain electrode for a first application time to erase the cells by a Fowler-Nordheim tunnel current, characterised in that the threshold voltage of the field effect transistor having the lowest data erasing operation speed becomes a predetermined value nearest to a value in the writing state, from a range of values in the data erasing state; the method further comprising the step of: applying, to each of the n-type field effect transistors, a positive second voltage, or to each of the p-type field effect transistors, a negative second voltage to the control gate electrode, with respect to the potential at the source and the drain electrode for a second application time to write the cells by a Fowler-Nordheim tunnel current so that the threshold voltage of the field effect transistor having the highest data writing operation speed becomes said predetermined value. A method of erasing data on a non-volatile semi-conductor memory on which a plurality of n- or p-type field effect transistors each having a source electrode (S), a drain electrode (D), a floating gate electrode (FG) and a control gate electrode (CG) are arrayed on a semi-conductor substrate as non-volatile memory cells and wherein a low threshold voltage state is defined as a writing state and a high threshold voltage state is defined as an erasing state, comprising the step of: applying, to each of the n-type field effect transistors, a positive first voltage, or to each of the p-type field effect transistors, a negative first voltage to the control gate electrode, with respect to the potential at the source electrode and the drain electrode for a first application time to erase the cells by a Fowler-Nordheim tunnel current, characterised in that the threshold voltage of the field effect transistor having the lowest data erasing operation speed becomes a predetermined value nearest to a value in the writing state, from a range of values in the data erasing state; the method further comprising the step of: applying, to each of the n-type field effect transistors, a negative second voltage, or to each of the p-type field effect transistors, a positive second voltage to the control gate electrode, with respect to the potential at the source electrode and the drain electrode, for a second application time to write the cells by a Fowler-Nordheim tunnel current so that the threshold level voltage of the field effect transistor having the highest data writing operation speed becomes the predetermined value. A method as claimed in Claim 1 or 2, wherein the first application time is 0.01 second, the first voltage is 19 volts, the second application time is 0.1 second and the second voltage is 14 volts. A method as claimed in any preceding claim, wherein the cell having a lowest data erasing operation speed allows Fowler-Nordheim current to pass a tunnel insulation film (2) of that cell and the cell having a highest erasing operation speed allows a greatest Fowler-Nordheim current to pass a tunnel insulation film (2) of that cell. A method of erasing data on a non-volatile semi-conductor memory as claimed in any preceding claim, wherein said plurality of cells are n-type field effect transistors.

Inventors: OYAMA KENICHI, OYAMA, KENICHI, OYAMA, KENICHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: G11C16
IPC codes: G11C16, G11C17