LOGIC CELL FOR FIELD PROGRAMMABLE GATE ARRAY HAVING OPTIONAL INTERNAL FEEDBACK AND OPTIONAL CASCADE

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

Description: LOGIC CELL FOR FIELD PROGRAMMABLE GATE ARRAY HAVING OPTIONAL INTERNAL FEEDBACK AND OPTIONAL CASCADE FIELD OF THE INVENTION The invention relates to programmable logic devices formed in integrated circuit semiconductor chips. More particularly, the invention relates to logic cells which are part of field programmable gate array chips. BACKGROUND OF THE INVENTION Programmable devices are currently available in several different architectures. Earliest of the programmable devices are the programmable logic array (PLA) devices which comprise a plurality of AND gates programmably connected to a second plurality of OR gates. These devices can generate any combinational logic function, because any combinational logic function can be written as a sum of products, the products being generated in the AND array and the sums being generated in the OR array. These two level logic devices (one AND level and one OR level) are simple to program, and it is easy to predict the time delay for generating an output. However, the silicon area needed to calculate a complex logic function can be undesirably large. More recently, programmable logic devices called field programmable gate arrays or FPGAs have been developed. These devices comprise an array of programmable logic cells which can be interconnected by programmable interconnect lines to generate complex logic functions. In an FPGA device, a function need not be calculated as a two-level sum of products because it is possible to feed the output of any one logic cell to an input of any other logic cell, and thereby form a chain, generating a function which has multiple levels of logic. Thus it is possible to implement complex logic in a smaller physical area. Several architectures of these field programmable logic devices are available today. The various devices differ in the complexity of a single logic cell. Some manufacturers offer devices having logic cells such as shown in Fig. 1 which are quite small (fine grained architecture) . Others offer devices having logic cells such as shown in Fig. 2 which are considerably larger and which handle larger functions within a single logic block (coarse grained architecture) . A small logic cell such as shown in Fig. 1 has the advantage of being able to be completely filled by the logic of a user, and thereby not leave unused logic resources within the cell. It may be possible to generate either combinational or sequential functions from a plurality of small logic cells. However, with fine grained architectures made up of small logic cells, it requires many logic cells to generate a complex logic function. A function which must make use of more than one logic cell must use programmable interconnect line to generate the function. When the signal path passes through resistive programmable elements, the time delay associated with capacitive and resistive interconnect line considerably slows down the response of the sequential function. The larger celled (coarse grained) logic devices can generate complex functions quickly within a single logic block. However, if the user specifies a set of functions which do not make full use of the rather large logic cell, portions of the logic cell will be unused. Also, some of the fairly large logic cells include separate resources for generating combinational functions and for generating sequential functions. The cell of Fig. 2 is such a cell. If a user wants a circuit which uses many combinational functions and few sequential functions, many sequential resources will be unused. Likewise, if the user wants many sequential functions and few combinational functions, many combinational functions will go unused. Another significant consumer of silicon faced by designers is that signals must be inverted, and using a configurable cell to generate an inverter consumes resources otherwise available for more powerful functions. Prior efforts have been made to provide dedicated hardware for the invert function. A structure described by Quicklogic in a publication entitled pASIC™ 1 Family ViaLink™ Technology Very High Speed CMOS FPGAs published May 1991 shows a programmable structure using two-input AND gates which have one inverted input and one non-inverted input. This structure thus gives a choice of applying a signal to the inverted or the non-inverted input. Though this solution allows for applying signals to both the inverted and noninverted inputs, when used simply to offer an optional inversion, this solution doubles the number of input lines needed. Thus using the above structure to achieve optional inverters adds considerable silicon area and complexity to a cell. SUMMARY OF THE INVENTION It is the goal of the present invention to provide a logic cell which is flexible, dense and fast, that is, which implements many useful functions, which allows a user's logic to be implemented in a small silicon area, and which is fast at generating an output signal in response to an input signal. According to the present invention, a logic cell is provided which includes an optional internal feedback loop for sequential functions and thus avoids the delay and the resource consumption of using general interconnect for feedback. This optional feedback loop allows high density utilization of the chip since no area is wasted by having the wrong ratio of dedicated resources for combinational and sequential functions. The invention also provides an optional feed-forward or cascade connection. Speed of generating wide combinational functions, cascading latches to form flip flops, and of forwarding signals without multiple fanout is achieved by providing an optional connection from the output of one cell to an input of an adjacent cell, allowing adjacent cells to be cascaded together. (This feature will be called the cascade feature.) A cell incorporating the present invention includes three sections: (D a cascade section which receives input from the general interconnect structure and optionally as another input receives output from an adjacent cell, (2) a feedback section which also receives input from the general interconnect structure and optionally receives feedback from the same cell, and (3) a second stage combinational section which combines signals from the cascase and feedback sections in a selectable way and generates an output signal. Internal Feedback To form a latch, the internal feedback loop is enabled, providing the output signal from the second combinational section as input to the feedback section. An input signal is provided to the cascade section, and a clock signal selects between the two sections. Thus when the clock signal selects the feedback section, the input signal is latched into the feedback section. With this optional internal feedback loop, sequential functions may be formed without placing any programmable interconnect means or any input or output buffers in the signal path, resulting in a high speed, small implementation of a sequential function. When the feedback option is not used, the cell can generate decoders, multiplexers, or other combinational functions. Cascade It is possible to combine adjacent cells for performing certain functions without inserting any interconnect means or any input or output buffer means into the signal path. The output of one cell is programmably provided as input to an adjacent cell, bypassing the input/output buffering means. This allows the designer to generate wide functions without adding significant delay beyond the delay of using a single cell. For implementing logic gates which have only one source and one destination, the improvement is valuable because the gates can be implemented in adjacent cells which are connected through the cascade path, again avoiding the input/output buffering means. Thus the gate delay can be minimized. A significant speed and density improvement is thus provided by this cascade feature. Example Functions Functions which can be generated by a single cell of the present invention include a two-input multiplexer, exclusive- or and exclusive-nor gates, a two-input sum of two-input products, a transparent latch, a set/reset latch, and two- to four-input AND and OR functions. Larger functions can be generated by combining adjacent cells using the cascade feature. For example, a D-flip flop can be generated using the feedback and cascade features without using the general interconnect structure. Still larger functions can also use the general interconnect structure. For example, a JK flip flop can be generated using three adjacent cells and one piece of general interconnect line. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art logic cell having a small cell size. Fig. 2 shows a prior art logic cell having a large cell size as used in the Xilinx 3000 series parts. Fig. 3 shows a logic cell according to the present invention. Figs. 4A and 4B show a two-input multiplexer and its implementation using the cell of Fig. 3. Figs. 5A and 5B show an exclusive-OR gate and its implementation using the cell of Fig. 3. Figs. 6A and 6B show an exclusive-NOR gate and its implementation using the cell of Fig. 3. Figs. 7A and 7B show a sum-of-products circuit and its implementation using the cell of Fig. 3. b Figs. 8A and 8B show a latch with clear and its implementation using the cell of Fig. 3. Figs. 8C shows the equivalent circuit formed by the circuit of Fig. 8B. Figs. 8D and 8E show a latch with clear having the opposite clock polarity from that of Figs. 8A-8C. Fig. 8F shows the equivalent circuit formed by the circuit of Fig. 8E. Figs. 9A and 9B show a set-reset latch and its implementation using the cell of Fig. 3. Figs. 10A and 10B show a 4-input AND gate with one inverted input, and its implementation using the cell of Fig. 3. Figs. 11A and 11B show an 8-input AND gate with some inverted inputs, and its implementation using two of the cells of Fig. 3 interconnected using the cascade feature. Figs. 12A-12C show a D flip flop and its implementation using two of the cells of Fig. 3 interconnected using the cascade feature, and latching using the feedback feature of the cells. Figs. 13A-13C show a JK flip flop and its implementation in three cells of Fig. 3, using the cascade and feedback functions to form the master-slave portions of the flip flop and a third cell connected through general interconnect to form the J and K functions of the flip flop. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The logic cell of Figure 3 comprises seven major sections: (1) a programmable input inverter stage 300, (2) a cascade-in first combinational stage 310, (3) a feedback first combinational stage 320, (4) a second combinational stage 330, (5) an output driver stage 340, (6) a selective global reset circuit 350, and (7) a set of configuration control units CCUl through CCU7 for controlling the configuration of the cell. Overview of the Seven Sections of Fiσ. 3 Input buffer stage 300 comprises four input buffers 301 through 304, each of which can be inverting or non-inverting as selected by the user. Providing optional inverters at every input allows the elimination of inverters at the outputs, thus combinational logic resources never need be used simply for the purpose of inverting a signal. Cascade-in first combinational stage 310 comprises a 3- input NAND gate 311 and a 2-input OR gate 312. OR gate 312 receives a cascade enable control input 313 and a cascade input 314 from an adjacent cell. OR gate 312 provides input to NAND gate 311. Also provided as input to NAND gate 311 are outputs from selectively inverting input buffers 301 and 302. Feedback first combinational stage 320 also comprises a three-input NAND gate 321 fed by output signals from selectively inverting input buffers 303 and 304. NAND gate 321 further receives input from OR gate 322 which receives on one of its input terminals a feedback signal 332 and on another input terminal a feedback enable control input 323. Second combinational stage 330 can be programmed to provide a NAND or a NOR function of outputs from the cascade combinational stages 310 and 320. Second combinational stage 330 provides an output signal 332 which can be fed back by OR gate 322 to AND gate 321, can further be provided as a cascade OUT signal which becomes a cascade IN signal to an adjacent cell, and which is provided to output driver stage 340, where it can be driven onto the interconnect structure and used as input to other cells. Output driver stage 340 includes a buffer 341 of sufficient strength to drive the output signal onto an interconnect structure represented in Fig. 3 by interconnect lines II and 12. Global reset circuit 350 allows the cell to be reset when used as a latch or flip flop. o Configuration control units CCUl through CCU7 are used for storing configuration information which configures the cell during operation. Example Implementations of the Circuits of Fiσs. 4A through 13A Shown in Fiσs. 4B through 13B Respectively Figs. 4A through 10A show some of the functions which can be implemented in a single cell of Fig. 3. Figs. 4B through 10B show the configuration control bits which are applied to the cell of Fig. 3 to implement the respective functions. It can be seen by tracing the signal path through the cell of Fig. 3 that none of the functions implemented in the cell of Fig. 3 use a signal path through an antifuse or other interconnect configuration means. Thus the cell offers fast implementation of these functions. For example, Fig. 4A shows a two-input multiplexer having two inputs INO and INl, and a select input SEL. Fig. 4B shows an implementation of this two-input multiplexer. Input INO is applied to line Al and input INl is applied to line A4. Select input SEL is applied to lines A2 and A3. A logical 0 stored in the memory cell which controls configuration control unit CCU3 causes optional inverter 301 to be noninverting. (The configuration control units are discussed in more detail below. ) Thus the value of INO is provided by optional inverter 301 to the B input of NAND gate 311. A logical 1 stored in the memory cell which controls configuration control unit CCU4 causes optional inverter 302 to invert the SEL select signal on line A2 and apply the inverted signal to the A input of NAND gate 311. The logical 0 controlling optional inverter 303 allows the SEL signal to be applied to the A input of NAND gate 321. Finally, the logical 0 controlling inverter 304 allows input INl to be passed noninverted to the B input of NAND gate 321. Three more memory cells control the cell of the invention, as represented by CCUl, CCU2 , and CCU7. A logical 0 in CCU2 is inverted at the input to OR gate 312, causing OR gate 312 to apply a high signal to NAND gate 311 regardless of the signal on line 314. Thus NAND gate 311 is configured as the logical equivalent of a two-input NAND gate, as shown in Fig. 4A. A logical 0 in CCU7, inverted at the input to NAND gate 321 disables the feedback loop, so that NAND gate 321 operates as a two-input NAND gate as shown in Fig. 4A. Finally, a logical 1 in CCUl causes second combinational stage 330 to operate as a NAND gate. Recall that by deMorgan's theorem a NAND gate with inverted inputs is equivalent to an OR gate, thus NAND gates 311 and 321 in combination with NAND gate 330 form the AND gates and OR gate shown in Fig. 4A. Thus the circuit of Fig 3 configured as shown in Fig. 4B implements the multiplexer of Fig. 4A. Implementation of XOR, XNOR, Sum-of-Products of Figs. 5A, 6A. and 7A Shown in Figs. 5B, 7B, and 7B, Respectively Figs. 5B, 6B, and 7B show the arrangement of logical 0's and l's in the seven CCUs of the cell of Fig. 3 to implement the functions shown in Figs. 5A, 6A, and 7A respectively. An understanding of these implementations can be understood from the detailed multiplexer description above. Figs. 8A through 8H: Latch with Clear Fig. 8A shows a latch with clear which can be implemented by the circuit of Fig. 3. Fig. 3 can be configured several ways to implement the static latch, however only one method will be described. As shown in Fig. 8B, the D (data) input of Fig. 8A is provided on line Al of Fig. 3. Latch enable signal LE of Fig. 8A is applied to lines A2 and A3. Optional inverter 302 is set to be inverting and optional inverter 303 is set to be noninverting. The Reset input of Fig. 8A is provided to line A4. Feedback control unit CCU7 stores a logical 1 which enables the feedback path by applying a logical 0 to the C input of OR gate 322. The Q output signal is thus fed back through the D input of OR gate 322 to NAND gate 321. AND gates AND1 and AND2 and OR gate ORl of Fig. 9A are achieved (according to DeMorgan's theorem) by configuring second combinational stage 330 as a NAND gate. Fig. 8D illustrates a latch with clear in which the latch enable signal LE has the opposite polarity of that in Fig. 8A. Both polarities are needed when sequential latches are needed, for example in a flip flop. Fig. 8E shows the implementation of the latch of Fig. 8D in the Fig. 3 circuit, and Fig. 8F shows the equivalent circuit which results. Optional inverter 302 is configured to pass the LE signal through to the A input of NAND gate 311 and optional inverter 303 is configured as an inverter, passing the complement of A3 to the A input of NAND gate 321. Set/Reset Latch Fig. 9A shows a set/reset latch which can be implemented as shown in Fig. 9B using the cell of Fig. 3. 4-Input AND Gate Figs. 10A and 10B show a 4-input AND gate with one inverted input, and its implementation using the cell of Fig. 3. Note that second combinational stage 330 is configured as a NOR gate by a logical 0 from CCUl. With the two inverted inputs (the inverted outputs of NAND gates 311 and 321) second combinational stage provides the AND function. In the example of Fig. 10A, the A2 input is inverted. Therefore, a logical 1 in CCU4 causes optional inverter 302 to act as an inverter. Clearly any combination of inverted inputs may be selected. Example Wide AND Function, Figs. 11A and 11B Using Cascade Fig. 11A shows an 8-input AND gate with inputs A2, A3, A6, and A8 inverted. As shown in Fig. 11B this 8-input AND gate is implemented using two cells of Fig. 3 connected using the cascade feature. Users may cascade more than two adjacent cells together to form wider or larger functions. Lines Al through A8 provide the eight inputs, while the AND function is provided as the X output. The logical 0 in cascade-in control unit CCU2a causes cell 7a to ignore the signal on line 314a. Optional inverter 301a is caused by a logical 0 in CCU3 to provide a noninverted version of Al. Optional inverter 302a is caused by the logical 1 in CCU4a to invert the A2 signal. Logical 1'ε at CCU5a, CCU4b, and CCU6b also cause inversion of A3, A6, and A8. Feedback control unit CCU7a provides a logical 1, which causes 320a to ignore Q output signal 332a. The logical 0 control signal from control unit CCUla causes second combinational stage 330a to provide the NOR function of stages 310a and 320a. Thus, by deMorgan's theorem, the output signal placed on line 332a is the AND function of Al through A4. Configuration control unit CCU2b carries a logical 1, which causes the cascade 332a output signal from cell 7a to be provided as input D to cascade unit 310b of cell 7b. Thus cascade unit 310b provides the NAND function of three inputs, A5, A6, and the AND output of cell 7a. Importantly, the AND output of cell 7a arrives at the input of cascade unit 310b without passing through any programmable interconnect. Thus this cascade connection reduces delay as well as saving interconnect resources. Cell 7b also has a logical 0 in CCUlb and CCU7b. The result is that the output B2 of cell 7b is an AND function of eight inputs Al through A8. In particular, B2 = Al * A7 * IT * A4 * A5 * A? * A7 * A8~ Though the cascade path connecting output line 332a to cascade-in line 314b avoids the delay of output buffer 340a and input buffer 300b, nevertheless for maximum speed of the system using a wide AND gate such as implemented in Fig. 11B it is preferable to apply signals requiring minimum delay to inputs A5-A8 because these signals will not have to be processed through two cells before reaching the output at B2. Because an extra cascade-in input signal can be used, it is not necessary to use one of the inputs A5-A8 to receive the output from 332a (the AND function of A1-A4) to compute an AND function. Thus two cells having four inputs each can be used to calculate an 8-input AND (or other) function. Without the cascade path, not only would the performance be slower and some of the interconnect resources be used up, but the two cells with together 8 inputs could only calculate a 7-input function because one input would be required for forwarding the output of the first stage. Example D Flip. Flop Figs. 12A-12C Figs. 12A, 12B, and 12C show a D flip flop and its implementation in Fig. 3. This flip flop uses two of the cells of Fig. 3, each indicated by one of the dotted lines 7a and 7b. The flip flop is formed by cascading two transparent latches; in this case, the latch of Figs. 8A-8C forms the master while the latch of Figs. 8D-8F forms the slave. The implementation shown is only one of several ways available with a pair of cells as in Fig. 3. The D input of Fig. 12A is provided on line Al of Fig. 12B. Clock input CK of Fig. 12A is provided on lines A2, A3, A6 and A7, and is inverted by buffers 302a and 303b but not by buffers 303a or 302b. Reset input R is provided on lines A4, A5, and A8, and inverted by all three of buffers 304a, 301b, and 304b. In both cells, second combinational stages 330a and 330b are configured as NAND gates. Cascade enable unit 312b carries a logical 1, enabling the output signal on line 332a from the master section of the flip flop to be passed by OR gate 312b to NAND gate 311b. Logical 1 signals from feedback control units CCU7a and CCU7b enable the internal feedback paths. Thus the circuit of Fig. 12B formed from two cells of Fig. 3 implements the D flip flop of Fig. 12A. This circuit is formed from two cells connected by a direct connect path without using the general interconnect structure, and therefore the signal path does not pass through any input or output buffers or any programmable interconnect means. Example JK Flip Flop, Figs. 13A-13C Figs. 13A-13C show a JK flip flop and its implementation. This flip flop uses three of the cells of Fig. 3, each indicated by one of the dotted lines 7a, 7b, and 7c of Fig. 13B. Cells 7b and 7c implement a D flip flop, and are configured similarly to cells 7a and 7b of Fig. 12B. Cell 7a implements a multiplexer as in Figs. 5A-5C. Connection of the multiplexer to the D flip flop occurs through the cascade connection between cells 7A and 7B as caused by the 1 in CCU2b. However a connection L7 between the first and last cells is also needed to feed the Q output back to cell 7a, and is formed using the general interconnect. Therefore general interconnect line L7 is programmably connected to output line B3 of cell 7c at programmable interconnect 171, and to cell 7a at input lines A2 and A3 at programmable interconnects 172 and 173. As with other examples, the O's and l's in each of the CCUs shows the configuration of each part of each cell to achieve the JK flip flop of Fig. 13A. Other embodiments of the invention will become obvious to those skilled in the art in light of the above description. These other embodiments are intended to fall within the scope of the present invention.

Claims: CLAIMS We claim: 1. A logic cell comprising: input buffer means for providing a signal from an interconnect structure to said logic cell; means for calculating a logic function; output buffer means for providing said logic function to said interconnect structure; and cascade means for providing said logic function as input to at least one other of said logic cells without passing through said output buffer means of said one of said logic cells. 2. A plurality of logic cells as in Claim 1, each further comprising programmable means for feeding back said logic function to an input port of said means for calculating a logic function, thereby allowing said means for calculating a logic function to be configured as a latch. 3. A plurality of logic cells as in Claim 1 in which each of said input buffer means comprises an optional inverter for selectively inverting said signal from an interconnect structure. 4. A logic cell in a logic array integrated circuit chip having a plurality of said logic cells and a plurality of interconnect lines, each logic cell comprising: a.means (A1-A4, 300) for providing a plurality of input signals to said logic cell; b.means (314, 313, 312) for selectively providing as a cascade-in signal to said logic cell a logic output signal generated by another one of said logic cells; c. a cascade-in unit (311) comprising: _ 1.means (A, B) for receiving some of said input signals, and 2.means (D, CCU2) for selectively receiving said cascade- in signal; 3.means (311) for generating a first logic function of said some of said input signals and said cascade-in signal; d.means (CCU7,322,D) for selectively providing as a feedback signal to said logic cell an output logic function of said logic cell (332); e.a feedback unit comprising: 1.means (321 A,B) for receiving remaining input signals not received by said cascade-in unit, 2.means (322 output) for receiving said feedback signal, and 3.means (321) for generating a second logic function of said remaining input signals and said feedback signal; and f.means (330) for generating said output logic function as a function of said first and second logic functions. 5. A logic cell as in claim 4 further comprising: g.means (340) for selectively providing said output logic function to one of said interconnect lines of said logic cell array. 6. A logic cell as in claim 5 in which said means for selectively providing said output logic function to one of said interconnect lines of said logic cell array comprises: a.a buffer unit comprising a plurality of serially connected inverters which receives said output logic function at ita input and provides a buffered signal representing said output logic function; b.a pass transistor for selectively providing said buffered signal to said one of said interconnect lines; and c.means for controlling said pass transistor. 7. A logic cell as in claim 6 in which said means for controlling said pass transistor is a pumped voltage supply which provides a voltage swing sufficiently wider than a voltage swing of said buffered signal that said pass transistor for selectively providing said buffered signal does not reduce the voltage swing of said buffered signal. 8. A logic cell as in claim 7 in which said pump means provides a regulated voltage which is actively held between upper and lower pumped voltage values. 9. A logic cell as in claim 10 in which said means (A1-A4, 300) for providing a plurality of input signals to said logic cell comprises means for generating selectively inverted input signals from signals present on said interconnect lines. 10. A logic cell as in claim 9 in which said means for generating selectively inverted input signals comprises: an inverter having an input terminal connectable to one of said interconnect lines and having an output terminal; a pair of complementarily controlled transistors for connecting one of said input terminal and said output terminal to said logic cell; and pump means for controlling said complementarily controlled transistors such that a signal passed by the on one of said transistors does not experience a threshold voltage drop when passing through said on transistor. _ 11. A logic cell as in claim 10 in which said pump means provides a regulated voltage which is actively held between upper and lower pumped voltage values. 12. A logic cell as in claim 4 in which said b. means (314, 313, 312) for selectively providing as a cascade-in signal to said logic cell a logic output signal generated by another one of said logic cells comprises: a two-input OR gate having a selection means as one input and said logic output signal generated by another one of said logic cells as the other input, and providing as its output signal an input signal to said cascade-in unit. 13. A logic cell as in claim 4 in which said (311) a cascade- in unit comprises a NAND gate which receives as one of its input signals an output signal from said means for selectively providing a logic output signal generated by another one of said logic cells, and as other of its input signals said some of said input signals and generates said first logic function as the NAND function of said input and cascade-in signals. 14. A logic cell as in claim 4 in which said means for selectively providing as a feedback signal to said logic cell an output logic function of said logic cell comprises a two- input OR gate having a selection means as one input and said output logic function of said logic cell as the other input, and providing as its output signal an input signal to said feedback unit. 15. A logic cell as in claim 4 in which said feedback unit comprises a NAND gate which receives as a cascade-in input signal a logic output signal generated by another one of said logic cells; receives as other of its input signals said some of said input signals; and generates said first logic function as the NAND function of said input and cascade-in signals. 16. A logic cell as in claim 4 in which said means (330) for generating said output logic function as a function of said first and second logic functions comprises: a. means for generating a NOR function; b. means for generating a NAND function; and c. means for causing said means for generating said output logic function to generate one of said NOR and NAND functions.

Inventors: GOETTING F ERICH, TRIMBERGER STEPHEN M, GOETTING, F., ERICH, TRIMBERGER, STEPHEN, M.
Applicants: XILINX INC, XILINX, INC.
Application year: 1993
Main classification: H03K19
IPC codes: H03K3, H03K19