A monolithic integrated structure of an electronic device having a predetermined unidirectional conduction threshold

Abstract: A structure of an electronic device having a predetermined unidirectional conduction threshold, being formed on a chip of an N-semiconductor material, comprises a plurality of isolated N-regions (16a-c), each bounded laterally by an isolating region (15a-c) and at the bottom by two buried P- and N-regions which form in combination a junction with a predetermined reverse conduction threshold, and means (15a,18,17b,15b,17c) of connecting the junctions of the various isolated regions serially together in the same conduction sense; the buried N-region of the first junction (Z1) in the series is connected to a common electrode (C), which also is one terminal of the device, over an internal path (R) of the N-material of the chip, and the buried P-region of the last junction (Zn) in the series contains an additional buried N-region (14d) which is connected electrically to a second terminal (18a) of the device.

Description: This invention relates to monolithic semiconductor integrated circuit structures, and in particular to a device having a predetermined unidirectional conduction threshold which is especially adapted to protect a power transistor integrated to said structure against overvoltages. Transistors, whether of the bipolar or field-effect types, are frequently used as switches to supply a load with switching currents which may be quite large. Especially where the transistor load is an inductive one, the switch breaking, that is the sudden transition from the conduction state to the cutoff state of the transistor, brings about a transient situation of overvoltage across the power terminals of the transistor, that is between its collector and emitter in the instance of a bipolar transistor or between its drain and source terminals in the instance of a field-effect transistor. This overvoltage may be several times higher than the transistor supply voltage and attain such values and durations as to exceed safe limits set by the structural characteristics of the transistor, to the point that the transistor may be destroyed. A known practice for protecting a bipolar transistor in such circumstances is to connect, between the collector and the base of the transistor, a device with a predetermined unidirectional conduction threshold, such as a Zener diode having a lower reverse breakdown voltage than the breakdown voltage between the transistor collector and emitter, with the base open or floating, referred to as BV ceo . As the collector/emitter voltage increases due to the transition from the conduction to the cutoff state up to the reverse conduction value of the Zener, a current is injected into the transistor base. The latter is, therefore, restored to conduction and discharges the energy stored in the inductive load on itself. Of course, the transistor should be sized to absorb such energy harmlessly. The maximum overvoltage between the collector and the emitter would equal here the breakdown or reverse conduction threshold voltage of the Zener diode plus the transistor base/emitter forward voltage. A similar device to the above-described one is used to protect a field-effect power transistor, such as a vertical MOSFET, against overvoltages across the source and drain terminals. But in this case the structure is somewhat different, because a diode with opposite polarity from that of the Zener diode must be connected in series with the Zener diode connected between the gate and drain terminals. In fact, the gate terminal voltage may exceed by some 10-15 volts the drain terminal voltage in normal operation of the transistor, so that a Zener diode connected directly between the gate and the drain would disallow such operating conditions because it would be in forward conduction the very moment that the gate/drain voltage exceeds the forward conduction threshold (typically 0.7 volts at the silicon) of the Zener diode. It is recognized that, to provide a protection device of the aforesaid kind, one may use, for the predetermined conduction threshold component, an open-base bipolar transistor connected between the emitter and the collector by utilizing the base punch-through effect, or use a diode which, while not being operated on Zener's effect, has a conduction characteristic similar to that of a Zener diode, i.e. a non-destructive reverse breakdown voltage having a predetermined threshold, like most of the diodes including an avalanche reverse breakdown junction. If necessary, instead of a single Zener diode or its equivalent, there may be connected in series several, until the desired threshold voltage for protection is attained. The need for this may arise where the protection device is to be implemented in a monolithic integrated structure within a well-defined manufacturing process and the latter is not to be altered by the addition of specific steps directed to form a diode with the reverse breakdown characteristics sought; that is, it is preferred to connect in series several junctions which can be easily obtained by the standard process. In this case, however, the serial resistance of the protection device in conduction may be comparatively high, which is apt to impair the protection effectiveness, especially where the transistor to be protected is a bipolar one. To obviate this problem, it has been known to use an additional bipolar transistor serving as a current amplifier. That transistor, as shown at T1 in Figure 1 of the accompanying drawings, has its collector in common with the collector of the transistor to be protected; the latter being in this example the power transistor T2 of an NPN Darlington pair whose drive transistor is designated T3. Further, the transistor T1 has its emitter connected to the base of the power transistor T2 and its base connected to the anode of the first Zener diode Zn in a chain of n Zener diodes Z1, Z2 ..., Zn connected, with the other end, to the common collectors of the transistors. An integrated protection device useful especially with a MOSFET transistor is disclosed in German Patent Application DE 4,122,347. The circuit diagram of that device is shown in Figure 2 of the accompanying drawings applied to an N-channel MOSFET transistor indicated at T4. The component with Zener diode function, i.e. with predetermined reverse breakdown unidirectional conduction, is represented there by a series of n Zener diodes Z1, Z2..., Zn to indicate that it is formed from n junctions connected serially together. Thus, an overall breakdown or reverse conduction voltage is obtained which is a multiple of that to be obtained with a single junction formed by the particular manufacturing process adopted. As may be seen, provided in series with the diodes Z1-Zn is a diode D1 connected in reverse polarity with respect to the Zener diodes in order to inhibit forward conduction between the gate G and the drain D. However, that prior structure cannot provide accurate and repeatable reverse conduction threshold voltages because the junctions of the component diodes are formed between diffused regions, and accordingly, with a reverse breakdown which is not to be accurately foreseen, as is well known. In addition, its dimensioning is fairly critical due to the risk of parasitic effects between components of the device, and is unsuited to applications where the protection device is integrated along with control circuits for the power transistor to be protected. It is the object of this invention to provide a monolithic integrated structure of a predetermined unidirectional conduction threshold device, particularly for protecting a power transistor, wherein the threshold voltage can be defined accurately and repeatably, wherein optimum isolation from the other circuit components can be provided, and which can be integrated without having recourse to additional steps, along with a power transistor and associated control circuit. This object is achieved according to the invention by the structure as defined in claims 1 and 9. The invention can be more clearly understood from the following detailed description of an exemplary, and in no way limitative, embodiment thereof, to be taken in conjunction with the accompanying drawings, in which: Figures 1 and 2, as already described, show two circuit diagrams of devices which can be implemented in integrated structures according to the invention; and Figures 3, 4 and 5 are sectional views of three integrated structures according to the invention. The structure shown in Figure 3 reproduces the circuit of Figure 1 in integrated form on a chip of a semiconductor material such as monocrystalline silicon. It is advantageously formed by a manufacturing process called "VIPower", an Applicant's trade mark. That process is specially directed to provide integrated structures comprising power transistors and signal processing circuits for controlling power transistors. The drive transistor T3 of the Darlington pair has been omitted from Figure 3 of the drawings for simplicity; in practice, it would have a similar configuration to that of the power transistor T2. The structure is formed, through conventional steps of the VIPower process, on a monocrystalline silicon substrate 10 which is heavily doped with impurities of the N type. Notice that, in the drawing, the relative concentrations of impurities of the N and P types are customarily indicated by adding "-" and "+" symbols to the characters N and P; characters N and P carrying no "-" or "+" suffix denote concentrations at intermediate values. Formed on the substrate 10 by epitaxial growth is a first layer 11 having the same type of N conductivity but a lower concentration of impurities. On the surface of the epitaxial layer 11 there are implanted regions of the P type having a comparatively low concentration of impurities, and subsequently, regions of the N type having a high concentration of impurities substantially within the P-type regions. A second layer 12 of the N type having a higher concentration of impurities than the first layer 11 is formed on the layer 11 by epitaxial growth. In this step, which is carried out at a high temperature, the implanted regions of the P type and N type extend by diffusion through the two epitaxial layers to create buried regions denoted in the drawing by 13a-d and 14a-e, respectively. Formed then in the second layer 11 by conventional masking and diffusing techniques, are P-type regions having a high concentration of impurities, as shown at 15a-d, which extend through the second epitaxial layer 12 and partway penetrate the first 11 to join the regions 13a-d, as shown in the drawing. Notice that the regions 15a-d have in plan view the shape of a picture frame and will, therefore, bound mutually isolated portions of the second epitaxial layer 12 which are closed at the bottom by the regions 13a-d and 14a-e, thereby forming a plurality of N type wells 16a-d which are isolated from one another. By similar techniques N-type regions 17b-e having a high concentration of impurities and which are extended to join some of the buried regions 14a-e of the N type are then formed within some of the wells 16a-d. Metallic paths are then formed using conventional deposition, masking, and etching techniques to selectively interconnect, by an ohmic contact on the large surface of the silicon chip thus formed, the regions 15a-d and 17b-d, and provide further connections and metallized areas of ohmic contact, such as those indicated at E and B in the drawing. The free surface of the substrate is also covered with a metallic layer 19 which constitutes a terminal, indicated at C, shared in common by several device components. The resultant structure includes the power transistor T2, being a vertical bipolar transistor of the NPN type which has the common terminal C as its collector terminal, the terminal E contacting the region 17e which establishes a deep contact with the buried region 14e of the N type as its emitter terminal, and the terminal B contacting the buried region 13d of the P type through the isolating region 15d of the P type as its base terminal. The buried region 13d forms, together with the buried region 14e of the N type, the emitter junction of the transistor, and with the first epitaxial layer 11, the collector junction of the transistor. In the drawing, the power transistor T2 is represented as a single element formed in a well 16. In actual practice, however, it would be frequently composed of a number of elements, equal to that shown and connected together in parallel. The chain of Zener diodes Z1--Zn in Figure 1 is implemented in the structure of Figure 3 as a series of junctions between buried regions 13a-c of the P type and buried regions 14a-c of the N type, each having a predetermined breakdown, or reverse conduction threshold, voltage. The individual junctions are interconnected together by joining opposite type regions of different junctions such that the anode of each basic diode is connected to the cathode of the next; thus, the voltage at which the diode chain reverse conduction will occur is given by the sum of the breakdown voltages of the individual junctions. Notice that, in a specially advantageous embodiment of the invention, the cathode of the first element Z1 in the chain, i.e. the buried region 14a of the N type, is connected to the common terminal C, directly to the structure interior through an aperture 30 in the respective buried region 13a of the P type. This is, therefore, a resistive connection, denoted by R, through the first epitaxial layer 11 and the substrate 10. The elemental diodes after the first (Z1) use, for cathode connection, each a deep contact region 17b,c of the N type and a section of metallic surface path 18 in contact with the surface of the P-type region 15a,b of its preceding diode. Shown at Z2 in the drawing is just one of those intermediate diodes. It is understood that the number of the diodes like Z2 is determined by the value of the overall reverse conduction threshold voltage sought. As an example, in a practical embodiment of the structure, four equal diodes have been formed which have a reverse conduction voltage of 85 V. The last of the elemental diodes, indicated at Zn, has no external electric connection between its anode and the remainder of the circuit, i.e. the base of the additional transistor T1, but is integrated into a single structure with the latter. Specifically, the transistor T1 is implemented using for the base region the P-type region 13c which acts as the diode Zn anode, and forming its emitter junction from an additional buried region 14d of the N type provided in the buried region 13c. The emitter contact is provided by an additional deep region 17d of the N type, and the collector contact is the common terminal C. One of the paths 18, denoted by 18a, joins the emitter of transistor T1 to the base of the power transistor T2. Both buried regions of the N type, 17c and 17d, which form the diode Zn cathode and the transistor T1 emitter, have the same concentration of impurities where, as in the example described, they are merely formed by the available steps of the VIPower process. If necessary and in view of the current required to drive the power transistor T2, however, the horizontal extent or area of the emitter region 14d of T1 may conveniently be greater than that of the cathode region Zn. An advantageous feature of the inventive structure is that all the junctions of the diode Z1-Zn are formed by implanted regions (13a-c and 14a-c), so that the reverse conduction threshold can be set with great accuracy and is little affected by normal fluctuations in the process parameters, as against prior structures which employ junctions between regions doped by deposition and diffusion which, as is recognized, produce breakdown voltages tightly dependent on the process parameters. Another advantageous feature is that all the junctions of the protection device but that of the first diode Z1 are completely isolated from one another and from other components because they are buried junctions contained within isolated wells. Thus, no parasitic effects occur which may detract from the protection effectiveness. The one partial departure from this isolated condition concerns the first junction in the diode chain Z1-Zn which, however, is no cause of harmful parasitic effects and represents an effective way of connecting the cathode of said first diode to the common terminal C. As mentioned, the above-described protection device is made using standard steps of the VIPower process for manufacturing complex structures comprising a power component and a low-voltage control circuit for the power component. An example of a structure of this kind is illustrated by Figure 4, where along with a bipolar power transistor T2 and a protection device like that just described, there are shown two typical components of a control circuit, namely a low-voltage vertical NPN transistor T5 and a lateral PNP transistor T6. As can be seen, the epitaxial wells bound by the P-type buried regions and the P-type isolation regions of the transistors are formed by the same process steps as are required to form the like epitaxial wells containing the junctions of the diode Z1-Zn. Additional masking and doping steps are provided to jointly form the base region 20 of the bipolar transistor T5 and the emitter and collector regions 39 of the lateral PNP transistor T6, and to jointly form the deep collector contact 31 of the bipolar transistor T5 and the deep base contact 32 of the lateral transistor T6, as well as the emitter, shown at 33, of the vertical transistor T5. Shown in Figure 5 is an integrated structure wherein a protection device according to the invention is applied to a vertical construction, N-channel MOSFET power transistor T4. The manufacturing process is the same as that described above in connection with the bipolar structure, up to the step of diffusing the regions 17b-e of the N type. Subsequently, a P-type region, shown at 20 in Figure 5, is implanted and diffused which constitutes the so called deep body of the transistor. The gate electrode 25 of polycrystalline silicon is formed next which is isolated from the chip surface by an appropriate gate dielectric, not shown. Then, a P-type region 19 is formed, with a lower impurity concentration than that of region 20, to provide the transistor body. During the last-named step, the base regions of any low-voltage vertical NPN bipolar transistors T5 and the emitters and collectors of any lateral PNP transistors T6 are also formed. N-type regions 22 are then formed which constitute the source of the MOSFET transistor, and simultaneously therewith, the emitter regions of the low-voltage NPN transistors. A metallic connection path 23 is finally formed along with the interconnection paths for the protection device, as described already in relation to Figure 3, in order to connect the gate electrode 25 to the emitter of the additional transistor T1. The drain electrode D is coincident with the common terminal C of the structure. The circuit diagram representing the above-described structure is basically the same as in Figure 2, where the diode D1 constitutes the emitter junction of transistor T1. While one embodiment of the invention has only been described, it will be appreciated that several changes and modifications may be made thereunto within the scope of the same inventive concept. As an example, the predetermined unidirectional conduction threshold device could include a single junction, rather than several junctions connected in series; in this case, the structure would include a single isolated well bound on the bottom by a P-type region shaped similar to the region 13a in Figure 3 and having an additional buried region of the N type, such as the region 14a in that Figure. It is understood, moreover, that complementary structures of that described may be provided using materials and regions of the P type instead of the N-type ones, and vice versa.

Claims: An integrated structure of an electronic device having a predetermined threshold for the unidirectional conduction between a first (C) and a second (18a) terminal thereof, said structure being formed on a semiconductor material chip of the N conductivity type (11, 12, 10) and comprises: an isolated region (16c) of the N type which extends into the chip from the top surface of the chip and is isolated laterally from the rest of the chip by an isolating region (15c) of the P+ type and is bounded at the bottom by a buried region (13c) of the P- type and by first (14c) and second (14d) buried regions of the N+ type, said first and second buried regions of the N+ type being laterally separated from each other and extending from said buried region of the P- type to said isolated region of the N type (16c), said first (14c) and second (14d) buried regions of the N+ type forming with the buried region (13c) of the P- type a first and a second junction, respectively, the buried region (13c) of the P- type being joined to the isolating region of the P+ type (15c), the first junction defining an elemental diode (Zn) and the unidirectional conduction comprising the reverse conduction through the elemental diode; a first electric connection means (17c, 18; R) connecting the first buried region (14c) of the N+ type to the first terminal (C) of the device; and a second electric connection means (17d) connecting the second buried region (14d) of the N+ type to the second terminal (B) of the device. An integrated structure according to Claim 1, wherein the first terminal (C) of the device is formed on the surface opposite from the top surface, and the buried region of the P- type is shaped such that the first buried region of the N+ type is in contact with the N-type material (11) of the chip outside the isolated region, whereby the portion (R) of the N-type material included between the first buried region (14a) of the N+ type and the first terminal (C) of the device is a part of the first electric connection means. An integrated structure according to Claim 1 or 2, wherein the second electric connection means comprises a deep contact region (17d) extending from the top surface of the chip to the second buried region (14d) of the N+ type. An integrated circuit according to claim 1 comprising at least one further isolated region (16b) of the N type which extends into the chip from the top surface of the chip and is isolated laterally from the rest of the chip by a further isolating region (15b, 15a) of the P+type and is bounded at the bottom by a further buried region (13b, 13a) of the P-type and by a third buried region (14b, 14a) of the N+type, said third buried region forming with the further buried region a third junction, the further buried region (13b, 13a) being joined to the further isolating region (15b, 15a) of the P+ type, the third junction defining a further elemental diode (Z2,Z1) and the unidirectional conduction comprising the reverse conduction through the further elemental diode; a first contact means (17b) contacting the third buried region (14b) and being a first terminal of the further elemental diode, a second contact means (15b) contacting the further buried region (13b) and being a second terminal of the further elemental diode, said first electric connection means (17c, 18; R) comprising a series connection of at least one of said further elemental diode in the reverse conduction direction. An integrated structure according to Claim 4, wherein the second contact means (15b) comprises the further isolating region (15b). An integrated structure according to Claim 4 or 5, wherein the first terminal (C) of the device is formed on the surface opposite from the top surface; and the further buried region (13a) of the P- type of that elemental diode which is the first in the series connection starting from the first terminal (C) of the device is shaped such that the third buried region (14a) of the N+ type is in contact with the N-type material (11) of the chip outside its respective further isolated region (16a), whereby the portion (R) of the N-type material included between that third buried region (14a) of the N+ type and the first terminal (C) of the device is a part of the first electric connection means. An integrated structure according to Claim 4, 5 or 6, comprising a deep contact region (17d) extending from the top surface of the chip to the second buried region (14d) of the N+ type. An integrated structure according to any of the preceding claims, wherein the first and second connection means comprise metallic paths (18, 18a) extending across the top surface of the chip, An integrated structure of an electronic device having a predetermined threshold for the unidirectional conduction between a first (C) and a second (18a) terminal thereof, said structure being formed on a semiconductor material chip of the P conductivity type (11, 12, 10) and comprises: an isolated region (16c) of the P type which extends into the chip from the top surface of the chip and is isolated laterally from the rest of the chip by an isolating region (15c) of the N+ type and is bounded at the bottom by a buried region (13c) of the N- type and by first (14c) and second (14d) buried regions of the P+ type, said first and second buried regions of the P+ type being laterally separated from each other and extending from said buried region of the N- type to said isolated region of the P type (16c), said first (14c) and second (14d) buried regions of the P+ type forming with the buried region (13c) of the N- type a first and a second junction, respectively, the buried region (13c) of the N- type being joined to the isolating region of the N+ type (15c), the first junction defining an elemental diode (Zn) and the unidirectional conduction comprising the reverse conduction through the elemental diode; a first electric connection means (17c, 18; R) connecting the first buried region (14c) of the P+ type to the first terminal (C) of the device; and a second electric connection means (17d) connecting the second buried region (14d) of the P+ type to the second terminal of the device. An integrated structure as claimed in any of the preceding claims comprising a protection device against overvoltages between the collector (C) and the emitter (E) terminals of a bipolar power transistor (T2), wherein said first and second terminals of the device are terminals of the protection device and are respectively connected to the collector terminal (C) and the base terminal (B) of the bipolar power transistor (T2). An integrated structure as claimed in any of Claims 1 to 9 comprising a protection device against overvoltages between the drain (D) and the source (S) terminals of a field-effect power transistor (T4), wherein said first and second terminals of the device are terminals of the protection device and are connected to the drain (D) and the gate (G) terminal through a diode (D1) connected in a reverse polarity with respect to the elemental diodes of the protection device.

Inventors: PALARA SERGIO, PALARA, SERGIO
Applicants: CONS RIC MICROELETTRONICA, CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1993
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21