Raised feature on substrate for flip chip interconnection

Abstract: An integrated circuit chip (26, 34) is connected to a circuit trace by providing a raised feature on a circuit trace (17, 28) which is coated with a material capable of forming an electrical connection (23, 32), as well as an attachment when the pad (25, 33) of an integrated circuit chip (26, 34) is brought into engagement with it. This material may be solder (23) or it may be a Z-axis adhesive (32) which becomes conductive at areas where it is compressed. The raised feature or bump (18, 31) on the circuit trace (17, 28) may be produced by providing a mandrel (10) having a recess (12) complementary to the raised feature (18, 31) to be provided, and suitably plating the circuit trace (17, 28) on the mandrel (10) including the recessed area (12). Upon subsequent lamination of a dielectric layer (19, 30) and removal from the mandrel (10), there is produced a circuit trace (17, 28) on a dielectric with a raised feature (18, 31) which can be used to attach to an integrated circuit chip (26, 34).

Description: This invention pertains to the connection of integrated circuit chips in an electrical circuit. Conventional techniques for attaching integrated circuit chips to circuit traces on a printed circuit board or flexible conductor take up a considerable amount of space so that the chips cannot be positioned as close to each other as desired for many installations. A high density of chips may be essential in an increasing number of electrical circuits. In conventional chip attachment a chip is positioned on a substrate with its pads facing outwardly and wires are extended between the pads of the chip and the circuit traces or pads on the substrate. Obviously, space must be provided around the chip to accommodate the connecting wires. In order to alleviate this problem what is known as the flip chip or controlled collapse chip connection has been devised. In this arrangement, solder bumps are plated onto the pads of the integrated circuit chip. The chip then is inverted with its pads positioned over and pressed against the circuit traces. Upon melting and fusion of the solder, connections can be achieved. This successfully increases the permissible density of the chips on a substrate, but has serious drawbacks. Unless all of the solder bumps on the chip properly engage the corresponding circuit traces, a solder joint will not be achieved. When this occurs, it becomes necessary to scrap the part. The solder bumps are destroyed upon heating and cannot be reworked. For multichip modules it may then become necessary to discard a very expensive component which has had a number of prior operations performed on it before the attempted connection of the chip. Inasmuch as it is impossible to achieve complete assurance that all of the chips will bond properly in the normal flip chip operation, the expense may become prohibitive for multichip modules. Also, it is necessary to apply the solder to the chip at wafer level of fabrication. Not all chip manufacturers are willing to supply chips with solder bumps, and some manufacturing methods preclude solder bumps at all. Thus only a limited number of chips are available for flip chip. To use flip chip methods, all the chips on a module should be attached via flip chip. If some of the chips are not available with solder bumps, then it may not be economical to use flip chip processing at all. Similar problems are encountered when posts are formed on the chip pad or when bumps are provided with tape automated bonding. GB-A-1197272 describes methods of connecting integrated circuits, in which an insulating support substrate is provided with mounting pillars having conductive traces extending from the top of the mounting pillars, and the contact pads of the integrated circuit are bonded to respective conductive traces at the top of the mounting pillars by ultrasonic or thermo-compression techniques. US-A-4056681 describes a self aligning integrated circuit package, including an integrated circuit die having raised contact pads mounted to an interconnecting die in flip chip fashion. The present invention provides a method of connecting a conductor to an integrated circuit chip comprising the steps of: forming a circuit trace on a dielectric substrate such that said circuit trace includes at least one raised feature; positioning the integrated circuit chip so that its pad engages said raised feature; and securing said pad to said raised feature by a conductive material interposed between said pad and said raised feature, characterized in that said conductive material is a Z-axis conductive adhesive applied to said raised feature, and said integrated circuit chip is biased toward said raised feature so as to cause compression of said Z-axis conductive adhesive at said raised feature while said Z-axis conductive adhesive becomes cured to bond said pad to said raised feature, thereby to cause said Z-axis conductive adhesive to become electrically conductive only at said raised feature, and further characterized in that the step of forming said circuit trace comprises forming a mandrel having a recess therein, forming said circuit trace on said mandrel and in said recess, laminating a dielectric material to said circuit trace so formed, and removing said dielectric material and said circuit trace from said mandrel with said circuit trace which was formed in said recess defining said raised feature of said circuit trace. In accordance with this invention, the circuit trace on the dielectric substrate is prepared generally in the manner set out in patent applications EP-A-0476868 and EP-A-0529578. In accordance with the invention, a mandrel is provided which includes a flat surface in which is formed a depression or recess which has a contour complementary to that of a raised feature to be produced. A flash copper plating is preferably applied over the mandrel surface including the surface of the recess. After this, a photoresist, which is the negative of a circuit to be produced, is preferably applied over the flash copper plating and copper is electroplated into the spaces in the photoresist to result in an electrical circuit. The resist then is removed, a dielectric layer is laminated over the copper and the assembly is separated from the mandrel. The flash copper layer then is etched away to leave a completed circuit on a dielectric substrate. In accordance with the present invention, a Z-axis conductive adhesive material is provided on the raised features or bumps which can both attach to an integrated circuit pad and also provide electrical conductivity. This type of adhesive contains metal particles which, upon compression, become interengaged so as to create an electrical conductor. The chip is pressed down onto the bump to which the adhesive has been applied so that upon curing of the adhesive there will be an electrical connection at the pad and a bonding, as well. In the accompanying drawings: FIGS. 1 through 10 are sectional views that illustrate a sequence of steps in the preparation of circuit traces on a substrate and the attachment of an integrated circuit chip in accordance with this invention; and FIG. 11 is a view of a variation of the attachment by an adhesive. In attaching an integrated circuit chip in an electrical circuit in accordance with this invention there are first provided raised features on a substrate. This may be accomplished through the use of a mandrel 10 of stainless steel, having a flat upper surface 11, as seen in FIG. 1. At least one localized depression 12 is formed in the surface 11 and made complementary to the raised feature that is to be provided. The recess 12 is illustrated as dome-shaped but it may be given any desired contour. Next, there is provided over the surface 11 and within the recess 12 a continuous copper coating 13, as shown in FIG. 2. This is a thin electroplated flash coating of a thickness of about 5 µm (.2 mil). After this, a photoresist 14 is applied over the flash coating 13, leaving spaces 15 which correspond to an electrical circuit to be produced. The spaces 15 include the recess 12. Then, copper is electroplated in the spaces 15 over the flash coating 13 (FIG. 4). The result is to provide circuit trace 17 as well as what will become a raised feature or bump 18 at the recess 12. The photoresist 14 then is stripped away, leaving only the electroplated circuit traces 17 and the bump or raised feature 18, as well as the flash copper plating 13, on the mandrel 10 (FIG. 5). After this, a dielectric layer 19 is laminated to the circuit traces 17, raised feature 18 and the exposed flash copper plating 13 on the mandrel 10 as seen in FIG. 6. The dielectric layer 19 may be, for example, a Kapton and adhesive, laminated under elevated temperature and pressure conditions so that the adhesive will flow around the circuit traces and the raised features covering their exposed sides. The assembly 21 of the dielectric layer along with the electroplated copper 17 and 18 and the flash copper layer 13 then is removed from the mandrel 10 (FIG. 7). This separation is made possible by the flash copper layer 13 which does not permanently adhere to the surface of the stainless steel mandrel 11. Otherwise, the dielectric layer of Kapton and adhesive would become bonded to the mandrel and could not be removed. The next step is to flash-etch the assembly to remove the thin copper layer 13. The bumps on the substrate are attached to the pads on the chip by a Z-axis conductive adhesive, which is available as a liquid or a film, rather than solder. Such an anisotropically electrically conductive adhesive is available from several sources. As shown in FIG. 9, when the pitch of the chip pads is small, a Z-axis conductive adhesive 32 is applied as a liquid over the entire exposed surface of the assembly. Alternatively, the pad 33 of the chip 34 may be coated. A chip 34 then is pressed against the assembly so that the pad 33 of the chip bears against the adhesive 32 on the bump 18 as the adhesive is cured. With the chip 34 being forced toward the bump 18, compression of the Z-axis adhesive 32 will occur only at the point of engagement of the chip, namely, at the pad 33. The remainder of the adhesive 32 is not compressed. As a result, the Z-axis adhesive 32 becomes conductive at the bump 18, but remains nonconductive elsewhere. Consequently, a circuit is completed between the chip 34 and the circuit traces 17. When there is lesser density of the chip pads, a coverlay 36 may be applied over the assembly, as seen in FIG. 13, leaving the bump 18 exposed. The Z-axis adhesive 32 then is applied only at the exposed bump 18 to avoid using excess adhesive. The chip then is pressed against the exposed bump, as described above, compressing the adhesive only at that localized area to both attach the chip to the circuit and to produce an electrical connection.

Claims: A method of connecting a conductor to an integrated circuit chip (34) comprising the steps of: forming a circuit trace (17) on a dielectric substrate (19) such that said circuit trace (17) includes at least one raised feature (18); positioning the integrated circuit chip (34) so that its pad (33) engages said raised feature (18); and securing said pad (33) to said raised feature (18) by a conductive material (32) interposed between said pad and said raised feature; characterised in that said conductive material (32) is a Z-axis conductive adhesive applied to said raised feature (18), and said integrated circuit chip (34) is biased toward said raised feature (18) so as to cause compression of said Z-axis conductive adhesive at said raised feature (18) while said Z-axis conductive adhesive becomes cured to bond said pad (33) to said raised feature (18), thereby to cause said Z-axis conductive adhesive to become electrically conductive only at said raised feature; and further characterized in that the step of forming said circuit trace (17) comprises forming a mandrel (10) having a recess (12) therein, forming said circuit trace (17) on said mandrel and in said recess, laminating a dielectric material to said circuit trace (17) so formed, said dielectric material forming said dieletric substrate (19), and removing said dielectric material and said circuit trace (17) from said mandrel (10) with said circuit trace (17) which was formed in said recess (12) defining said raised feature (18) of said circuit trace. A method according to claim 1 in which said Z-axis conductive adhesive is also applied to portions of said circuit trace (17) remote from said raised feature (18). A method according to claim 1 in which said Z-axis conductive adhesive is applied only to said raised feature (18), and a coverlay is applied over other portions of said circuit trace. A method according to claim 1, 2 or 3 including the step of applying to said mandrel (10) a coating (13) of a material capable of separation therefrom prior to said forming of said circuit trace on said mandrel (10) and said lamination of said dielectric material (19) to said circuit trace (17). A method according to claim 4, wherein the coating (13) is a thin coating of copper, said coating (13) being removed from said raised feature (18) prior to applying said Z-axis conductive adhesive thereto. A method according to claim 5 in which said thin coating (13) of copper is formed on said mandrel (10) by electroplating. A method according to claim 4, 5 or 6 in which said thin coating (13) is removed from said raised feature (18) by etching. A method according to claim 1 in which said circuit trace (17) is formed on said mandrel by electroplating. A method according to any of claims 4 to 8, in which for forming said circuit trace (17) a resist (14) is photolithographically formed over said coating except for spaces where said circuit trace (17) is to be formed, copper material is electroplated onto said mandrel (10) at said spaces, and then said resist (14) is removed.

Inventors: CRUMLY WILLIAM R, FEIGENBAUM HAIM, CRUMLY, WILLIAM R., FEIGENBAUM, HAIM
Applicants: HUGHES AIRCRAFT CO, HUGHES AIRCRAFT COMPANY
Application year: 1993
Main classification: H01L23
IPC codes: H05K3, H01L23, H01L21, H05K1