Semiconductor memory with memory matrix comprising redundancy cell columns associated with single matrix sectors

Abstract: There is described a semiconductor memory comprising a matrix of lines and columns of memory cells, wherein the columns (BL) are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets (1) of columns, and there are redundancy columns (BLR) suitable for replacing a matrix column (BL) containing defective memory cells. Each of the redundancy columns (BLR) is included in a respective packet (1). The memory also comprises control circuits (5,6,7) to execute the abovementioned replacement.

Description: The present invention relates to a semiconductor memory with memory matrix comprising redundancy cell columns associated with single matrix sectors. In the manufacture of semiconductor memories defects are frequently encountered that afflict a limited number of cells of the memory matrix. The reason for the high probability of defects of this type resides in the fact that in a semiconductor memory chip the greater part of the area is occupied by the matrix of memory cells itself. In order to avoid that the presence of a limited number of defective memory cells on many millions force the rejection of the entire chip, the technique is known of providing for the manufacture of a certain number of additional memory cells, commonly called "redundancy cells", to be used as a replacement of those cells that, during testing of the integrated component, prove defective; the circuits, with which the integrated component must of necessity be provided, designed to operate the abovementioned functional replacement of a defective cell with a redundancy cell are indicated as a whole with the name of "redundancy circuits", while the set of redundancy cells and circuits are defined for short as "redundancy". Since semiconductor memories are organized in matrix structures wherein the single memory cells are located at the intersection of rows (known as "word lines") and of columns (known as "bit lines") of the matrix itself, what takes place in practice is the replacement of those rows or of those columns containing defective cells with as many rows or columns of redundancy cells (known as "redundancy rows" and "redundancy columns", respectively), storing the configuration of address signals corresponding to each defective line or column in special non-volatile memory registers (for example, fuses, or programmable but non-erasable memory cells) so that whenever said combination of signals shows up again at the input of the integrated component the replacement is automatically executed and, instead of accessing the defective cells, access is gained to the redundancy cells that replace them. A first embodiment of redundancy provides for the presence of groups of redundancy bit lines, where each of these groups is associated with a respective sector of the memory matrix, comprising a given number of bit lines of memory cells, constituting the portion of the memory matrix itself related to a data input/output Line of the integrated component. For the purposes of the selection of a particular bit line, each of the abovementioned sectors is generally in turn divided into packets of bit lines, say eight packets of eight bit lines each for a total of 64 bit lines in each sector. The selection of a given bit line among the 64 bit lines constituting a sector is executed by means of a twin-level decoding of the address signals: one among eight signals known as being of the first level is triggered to select one among the eight bit lines of each packet, while the triggering of one among eight signals known as being of the second level allows the selection of one among the eight packets. Said first- and second-level signals generally drive transistors that are placed in series with the bit lines and that connect the latter to the reading circuit of the memory cells. In this type of embodiment the selection of one of the redundancy bit lines is also executed by means of two levels of selection signals, where signals of the first level execute the selection of a redundancy bit line among those constituting one group, while a single second-level signal allows the connection of the group of redundancy bit lines to the reading circuit. The redundancy circuits proceed with the triggering of these first- and second-level signals related to the redundancy bit lines, and at the same time they inhibit the triggering of the signals for the selection of the bit line of the matrix containing the defective memory cell. An architecture such as the one described poses some problems, however, in the design of the integrated circuit layout. In order to programme the memory cells, in fact, with each of the abovementioned packets of matrix bit lines, as well as with the redundancy bit lines, there is associated a programming loading circuit, comprising a transistor that, depending on the data to be stored in the single memory cell, connects the bit line selected by the first-level signals to a programming voltage. Since the current required by the memory cell for its programming is generally fairly high, the size of said transistor is consequently fairly substantial. This circumstance does not present particular problems for transistors associated with packets of matrix bit lines, where the pitch between two of these transistors is, say, of eight bit lines; since, however, a group of redundancy bit lines is generally constituted by a smaller number of bit lines, the space available for the design of the corresponding programming transistor is restricted, and it is necessary to introduce irregularities in its size or in its design. A second type of embodiment is known, wherein with the entire complex of the packets of matrix bit lines and of the group of redundancy bit lines there is associated a single loading circuit, of the type described earlier. It is evident that in this second type of architecture the problems that are found in the first type of architecture described do not obtain, since the pitch between two successive programming transistors consists of many bit lines. But in this case the programming transistor is no longer connected to the selected bit line through the first-level selection transistor only, but, rather, through the connection of the latter to the second-level selection transistor. This allows a limited regulation of the programming voltage across the drain of the memory cell to be programmed, due to the additional drop in voltage across the second-level selection transistor. Moreover, in order to limit this additional drop in voltage across the second-level selection transistor, it is necessary for the second-level selection signal to have a value that is higher than the programming voltage, with the consequent complication of the decoding circuits. Lastly, since in order to speed up testing operations it is usual to programme several bits simultaneously, the programming transistor must, in this second architecture, be able to drive a multiple number of bit lines simultaneously; this means that its size must be larger than that of a programming transistor for architectures of the type described earlier, and layout problems may arise. In EP-A-0 472 209 a semiconductor memory device is disclosed having redundant circuit, substantially as described in the preamble of claim 1. In view of the described state of the art, the object of the present invention is to manufacture a semiconductor memory with a matrix architecture such that the abovementioned problems are not introduced in redundancy operations. According to the present invention, such object is attained thanks to a semiconductor memory, comprising a matrix of memory cells located at the intersection of rows and columns of the matrix, which further includes the features of the characterizing clause of claim 1. It has been possible to observe that thanks to the present invention it is possible to manufacture matrices of memory cell in which it is no longer necessary to provide specific loading circuits for programming the cells of redundancy columns, as the latter are connected to the loading circuit of a packet of columns. This has a substantial benefit from the viewpoint of the layout of the memory matrix. These and other features of the present invention shall be made more evident by the following detailed description of one of its embodiments illustrated as a non-limiting example in the enclosed drawings, wherein: Fig. 1 shows a sector of a memory matrix for a semiconductor memory according to the invention; Fig. 2 shows a block diagramme of the circuits constituting the selection means of a packet of bit lines belonging to said sector of a memory matrix. There is illustrated in Fig. 1 a memory sector that represents the portion of a matrix of memory cells related to a data input/output line, and is divided in a given number of packets 1 of columns or bit lines, say eight. Each of the packets 1 consists in turn of matrix bit lines BL, say in the number of eight, and of one redundancy bit line BLR; it follows that each sector consists of 64 + 8 bit lines. Within each packet 1, in series with each bit line BL there is a transistor MS for the selection of the bit line BL, say of the n-channel MOS type whose source is connected to the bit line BL itself; the redundancy bit line BLR is in turn connected to the source of a transistor MSR for the selection of the redundancy bit line BLR itself. The drains of the transistors MS amd MSR of any one packet 1 are shortcircuited one to the other, while their gates are connected to eight signals YN0-YN7 and to a signal YNR, respectively, the first coming from the circuit for decoding the address signals (not shown in the figures), the second generated by a circuit 6 for recognizing the address signals corresponding to defective memory cells (Fig. 2); the eight signals YN0-YN7 and the signal YNR constitute a first level of selection. To the common drain of the transistors MS amd MSR of any one packet 1 there is also connected the source of a transistor MSP for the selection of a packet 1 of bit lines among the eight that are present, whose drain, shortcircuited with the drain of the seven other transistors MSP related to the other seven packets 1 of the sector, is connected to a circuit 2 for reading the informative content of the memory cells. The gates of the MSP transistors are connected to eight signals YM0-YM7, coming from a further decoding circuit 7 of the address signals, shown in Fig. 2. Still to the common drain of the transistors MS and MSR of each packet 1 there is connected a loading circuit for programming 3, constituted by a transistor MP1 of the p-channel MOS type whose drain is connected to the abovementioned common drain of the transistors MS amd MSR, whose source is connected to a line placed at a programming voltage VP, and whose gate is connected to the output of a circuit 4 accomplishing the NAND logic function. Said NAND circuit 4 comprises a loading transistor M41 of the p-channel MOS type with the source connected to the line placed at the voltage VP, the drain connected to the gate of the transistor MP1 and gate connected to a ground potential. To the drain of the transistor M41 there is connected the drain of a transistor M42, and to the source of the latter there is connected the drain of a transistor M43, whose source is on the other hand connected to the ground potential. To the gate of the transistor M42 there is connected one of the eight signals YM0-YM7, while to the gate of the transistor M43 there is connected a signal DIN representing the data to be programmed in the selected memory cell. There are shown in Fig. 2 controls circuits 5, 6, 7 for the generation of the eight signals YM0-YM7 and of the signal YNR. They comprise a multiplexer circuit 5, provided with two groups of input lines, connected to a sub-system A0-A2 of address signals ADD and to the outputs N0-N2 of a circuit 6, respectively, for recognizing the repaired addresses. Said recognition circuit 6 (known in itself) in turn receives as inputs the address signals ADD, and also provides an output signal ENR to enable the redundancy connected to a control input CTL of the multiplexer 5, and the output signal YNR. The multiplexer 5 is lastly provided with three output lines C0-C2, constituting as many inputs for the selection of the packet (1) of the decoding circuit 7 (also known in itself); the latter circuit's eight output lines constitute the second-level selection signals YM0-YM7. In order to read the data stored in a non-defective memory cell, the address signals ADD are presented across the inputs of the circuit 6 for recognizing the repaired addresses, which, having recognized that the present address does not correspond to the address, previously stored during the memory testing step, of a defective cell, does not trigger the signal ENR. Consequently the multiplexer 5 presents at its outputs C0-C2 the sub-system A0-A2 of the address signals ADD; such signals A0-A2 are thus decoded by the circuit 7 with the purpose of triggering one of the eight signals YM0-YM7 for the selection of one of the packets 1 of bit lines BL. At the same time one of the signals YN0-YN7 is triggered, for the selection of a bit line BL among those of the selected packet 1. In this way the reading circuit 2 is connected to the drain of the selected memory cell, and can as a consequence execute the reading of the data. The same thing takes place when a non-defective memory cell is to be programmed. In this case, however, as a result of the signal DIN constituting the data to be stored, the selected bit line BL can then be connected to the programming voltage VP. In fact, if the signal DIN is active, the transistor M43 is on. The loading circuit 3 related to the packet 1 selected, say by means of the signal YM0, shall have both inputs DIN and YMO of the NAND circuit 4 active, the output of said NAND circuit 4 shall go to the ground potential, and thus the programming transistor MP1, whose gate is connected to the output of said NAND circuit 4, shall be on; this allows the selected bit line BL to go to the programming voltage VP. But, on the other hand, if access to a defective memory cell is attempted, either to read its content or to programme it, the circuit 6 recognizes that the combination of address signals ADD corresponds to the address of a defective cell; it thus triggers the signal ENR that switches the outputs of the multiplexer 5 to the signals N0-N2 coming from the circuit 6 itself and carrying in a coded form the address useful for the selection of the redundancy bit line BLR that has replaced the bit line BL containing the defective matrix cell. The decoding of the signals N0-N2 on the part of the decoding circuit 7 guarantees the triggering of one of the eight signals YM0-YM7, suitable for selecting the packet 1 containing the redundancy bit line BLR that has replaced the defective bit line BL. Simultaneously the circuit 6 triggers the signal YNR, while all the signals YN0-YN7 are disactivated, so that inside the packet 1 selected by the corresponding signal YM0-YM7 the redundancy bit line BLR is selected. Thanks to the special type of decoding used for the generation of the signals YM0-YM7, not linked, in the case of an address corresponding to a defective cell, to the combination of the sub-system A0-A2 of the address signals ADD, it is possible to replace the bit line BL containing the defective cell with any of the eight bit lines BLR of the same sector, and not just with the bit line bLR of the packet 1 to which the defetive bit line BL also belongs. If, in fact, a traditional decoding circuit were to be used for the generation of the signals YM0-YM7, wherein the latter would always be generated starting from the signals A0-A2, a defective bit line BL could be replaced only by the redundancy bit line BLR belonging to the same packet 1 as the bit line BL. This would have as an undesired consequence that whenever there were to be two o more defective bit lines BL in a packet 1, the entire memory would have to be rejected, while there would still be other redundancy bit lines BLR in other packets 1. It should also be highlighted that, thanks to the described architecture, for the selection of the redundancy bit line BLR only one additional signal YNR is necessary over and above the signals YN0-YN7 and YM0-YM7 normally necessary for the selection of the bit lines BL of the matrix, while in the previous redundancy embodiments as many distinct selection signals are necessary as there are redundancy bit lines BLR.

Claims: A semiconductor memory, comprising a matrix of memory cells located at the intersection of rows and columns (BL) of the matrix, the columns (BL) of memory cells being grouped together in packets (1) and said packets (1) being in turn grouped together in sectors, the latter all together forming said matrix, comprising also first-level selection means (MS) for the selection of a particular column (BL) inside each packet (1), second-level selection means (MSP) for the selection of a particular packet (1) inside each sector, columns (BLR) of redundancy memory cells suitable for replacing columns (BL) containing at least one defective memory cell, each of said redundancy cell columns (BLR) being included in a respective packet (1) of memory cell columns (BL) and being provided with selection means (MSR) for the selection of one of said redundancy cell columns (BLR) as an alternative to the memory cell columns (BL) of the packet (1) to which the redundancy cell columns (BLR) belongs, a decoding circuit (7) supplied with packet address signals (C0-C2) for generating second-level selection signals (YM0-YM7) to drive said second-level selection means (MSP), and control circuits (5,6) to execute the replacement of a defective memory cell column (BL) with a redundancy cell column (BLR), said control circuits (5,6) comprising a recognition circuit (6) for storing the addresses of the defective memory cell columns (BL), characterized in that said recognition circuit (6) stores the adresses of the respective substitutive redundancy cell columns (BLR) and compares address signals (ADD) externally supplied to said recognition circuit (6) with the addresses of the defective memory cell columns (BL), said control circuit (5,6) further comprising switching means (5) controlled by the recognition circuit (6) to supply said decoding circuit (7) with packet address signals (C0-C2) represented either by a sub-system (A0-A2) of said externally supplied address signals (ADD) when the recognition circuit (6) recognizes that the externally supplied address signals (ADD) do not correspond to a defective memory cell column (BL), or by signals (N0-N2) supplied by the recognition circuit (6) representing a sub-system of the address of one redundancy cell column (BLR) when the recognition circuit (6) recognizes that the externally supplied address signals (ADD) correspond to a defective memory cell column (BL). The semiconductor memory according to claim 1, characterized in that said switching means (5) are constituted by a multiplexer (5) having a first input channel supplied with said sub-system (A0-A2) of the externally supplied address signals (ADD), a second input channel supplied with said sub-system (N0-N2) of the address of one redundancy cell column (BLR), an output channel supplying said packet address signals (C0-C2) to the decoding circuit (7), and a control input (CTL) supplied with a control signal (ENR) supplied by the recognition circuit (6). The semiconductor memory according to claim 1, characterized in that said first-level (MS) and second-level (MSP) selection means are represented by transistors. The semiconductor memory according to claim 1 characterized in that with each packet (1) of each sector there is associated a loading circuit (3) for programming the memory cells. Semiconductor memory according to one of the prior claims, characterized in that each of said packets (1) of the same sector contains one of said redundancy columns (BLR).

Inventors: OLIVO MARCO, PASCUCCI LUIGI, OLIVO, MARCO, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C11
IPC codes: G11C11, G11C29