MEMORY MATERIAL AND METHOD FOR ITS MANUFACTURE

Abstract: A composition of materials having ferromagnetic, piezoeletric, and electro-optical properties is disclosed. In the preferred embodiment, the composition of materials (310 and 350) comprises a first layer of Pb(1-x-y)CdxSiy, a second layer of Se(1-z)Sz, and a third layer of Fe(1-w)Crw, where x, y, z and w are values within the ranges of 0.09 </= x </= 0.11, 0.09 </= y </= 0.11, 0.09 </= z </= 0.11 and 0.18 </= w </= 0.30. Additionally, each of the layers contain at least one of the elements of Ag, Bi, O and N. A random-accesible, non-volatile memory built using the invented composition of materials is also disclosed. This memory provides for storing two independent bits of binary information in a single memory cell. Each cell comprises two orthogonal address lines formed on the opposite surface of an Si substrate, a composition of materials of the present invention formed over each of the address lines (340 and 320), and an electrode formed over each composition of materials. The data is stored electromagnetically and retrieved as a piezoelectric voltage.

Description: MEMORY MATERIAL AND METHOD FOR ITS MANUFACTURE BACKGROUND OF THE INVENTION Computer technology requi.res memori.es havi.ng large storage capacity and high speed. Typically, in a modern computer, a semiconductor memory is employed as high-speed primary memory and magnetic disks are used for a large volume secondary memory. Prior to the development of semiconductor memories, the high-speed primary memory was implemented using a magnetic core memory. A magnetic core memory comprises a matrix of ring-shaped ferromagnetic cores. Each memory cell of the magnetic core memory includes a ferromagnetic core having two or more wires passing through the center of the core and a sensing coil installed around the core. When a current I is applied to a wire that passes through the core, a magnetic field is produced which has a magnetic field strength H which is a function of the current I. The magnetic field produced by the current causes a permanent magnetization of the core which is measured by the magnetic induction B. The relationship between B and H has substantial hysteresis with the result that a plot of B versus H, which is known as the magnetization curve or BH loop, is substantially square. The magnetic induction B in the pore has two states, B r and -B r , that correspond to the opposite directions of the magnetic field. Accordingly, each core can store a bit of binary data by associating one state with a ■■ l" and the other state with a "0". Illustratively, +B r may be associated with a binary • ■ I** and -B r with a binary "O". The binary data is written into a core memory cell by applying appropriate currents to the wires. If the total current passing through the core is greater than a critical current I c , the magnetic induction of the core changes from -B r to +B r . Similarly, if the current is less than -I c , the magnetic induction switches from +B r to -B r . Advantageously, in an array of magnetic cores, switching is performed as the result of the coincidence of signals on two or more wires. Thus, if the magnetic induction initially has the value of -B r corresponding to a **0", a binary ■■ l" is stored by applying a current I>I c /2 to each of the two wires, so that the total current passing through the core is greater than +I C which causes the magnetic induction to change to +B r The data stored in the core is retrieved by sensing the voltage across the coil induced by switching between the two magnetic states described above. The polarity of the induced voltage indicates the magnetic state of the core prior to switching. Although the magnetic core memory described above is random accessible and non-volatile, such memory is large, consumes a large amount of power, operates at a slow speed and can not be manufactured to have a high storage density. To overcome these problems, magnetic thin film memory devices have been developed. A magnetic thin film memory consists of a strip of ferromagnetic thin film, two or more wires for writing data formed on the film and a coil around the film for reading data. In the thin film memory, the magnetic moment M of the film represents the stored information. The magnetic moment M is oriented primarily in the plane of the film, and has two discrete orientations or states M and -M that represent binary --1" and **0*-. To store a bit of binary data, currents are applied to the wires formed on the thin film. These currents induce a magnetic field that is sufficient for changing the direction of the magnetic moment M. The stored information is retrieved by applying currents to the wires and measuring the induced voltage in the coil. As in magnetic core memory, the currents are typically selected such that a single current has insufficient amplitude to reverse the magnetic moment of the film so that at least two coincident currents are required for storing data. There are significant drawbacks associated with magnetic thin film memory technology. First, thin film devices have an open magnetic flux structure and therefore the BH loop is smeared by a self- demagnetizing effect. To reduce this effect, the film is typically fabricated as a rectangle whose length is much greater than its width. Since the induced voltage in the coil around the film is proportional to the cross-sectional area of the film, reducing the width of the film also reduces the induced voltage. As a result, the readout signal is easily affected by noise. Second, in existing magnetic films, the magnetic moment has a preferred in-plane direction. Thus the device is complicated by the necessity of applying currents of different amplitude for storing and retrieving data in the selected orientations. In addition, the thin film devices are not sufficiently small to achieve high densities. In comparison to magnetic core and thin film memories, semiconductor memory is faster, consumes less power, and can have higher storage densities. Typical semiconductor memories include Dynamic Random Access Memory (DRAM) , Static Random Access Memory (SRAM) , and Read Only Memory (ROM) . DRAM offers relatively high speed, high density, low power consumption, and is readable and writable. However, both DRAM and SRAM are volatile, that is, they lose the stored information when the power is turned off. In addition, DRAM requires a constant refresh of the stored data which necessitates complex circuitry. While SRAM does not require a refresh, it has high power consumption and does not have high storage density. ROM's are non-volatile but the information stored in a ROM cannot be updated, i.e., data cannot be easily written into a ROM. In a typical disk storage system, ferromagnetic material having a substantially square BH loop is coated on the disk; and a magnetic head reads and writes information on the disk as it rotates past the head. The disk is divided into circular tracks. Each track is further divided into small regions in which a magnetic moment has two states that represent binary values. An external magnetic field introduced by the read/write head changes the magnetic moment of each small region so as to store a binary value in the region. Thus, to write data, the magnetic head magnetizes an adjacent small region of the rotating disk material. Stored data is retrieved in the form of a voltage induced in the head by the magnetic moment of the small region as it moves past the head. Magnetic disk storage systems can store high volumes of data, e.g., 500 Megabytes or more. The magnetic disk storage systems, however, are not random accessible, operate at slow speed due to the requirement of mechanical movement, and require complex mechanical and electronic assemblies. As will be apparent, none of the above- described memory technologies provides all the features that are desirable in a memory storage system. Thus, there is a present need tb develop a non-volatile, high speed, high capacity, random accessible, static, and updatable storage system. SUMMARY OF THE INVENTION » The present invention relates to a new composition of materials which has ferromagnetic, piezoelectric and electro-optical properties and can be employed as a storage media. This invention also relates to a non-volatile random accessible memory built on the basis of the invented composition of materials. A novel method for storing and retrieving two independent bits of information in a single memory cell of the present invention is also disclosed. The preferred composition of materials of the present invention comprises layers of Pb (1 . x . y) Cd x Si y , Se 0 . z) S z , and Fe (1 . w) Cr w where x, y, z and w indicate the proportions of the elements within their respective layers. These values are preferably within the following ranges: 0.09 < x < 0.11, 0.09 < y ≤ 0.11, 0.09 < z < 0.11, and 0.22 < w < 0.36. In the preferred embodiment, the layers of the composition of materials also contain the following elements: Bi, Ag, O and N. These elements are introduced by electrolysis in a solution containing Bi 2 0 3 and AgN0 3 . In a memory device of the present invention, two sets of parallel address lines are disposed orthogonally on the opposite sides of a planar substrate. The layers of the novel composition of materials, as described above, are disposed on both sides of the substrate above the address lines with the FeCr layers outermost, and an electrode is connected to the outermost FeCr layer on each side of Λ the substrate. An individual memory cell is located at each crossing point of the address lines of the two sets. By applying appropriate current pulses to the two address lines, two independent bits of information can be magnetically stored in a single memory cell. This information is retrieved as a piezoelectric voltage between the electrodes that is generated in response to appropriate current pulses applied to the two address lines. More specifically, to store and retrieve a first bit of information in a memory cell, two synchronized current pulses having the same amplitude and polarity are applied to two orthogonal address lines. The second bit is stored and retrieved in that memory cell by applying two synchronized pulses of the same amplitude but opposite polarity to the same two address lines. The current pulses employed for storing binary information are such that the amplitude of a single pulse is not sufficient to alter the state of the stored information but that two concurrent pulses are sufficient for storing data. The current pulses employed for retrieving the stored binary information have amplitudes insufficient to alter the 1 stored information. Such a memory cell is non-volatile, random accessible, static, operates at high speed, requires low power, is readable and writable, and can be made in high density arrays. BRIEF DESCRIPTION These and other objects, features and advantages of the invention are more fully set forth in the accompanying Detailed Description in which: Fig. 1 shows the cross-section of a preferred embodiment of the composition of materials of the present invention; Fig. 2 illustrates the magnetization curve (BH loop) of a conventional ferromagnetic material; Fig. 3 shows a substantially square BH loop of the composition of materials of the present invention; Figs. 4 (a)-(j) illustrate the process of generating piezoelectric voltage within the composition of materials; Figs. 5 (a) and (b) are the cross section and top-view of the preferred embodiment of the memory device of the invention; Figs. 6 (a) and (b) illustrate the process of selecting carriers within the memory device; Figs. 7 (a) and (b) illustrate storing the first bit of information into the memory device; Figs. 8 (a) and (b) show the process of reading the stored first bit of information; Figs. 9 (a) and (b) illustrate storing a second bit of information into the memory device; Fig. 10 shows the current pulses used for retrieving the second bit of information stored in the memory device and corresponding output; Fig. 11 is a summary list of preferred methods for storing and retrieving information from the memory device; and Figs. 12(a) and (b) show the electrical current with respect to process time in an electrolysis process utilized as a step in fabricating the composition of materials. DETAILED DESCRIPTION The present invention relates to a composition of materials having ferromagnetic, electro-optic and piezoelectric properties. A random accessible non-volatile memory device utilizing the invented composition of materials is also disclosed. Advantageously, the memory device is capable of storing two independent bits of information. The preferred composition of materials comprises layers of Pb (1 _ x _ y) Cd x Si y , Se (1 . z) S z , and Fe ( ,. w) Cr w . The values of x, y, z and w are preferably in the ranges of 0.09<x<0.11, 0.09<y≤0.11, 0.09<z<0.ll, and 0.22<w<0.26. Preferably, each layer also includes one or more of the elements Bi, Ag, 0 and N. Alternatively, in the Pb α . x . y) Cd x Si y layer, Ge can be employed in place of Si and/or Zn or Te can be employed in place of Pb. Also, other conductive elements such as Au, Pt, or Cu can be added to the layer structure in place of Ag. The invention may also be practiced using concentrations of Cr in the Fe (1 . w) Cr w layer such that w ranges from 0.18 to 0.30. More specifically, as shown in Fig. 1, a preferred embodiment of the invented composition of materials comprises a Pb ogo Cd 010 Si 010 layer 110, a Se 090 S 010 layer 120, and a Fe 076 Cr 024 layer 130. The Fe 076 Cr 024 layer is mainly responsible for the ferromagnetic properties of the composition of materials, and the Pd 080 Cdo. 10 Si 0 .ι and Se 09 S 01 layers are mainly responsible for its electro-optical properties. All three layers exhibit piezoelectric properties. In the devices described below, these layers are sequentially ' formed on a substrate 100 and each of the Pb og oCdo.,oSio. 10 , Se 090 S 0 . 10 and Feo.7eCro. 24 layers is 0.5 μm thick. Physical properties of the invented composition of materials are described below. Understanding of these properties will help to understand the operation of the memory device employing this composition of materials. By way of background, a ferromagnetic material exhibits a permanent magnetic field in the absence of an external magnetic field. Such materials can be described in terms of a large number of small magnets known as magnetic dipoles. An external magnetic field applied to a ferromagnetic material aligns the magnetic dipoles within the material in the direction of the applied field, so that the total magnetic field within the material is the sum of the external field and the field generated by the aligned magnetic dipoles. When the influence of an external magnetic field is discontinued, the orientation of magnetic dipoles does not change, resulting in a constant magnetic field in the material. Magnetic information storage is based on this property of ferromagnetic materials. Fig. 2 shows an exemplary magnetization curve of a typical ferromagnetic material. The magnetization curve is also referred to as a BH loop. The y axis in this figure represents magnetic induction B, which is the overall magnetic field in the material, and the x axis represents the magnetic field strength H of the external magnetic field. Thus, the BH loop shows the change in the magnetic induction B with changing magnetic field strength H. Let us consider the BH loop of Fig. 2 in further detail. Assuming that initially the orientations of magnetic dipoles of the ferromagnetic material are evenly distributed in all directions, the total value of B in the absence of the external field is zero (point "a*' on the curve) . When an external magnetic field is applied to the ferromagnetic material, the value of B gradually increases as H increases until it reaches a point where magnetic induction B begins to saturate (point "b" on the curve) . In other words, when H reaches a certain value, B remains substantially at B 0 even if H is being increased. If, after saturation, the external magnetic field is decreased to H=0, magnetic field induction B does not return to the point "a' 1 (B=0) . Instead, the value of B remains approximately at B=B 0 (point "c" on the curve) . At point "c** the direction of the external magnetic field H is reversed. At approximately H=-H c , the external field changes the polarity of the field B, and, at point "e", the field saturates at the opposite polarity B=-B 0 . Increasing the field strength H causes B to change from point "e" on the curve to point "b", as illustrated in Fig. 2. Fig. 3 illustrates the BH loop of the composition of materials of the present invention. As in Fig. 2, the x-axis indicates the external field strength H and the y axis indicates the magnetic induction B. It is important to note that for the invented composition of the materials, the shape of the BH loop is substantially square with the angle a between the y-axis and the BH loop at B=0 being less than 1°. Because the magnetization curve is substantially square, the magnetic induction B is almost invariably at one of two discrete, stable states, +B 0 and -B 0 . Accordingly, the novel composition of materials is suitable for storing binary information. The composition of materials of the present invention also has piezoelectric properties. In general, if the mechanical pressure on a piezoelectric material is reduced, a piezoelectric voltage is generated. In the present invention, if the mechanical pressure on the composition of materials is reduced in a direction substantially perpendicular to the plane of the layers within the composition of materials, a piezoelectric voltage is generated across the layers. In the present invention, the change in mechanical pressure is produced by a change in the magnetic states of the composition of materials. An illustrative structure exhibiting the piezoelectric properties of the present invention is shown in Fig. 4 (a) . An explanation of its operation is set forth in conjunction with Figs. 4 (b)-(j). Fig. 4 (a) illustrates a structure 190 comprising two layers of the composition of materials of the present invention. Specifically, the structure comprises a first FeCr layer 200, a first SeS layer 210, a first PbCdSi layer 220, a second PbCdSi layer 230, a second SeS layer 240, and a second FeCr layer 250. In addition a wire 260 passes through the middle of the structure, parallel to the layers. As shown in Fig. 4 (b) , an electrical current applied to the wire 260 in a direction that is into the page generates a substantially circular magnetic field around the wire, as indicated by a circle B r in the clockwise direction indicated by the arrow. Arrows 270 illustrate the directions of the magnetic dipoles in FeCr layers 200, 250 under the influence of this external field. If we divide the structure into two sections 275, 280 that are symmetric about a vertical axis 265 perpendicular to wire 260 as shown in Fig. 4 (b) , the dipole arrangement in sections 275, 280 is equivalent to two magnets of the same strength having north and south poles as indicated by arrows 282 and 284 in Fig. 4 (c) . The length of each arrow represents the amplitude of the magnetic induction B of the corresponding magnet. Due to the attraction between the South pole S and the North pole N of each magnet, the storage media is mechanically compressed in the direction perpendicular to the layers of the structure. The BH loop of the magnetic induction B r is shown in Fig. 4 (d) . As described previously the BH loop is substantially square, exhibiting two discrete, stable magnetic states, +B 0 and -B 0 . Additionally, the magnetic field has a critical field strength H c which is defined as the amplitude of the magnetic field strength which causes switching between +B 0 and -B 0 . Consequently, if H is greater than H c , the magnetic induction B r will have a value +B 0 . If H is less than -H c , B r will have a value -B 0 . Assume that initially under the influence of the applied external field, the magnetic state is described by point "a" on the curve of Fig. 4(d), where the induction is +B 0 . To change the magnetic state of the storage media from +B 0 to -B 0 , the current through wire 260 must be reduced to reduce the magnetic field strength H. When the current is zero the magnetic strength H is also zero (point "b" on the BH loop) . As noted, due to its ferromagnetic properties, even without the external field, the magnetic state of the storage media remains at B 0 , i.e., the information represented by the magnetic induction B 0 is retained. When the direction of the current is reversed, the magnetic field strength continues to decrease point. At "c", the magnetic induction B reaches the value B c , which is less than B 0 . At this point, the dipole moment has been reduced, as shown in Fig. 4 (e) , because the dipoles begin to realign in the opposite direction. Accordingly, the mechanical pressure on the layers due to the attraction of the FeCr layers 200, 250 has been reduced. The change in the pressure on the layers causes piezoelectric voltage to be generated perpendicularly across the layers. At point "d", where H=-H c and the -magnetic induction B is zero, the pressure applied to the layers is minimal because the dipoles are aligned in different directions. At this point, the induced piezoelectric voltage reaches its maximum value, due to the maximum change in the pressure on the layers. As H continues to decrease below -H c , the magnetic state switches from point "d" to the point "e" and then to point "f" where it reaches the second stable state B=-B 0 . Fig. 4 (f) shows that at point "f* 1 the poles of the magnets have been reversed. Thus, at point "f", the mechanical pressure on the layer returns to its initial value, diminishing the piezoelectric voltage. Increasing the reversed current further (from point "f" to point "g") would not increase the magnitude of the dipole moment and therefore would not increase mechanical pressure on the layers. J Fig. 4 (g) illustrates the piezoelectric voltage that corresponds to various points on the BH loop of Fig. 4 (d) as B 0 changes to -B 0 . In Fig. (h) , the piezoelectric voltage generated in response to a current pulse is illustrated in the time domain. The piezoelectric voltage is a piezoelectric voltage pulse that is delayed from the time of the application of the current pulse. The current pulse applied to c the wire has an amplitude -I that is sufficient to switch B 0 to -B 0 . Similarly, switching from the magnetic state -B 0 to +B 0 generates a negative piezoelectric voltage pulse. As indicated in Fig. 4 (d) , a current that generates a field having an amplitude greater than H c is required for switching between the magnetic states. If, however, a current is applied having a lesser amplitude which causes B to assume a value indicated t»y point "c" in Fig. 4 (e) , the magnetic state is unstable. In such case, the magnetic induction B tends to oscillate between the values of B 0 (point "b") and B c (point "c") , A piezoelectric voltage pulse generated in response to such oscillation is shown in Fig. 4 (i) . The amplitude V 2 of this piezoelectric voltage pulse is smaller than the amplitude of the pulse generated as a result of switching from +B 0 to - B 0 (Fig. 4 (g)). Fig. 4 (j) shows a current pulse I which causes B to assume the value B c . The piezoelectric voltage pulse, generated in response to this current is shown in the lower portion of the figure. The shaded area reflects the oscillation between the two states (B c and +B 0 ) , as it would be observed on an oscilloscope. As described subsequently, the piezoelectric voltage generated in response to the current that disturbs but does not switch the magnetic states, can be employed for reading magnetically stored information. Figs. 5 (a) and (b) illustrate the cross- section (not to scale) and the top-view of a preferred embodiment of a portion of a memory device 290 of the present invention. The memory device comprises a silicon planar substrate 330, first address lines 320 formed on one surface of the substrate, and second address lines 340 orthogonal to the first lines, formed on the opposite surface of the substrate. A first set 310 and a second set 350 of the layers of materials of the present invention are disposed on opposite sides of the substrate over the address lines. Electrodes 300, 360 are connected to the layers 310, 350 respectively of the composition of materials. The first and second address lines are silver strips approximately 2μm wide and approximately lμm thick. Illustratively the spacing between adjacent address lines is approximately between 9 to 20 μm, depending on the desired density of the memory device. For example in one embodiment the spacing is 9.5 μm and in a different embodiment the spacing is 19 μm. Each set of layers of materials 310, 350 comprise a Pb 80 Cd ( 0 Si 0 ., layer, a Se 0K) S 0 . 10 layer, and a Fe 0 . 76 Cr 24 layer sequentially formed on one of the address lines 320, 340 on the Si substrate with the two FeCr layers being outermost. Also, each of the layers is preferably 0.5 μm thick so that each set is preferably 1.5 μm. Each layer is homogeneously saturated with Bi, Ag, O, and N. Preferably the substrate is 40 μm thick and the electrodes are lμm thick silver layers. The fabrication of this device begins with depositing lμm thick metal (preferably silver) layers onto the opposite surfaces of a 40μm thick silicon planar substrate. Alternatively, substrates made of other materials such as BaF 2 could be used in place of the Si substrate. The deposition is conducted by a conventional technique such as thermal evaporation, e- beam evaporation, or sputtering. The deposited silver layers are then photolithographically patterned and etched to form a series of metal strips, each having a width of approximately 2μm. The series of strips on one side of the Si substrate is orthogonal to the strips on the opposite side. The strips on both sides of the substrate form a cross-barred structure. The layers of Pb 080 Cdo. 10 Sio.ιo, Se 090 S 010 , and Fe 076 Cr 0 . 24 are then deposited sequentially. Prior to the deposition, components of the layers are prepared by mixing together proper amounts of powder of each required element. The amount of powder of each element corresponds to the desired proportion of the element in the corresponding layer. For example, for the deposition of the Pb 080 Cd 010 Si 0 , 0/ layer the powders of Pb, Cd and Si are mixed in the proportions 80:10:10. After the powders of Pb, Cd, and Si are well mixed, the mixture is pressed and baked to form a suitable source of materials for the selected deposition technique. The source materials for deposit of the Se 0 . 9 oS 010 and Fe 076 Cr 024 layers are prepared in a similar fashion. The layers of Pb ogo Cd 010 Si 010 , Se 09 S 01 and Fe 076 Cr 024 are then sequentially deposited onto both sides of the substrate. The deposition can be accomplished using well-known methods. For example in the preferred embodiment a plasma sputtering techniques is utilized for creating the layered structure. After each layer is deposited by sputtering, the temperature of the layer is raised rapidly (i.e. in about 1.5 seconds) to approximately 500°C and then cooled to approximately a room temperature for the deposition of the next layer. As conventionally done, the spattering is performed in vacuum utilizing Ar gas. As indicated, each of the *-' e o.o , ---o.io and Fe 0 7 6 Cr 02 layers is approximately 0.5 μm thick, forming two structures approximately 1.5μm thick on the opposite surfaces of the substrate with the two FeCr layers beipg outermost. The elements Bi, Ag, 0 and N by are then added to the layers by an electrolysis process that employs a heated electrolyte containing Bi 2 0 3 and AgN0 3 . The electrolyte is prepared by heating high purity water to 97°C in a stainless steel container with a stirring device on the bottom of the container. The Bi 2 0 3 and AgN0 3 powders are then added to the heated water to form the electrolyte. Preferably the proportion of weight of the added powders is about 40% of Bi 2 0 3 and 60% of AgN0 3 . The amounts of these powders can be adjusted to achieve a desired current in the electrolyte. After adding the powders, the electrolyte is maintained at 97°C and stirred continuously for at least one hour to form a uniform solution. Prior to the electrolysis process, all the metal strips on both sides of the substrate are connected to form a single electrode. The substrate is then immersed in the electrolyte which is maintained at a temperature of 97°C and is continuously stirred. Advantageously, many substrates can be simultaneously immersed in the electrolysis solution. For example, 100 1cm x 1cm substrates can be processed simultaneously. In this case the metal strips of all the substrates should be connected to a single electrode. The complete electrolysis process takes 45 days. Each day the same process cycle is repeated. During the initial 10 hours of the cycle, an electrical potential of +60V is applied to the substrates and during the next 14 hours, a -60V potential is applied to the substrates. The stainless steel container is always kept at ground potential. Also, every 12 hours during the electrolysis process, the positions of the substrates within the container are interchanged for uniform processing. Throughout the process the electrolyte is continuously stirred. During the process, the amplitude of the current flow in the electrolyte solution is monitored. Fig. 12(a) illustrates the current I in Amperes in the electrolyte during the first forty days of the process. The days are indicated on the horizontal axis "t". Fig. 12(b) illustrates the values of the current I during the last five days. The current I is in rnA's. At the end of the forty-fifth day, the electrode is disconnected from the substrates and the substrates are removed from the electrolyte solution. At this point, the ions of the elements listed above have sufficiently penetrated the layered structure. Note that in a different embodiment ion implantation techniques can be employed for introducing .these elements into the layered structure. The composition of materials on both surfaces of the substrate is then polished until the surfaces are substantially smooth. Subsequently, an approximately lμm thick layer of silver is deposited on the surfaces of each substrate to form the electrodes 300, 360. At the completion of this procedure, a novel two-dimensional memory array has been manufactured. The area near each intersection of the orthogonal address lines 320, 340 constitutes a cell of the memory. More specifically, as shown in Figs. 5 (a) and 5 (b) , the set of metal strips on the lower surface of the Si substrate forms a first set of addressing lines, (referred to as X lines) , and the set of metal strips on the upper surface of the substrate forms a second set of addressing lines, (referred to as Y lines) . When two electrical currents Ij and I j are simultaneously applied to a given line X; of the X lines and a line Y j of the Y lines, respectively, a memory device (i,j) at the intersection of X; and Y j is selected. By properly choosing the magnitudes and polarities of the currents I; and I j , information can be stored or retrieved from the memory device (i,j) . Thus, the memory,array, comprising the memory devices of the present invention, is random accessible. The process of storing information in a cell will be apparent from Figs. 6 (a), 6 (b) , 7 (c) , 7 (b) , 8 (a), 8 (b) , 9 (a) and 9 (b) , 10 and 11. Figs. 6 (a) and (b) , show top views of a single cell of the memory device. The orthogonal address lines 325, 345 divide the cell into four quarters 370, 375, 380 and 385, as illustrated in Fig. 6 (a) . As discussed below, a first bit of information is magnetically stored in the quarters 370 and 380 and a second bit is magnetically stored in the quarters 375 and 385. For simplicity, the quarters 370 and 380, where a first bit of information is stored, are collectively referred to as carrier ■ •a" and the quarters 375 and 385 where a second bit is stored are collectively referred to as a carrier ■■ b". To store a bit of information in one of the carriers of the memory device, two electrical currents having specified amplitudes and polarities are applied to the first and second address lines, 325, 345. Information is retrieved from one of the carriers by applying two electrical currents to the address lines and measuring a piezoelectric voltage generated between the upper and lower electrodes. The current applied to the firs ,address line is represented as I ; , and the current applied to the second address line is represented as I j . The directions of Ij and I j are indicated by the arrows entering the address lines. In the preferred embodiment, the currents I ; and I j have the same amplitude, I 0 . Each current generates an induced circular magnetic field around the address lines as illustrated by the arrows 390 and 395. The directions of the magnetic fields B ; and B j induced by Ij and I j in each quarter is illustrated in Figs. 6 (a) and (b) . A dot (•) indicates that the field is in the ■■ up" direction and a cross (x) indicates that the field is in the opposite or "down" direction. As illustrated in Fig. 6 (a) , in the quarters 485 and 475 (carrier "b") B ; and B j have the opposite directions and thus cancel each other out. For this reason the currents illustrated in Fig. 6 (a) do not affect the information stored in the carrier "b". On the other hand, in the quarters 470 and 480 (carrier "a") the fields B; and B j are induced in the same direction. Accordingly, these fields enhance each other and, thus, can alter the stored information. Thus two currents having the same polarities and amplitudes applied to the address lines, affect only the magnetic state of the carrier "a" and thereby select this carrier. Likewise, two negative pulses also select and can store data in the carrier "a". Note also that the amplitudes of the currents that select the carrier "a" do not have to be equal, as long as their combined effect does not change the magnetic state in the carrier "b". Fig. 6 (b) illustrates the process of selecting the carrier "b". Two currents, having opposite polarities, Iι=+I 0 and I j =-I 0 , are applied to the first and second address lines respectively. As illustrated using the dot and cross convention described above, in the carrier "a", the fields generated by these currents cancel each other out, without affecting the magnetic state. In carrier "b" however the fields generated by these currents enhance each other so that the carrier "b" is selected. Similarly, two currents I;-=-I 0 and I j =+I 0 applied to the two address lines also select the carrier "b". Thus two currents with the same amplitude but the opposite polarities select the carrier "b" for storing or retrieving information. To store information, the amplitudes of the two currents combined should be sufficiently large to switch the magnetization of a carrier between the magnetic states B 0 and -B 0 . In addition, the amplitudes of the two currents combined should be sufficiently small so that a single current alone is unable to change the magnetic state of a carrier. This is necessary to assure that only one carrier in the memory array is selected by the signal on an address line. To retrieve information, the amplitudes of the two currents combined should be small enough that the induced field is not strong enough to change the magnetic state of the carrier. The combined amplitudes, however, should be sufficient to disturb the magnetic state of the carrier so as to generate a piezoelectric voltage across the storage media. As discussed above, the direction of this piezoelectric voltage represents the binary data stored in the carrier. By way of illustration, Fig. 7 (a) depicts the process of writing a binary "1" into the carrier "a" using synchronous current pulses on the two address lines. Initially, all the cells of the array are assumed to be in the "0" state which corresponds to a magnetic induction of -B 0 . To write a binary "1", two synchronized current pulses, I;=+20μA and I j =+20μA are applied to the two address lines, respectively. This generates a magnetic field H which magnetizes the FeCr layers of the composite material. The magnetic induction B of these layers is depicted in, Fig. 7 (a) as a closed loop with an arrow. For the structure of Fig. 5 having the dimensions described above, the amplitude of the critical current I c necessary to generate the critical field strength H c required for switching between the two discrete states is approximately 35 μA. At the cell where the two pulses coincide, the two +20μA currents create a field H that would be generated by applying a 40μA current. Since this current is greater than I c , the magnetic induction becomes B 0 so that a binary "1" is stored. As explained previously, after the pulses have ended, the magnetic induction at the cell B a remains equal to B 0 , so that a binary "1" is retained in the carrier "a". As shown in Fig. 7 (b) , to store a binary "0" into the carrier "a", two synchronized current pulses, I;-***-20μA and I j =-20μA are applied to the address lines respectively. Since the sum of these currents is -40μA, which is less than -I c , the current pulses switch the magnetic state from +B 0 to -B 0 . Switching between +B 0 and -B 0 generates a piezoelectric voltage pulse between the first and second electrodes after a delay Δt from the time of the application of the current pulses. The piezoelectric pulse is positive for switching from +B 0 to -B 0 and is negative for switching from -B 0 to +B 0 . If the magnetic state does not change, no . piezoelectric pulse is generated. Accordingly, the generated piezoelectric voltage pulses can be employed to verify that a bit of binary data has been stored. To read information stored in the carrier "a" of the memory, two synchronized current pulses I ; =-15μA and I j =-15μA are applied to the address lines. Since the critical current I c =-35μA, the -30μA sum of these currents cannot switch the magnetic states from +B 0 to -B 0 . This current, however, is sufficient to disturb the magnetic state without complete switching. As shown in Fig. 8 (a) , assuming a binary "1" is stored in the carrier, the applied current pulses change B„ from a value corresponding to a point such as "a" on the magnetization curve to the value corresponding to point "b" on the curve. Because of the previously discussed piezoelectric properties of the cell, this change in the magnetic induction generates a positive piezoelectric voltage of approximately +15μV, indicating a "1" is stored in the carrier. If a "0" is stored in the carrier "a", the applied current pulses will change B, from a value corresponding to point "c" to the value corresponding to point "d" on the curve. In this case, however, the magneti.c i.nducti.on of carrier "a" remains at B a =-B 0 , so that no piezoelectric voltage is generated, indicating a **0" is stored. The information stored in the device is not changed during the reading process because I is less than I c . This process of retrieving data is illustrated in the time domain in Fig. 8 (b) . The delay between the piezoelectric voltage pulse and the synchronized current pulses is approximately 0.75ns. The storage and retrieving of data for carrier "b" is similar. As shown in Fig. 9 (a) , two synchronized current pulses, I i =-20μA and I j *=+20μA are applied to the address line to store a "1" in the carrier "b". As discussed above, such current pulses do not affect the carrier "a". At the point where the pulses coincide, a field is induced that is equivalent to the field induced by the 40μA current. Since this is greater than I c =35μA, a "1" is stored in the carrier "b". As shown in Fig. 10 (b) , the current pulses I~+20μA and I j =-20μA are applied to store a "0" in the carrier "b". Switching from "1" to "0" in the carrier B generates a negative piezoelectric voltage pulse between the electrodes at a delayed time Δt, and switching from "0" to "1" generates a positive piezoelectric voltage pulse. If the state does not change, no piezoelectric voltage is generated. The data stored in the carrier "b" is retrieved in a similar way as discussed in conjunction r with carrier "a". As shown in Fig. 10, to retrieve data stored in the carrier B, two synchronized current pulses, I ; =+15μA and I j =-15μA are applied. The combined magnitudes of these pulses are not large enough to switch the magnetic state in carrier "b". If a "0" is stored, the current pulses would not change the magnetic induction B b of carrier "b", and no piezoelectric voltage between the electrodes is generated. If a "1" is stored, the applied current pulses would disturb the magnetic state B b =B 0 , but would not change it, generating a positive piezoelectric voltage pulse at a delay Δt. Thus, for the carrier "b", no piezoelectric voltage pulse indicates that a "0" is stored, and a positive piezoelectric voltage indicates that a "1" is stored. Fig. 11 summarizes the above-described methods of storing and retrieving data from the carriers "a" and "b" of the memory device. Different methods of storing and retrieving information from the memory device of this invention can also be employed. For example, two synchronized currents Ij * =+15μA and I j =+15μ can be utilized for retrieving information from the carrier "a". Similarly, two synchronized currents I;=-15μA and I j =+15μA can be used to retrieve data from the carrier "b". A method of destructive readout can also be employed. For example, two synchronized current pulses I—-i-20μA and I j =+20μA, that write a "1" in the carrier "a", can be applied and the piezoelectric voltage generated in response to these pulses would identify the previously stored data, thereby destructively retrieving data from the carrier A. One of the advantages of the memory device of the present invention is its low power consumption as compared with the prior art non-volatile magnetic memory devices. Since the storage media employed in this device is highly sensitive to the magnetic field generated by the driving currents, it can quickly switch between "0" and "1" at relatively small driving currents, about 20 μA on each line. Consequently, the power consumption is low for storing and retrieving data. In one embodiment, it consumes approximately 3.4xl0" 10 w for reading and 6xi0" ,0 w for storing a bit of data into the device. Note also that the retrieval of information as a piezoelectric voltage generated between the sensing electrode is intrinsically faster than generating induced electromagnetic voltage as in prior art magnetic memory devices. Typically, the delay between the current pulses and corresponding piezoelectric voltage is in the range of subnanoseconds. Switching between "1" and "0" usually takes a few nanoseconds. Thus a memory device which is random accessible, non-volatile, and operates in static mode has been described. This memory device offers high¬ speed operation, low power consumption, and can store information at high density. The claims which follow are to be interpreted to cover all the equivalent structures and methods. The invention is, thus, not to be limited by the above exemplary disclosure, but only by the following claims.

Claims: WHAT IS CLAIMED IS: 1. A composition of materials comprising: a first layer of material having a composition of M ( ,. x . y) Cd x R y where M is an element selected from the group consisting of Pb, Zn, and Te, and R is an element selected from the group consisting of Si and Ge, wherein x and y are values within the ranges of 0 < x < 1, 0 < y < 1, and 0 < (x+y) < 1; a second layer of Se ( ,. z) S z formed on the first layer, wherein z is a value within the range of 0 < z < l; and a third layer of Fe (1 . w) Cr w formed on the second layer, wherein w is a value within the range of 0 < w < 1. 2. The composition of materials of claim 1 wherein the first layer includes at least one of the following elements: Bi, O, N, and an element selected from the group consisting of Ag, Au, Pt, and Cu. 3. The composition of materials of claim 2 wherein the second layer includes at least one of the following elements: Bi, O, N, and an element selected from the group consisting of Ag, Au, Pt and Cu. 4. The composition of materials of claim 3 wherein the third layer includes at least one of the following elements: Bi, O, N, and an element selected from the group consisting of Ag, Au, Pt, and Cu. 5. The composition of materials of claim 1 wherein the value of x is within the range of 0.09 < x < 0.11. 6. The composition of materials of claim 5 wherein the value of y is within the range of 0.09 < y < 0.11. 7. The composition of materials of claim 6 wherein the value of z is within the range of 0.09 < z < 0.11. 8. The composition of materials of claim 7 wherein the value of w is within the range of 0.18 < w < 0.30. 9. The composition of materials of claim 8 wherein the value of w is within the range of 0.22 < w < 0.26. 10. The composition of materials of claim 1 wherein the value of x is substantially 0.10. 11. The composition of materials of claim 10 wherein the value of y is substantially 0.10. 12. The composition of materials of claim 11 wherein the value of z is substantially 0.10. 13. The composition of materials of claim 12 wherein the value of w is substantially 0.24. 14. The composition of materials of claim 13 wherein the first layer is substantially 0.5μm thick. 15. The composition of materials of claim 14 wherein the second layer is substantially 0.5μm thick. 16. The composition of materials of claim 15 wherein the third layer is substantially 0.5μm thick. 17. A method of manufacturing a composition of materials having ferromagnetic, electro-optic and piezoelectric properties comprising the steps of: a first layer of material having a composition of M ( ,. x _ y) Cd x R y where M is an element selected from the group consisting of Pb, Zn, and Te, and R is an element selected from the group consisting of Si and Ge, wherein x and y are values within the ranges of O ≤ x ≤ l, 0 < y < 1, and o < (x+y) < 1; forming a second layer of Se (1 . z) S z on the first layer, wherein z is a value within the range of 0 < z < 1; and forming a third layer of Fe (1 . w) Cr w on the second layer, wherein w is a value of 0 ≤ w < 1. 18. The method of claim 17 further comprising the step of adding at least one of the elements of Bi, 0, N, and an element selected from the group consisting of Ag, Au, Pt, and Cu, into the first, second, and third layers. 19. The method of claim 17 further comprising the step of adding at least one of the elements of Bi, 0, N, or Ag, into the first, second, and third layers. 20. The method of claim 19 wherein the step of adding at least one of the elements of Bi, O, N, Ag comprises immersing the composition of materials in an electrolyte containing Bi 2 0 3 and AgN0 3 and performing an electrolysis. 21. The method of claim 20 wherein the electrolyte is saturated with AgN0 3 . ^ 22. The method of claim 20 further comprising the step of continuously stirring the electrolyte. 23. The method of claim 22 further comprising the step of heating the electrolyte. 24. The method of claim 23 further comprising the step of maintaining the electrolyte at substantially 97°C. 25. The method of claim 20 further comprising the steps of applying a negative electrical potential to the composition of materials with respect to the electrolyte. 26. The method of claim 20 further comprising the steps of alternatively applying positive and negative electrical potentials to the composition of materials with respect to the electrolyte. 27. The method of claim 26 wherein, in a 24 hour interval, the negative potential is applied for substantially 14 hours and the positive potential is applied for substantially 10 hours. 28. The method of claim 20 wherein the electrolysis is performed for substantially 45 days. 29. The method of claim 17 wherein the value of x is within the ranges of 0.09 < x < 0.11. 30. The method of claim 29 wherein the value of y is within the ranges of 0.09 < y < 0.11. 31. The method of claim 30 wherein the value of z is within the ranges of 0.09 < z < 0.11. 32. The method of claim 31 wherein the value of w is within the ranges of 0.22 < w < 0.26. 33. The method of claim 17 wherein the value of x is substantially 0.10. 34. The method of claim 33 wherein the value of y is substantially 0.10. 35. The method of claim 34 wherein the value of z is substantially 0.10. 36. The method of claim 35 wherein the value of w is substantially 0.24. 37. A non-volatile, random-accessible, memory device comprising: a substrate having first and second surfaces; a first address line formed on the first surface of the substrate; a second address line formed on the second surface of the substrate; a first composition of materials having ferromagnetic and piezoelectric properties formed on the first address line and the first surface of the substrate; and a second composition of materials having ferromagnetic and piezoelectric properties formed on the second address line and the second surface. 38. The device of claim 37 wherein the second address line is substantially orthogonal to the first address line. 39. The device of claim 37 further comprising: a first electrode formed on the first composition of materials; and a second electrode formed on the,second composition of materials. 40. The device of claim 37 wherein the first and second compositions of materials are substantially identical. 41. The device of claim 40 wherein each of the first and second compositions of materials comprise three sequentially formed layers wherein the outermost layers have ferromagnetic properties. 42. The device of claim 41 wherein each of the first and second compositions of materials comprise a layer of Se (1 . z) S z interposed between a layer of M (1 . x . y) Cd x R y where M is an element selected from the group consisting of Pb, Zn, and Te, and R is an element selected from the group consisting of Si and Ge, and a layer of Fe (1 . w) Cr w , wherein x, y, z and w are values within the ranges of O ≤ x ≤ l, O ≤ y ≤ i, o ≤ (x+y) < 1, 0 < z < 1, and 0 < w < 1. 43. The device of claim 42 wherein each of the layers of Pb (1 . x . y) Cd x Si y , Se (1 . z) S z , and Fe (1 . w) Cr w includes at least one of the following elements: Bi, O, N and an element selected from the group consisting of Ag, Au, Pt, and Cu. 44. The device of claim 43 wherein x, y, z and w are values within the ranges of 0.09 ≤ x < 0.11, 0.09 ≤ y < 0.11, 0.09 ≤ z ≤ 0.11, and 0.18 ≤ w ≤ 0.30. 45. The device of claim 44 wherein w is a value within the range of 0.22 ≤ w < 0.26. 46. The device of claim 44 wherein the value of x is substantially 0.10, the value of y is substantially 0.10, the value of z is substantially 0.10, and the value of w is substantially 0.24. 47. The device of claim 41 wherein the substrate is an insulator. 48. The device of claim 41 wherein the substrate is a silicon substrate. 49. The device of claim 41 wherein the substrate is a BaF 2 substrate. 50. The device of claim 41 wherein the first and second address lines are made of a conductive material. » 51. The device of claim 50 wherein the conductive material is silver. 52. The device of claim 51 wherein the address lines are metal strips substantially 2μm wide and substantially lμm thick. 53. A method of manufacturing a non¬ volatile, random-accessible memory device comprising the steps of: forming a first address line on a first surface of a substrate; forming a second address line on a second surface of the substrate; forming a first composition of materials on the first address line and the first surface of the substrate, the first composition of materials having ferromagnetic and piezoelectric properties; forming a second composition of materials on the second address line and the second surface of the substrate, the second composition of materials having ferromagnetic and piezoelectric properties. 54. The method of claim 53 further comprising the steps of: forming a first electrode on the first composition of materials; and forming a second electrode on the second composition of materials. 55. The method of claim 53 wherein the second address line is substantially orthogonal to the first address line. 56. The method of claim 53 wherein the steps of forming each of the first and the second compositions of materials further comprises forming a first layer of material having a composition of M (1 . x . y) Cd x R y where M is an element selected from the group consisting of Pb, Zn, and Te, and R is an element selected from'the group consisting of Si and Ge, wherein x and y are values within the ranges of O ≤ x ≤ l, O ≤ y ≤ i, and 0 ≤ (x+y) ≤ 1; forming a second layer of Se (1 . z) S z on the first layer, wherein z is a value within the range of 0 ≤ z < 1; and forming a third layer of Fe α . w) Cr w on the second layer, wherein w is a value of 0 ≤ w ≤ l. 57. The method of claim 56 wherein the values of x, y, z, and w are within the ranges of 0.09 ≤ X ≤ 0.11, 0.09 ≤ y < 0.11, 0.09 < z ≤ 0.11, and 0.22 ≤ W < 0.26. 58. The method of claim 57 wher.ein the value of x is substantially 0.10, the value of y is substantially 0.10, the value of z is substantially 0.10, and the value of w is substantially 0.24. 59. The method of claim 56 wherein the step of forming the address lines comprises depositing conductive layers onto the surfaces of the substrate and etching the conductive layers. 60. A method of storing two independent bits of binary data in a single storage cell of a non¬ volatile, random accessible memory, each such cell being addressable by a first and a second address line comprising the steps of: applying two electrical currents having the same polarities to the first and second address lines, respectively, for storing a first bit of binary data in the storage cell; and applying two electrical currents having opposite polarities to the first and second address lines, respectively, for storing a second bit of data in the storage cell. 61. The method of claim 60 wherein the currents applied for storing the first bit of data have substantially the same amplitudes. 62. The method of claim 61 wherein the , currents applied for storing the second bit of data have substantially the same amplitudes. 63. The method of claim 62 wherein the amplitudes of the electrical currents applied for storing the first and the second bits of data are such that a single current is not sufficient to change the binary value of the stored data. 64. The method of claim 63 wherein each current applied for storing the first bit of data is substantially 20μA. 65. The method of claim 64 wherein each current applied for storing the second bit of data is substantially 20μA. 66. The method of claim 62 further comprising the step of detecting a piezoelectric voltage indicating that a binary data has been stored in the cell. 67. The method of claim 60 wherein the step of applying two electrical currents for storing the first bit of data includes storing a first binary value by applying two electrical currents both having a first polarity and the same amplitude to the first and second address lines, respectively, and storing a second binary value by applying two electrical currents having a second polarity which is opposite to the first polarity and the same amplitude to the first and second address lines, respectively. 68. The method of claim 67 wherein the two electrical currents for storing the first bit of data are applied as two synchronized electrical current pulses having the same polarities. 69. The method of claim 67 wherein the step of applying two electrical currents for storing the second bit of data includes storing a first binary value by applying two electrical currents having a first and second polarities and the same amplitudes to the first and second address lines, respectively, and storing a second binary value by applying two electrical currents having the second and first polarities and the same amplitudes to the first and second address lines, respectively. 70. The method of claim 69 wherein the two electrical currents for storing the second bit of data are applied as two synchronized electrical.current pulses having opposite polarities. 71. A method of retrieving first and second independent bits of data stored in a single storage cell of a non-volatile, random-accessible memory, each such cell being addressable by a first and a second address line comprising the steps of: applying two electrical currents having the same polarity to the first and second address lines, respectively, for retrieving the first bit of data, wherein the amplitudes of the currents are substantially the same and the combined amplitudes of the currents are insufficient for changing the binary value of the stored data; and applying two electrical currents having opposite polarities to the first and second address lines, respectively, for retrieving the second bit of data, wherein the amplitudes of the currents are substantially the same and the combined amplitudes of the currents are insufficient for changing the binary value of the stored data. 72. The method of claim 71 further comprising the step of sensing a piezoelectric voltage generated in response to the applied currents. 73. The method of claim 72 wherein the amplitudes of the two electrical currents applied for retrieving the first or the second bits of data are substantially 15μA. 74. The method of claim 72 wherein the two electrical currents are applied for retrieving the first bit of data as two synchronized electrical current pulses having the same amplitudes and polarities. :. 75. The method of claim 74 wherein the two electrical currents are applied for retrieving the second bit of data as two synchronized electrical current pulses having the same amplitudes and opposite polarities. . * - .

Inventors: GENDLIN SHIMON, GENDLIN, SHIMON
Applicants: KAPPA NUMERICS INC, KAPPA NUMERICS INC.
Application year: 1993
Main classification: G11C11
IPC codes: C23C14, C25D11, G11C11, H01F10, H01F41, H01L21, H01L41