One bit differential detector for GMSK with frequency offset compensation

Abstract: A one-bit differential detector for a GMSK signal operates independently of an offset frequency. In particular, a decision signal used by a decision circuit to distinguish between logic "0" and logic "1" is always equal to sin[Δ(T)] . The inventive detector has an improved bit error rate performance in comparison to the prior art.

Description: The present invention relates to a detector for use in a communication system using a phase-shift-keying (PSK) modulation scheme. More particularly, the present invention relates to a one-bit differential detector for a Gaussian baseband filtered minimum shift keying (GMSK) signal which eliminates problems relating to frequency offset. FIG 1 illustrates a GMSK transmitter. Such a transmitter may be used for mobile communications in Europe in accordance with Digital European Cordless Telecommunications (DECT) standard. The GMSK transmitter 10 of FIG 1 comprises a Gaussian Low Pass Filter (LPF) 12 and an FM modulator 14. The transfer function of the Gaussian LPF is h t ( t ) = (1 π )α t exp[-(α t t ) 2 ] α t = 2 2π B tn = 2 2π KB t K = (1/2) (π/1 n 2) = 1.0645 B t denotes the Gaussian Lowpass Filter (LPF) bandwidth which is illustratively 3dB. B is the cutoff frequency of the Gaussian filter and T is the data symbol time. Illustratively, BT=0.5 B tn is the equivalent noise bandwidth. K is the transformation coefficient which relates B t to B tn and is often considered to be one. The Gaussian LPF filter 12 receives a Non-Return-to-Zero (NRZ) signal at its input. The output of the filter 12 is a baseband signal of frequency fb equal to 1.152 MHz. The baseband signal is inputted to the modulator 14. The FM modulator 14 is a minimum shift keying (GMSK) modulator. The output signal of the modulator 14 is a GMSK signal. The GMSK signal is in the intermediate band and has a frequency f IF = 4fb. A prior art detector 20 for a GMSK signal is illustrated in FIG 2. The GMSK signal enters the intermediate band filter 22 with transfer function H r (t). The output signal of the filter 22 is x(t) = cos [ω IF t + (t)] In the signal x(t), ω IP =2πf IF . The phase is (t). The filter 22 serves to band limit the signal x(t) and normalizes the envelope of x(t) to unity for all t. The phase (t) contains the information. The detector 20 comprises the one unit delay 24, the 90° phase shifter 26, and the multiplier 28. The multiplier 28 receives the signal x(t) directly, via path 29, and via path 30, which includes the delay 24 and phase shifter 26. The output of the multiplier 28 is connected to the zonal LPF 32. The output of the zonal LPF 32 is y(t)=sin[Δ(T)] where Δ(T) = (t) - (t-T). Thus Δ(T) represents the change in phase of the signal x(t) over a one symbol time interval. The function sin[Δ(T)] represents the sine of the change of phase of the signal x(t) over a one symbol time interval. The output of the zonal LPF 32 goes to a decision circuit 34. The decision circuit outputs logic 1's and 0's according to the decision rule sin[Δ(T)] > 0 output logic 1 sin[Δ(T)] < 0 output logic 0 A transmitter and a detector for GMSK signals such as the transmitter 10 of FIG 1 and the detector 20 of FIG 2 is disclosed in Marvin K. Simon et al., "Differential Detection of Gaussian MSK in a Mobile Radio Environment", IEEE Transactions on Vehicular Technology, Vol. VT-33, No.4, November 1984, page 307. One problem with the detector 20 of FIG 2 is that an offset frequency will degrade the bit error rate performance. However, in the DECT standard an offset of ± 50 kHz is acceptable. If ω IF = 8πf b + Δω = 8πf b + 2πΔf, where Δf is the frequency offset, then the output of the zonal filter 32 is y(t) = sin[2πΔf/f b + Δ(T)] The signal y(t) is now the sine of the change in phase of the signal x(t) over a one symbol time interval plus a frequency offset term. Thus, the signal used by the decision circuit 34 to decide between logic "1" and logic "0" is distorted due to the frequency offset. This distortion will degrade the bit error rate performance of the detector. Furthermore in Marvin K. Simon et al., "on the implementation and performance of single and double differential detection schemes", IEEE Transactions on Communication, Vol. 40 (1992) February No. 2, pages 278-291, a Doppler-corrected differential detection system is disclosed. There it is disclosed that the change in phase of a received MDPSK signal over a full symbol contains both the differently encoded data and the Doppler induced phase shift. The phase over half a symbol, however, contains only the Doppler induced phase shift and the Doppler effect can be estimated and removed from the incoming signal. In view of the foregoing, it is an object of the present invention to provide a one bit differential detector for a GMSK signal which eliminates the distortion caused by frequency offset. More particularly, it is an object, of the present invention to modify the detector circuit 20 of FIG 2 to eliminate the dependence on the offset frequency of the output of the zonal filter 32. In accordance with the present invention, a one bit differential detector for a GMSK signal which is independent of any offset frequency is provided according to claim 1. In particular, a decision signal used by a decision circuit to decide between logic "0" and logic "1" is always proportional to sin[Δ(T)] independently of the presence of any offset frequency. The inventive detector has an improved bit error rate performance in comparison to the prior art. FIG 1 schematically illustrates a prior art GMSK transmitter. FIG 2 schematically illustrates a prior art GMSK detector. FIG 3 schematically illustrates an improved GMSK detector according to the invention. FIG 4 illustrates a filter for determining an expectation value for use in the detector of FIG 3. FIG 5 illustrates a 90° phase shifter for use in the detector of FIG 3. FIG 6 illustrates an alternate improved GMSK detector according to the invention. A one bit differential detector for a GMSK signal which is independent of a frequency offset is illustrated in FIG 3. In the detector 40 of FIG 3, a GMSK signal arrives at an Automatic Gain Control (AGC) device or hard limiter 42 which outputs the signal x(t). As in the case of the prior art detector 20 of FIG 2, the signal x(t) is bandwidth limited and has a normalized envelope for all t. The detector 40 has two paths. The path I is identical to the processing path of the prior art detector 20 of FIG 2 and comprises the unit delay 24, the 90° degree phase shifter 26, the multiplier 28 and the low pass filter 32. The multiplier 28 receives the signal x(t) directly and via the delay 24 and 90° phase shifter 26. The output of the low pass filter 32 is the signal y 1 = sin[2πΔf/f b +Δ(T)] As indicated above, the signal y 1 , is equal to the sine of the change in phase of the signal x(t) for one symbol time interval plus a frequency offset term. Note that the cutoff frequency f cut-off of the filter 32 of FIG 3 is 4f b and the gain is 2. Path II and the rest of the circuitry has been added to the detector 40 of FIG 3 to eliminate the frequency offset term from the signal y 1 . Thus, the overall output signal which is then inputted to the decision circuit 34 is u(t) = sin[Δ(T)] As can be seen, the frequency offset term has been eliminated from this signal. The path II includes the unit delay 24, the multiplier 43 and the low pass filter (LPF) 44. The filter 44 has a cut-off frequency f cut-off = 4f b and a gain of 2. The inputs to the multiplier 43 are the signal x(t) and the signal x(t) as delayed by the unit delay 24. The output of the multiplier 43 is inputted to the filter 44. The output of the filter 44 is y 2 (t) = cos [2πΔf/f b +Δ(T)] The signal y 2 is equal to the cosine of the change of phase of the signal x(t) in one symbol time interval plus a frequency offset term. Thus, to summarize the discussion thus far, the following signals have been considered x(t) = cos[ω IF t+(t)], ω IF = 8πf b + 2πΔf y 1 (t) = sin [2πΔf/f b + Δ(T)] y 2 (t) = cos [2πΔf/f b + Δ(T)] Using the approximation Δf/fb is small, the expression for the signal y 1 becomes y 1 (t) = (2πΔf/f b )cos[Δ(T)]+sin[Δ(T)] The filter 46 is now used to calculate y 1 = E[y 1 (t)], where E is the expectation value, i.e., longterm average. The expectation value E[y 1 (t)] is evaluated as follows: y 1 = E[y 1 (t)]=(2πΔf/f b ) E[cos[Δ(T)]]+E[sin[Δ(T)]] For one bit differential detection Δ(T) = Δ k = b k-1  -1 + b k  0 + b k+1  1 The following chart corresponds total possible combinations for BT=0.5. Coefficient Combination Δ(T) b k-1 b k b k+1 1 1 1 90° -1 1 1 73.7° 1 1 -1 68.1° -1 1 -1 51.8° 1 -1 1 -51.8 -1 -1 1 -68.1° 1 -1 -1 -73.7° -1 -1 -1 -90° Note that the first four entries of the chart correspond to b k =1 and the last four entrees correspond to b k =-1. To evaluate E[cos[Δ(T)]] and E[sin[Δ(T)]], it is assumed that all combinations are equally likely. Thus, because sin[Δ(T)] is an odd function, E[sin[Δ(T)]]=0. The function cos[(T)]is an even function so that E[cos[Δ(T)]] = [cos 90° + cos 73.7° + cos 68.1°+ cos 51.8°] (1/4) = 0.318. Thus, the signal at the output of the filter 46 is y 1 = (2πΔf/f b ) (0.318) The multiplier 47 multiplies y 1 by (1/.318) to obtain the signal y 1 = 2πΔf/f b . The multiplier 48 multiplies y 2 (t) by y 1 to obtain z(t) = y 2 (t) y 1 ≈ (2πΔf/f b ) cos[Δ(T)] Then the subtraction element 49 obtains u(t) = y 1 (t) - z(t) = sin[Δ(T)] as desired. The signal u(t) is then inputted into the decision circuit 34 which decides between logic "1" and logic "0". The low pass filter 46 of FIG 3 for determining E[y 1 (t)] is illustrated in greater detail in FIG 4. The filter 46 of FIG 4 comprises a Butterworth low pass filter 52 and a low pass filter 54. The lowpass filter 54 comprises the weighting elements 55 and 56, the unit delay 57 and the adder 58. The transfer function of the Butterworth filter is 1 + 2 z -1 + z -2 1-1.993692172 z -1 + 0.9937315894 Z -2 - • 1 + z -1 1-0.9937315276 z -1 The transfer function for the lowpass filter is 0.00001 1-0.99999z -1 The 90° phase shifter 26 may be implemented as shown in FIG 5. The phase shifter 26 comprises two paths 61 and 62. In the path 61 the signal is advanced one sample, in path 62 the signal is delayed one sample, then the signals are combined using the summer 63. An alternative one bit differential GMSK detector which eliminates the influence of an offset frequency is illustrated in FIG 6. The detector 100 of FIG 6 does not rely on the assumption that Δf/f b is small. The detector 100 includes the same path I and path II as the detector 40 of FIG 3. Thus, the filter 32 of path I outputs y 1 (t) = sin [2πΔf/f b + Δ(T)] The filter 44 of path II outputs y 2 (t) = cos [2πΔf/f b + Δ(T)] It can be shown that sin[Δ(T)] = -sin[2πΔf/f b ]y 1 (t) + cos[2πΔf/f b ]y 2 (t) The processing circuitry 110 performs this calculation. More specifically, to perform the calculation, the circuitry 110 includes the filter 112 for performing E[y 1 ] where E[y 1 ] = sin(2πΔf/f b )E[cosΔ(T)]=Csin(2πΔf/f b ) The filter 114 performs E[y 2 ] where E [y 2 ] = cos(2πΔf/f b )E[cosΔ(T)] = Ccos(2πΔf/f b ) where C is a predetermined constant equal to 0.318 for the case BT = 0.5. The multipliers 116 and 118 perform y 1 E[y 2 ] and y 2 E[y 1 ] respectively. The results are then subtracted using the subtraction element 120 and multiplied by (1/C) in the multiplier 122 to obtain the desired output result. To summarize, a one bit differential GMSK detector has been disclosed. The inventive detector eliminates the distortions caused by offset frequency to improve the bit error rate performance. Finally, the above-described embodiments of the invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.

Claims: A one bit differential detector (40,100) for a GMSK signal of the form x(t)=cos(ω IF t + (t)) wherein ω IF =2π(f IF +Δf),f IF is an intermediate frequency of x(t), Δf is a frequency offset of f IF , and (t) is a phase, said detector (40,100)comprising: a first signal processing path (I) for outputting a signal y 1 = sin(2πΔf/f b +Δ(T)), where f b is a baseband signal frequency and Af is small compared to f b , and Δ(T) is a change in phase of x(t) over a one symbol time period, and which signal y 1 is proportional to the sine of a change of phase of the signal x(t) over a one-symbol time interval plus a frequency offset term, a second signal processing path (II) for outputting a signal y 2 =cos(2πΔf/f b +Δ(T)), which signal y 2 is proportional to the cosine of the change of phase of the signal x(t) over a one symbol time interval plus a frequency offset term, and signal processing means connected to said first and second signal processing paths (I,II) and being connected to receive signals y 1 and y 2 and configured to output an output signal u(t)=sin(Δ(T)), which output signal is proportional to the sine of the change of phase of the signal x(t) over one symbol time interval and independent of said frequency offset, said signal processing means comprising: (a) means (46,47,48) for generating a signal proportional to said frequency offset term of said signal y 1 , wherein the signal proportional to said frequency offset term of said signal y 1 equals z(t) and z(t) being approximated as equal to (2πΔf/f b )cos (Δ(T)) (b) means (49) for subtracting said signal proportional to said frequency offset from said signal y 1 to generate said output signal u(t). The detector (40,100) of claim 1 wherein said first signal processing path (I) comprises, a one period delay unit (24) for receiving said signal x(t), a 90° phase shifter (26) connected to said one period delay (24) unit having an output signal x 1 (t), a multiplier (28) for directly receiving said signal x(t) and for receiving said output signal x 1 (t) of said phase shifter wherein said multiplier (28) has an output signal x(t)*x 1 (t)=sin(ω IF T+Δ(T)), and a low pass filter (32) connected to an output of said multiplier (28) for receiving said output signal x(t)*x 1 (t) of said multiplier (28) and for outputting said signal y 1 . The detector (40,100) of claim 1 wherein said second signal processing path (II) comprises: a one period delay unit (24) for receiving said signal x(t), a multiplier (43) connected to receive said signal x(t) directly and to receive an output of the one period delay unit (24), and a low pass filter (44) connected to an output of said multiplier (43) for outputting said signal y 2 . The detector (40,100) of claim 1 further comprising a decision circuit (34) for receiving said output signal u(t) from said signal processing means and for generating logic 1's and logic 0's in response thereto. The detector (40,100) of claim 1 wherein said means for generating said signal proportional to the frequency offset term of the signal y 1 comprises a filter (46) for obtaining an expectation value of the signal y 1 . The detector (40,100) of claim 5 wherein said means for generating said signal proportional to the frequency offset term of the signal y 1 further comprises: a first multiplier (47) for multiplying the expectations value by a constant factor, and a second multiplier (48) for multiplying the signal y 2 , by an output of the first multiplier for generating said signal proportional to said frequency offset term. The detector (40,100) of claim 1, wherein said signal processing means comprises: first and second filters (112,114) for obtaining the expectation values of E(y 1 ) and E(y 2 ) of said signals y 1 and y 2 , a first multiplier (116) for multiplying y 1 and E(y 2 ) a second multiplier (118) for multiplying y 2 and E(y 1 ), and a subtractor (120) for obtaining the difference of an output from said first multiplier (116) and the output from said second multiplier (118).

Inventors: HUANG YUNG-LIANG, LU CHUNG H, SHIH JUNE-DAN, YU JI-SHANG, HUANG, YUNG-LIANG, LU, CHUNG H., SHIH, JUNE-DAN, YU, JI-SHANG
Applicants: IND TECH RES INST, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Application year: 1993
Main classification: H04L27
IPC codes: H04L27