NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING FLOATING GATE

Abstract: A flash memory includes a semiconductor substrate having a first conductivity type; a first well having a second conductivity type opposite to the first conductivity type, and so formed on the surface of the semiconductor substrate as to be contained in the semiconductor substrate; a second well having the first conductivity type and so formed on the surface of the first well as to be contained in the first well; a plurality of memory cells formed in the second well, each having a floating gate; and an erase portion for erasing charge stored in the memory cells by dissipating it into the channel region of the second well through a tunnel insulating film. The erase portion applies a first erase signal to the first well in response to a start signal instructing the start of erase, applies a second erase signal having the same polarity as that of the first erase signal to the second well, and the first erase signal is applied earlier than the second erase signal.

Description: TECHNICAL FIELD The present invention generally relates to electrically erasable non-volatile semiconductor memory devices (EEPROMs), and more particularly to a so-called flash memory that stores information in the form of electric charges accumulated in a floating gate. BACKGROUND ART Recently, intensive efforts are being made on research and development of so-called flash memories. Flash memories, having a compact and solid construction, are expected to replace bulky and fragile conventional hard disk devices in various computers including laptops. As each memory cell in the flash memory is formed of a single transistor similar to the memory cell transistor of conventional dynamic random access memories, flash memories can easily realize high integration density and large storage capacity. Further, flash memories lack movable parts such as driving motors and consume little electric power. In flash memories, each memory cell has a construction similar to a MOS transistor and includes a source region and a drain region formed in a semiconductor substrate. Further, there is provided a floating gate between the substrate and a control electrode such that the floating gate is insulated by a thin tunneling insulation film, wherein the control electrode corresponds to the gate electrode of conventional MOS transistors. When storing information, a predetermined control voltage is applied to the gate electrode. Thus, carriers flowing from the source region to the drain region are accelerated in the vicinity of the drain region and are injected to the floating gate through the aforementioned tunneling insulation film. The carriers and hence the electric charges thus injected to the floating gate are held therein stably and urge the potential level of the floating gate at a predetermined level. As a result, the flow of carries from the source to the drain is controlled on and off by the carries stored in the floating gate. In other words, it is possible to read the electric charges and hence the information stored in the floating gate by detecting the drain current of the memory cell transistor. When erasing information thus stored, a potential is applied to the control electrode such that the electric charges in the floating gate are expelled, simultaneously to a potential that is applied to the semiconductor substrate or to the source region in the substrate, for extracting the electric charges from the floating gate. As a result, the electric charges in the floating gate are dissipated, through the aforementioned tunneling insulation film, either to the semiconductor substrate or to the source region in the substrate. FIG.1 schematically shows the construction of the memory cell in the conventional flash memory described above. Referring to FIG.1, the memory cells are formed on a semiconductor substrate 10, which may be doped to the p-type for example, in rows and columns, wherein each of the memory cells includes an n + -type source region 11a and an n + -type drain region 11b on the substrate 10 such that the regions 11a and 11b are separated from each other by a p-type channel region 10a interposed therebetween. The part of the semiconductor substrate 10 corresponding to the channel region 10a is covered by a tunneling insulation film 12a, and a floating gate electrode 12 is provided on the tunneling insulation film 12a. Further, the gate electrode 12 is covered by an interlayer insulation film 13a, and a control electrode 13 is provided on the interlayer insulation film 13a. When storing information, a negative source voltage Vs is applied to the source region 11a, and a positive drain voltage Vd is applied to the drain region 11b, such that electrons flow from the source region 11a to the drain region 11b through the channel region 10a. Further, a positive control voltage Vg is applied to the control electrode 13. Thereby, the electrons flowing from the source region 11a to the drain region 11b are accelerated in the channel region 10a and acquire a large kinetic energy in the vicinity of the drain electrode 11b. The electrons accelerated are injected to the floating gate 12 after transit through the tunneling insulation film in the form of Fowler-Nordheim tunneling current that is caused to flow as a result of the positive voltage of the control electrode 13. The electrons thus injected to the floating gate 12 are held stably therein with little leak, even when the power is shut off. When negative electric charges are thus accumulated in the floating gate 12, the MOS transistor formed between the source region 11a and the drain region 11b no longer turns on due to the negative charges of the floating gate 12, even when a control voltage Vg is applied to the control electrode 13 so as to cause a turning-on of the MOS transistor. Thus, by detecting the drain voltage Vd, it becomes possible to read the information stored in the memory cell. When updating or erasing information stored in a memory cell, the control voltage Vg applied to the control electrode 13 is set to a large negative voltage. Simultaneously, a positive voltage is applied to the substrate 10 as a substrate voltage. Alternatively, a positive voltage is applied to the source region 11a as the source voltage Vs. As a result, the electrons accumulated in the floating gate 12 are expelled to the substrate 10 or to the source region 11a provided in the substrate 10. As a result, the information stored in the memory cell is erased. FIG.2(A) shows the operation of a flash memory cell of the so-called channel erase type wherein the electrons in the floating gate 12 are dissipated to the substrate 10 when erasing information. Further, FIG.2(B) shows the setting of the source voltage Vs, the drain voltage Vd, the control voltage Vg and the substrate voltage V SUB for each of the writing, reading and erasing mode for the memory cell of FIG.2(A). In the drawing, the tunneling insulation film 12a and the interlayer insulation film 13a are omitted for the sake of simplicity. Referring to FIG.2(B), a large negative voltage V MM is applied to the control electrode 13 in the erase mode. Simultaneously, a positive supply voltage Vcc is applied to the substrate 10. As a result, the electrons in the floating gate 12 are dissipated to the substrate 10 along a path (1) shown schematically in FIG.2(A). In this process, the source region Vs and the drain region Vd assume an opened or floating state. When in the write mode, on the other hand, the control voltage Vg applied to the control electrode 13 is set to a large positive voltage V PP . Simultaneously, the source region 11b is grounded (Vs = 0 V) and the positive supply voltage Vcc is applied to the drain region 11b. As a result, the electrons are caused to flow from the source region 11a to the drain region 11b, and accelerated electrons are injected to the floating gate 12 in the form of tunneling current, after passing through a path (2) schematically shown in FIG.2(A). In the read mode, on the other hand, the supply voltage Vcc is applied to the control electrode 13 via a selected word line, and the drain voltage Vd is set to a positive voltage of about 1 V. Further, the source region 11a and the substrate 10 are grounded (Vs = 0 V). As a result, the electrons flow from the source region 11a to the drain region 11b in the case where there is no electron accumulation in the floating gate 12 and the transistor of FIG.2(A) is turned on. When the electrons are accumulated in the floating gate 12, on the other hand, the flow of electrons through the channel region 10a does not occur due to the electric charges of the electrons. In other words, the transistor of FIG.2(A) does not turn on. Thus, by detecting the change of the drain voltage Vd caused as a result of the turning-on and turning-off of the foregoing transistor by means of a sense amplifier, it becomes possible to read the information stored in the floating gate 12. FIGS.3(A) and 3(B) show the construction and operation of a flash memory cell that causes a dissipation of the electric charges of the floating gate 12 to the source region 11a, not to the substrate 10, when erasing information. Similarly to FIG.2(A), the tunneling insulation film 12 and the interlayer insulation film 13a are omitted in FIG.3(A). As the write mode operation and the read mode operation of the memory cell of FIGS.3(A) and 3(B) are identical with those of the memory cell of FIGS.2(A) and 2(B), only the erase mode operation will be described below. Referring to FIG.3(B), the source voltage Vs applied to the source region 11a is set to the positive supply voltage Vcc in the erase mode. Further, the control voltage Vg applied to the control electrode 13 is set to the negative high voltage V MM . On the other hand, the substrate 10 is grounded and the substrate voltage V SUB is set to 0 V. Further, the drain region 11b is set to an opened state. As a result, the electrons in the floating gate 12 are dissipated to the source region 11a along the path (1) shown schematically in FIG.3(A). In any of the device of FIGS.2(A) and 2(B) and the device of FIGS.3(A) and 3(B), unwanted erase of memory cells is avoided by applying the positive supply voltage Vcc to the memory cell not to be erased, as the control voltage Vg. FIG.4 shows an example of the flash memory that uses the memory cell of FIG.2(A). Referring to FIG.4, the flash memory includes an n-type well 10A formed in the p-type substrate 10, wherein another, p-type well 10B is formed within the n-type well 10A. In the p-type well 10B, n + -type diffusion regions are formed in correspondence to the source region 11a and the drain region 11b of FIG.2(A), and a number of floating electrodes 12 as well as control electrodes 13 are arranged in rows and columns. By forming a memory cell in the well 10B and applying an erase voltage V PW to the well 10B, it becomes possible to achieve simultaneous erase of information in each of the wells. As such a double well structure, which includes the n-type well 10A and the p-type well 10B, forms a parasitic pnp transistor when constructed on a p-type substrate such as the substrate 10 of FIG.4, it is necessary to apply a voltage V NW to the n-type well 10A when applying the erase voltage V PW to the well 10B, in order to avoid the conduction of the transistor. FIG.5 shows the circuit construction of the flash memory shown in FIG.4. Referring to FIG.5, it will be noted that memory cells C, each having the construction of FIG.2(A), are disposed in rows and columns on the well 10B, which in turn is formed on the semiconductor substrate 10 shown in FIG.4, wherein those memory cells C aligned in the row direction have respective control electrodes 13 connected commonly with each other by a word line WL. On the other hand, those memory cells aligned in the column direction have respective drain regions 11b connected commonly with each other by a bit line BL. The word line WL is selected, via an address buffer 23 and a row decoder 24, in response to the row address data supplied to the flash memory device, and the control voltage Vg shown in FIG.2(B) is applied to the selected word line WL. Particularly, the row decoder 24 supplies, in the erase mode, the negative erase voltage V MM shown in FIG.2(B) exclusively to the selected word line WL, based upon the supply voltage supplied from a decoder power supply circuit 25. The row decoder 24 further supplies the normal, positive supply voltage Vcc to the unselected word line WL in order to avoid unwanted erase. As a result, only those memory cells C that are connected to the selected word line are erased simultaneously. In other words, the memory cells of the selected memory cell block are erased simultaneously. In the construction of FIG.5, it will be noted that each bit line BL is provided with a corresponding column selection transistor T, wherein the column selection transistor T is selectively turned on and turned off via a column address buffer 21 and a column decoder 22, based upon column address data supplied to the column decoder 22. Each bit line BL is connected to a common data line DL via a corresponding column selection transistor T, and an ordinary sense amplifier 27 connected to the line DL discriminates the logic value of the information read out from the selected memory cell C that has been selected in response to the supplied address data. The output of the sense amplifier 27 is supplied via an input/output buffer 28 to an output terminal. Further, there is provided a write amplifier 26 in connection to the line DL for supplying an information signal, which has been supplied via the input/output buffer 28, to a selected bit line BL via the switch transistor T. Further, the circuit of FIG.5 includes an erase power supply circuit 29 for applying the erase voltages V NW and V PW to the wells 10A and 10B of FIG.4 in the erase mode, in addition to the foregoing circuits. FIG.6 shows a block diagram of a flash memory that uses the memory cell of FIGS.3(A) and 3(B). As the flash memory of FIG.6 has a construction generally identical to the device of FIG.5, those parts of FIG.6 corresponding to FIG.5 are designated by the same reference numerals and the description thereof will be omitted. In the flash memory having a construction of FIG.6, the source regions of each memory cell transistor C are connected commonly to an erase power supply circuit 29', while the erase power supply circuit 29' produces a source voltage Vs as indicated in FIG.3(B). In correspondence to this, the decoder circuit 25 supplies the erase voltage V MM to the selected word line WL and the positive supply voltage Vcc to the unselected word line WL. Meanwhile, the flash memories of the type that erases information by causing a dissipation of electric charges to the substrate, have the problem of the wells 10A and 10B forming a parasitic bipolar transistor with the substrate 10, as already explained. Thus, in order to avoid turning-on of the parasitic bipolar transistor, it is necessary to apply a suitable biasing to the substrate 10 as well as to the wells 10A and 10B. Conventionally, the bias voltage V NW applied to the well 10A and the bias voltage V PW applied to the well 10B, have been set equal to the positive supply voltage Vcc. On the other hand, the existence of parasitic resistances 10A and 10B in the p-type well 10A and in the n-type well 10B raises a problem that there may occur a transient state wherein the parasitic bipolar transistor turns on. When such a turning-on of the parasitic bipolar transistor occurs, the operation of the flash memory becomes unstable. It should be noted that the construction to apply the so-called anti-disturb voltage, with the magnitude of about Vcc, to unselected word lines to avoid unwanted erasing of information in unselected memory cell blocks, is employed not only in the flash memories of the type to cause the dissipation of electric charges to the substrate in the erase mode but also in the flash memories in which the electric charges are dissipated to the source region. On the other hand, such a construction has a problem that there may occur a transient state wherein the anti-disturb voltage is not effectively applied. In such a case, there is a risk that the information that should be retained are unwantedly erased from the memory cell. Further, the flash memories of the type shown in FIG.4 that dissipate electric charges in the floating gate 12 to the well 10B in the erase mode, tend to show a problem that the p-n junction, formed between the well 10B and the n-type diffusion region 11a that forms the drain region or source region, is subjected to a forward biasing in the erase mode. When this occurs, the bit line BL as well as the source region are charged to the level of the supply voltage Vcc. Further, in the flash memories having the construction to dissipate electric charges in the floating gate to the source region 11a in the erase mode as shown in FIG.3(A), there arises a problem in that the drain region 11b assumes an opened state in the erase mode. Further, the anti-disturb voltage is applied to the unselected word lines in this state. Thus, while it is possible to dissipate the positive electric charges of the Vcc level on the bit line BL by turning the memory cell transistor on, there occurs a problem in that the electrons are accelerated in the channel region 11a during the dissipation process as they travel from the source region 11a to the drain region 11b (see FIG.3A) and injected to the floating gate 12 in the form of tunneling current. In other words, there may occur an unwanted writing of information into the floating gate while conducting a discharging of the bit line BL in the construction of FIG.3(A). A non-volatile semiconductor memory device according to the upper clause of claim 1 is known from TOSHIKATSU JINBO ET AL: 'A 5V-ONLY 16 MB FLASH MEMORY WITH SECTOR-ERASE MODE' IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, vol. 35, 1 February 1992, pages 154-155, 271, XP 000315799. DISCLOSURE OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel and useful non-volatile semiconductor memory device wherein the foregoing problems are eliminated. Another object of the present invention is to provide a non-volatile semiconductor memory device having a floating gate for storing information in the floating gate in the form of electric charges, wherein a stable operation is guaranteed even in the transient state. These objects are achieved by the features of claim 1. According to the present invention, it is ensured to apply a reverse biasing to the p-n junctions formed between the substrate and the first well and between the first well and the second well, by applying the erase voltage first to the first well. As a result, the problem of unstable operation of the flash memory, caused by the transient turning-on of the bipolar transistor formed on the substrate by the first and second wells, is successfully eliminated. Further features and advantages of the present invention will become apparent from the following description of the preferred embodiment when read in conjunction with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a diagram showing the fundamental construction of a conventional flash memory; FIGS.2(A) and 2(B) are diagrams for showing the construction and operation of a conventional flash memory that dissipates electric charges to a substrate when erasing information; FIGS.3(A) and 3(B) are diagrams for showing the construction and operation of a conventional flash memory that dissipates electric charges to a source region when erasing information; FIG.4 is a diagram showing the construction of a substrate used in the flash memory of FIGS.2(A) and 2(B); FIG.5 is a circuit diagram showing the circuitry of the flash memory of FIG.4; FIG.6 is a circuit diagram showing the circuitry of the flash memory of FIGS.3(A) and 3(B); FIG.7 is a circuit diagram showing the construction of a timing circuit used in a flash memory according to a first embodiment of the present invention; FIGS.8(A) - 8(C) are diagrams showing the operational timing of the circuit of FIG.7; FIG.9 is a flowchart showing the erasing mode operation of the flash memory of the first embodiment of the present invention; FIG.10 is a circuit diagram showing the construction of the flash memory according to a second embodiment of the present invention; FIGS.11(A) and 11(B) are diagrams showing the construction and operation of the word decoder used in the circuit of FIG.5 or FIG.10; FIG.12 is a diagram showing the timing for discharging the bit line in the circuit of FIG.10; FIG.13 is a circuit diagram showing the construction for obtaining the timing shown in FIG.12; FIG.14 is a circuit diagram showing an example a construction for discharging the bit line in the flash memory of FIG.5; FIG.15 is a circuit diagram showing the construction of the circuit that is used in the circuit of FIG.6 or FIG.10 for setting the timing of the anti-disturb voltage with respect to the erase voltage; FIG.16 is a circuit diagram showing the construction of the circuit that is used in the circuit of FIG.5 for setting the timing of the anti-disturb voltage with respect to the erase voltage; and FIG.17 is a circuit diagram showing the construction for gradually increasing the control voltage applied to the control electrode of the flash memory. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a first embodiment of the present invention will be described. The flash memory according to the first embodiment of the present invention is constructed on the substrate 10 shown in FIG.4 and has a general circuit construction explained with reference to FIG.5. In order to eliminate the transient instability of erase mode operation described in relation to the background art, the present invention uses a timing circuit of FIG.7 for adjusting the timing of the erase voltages V NW and V PW produced by the erase power supply circuit 29 respectively for the wells 10A and 10B on the substrate 10. Referring to FIG.7, the timing circuit is formed of a flip-flop including a NOR gate 113 and a NAND gate 114, wherein the erase voltage signal ERASE produced by the erase power supply circuit 29 is supplied respective first input terminals of the NOR gate 113 and the NAND gate 114. Further, the output signal of the NOR gate 113 is supplied on the one hand to an output terminal via an inverter 115 as an output signal V PW and on the other hand to a second input terminal of the NAND gate 114 via an inverter 112 that has a delay τ. On the other hand, the output signal of the NAND gate 114 is supplied on the one hand to an output terminal via an inverter 116 as an output signal V NW and on the other hand to a second input terminal of the NOR gate 113 via another inverter 111 that has a delay τ. FIGS.8(A) - 8(C) show the timing of the input signal ERASE supplied to the timing circuit of FIG.7 and the timing of the output signals V NW and V PW . Referring to FIGS.8(A) - 8(C), the output signal V NW changes from a level H (high) to a level L (low) upon transition of the logic value of the erase voltage signal ERASE supplied from the erase power supply circuit 29 from a level H to a level L. Further, the change of the output signal V NW is transmitted to the NOR gate 113 after a delay τ by the inverter 111, and the output signal V PW of the gate 113 changes from a level H to a level L after a delay τ from the foregoing transition of the input signal ERASE from the level H to the level L. As long as the level of the signal ERASE is L, the foregoing state is maintained. When the erase voltage signal ERASE changes from the level L to the level H, the output signal of the NOR gate 113 changes immediately from the level L to the level H. Further, the change of the output level of the NOR gate 113 is transmitted to the NAND gate 114 after a delay τ caused by the inverter 112, and the output signal of the NOR gate 113 changes from the level L to the level H after a delay τ from the transition of the signal ERASE from the level L to the level H. In the circuit of FIG.7, the output signal V PW of the NOR gate 113 is applied to the p-type well 10B of FIG.4. On the other hand, the output signal V NW of the NAND gate 114 is applied to the n-type well 10A of FIG.4. By setting the timing of applying the signals V PW and V NW by means of the circuit of FIG.7, it will be noted that the erase voltage is applied always to the well 10A first when conducing erase of information. As a result, the p-n junction formed in the substrate of FIG.4 is always biased in the reverse biased state, and the turning-on of the parasitic bipolar transistors associated with the wells 10A and 10B is effectively suppressed. FIG.9 shows the flowchart of the sequence for applying the erase voltage to the substrate 10 of FIG.4 as a result of use of the circuit of FIG.7. Referring to FIG.9, the erase voltage signal ERASE is produced by the erase power supply circuit 29 in a step S1. Further, in a step S2, the NAND gate 114 produces the erase signal V NW in response to the foregoing erase voltage signal ERASE, and the n-type well 10A in the substrate 10 is biased to the level Vcc for the positive supply voltage. Next, in a step S3, the NOR gate 113 produces the erase signal V PW after a delay τ, and the p-type well 10B in the substrate 10 is biased to the foregoing positive Vcc level. Further, erase of information is conducted in this state in a step S4, wherein the electric charges in the floating gate 12 are dissipated to the substrate 10, more particularly to the p-type well 10B in the substrate 10 after passing through the tunneling insulation film provided under the gate electrode 12. Further, in a step S5, the erase voltage signal ERASE falls, and in response thereto, the erase signal V PW from the NOR gate 113 is canceled in a step S6. Further, in a step S7, the erase signal V NW from the NAND gate 114 is canceled after a delay τ from the moment in which the erase signal V PM is canceled. Next, a second embodiment of the present invention will be described with reference to FIG.10, wherein the circuit of FIG.10 corresponds to the circuit of FIG.5 described with reference to the background art. Thus, those parts described in FIG.10 are designated by the same reference numerals and the description thereof will be omitted. Referring to FIG.10, the flash memory of the present embodiment corresponds to the device shown in FIGS.3(A) and 3(B) that dissipates the electric charges from the floating gate to the source region of the memory cell when erasing information. Thus, the device of FIG.10 uses the erase power supply 29' that is connected commonly to the source regions of the memory cells. Similarly to usual semiconductor memory devices, the flash memory of FIG.10 includes the memory cells arranged in rows and columns on a semiconductor substrate, wherein those memory cells aligned in the row direction have respective control electrodes 13 connected commonly to a word line WL. Similarly, those memory cells aligned in the column direction have respective drain regions connected commonly to a bit line BL. The word line WL is selected by the row decoder 24 based upon the address data supplied to the row address buffer 23, while the bit line BL are selected by the column decoder 22 via the switch transistor T, based upon the address data supplied to the column address buffer 21. Further, each of the switch transistors T is connected the write amplifier 26 and to the sense amplifier 27 via the common data line DL. Further, the write amplifier 26 and the sense amplifier 27 are connected to the data input/output buffer 28. FIG.11(A) shows the construction of the row decoder 24 in the circuit of FIG.10. Referring to FIG.10, the row decoder 21 includes a NAND gate 121 that is supplied with row address data from the address buffer 23, wherein the NAND gate 121 supplies the output to a latch circuit 124 via an N-channel MOS transistor 122 and a P-channel MOS transistor 124 that are held in the conduction state by the supply voltage Vcc and the substrate voltage V SUB . It will be noted that the latch circuit 124 includes a first inverter formed of a P-channel MOS transistor 127 and an N-channel MOS transistor 128 connected in series between a voltage source that supplies a first voltage V 1 and a voltage source that supplies a second voltage V 2 , and a second inverter formed of a P-channel MOS transistor 129 and an N-channel MOS transistor 130 connected in series between the voltage source that supplies the voltage V 1 and the other voltage source that supplies the voltage V 2 , wherein the node in which the transistors 127 and 128 are connected each other, is connected to respective gates of the transistors 129 and 130. Thus, the output signal of the MOS transistor 123 is supplied to the node where the transistors 127 and 128 are connected commonly, as an input signal of the latch circuit 124. Similarly, the node in which the transistors 129 and 130 are connected each other, is connected to respective gates of the transistors 127 and 128. Thus, the latch circuit 124 produces an output signal at the node where the transistors 129 and 130 are connected each other. The output signal of the latch circuit 124 thus obtained is supplied to an output circuit formed of N-channel MOS transistors 125 and 126 connected in series between a voltage source that supplies a voltage V 3 and another voltage source that supplies a voltage V 4 . More specifically, the output signal of the foregoing latch circuit 124 is supplied to the gate of the transistor 125 while the input signal to the latch circuit 124 is supplied to the gate of the transistor 126. The output circuit produces the output signal at the node where the transistors 124 and 125 are connected commonly, wherein the output signal thus obtained is supplied to the word line WL. FIG.11(B) shows the combination of the voltages V 1 , V 2 , V 3 and V 4 used in the circuit of FIG.11(A) for each of the erasing, writing and reading modes. Referring to FIG.11(B), it will be noted that, in the erase mode, the voltage V 1 is set to the supply voltage level Vcc and the voltage V 2 is set to a negative voltage. As a result, the output of the latch circuit 124 corresponding to the word line selected by the row address data, is held at the level Vcc that corresponds to the voltage V 1 , in correspondence to the fact that the output of the NAND gate 121 is held in the low level state. As a result, the transistor 125 is turned on and the transistor 126 is turned off. Thus, a large negative voltage is applied to the word line WL. On the other hand, the output voltage of the latch circuits 124 corresponding to the word lines not selected by the row address data are held at a negative voltage V 2 in correspondence to the high level state of the output of the NAND gate 121. As a result, the transistor 125 of the output circuit does not cause turning-on while the transistor 126 is turned on. Thus, the unselected word lines WL are applied with an anti-disturb voltage with the magnitude of Vcc. In the write mode, on the other hand, the voltage V 1 is set positive while the voltage V 2 is set to the ground level. Thus, the latch circuit corresponding to the selected word line produces a positive voltage, and the transistor 125 of the output circuit turns on in response thereto. On the other hand, the transistor 126 does not turn on because of the low level output of the NAND gate 121. As a result, the voltage V 3 , set to a large positive voltage, is applied to the selected word line WL as a write voltage. On the other hand, the latch circuits 124 corresponding to the unselected word lines supply the voltage V 2 set to the ground voltage level, to the transistor 125 as an output signal, in correspondence to the high level state of the output of the NAND gate 121. Thus, the transistor 125 does not turn on. On the other hand, the transistor 126 is turned on by the high level output of the NAND gate 121, and the unselected word line is set to 0 V corresponding to the ground level. In the read mode, the voltage V 1 is set to the supply voltage level Vcc. Further, the voltage V 2 is set to 0 V corresponding to the ground level. Thus, the latch circuit 124 corresponding to the selected word line supplies the output voltage V 1 set to the supply voltage level Vcc to the output transistor 125, and the transistor 125 is turned on in response thereto. Further, the output transistor 126 turns off in response to the low level voltage signal supplied from the NAND gate 121. As a result, a voltage V 3 set to the supply voltage Vcc is supplied to the selected word line as a read control voltage. On the other hand, the output voltage of the latch circuits corresponding to the unselected word lines is set to the level V 2 which is equal to the ground level. Thus, the output transistor 125 is turned off. On the other hand, the output transistor 126 is turned on in response to the output of the NAND gate 121, and the voltage V 4 set to zero or ground voltage level is supplied to the word line as the read control voltage. It should be noted that the circuit of FIG.10 includes a discharge transistor N in correspondence to each of the bit lines BL for discharging, in the erase mode, the electric charges accumulated on the bit line BL. Each of the transistors N is supplied with a common drive signal S DB and turns on in response to the drive signal S DB . As a result of the turning-on of the transistor N, the corresponding bit line BL is grounded. As a result, the problem of erroneous writing into the memory cell in the read mode conducted subsequently to the erase mode, by the electric charges accumulated on the bit line, is successfully eliminated. In the present invention, the drive signal S DB of the discharge transistor N is supplied with a timing shown in FIG.12, in order to achieve the activation of the discharge transistor N immediately after the end of the erase mode. Referring to FIG.12, the signal S DB is produced substantially in correspondence to the trailing edge of the erase signal and is held in the high level state for an interval corresponding to the time constant of the bit line BL. FIG.13 shows the timing circuit for producing the signal S DB with the timing shown in FIG.12, wherein the timing circuit includes an inverter 131 supplied with the erase voltage signal ERASE, a time constant circuit RC formed of a resistor 132 and a capacitor 133 for integrating the output of the inverter 131, and a NOR gate 134 supplied with the output of the time constant circuit RC and the erase voltage signal ERASE. Thus, the NOR gate 134 produces the high level drive signal with the timing shown in FIG.12, for an interval corresponding to the delay time δ of the time constant circuit RC. It is preferred to set the delay time δ approximately equal to the time constant of the bit line BL. The row decoder of FIG.11(A) is used also in the flash memory of FIG.4 that causes the electric charges in the floating gate 12 to dissipate into the channel region in the substrate 10. In the flash memory having such a construction, too, it will be noted that the bit line BL experiences a charge up in the erase mode, and it is effective to conduct the discharge of the bit line BL by the discharge circuit 30 of FIG.10. FIG.14 shows such a construction. As the construction of FIG.14 is obvious from the foregoing explanations, further description will be omitted. It should be noted that the flash memory having the circuitry of FIG.10 eliminates the unwanted erasing of information in the unselected memory cells by applying, in the row decoder 24 of FIG.11(A), the anti-disturb voltage to the unselected word lines in the erase mode. More specifically, the level of the voltage V 4 is set, in correspondence to the erase voltage signal, to the supply voltage level Vcc as indicated in FIG.11(B). In order to avoid unwanted erase of information in the transient state immediately after the commencement of the erase mode, it is desired to apply the anti-disturb voltage to the control electrode of the corresponding memory cells before the erase voltage is actually applied to the source region of the memory cells. Further, it is desired to cancel the anti-disturb voltage after the erase voltage is canceled. FIG.15 shows the construction of a timing circuit for setting the timing of the anti-disturb voltage with respect to the erase voltage signal ERASE. Referring to FIG.15, the timing circuit has a construction identical with the construction of the timing circuit shown in FIG.7. Thus, description about the construction of the timing circuit will be omitted. In the circuit of FIG.15, the erase voltage signal ERASE is supplied with a timing shown in FIG.8(A), and an anti-disturb signal DIS is formed in response thereto with a timing shown in FIG.8(B). Further, an erase voltage signal ERS supplied to the source region of the memory cell is produces with a timing shown in FIG.8(B). As a result, the voltage V 4 corresponding to the anti-disturb voltage DIS is supplied to the row decoder 24 of FIG.11(A), in advance to the erase voltage signal ERS. FIG.16 shows the construction of the timing circuit for implementing the timing adjustment described with reference to FIG.15, to the flash memory having the construction of FIG.4 or FIG.14. Referring to FIG.16, the illustrated circuit has a construction in which the circuit of FIG.7 is connected to the timing circuit of FIG.15 such that an input terminal of the circuit of FIG.7 supplied with the signal is connected to the output terminal of FIG.15 that supplies the signal ERS. Thus, the anti-disturb signal DIS and the erase voltage signal V NW to be applied to the well 10A cause a transition first in response to the transition of the erase voltage signal ERASE. Next, the signal V PW to be applied to the well 10B causes a transition. As a result, the erase voltage is applied to the substrate without causing a conduction of the parasitic bipolar transistor in the substrate 10. It should be noted that the anti-disturb voltage is applied to the control electrode 13 before the erase voltage is applied to the p-type well in the substrate 10. FIG.17 shows a circuit used in the circuit of FIG.11(A) for producing the erase voltage V3 such that the concentration of electric field to the tunneling insulation film 12a is relaxed. Referring to FIG.17, a large negative voltage corresponding to the voltage V3 is supplied to an input terminal IN, and the negative voltage is supplied to the input terminal of the circuit of FIG.11(A) that receives the voltage V3, via P-channel transistors Tr1 and Tr2. Thus, the transistors Tr1 and Tr2 conduct when the voltage level on the output terminal is lower than the voltage level of the voltage V3 on the input terminal IN. Further, the transistor Tr2 receives, at a gate thereof, positive clock pulses continuously via a capacitor C. As a result, the negative charges accumulated in the capacitor C as a result of the foregoing negative input voltage are periodically neutralized, and the rate of increase of the voltage on the output terminal OUT is reduced. Such a decrease in the rate of voltage rise, in turn, relaxes the concentration of electric field to the tunneling insulation film, and the number of times the flash memory can be updated is increased. The circuit of FIG.17 is applicable to any of the flash memory of FIG.10 and the flash memory of FIG.14. Further, the present invention is by no means limited to those embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention as defined in the claims. INDUSTRIAL APPLICABILITY According to the first aspect of the present invention, one can eliminate the problem of the parasitic bipolar transistor in the substrate being turned on when erasing information from the flash memory. According to the second aspect of the present invention, the problem of erroneous writing of information to the memory cell is avoided by discharging the bit lines after the completion of the erase mode operation. According to a third aspect of the present invention, it is possible to retain information not to be erased, by applying the anti-disturb voltage to those memory cells that hold the information to be retained in advance to the erase voltage and by canceling the anti-disturb voltage after the erase voltage is canceled. Further, according to a fourth aspect of the present invention, it becomes possible to extend the lifetime of the flash memory by gradually increasing the voltage applied to the control electrode of the memory cell in the erase mode for avoiding the concentration of electric field to the tunneling insulation film.

Claims: A non-volatile semiconductor memory device, comprising: a semiconductor substrate (19) having a first conductivity type; a first well (10A) of a second, opposite conductivity type formed on a surface of said semiconductor substrate such that said first well is included in said semiconductor substrate; a second well (10B) of said first conductivity type formed on a surface of said first well such that said second well is included in said first well; a plurality of memory cells (C) provided in said second well, each of said memory cells comprising a tunneling insulation film provided on a surface of said second well in correspondence to a channel region and having a thickness for allowing a tunneling of carriers therethrough; a floating gate electrode provided on said tunneling insulation film so as to be insulated electrically from surroundings; an interlayer insulation film provided on said floating gate electrode; a control electrode provided on said interlayer insulation film; and a pair of diffusion regions of said first conductivity type formed on said second well at both sides of said channel region; and erasing means (29') for dissipating electric charges held in said floating gate electrode into said channel region in said second well through said tunneling insulation film in the form of a tunneling current; characterized in that said erasing means is arranged to apply, in response to a start signal indicative of commencement of erasing, a first erase signal (V NW ) to said first well and a second erase signal (V PW ) having a polarity identical to said first erase signal to said second well, such that said first erase signal is applied in advance to said second erase signal. A non-volatile semiconductor memory device as claimed in claim 1, wherein said erase means (29') is arranged to cancel said first erase signal (V NW ) after canceling said second erase signal (V PW ) in response to an end signal indicating the end of erasing mode operation. A non-volatile semiconductor memory device as claimed in claim 1 or 2, wherein said plurality of memory cells (C) are arranged in rows and columns such that, in each of said columns, the memory cells included in the column have respective drain regions connected commonly by a bit line (BL); and wherein each of said bit lines is provided with a discharging circuit (30) for discharging electric charges accumulated on said bit line, said discharging circuit being activated in response to a rear edge of an erase voltage signal after information stored in said memory cell is erased, said discharging circuit thereby causing a discharge of said bit lines. A non-volatile semiconductor memory device as claimed in claim 3, wherein said discharging circuit comprises a transistor (N) provided between said bit line (BL) and a ground level, and a control circuit (131 - 134) supplied with said erase control voltage for causing said transistor to turn on in response to said rear edge of said erase control voltage, for an interval (δ) corresponding to a time constant of said bit line. A non-volatile semiconductor memory device as claimed in any of claims 1 - 4, wherein said erasing means (29') is arranged to apply an erase control voltage (ERS) to said channel region with a polarity and magnitude such that electric charges held in said floating gate as information are extracted, said erase means (111 - 116) simultaneously applies an anti-disturb voltage (DIS) to said control electrode of said memory cells except for said selected memory cell, for avoiding unnecessary erase of information; wherein said erasing means comprises timing setting means (111 - 114) for canceling said anti-disturb voltage (DIS) upon end of erasing of information, such that said anti-disturb voltage is canceled after said erase control voltage (ERS) is canceled. A non-volatile semiconductor memory device as claimed in claim 5, wherein said timing setting means (111 - 114) is arranged to apply said anti-disturb voltage (DIS), upon commencement of erasing of information, such that said anti-disturb voltage is applied in advance to said erase control voltage (ERS). A non-volatile semiconductor memory device as claimed in any of claims 1 - 6, wherein said erasing means includes internal boosting means (C, Tr 1 , Tr 2 ) for supplying a control voltage to said control electrode of said selected memory cell so as to expel electric charges accumulated in said floating gate electrode, said internal boosting means causing a gradual increase of said control voltage. A non-volatile semiconductor memory device as claimed in claim 7, wherein said internal boosting means comprises current supplying means (Tr 1 , Tr 2 ) supplied with said control voltage from a voltage source for supplying electric charges to said floating gate electrode in response thereto, and leak means (C) supplied with a periodical pulse signal for removing electric charges periodically from said current supplying means in response to said pulse signal.

Inventors: AKAOGI TAKAO, AKAOGI,TAKAO, AKAOGI,TAKAO, FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1993
Main classification: G11C16
IPC codes: G11C16, H01L29, G11C17, H01L27, H01L21