Driver circuit for sinking current to two supply voltages

Abstract: An insulated gate bipolar transistor (IGBT) (43) gate driver circuit with a push-pull output stage which provides current sinking to two power supply rails. Current sinking to a low impedance power supply rail (GND) via a high current NPN bipolar transistor (52) provides fast IGBT turn off. A PNP bipolar transistor (53) forward biased emitter-base junction in series with an N channel field effect transistor (60) provides current-limited current sinking to a higher impedance power supply rail (V EE ) . The on resistance of the N channel field effect transistor (60) can be chosen to set the maximum current drawn from the higher impedance V EE power supply rail. This current-limiting avoids the need for a second low impedance power supply. The transition of the output of the driver from ground to V EE is only a function of the output voltage output by the driver. It is not a function of any timed switching of transistors.

Description: This invention relates to a driver circuit for sinking current to two supply voltages. Reference is now made to Figures 1-3 of the accompanying drawings, in which: Figure 1 (Prior Art) shows the gate-to-collector capacitance C gc which gives rise to a false turn on of an IGBT which may occur when the IGBT is switched off with a conventional driver, Figures 2A-2C (Prior Art) show a relationship between the gate-to-emitter voltage, the collector current, and the collector-to-emitter voltage in the IGBT driven with the conventional driver of Figure 1, Figure 3A (Prior Art) shows an IGBT driven with a CMOS inverter connected between V DD and V EE , and Figure 3B (Prior Art) shows an IGBT driven with a bipolar inverter connected between V DD and V EE . Figure 1 shows a gate driver 1 for driving the gate of a gate insulated bipolar transistor ("IGBT") 2. Such a gate driver should provide a relatively high output voltage of 10 to 15 volts in order to enhance adequately the conductivity of the IGBT so that conduction losses are minimized when the IGBT conducts from collector to emitter. Figure 1 shows a load 3 connected between a positive relatively high supply voltage source V +HV and the collector of the IGBT 2. In order to switch the IGBT off, however, the driver 1 must also be capable of quickly discharging the gate-to-emitter and gate-to-collector capacitances of the IGBT, C ge and C gc , respectively in order to effectively pull down the base of the IGBT 2. A low impedance supply voltage line 4 connects to the emitter of the IGBT to a zero volt ground in order to accommodate the pulse of capacitive discharge current when the voltage on the gate is increased and in order to conduct the high conduction current from the emitter when IGBT 2 is switched on. During switching off of IGBT 2, the voltage on the collector of the IGBT increases rapidly. Figures 2A, 2B and 2C show the gate-to-emitter voltage V ge of IGBT 2 of Figure 1, the collector current I C of IGBT 2 of Figure 1, and the collector-to-emitter voltage V ce of IGBT 2 of Figure 1. As Figures 2A-2C show, the rapid decrease in gate-to-emitter voltage V ge associated with IGBT 2 switching off results in a rapid decrease in collector current Ic as well as a rapid increase in the collector-to-emitter voltage V ce . This rapid increase in the collector-to-emitter V ce voltage causes a temporary increase in the gate-to-emitter voltage V ge , due to capacitive coupling of the gate-to-collector capacitance C gc , of IGBT 2. During the time when the IGBT collector exhibits its highest rate of increase in voltage as seen in Figure 2C, current flow through the gate-to-collector capacitance may exceed the ability of driver circuit to sink current from the gate of the IGBT 2. If the gate-to-emitter voltage momentarily rises above the threshold voltage V t of the IGBT shown in Figure 2A, the IGBT may momentarily switch back on despite the fact that driver circuit 1 is attempting to switch IGBT 2 off. The consequence of this momentary switching on of IGBT 2 when the IGBT is in the process of being switched off is a high conduction current I c and a simultaneous high collector-to-emitter voltage V ce . This high current and high voltage situation results in a large amount of power being dissipated. The IGBT may therefore be pushed beyond its safe operating region resulting in a loss of circuit efficiency and possible device breakdown. Gate driver circuits with low impedance pull down devices are known. Although these drivers are able to sink higher currents from the gate of the IGBT to ground, these drivers nevertheless still result in momentary false turn-on situations due to the decrease of the threshold V t of the IGBT with increasing temperature. Although it is possible to compensate for this decrease in V t with temperature by increasing the threshold of the IGBT, such compensation results in a deleterious decrease in device efficiency during conduction. What is needed is a low impedance pull down gate driver which can pull the potential of the gate of the IGBT below the potential of the emitter of the IGBT. Figures 3A (Prior Art) and Figure 3B (Prior Art) show two such gate driver circuits which drive the gate of the IGBT below the potential of the IGBT emitter. Figure 3A (Prior Art) shows a CMOS inverter driver circuit comprised of an input terminal 31 connected to the gate of a PMOS transistor 32 and to the gate of a NMOS transistor 33. The source of PMOS transistor 32 is connected to +V DD which is, for example, +15 volts. The source of the NMOS transistor 33 is connected to V EE which is, for example, -5 volts. The drain of PMOS transistor 32 is connected to output node 34 which is connected to the gate of an IGBT to be driven 35. The drain of NMOS transistor 33 is also connected to the gate of IGBT 35. The emitter of IGBT 35 is connected to a ground supply voltage GND, for example, 0 volts. Figure 3B (Prior Art) shows a low impedance pull down bipolar inverter driver comprised of input terminal 37 connected to the base of an PNP bipolar transistor 38 and the base of an NPN bipolar transistor 39. The emitter of PNP bipolar transistor 38 is connected to +V DD which is, for example, +15 volts. The emitter of NPN transistor 39 is connected to V EE which is, for example, -5 volts. The collector of PNP transistor 38 is connected to output node 40 which is connected to the gate of an IGBT to be driven 41. The collector of NPN bipolar transistor 39 is also connected to the gate of IGBT 41. The emitter of IGBT 41 is connected to a ground supply voltage GND. The problem with the low impedance pull down gate drivers of Figures 3A and 3B relates to the nature of the V EE supply voltage. The gate drivers of Figures 3A and 3B discharge the capacitive discharge current from the gate of the IGBTs only to the V EE supply voltage. The V EE supply voltage, unlike a ground supply voltage, usually has a relatively high series impedance. The V EE supply voltage is usually generated by an on-chip back bias charge pump circuit. Such charge pump circuits are usually designed to output small amounts of current. Accordingly, large surges of capacitive discharge current drawn from a standard V EE supply may result in a rise in the potential of the V EE supply itself. Although the gate driver is only driving the gate of an IGBT, the equivalent capacitance of the gate of the IGBT may exceed 5000 pF. To switch this large capacitance quickly can require a surge of several amperes of current. As a result, when the gate drivers of Figures 3A and 3B switch to pull the voltage on the gate of the IGBT down to the V EE supply voltage, large surges of current from the V EE supply may overburden the V EE charge pump, thereby causing the voltage supplied by the charge pump to rise several volts above V EE and thereby causing the voltage on the gate of the IGBT to rise. Allowing V EE which powers the gate drive buffer to rise is equivalent to allowing the gate potential to rise. As a result, false turn on of the IGBT may occur despite the negative gate drive circuitry. What is needed is a gate drive circuit which sinks most of the gate drive current to a guaranteed low impedance supply such as ground, yet provides the beneficial noise margins of a negative gate drive to assure that the device remains off as desired under all conditions. Ground, it should be noted, is a guaranteed low impedance supply rail because it must be capable of conducting the potentially large current I c of the IGBT. Compared to this current level, the gate drive current requirements are negligible, (e.g., I gpeak = 2A, I cpeak = 300 A). The present invention therefore provides a gate driver which includes a low impedance high current path between the gate of the IGBT and a ground supply voltage as well as a higher impedance low current path between the gate of the IGBT and a V EE supply voltage. The gate driver initially conducts a relatively high amount of current from the gate of the IGBT to the low impedance ground supply voltage in order to discharge the gate capacitance rapidly to ground potential. The gate driver therefore only need to conduct a smaller magnitude of current from the gate of the IGBT to the higher impedance V EE supply in order to pull the gate of the IGBT from ground potential down to the negative V EE supply voltage. Accordingly, the gate driver of the present invention allows a relatively small, relatively high impedance charge pump circuit to be used as the source of the V EE supply voltage. The invention is further described below, by way of example, with reference to the remaining figures of the accompanying drawings, in which: Figure 4 is a circuit diagram of a first embodiment of the present invention for sinking current to ground for fast turn off of the IGBT and then for sinking current to V EE to prevent false IGBT turn on, Figure 5 is a circuit diagram of a second embodiment of the present invention for sinking current to two supply voltages, ground and V EE , Figure 6A is a circuit diagram of the first stage of current flow in the present invention of Figure 5 when the present invention is pulling the voltage V OUT on the output terminal low, Figure 6B is a circuit diagram of the second stage of current flow in the present invention of Figure 5 when the present invention is pulling the voltage V OUT on the output terminal low, Figure 7 is a graph showing the relationship between the input voltage V IN input into the present invention and the output voltage V OUT output from the present invention onto the output terminal, and Figure 8 is a diagram illustrating polarities in accordance with some embodiments of the present invention. Figure 4 is a circuit diagram of a first embodiment of the gate driver of the present invention. Figure 4 shows an MOS gate driver circuit which sinks current to a low impedance ground GND for fast turn off of the IGBT 43 and which subsequently sinks current to a relatively higher impedance negative voltage source V EE . A first control node C1 controls the voltage of a gate of a P channel field effect transistor 41. The source of transistor 41 is connected to a V DD supply voltage whereas the drain is connected to a node 42. Node 42 is connected to the gate of IGBT 43. The emitter of IGBT 43 is connected to low impedance ground GND. A second control node C2 controls the voltage on a gate of a first N channel field effect transistor 44. The drain of transistor 44 is connected to node 42 whereas the source of transistor 44 is connected to the low impedance ground GND. A third control node C3 controls the voltage on a gate of a second N channel field effect transistor 45. The drain of transistor 45 is connected to node 42 whereas the source of transistor 45 is connected to a relatively high impedance supply voltage V EE . In operation, to raise the voltage on the gate of IGBT 43, the voltage on first control node C1 is lowered when the voltages on second and third control nodes C2 and C3 are low. Transistor 41 therefore switches on to pull the voltage on the gate of IGBT 43 up to V DD while transistors 44 and 45 remain turned off in a nonconductive state. To lower the voltage on the gate of IGBT 43 in order to switch IGBT 43 off, the voltage on first control node C1 is raised to switch transistor 41 off. The third control node C3 is kept low to ensure that transistor 45 remains non-conductive. Once transistor 41 is nonconductive, the voltage on second control node C2 is raised to switch transistor 44 on. The low impedance supply GND is therefore coupled to the gate of IGBT 43 and the voltage on the gate of IGBT 43 is pulled down toward ground GND. Once the voltage on the gate of IGBT 43 has reached ground potential or a voltage substantially close to ground potential, control node C2 is lowered and transistor 44 is switched off. With transistors 44 and 41 in non-conductive states, the voltage on control node C3 can be raised to switch transistor 45 on. When transistor 45 is conductive, a path between the higher impedance supply voltage V EE and the gate of IGBT 43 is established. The voltage on the gate of IGBT 43 is therefore pulled from ground toward the V EE voltage in such a way that all the charge necessary to pull the gate of IGBT 43 to V EE does not need to be provided from the V EE supply. In the circuit of Figure 4, the switching of transistors 41, 44 and 45 are carefully controlled to prevent "shoothrough" or cross-over current to flow from the V DD supply voltage to either the ground GND supply voltage or to the V EE supply voltage. This shoothrough current from V DD to ground will occur if transistor 41 is on for a period of time when transistor 44 is on. Similarly, shoothrough from ground to the V EE supply voltage must be prevented. Such shoothrough current will occur if transistor 44 is on for a period of time when transistor 45 is on. The circuit of Figure 4, therefore, uses precise timing of the voltages on control nodes C1, C2 and C3. Furthermore, if a diode D1 shown in dashed lines in Figure 4 is present in the structure of transistor C2, an additional diode D2 shown in dashed lines is required in order to allow the output voltage on node 42 to drop more than one diode drop below ground. As is apparent from Figure 4, if diode D2 were not present, the voltage on node 42 would not be able to fall more than one diode drop below ground, due to diode D1 conducting current from the supply voltage GND to node 42. Even if diode D2 is provided to block this conduction, control node C3 must still be precisely controlled so that the turning on of transistor 45 will coincide with the time when the voltage on node 42 reaches one diode drop below ground GND. These timing requirements on the control nodes of the structure of Figure 4 render using the design of Figure 4 difficult, especially when temperature variations on the threshold voltages of the transistor are considered. A second gate driver circuit of the present invention for sinking current to two supply voltages is therefore disclosed in Figure 5. This gate driver comprises a first NPN bipolar transistor 51, a second NPN bipolar transistor 52, and a PNP bipolar transistor 53. The collector of transistor 51 is connected to supply voltage V DD . V DD may, for example, be +15 volts. The emitter of transistor 51 is connected to an output terminal 54. The base of transistor 51 is connected to an input node 55. The collector of transistor 52 is connected to output node 54. The emitter of transistor 52 is connected to a low impedance supply voltage GND of, for example, 0 volts. The base of transistor 52 is connected to an intermediate node 56. The emitter of transistor 53 is connected to output node 54, the base of transistor 53 is connected to input node 55, and the collector of transistor 53 is connected to intermediate node 56. A resistance 57 is connected between intermediate node 56 and a relatively high impedance supply voltage V EE . A CMOS inverter drives input node 55. The gate of a P channel field effect transistor 58 is connected to an input terminal 59. The source of P channel transistor 58 is connected to the V DD supply voltage. The drain of P channel transistor 58 is connected to node 55. The gate of an N channel field effect transistor 60 is also connected to input terminal 59. The source of N channel transistor 60 is connected to the V EE supply voltage. The source of the N channel transistor 60 is connected to node 55. In operation, when the voltage on input terminal 59 has been low below the switching point of the CMOS inverter for a period of time, the voltage on node 55 is high at V DD due to the inverting operation of the CMOS inverter. When input node 55 has been at V DD for a period of time, the voltage on output terminal 54 V OUT is within a diode drop of V DD due to the 0.7 forward bias base-to-emitter voltage drop of transistor 51. The voltage on the gate of transistor 53 is also at V DD , so the base of transistor 53 cannot be 0.7 volts higher than the emitter of transistor 53. Transistor 53 therefore cannot be conductive. If transistor 53 is not conductive, resistance 57 pulls intermediate node 56 down toward V EE , thereby pulling the base of transistor 52 down toward V EE . The base-to-emitter voltage of transistor 52 is therefore less than 0.7 volts and transistor 52 remains off. With transistors 52 and 53 switched off and transistor 51 conductive and pulling output terminal 54 up toward V DD , the voltage on node 54 V OUT is pulled high to approximately V DD minus 0.7 volts. When the voltage on input terminal 59 transitions from low to high, the CMOS inverter causes the voltage on node 55 to transition from V DD to V EE . When node 55 transitions to V EE , the voltage on the base of transistor 51 also transitions to V EE . Regardless of the voltage on output terminal 54, the base-to-emitter voltage on transistor 51 cannot be a positive 0.7 volts if the base of transistor 51 is at V EE . Transistor 51 is therefore turned off. This is the situation depicted in Figure 6A. P channel transistor 58 of the CMOS inverter and NPN bipolar transistor 51 are not shown in Figures 6A and 6B because these transistors are not conducting. With the voltage on node 55 being driven down to V EE , and with the voltage on output terminal 54 V OUT having been high at or near V DD minus 0.7 volts, the emitter-to-base voltage V bep of transistor 53 becomes 0.7 volts, a base current I bp flows from the base of transistor 53 through N channel transistor 60 of the CMOS inverter to the supply voltage V EE , and transistor 53 switches on. The magnitude of this base current Ibp is I bp = (V OUT - V EE - 0.7)/Rn where Rn is the drain-to-source on resistance of N channel transistor 60. If the collector current and the emitter current of transistor 53 are assumed to be approximately identical, transistor 53 conducts collector current Icp from output terminal 54 to the V EE supply voltage through resistance 57. With transistor 53 conducting current through resistance 57, a voltage is dropped across resistance 57 and the voltage on the collector of transistor 53 climbs from V EE . Because the base of transistor 52 is connected to the collector of transistor 53, the base of transistor 52 also climbs. Consequently, when the voltage on node 56 reaches 0.7 volts above GND, the base-to-emitter junction of transistor 52 becomes forward biased and a base current I bn flows into the base of transistor 52. Transistor 52 therefore turns on to conduct a relatively large amount of current I cn from output terminal 54 to ground supply voltage GND. Assuming that the current flow through resistance 57 is negligible with respect to the current I bn flowing into the base of conducting transistor 52, the magnitude of current I cn flowing from output terminal 54 to ground supply voltage GND is I cn = β n * I bn = βn * βp * I bp where I cn = βn I bn and where I cp = β p I bp . Assuming that the amount of current flowing through resistor 57 is negligible with respect to I bn , the ratio of current being supplied to the output terminal 54 from the V EE supply voltage to the current being supplied to output terminal 54 from ground supply voltage GND is I bp I cn = I bp βn * βp * I bp = 1 βn * βp The gate driver of the present invention therefore behaves like a Darlington pair having a current gain easily in excess of 10,000. The gate driver of the present invention continues to operate in this mode until the voltage V OUT on output terminal 54 decreases from V DD to a voltage below the sum of the base-to-emitter voltage of NPN transistor 52 V ben and the collector-to-emitter voltage of transistor 53 when PNP transistor 53 is saturated V cep (sat). This voltage is typically about 0.7 to 0.9 volts and is generally well below the threshold voltage V t of an IGBT at room temperature. This voltage decreases at approximately 2.2 mV/°C. Since most IGBTs have a threshold voltage V t which decreases at approximately 2 to 3 mV/°C, the switching off of NPN bipolar transistor 52 will track V t of the IGBT being driven so that NPN transistor 52 will always conduct until the IGBT is turned off. After the NPN transistor 52 turns off, the voltage V OUT on output terminal 54 continues its negative transition due to the forward biased emitter-to-base junction of PNP transistor 53 being in series with the equivalent resistance of the conducting N channel transistor 60 of the CMOS inverter. This is the situation depicted in Figure 6B. The magnitude of the current flow I bp from output terminal 54, through the forward biased emitter-to-base junction of PNP transistor 53, through the drain-to-source on resistance of N channel transistor 60, and to the V EE supply voltage is determined by the equivalent on resistance of N channel transistor 60. Accordingly, the sizing of the N channel transistor 60 can be chosen to limit the maximum current sinking capability of the driver to the V EE supply voltage to match the current sinking capability of a charge pump circuit or any other apparatus generating the V EE supply voltage. When the voltage V OUT on output terminal 54 approaches ground GND potential, the voltage on the collector of conducting transistor 53 drops below 0.7 volts. The voltage across the base-to-emitter junction of NPN transistor 52 therefore falls below 0.7 volts and transistor 52 turns off. Due to the conduction of PNP transistor 53, the voltage on the output terminal 54 continues to decrease toward V EE until voltage V OUT reaches approximately 0.7 volts above V EE . Accordingly, the maximum reverse bias possible across the base-to-emitter junction of NPN transistor 52 is the magnitude of V EE plus 0.7 volts. The voltage swing on the output terminal swings between (V DD - 0.7) volts and (V EE + 0.7) volts. The transition between NPN transistor 52 conducting and PNP transistor 53 conducting is only a function of the voltage V OUT on terminal 54. It is not a function of any timed controlling of transistors. The totem pole, push pull output stage comprising transistors 51 and 52 switches fairly quickly because the only transistor to saturate in the gate driver is PNP transistor 53. Figure 7 shows how the voltage V OUT on output terminal 54 of the driver circuit of Figure 5 varies with various voltages V IN on input terminal 59 of Figure 5. As V OUT drops from (V DD - 0.7) volts at the upper right 70 of the figure, a deadband region 71 is reached where V IN increases but V OUT does not change. Accordingly, neither transistor 51 or 52 is conducting current from output terminal 54 and no shoothrough is possible. There is a full 2V be deadband region that the V IN voltage must pass through when going from low to high or from high to low, in order for the gate driver to switch between transistor 51 and transistor 52 being the conductive transistor. Although the invention has been described by way of the above described embodiments, the scope of the invention is defined by the appended claims. For example, the present invention is not limited to the low-side driving of an IGBT, but may also be used as a high-side or a floating driver. The present invention is amenable to monolithic integration, with or without the charge pump for supplying V EE . The NPN base pull down resistor may also be replaced by a MOSFFT although this implementation complicates the timing considerations. Furthermore, this invention includes a gate driver for driving a P channel IGBT as well as the gate driver for driving an N channel IGBT which is discussed above. The use of the term "ground" in this specification is only meant as a supply voltage. The actual voltage of this "ground" supply voltage may be a voltage other than zero volts. Accordingly, the above description of specific embodiments is presented only for instructional purposes and is not intended to limit the scope of the appended claims which fully define the invention.

Claims: A driver circuit comprising: first means (41, 51) for pulling a voltage on an output node (42, 54) to a first supply voltage (V DD ) when a voltage on a first input node (C1, 55) for receiving a control signal is positive with respect to the voltage on the output node (42, 54); second means (52, 44) for pulling a voltage on the output node (42, 54) to a second supply voltage (GND) when the voltage on the output node (42, 54) is positive with respect to the second supply voltage (GND) and when a voltage on a second input node (C2, 56) is negative with respect to the voltage on the output node; and third means (45, 53, 57) for pulling a voltage on the output node (42, 54) to a third supply voltage (VEE) when the voltage on the output node (42, 54) is negative with respect to the second supply voltage (GND) and when a voltage on a third input node (C3, 55) is negative with respect to the voltage on the output node (42, 54), the first supply voltage (V DD ) being positive with respect to the second supply voltage (GND), and the third supply voltage (VEE) being negative with respect to the second supply voltage (GND). A circuit as claimed in claim 1 wherein the first means for pulling comprises a bipolar transistor (51) having a base coupled to the first input node (55). A circuit as claimed in claim 1 or 2 wherein the third means for pulling comprises a bipolar transistor (53) having a base coupled to the third input node (55). A circuit as claimed in claim 3 wherein the third means for pulling comprises a resistance element (57) connected between a collector of the bipolar transistor (53) and the third supply voltage (VEE), and wherein the second means for pulling comprises a bipolar transistor (52) having a base coupled to the collector (56) of the bipolar transistor (53) of the third means for pulling. A circuit as claimed in claim 1, 2, 3 or 4 having an input terminal (59) and means (58, 60) for buffering an input voltage (V IN ) on the input terminal (59) and for supplying a buffered output signal onto the first and third input nodes (55) the means for buffering being connected to the first supply voltage (V DD ) and to the third supply voltage (VEE). A circuit as claimed in claim 5 wherein the means for buffering comprises a P channel field effect transistor (58) coupled to the first supply voltage (V DD ) and a N channel field effect transistor (60) coupled to the third supply voltage (VEE). A circuit as claimed in claim 5 or 6 wherein the means for buffering comprises a CMOS inverter (58, 60). A circuit comprising: a first transistor (51) having a first terminal coupled to an output node (54), a second terminal coupled to a first supply voltage (V DD ), and a control terminal being coupled to an input node (55). a second transistor having a first terminal coupled to a second supply voltage (GND), a second terminal coupled to the output node (54), and a control terminal coupled to an intermediate node (56); a third transistor having a first terminal coupled to the output node (54), a second terminal coupled to the intermediate node (56), and a control terminal coupled to the input node (55); and a resistance element (57) connected between the intermediate node (56) and a third supply voltage (VEE). A circuit as claimed in claim 8 wherein the first supply voltage (V DD ) is positive with respect to the second supply voltage (GND), and wherein the third supply voltage (VEE) is negative with respect to the second supply voltage (GND). A circuit as claimed in claim 8 wherein the first supply voltag (V DD ) is negative with respect to the second supply voltage (GND), and wherein the third supply voltage (VEE) is positive with respect to the second supply voltage (GND). A circuit as claimed in claim 8, 9 or 10 wherein the first terminals of the first (51), second (52) and third (53) transistors are emitter terminals, and wherein the control terminals of the first (51), second (52), and third (53) transistors are base terminals. A circuit as claimed in claim 8, 9, 10 or 11 comprising an inverter (58, 60) having an inverter input node (59) and an inverter output node (55) being coupled to the control terminal of the third transistor (53), the inverter being connected to the first (V DD ) and third (VEE) supply voltages. A circuit as claimed in claim 12, wherein the inverter comprises a resistance element (Rn) connected between the third supply voltage (VEE) and the control terminal of the third transistor. A circuit as claimed in claim 13 wherein the resistance element (Rn) of the inverter comprises a resistor-connected transistor (60). A circuit as claimed in any preceding claim comprising an insulated gate bipolar transistor (43) having a gate coupled to the output node (42, 54). A circuit as claimed in any preceding claim comprising a charge pump circuit which generates the third supply voltage (VEE). A circuit as claimed in any preceding claim realised on a single integrated circuit chip. A method of driving a transistor (43) having an input terminal (42, 54) comprising the steps of: using a first means (41, 51) for conducting to conduct current between the input terminal (42, 54) and a first supply voltage (V DD ) when a voltage on a first input node (C1, 55) is positive with respect to a voltage on the input terminal (42, 54); using a second means (44, 52) for conducting to conduct current between the input terminal (42, 54) and a second supply voltage (GND) when a voltage on a second input node (C2, 56) is negative with respect to a voltage on the input terminal (42, 54) and when the voltage on the input terminal (42, 54) is positive with respect to the second supply voltage (GND); and using a third means (45, 53, 57) for conducting to conduct current between the input terminal (42, 54) and a third supply voltage (VEE) when a voltage on a third input node (C3, 55) is negative with respect to a voltage on the input terminal (42, 54) and when the voltage on the input terminal (42, 54) is negative with respect to the second supply voltage (GND). A method as claimed in claim 18 wherein the transistor is an insulated gate bipolar transistor (43) having a gate, the input terminal (42, 54) being connected to the gate. A method as claimed in claim 18 or 19 wherein the third means for conducting comprises a resistance element (57) having a magnitude chosen to limit a maximum current flow from the third supply voltage (VEE). A method as claimed in claim 18, 19 or 20 wherein the steps of using the first, second and third means for conducting are performed so that the first means (41, 51) for conducting conducts substantially no current when either of the second (44, 52) and third means (45, 53, 57) for conducting is conducting current. A method as claimed in claim 18, 19, 20 or 21 wherein the method comprises the step of using an inverter (58, 60) to drive the first and third input nodes (55), the inverter being connected to the first supply voltage (V DD ) and to the third supply voltage (VEE) so that a voltage on the first and third input nodes (55) swings substantially between first (V DD ) and the third (VEE) voltages. A method as claimed in claim 22 wherein the inverter comprises an N channel field effect transistor (60) having an on resistance with a magnitude chosen to limit a maximum current flow from the third supply voltage (VEE).

Inventors: CONCKIN BARRY J, WILLIAMS RICHARD K, CONCKIN, BARRY J., WILLIAMS, RICHARD K.
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1993
Main classification: H03K17
IPC codes: H03K17