Digital correction for missing codes caused by capacitive mismatching in successive approximation analog-to-digital converters

Abstract: An ADC, comprising an internal DAC, driven by a successive approximation SAR, and a comparator, is provided with a correction logic circuit that controls the execution of a verifying and correcting routine at the end of each conversion routine. Master-Slave cells that compose the SAR are provided with a dedicated circuitry, responding to said correction control circuit, for confirming, incrementing or decrementing the bit stored in the cell by at least an LSB. An extremely simple routine, performed at the end of each conversion cycle, permits to correct incorrectly converted digital data because of the occurrence of missing codes in the internal DAC. The corrector does not require the use of memories and/or analog circuits and is very cost-effective and permits to greatly improve production yield of complex devices containing ADCs.

Description: The present invention relates to a method and to a relative device for verifying and correcting data resulting from a conversion process of an analog value in a digital value through a so-called successive approximation technique, employing an analog-digital converter (ADC) liable to introduce an error of a certain entity because of the process spread or of other imprecisions in its circuit. Analog-to-digital converters (ADC) are of fundamental importance in control, regulation, data collection and processing systems, by constituting conversion interfaces of analog entities (real-world parameters) in digital data that can be easily processed by digital circuits, such as combinative logic networks, memories, microprocessors and the like. Among these, analog-to-digital converters (ADC), that work according to a technique based on a certain number of successive approximation steps, cover a large portion of applications. The document FR-A-2 349 239 discloses an analog-to-digital converter given by a successive approximation register (SAR). In successive approximation ADCs, an analog input voltage is compared with a voltage that is synthetized by an internal digital-to-analog converter (DAC) contained within the ADC converter. A digital input to said internal DAC is provided by a register (SAR) that stores the current digital value of the successive approximation process, which is updated step by step depending on the result of the last comparison carried out. After a number of comparisons equal to or greater than the number of bits handled by the converter, the data stored in the SAR register represents the digital result of the completed conversion. Commonly, at the start of any new conversion process, a certain code or digital value, for example 100..0, that may represent the intermediate code (value or digital data) as referred to the range of convertible digital values, is provided to the internal DAC. This is effected by "setting" to such an intermediate value the SAR. The result of a first comparison will define the successive content of the SAR which may become for example either 110..0 or 0100..0, and therefore, through successive bi-sections, the code or digital data that represents the converted input analog value will be reached, within the theoretical approximation limit defined by the number of bits of the converter. Fig. 1 is a functional diagram of a successive approximation ADC. As may be observed, the internal DAC may be constituted by an array of capacitances: C, C/2, C/4, C/8 and C/16, that operates a capacitive partition of a reference voltage V REF in order to produce an analog value corresponding to the digital code stored in the SAR. Practically, a capacitance is associated to each bit of the SAR, the capacitance associated with the first bit (MSB or Most Significant Bit) is twice the capacitance that is associated with the second bit, which is twice the capacitance associated with the third bit and so forth, until the so-called LSB (Least Significant Bit). Therefore the analog value produced by the code 0100..0 is double the value that would be produced with the digital code 0010..0 and half the value corresponding to the code 1000..0. A main cause of problems in this type of converters is capacitive mismatching, that is an imprecise ratio among the values of the various capacitances that compose the internal DAC, which causes an incorrect conversion of the current digital value stored in the SAR register in an analog value (by capacitive partitioning of a V REF ). For example, it may occur that, because of an incorrect ratio between the capacitances of the various capacitors that compose the internal DAC, the voltage level or analog value that is associated with a digital code, as for example 100.0, be lower than the analog value corresponding to the digital code 011..1. In such a situation, a so-called "missing code" phenomenon occurs, that is the digital code 011..1 will never be converted by the internal DAC. Such an operating condition, that may be due to the process spread or to some other defect that may have altered the correct design capacitance ratio, is illustrated in Fig. 2B by direct comparison with a correct operating condition illustrated in Fig. 2A. For simplifying the illustration, the schemes refer to the case of a three-bit converter (that is every conversion implies the execution of three comparisons) and show three distinct conversion processes for three different values or codes (010, 011 and 100) representing three different levels in a voltage scale from 0V to 5V (as schematically depicted on the right hand side of the conversion schemes). In the case shown in Fig. 2B, the occurrence of a capacitive mismatching causing an impossibility of converting correctly the code 011 by the internal DAC is shown. Of course, it may also occur that the so-converted level 100..0 be lower than the level 011..10, that is that the mismatching of the capacitance ratio be so marked as to cause the disabling of two adjacent digital codes (values) or even more. Various remedies have been studied and proposed for recovering the functionality of complex integrated circuits containing one or more ADC converters that have revealed themselves defective in the above-noted manner. This has been achieved by suitably modifying the operating characteristic of the internal DAC that has been recognized as defective through a series of specific functionality tests, by the use of dedicated analog circuits (amplifiers, track-and-hold circuits and the like, associated with EPROMs that may be programmed through a correction test and trimming process, and/or ROMs). These known correction systems are relatively complex and greatly penalize the economy of the whole integrated circuit. Digital correction techniques, based on the generation of redundant codes that may be employed for effecting a digital correction capable of reestablishing the functionality of the internal DAC are also known. These correction systems, though not requiring the integration of analog circuits, require the use of RAM and/or EPROM memories capable of storing the necessary information for performing one or more correction procedures during the conversion process. As an alternative to the use of dedicated memories, the correction may also be performed automatically, by the use of an appropriate algorhythm, in function of the redundant bits that are generated. In general, the procedures for detecting missing codes and for correcting a defective converter are relatively complex and require the realization of arrays of trimming elements or the use of a plurality of internal DACs and memories. The volume: "Design of CMOS Analog Integrated Circuits" by F. Maloberti, 1986, Section 8, pages 37-60, contains a brief description of various correction techniques. Several of these techniques permit also to reduce the so-called unadjusted total error (TUE), which accounts also for the input offset of the ADC converter. In a large number of integrated devices containing successive approximation ADCs, as for example in many microcontrollers, the device specifications may not be particularly stringent as far as TUE is concerned; for example they may accept a TUE equal to ±2LSB, but they are typically untolerant of missing codes. Moreover, by analyzing the causes that determined the rejection of a certain percentage of fabricated devices, it may be found that for about 90% of the rejected devices, the cause consisted of a missing code. By analyzing further the rejected devices, a typical "breakdown" of causes may reveal that about 60-70% of the rejections are due to a single missing code occurrence, about 28-38% of rejects are due to the presence of a double missing code, while a residue of about 2% denounces a triple missing code , notwithstanding the fact that a percentage of over 90% of all the rejected devices satisfy the specifications as far as TUE is concerned. Therefore there is an evident need and/or utility for a correction method for missing code, imputable to capacitive mismatching in an internal DAC of a successive approximation ADC, easy to implement by employing exclusively logic circuitry, that practically will permit to avoid the rejection of a relatively large percentage of devices because of the occurrence of a missing code, almost exclusively due to capacitive mismatching in the internal DAC, while satisfying the specifications for what concerns the total unadjusted error (TUE). This objective is fully satisfied by the system of the present invention that can be implemented without requiring the use of memories or of analog circuits for altering the analog structure of the internal DAC. The system of the invention is theorethically capable of correcting also plural missing codes. The eventual choice of implementing in a certain device a "corrector" for a single missing code, for a double missing code or for more than two missing codes, will depend from the yield characteristics of the particular fabrication processes of the device. From the percentages that emerge from an analysis of a typical production, as reported above, it would appear that an optimum design choice would imply the implementation of a corrector, according to the present invention, capable of correcting as far as two adjacent missing codes. This would permit to "recover" to a perfect functionality what would otherwise be, by far, the largest proportion of rejected devices. The occurrence of adjacent missing codes in a number greater than two is statistically not very significant or, whenever it becomes statistically significative, it may almost certainly be an indication that serious problems have occurred in the fabrication process, the occurrence of which would normally tend to bring out of specification limits many other parameters, even less critical than the capacitive mismatching in DACs. Of course, the correction process of the invention, for example for a double missing code, will require the performing of three further comparisons beyond those necessary to the normal conversion process and, in view of the fact that each comparison requires a certain execution time (for example of about 800 ns), the correction procedure implies an increase of the conversion time of about 2-3 microseconds. On the other hand, it is often the case in microcontrollers that the circuits dedicated to the analog-to-digital conversion be amply "margined", i.e. they are often structurally capable of operating (as stand-alone circuits) correctly at clock frequencies that may be well above those actually used by the system, and, in such a frequent case, it is possible, by suitably modifying the timing signals of the converter, to maintain the same conversion times, without requiring any redesigning of the analog part of the comparator circuit. The correction process, for the case of implementing a corrector for a single missing code, consists of the steps (a) to (e) as defined in claim 1. In case of implementing a corrector for a double missing code, the process consists of the steps (a) to (i) as defined in claim 2. The different aspects and advantages of the invention will become more evident through the following description of several important embodiments and by referring to the attached drawings and diagrams, wherein: Figure 1 is a circuit diagram of a successive approximation ADC, as already described above; Figures 2A and 2B are operation schemes of a three-bit ADC converter, correct and incorrect because of the existence of a missing code, respectively; Figure 3 depicts the correction process of the invention of a data produced by a three-bit ADC denouncing the presence of a single missing code; Figure 4 is a flow-chart of the correction process for a single missing code; Figure 5 is a flow-chart of the correction process for two adjacent missing codes; Figure 6 is a block diagram of a successive approximation ADC provided with a corrector according to the present invention; Figure 7 is a partial circuit diagram showing the architecture of the SAR of the ADC of Fig. 6, composed of special cells (V_SARCELL) provided with incrementing and decrementing logic circuitry driven by a control circuit that supervises execution of the correction routine; Figure 8 shows a circuit diagram of V_SARCELL of the SAR of Fig. 7. With reference to the scheme of Fig. 2B, it should be observed that in this particular example the code 011 is not converted giving raise to a so-called missing code situation. According to the present invention, in an ADC it is implemented a correction process that is schematically depicted in Fig. 3 (for four examples of conversions of as many different codes) and which leads to the conversion by the internal DAC of also the missing code 011 (as denounced by the DAC of Fig. 2B). Basically, at the end of each conversion cycle, the digital data produced by the conventional conversion process, stored in the SAR, is decremented by one LSB (Least Significant Bit). The decremented digital value is again converted into an analog value by the internal DAC and the resulting analog value is compared with the input analog value, object of the conversion process. Only if the analog value corresponding to the decremented and converted digital value is less than the input analog value, the digital data stored in the SAR is incremented by one LSB. Viceversa, if the converted analog value is equal or greater than the input analog value, the digital data present in the SAR is no longer modified. As may be observed in Fig. 3, the result of the correction process at the end of a conversion cycle is that also an eventual missing code (011) is virtually converted. The correction process for the case of a corrector for single missing code described above is depicted also in the form of a flow-chart in Fig. 4. If a corrector capable of correcting two adjacent missing codes must be implemented, the correction process becomes the one depicted in the form of a flow-chart in Fig. 5. Fig. 6 is a block diagram of a successive approximation ADC made according to the present invention. As compared with a conventional architecture, the converter is provided with an additional block, CORR, containing the logic circuitry that implements the correction routine. The block KOMP performs the comparison between an input analog voltage and an analog voltage synthetized by the internal DAC and which corresponds to the current digital value stored in the SAR. The array of capacitors for partitioning a reference voltage is contained in the block C_NETZ, while the array of switches for configuring the capacitor array is contained in the block named SWITCH_TREE, which is driven by the SAR. ZYKLUS is a block that generates all the timing signals used in the converter. Of course, according to the present invention, the architecture of the SAR integrates additional logic circuits capable of performing the decrementing and incrementing functions of the digital data stored in the SAR, according to the correction process of the invention, whether it is implemented for correcting a single missing code or for the correction of two or more adjacent missing codes, under the control of the supervising block CORR. A circuit diagram of a ten-bit SAR block of an ADC of the invention of Fig. 6 is shown in Fig. 7. As in the case of a conventional SAR, to all the ten cells, SARCELLØ...SARCELL9, is input the COUT signal that represents the output signal of the comparator KOMP and which therefore carries the information relative to the performed comparison, which, depending on its value, update the digital data stored in the SAR. Also in a modified SAR of the converter of the invention, the same function is performed through the signal COUT, for the first ten comparisons (being the comparator taken into a consideration a ten-bit comparator). At the end of the ten comparisons, the digital data stored in the SAR is updated by means of an increment or a decrement signal, provided by the control block CORR through the signals: INC2, ,INC1, DEC2, DEC1, STOP_0, RST, CTR_CORR≈. The single cells, SARCELL( * ), may have the structure depicted in Fig. 8. Purely for illustrative purposes, the circuit of a cell of a known design, modified in order to implement the corrector system object of the present invention, is shown. Basically, the single cells may be provided with an additional circuitry constituted by the upper portion of the circuit diagram of Fig. 8, which is identified by confining the added circuitry into a dash-line perimeter, to distinguish it from the lower portion of the cell circuit that represents the circuit of a substantially standard cell. In practice, in a "retrofit design situation", a dedicated circuit (upper portion of the circuit of Fig. 8) may be added in order to substantially realize a so-called Master latch of the register cell, in an appropriately modified form (in substitution of the pre-existing, standard, Master latch of the cell), provided with incrementing and decrementing devices of a stored logic value. With reference to the circuit shown in Fig. 8, the INC signal practically informs the depicted cell (SARCELL1 of the SAR), that the preceding cell (SARCELLø) has been updated pursuant to an incrementing operation. Viceversa, the signal DAC informs that the preceding cell has been updated pursuant to a decrementing operation. The signal CHANGE≈ operates a change of the logic content of the depicted cell, while the output signal CHANGES≈ is the signal that is activated when it is necessary to modify the content of the successive cell (SARCELL2). For example, if both the signals CHANGES and INC are activated, this means that an increment operation is being performed and that the content of the cell must be changed. If a logic "0" is stored in the cell, the value is changed to a logic "1" and the signal for changing the value stored in the next cell, that is the signal CHANGES≈, is not activated; viceversa, if a "1" is stored in the cell, the value is changed to "0" and the signal CHANGES≈ for changing value of the next cell is activated. Once the operation has been performed, the result is stored in the Master latch of the cell. The so stored value in the Master latch of the cell is conditionally transferred to the Slave latch of the same cell (in order to update the data stored in the SAR) only if the signal CTR_CORR≈ enables the writing of the result of the operation. This is necessary because the decrementing or incrementing steps are always performed at the end of every conversion cycle and only when necessary (on the basis of the result of the comparison), the result of the operation is effectively written in the SAR. The logic operator that permits to perform the incrementing and decrementing operations may be a classical EX_NOR circuit, as depicted in Fig. 8. Of course, in case of a completely new design, the single cells of the SAR may also be realized with a different circuit from the one shown in the figure and their circuit may be optimized in terms of the total number of transistors required. Also the cells SARCELLø, SARCELL8 and SARCELL9 have a circuit that is functionally similar to that of the other cells, except for the absence of certain input and/or output terminals. The SAREND block, that is normally present in a common SAR architecture, serves to close a comparison cycle. Also in the case of the modified SAR register of the invention, the function of the SAREND block is the same, that is that of determining the termination of a comparison and correction cycle. The signals MA_EOS and EOS_AR are input to the control block CORR, which supervises the execution of the correction steps at the end of each conversion process, for commanding the termination of the cycle. In a practical design, implementing the correction system of the invention for two adjacent missing codes, in an eight-bit ADC, the total number of "gates" used was 2002, as compared with a total number of gates of 1576 that was required by the ADC converter without correction system.

Claims: A correction process for a single missing code of a digital data produced by a conversion process of an input analog value in a digital value through successive approximations, performed in an analog-to-digital converter (ADC) comprising an internal digital-to-analog converter (DAC), a comparator and a register of successive approximations (SAR), said digital-to-analog converter (DAC) converting into an analog value, a digital value stored in the said register (SAR), which, compared with said input analog value, determines an updating either in an incrementing or in a decrementing direction of the digital value present in said register (SAR), the process being repeated for a number of times equal at least to the number of bits of said register (SAR), characterized by comprising the following steps: a) decrementing by an LSB the digital value produced by the conversion process and stored in said (SAR); b) converting the decremented digital value stored in said register (SAR) into an analog value; c) comparing said converted analog value with the input analog value; d) incrementing the digital value stored in said register (SAR) by an LSB if the analog value corresponding to the converted digital value is less than said input analog value; e) using the digital value stored in said register (SAR) as the correct digital result of the analog-digital conversion of said input analog value. A correction process for a double missing code of a digital data produced by a conversion process of an input analog value in a digital value through successive approximations, performed in an analog-to-digital converter (ADC) comprising an internal digital-to-analog converter (DAC), a comparator and a analog-to-digital converter (SAR) of successive approximation, said digital-to-analog converter (DAC) converting into an analog value, a digital value stored in the said register (SAR), which, compared with said input analog value, determines an updating in either an incrementing or in a decrementing direction of the digital value present in said register (SAR), the conversion process being repeated for a number of times equal at least to the number of bits of said register (SAR), characterized by comprising the following steps: a) decrementing by two LSBs the digital data produced by the conversion process and stored in the SAR; b) converting the digital value stored in said register (SAR) in an analog value; c) comparing said converted analog value with the input analog value; d) incrementing by an LSB the digital value stored in said register (SAR) if the analog value corresponding to the converted digital value is less than said input analog value; e) repeating the steps b), c) and d) ; f) incrementing the digital value stored in said register (SAR) by two LSBs; g) repeating the steps b) and c) ; h) decrementing the digital value stored in said register (SAR) by two LSBs if the analog value corresponding to the converted digital value is greater or equal to said input analog value or decrementing by one LSB the digital value stored in said register (SAR) if the analog value corresponding to the converted digital value is less than said input analog value; i) using the digital value stored in said register (SAR) as the correct digital result of the analog-to-digital converter conversion of said input analog value.

Inventors: MORONI ANGELO, MORONI,ANGELO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H03M1
IPC codes: H03M1