A method of manufacturing a semiconductor device

Abstract: A method of processing a polysilicon film formed on a single-crystal silicon substrate which can remove the polysilicon film with good selectivity in a fabrication process of semiconductor devices. First, a polysilicon film having an N-portion to be removed is formed on a single-crystal silicon substrate and then, the portion is selectively removed by the reactive ion etching using a Cl₂ gas or mixed gases including a Cl₂ gas. Preferably, N-impurity doping into the polysilicon film is performed by P or As ion-implantation with a dose of 1 x 10¹⁵ cm⁻² or more. A Cl₂ gas, mixed gases of Cl₂ and BCl₃, mixed gases of Cl₂ and HBr, mixed gases of Cl₂ and BBr₃, and mixed gases of Cl₂ and SiCl₄ are preferably used.

Description: The present invention relates to a method of manufacturing a semiconductor device such as a bipolar transistor or a MOS transistor. As used herein, the term "substrate" includes any form of layer, regardless of its thickness or of its position in the overall semiconductor structure. Recently, a selective etching technique of a polysilicon film on a single-crystal silicon substrate as become very important in Large Scale Integrated circuit (LSI) fabrication. The technique is used for forming an emitter opening in fabricating a bipolar transistor having a polysilicon base electrode connected to a graft base. This technique will be described concretely below referring to Fig. 1. Fig. 1 shows a step in the fabrication process of a bipolar transistor in which the above-described conventional technique is used. In Fig. 1, silicon dioxide film 2 for isolation is formed on a single-crystal silicon substrate 1 by selective oxidization. On the surface of the film 2 and the exposed surface of the substrate 1, a P + -polysilicon film 3 having a thickness of 200 to 300 nm is deposited, and on the film 3 a silicon dioxide film 4 having a thickness of 200 to 300 nm is deposited. In an active region defined by the oxide film 2 of the substrate 1, a graft base area 6 is formed near the surface of the substrate 1 and an emitter opening is formed in the oxide film 4 and the polysilicon film 3. The polysilicon film 3 is patterned to form a base electrode. An N-emitter region 8 and a P-active base region 7 are formed in a portion of the substrate which is facing the emitter opening. In the emitter opening, a side wall 10 of a silicon dioxide film is formed on the side surfaces of the polysilicon film 3 and the silicon dioxide film 4, and an emitter electrode 9 of an N + -polysilicon film is formed on the surfaces of the sidewall 10, the emitter region 8 and the silicon dioxide film 4. The bottom end of the emitter opening should be positioned at a level which is almost the same as that of the substrate 1 (or the graft base region 6) so that the graft base region 6 and the active base region 7 may be connected to each other, however, in Fig. 1, the bottom end of the emitter opening is positioned near the bottom end of the graft base region 6 due to over-etching. In addition, the bottom end of the spacer 10 is nearly extended to the bottom end of the graft base region 6. In the process of forming the emitter opening, first, an unmasked portion of the silicon dioxide film 4 is selectively removed by an anisotropic etching technique such as the Reactive-Ion-Etching (RIE) technique using a fluorine gas or the like, and thereafter a portion of the polysilicon film 3 thus exposed is selectively removed by an anisotropic etching technique such as the RIE technique using a chlorine gas or The like. In this process, it is impossible to selectively etch one of the P + -polysilicon film 3 and the single-crystal silicon substrate 1. Besides, it is extremely difficult to etch the polysilicon film 3 without etching The substrate 1 with regard to the present etching rate stability and etching uniformity. Accordingly, the polysilicon film 3 tens to remain partially on the substrate 1 due to insufficient etching, or the substrate 1 tends to be over-etched. If the polysilicon film 3 remains partially on the substrate 1, there arises the problem that the emitter region 8 and the graft base region 6 are short-circuited with each other through the remainder of the film 3. If the substrate 1 is over-etched, sufficient interconnection between the graft base region 6 and the active base region 7 cannot be obtained, as shown in Fig. 1, and, as a result, there arises the problem that base resistance will increase and punch through between the emitter region 8 and a collector region (not shown) will occur. The above-described process of selective etching of the polysilicon film is also used in a process of forming a node portion of a memory cell of static random access memory (SRAM) composed of MOS transistors. Fig. 2 shows a step in the fabrication process of an SRAM in which the above-described conventional etching technique is used. As shown in Fig. 2, silicon dioxide film 12 for isolation is formed on a single-crystal silicon substrate 11 by selective oxidation. In an active region defined by the oxide film 12 of the substrate 11, the surface area of the substrate 11 is covered with a silicon dioxide film 15 as a gate insulator. The film 15 is selectively removed at a node portion N of an SRAM memory cell. A gate electrode 16 of a N + -polysilicon film is formed on the film 15. A source region 13 and a drain region 14 are formed in the substrate 11 in self-alignment with respect to the gate electrode 16. The surface of the substrate 11 is partially exposed from the film 15 at the node portion N, and at the exposed area of the substrate 11, a concavity A is formed by etching. The reason for the concavity A being formed is as follows: During the selective etching process of the polysilicon film to form the gate electrode 15, etching action affects the exposed surface area of the substrate 11. Besides, the etching rate of the phosphorus diffusion region in the substrate 11, that is the source region 13 and the drain region 14 in Fig. 2, is larger than that of the other region. Therefore, the exposed surface area of the substrate 11 at the node portion N is easily etched. Since the concavity A induces crystal defects in the substrate 11, there arises the problem that minute node leakage may occur to degrade the data storage characteristics of the SRAM. US-A-4479850 discloses a method for etching a double layer semiconductor structure containing metal silicide layers or a metal silicide-polysilicon layer on a silicon substrate through a photoresist mask by means of reactive ion etching wherein dissociation and ionization of reactant gases take place in a plasma, the improvement comprising employing a mixture of chlorine gas and a highly reducing gas such as boron trichloride as the reactant gases. EP-A-401786 discloses a bipolar transistor in which the base width is determined not by the image resolution limit, but by impurity difusion from the polysilicon layer, permitting the base to be small. According to the present invention, there is provided a method as set out in claim 1. With the method of the present invention, the etching rate of N-polysilicon, can be made 1.5 to 2 times faster than that of P- or I- (no impurity-doped polysilicon or single-crystal silicon, so that only the N-portion of the polysilicon film may be removed by the etching without the substrate being affected adversely. As a result, the polysilicon film can be processed with good selectivity. The substrate may be N-, P- or I-single-crystal silicon. The impurity concentration of the N-type part of the polysilicon film may be set according to the necessary conditions for etching. Preferably, N-impurity doping into the polysilicon film is performed by phosphorus or arsenic (or possibly phosphorus and arsenic) ion-implantation with a dose of 1 X 10 15 cm -2 or more. In the step of selectively removing the N-type part reactive ion etching may be performed under the ordinary condition. As the etching gas, the following gas or mixed gases may be used: a chlorine (Cl 2 ) gas; mixed gases of Cl 2 and boron chloride (BCl 3 ); mixed gases of Cl 2 and hydrogen bromide (HBr); mixed gases of Cl 2 and boron bromide (BBr 3 ); and mixed gases of Cl 2 and silicon chloride (SiCl 4 ). In a preferred embodiment, the polysilicon film forms a P-base electrode of a bipolar transistor and the N-type part of the polysilicon film is a portion to be removed for forming an emitter opening. In another preferred embodiment, the polysilicon film forms a gate electrode of an MOS transistor and the N-type part of the polysilicon film is a portion where a node of an MOS-RAM is to be formed. Preferred features of the invention are described in the specification, by way of example, with reference to the accompanying drawings, in which: Fig.1 is a cross-sectional view of a bipolar transistor in which an emitter opening is formed by a conventional etching method. Fig.2 is a cross-sectional view of an MOS transistor of a CMOS-SRAM in which a gate oxide film is selectively removed at a node portion by a conventional etching method. Figs. 3A to 3D are cross-sectional views showing a method of processing a polysilicon film according to the present invention. A preferred embodiment of the present invention will be described with reference to Figs. 3A to 3D. Figs. 3A to 3D show a fabrication process of a bipolar transistor using a method of processing a polysilicon film according to the present invention. First, as shown in Fig. 3A, a surface of a single-crystal silicon substrate 21 is selectively oxidized to form silicon dioxide (SiO 2 ) films 22 for device isolation on the surface. Then, a polysilicon film 23 having a thickness of 100 to 200 nm is formed on the surface of the oxide films 22 and the exposed surface of the substrate 21 and,thereafter, the polysilicon film 23 is patterned so as to form a base electrode. After boron (B) or boron fluoride (BF 2 ) is ion-implanted into the entire polysilicon film 23 to make it P + -type, a silicon dioxide film 24 having a thickness of 200 to 300 nm is formed on the film 23 by the chemical vapor deposition (CVD) technique. Next, as shown in Fig. 3B, a photoresist film 25 with a hole H1 is formed on the oxide film 24 to form an emitter region, and the oxide film 24 is selectively removed to expose the surface of the P + -polysilicon film 23 by the anisotropic etching technique using the photoresist film 25 as a mask. Subsequently, Phosphorus (P) is selectively ion-implanted into a portion 23a facing the opening H1 of the polysilicon film 23 to make it N-type using the same film 25 as a mask. In this process, the appropriate energy and dose of the ion-implantation vary depending on the thickness of the P + -polysilicon film 23. For example, in the case of the thickness of the film 23 being 200 nm, the appropriate energy ranges from 40 to 50 keV and the appropriate dose ranges from 1 x 10 15 to 5 x 10 15 cm -2 . If ion-implantation is performed under the above conditions, implanted ions are distributed in the portion 23a and its neighboring area, and the depth of the ion-distributed range is slightly smaller than the thickness of the film 23. Besides, the ion concentration in the portion 23a becomes 5 x 10 19 cm -3 or more. Arsenic (As) may be ion-implanted in place of Phosphorus. Which ion is to be used is determined according to the thickness of the polysilicon film 23. The N + -portion 23a thus ion-implanted is then removed selectively by the reactive ion etching technique, using a Cl 2 gas or mixed gases including a Cl 2 gas, thereby to form a hole H2 extending to the surface of the substrate 21. The hole H2 is an emitter opening. The bottom end of the hole H2 is positioned at almost the same level of the surface of the substrate 21, and does not enter into the substrate 21 as shown in Fig. 1. Since the ion concentration in the N + -portion 23a of the polysilicon film 23 is 5 x 10 19 cm -3 or more, the etching rate of the portion 23a can be made 1.5 to 2 times faster than that of the single-crystal silicon substrate 21, so that only the portion 23a can be removed by the etching process without the substrate 21 being affected adversely. As a result, the polysilicon film 23 can be removed with good selectivity even if the etching rate dispersion is large and/or etching uniformity is bad. For example, in case of the etching uniformity in a surface being ±10 %, substantial etching dispersion can be made within ±3 %. Next, P-impurities are selectively doped into the substrate 21 to form a P + -graft base region 26 by diffusion from the inside of the P + -polysilicon film 23 or ion-implantation through the film 23, as shown in Fig. 3D. P-impurities are doped through the hole H2 into the substrate 21 to form a P-active base region 27 and, thereafter, a sidewall 30 of silicon dioxide is formed on the side surfaces of the polysilicon film 23 and the silicon dioxide film 24. Then, N-impurities are doped selectively through the hole H2 into the P-active base- region 27 to form an N-emitter region 28, as shown in Fig. 3D, and an emitter electrode 29 connected to the N-emitter region 28 is formed in the sidewall 30. The top end of the emitter electrode 29 is placed on the surface of the silicon dioxide film 24. With the bipolar transistor thus fabricated, due to good etching selectivity, the polysilicon film 23 does not remain on the substrate 21 and also the bottom end of the emitter opening H2 is positioned at almost The same level of the surface of the substrate 21, so that the graft base region 26 and the active base region 27 are well connected to each other. As a result, the problems generated in the conventional method such as base resistance increase and punch through between the emitter and collector regions do not arise. Fabricating bipolar transistors using the method of the embodiment as a test, it was found that almost 100 % yield was obtained Ln the emitter opening forming process. In the above embodiments, the method of the present invention is applied to a bipolar transistor; however, the present invention can be applied to other semiconductor devices. It will be understood that the invention has been described above purely by way of example, and modifications of detail can be made within the scope of the invention.

Claims: A method of manufacturing a semiconductor device, said method comprising the steps of:- forming a polysilicon film (23) on a surface of a single-crystal silicon substrate (21); doping said polysilicon film with a P-type impurity; forming a mask layer (25) on the P-type polysilicon film, said mask layer having a hole (H1) to expose a part (23a) of said P-type polysilicon film; introducing an N-type impurity into said part (23a) of said P-type polysilicon film through said hole (H1), thereby converting said part (23a) into an N-type part; selectively removing said N-type part of said polysilicon film with an etchant containing chlorine gas and using said mask layer to make a hole (H2) in said polysilicon film; selectively introducing a P-type impurity into said substrate to form a P-graft base region (26) of a bipolar transistor at an area surrounding said hole in said polysilicon film; selectively introducing a P-type impurity into said substrate to form a P-active base region (27) of said bipolar transistor through said hole in said polysilicon film, said P-active base region being connected to said P-graft base region; making a sidewall spacer (30) on a side face of said polysilicon film (23) in said hole in said polysilicon film; and selectively introducing an N-type impurity into said P-active base region to form an N-emitter region (28) of said bipolar transistor using said sidewall spacer; wherein an etching rate of said N-type part of said P-type polysilicon film is higher than that of said P-type polysilicon film itself during said step of removing said N-type part of said P-type polysilicon film and therefore said N-type part of said P-type polysilicon film is selectively etched without overetching of said substrate. A method according to Claim 1, wherein said N-type impurity is doped to a depth slightly less than the depth of said surface of said substrate. A method according to Claim 1 or Claim 2, wherein ion implantation is employed in said step of introducing said N-type impurity into said part (23a) of said P-type polysilicon film. A method according to Claim 3, wherein ion implantation of one of phosphorus and arsenic ions is employed, with a dose of at least 1 x 10 15 cm -2 . A method according to Claim 4, wherein the implantation energy is set in the range 40 to 50 keV. A method according to any of the preceding claims wherein said step of selectively removing said N-type part of said polysilicon film is performed by a reactive ion etching using a gas selected from the group consisting of a Cl 2 gas, mixed gases of Cl 2 and BCl 3 , mixed gases of Cl 2 and HBr, mixed gases of Cl 2 and BBr 3 , and mixed gases of Cl 2 and SiCl 4 . A method according to any of the preceding claims wherein the etch rate of said N-type part of said P-type polysilicon film is 1.5 to 2 times faster than that of said substrate. A method according to any one of the preceding claims, wherein said N-type part of said P-type polysilicon film is removed for forming an emitter opening (H2)

Inventors: SHIMIZU JUNZOH, SHIMIZU, JUNZOH, Shimizu, Junzoh, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L29