LOW POWER ELECTRONIC CIRCUIT COMPRISING A RESONANT SYSTEM AND A FUNCTION CIRCUITRY

Abstract: An electronic circuit uses a resonance technique to reduce power consumption. The circuit contains function circuitry (14) that performs electronic functions. Certain elements (14F) of the function circuitry change state at a circuit frequency in response to one or more input signals, typically clock signals (CKR and C &cir& NOt K &cir& NOt R &cir& NOt ), that change state at the circuit frequency. A resonant system (50 or 140), which oscillates at the circuit frequency, is operated close to a resonant frequency so that the resonant system is largely in resonance. The resonant system is coupled to the function circuitry in order to help the indicated elements in changing state by overcoming parasitic capacitances and/or inductances associated with the function circuitry.

Description: Low Power Electronic Circuit Comprising a Resonant System and a Function Circuitry FIELD OF THE INVENTION This invention relates to electronic circuits. More specifically, this invention relates to the reduction of power consumption in electronic circuits. BACKGROUND ART An electronic circuit consumes power in various ways. In particular, power is consumed when input signals to elements of the circuit change state. This power consumption occurs as a result of the charging and discharging of parasitic capacitances associated with the inputs to the circuit elements. Power is not dissipated in the parasitic capacitances themselves but, instead, in the output resistances of earlier circuit elements that furnish the input signals. In modern synchronous integrated circuits ("ICs") , a large portion of the power consumption occurs in cloc drivers that provide clock signals to the functional circuit elements. Referring to the drawings, Fig. 1 illustrates a conventional synchronous CMOS IC useful in understanding clock-driver power consumption. The circuit in Fig. 1 contains a clock driver 10 that furnishes a circuit clock signal CKD on a circuit clock line 12 in response to an input clock signal CKI. Clock driver 10 consists of a group of CMOS inverters 10D connected in parallel. Each inverter 10D is formed with a pair of complementary insulated-gate field-effect transistors ("FETs") QN and QP connected in series between circuit ground and a source of a high supply voltage V HH . Clock signal CKD is provided by way of a clock net to the clock inputs of function elements 14F in function circuitry 14. The clock net consists of the lines that branch out from clock line 12 and go to function elements 14F. A parasitic capacitance is associated with the clock input section of each element 14F. The lines that form the clock net also have their own parasitic capacitances. Function elements 14F are built in proximity to, or contain components connected to, at least one low- impedance source of fixed reference voltage, typically earth or circuit ground potential. The lines that form the clock net are similarly situated in proximity to at least one low-impedance source of fixed reference voltage. To a good approximation, the parasitic capacitances of the clock net lines and the clock inputs to elements 14F can be represented by a single capacitor CPl connected between clock line 12 and the ground-potential source. Typically, (a) the clock input resistance of each function element 14F is very high, (b) the propagation delay from driver 10 to the most remote of elements 14F is small compared to clock-frequency period, and (c) the clock-net lines have low resistance and inductance. To a reasonable approximation, the load that clock CKD presents to driver 10 can likewise be represented by capacitor CPl since it is also connected between the output of driver 10 and the ground-potential source. Input clock signal CKI switches between a low voltage level, typically ground reference, and a high voltage level, typically V HH , at an input clock frequency f CKI . During a full clock cycle in which input clock CKI goes from one level to the other level and then back to the first, driver 10 expends an energy equal to C pl V HH 2 , where C pl is the value of parasitic capacitance CPl. Half of this energy is dissipated as heat by the QP channel resistances when current flows from the V HH supply through FETs QP to charge capacitance CPl during one half of the clock cycle. The remaining half of energy C pl V HH 2 is dissipated as heat by the QN channel resistances when current flows through FETs QN to discharge capacitance CPl during the other half of the clock cycle. The number of functional elements 14F in some modern synchronous ICs is very high. As a consequence, parasitic capacitance CPl is very high. Driver 10 must be quite large in order to charge and discharge capacitance CPl at the high switching speed typically required. The net result is that driver 10 dissipates a large portion of the power utilized by the IC. For example, the clock driver in the Alpha RISC processor made by Digital Equipment Corporation reportedly consumes about half of the processor power. This is highly disadvantageous. The IC of Fig. 1 employs only a single circuit clock signal. However, high clock-driver power dissipation also occurs in synchronous prior art ICs that utilize complementary clock signals. Fig. 2 illustrates part of such a complementary-clock circuit. The circuit of Fig. 2 contains a clock driver 16 formed with inverters 18 and 20 that provide complementary circuit clock signals CKD and CKD on circuit clock lines 22 and 24 in response to input clock CKI. Clocks CKD and CKD are furnished to a D-type CMOS master-slave flip-flop 26 consisting of a data input buffer, a master portion, a slave portion, and an output buffer. The input buffer, in turn, consists of a CMOS inverter 28 that inverts data signal D and supplies the inverted D signal to the master portion formed with transmission gates 30 and 32 and CMOS inverters 34 and 36. The slave portion consists of transmission gates 38 and 40 and CMOS inverters 42 and 44 that drive the output buffer formed with CMOS inverters 46 and 48. Each transmission gate 30, 32, 38, or 40 consists of a pair of complementary insulated-gate FETs connected in parallel. Transmission gates 30, 32, 38, and 40 constitute the clock inputs for flip-flop 26. The parasitic capacitances associated with FETs QA1, QB1, QC1, and QD1 of the transmission-gate clock inputs are represented by equivalent parasitic capacitance CPl associated with line 22. Similarly, the parasitic capacitances associated with FETs QA2, QB2, QC2, and QD2 of the transmission-gate clock inputs are represented by equivalent parasitic capacitance CP2 associated with line 24. The circuit in Fig. 2 operates as follows. Assume that input clock CKI is initially low so that circuit clock CKD is low and circuit clock CKD is high. Gate 30 is conductive, allowing data D to be loaded into the master portion of flip-flop 26. Gate 32 is non- conductive. When input clock CKI goes high so that circuit clocks CKD and CKD change state, gate 30 turns off. Gate 32 turns on to latch data D into the master portion. At the same time, gate 38 turns on to allow data D to enter the slave portion. Gate 40 turns off. When input clock CKI returns to its low level, circuit clocks CKD and CKD switch back. Gate 38 turns off. Gate 40 turns on to latch data D into the slave portion. Complementary output signals Q and Q are then respectively provided at the true and inverted values of data D. Letting V HH represent the high supply voltage, it turns out that driver 16 dissipates an energy equal to (C pl + C P2 )V HH 2 in one clock cycle, where C pl and C p2 are the respective values of parasitic capacitances CPl and CP2. Consequently, the circuit of Fig. 2 has high clock- driver power dissipation. High power consumption in the clock-drivers of large state-of-the-art synchronous ICs is a major impediment to future synchronous IC design. It would be extremely desirable to have a mechanism for operating an IC in a synchronous manner without incurring this power penalty. GENERAL DISCLOSURE OF THE INVENTION The present invention furnishes a resonance technique for driving clock inputs of circuit elements in an electronic circuit that is at least partially synchronous. The parasitic capacitances associated with the clock inputs of the circuit elements and with the lines of the attendant clock net become part of a resonance mechanism. When the parasitic capacitances are discharged, a large part of the energy in the capacitances is transferred to another part of the resonance mechanism for temporary storage rather than being dissipated as heat. The stored energy is subsequently reused. Consequently, the power consumption of an electronic circuit designed according to the invention is much less than that in an otherwise comparable prior art circuit that utilizes a conventional clock driver. More particularly, an electronic circuit in accordance with the invention contains a resonant system and function circuitry. In response to an input clock signal at an input clock frequency, the resonant system oscillates at a circuit clock frequency substantially proportional to the input clock frequency to generate a circuit clock signal at the circuit clock frequency. The resonant system is operated close to a fundamental resonance frequency so that the resonant system is largely in resonance. The function circuitry performs electronic functions in synchronism with the circuit clock signal. In a single-clock implementation, the resonant system typically contains a resonator and a resonance capacitor coupled in series between (a) a circuit clock line on which the circuit clock signal is transmitted and (b) a source of a substantially fixed reference voltage or other voltage at a much lower frequency that the circuit clock frequency. When the parasitic capacitances associated with the clock net and with the clock inputs of elements in the function circuitry are discharged during a half clock cycle, much of the energy in these parasitic capacitances is temporarily transferred to the resonance capacitor. During the next half clock cycle, the energy stored in the resonance capacitor is used to recharge the parasitic capacitances associated with the clock net and clock inputs of the function circuitry. Alternatively, the resonant system in a single-clock implementation can be formed with a resonator coupled between the circuit clock line and a source of a reference voltage approximately equal to the time-averaged voltage of the circuit clock signal. In this case, the energy in the parasitic capacitances is largely returned to the reference-voltage source. The invention is readily extended to a complementary- clock implementation in which the resonant system generates a second circuit clock signal substantially inverse to the first circuit clock signal. At least part of the electronic functions of the function circuitry are also performed in synchronism with the second circuit clock signal. In the complementary-clock implementation, the resonant system typically contains a resonator coupled between a pair of circuit clock lines on which the circuit clock signals are respectively transmitted. When the parasitic capacitances associated with the clock inputs driven from one of the circuit clock signals are discharged during a half clock cycle, much of the energy in these parasitic capacitances is transferred through the resonator to charge the parasitic capacitances associated with the clock inputs driven from the other circuit clock signal. The opposite occurs during the next half clock cycle. The resonator in both implementations typically contains a main inductive device formed with an inductor or a group of inductors coupled to one another in series. When the resonator is implemented solely with such an inductive device, the fundamental resonance frequency is approximately equal to l/2π /L E C τ where L E is the inductance of the main inductive device, and C τ is the series equivalent capacitance of all capacitors (both parasitic and real) in parallel with the main inductive device. The waveform of each circuit clock then approximates a sinusoid—i.e., a sine or cosine wave. The resonator is commonly provided with additional elements so that each circuit clock waveform contains components attributable to one or more resonance frequencies beside the fundamental frequency. For example, the resonator may also contain (a) one or more inductive-capacitive arrangements coupled in parallel with part or all of the main inductive device or/and (b) one or more capacitors coupled to internal points of the main inductive device. As a result, the waveform for each circuit clock can approach various non-sinusoid shapes such as the square-wave shape desirable for the clock inputs of edge-triggered flip-flops and other level- sensitive elements. The resonant system preferably includes control circuitry for adjusting the resonance frequency. This typically involves changing inductance and/or capacitance values. Also, the resonant system normally includes a driver that provides a small amount of energy to compensate for energy dissipated as heat due to non- idealities in certain parts of the circuit. By reusing the energy stored in the parasitic capacitances associated with the clock net and clock inputs of the function circuitry, the power needed for these items is small compared to the power dissipated as heat in the transistors of a conventional clock driver. In particular, the invention reduces clock power consumption at least 50% and often much more. When the present circuit is implemented in IC form, the invention commonly reduces chip area because the resonant system occupies less space than a conventional large clock driver. While the principles of the invention are particularly applicable to circuit clocking, these principles apply to other situations in which there are repetitive signals. More generally, the invention covers an electronic circuit containing function circuitry which performs electronic functions where specified elements of the function circuitry change state at a circuit frequency in response to one or more input signals. The circuit includes a resonant system which oscillates at the circuit frequency. The resonant system is operated close to a fundamental resonance frequency so that the resonant system is largely in resonance. The resonant system is coupled to the function circuitry to assist the specified elements in changing state by overcoming parasitic capacitances and/or parasitic inductances associated with the function circuitry. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 and 2 are circuit diagrams of synchronous prior art electronic circuits that employ clock drivers. Fig. 3 is a general block diagram of a synchronous electronic circuit that utilizes a resonant system in accordance with the invention. Fig. 4 is a circuit diagram of a complementary-clock implementation of the synchronous circuit in Fig. 3. Fig. 5 is a circuit diagram of a resonator employable in the implementations of Figs. 4, 22 - 24, 26, 32, 34 - 37, and 39. Fig. 6 is a simplified graph of waveforms that arise when the resonator of Fig. 5 is utilized in the complementary-clock implementation of Fig. 4. Figs. 7 and 8 are partial circuit diagrams of embodiments in which the resonator of Fig. 5 is utilized in the complementary-clock implementation of Fig. 4. Figs. 9 and 10 are circuit diagrams of resonators employable in the implementations of Figs. 4, 22 - 24, 26, 32, 34 - 37, and 39. Fig. 11 is a circuit diagram of an embodiment in which the resonator of Fig. 10 is utilized in the complementary-clock implementation of Fig. 4. Fig. 12 is a simplified graph of waveforms that arise when the resonator of Fig. 10 is utilized in the complementary-clock implementation of Fig. 4. Fig. 13 is a circuit diagram of a resonator employable in the implementations of Figs. 4, 22 - 24, 26, 32, 34 - 37, and 39. Fig. 14 is a partial circuit diagram of an embodiment in which the resonator of Fig. 13 is employed in the complementary-clock implementation of Fig. 4. Fig. 15 is a simplified graph of waveforms that arise in the embodiments of Figs. 14 and 29. Figs. 16, 17, 18, 19, and 20 are circuit diagrams of resonators employable in the implementations of Figs. 4, 22 - 24, 26, 32, 34 - 37, and 39. Fig. 21 is a simplified graph of AC impedance as a function of frequency for the resonators of Figs. 5, 9, 10, 13, and 16 - 20. Figs. 22 and 23 are circuit diagrams of resonating sections alternatively employable in the complementary- clock implementations of Figs. 4, 37, and 39. Fig. 24 is a circuit diagram of a control circuit generally employable in the complementary-clock implementation of Fig. 4, specifically in the embodiments of Figs. 7, 8, and 14. Fig. 25 is a circuit diagram of an embodiment of the phase comparator in Fig. 24. Fig. 26 is a circuit diagram of a single-clock implementation of the synchronous circuit in Fig. 3. Fig. 27 is a circuit diagram of an embodiment in which the resonator of Fig. 10 is utilized in the single- clock implementation of Fig. 26. Fig. 28 is a simplified graph of waveforms that arise when the resonator of Fig. 10 is utilized in the single- clock implementation of Fig. 26. Fig. 29 is a partial circuit diagram of an embodiment in which the resonator of Fig. 13 is utilized in the single-clock implementation of Fig. 26. Fig. 30 is a partial circuit diagram of a single- clock implementation of the circuit in Fig. 3. Fig. 31 is a simplified graph of waveforms that arise in the implementation of Fig. 30. Fig. 32 is a circuit diagram of a single-clock implementation of the circuit in Fig. 3. Fig. 33 is a simplified graph of waveforms that arise in the implementation of Fig. 32. Fig. 34 is a partial circuit diagram of an embodiment of the single-clock implementation in Fig. 32. Figs. 35 and 36 are circuit diagrams of single-clock implementations of the circuit in Fig. 3. Fig. 37 is a partial circuit diagram of a variation of the complementary-clock implementation in Fig. 4. Fig. 38 is a general block diagram of another synchronous electronic circuit that utilizes a resonant system in accordance with the invention. Fig. 39 is a circuit diagram of an embodiment of the variable-frequency oscillator in Fig. 38. Fig. 40 is a partial circuit diagram of an implementation of the synchronous circuit in Fig. 3 or 38. Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. All transistors shown in the drawings are enhancement-mode insulated-gate FETs. Bubbles are placed on the gates of P-channel FETs to distinguish them from N-channel FETs. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Fig. 3, it illustrates a general configuration for a synchronous electronic circuit that contains a resonant system 50 for supplying one or more clock signals to function circuitry 14 at low power consumption in accordance with the teachings of the invention. Resonant system 50 oscillates at a circuit clock frequency f CKR in response to input (or reference) clock signal CKI which switches between its low and high values at input clock frequency f CKI . Circuit clock frequency f CKR substantially equals f CKI . Resonant system 50 provides a circuit clock signal CKR at circuit clock frequency f CKR to function circuitry 14 along a circuit clock line 52. Circuit clock CKR is largely in phase with, or largely of opposite phase to, input clock CKI. In complementary-clock implementations, system 50 supplies a further circuit clock signal CKR at frequency f C R to circuitry 14 along a circuit clock line 54. Circuit clock signal CKR is of substantially opposite phase to circuit clock signal CKR. Parasitic capacitance CPl associated with clock line 52 represents the equivalent sum of (a) the parasitic capacitances associated with the clock inputs of the function elements that receive circuit clock CKR in function circuitry 14 and (b) the parasitic capacitances of the clock-net lines that transmit clock CKR in circuitry 14. To a reasonable approximation, capacitance CPl thereby represents the capacitive load presented by clock CKR to resonant system 50. When resonant system 50 also generates circuit clock CKR, parasitic capacitance CP2 associated with clock line 54 represents the equivalent sum of (a) the parasitic capacitances associated with the clock inputs of the function elements that receive circuit clock CKR in circuitry 14 and (b) the parasitic capacitances of clock- net lines that transmit clock CKR in circuitry 14 Capacitance CPl then reasonably represents the capacitive load presented by clock CKR to system 50. The values C pl and C p2 of capacitances CPl and CP2 are usually very close to each other. Resonant system 50 consists of a small driver 56, a resonating section 58, and a control circuit 60. Driver 56 amplifies input clock CKI to drive a driver clock signal CKD at input clock frequency f CKI . Driver 56 may also drive a driver clock signal CKD substantially inverse in phase to driver clock CKD. Resonating section 58 produces circuit clock CKR and, when present, circuit clock CKR. For purposes of pictorial illustration. Fig. 3 indicates that section 58 operates in response to driver clock CKD and, when present, driver clock CKD. Control circuit 60 controls the operation of resonant system 50 in response to input clock CKI and one or more feedback signals FB supplied from resonating section 58. For this purpose, control 60 may supply one or more resonator control signals RC to section 58. Depending on how components 58 and 60 are implemented, two or more of signals CKD, CKR, FB, and RC may be the same signal. Likewise, two or more of signals CKD, CKR, FB, and RC may be the same signal. Control 60 may furnish one or more additional control signals (not shown) to driver 56. Resonant system 50 operates generally in the following manner. Circuit clock CKR switches between substantially fixed low and high voltage levels at circuit frequency f CKR . Assume that clock CKR is at its high level so that parasitic capacitance CPl is fully charged. When input clock CKI changes in such a way as to cause circuit clock CKR to be driven low, parasitic capacitance CPl largely discharges along line 52 into resonating section 58. Instead of letting all the capacitive discharge energy be dissipated as heat, section 58 transfers part, usually considerably more than half, of the capacitive discharge energy to a temporary storage site. When clock CKR returns to its high level, section 58 recovers the capacitive energy stored at the temporary site and supplies that energy along line 52 to recharge capacitance CPl. In a single-clock implementation of system 50, the temporary storage site is typically a capacitor. In a complementary-clock implementation, the temporary storage site is normally parasitic capacitance CP2. The charging and discharging of capacitance CP2 then occurs in a manner complementary to that of parasitic capacitance CPl. In being driven by driver 56 at input clock frequency f CKI resonating section 58 oscillates in sympathy with input clock CKI so that circuit clock frequency f CKR substantially equals f CKI at steady-state. Section 58 and, consequently, resonant system 50 have a fundamental resonance frequency f R at which the system oscillations as represented by circuit clock CKR and, when present, circuit clock CKR locally reach maximum voltage amplitude as a function of input clock frequency f KI . System 50 is then in resonance. Control circuit 60 adjusts the value of fundamental resonance frequency f R in order to make it very close to f CKI . Resonant system 50 then goes substantially into resonance. The result is that (a) the voltage amplitudes of circuit clock CKR and, when present, circuit clock CKR reach local maxima, (b) the phase angle between circuit clock CKR and input clock CKI is approximately 0° or 180, and (c) the power consumed by driver 56 is minimized. To ease the demands on control circuit 60, the values of the elements used to implement components 56 - 60 are chosen so that the nominal uncontrolled value f RN of resonance frequency f R is relatively close to input clock frequency f CKI . Typically, f RN is slightly more than f CKI . Although manufacturing variations may cause the actual uncontrolled value of frequency f R to differ significantly from f RN , components 56 and 58 are implemented in a manner that still enables f R to be made close to f CKR and f CKI . Accordingly, system 50 operates largely in resonance. A small amount of energy is needed to initiate and sustain the resonant oscillations of resonating section 58. Driver 56 provides this energy. In addition, driver 56 provides energy to compensate for non-idealities such as the small clock-line resistance and the limited quality factors of the components in resonating section 58. More particularly, resonance frequency f R depends (among other things) on the values of parasitic capacitance CPl and, when present, parasitic capacitance CP2. Consider the case where circuit clock CKR is intended to be in phase with input clock CKI. If f R differs from f CKI , a phase difference exists between clocks CKR and CKI (even though f CKR and f CKI are substantially the same) . The sign and magnitude of this phase difference is onotonically related to the sign and magnitude of the frequency difference between f R and f CKI . Control circuit 60 normally senses the phase difference between clocks CKR and CKI. Control 60 may also sense how close the phase difference between clocks CKR and CKI is to 180°. Depending on the magnitude(s) and sign(s) of the phase difference(s) , control 60 typically adjusts resonance frequency f R by appropriately adding/subtracting inductance and/or capacitance to bring f R close to f CKR and thus close to f CKI . Fig. 4 depicts a complementary-clock implementation of the synchronous circuit in Fig. 3. Resonating section 58 of Fig. 3 " is implemented in Fig. 4 with a passive resonator 62 connected between clock lines 52 and 54. The lines carrying signals FB and RC, which can be the same signal, may connect to internal points of resonator 62 or to line 52 and/or line 54. Function circuitry 14 in Fig. 4 consists of a group of function elements 14G having clock inputs connected through a clock net to lines 52 and 54. Each element 14G is illustrated as being responsive to both of circuit clocks CKR and CKR. However, some of elements 14G could be responsive to only one of clocks CKR and CKR. When parasitic capacitance CPl discharges as clock CKR goes from high to low during a half clock cycle, the CPl charge largely flows along line 52, through resonator 62, and then along line 54 to charge parasitic capacitance CP2 as clock CKR simultaneously goes from low to high. The reverse occurs during the next half clock cycle in which clock CKR goes from low to high while clock CKR simultaneously goes from high to low. In this way, the capacitive charge alternately switches between capacitances CPl and CP2 to keep power consumption low. Resonator 62 in the complementary-clock implementation of Fig. 4 can be embodied simply with a main inductor LI as shown in Fig. 5. In this case, resonance frequency f R approximately equals l/2π^L 1 C τ where 1>_. is the value of inductor LI, and C τ is the series equivalent capacitance of all parasitic and real capacitances in parallel with inductor LI. When resonator 62 consists solely of an inductor, the waveforms for clocks CKR and CKR are generally sinusoidal in shape. Fig. 6 illustrates a simplified example of the CKR and CKR waveforms when resonator 62 is an inductor, and the waveform for input clock CKI is substantially a square wave. Fig. 7 depicts a partial embodiment of Fig. 4 for the case where resonator 62 is formed with inductor LI, and one of function elements 14G in circuitry 14 consists of flip-flop 26 described above in connection with Fig. 2. Instead of receiving driver clock signals CKD and CKD as in Fig. 2, the clock inputs of transmission gates 30, 32, 38, and 40 are connected to clock lines 52 and 54 to receive clocks CKR and CKR in Fig. 7. Aside from this difference, flip-flop 26 operates in the manner described above in connection with Fig. 2. Fig. 8 illustrates how the partial circuit of Fig. 7 is extended to include a group of flip-flops such as flip-flop 26. Inductor LI in resonator 62 can be a variable (or adjustable) inductor whose inductance is controlled to adjust resonance frequency f R . Fig. 9 illustrates a partial embodiment of Fig. 4 where inductor LI is a variable inductor controlled by one signal RC from control circuit 60. Manufacturing variations normally cause corresponding variations in the voltage switching thresholds of (otherwise identical) edge-triggered flip-flops and other level-sensitive switching devices. Since the time-domain waveforms for signals that cause the clock inputs of switching devices to change state invariably differ from the ideal square-wave shape, the difference in switching thresholds affects the synchronism of a circuit containing the switching devices. A square waveform for a signal that changes state at a given frequency consists of a weighted summation of the sinusoidal waveforms of the odd- numbered harmonics (or multiples) of the given frequency—i.e., the first harmonic (which is the given frequency) , the third harmonic, the fifth harmonic, and so on. The synchronism of the circuit in Fig. 4 is improved by adding a parallel combination of one or more inductive- capacitive ("LC") pairs to resonator 62. Each LC pair consists of an inductor and a capacitor connected in series with each other (and in parallel with inductor LI) . Each LC pair enables an additional sinusoidal component to be included in the waveforms of clocks CKR and CKR. The LC values of each LC pair are preferably chosen in such a way that the odd-numbered harmonics above the first harmonic of fundamental resonance frequency f R are incorporated into the CKR and CKR waveforms when f R equals f cκι- τhe CKR and CKR waveforms thereby start to approximate square time-domain shapes. The third harmonic is the most important harmonic (beyond the first) for creating a square waveform. Moving to Fig. 10, it illustrates an example in which an LC pair consisting of an inductor L2 and a capacitor C2 is incorporated into resonator 62 in parallel with inductor LI. The values of components L2 and C2 are chosen to produce the third harmonic of f R when it equals f CKI . Fig. 11 depicts an embodiment of Fig. 4 where resonator 62 is implemented as in Fig. 10, and control circuit 60 utilizes a phase comparison technique for adjusting resonance frequency f R . Control 60 in Fig. 11 consists of a phase comparator 64 and a pair of variable capacitors CA1 and CA2. Phase comparator 64 compares the phases of circuit clocks CKR and CKR with the phase of input clock CKI. Depending on the phase differences, comparator 64 generates one or more signals PC that adjust the values of variable capacitors CA1 and CA2. Inasmuch as capacitors CA1 and CA2 are respectively in parallel with parasitic capacitances CPl and CP2 and thus respectively increase the capacitances of clock lines 52 and 54, the nominal values of capacitances CPl and CP2 are normally less than the values which would cause nominal value f RN to equal f CKI . Fig. 12 illustrates a simplified example for the CKR and CKR waveforms of Fig. 11 when the input CKI waveform is a square wave. The CKR and CKR waveforms in Fig. 12 include the third f R harmonic when f R equals f C I . As Fig. 12 shows, the CKR and CKR waveforms are now reasonable approximations of square waves. Fig. 13 illustrates an extension of resonator 62 in Fig. 10 in which a further LC combination consisting of an inductor L3 and a capacitor C3 is connected in parallel with inductor LI. The values of elements L3 and C3 are chosen so as to add the fifth f R harmonic to the CKR and CKR waveforms when f R equals f CKI . Fig. 14 depicts a partial embodiment of Fig. 4 where resonator 62 is implemented as in Fig. 13, and driver 56 consists of a pre-driver 66, a pair of serially connected complementary insulated-gate switching FETs QN1 and QP1, and a pair of serially interconnected complementary insulated-gate switching FETs QN2 and QP2. In response to input clock CKI and one or more additional input signals NPI, pre-driver 66 generates (a) a first pair of switching signals Nl and PI that vary between ground reference and V HH at input frequency f CKI and (b) a second pair of switching signals N2 and P2 that likewise vary between ground reference and V HH at frequency f CKI . FETs QN1 and QP1 furnish circuit clock CKR on line 52 in respective response to switching signals Nl and PI. FETs QN2 and QP2 similarly provide circuit clock CKR on line 54 in respective response to switching signals N2 and P2. Fig. 15 illustrates simplified waveforms for switching signals Nl and PI. The waveforms for switching signals N2 and P2 (not shown) are respectively inverse in phase to the PI and Nl waveforms. Each of signals Nl, N2, PI, and P2 ideally has a square-wave shape. In each pair of signals Ni and Pi, where i equals 1 or 2 , each signal Ni or Pi is at its active level only when the other signal Pi or Ni is at its inactive level. Hence, only one of signals Ni and Pi in each pair is active at a time. The pulse widths of signals Nl, PI, N2, and P2 are determined by additional input signal (s) NPI. By arranging for switching signals Nl, PI, N2, and P2 to have the preceding characteristics, only one of FETs QNi and QPi in each FET pair is conductive at any time. At no time is a path from the V HH supply to ground created through (either) FET pair QNi and QPi. Also, because the (positive-going) Ni and (negative-going) Pi pulses are shorter than the CKI pulses, much of the energy dissipation that would otherwise occur in the QNi and QPi channel resistances due to the injection of current from the V HH supply when circuit clocks CKR and CKR are at values between V HH and ground reference is avoided. The power consumption is very low. The harmonic content of the CKR and CKR waveforms can be controlled by adjusting the Ni and Pi waveforms. This 5 also furnishes a mechanism for obtaining an optimum design trade-off between power consumption and slew rate when CKR and CKR change state. Increasing the Ni and Pi pulse widths increases the slew rate but consumes more power. In addition to showing the Nl and PI waveforms, Fig. 10 15 illustrates simplified waveforms for clocks CKI and CKR. Clock CKI is again depicted as a square wave. Because resonator 62 in Fig. 14 furnishes the third and fifth harmonics of frequency f R when it equals f CKI , the CKR waveform is even closer to a square wave than in Fig. 15 12. Referring to Fig. 16, a capacitor CA can be placed across part of inductor LI in resonator 62. Inductor LI then consists of portions L1A and LIB with capacitor CA connected in parallel with portion LIB. Elements L1A and 20 LIB can be separate inductors. Resonator 62 in Fig. 16 operates in a similar manner to that of Fig. 10 to introduce the third f R harmonic frequency into the CKR and CKR waveforms. In particular, the impedance of a capacitor decreases 5 with increasing frequency. By appropriately choosing the value of capacitor CA, it appears largely as an open circuit at the first f R harmonic and as a short circuit at the third f R harmonic. The effective inductance L E of resonator 52 in Fig. 16 thus changes with frequency since 0 part of the turns of inductor LI are shorted out at high frequency. Resonance occurs at a frequency approximately equal to l/2π < JL E C τ . Consequently, a second resonance point arises at the third f R harmonic when f R equal f CKI . The principle of resonator 62 in Fig. 16 is readily 5 extended to introduce odd-numbered f R harmonics above the third by utilizing two or more capacitors connected in parallel with various parts of inductor LI. Fig. 17 depicts an example in which inductor LI is divided into three portions L1A, LIB, and LIC. Capacitor CA is again connected across portion L1A to add the third f R harmonic frequency by appropriately choosing the CA value so as to short out portion L1A at the third harmonic. In addition, a further capacitor CB is connected across portions L1A and LIB. By appropriate choice of the value of capacitor CB, it shorts out portions L1A and LIB at the fifth f R harmonic frequency to reduce L E and introduce the fifth harmonic into circuit clocks CKR and CKR. Alternatively, elements L1A, LIB, and LIC can be separate inductors. Resonator 62 of Fig. 17 can be equivalently implemented as shown in Fig. 18 where inductor LI is divided into five portions L1A, L1BU, L1BV, LICU, and L1CV. The sum of the L1BU and L1BV inductances equals the LIB inductance. Likewise, the sum of the LICU and L1CV inductances equals the LIC inductance. Elements L1A, L1BU, L1BV, LICU, and L1CV may all be separate inductors. The resonance frequency characteristics of resonator 62 in Fig. 18 can alternatively be achieved by splitting each of capacitors CA and CB into two parts and grounding the lower capacitor plates. Fig. 19 shows how this alternative is achieved. Capacitor CA is replaced with a pair of equal-value capacitors CAU and CAV whose equivalent series capacitance equals the CA capacitance. Likewise, capacitor CB is replaced with a pair of equal- value capacitors CBU and CBV whose series equivalent capacitance equals the CB capacitance. In the manner described in the last two paragraphs, resonator 62 of Fig. 16 can be equivalently implemented by simply deleting elements LICU, L1CV, and CB in Fig. 18. The resonance frequency characteristics of the so-modified version of resonator 62 in Fig. 16 can then be alternatively achieved by simply deleting elements LICU, L1CV, CBU, and CBV in Fig. 19. These principles readily extend to embodiments of resonator 62 having more inductor portions or inductors in series than shown in Figs. 16 - 19. As a further alternative, the resonant frequency 5 characteristics of resonators 62 in Figs. 16 - 19 can largely be achieved by using a distributed inductance- capacitance network commonly referred to as a transmission line. An example of this is depicted in Fig. 20 where the resonator 62 consists of a transmission line 68. Although 10 inductance and capacitance are normally distributed equally along a transmission line, the inductance and capacitance can be distributed unequally along transmission line 68. Resonator 62 in Fig. 20 is an approximate analog to resonator 62 in Fig. 19. 15 In providing CKR and CKR waveforms with odd-numbered f R harmonics above the first harmonic, the magnitude of the AC impedance as seen from driver 56 reaches local minima when f CKR is at odd multiples of f CKI . This is qualitatively illustrated in Fig. 21. Also, the phase 20 angle of the AC impedance is approximately zero at the odd-numbered f R harmonics. In complementary-clock embodiments where resonating section 58 is implemented with resonator 62 , section 58 can be modified by placing one or two switches or one or 25 two capacitors in series with resonator 62 between clock lines 52 and 54. Fig. 22 illustrates an example in which a switch 70 is inserted between line 52 and resonator 62. Fig. 23 depicts a similar example utilizing a capacitor CR. These two implementations of section 58 enable the 30 clocking circuitry to go into an inactive mode without consuming shut-down power while certain other (typically asynchronous) parts of the circuit are active. Fig. 24 illustrates a partial embodiment of Fig. 4 in which control circuit 60 consists of a phase comparator 35 72, an M-bit up/down counter 74, an M-to-2 M decoder 76, 2 M switches 78, and 2 M trimming capacitors CT. M is typically 8 or more. Each switch 78 consists of a pair of complementary insulated-gate FETs QNT and QPT arranged as a transmission gate. Control 60 in Fig. 24 can be used in any of the above-described embodiments of Fig. 4 for adjusting resonance frequency f R when the nominal value C P1N of parasitic capacitance CPl is less than the parasitic capacitive value that would cause f R to equal f CKI . This embodiment of control 60 interposes one or more of capacitors CT between lines 52 and 54 so as to effectively increase C P1 and C p2 . Phase comparator 72 senses the phase difference between input clock CKI and circuit clock CKR. Depending on the phase difference, comparator 72 either sends a signal UP to counter 74 to cause it to count up, or a signal DN to counter 74 to cause it to count down. In response, counter 74 furnishes decoder 76 with an M-bit signal CTR that indicates the number of capacitors CT to be interposed between lines 52 and 54. Decoder 76 then sends decode signals DC that cause appropriate ones of switches 78 to be closed (activated) to place the desired amount of capacitance between lines 52 and 54. Fig. 25 illustrates an embodiment of phase comparator 72 in Fig. 24. In Fig. 25, comparator 72 is formed with CMOS inverters 80 and 82, a transmission gate 84, a charge-storage capacitor CS, CMOS inverters 86 and 88, and a D-type flip-flop 90. Transmission gate 84 consists of a pair of complementary insulated-gate FETs NS and PS connected in parallel. Components 80 - 84 and CS form a sample-and-hold subcircuit which senses the phase difference between clocks CKR and CKI by sampling the voltage level of circuit clock CKR during its rising edge in response to the rising edge of input clock CKI to produce a corresponding sample-and-hold signal SH. Inverter 80 also inverts clock CKI to produce an inverted input clock signal CKI . Capacitor CS stores the sampled CKR voltage during the high CKI phase. Inverters 86 and 88 form a buffer that amplifies signal SH to a logic "1" or logic "0" depending on the sign of the phase difference. When clock CKI goes low, the amplified SH signal is loaded into flip-flop 90 whose Q and Q outputs provide signals UP and DN to counter 74 in synchronism with input clock CKI . When resonance frequency f R is greater than input frequency f CKI , the CKR waveform leads the CKI waveform. The phase difference is positive. Flip-flop 90 receives a "1" which causes counter 74 to count up. The reverse occurs when f R is less than f CKI so as to cause counter 74 to count down. Fig. 26 illustrates a single-clock implementation of the synchronous circuit in Fig. 3. In this single-clock implementation, resonating section 58 of Fig. 3 consists of passive resonator 62 and a non-parasitic resonance capacitor Cl connected in series between circuit clock line 52 and circuit ground. Any of the embodiments of resonator 62 shown in Figs. 5, 9, 10, 13, and 16 - 20 can be used in the implementation of Fig. 26. Function circuitry 14 in Fig. 26 consists of function elements 14F that receive circuit clock CKR on line 52 by way of the clock net. When circuit clock CKR goes from high to low during a half clock cycle so as to cause parasitic capacitance CPl to discharge, the CPl charge largely flows along line 52 and through resonator 62 to capacitor Cl which thereby charges up. During the next half clock cycle when CKR returns to its high value, the charge in capacitor Cl flows back through resonator 62 and along line 52 to recharge capacitance CPl. The charge on capacitance CPl is thus reused to keep power consumption low. Fig. 27 depicts an embodiment of Fig. 26 in which resonator 62 is implemented as in Fig. 10, and control circuit 60 consists of a phase comparator 100 and variable capacitor CA1. Phase comparator 100 senses the phase difference between clocks CKR and CKI. Comparator 100 then adjusts resonance frequency f R by supplying control signal PC to capacitor CA1 to increase or decrease its capacitance. Control 60 in Fig. 27 is utilized when nominal parasitic capacitive value C P1N is less than the parasitic capacitive value that would cause f R to equal f CKI • Fig. 28 illustrates simplified clock waveforms for the circuit of Fig. 27. Elements L2 and C2 in resonator 62 of Fig. 27 are chosen so as to incorporate the third f R harmonic into the CKR waveform. As shown in Fig. 28, the CKR waveform thereby provides a reasonable approximation to a square wave. Fig. 29 illustrates a partial embodiment of Fig. 26 where resonator 62 is implemented as in Fig. 13, and driver 56 consists of a pre-driver 102 and complementary FETs QNI and QPI as in driver 56 of Fig. 14. Pre-driver 102 in Fig. 29 furnishes switching signals Nl and PI in response to input clock CKI and additional input signal(s) NPI. Signals Nl and PI have the characteristics described above in connection with Figs. 14 and 15. FETs QNI and QPI likewise respond to signals Nl and PI in the manner described above for Fig. 14. The circuit in Fig. 29 thus has the same type of power advantages as the circuit of Fig. 14. The simplified CKI and CKR clock waveforms of Fig. 15 also apply to the circuits of Fig. 29. Turning to Fig. 30, it illustrates a partial single- clock implementation of the circuit of Fig. 3 where driver 56 consists of a pre-driver 104 and a pair of switches 106 and 108. In response to input clock CKI and input signal(s) NPI, pre-driver 104 generates switching signals NS and PS that typically have the characteristics described above for switching signals Nl and PI. Fig. 31 illustrates simplified waveforms for signals NS and PS. Switches 106 and 108 are connected in series between the V HH supply and ground. The interconnection point of switches 106 and 108 provides driver clock signal CKD on a driver clock line 110. Switches 106 and 108 operate in response to signals NS and PS in the same way that FETs QNI and QPI respond to signals Nl and PI in the circuits of Figs. 16 and 26. Consequently, driver 56 in Fig. 30 generates driver clock signal CKD at low power consumption. Resonating section 58 of Fig. 3 is implemented in Fig. 30 with a resonator 112 and resonance capacitor Cl whose lower plate is grounded. Resonator 112 consists of a transformer Tl whose primary coil is connected between line 110 and the upper Cl plate. The secondary coil of transformer Tl is connected between circuit clock line 52 and the upper Cl plate. Transformer Tl enables circuit clock CKR to have a greater voltage swing than input clock CKI. Fig. 31 also indicates simplified versions of the CKI and CKR waveforms. The secondary coil of transformer Tl may utilize, or be modified to utilize, any of the arrangements of Figs. 10, 13, and 16 - 20. Fig. 32 depicts a single-clock implementation of Fig. 3 in which components 56 and 60 are merged into a composite driver/control circuit 56/60 that provides driver clock signal CKD on a driver clock line 114. In Fig. 32, resonating section 58 of Fig. 3 again consists of passive resonator 62 and capacitor Cl. Resonator 62 in Fig. 32 can be implemented using any of the embodiments of Figs. 5, 9, 10, 13, and 16 - 20. Instead of circuit clock line 52 being connected to driver/control circuit 56/60, the interconnection node between resonator 62 and capacitor Cl is connected to circuit 56/60 by way of driver clock line 114. The value Cl of capacitor Cl in the circuit of Fig. 32 is chosen to significantly exceed the nominal value C P1N of parasitic capacitance CPl. This enables capacitor Cl to hold a greater charge than capacitance CPl at a given voltage. A voltage magnification approximately equal to C I/ C P I N thereby occurs when the Cl charge is transferred to capacitance CPl. Because driver clock CKD is supplied to the node between capacitor Cl and resonator 62, circuit clock CKR achieves a greater voltage swing than both driver clock CKD and input clock CKI. The CKR voltage swing in the circuit of Fig. 32 also exceeds the supply voltage for the circuit. For example, when V HH is 5 volts, circuit clock CKR can attain a voltage swing of 7 volts. The increased CKR voltage swing is obtained without adding a second power supply. Fig. 33 illustrates the increased CKR voltage swing for the case in which the CKR waveform include the third f R harmonic. Aside from the unbalanced capacitive values and the different connections for resonator 62, the circuit in Fig. 32 basically operates in the manner described above for Fig. 26. Fig. 34 illustrates a partial embodiment of Fig. 32 in which function circuitry 14 contains a flip-flop 116 similar to flip-flop 26 in Figs. 2 and 7. Flip-flop 116 consists of a data input buffer, a master portion, a slave portion, and an output buffer. As in Figs. 2 and 7, the input buffer is formed with CMOS inverter 28 while the output buffer consists of CMOS inverters 46 and 48. The master portion of flip-flop 116 is formed with transmission gates 118 and 120 and CMOS inverters 34 and 36. The slave portion is formed with transmission gates 122 and 124 and CMOS inverters 42 - 44. Instead of being CMOS gates like transmission gates 30, 32, 36, and 38 in Figs. 2 and 7, transmission gates 118 - 124 in Fig. 34 are single-FET gates respectively formed with FETs QA1 - QD1. Because the CKR voltage swing goes somewhat below ground and somewhat above V HH , the second FET used in each of gates 30, 32, 36, and 38 of Figs. 2 and 7 is not necessary in the circuit of Fig. 34. The part count is thereby reduced. Fig. 35 illustrates a hybrid single-clock implementation of the circuit in Fig. 3 where components 56 and 60 are again merged into driver/control circuit 56/60. In this case, circuit 56/60 furnishes circuit clock CKR and driver clock CKD respectively on circuit clock line 52 and a driver clock line 126. Clocks CKR and CKD are complementary to each other. Resonating section 58 of Fig. 3 again consists of resonator 62 and resonance capacitor Cl in Fig. 35. Driver clock line 126 is connected to the interconnection point between capacitor Cl and resonator 62. The circuit in Fig. 35 basically operates in the manner described above for the circuit of Fig. 26. Because clocks CKR and CKD are complementary, the CKR waveform should be quite symmetrical. Fig. 36 depicts another single-clock implementation of the circuit in Fig. 3 where components 56 and 60 are merged into driver/control circuit 56/60. Resonator 62 in Fig. 36 is connected between circuit clock line 52 and a low-impedance source 128 that provides an intermediate power supply voltage V H approximately equal to the time- averaged voltage of circuit clock CKR. Typically, supply voltage V H is V HH /2. When parasitic capacitance CPl discharges during a half clock cycle in the circuit of Fig. 36, the CPl charge is largely transferred to V H supply 128. During the next half clock cycle, supply 128 charges capacitance CPl, thereby keeping power consumption very low. Capacitor Cl may optionally be connected between resonator 62 and ground to ensure that system efficiency is high. In some of the previous embodiments of Fig. 3, driver 56 can be replaced with an oscillator that is not directly forced by an external stimulus such as input clock CKI. Instead, the forcing stimulus is derived from internal circuit clock CKR and/or internal circuit clock CKR so as to provide the phase shift needed to induce oscillation. Equivalently, driver 56 can be converted into such an internally driven oscillator by coupling clock CKR or CKR back to the CKI input of driver 56. The internally driven oscillator tends to oscillate at resonance frequency f R . Controlling frequency f R 5 thereby controls circuit clock frequency f CKR . The oscillator becomes a controllable oscillator employable, for example, in a phase-locked loop. One or more dividers or multipliers may be used to generate f CKR at some multiple or fraction of an external reference frequency. 10 Fig. 37 depicts a partial implementation of the circuit in Fig. 4 where driver 56 is replaced with an internally driven oscillator 130 connected between internal clock lines 52 and 54. Oscillator 130 contains an inverter circuit formed with a single CMOS inverter 15 132. Alternatively, the inverter circuit could be formed with an odd number of CMOS inverters connected front-to- back in series. Oscillator 130 also contains resistors Rl and R2 that provide bias and impedance matching. Fig. 38 illustrates a general configuration for a 20 synchronous electronic circuit containing a resonant system 140 that supplies clock pulses to function circuitry 14 at low power consumption according to the invention. Resonant system 140 oscillates at circuit clock frequency f CKR in response to input (or reference) 5 clock signal CKI at input clock frequency f CKI . In system 140, f CKR is substantially an integer multiple of f CK ι, where the lowest integer multiplier is 1. Accordingly, f CKR is substantially proportional to f CKI . Resonant system 140 supplies circuit clock CKR to 0 function circuitry 14 and, in complementary-clock implementations, supplies circuit clock CKR to circuitry 14. Parasitic capacitance CPl associated with circuit clock line 52 and, when present, parasitic capacitance CP2 associated with circuit clock line 54 have the meanings 5 described above in connection with the circuit of Fig. 3. Aside from the fact that f CKR is substantially proportional to f CKI but (unlike the circuit of Fig. 3) is not necessarily substantially equal to f CKI , clocks CKI, CKR, and CKR have the characteristics described above in connection with the circuit of Fig. 3. Resonant system 140 consists of a phase/frequency comparator 142, a low-pass filter 144, a variable- frequency oscillator ("VFO") 146, and an optional divide- by-N pulse counter 148 all arranged in a phase-locked loop. The input signals to phase/frequency comparator 142 are input clock CKI and a loop feedback signal LF at a feedback clock frequency f LF . Comparator 142 senses the difference between frequencies f CKI and f LF and provides a comparator voltage signal VC indicative of the frequency difference. Filter 144 filters signal VC to produce a control voltage signal VF. VFO 146 oscillates at circuit clock frequency f CKR as determined by control signal VF. VFO 146 also furnishes circuit clock CKR and, when present, circuit clock CKR. In response to clock CKR, pulse counter 148 divides f CKR by an integer N to produce feedback signal LF at frequency f LF . That is, f LF approximately equals fcκ R N * f counter 148 is not present, the loop is completed by supplying clock CKR directly to the LF input of comparator 142. The phase-locked loop forces f LF to be substantially equal to f CKI . Consequently, f CKR substantially equals Nf CKI where N is 1 in the absence of counter 148. VFO 146 is formed with a small driver 150, resonating section 58, and frequency adjustor 152. Driver 150 generates driver clock signal CKD in response to circuit clock CKR and/or circuit clock CKR. Driver 150 may also generate circuit clock signal CKD. Responsive to driver clock CKD and, when present, driver clock CKD, resonating section 58 produces circuit clocks CKR and CKR in the manner described above in connection with Fig. 3. Depending on the configurations of components 150 and 58, clocks CKR and CKD may be the same clock. Likewise, clocks CKR and CKD may be the same. Frequency adjustor 152 controls the value of f CKR in response to control voltage VF. Resonant system 140 transfers charge between parasitic capacitance CPl and a temporary storage site in the manner described above for resonant system 50 in Fig. 3. As with system 50, the temporary storage site is usually a capacitor in a single-clock implementation of system 140. In this case, resonating section 58 typically consists of resonator 62 in series with the capacitor. In a complementary-clock implementation, the temporary storage site is normally parasitic capacitance CP2. Section 58 then simply consists of resonator 62. System 140 oscillates very close to its fundamental resonance frequency f R in largely the same manner as system 50. In essence, components 142, 144, and 148 - 152 in resonant system 140 form a controllable driver that, like the controllable driver formed by components 56 and 60 in resonant system 50, operates in response to input clock CKI for providing the small amount of energy needed to sustain the oscillations of resonating section 58 at circuit clock frequency f CKR very close to resonance frequency f R . The two drivers differ in that f CKR , and thus f R , can exceed input clock frequency f CKI in system 140 but are substantially equal to f CKI in system 50. Fig. 39 shows part of a complementary-clock implementation of the synchronous circuit in Fig. 38. Resonating section 58 here consists of resonator 62 connected between lines 52 and 54. Resonator 62 in Fig. 39 can be implemented with any of the embodiments shown in Figs. 5, 9 , 10, 13, and 16 - 20. Frequency adjustor 152 is formed with variable capacitors CA1 and CA2 whose values are controlled by voltage VF. Because capacitors CA1 and CA2 are respectively in parallel with parasitic capacitances CPl and CP2, the nominal CPl and CP2 values are usually less than the parasitic capacitive values which would cause the phase-locked loop to lock onto input clock CKI. The synchronous circuit of Fig. 3 or 38 is often a single monolithic IC. Alternatively, function circuitry 14 can be divided among multiple monolithic ICs mounted on a common substrate. Resonant system 50 or 140 may be part of one of these ICs or contained in a separate monolithic IC. However, resonator 62 and, when present, capacitor Cl are often (a) provided as discrete components separately mounted on the substrate, (b) formed by metalization and dielectric layers on the substrate, or (c) provided on a separate substrate. Ceramic typically yields the best stability and performance as the substrate material. Fig. 40 illustrates part of a complementary-clock implementation of Fig. 3 or 38 in which the components of circuitry 14 are distributed among a group of monolithic ICs 160 mounted on a ceramic substrate 162. While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, the components of function circuitry 14 as well as resonant systems 50 and 140 could be implemented in bipolar or BiCMOS technology. PZT-type piezoelectric material may be suitable for manufacturing the elements of resonator 62. Adjustable capacitors could be implemented with varicap diodes—i.e., reverse-biased semiconductor diodes whose capacitances depend on the applied reverse-bias voltages. Lower capacitor plates described as being connected to ground could generally be connected to a source of a voltage whose frequency is much lower than f CKR , typically at least ten times lower. Analogous to what is shown in Fig. 24 for complementary-clock implementations, a controllable capacitance network for single-clock implementations could be formed with a group of capacitor-gate pairs connected in parallel between circuit clock line 52 and ground, each capacitor-gate pair consisting of a transmission gate in series with a trimming capacitor. The transmission gate could be formed with a single insulated-gate FET or a pair of complementary insulated-gate FETs connected in parallel. Two such grounded networks could be used in complementary-clock implementations, one connected to each of clock lines 52 and 54. A frequency multiplier or divider could be placed at the input to driver 56 in the circuit of Fig. 3. As a result, f CKR would substantially equal the resultant multiple or fraction of f CKI . As transistor switching speeds increase, parasitic inductances cause ringing problems to become progressively more severe. The resonance technique of the invention could be utilized to partially overcome the ringing by utilizing a resonance inductor whose inductance approximately equals the value needed for resonance minus the estimated value of the parasitic inductance. Various modifications and applications may thus be made by those skilled in the art without departing from the true scope and spirit of the invention as defined in the appended claims.

Claims: I CLAIM : 1. An electronic circuit comprising: a resonant system which, in response to an input clock signal at an input clock frequency, oscillates at a circuit frequency substantially proportional to the input clock frequency to generate a first circuit clock signal at the circuit frequency, the resonant system being operated close to a fundamental resonance frequency such that the resonant system is largely in resonance; and function circuitry which performs electronic functions in synchronism with the circuit clock signal. 2. An electronic circuit as in Claim 1 wherein the resonant system comprises a resonator and a non-parasitic capacitor coupled in series between (a) a circuit clock line on which the circuit clock signal is transmitted and (b) a source of a substantially fixed reference voltage or other voltage at a much lower frequency than the circuit frequency. 3. An electronic circuit as in Claim 1 wherein the resonant system comprises a resonator coupled between (a) a circuit clock line on which the circuit clock signal is transmitted and (b) a source of a reference voltage approximately equal to the time-averaged voltage of the circuit clock signal. 4. An electronic circuit as in Claim 3 wherein the resonant system includes a non-parasitic capacitor coupled between (a) the source of the reference voltage and (b) a source of a substantially fixed further reference voltage or other voltage at a much lower frequency than the circuit frequency. 5. An electronic circuit as in Claim 1 wherein the resonant system generates a second circuit clock signal substantially inverse to the first circuit clock signal, at least part of the electronic functions of the function circuitry also being performed in synchronism with the second circuit clock signal. 6. An electronic circuit as in Claim 5 wherein the resonant system comprises a resonator coupled between a pair of circuit clock lines on which the circuit clock signals are respectively transmitted. 7. An electronic circuit as in Claim 6 wherein the resonant system includes at least one switch or capacitor coupled between the clock lines in series with the resonator. 8. An electronic circuit as in Claim 2 - 4, 6, or 7 wherein the resonator comprises a non-parasitic main inductive device comprising an inductor or a group of inductors coupled to one another in series. 9. An electronic circuit as in Claim 8 wherein the main inductive device has a controllably variable inductance. 10. An electronic circuit as in Claim 8 or 9 wherein the resonator includes at least one inductive-capacitive arrangement coupled in parallel with at least part of the main inductive device, each inductive-capacitive arrangement comprising an inductor and a capacitor coupled to each other in series. 11. An electronic circuit as in Claim 8, 9, or 10 wherein the resonator includes at least one capacitor coupled in parallel with part of the main inductive device. 12. An electronic circuit as in Claim 8 - 10 or 11 wherein the resonator includes at least one capacitor coupled between an internal point of the main inductive device and a source of a substantially fixed reference voltage or other voltage at a much lower frequency than the circuit frequency. 13. An electronic circuit as in Claim 8 - 11 or 12 wherein the resonator includes a distributed capacitor coupled to multiple points of the main inductive device. 14. An electronic circuit as in any preceding claim wherein the resonant system includes control circuitry that adjusts the fundamental resonance frequency. 15. An electronic circuit as in Claim 14 wherein the control circuitry adjusts the fundamental resonance frequency by changing inductance and/or capacitance values. 16. An electronic circuit as in Claim 14 or 15 wherein the control circuitry includes at least one variable capacitor whose capacitance is adjustable in response to at least one control signal. 17. An electronic circuit as in Claim 14, 15, or 16 wherein the control circuitry is arranged in a phase- locked loop. 18. An electronic circuit as in Claim 14 or 15 wherein the control circuitry includes a plurality of capacitive-gate arrangements coupled to one another in parallel for controllably changing capacitance values in response to at least one control signal, each capacitive- gate arrangement comprising a capacitor and a transmission gate coupled to each other in series. 19. An electronic circuit as in Claim 14 - 17 or 18 wherein the control circuitry includes a phase comparator that compares the phases of the input clock signal and the first circuit clock signal. 20. An electronic circuit as in any preceding claim •wherein oscillati ns of the resonant system locally reach maximum amplitude when they occur at the fundamental resonance frequency. 21. An electronic circuit as in any preceding claim wherein the circuit frequency is substantially an integer multiple of the input frequency, whereby the fundamental resonance frequency approximately equals the same integer multiple of the input frequency, the integer multiple including one as the lowest integer multiplier. 22. An electronic circuit as in Claim 21 wherein the resonant system controllably adjusts the fundamental resonance frequency towards the integer multiple of the input frequency. 23. An electronic circuit as in any preceding claim wherein the resonant system includes a driver via which each circuit clock signal is supplied in response to the input clock signal. 24. An electronic circuit as in Claim 2 wherein the resonant system includes a driver responsive to the input clock signal for providing a driver signal to a node between the resonator and the capacitor. 25. An electronic circuit as in Claim 23 or 24 wherein the driver comprises: a pre-driver that generates a pair of switching signals substantially in synchronism with the input clock signal, each switching signal having an active level and an inactive level, each switching signal being at its inactive level only when the other switching signal is at its active level, whereby only one of the switching signals is active at any time; and a pair of switches coupled together to a driver line and coupled in series between a pair of different voltage supplies, the switches being respectively responsive to the switching signals for enabling current to flow through the driver line when either switching signal is at its active level. 26. An electronic circuit as in Claim 25 wherein the switches comprise a pair of complementary field-effect transistors having respective drains coupled together to the driver line, respective sources respectively coupled to the voltage supplies, and respective gate electrodes that respectively receive the switching signals. 27. An electronic circuit as in any preceding claim wherein the system oscillations include frequency components attributable to at least one resonance frequency other than the fundamental resonance frequency. 28. An electronic circuit as in Claim 27 wherein the system oscillations include harmonics of approximately the fundamental resonance frequency. 29. An electronic circuit as in Claim 28 wherein the harmonics are odd-numbered harmonics. 30. An electronic circuit as in any preceding claim wherein each circuit clock signal has a substantially different voltage swing than the input clock signal. 31. An electronic circuit as in any preceding claim wherein each circuit clock signal has a substantially greater voltage swing than the input clock signal. 32. An electronic circuit as in Claim 31 wherein the function circuitry includes at least one circuit element containing state circuitry configured substantially as illustrated for the master portion of the flip-flop in Fig. 34. 33. An electronic circuit as in any preceding claim wherein the electronic circuit is part of a single integrated circuit. 34. An electronic circuit as in any preceding claim wherein the electronic circuit is distributed across at least two integrated circuits mounted on a common substrate. 35. An electronic circuit as in any preceding claim wherein the function circuitry comprises CMOS, bipolar, or BiCMOS components. 36. An electronic circuit as in any preceding claim wherein the function circuitry includes level-sensitive state elements. 37. An electronic circuit comprising: function circuitry which performs electronic functions, specified elements of the function circuitry changing state substantially at a circuit frequency in response to at least one input signal that changes state at the circuit frequency; and a resonant system which oscillates at the circuit frequency, the resonant system being operated close to a fundamental resonant frequency such that the resonant system is largely in resonance, the resonant system being coupled to the function circuitry to assist the specified elements in changing state by overcoming capacitances and/or inductances associated with the function circuitry. 38. An electronic circuit as in Claim 37 wherein the system oscillations include components attributable to at least one resonance frequency other than the fundamental resonance frequency. 39. An electronic circuit as in Claim 37 or 38 wherein the system oscillations include harmonics of approximately the fundamental resonance frequency. 40. An electronic circuit as in Claim 39 wherein the harmonics are odd-numbered harmonics. 41. A digital electronic circuit wherein repetitive pulses for control or synchronisation are supplied by resonant charge storage means in preference to resistive switching means. 42. A clock drive circuit having resonant output means adapted to resonate in accordance with a desired clock frequency. 43. A circuit according to claim 41 or 42, further comprising the feature(s) of any of claims 1 to 40.

Inventors: HARVEY GEOFFREY PHILIP, HARVEY, GEOFFREY, PHILIP
Applicants: HARVEY GEOFFREY PHILIP, HARVEY, GEOFFREY, PHILIP
Application year: 1993
Main classification: H03B5
IPC codes: H03B1, H03B5, H03K3, H03K17, H03L7