Method for forming a bipolar transistor

Abstract: A method for forming a bipolar transistor employs a single drive-in step to form an emitter (16) and a base (14). A layer (30) of spin on glass containing a plurality of dopants is spun onto a collector (12) in a silicon substrate. The dopants are driven into the collector (12) to form the base (14) and emitter (16). The method employs diffusion instead of implanting to form shallow and abrupt junctions without damage to the crystal lattice of the silicon.

Description: The present invention relates to methods of producing integrated circuit devices and more specifically to a method of forming a bipolar transistor. Known methods for forming bipolar transistors involve at least two mask, etch, and implant operations in which n-type and p-type impurities are implanted into a collector, typically made of silicon. The base is formed with the first mask, etch, and implant operation. The photoresist layer used during the masking operation is removed and a new photoresist layer is provided before the second implanting operation. The emitter is formed during the second mask, etch, and implant operation. In such a process, the implant energy has to be reduced to produce shallow junctions. This method suffers from the disadvantage that implanting produces defects which lie in the space charge region of the junction. The implanted impurity is brought to rest by an inelastic collision with silicon atoms in the crystal lattice, which damages the crystal lattice structure by knocking silicon atoms out of place. The crystal lattice structure must be epitaxially regrown by a thermal anneal to activate the implanted impurities by incorporating them into the crystal lattice. For shallow junctions, a rapid thermal process (RTP) cycle is typically performed. The damage from implanting is not totally repairable without causing undesirable enhanced diffusion of the impurities which is inconsistent with shallow junction technology. Defect sites having energies in the middle of the band gap remain and produce a conduction path which ultimately causes a leakage current to flow. The document Motorola Technical Developments, Volume 4, April 1984, pages 32-33 discloses a method of achieving so-called one-step transistor formation utilising a liquid source containing a mixture of n-type and p-type dopants which is spun on a semiconductor wafer, baked, and so diffused into the substrate. It is an object of the present invention to provide a simple method for forming a semiconductor device wherein the disadvantages caused by defect sites are alleviated. Therefore, according to the present invention, there is provided a method of forming a semiconductor device, comprising the steps of: spinning a layer of spin on glass over a semiconductor substrate which includes a collector region and wherein the layer of spin on glass includes first and second dopants having different diffusion rates into the semiconductor substrate; heating the substrate to drive the dopants simultaneously into the substrate region, and wherein the first dopant forms a base region and the second dopant forms an emitter region and characterised by the steps or removing a portion of the layer spin on glass over said emitter region; and implanting the exposed emitter region portion with said first dopant to provide a base contact region. One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which:- Fig. 1 is a cross-sectional view of a bipolar transistor formed using the method of the present invention; Fig. 2 is a flow diagram of the method of the present invention; Fig. 3 is a cross-sectional view of the bipolar transistor of Fig. 1 at a point in its formation; Fig. 4 is a cross-sectional view of the bipolar transistor of Fig. 1 at a point in its formation; and Fig. 5 is a cross-sectional view of the bipolar transistor of Fig. 1 at a point in its formation. Referring now to Fig. 1, a bipolar transistor 10 manufactured using the method of the present invention is shown. Transistor 10 includes underlying collector layer 12, base layer 14, emitter layer 16, field oxide portions 18, insulating layer 20, and metal interconnect layer 22. Turning now to Fig. 2, the method of the present invention begins at START 28. In block 30, collector 12, and field oxide portions 18 are defined using known BiCMOS or bipolar process steps. In block 32, layer 33 of doped SOG is spun onto collector 12 at a thickness anywhere between about 10 nm to 15 micrometers, with a preferred thickness of about 300 to 500 nm. Layer 33 preferably includes two dopants, such as boron and phosphorus. A base dopant is chosen which will diffuse faster than the emitter dopant at a predetermined temperature. Preferably, boron is used to form base 14 while phosphorus is used to form emitter 16. Other dopants may include arsenic, antimony, and gold. Arsenic may be used in place of phosphorus to provide more abrupt junctions. Gold may be combined with phosphorus to increase the generation or recombination rate of electrons, thus allowing device 10 to operate at higher frequencies. There are two different ways of doping the SOG. A first way is to put the dopant into the SOG polymer. A second way is to leave the dopant as a free-floating particle suspended outside the polymer. When boron and phosphorus are part of the polymer, concentrations of about 4% boron and about 1% phosphorus have worked well. In block 34, the base and emitter dopants are both driven into collector 12 using a single rapid thermal process (RTP) cycle. This involves heating the substrate to a predetermined temperature for a predetermined time. In one example the substrate is heated to about 1050 degrees Celsius for about 60 seconds. In another example the substrate is heated to about 1100 degrees Celsius for about 40 seconds. The described method enables the formation of devices having shallow and abrupt junctions, without damage to the crystal lattice of the silicon. The width of base 14 may be varied by varying the heating time or temperature. Relatively speaking, smaller base widths can be produced by either lowering the temperature or decreasing the heating time. During the RTP cycle, layer 33 is changed to silicon dioxide, which is an insulator. In block 36, layer 33 may be left in place or removed by a plasma or wet etch process in favour of a better insulator. Undoped silicon oxides are preferred. In block 38, a portion of layer 20 over emitter 16 is removed by a mask and etch operation (Fig. 3). In block 40, boron is implanted into the exposed portion of emitter 16. This step is performed to provide a contact point for base 14 (Fig. 4). In block 42, another portion of layer 20 is removed to provide a contact point for emitter 16. A mask and etch operation is performed (Fig. 5). In block 44, metal interconnect layer 22 is deposited over layer 20. The described method enables the formation of devices having shallow and abrupt junctions, without causing damage to the crystal lattice structure.

Claims: A method of forming a semiconductor device, comprising the steps of: spinning a layer of spin on glass (33) over a semiconductor substrate which includes a collector region (12) and wherein the layer of spin on glass (33) includes first and second dopants having different diffusion rates into the semiconductor substrate; heating the substrate to drive the dopants simultaneously into the substrate region (12), and wherein the first dopant forms a base region (14) and the second dopant forms an emitter region (16) and characterised by the steps of removing a portion of the layer of spin on glass (33) over said emitter region (16); and implanting the exposed emitter region portion with said first dopant to provide a base contact region. A method according to Claim 1, characterised in that said first dopant is boron and said second dopant is phosphorus or arsenic. A method according to Claim 2, characterised in that said second dopant is phosphorus and in that said layer of spin on glass (33) includes a third dopant comprising gold. A method according to any one of the preceding claims, characterised in that said step of heating includes heating said substrate for a predetermined time in a rapid thermal process (RTP) cycle. A method according to Claim 4, characterised in that said predetermined temperature is about 1050 degrees Celsius and said predetermined time is about 60 seconds. A method according to Claim 4, characterised in that said predetermined temperature is about 1100 degrees Celsius and said predetermined time is about 40 seconds. A method according to Claim 1, characterised by the steps of removing a further portion of said layer of spin on glass over said emitter region (16), and depositing a metal interconnect layer (22) over said substrate.

Inventors: ALLMAN DERRYL DWAYNE JOHN, KWONG DIM-LEE, ALLMAN, DERRYL DWAYNE JOHN, KWONG, DIM-LEE
Applicants: HYUNDAI ELECTRONICS AMERICA, NCR INT INC, SYMBIOS INC, NCR INTERNATIONAL, INC., SYMBIOS, INC.
Application year: 1993
Main classification: H01L21
IPC codes: H01L29, H01L21