Balanced driver circuit for eliminating inductive noise

Abstract: A balanced driver circuit (28) essentially eliminates inductive noise without a power dissipation penalty, and is similar to a conventional balanced driver circuit except that the circuit is impedance matched at both ends and has resistors (44,46) connected in series with the outputs of the transistors (40,42) in the chip. The resistors are equal in value to a termination resistor (48,50) less the output impedance (R₀). of the transistors. The impedance between the pair of signal leads (32,34), referred to as the primary and secondary leads, is equal to the sum of the termination resistors (48,50). The current traversing the secondary lead has the same amplitude, but the opposite sign as the current traversing the primary lead. Thus, there is negligible current return through the common ground leads.

Description: This invention relates to circuits for driving electrical signal output leads of an integrated circuit. A major performance limitation of electrical interconnections is inductive noise encountered when one interconnects high-speed, high pin-out integrated circuit (IC) chips having many drivers that switch simultaneously. For example, an array size of 256 x 256 can be fabricated on a single chip, however such large arrays are impractical because of the inductive noise generated by the line drivers driving the output leads of the chip. When a large number of drivers are active simultaneously, a substantial transient current passes through the inductance of the ground and power distribution systems, causing a noise spike to emerge on the power and ground lines. The resulting fluctuation of the power and ground voltage levels can cause false switching of devices with an accompanying error or loss of data. Several techniques have been proposed for reducing inductive noise. At the circuit level, the noise can be reduced by staggering the switching times of the drivers. The staggering of the switching times, however, has the drawbacks of decreased switching speed and increased complexity of clock distribution. At the architectural level, techniques such as the design rule, called the Simultaneous Switching Rule (SSR) can be used to limit the number of drivers that need to be activated simultaneously in a chip. The SSR is a linear inequality that restricts the number of driver circuits allowed to switch simultaneously, so that no logic errors will occur. The restrictions imposed by the SSR however translate into machine cycle time penalties and affect the performance rating of a machine. Thus, a compromise must be made when developing the SSR in order to minimize the impact on the machine cycle. Other approaches also used to reduce inductive noise include chip attachment technologies such as solder bump leads and tape automated bonding (TAB). However, the use of these techniques is substantially more expensive than conventional wire bonding and has not achieved the realiability of wire bond technology. Since wire bonding is a mature and reliable technology with a large capital investment, it is desirable to reduce the inductive noise and retain the wire bond technology. From document PROCEEDINGS OF THE 1990 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING, 17 September 1990, pages 148-151, P. Sandborn et al.: "Switching Noise in ECL Packaging and Interconnect Systems" it is known a circuit having the features of the preamble of claim 1. According to this invention there is provided a circuit as claimed in claim 1. In an embodiment of the invention a balanced driver circuit essentially eliminates inductive noise without a power dissipation penalty. The balanced driver circuit is similar to a conventional balanced driver circuit driving a balanced transmission line but the present driver circuit provides for impedance matching of the transmission line at both ends. This is accomplished by connecting resistors in series with the outputs of the emitter followers in the chip. The resistors are equal in value to a termination resistor less the output impedance of the emitter followers. There is a pair of signal leads, referred to as the primary and secondary leads connected to the resistors. The current traversing the secondary lead has the same amplitude, but the opposite sign as the current traversing the primary lead. Thus there is negligible current return through the common ground leads. This design can be implemented in various logic families including ECL (emitter coupled logic), GaAs, and BiCMOS (bipolar complementary metal-oxide semiconductor) technologies. The driver can also be used for other purposes when driving balanced interconnections on printed wiring boards (PWBs) and multichip modules (MCMs). Brief Description of the Drawings FIG. 1 shows the conventional AC circuit used to drive unbalanced transmission lines; FIG. 2 shows a conventional AC circuit section used to drive balanced transmission lines; FIG. 3 illustrates the output circuit for a balanced driver circuit embodying the invention that exemplarily uses ECL or BiCMOS logic for the on-chip driver circuitry; FIG. 4 illustrates a conventional output circuit for an unbalanced driver circuit using ECL or BiCMOS logic for the on-chip driver circuitry; FIG. 5 illustrates the output circuit for an exemplary balanced driver circuit embodying the invention that comprises GaAs logic for the on-chip driver circuitry; and FIG. 6 illustrates a conventional output circuit for an unbalanced driver circuit using GaAs logic for the on-chip driver circuitry. Detailed Description Referring to the drawings, Fig. 1 illustrates the conventional method used to drive unbalanced transmission lines 6 on a printed wiring board 14 (PWB). Only the AC portion of the circuit is displayed, thus the power supply voltages, bias resistors, voltage planes and by-pass capacitors are omitted. A problem associated with such unbalanced chip driver circuits 1 is that an induced transient potential difference occurs between the ground plane 8 present in the driver integrated circuit 4 and the ground plane 16 associated with the interconnect 14 i.e. , PWB, MCM, that provides electrical communication between the integrated circuits. The difference in ground potential is proportional to the rate of change of the driver current, the number of chip drivers switching, and the combined inductance of the ground return. The rate of change of ground return current, I ˙ g , flows from the terminations 18 located at the chip receivers (not shown), through the ground vias 20, ground plane 16, ground via at the chip 22, wire bond 24 of the chip 4, ground via 26 on the chip 4, and finally to the chip ground plane 8. The magnitude of the inductive noise developed between the two ground planes 8 and 16 is indicated as v n . Neglecting mutual inductances, inductive noise is given, approximated by v n = L s (n I ) N g where L s = self inductance of the ground return path n = number of chip drivers switching simultaneously in the same direction I ˙=rate of change of the signal current (ma/ns) N g = number of ground leads on the chip. Thus, for n = 8, N g = 3, I ˙ = 20 ma/ns, (i.e. IV / (50Ω)(1 ns)) and L s = 2.62 nH ( i.e., a 100 mil wire bond), equation (1) yields an inductive noise v n = 140 mv. This value of v n is significant especially since crosstalk can contribute an equal amount of noise. Additionally as the rise time of the chip is reduced from 1 ns to a value of 0.1 ns, v n increases by an order of magnitude which causes the inductive noise to become overwhelming. The inductive noise, v n can be reduced to a negligible amount by replacing each unbalanced chip driver 2 with a balanced chip driver 30 as illustrated in FIG. 2. There is a pair of driver leads designated as the primary and secondary leads 32 and 34. This correspondence of a pair 32 and 34 is continued to pads 36 and 38 and to the chip receiver (not shown) in the interconnecting equipment i.e. , other IC's in the multichip module (MCM) or other IC's on the PWB. Thus the current traversing the secondary lead 34 has the same amplitude, but the opposite sign as the current traversing the primary lead 32, thus, creating no inductive noise. A drawback of using a conventional balanced chip driver circuit 31 is that twice as much power is needed as compared to the unbalanced driver circuit 1. Further discussion can be found in U.S. Patent Application No. 07/841139, filed on February 25, 1992, entitled Balanced Circuitry For Reducing Inductive Noise Of External Chip Interconnections. This invention replaces the unbalanced driver circuit 1 with a balanced driver circuit 28 which essentially eliminates inductive noise while dissipating the same amount of power as the unbalanced driver circuit 1. This is accomplished by simply replacing each unbalanced driver 2 with a balanced driver 30 illustrated in FIGS. 3 and 5. The balanced driver 30 is comprised of two emitter follower output stages 40 and 42 which are each connected in series with a resistor 44 and 46. The resistors 44 and 46 are each connected in series to either a primary or secondary signal lead 32 and 34 which together is referred to as a balanced transmission line. Terminating the balanced transmission line 32 and 34 are termination resistors 48 and 50. A power supply 52 is connected to the center-tap of the termination resistors 48 and 50. A receiver 53 is connected in parallel to the termination resistors 48 and 50. The balanced transmission line 32 and 34 is impedance matched at both ends. The emitter followers 40 and 42 have an output impedance designated as R 0 . The termination resistors 48 and 50 have values designated as R B . The resistors 44 and 46 each have a value which is equal to the termination resistor 48 or 50 less the output impedance from the emitter followers 40 and 42 designated by R B - R 0 . The pair of signal leads 32 and 34 are internally connected to the integrated circuit so that the current traversing the secondary lead 34 has the same amplitude, but the opposite sign as the current traversing the primary lead 32 as in a conventional balanced chip driver. Thus, no inductive noise, v n = 0, is produced since there is no net rate of change of current flow, I ˙ g = 0, in the ground return path. Additionally the impedance between the leads 32 and 34 is designated as Z B and is equal to twice the value of the termination resistor 48 or 50. The power dissipation resulting from the balanced driver circuit 28 is equal to the power dissipation resulting from the unbalanced driver circuit 1 as a result of the addition of resistors 44 and 46. The value of the resistors 44 and 46 must be of a value equal to the termination resistor 48 or 50 less the output impedance from the emitter follower 40 and 42. The determination of the equal power dissipation condition follows. FIGS. 4 and 6 illustrate the output portion of a conventional unbalanced driver circuit 1 which is impedance matched at the receiver end only. The unbalanced driver circuit 1 is comprised of an emitter follower output stage 56 which has an output impedance designated by R 0 , a signal or transmission line 6 which has an impedance designated by Z 0 , a termination resistor 54 which has a value designated by R T , a power supply 52 which has a voltage designated by -V T and a receiver 58. - V 1 and - V 2 designate the two logic levels experienced by the circuit. The time average power dissipated by the output portion of the unbalance circuit 1 is given by P U = [ 1 2 ][ V T (V T -V 1 ) R T + V T (V T -V 2 ) R T ] or P U = V T (2V T -V 2 -V 1 ) 2R T The dissipated power of the output portion of the unbalanced circuit 1 can also be given by P U = P Ui + P Ue where P Ui = average unbalanced power dissipated internal to the chip ( i.e., the emitter follower 56) and P Ue = average unbalanced power dissipated external to the chip ( i.e. , the termination resistor 54). P Ui is given by P Ui = V 2 (V T -V 2 )+V 1 (V T -V 1 ) 2R T and P Ue is given by P Ue = (V T -V 2 ) 2 +(V T -V 1 ) 2 2R T The power dissipated by the output portion of the balanced circuit 28 which contains resistors 44 and 46, can be considered as twice the unbalanced portion but with R T = 2R B - R 0 . Accordingly, P B = 2 P U | R T = 2R B -R 0 and P B P U = 2R T 2R B - R 0 In analogy with equation (4), the power dissipated in the output portion of the balanced circuit 28 can be given by P B = P Bi + P Be where P Bi = average balanced power dissipated internal to the chip, i.e. , the two emitter followers 40 and 42, and P Be = average balanced power dissipated external to the chip, i.e. , the four resistors 44, 46, 48, 50. P Bi is given by P Bi = 2 P Ui | R T = 2R B -R 0 P Be is given by P Be = 2 P Ue | R T = 2R B -R 0 By imposing the constraint that the power dissipated by the output portions of the balanced 28 and unbalanced driver 1 circuits be equal, then from equation (8) the following results P B P U = 1 or R B = R T + R 0 2 and Z B = 2R B = 2R T + R 0 Interestingly, equation (8) is a general result that holds for general integrated circuit drivers independent of the operating voltages V T ,V 2 , and V 1 . This design can be implemented in various logic families including ECL, BiCMOS (as shown in FIG. 3) and GaAs (as shown in FIG. 5). For example when using ECL technology, let V T = 2 volts, V 2 = 1.705 volts, V 1 = 0.955 volts, R T = 50 ohms, and R 0 = 6 ohms. Using such values produced the following yields for unbalanced as well as balanced driver circuits. Average Power Dissipation of ECL Driver Circuits Having R 0 =6Ω Unbalanced Driver Balanced Driver (R T =50Ω,Z 0 =50Ω) (R B =53Ω,Z B =106Ω) P U =26.80mW P B =26.80mW P Ui =15.01 P Bi =15.01 P Ue =11.79 P Be =11.79 The remaining portions of the output portion of the unbalanced 2 and balanced 30 on-chip drivers not shown in FIGS. 3 - 6 are identical and dissipate equal power. Thus, the values of P Ui and P Bi only account for the average power dissipated by the output emitter followers 56 or 40 and 42 respectively. To account for the power dissipated in the remaining portion of the on-chip ECL driver circuitry, a common power dissipation of about 25mW must be added to both P Ui and P Bi . ECL technology shown in FIG. 3 can be replaced with comparable GaAs technology shown in FIG. 5 with analogous results. For unbalanced 2 and balanced 30 GaAs drivers, assume V T = 2 volts, V 2 = 1.9 volts, V 1 = 0.4 volts, R T = 50 ohms, R 0 = 8 ohms, and R B = 54 ohms. The above equations yield P U = P B = 34mW, P Ui = P Bi = 8.3mW, and P Ue = P Be = 25.7mW. Also, for GaAs the on-chip driver power dissipation not included in P Ui and P Bi is about 225 mW rather than 25mW for ECL technology and the GaAs drivers operate 3-5 times faster than ECL drivers. Implementation using high-speed CMOS (complementary metal oxide semiconductor) technology compatible with ECL logic levels also results in essentially eliminating the inductive noise. However, the circuit dissipates twice the average power dissipated by the unbalanced driver circuit 1. The balanced driver circuit 28 can be used in conjunction with the current chip attachment technique of wire bonds thus making use of the large capital investment in wire bonding automation as well as with new low noise chip attachment technologies such as solder bumps and TAB. The balanced driver circuit 28 provides for the introduction of digital architectures that require large digital words to switch in approximately 0.1 ns or less. When the balanced driver circuit 28 is used to drive balanced interconnections on PWBs 14 and MCMs as described in U.S. Patent Application No. 07/841139, filed on February 25, 1992, entitled Balanced Circuitry For Reducing Inductive Noise Of External Chip Interconnections substantial benefits of reduced crosstalk, increased noise immunity and elimination of ground noise results. Finally, the balanced driver circuit 28 is well suited for high-speed optoelectronics, and the introduction of high temperature superconducting interconnections on MCMs and in high density, high performance electronic systems. It is to be understood that the above-described balanced driver circuit is illustrative and that other arrangements such as replacing the emitter followers with other balanced driver configurations or compensating for the resistors 44 and 46 within the integrated circuit can be readily devised. The scope of the invention is defined by the appended claims.

Claims: A circuit for driving electrical signal output leads of an integrated circuit, comprising first and second transistor output stages (40, 42) each having an output impedance R O and an output terminal, first and second transmission lines (32, 34) each having an output end, first and second termination resistors (48, 50) connected serially between said first and second transmission line output ends, and means (52) for applying a voltage between said first and second termination resistors, and wherein each of said first and second termination resistors has a resistance R B , CHARACTERISED IN THAT each of said transmission lines (32, 34) is serially connected to the said output terminal of a respective one of said output stages (40, 42) through a respective one of first and second resistors (44, 46), and each of said first and second resistors has resistance essentially equal to R B -R O . A circuit according to claim 1, wherein said output stages are implemented using emitter coupled logic. A circuit according to claim 1, wherein said output stages are implemented using GaAs logic. A circuit according to claim 1, wherein said output stages are implemented using bipolar complementary metal oxide semiconductor logic.

Inventors: RAINAL ATTILIO JOSEPH, RAINAL, ATTILIO JOSEPH
Applicants: AT & T CORP, AT&T CORP.
Application year: 1993
Main classification: H03K19
IPC codes: H03K19, H03F1, H04L25