Solid state image sensor

Abstract: The solid state image sensor of the invention comprises a plurality of photosensitive elements arranged in a matrix form, a vertical shift register (66) disposed adjacent each column (65) of said photosensitive elements and adapted to vertically transfer signal charges read from the corresponding photosensitive elements, a storage region (62) for storing signal charges transferred by said vertical shift register (66), and a horizontal shift register (63) adapted to horizontally transfer signal charges read from said storage region (62), wherein said storage region (62) has a capacity to store signal charges from all the photosensitive elements independently and the number of transfer stages of said vertical shift register (66) is equal to 1/n (n is an integer greater than 2) of the vertical number of said photosensitive elements.

Description: The present invention relates to a solid state image sensor including a charge-coupled device Solid state image sensors are in common use of late as the imaging components of video cameras. Broadcasting cameras, in particular, include a solid state image sensor of the so-called frame interline transfer type which comprises an imaging region consisting of photosensitive elements and vertical shift registers, a storage region adapted to store signal charges, a horizontal shift register and a buffer amplifier so that the signal charges stored in photosensitive elements during an integrating time may be transferred at high velocity during the vertical blanking interval. The conventional solid state image sensor and its driving method are now described in some detail. Fig. 1 is a schematic view showing a representative prior art solid state image sensor. As shown, its imaging region 1 comprises a multiplicity of photosensitive elements 5 arranged in a matrix form and a plurality of vertical shift registers 6 adapted to transfer signal charges read out of the corresponding photosensitive elements 5 in a vertical direction. The storage region 2 comprises a plurality of vertical shift registers 7 which store the signal charges transferred from the imaging region 1 and line-transfer these signal charges to a horizontal shift register 3. The buffer amplifier 4 is a means for outputting the signal charges transferred to said horizontal shift register 3. In the above prior art solid state image sensor, each vertical shift register 6 has two independent transfer electrodes per picture element and transfers a block of signal charges by means of four transfer electrodes as an independent unit. Thus, the number of stages of said vertical shift register 6 is one-half of the number of photosensitive elements 5 in one vertical column and the number of stages of the vertical shift register 7 comprising the storage region 2 is equal to the number of stages of said vertical shift register 6. The method for driving the prior art solid state image sensor illustrated in Fig. 1 is now explained. Fig. 2 (a), Fig. 2 (b), Fig. 2 (c) and Fig. 2 (d) show the timing charts of the driving method for the prior art solid state image sensor. Thus, Fig. 2 (a) represents the composite synchronizing pulse, Fig. 2 (b) represents the vertical transfer pulse applied to the vertical shift register 5, Fig. 2 (c) represents the vertical transfer pulse applied to the storage region 2, and Fig. 2 (d) represents the horizontal transfer pulse applied to the horizontal shift register 3. Referring, first, to Fig. 2 (a), the driving method comprises reading out the signal charges from the photosensitive elements 5 in sets of two each during the vertical blanking interval 21a of A field and the vertical blanking interval 21b of B field and transferring the signal charges to the storage region 7 through the vertical shift register 6 and outputting them as a picture signal from the buffer amplifier 4. This sequence is explained in further detail taking A field as an example. First, as shown in Fig. 2 (b), the unnecessary charges accumulated in the vertical shift register 6 are swept by a sweeping pulse 22 in the vertical blanking interval 21a. Then, the signal charges accumulated in every other photosensitive elements 5 in the vertical direction are read out to the vertical shift register 6 by a read pulse 23. Then, the signal charges in the vertically adjacent photosensitive elements 5 are mixed by a mixing pulse 24 and transferred to the storage region 2 by a transfer pulse 25. Thereafter, as shown in Fig. 2 (c), the signal charges are horizontally line-transferred, during each horizontal transfer interval, from the vertical shift register 7 of the storage region 2 to the horizontal shift register 3 by a line transfer pulse 26. Then, the unnecessary charges remaining in the vertical shift register 7 are swept by a sweeping pulse 27 and signal charges from the imaging region 1 are freshly transferred by a transfer pulse 28. Thereafter, as shown in Fig. 2 (d), the signal charges are transferred to the horizontal shift register 3 by a horizontal transfer pulse 29 and outputted as a picture signal from the buffer amplifier 4. Regarding B field, a picture signal is outputted from the buffer amplifier 4 in the same manner as above except that signal charges from a different combination of photosensitive elements 5 from that used for A field are dealt with. Now, the method for driving the storage region of the prior art solid state image sensor is explained. Fig. 3 (a) is a waveform diagram showing the driving signal applied to the storage region of the prior art solid state image sensor and Fig. 3 (b) is a potential profile of the storage region of the same solid state image sensor. These diagrams pertain to the 4-phase driving mode and the drive pulses represented by ø 1, ø 2, ø 3 and ø 4 in Fig. 3 (a) are applied to 4 transfer electrodes per group of the storage region 2. The potential profile across a vertical section of the vertical shift register 7 of the storage region 2 can be represented as Fig. 3 (b). Thus, signal charges 31 are transferred from A to B to C to D. The maximum signal quantity that can be dealt with in the vertical shift register 7 of the storage region 2 is defined by the potential well formed by drive pulses ø 2 and ø 3 as shown at A in Fig. 3 (b). However, in the above solid state image sensor wherein signal charges from all the photosensitive elemente are transferred in a lump oum to tho storage region 2, the maximum signal quantity that can be handled is limited to the quantity of signals which the vertical shift register 6 can manage to transfer in one operation so that the dynamic range is inevitably low. Furthermore, in the above solid state image sensor, the signal charges of all the photosensitive elements cannot be transferred independently in the discrete form to the storage region 2 within the vertical blanking interval, no progressive-scan can be achieved. EP-A-0 286 123 relates to a solid state imaging device having a high speed shutter function. The device comprises an imaging section having photosensitive and vertical high speed transfer sections. The device further comprises a storage section to which storage charges held in the photosensitive section are transferred by the vertical high speed transfer section in units of lines. The charges stored in the storage section are transferred in units of lines by a line transfer section. Both the high speed transfer section and the storage section receive four pulse signals from a driver. The number of elements in the high speed transfer section is twice the number of elements in the photosensitive section. The device may include more than one storage region. JP-A-3 153 176 and PAJ Vol. 15, No. 383, E-1116 describes a solid-state image pickup device having a solid-state image pickup element comprising photoelectric conversion elements and first and second layer electrodes. The number of electrodes to form one potential well is 4. The signals output from the image pickup element are converted by an A/D converter, and the converted signals are then stored in a memory. EP-A-0 361 938 describes solid-state image sensing devices comprising a light receiving device having a number of light receiving elements arranged in the form of a matrix. The device may comprise a store part which is formed of 4-phase transfer electrodes receiving voltages from four transfer electrodes. US-A-4,959,724 relates to a solid-state imaging apparatus and driving method. The apparatus comprises an image pickup section having a two-dimensional array of photodiodes, and a memory section. The memory section receives four pulse trains. Further, the use of two transfer gate pulse signals, each comprising of two pulses described. The time period between these pulses are storage times which may be equal. EP-A-0315778 discloses solid state image pickup apparatus comprising eight photosensitive elements in each column. Further, there are provided column direction charge transfer devices which are made up of four stages, each stage corresponding to two photosensitive elements. Further, there are described apparatus including eight photosensitive elements in each column and a column directional transfer device which has eight transfer stages, each corresponding to each one of the photosensitive elements. Further, an apparatus is disclosed in which the series of photosensitive elements are used in common to act as the column directional transfer device. It is the object of the invention to provide a solid state image sensor capable of performing a progressive scan and having increased signal quantity that can be handled to expand the dynamic range. This object is solved according to the invention as claimed in the independent claim. According to the invention, the number of transfer stages of the vertical shift register which is disposed adjacent each column of photosensitive elements, is equal to 1/n (n is an integer greater than 2) of the vertical number of said photosensitive elements. Preferred embodiments of the invention are defined in the dependent claims. The invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings. Fig. 1 is a schematic view showing the prior art solid state image sensor; Fig. 2 (a), Fig. 2 (b), Fig. 2 (c) and Fig. 2 (d) show the timing charts of the driving method for the prior art solid state image sensor; Fig. 3 (a) is a waveform diagram showing the driving signal applied to the storage region of the prior art solid state image sensor; Fig. 3 (b) is a potential profile of the storage region of the same solid state image sensor; Fig. 4 (a) and Fig. 4 (b) are elementary diagrams illustrating a solid state image sensor and its driving method; Fig. 5 (a), Fig. 5 (b), Fig. 5 (c) and Fig. 5 (d) are diagrammatic representations of the method for driving the solid state image sensor of Fig.4 on an interlaced-scan mode; Fig. 6 is an elementary diagram showing another solid state image sensor; Fig. 7 (a), Fig. 7 (b), Fig. 7 (c) and Fig. 7 (d) are timing charts of the method for driving the solid state image sensor of Fig. 6; Fig. 8 is an elementary diagram illustrating another solid state image sensor and its driving method; Fig. 9 (a) and Fig. 9 (b) are timing charts of the method for driving the solid state image sensor of Fig.8; Fig. 10 (a), Fig. 10 (b), Fig. 10 (c), Fig. 10 (d), Fig. 10 (e) and Fig. 10 (f) are timing charts of the first method for driving another solid state image sensor; and Fig. 11 (a), Fig. 11 (b), Fig. 11 (c), Fig. 11 (d) and Fig. 11 (e) are timing charts of the second method for driving the solid state image sensor refered to in Fig.10. As shown in Fig. 4 (a) and Fig. 4 (b), this solid state image sensor comprises an imaging region 41, a storage region 42, a horizontal shift register 43 and a buffer amplifier 44. The imaging region 41 is comprised of a plurality of columns each comprising photosensitive elements 11, 12, 13, 14, 15, 16, 17 and 18 and a vertical shift register 46 adjacent to each of said columns and the storage region 42 is comprised of vertical shift registers 47. Indicated by A1, A2, A3 A4, A5, A6, A7 and A8 are conductors for supplying a clock signal to the vertical shift registers 46. Fig. 4 (a) shows the solid state image sensor in which the transfer electrodes of the vertical shift register 46 are provided in units of 2n (n is a positive integer of not less than 3) and the 2n (n=4) transfer electrodes are respectively independent. For simplicity, the imaging region 41 is represented by a column 45 of 1H X 8V photosensitive elements but actually it is implemented by a column of 948 H x 486 V photosensitive elements. The actions in the method of driving the above solid state image sensor are now explained. As shown in Fig. 4 (a), signal charges are respectively read out from photosensitive elements 11 and 15 in the first place and these read signal charges are transferred by the vertical shift register 46 to the storage region 42. As this read-out and transfer operation is repeated 4 times, the signal charges of photosensitive elements 15, 11, 16, 12, 17, 13, 18, 14 are transferred to the storage region 42 where they are stored successively from the bottom. These stored signal charges are serially transferred to the horizontal shift register 43, outputted from the buffer amplifier 44 and subjected to digital signal processing to provide progressive-scan picture signals. Then, the method for driving the above solid state image sensor on an interlaced-scan is described with reference to Fig. 5 (a), Fig. 5 (b), Fig. 5 (c) and Fig. 5 (d). First, referring to A field, as shown in Fig. 5(a), signal charges are read out from photosensitive elements 11 and 12 and photosensitive elements 15 and 16 are respectively read out to the vertical shift register 46, mixed and transferred to the storage region 42. These signal charges are respectively stored in integrating stages 51 and 52 of the vertical shift register 47 constituting the storage region 52. Then, as shown in Fig. 5 (b), signal charges are read out from photosensitive elements 13 and 14 and photosensitive elements 17 and 18 and these signals are respectively mixed and transferred to the storage region 42. Though these signal charges are transferred to the integrating stages 51 and 52, the signal charges previously stored in these stages 51 and 52 have already been transferred to the integrating stages 53 and 54 of the vertical shift register 47 constituting the storage region 42. When all the signal charges have been stored in the storage region 42, these signal charges are serially line-transferred to the horizontal shift register 43, outputted from the buffer amplifier 44 and subjected to digital signal processing to form a A field picture signal. After all the signal charges in the vertical shift register 47 in the storage region 42 have been transferred through the horizontal shift register 43, a sweeping pulse is applied to sweep the unnecessary charges remaining in the vertical shift register 47. Then, in B field, as shown in Fig. 5 (c), signal charges are read out from photosensitive elements 12 and 13 and photosensitive elements 16 an 17, which represent a second combination, in the column 45 to the vertical shift register 46, mixed and transferred to the storage region 42. Then, as shown in Fig. 5 (d), photosensitive elements 14 and 15 and photosensitive elements 18 and 19 (not shown) are read to the vertical shift register 46, mixed and transferred to the storage region 42. Though these signal charges are thus transferred to the integrating stages 51 and 52, the signal charges previously stored in these integrating stages 51 and 52 have already been transferred to integrating stages 53 and 54. When all the signal charges have been thus stored in the storage region 42, these signals are serially line-transferred to the horizontal shift register 53, outputted from the buffer amplifier 44 and subjected to digital signal processing to make a picture signal. Compared with the conventional transfer electrodes in sets of four, the above construction and driving method afford an increased maximum signal quantity that can be handled by the vertical shift register 46 and a commensurate gain in dynamic range. As shown in Fig. 6, this solid state image sensor comprises an imaging region 61, a storage region 62, a horizontal shift register 63 and a buffer amplifier 64. The imaging region 61 is comprised of columns 65 of photosensitive elements and a vertical shift register 66 disposed adjacent each of the columns and the storage region 62 is comprised of an upper storage area 67 and a lower storage area 68. Indicated by A1, A2, A3 and A4 are conductors for supplying clock pulses to the transfer stages of the vertical shift register 66. Conductors for supplying clock pulses to the vertical shift register in the storage region 62 are indicated by B1, B2, B3 and B4. For simplicity, the imaging region 61 is represented by columns 65 of 6 H x 6 V photosensitive elements but actually it is implemented by columns 65 of 948 H x 486 V photosensitive elements and the corresponding vertical shift registers 66 in the imaging region comprise 948 H x 243 V elements. The storage region 62 consists of 948 H x 486 V elements and, for simplicity of explanation, is divided into an upper storage area 67 and a lower storage area 68. The actions and functions of the above solid state image sensor are now explained with reference to the timing charts shown in Fig. 7 (a), Fig. 7 (b), Fig. 7 (c) and Fig. 7 (d). Fig. 7 (a) represents the composite synchronizing pulse, Fig. 7 (b) represents the transfer pulse for the vertical shift register, Fig. 7 (c) represents the transfer pulse for the vertical shift register in the storage region and Fig. 7 (d) represents the transfer pulse for the horizontal shift register. First, signal charges for one picture frame are transferred for storage from the imaging region 61 to the storage region 62 during the vertical blanking interval 71 shown in Fig. 7 (a). Thus, as shown in Fig. 7 (b), the unnecessary charges stored in the vertical shift register 66 are swept by a sweeping pulse 72 and, then, the signal charges accumulated in the even-number photosensitive elements of the photosensitive element column 65 are read by a first read pulse 73 to the vertical shift register 66. The signal charges read out to the vertical shift register 66 are transferred by a first transfer pulse 74 to the upper storage area 67. Then, the signal charges accumulated in the odd-number photosensitive elements of the photosensitive element column 65 are read out by a second read pulse 75 to the vertical shift register 66. The signal charges read out to the vertical shift register 66 are transferred by a second transfer pulse 76 to the upper storage area 67 and, at the same time, the signal charges accumulated in the upper storage area are transferred to the lower storage area 68. The waveforms, shown in Fig. 7 (c), represent the clock signals applied to the storage region 62. Thus, the unnecessary charges in the vertical shift register of the storage region are first swept by the transfer pulse 72 and, thereafter, the signal charges are shifted by the first transfer pulse 74 and second transfer pulse 76 within the storage region 62. After signal charges in all the photosensitive elements 65 have been stored in the storage region 62, the signal charges in the storage region 62 are transferred one column after another to the horizontal shift register 63 by a line transfer pulse 77, shifted by a horizontal transfer pulse 78, shown in Fig. 7 (d), within the horizontal shift register 63 and outputted from the buffer amplifier 64. In the above construction and driving method, the number of stages of the storage region 62 is equal to the number of photosensitive elements per column and the number of stages of the vertical shift register 66 in the imaging region 61 is equal to 1/2 of the number of stages of the vertical shift register in the storage region 62. The signal charges accumulated in the column of photosensitive elements 65 are transferred to the storage region in two installments within the vertical blanking interval, even-number photosensitive elements first and odd-number photosensitive elements next. As signal charges in all the photosensitive elements are transferred to the storage region 62, a progressive-scan becomes feasible and, moreover, the signal quantity that can be handled is increased to expand the dynamic range. While the number of transfer stages in the storage region is twice the number of stages in the vertical shift register of the imaging region in the above description, the same effect can be achieved when the former is 3 times as great as the latter. As shown in Fig. 8, this solid state image sensor comprises an imaging region 81, a storage region 82, a horizontal shift register 83 and a buffer amplifier 84. The imaging region 81 comprises columns of photosensitive elements 85 and a vertical shift register 86 disposed adjacent each of said columns and the storage region 82 comprises the corresponding vertical shift registers 87. The symbols A1, A2, A3 and A4 represent conductors for supplying clock pulses to the vertical shift registers 86 and B1, B2, B3, B4, B5, B6, B7 and B8 represent conductors for supplying clock pulses to the vertical shift register of the storage region 82. Fig. 8 shows an image sensor construction in which transfer electrodes in the vertical shift register 87 of the storage region 82 are provided in units of 8 + 4n (n is a positive integer inclusive of 0) transfer electrodes and these 8 + 4n transfer electrodes (n = 0) are respectively independent. For simplicity, the imaging region 51 is represented by 1 H x 8 V photosensitive elements 85 but actually it is implemented by 948 H x 486 V photosensitive elements. To perform a progressive-scan using the above solid state image sensor, signal charges are read out from all the photosensitive elements and stored in the storage region 82 in the first place and these signal charges are then line-transferred from the storage region 82 to the horizontal shift register 83 and shifted within the horizontal shift register 83. The picture signal output is available from the buffer amplifier 84. In this connection, the increased number of transfer electrodes in the vertical shift register 87 of the storage region 82 provides for a greater maximum signal quantity that can be handled and, hence, a broader dynamic range. The operation to achieve an interlaced-scan with the above solid state image sensor is now described. First, signal charges are read out from groups of vertically adjacent two photosensitive elements to the vertical shift register 86 and transferred to the storage region 82 comprising groups of 8 transfer electrodes. The signal charges stored in the storage region 82 are serially line-transferred to the horizontal shift register 83 and, as a result, a picture signal constituting A field is outputted via the buffer amplifier 84. Then, signal charges are read out from the other groups of photosensitive elements to the vertical shift register 86 and transferred to the storage region 82. These signal charges are serially line-transferred to the horizontal shift register 83 and a picture signal constituting B field is outputted via the buffer amplifier 84. An interlaced-scan can also be achieved by applying the same driving signal to groups of conductors B1 and B2, B3 and B4, B5 and B6, and B7 and B8 for supplying clock pulses to the transfer electrodes in the storage region 82. The transfer of signal charges within the storage region 82 is now described. Fig. 9 (a) shows the clock signals applied to the transfer electrodes of the storage region and Fig. 9 (b) is a potential profile of the storage region 82. As shown in Fig. 9 (a), clock pulses ø1, ø2, ø3, ø4, ø5, ø6, ø7, and, ø8, respectively, are applied to 8 transfer electrodes of the vertical shift register 87 of the storage region 82 to transfer the signal charges to the storage region 82. In this connection, the potential well 91 moves from A through D in Fig. 9 (b) to shift the signal charge 92. First, as shown in Fig. 9 (b), the signal charge 92 is accommodated in the potential well 91 formed by the clock pulses applied to a group of 8 transfer electrodes. This potential well 91 then moves to B to C to D according to the clock pulses to thereby transfer the signal charge 92. The above construction and driving method not only insure an improved dynamic range in progressive-scan but provide for an interlaced-scan signal output by mere change of the driving pulse applied to the transfer electrodes of the storage region 82 without provision of an external complicated digital signal processor. While the transfer electrodes of the storage region 82 are provided in groups of 8 in the above description, the same effect can be achieved by using transfer electrodes in groups of 8 + 4n (n is a positive integer inclusive of 0), such as groups of 12 or 16. It is now described a driving method for achieving an electronic shutter function with a solid state image sensor comprising an imaging region comprising photosensitive elements and vertical shift register, a storage region for accumulating signal charges from the imaging region, a horizontal shift register for horizontal transfer of signal charges from said storage region, and a buffer amplifier. Fig. 10 (a), Fig. 10 (b), Fig. 10 (c), Fig. 10 (d), Fig. 10 (e) and Fig. 10 (f) are the timing charts of a first driving method for achieving an electronic shutter function with the solid state image sensor. Fig. 10 (a) represents the composite synchronizing pulse, Fig. 10 (b) represents the photosensitive element reset pulse for an electronic shutter function, Fig. 10 (c) represents the vertical transfer pulse applied to the vertical shift register for reading signal charges for transfer from the even-number photosensitive elements, Fig. 10 (d) represents the vertical transfer pulse applied to the vertical shift register of the imaging region and Fig. 10 (e) and Fig. 10 (f) represent the vertical transfer pulse applied to the vertical shift register of the storage region. The first driving method for an electronic shutter function is now described with reference to the solid state image sensor shown in Fig. 6. First, as shown in Fig. 10 (b), a reset pulse 102 for initiating the electronic shutter function is applied during the vertical blanking interval 101 to reset the charges accumulated in the photosensitive elements 65. By this reset pulse 102, charges accumulated in all the photosensitive elements 65, irrespective of even-number or odd-number elements, are released. The reset pulse serves as an integration start signal for electronic shutter function and at this moment the photosensitive elements 65 (both even-number and odd-number elements) start accumulating electric charges anew. Then, as shown in Fig. 10 (c), a sweeping pulse 103 sweeps the unnecessary charges remaining in the vertical shift register 66 and with a lag time 108 after the reset pulse 102, signal charges are read out from the odd-number photosensitive elements 65 to the vertical shift register 66 by a first read pulse 106. The read signal charges are transferred to the storage region 62 by an odd-number transfer pulse 104. Then, as shown in Fig. 10 (d), a sweeping pulse 103 sweeps the unnecessary charges remaining in the vertical shift register 66. Then, with a lag time 109 from the reset pulse 102, a second road pulse 107 is applied so as to read signal charges from the even-number photosensitive elements 65 to the vertical shift register 66. The read signal charges are transferred to the storage region 62 by an even-number transfer pulse 105. The signal charges thus transferred to the storage region 62 are shifted within the storage region 62 by a series of pulses as shown in Fig. 10 (e) and Fig. 10 (f). However, in the first driving method described above, because of a large difference between the lag time 108 and lag time 109, there may occur a difference in luminance between A field and B field. The second driving method for electronic shutter function which overcomes the above problem is now described with reference to the solid state image sensor construction shown in Fig. 6. Fig. 11 (a), Fig. 11 (b), Fig. 11 (c), Fig. 11 (d) and Fig. 11 (e) are the timing charts of the second driving method for electronic shutter function with the solid state image sensor. First, within the vertical blanking interval (a), a first reset pulse 112 is applied to the photosensitive elements 65 as shown in Fig. 11 (b) to reset the charges previously accumulated in the photosensitive elements 65, which then starts accumulating charges anew. Then a sweep pulse 118 sweeps the unnecessary charges from the vertical shift register 66. Then, with a lag time 114 from the first reset pulse 112, a first read pulse 113 is applied so as to read signal charges from the odd-number photosensitive elements 65. The read signal charges are transferred to the storage region 62 by a transfer pulse 119 and, as a consequence, the picture signal for A field is outputted. Then, as shown in Fig. 11 (c), a second reset pulse 115 resets the charges accumulated in the photosensitive elements 65, whereupon the photosensitive elements 65 start accumulating charges anew. Then, a sweep pulse 118 sweeps the unnecessary charges in the vertical shift register 66. Then, with a lag time 117 from the second reset pulse, a second read pulse is applied so as to read signal charges from the even-number photosensitive elements 65. The read signal charges are transferred to the storage region 62 by a transfer pulse 120 and, as a result, a picture signal for B field is outputted. As independent reset pulses are provided for A-field and B-filed, respectively, in this manner, the integrating time for photosensitive elements 65 for A field and that for B field can be freely set so that the luminance of each field can be adjusted independently of the other. Furthermore, by equalizing the lag time 114 and lag time 117, any disparity in luminance between adjacent scan lines can be eliminated so that a subject of homogeneous luminance can be displayed without a disparity in luminance between adjacent scan lines and, hence, a picture of high quality can be obtained. The same effect can be obtained by applying high-voltage pulses between the image sensor semiconductor substrate and the photosensitive elements 65 as said first reset pulse and second reset pulse. Furthermore, the second driving method described above for electronic shutter function is not only applicable to the solid state image sensor shown in Fig. 6 but can be equally applied to the prior art solid state image sensor shown in Fig. 1 or any solid state image sensor of the FIT structure, invariably with the same result.

Claims: A solid state image sensor comprising a plurality of photosensitive elements arranged in a matrix form, a vertical shift register (66) disposed adjacent each column (65) of said photosensitive elements and adapted to vertically transfer signal charges read from the corresponding photosensitive elements, a storage region (62) for storing signal charges transferred by said vertical shift register (66), said storage region (62) having a capacity to store signal charges from all the photosensitive elements independently, and a horizontal shift register (63) adapted to horizontally transfer signal charges read from said storage region (62), characterised in that the number of transfer stages of said vertical shift register (66) is equal to 1/n of the vertical number of said photosensitive elements, wherein n is an integer greater than 2. The solid state image sensor according to claim 1, characterised in that said storage region (62) comprises a number of transfer stages, said number being 3 times as great as the number of transfer stages in the vertical shift register (66). The solid state image sensor according to claim 1 or 2, characterised in that said transfer stages of the vertical shift register (66) receive clock pulses from four conductors (A1, A2, A3, A4). The solid state image sensor according to one of claims 1 to 3, characterised in that said storage region (62) receives clock pulses from four conductors (B1, B2, B3, B4). The solid state image sensor according to one of claims 1 to 4, characterised in that said storage region (62) comprises an upper storage area (67) and a lower storage area (68). The solid state image sensor according to claim 5, characterised in that the signal charges of the vertical shift register (66) are transferred by a first transfer pulse (74) to the upper storage area (67). The solid state image sensor according to claim 6, characterised in that the signal charges accumulated in the upper storage area are transferred by a second transfer pulse (76) to the lower storage area (68) and, at the same time, the signal charges of the vertical shift register (66) are transferred to the upper storage area (67).

Inventors: ITAKURA KEIJIROU, KOKUSENYA NOHORU, NAGAYOSHI KYOUICHI, NOBUSADA TOSHIHIDE, OZAKI MASAYOSHI, SAITOH YUKIO, TANAKA HIRONORI, TOYODA YASUYUKI, ITAKURA, KEIJIROU, KOKUSENYA, NOHORU, NAGAYOSHI, KYOUICHI, NOBUSADA, TOSHIHIDE, OZAKI, MASAYOSHI, SAITOH, YUKIO, TANAKA, HIRONORI, TOYODA, YASUYUKI
Applicants: MATSUSHITA ELECTRONICS CORP, MATSUSHITA ELECTRONICS CORPORATION
Application year: 1993
Main classification: H04N3
IPC codes: H04N3