DC TRACKING CIRCUIT FOR GINOMY DATA SLICER

Abstract: In a transceiver (1) forming part of a digital communications system, there is described a system for data recovery from the demodulated analogue signal, said system comprising a slicer circuit (6) for extracting the digital data from the analogue signal and a low pass filter (9) for generating, from the input analogue signal (5), a threshold signal for use in the operation of said slicer circuit (6). The low pass filter (9) has a variable time constant, selected by a switch (5), to alter the rate of change of the threshold level in accordance with the position of the switch. The switch is itself controlled by a composite control signal (16) output from a gate (10) and indicative of two properties of the received R.F. signal, namely the received signal strength (RSSI) and the state of synchronisation. The arrangement is such that a high rate of change of threshold level is permitted only if the transceiver is not synchronised a &cir& _n &cir& _d &cir& _ the received signal strength is above a predetermined level.

Description: DC tracking circuit for Ginomy data slicer This invention relates to a system for data recovery and in particular to a system for extracting binary data from an analogue signal containing such data . Such systems are utilised, for example, in digital communications systems in which digital data is transmitted, which data is a mixture of digitised analogue information and control data, such as synchronising data. At the receiver, such data has to be recovered from the demodulated signal which is, of course, an analogue signal. An example of a transceiver which could utilise such a system is described in our European patent application 0333419 which is incorporated herein by this reference. In the receiver chain of this transceiver, the demodulated signal which is output from the frequency discriminator is filtered, and then passed to a data recovery circuit in the form of a data slicer before being applied as digital data to a data processor. The present invention is essentially concerned with data recovery circuits of this and similar type, although we do not wish to be limited to the particular arrangement shown in EP 0333419, which is presented simply by way of example, for the purpose of explanation. The fundamental purpose of a data recovery circuit is to decide what the smoothly varying analogue input signal represents m binary terms. The simplest technique is to base the decision .? ■ = ■ to whether, at any particular instant of time, a binary 0 or 1 is present on whether the input signal is above or below a predetermined threshold level. The circuit element which carries out such a task is the comparator but because in this application the signal is constantly crossing and recrossing the threshold level as the 1 's and O ' s of the data are received, the comparator is often referred to as a slicer. The slicer is thus the basic component of the data recovery circuit, and its output is a binary signal representing either 0 or 1. More complex systems are known, but the simple slicer system is quite effective. The problem with the slicer system is choice of the optimum slicer threshold level. The threshold level must be able to vary in order to quickly adjust to a freshly acquired signal; on the other hand, the threshold level must not be forgotten too quickly in the event that the input signal fades, or becomes unreliable. There are various ways of providing for a variable threshold level: 1 ) The slicer input or output signals may be filtered and thence used to generate a variable threshold level based on a reasonable estimate of the centre of the input signal. This works well provided that the data comprises a reasonably balanced mixture of O ' s and 1 's . 2) The positive and negative peaks of the slicer input signal are measured and a mean value taken for the threshold level. This is more complex than method ( 1 ) . 3) The data is analysed, and a decision on threshold level made on the basis of the detailed values of the previous few bits of data. This is even more complex. The philosophy adopted for the present invention is that a workable threshold value should be quickly acquired when the input signal first appears, but that the rate of change of threshold value should be slowed down when the extracted data is positively indicated as already being good or is expected to be of inadequate quality to permit changes. To this end, the invention provides means for measuring the signal strength and for altering the rate of change of the threshold level in accordance with this measurement. In particular, rapid changes in the threshold level will only take place if the signal strength is not below a predetermined critical value. In a preferred embodiment of the invention means are additionally provided for detecting whether the system is in synchronism, for example frame lock acquisition, and for altering the rate of change of the threshold in accordance with this decision. In particular, if the system is not synchronised, then rapid changes of threshold level will be allowed. The advantage of the prevention of rapid tracking, provided synchronism is achieved, is that any short duration interference does not alter the threshold level. Thus, when the measured signal strength is high then the incoming signal should be good and worth rapidly tracking; however, if synchronism has been achieved, there is no longer any need for rapid tracking of the threshold level as the data is now about good enough and any further refinement of the optimum threshold level can be allowed relatively slowly. In order that the invention may be better understood, an embodiment thereof will now be described by way of example only and with reference to the accompanying drawing which is a block diagram of the system of the invention. Referring to the drawing, a represen¬ tative transceiver is shown under reference 1. This transceiver may, for example, be of the type described in our European patent application 0333419. The transceiver includes means (not shown) for measuring the received signal strength of the incoming signal, and providing a logic signal at a "Low RSSI" terminal 2 which is high when the RSSI (received signal strength indicator) signal lies below some predetermined threshold, but is otherwise low. The transceiver further includes means (also not shown) for identifying, by bit pattern match, when the synchronising words have been received correctly, and providing a logic signal at a "Frame Sync" terminal 3 which is high when a bit pattern match has shown that the sync words have been received correctly. This is all known technology, and will not be described further. The demodulated data from the receiver portion of the transceiver is output at a "Demod data" terminal 4 and comprises an analogue waveform such as shown under reference 5. This signal is applied to one input of a slicer circuit 6 in the form of a comparator. The output from the slicer 6 takes the form of a digital waveform such as shown under reference 7. Applied to the other input 8 of slicer 6 is a threshold level which is adjusted by means of a low pass filter feedback network 9 to follow the variations in the input waveform 5. The slicer operates to compare the incoming analogue signal with the threshold level to thereby produce the digital waveform 7 in the known manner. In a simple system, the threshold level is adjusted to sit between the upper and lower levels of the input waveform and follows the variation of optimum slicing level quickly so that good data is not lost, but when the incoming data is bad the threshold level varies slowly as the signal knowledge is inadequate to optimally select the threshold level. By contrast, the illustrated circuit utilises the "low RSSI" and "Frame Sync" signals described above to control the time constant of the feedback network 9 so that only when the RSSI shows an adequate level of signal and the system has not detected adequate synchronism are fast threshold level changes permitted. To this end, the terminals 2 and 3 are connected to respective inputs of a NOR gate 10. The output of the NOR gate is applied as a control input 11 to the feedback network 9. The feedback network 9 includes a low-pass filter comprising a timing capacitor C, a high value resistor R1 and a low value resistor R2. A switch S selectively places the resistor R2 in parallel with resistor R1 to thus lower the time constant of the filter. Switch S is an electronic switch under the control of the signal at input 11. The input 12 of the low pass filter is taken from the input waveform at terminal 4 of the transceiver 1. The output 13 of the low pass filter is passed to the threshold level input 8 of the slicer 6- Under normal circumstances, the switch S is open, as shown, giving a relatively high time constant and thus a relatively low rate of change of threshold level as the input waveform 5 changes. However, if the "low RSSI" signal (reference 14) becomes low (indicating that the received signal strength is not below a critical value) and at the same time the frame sync signal (reference 15) is low (indicating that frame sync has not been achieved) , then the output from NOR gate 10 goes high (reference 16) and this causes the switch S to close, thus lowering the time constant of the filter. This in turn gives a relatively higher rate of change of threshold level as the input waveform 5 changes. In the above-described arrangement, only when there is both an adequate level of received signal strength and the system has not detected adequate synchronism are fast threshold level changes permitted. Otherwise threshold level variations are only permitted slowly. In an alternative embodiment (not shown) the switch S has a third position in which input 12 is, in effect, isolated. This causes the output 13 to remain at substantially the voltage previously held on capacitor C, so the threshold level remains substantially constant. This switch position may be used, for example, during the transmit portion of alternate transmission/reception cycles such as are used in certain communications systems. In such systems transmission and reception alternate on a cyclic basis; during transmission, if the switch S is switched to the third position, it will hold the threshold level from the previous reception window, and this level will be used to commence slicing in the next reception window. In practice, the switch S will be switched to the third position and back to the first/second position on a cyclic basis to match the alternations of reception and transmission.

Claims: CLAIMS 1. A data recovery system for extracting binary data from an analogue signal derived by demodulation of a received R.F. signal, said system comprising a slicer circuit having an input to which said analogue signal is applied, said slicer circuit being operable to extract binary data from said analogue signal, which binary data is applied to an output of said slicer circuit, and means for establishing a threshold level for said slicer circuit, said system being characterised by means for measuring the signal strength of the received R.F. signal to produce a control signal indicative of such signal strength, and in that said means for establishing a threshold level includes means for altering the rate of change of said threshold level in accordance with the value of said control signal. 2. A system as claimed in claim 1 wherein said means for altering the rate of change of threshold level is operable to permit rapid changes in the threshold level only if the signal strength is above a predetermined critical value. 3. A system as claimed in either one of claims 1 or 2 further comprising means for detecting whether the synchronising data has been correctly received, and producing a further control signal indicative of whether such synchronising data has been correctly received, and wherein said means for altering the rate of change of threshold level is additionally operable to alter the rate of change in accordance with the value of said further control signal. 4. A system as claimed in claim 3 wherein said means for altering the rate of change of threshold level is operable to permit rapid changes in the threshold level only if the synchronising data has not been correctly received. 5. A system as claimed in either one of claims 3 or 4 including means for combining said control signal and said further control signal to produce a composite control signal for application to said means for establishing a threshold level. 6. A system as claimed in claim 5 wherein said combining means comprises a logic gate having two inputs to which said control signal and said further control signal are respectively applied, and an output on which said composite control signal appears. 7. A system as claimed in any one of the preceding claims wherein said slicer takes the form of a comparator having two inputs, one for said analogue signal as aforesaid, and one to which said threshold signal is applied, and wherein said comparator is operable to compare the analogue signal with the threshold signal to produce a digital output signal. 8. A system as claimed in any one of the preceding claims wherein said means for establishing a threshold level comprises a low pass filter having a variable time constant selected by a switch, said switch being controlled by said control signal, or by said composite control signal, as appropriate. 9. A system as claimed in claim 8 wherein the input to said low pass filter is connected to receive said analogue signal. 10. A digital communications transceiver incorporating a system as claimed in any one of the preceding claims.

Inventors: MCCABE DAVID JAMES, WILLIAMS STEPHEN AKIRA, MCCABE, DAVID, JAMES, WILLIAMS, STEPHEN, AKIRA
Applicants: MCCABE DAVID JAMES, SHAYE COMMUNICATIONS LTD, WILLIAMS STEPHEN AKIRA, SHAYE COMMUNICATIONS LIMITED
Application year: 1993
Main classification: H04L25
IPC codes: H04L25