Semi-flash A/D converter and A/D converting method

Abstract: A semi-flash type analog/digital converter includes a D/A converter (101) for outputting a plurality of analog signals having voltages corresponding to output data of this A/D converter, a plurality of comparators (103-109) for each comparing the voltage of an unconverted analog signal with the analog signal from the D/A converter, latches (111,112) for holding the outputs of the comparators, and encoders (113,114) for receiving and encoding the output signals of the latches. One of the encoders is a correction encoder (114) for correcting any of the output signals (240-246) of the comparators when that output signal is in error, and encoding the corrected signal.

Description: The present invention relates to a semi-flash type A/D (Analog to Digital) converter and semi-flash type A/D converting method, and, more particularly, a semi-flash type A/D converter and semi-flash type A/D converting method which is insusceptible to noise. A semi-flash type A/D converter has a plurality of comparators, and successively performs comparison by a plurality of bits using the comparators to convert an analog signal into a digital signal. As this A/D converter successively performs comparison by a plurality of bits, it can convert an analog signal into a digital signal faster than an ordinary successive comparison type A/D converter. An example of the structure of a conventional semi-flash type A/D converter will be described referring to Fig. 1. Fig. 1 shows the structure of a semi-flash type 6-bit A/D converter which performs two consecutive comparing operations by three bits. The A/D converter shown in Fig. 1 comprises a D/A converter 101, a selector 102, seven comparators 103 to 109, a sample and hold circuit 110, latches 111 and 112, encoders 113 and 501, and registers 115 and 116 for storage of the conversion results. Signals S0, S1, S2, CLK and EOC are timing signals for controlling the converting operation, and are generated inside this semi-flash type A/D converter. The D/A converter 101 comprises a plurality of resistors as shown in, for example, Fig. 2. The D/A converter 101 receives signals 200 to 207 from the encoder 113 and outputs signals 210 to 216 and signals 220 to 226. The signals 210 to 216 and signals 220 to 226 have potentials obtained by dividing a difference between a conversion reference potential VREF and a conversion reference ground potential AVSS by resistors. The potentials of the signals 210-216 have the following relationship. signal 210 > signal 211 > signal 212 > signal 213 > signal 214 > signal 215 > signal 216 The signals 220-226 are obtained through switches A to H, respectively. The switches A to H are selected in association with the output signals 200-207 from the encoder 113. The potentials of the signals 220-226 have the following relationship. signal 220 > signal 221 > signal 222 > signal 223 > signal 224 > signal 225 > signal 226 Table 1 shows the relation between the potentials of the output signals 200-207 of the encoder 113 and those of the signals 220-226, obtained by the actions of the switches A-H. The selector 102 (Fig. 1) selects the signals 210-216 supplied from the D/A converter 101 while the timing signal S2 is at an L (low) level. While the timing signal S2 is at an H (high) level, the selector 102 selects the signals 220-226 from the D/A converter 101 and supplies the selected signals to inverting input terminals of the comparators 103-109. An analog signal, which is to be converted into a digital signal, is supplied to an analog input terminal AIN. The sample and hold circuit 110 samples the potential of the analog signal supplied to the analog input terminal AIN during the H-level duration of the timing signal S0, and holds the sampled potential and supplies that potential to the non-inverting input terminals of the comparators 103-109 during the L-level duration of the timing signal S0. The comparators 103-109 each compare the potentials of the two input signals with each other. Each of the comparators 103-109 outputs an L-level signal when the potential of the signal supplied to the inverting input terminal is higher than that of the signal supplied to the non-inverting input terminal and outputs an H-level signal when the potential of the signal supplied to the inverting input terminal is lower than that of the signal supplied to the non-inverting input terminal. The latch 111 latches the output signals of the comparators 103-109 while the timing signals S1 and CLK are both at an H level, and holds the latched signals during the other period. The latch 112 latches the output signals of the comparators 103-109 while the timing signals S2 and CLK are both at an H level, and holds the latched signals during the other period. The encoder 113, which is a logic circuit having a structure as shown in, for example, Fig. 3, produces signals 250 to 252 as well as the signals 200 to 207 from output signals 230 to 236 of the latch 111. The encoder 501, which is a logic circuit having a structure as shown in Fig. 4, produces signals 253 to 255 from output signals 240 to 246 of the latch 112. The registers 115 and 116 respectively receive the signals 250-252 and the signals 253-255 during the H-level duration of the control signal EOC, and holds the received signals during the other period. The function of the flash type A/D converter with the above-described structure will be described with reference to Figs. 5A through 5K. The converting operation of the A/D converter in Fig. 1 is executed in three stages of period 1, period 2 and period 3 shown in Fig. 5A. The operation for each period will be described below. Operation (S0=H, S1=L and S2=L) in Period 1 The period 1 is a sampling period where an analog input signal is sampled. During this period, the timing signal S0 keeps an H level and the timing signals CLK, S1, S2 and EOC keeps an L level as shown in Figs. 5A-5E. As the timing signal S2 has an L level, the selector 102 selects the signals 210-216 from among the output signals of the D/A converter 101 and supplies the selected signals to the comparators 103-109. As the timing signal S0 has an H level, the sample and hold circuit 110 samples the voltage of the analog signal supplied to the analog input terminal AIN. During this period, the output signals of the comparators 103-109, the signals 230-236, the signals 240-246, the signals 250-256 and the outputs of the registers 115 and 116 respectively keep the same potentials as those of the signals in the previous conversion cycle. Operation (S0=L, S1=H and S2=L) in Period 2 During the period 2, upper three bits of the 6-bit data corresponding to the analog input signal are obtained. The timing signal S0 becomes an L level as shown in 5B, so that the sample and hold circuit 110 supplies the potential of the analog input signal sampled in the period 1 to the non-inverting input terminals of the comparators 103-109. As the timing signal S2 keeps the L level as shown in Fig. 5D, the selector 102 selects the signals 210-216 as in the period 1. The comparators 103-109 respectively compare the potentials of the signals supplied from the selector 102 with the potentials of the signal supplied from the sample and hold circuit 110, and outputs the comparison results as shown in Fig. 5F. When the outputs of the comparators 103-109 become stable, the timing signal CLK becomes an H level as shown in Fig. 5A. As the timing signal S1 is at an H level as shown in Fig. 5C, the latch 111 latches the output signals of the comparators 103-109 and outputs the signals 230-236 as shown in Fig. 5G. Upon reception of the signals 230-236, the encoder 113 encodes those signals and outputs the signals 200-207 and the signals 250-252 (see Fig. 5H). The signals 250-252 are upper three bits of the conversion result, the signal 250 indicating the most significant bit (MSB). As mentioned earlier, the potentials of the signals 210-216 have the relationship of signal 210 > signal 211 > signal 212 > signal 213 > signal 214 > signal 215 > signal 216. In the period 2, therefore, the outputs of the comparators 103-109, the signals 200-207, and the signals 250-252 have signal levels as given in Table 2. Operation (S0=H, S1=L and S2=H) in Period 3 During the period 3, lower three bits of the 6-bit data corresponding to the analog input signal are obtained. In the period 3, the timing signal S2 becomes an H level as shown in Fig. 5D, and the selector 102 selects the signals 220-226. At this time, the signals have the signal levels as given in Table 1. The comparators 103-109 respectively compare signal levels of the signals 220-226 with the signal level of the output of the sample and hold circuit 110, and outputs the comparison results as shown in Fig. 5F. When the outputs of the comparators 103-109 become stable, the timing signal CLK becomes an H level as shown in Fig. 5A. As the timing signal S2 is at an H level, the latch 111 latches the comparison results and outputs the signals 240-246 as shown in Fig. 5I. The encoder 501 encodes the signals 240-246, and produces the signals 253-255 as shown in Fig. 5J. The signals 253-255 are lower three bits of the conversion result, the signal 255 indicating the least significant bit (LSB). When the operation up to this point is complete, the timing signal EOC becomes an H level as shown in Fig. 5E, and at this timing, the register 115 latches the upper three bits of the conversion result while the register 116 latches the lower three bits of the conversion result as shown in Fig. 5K. Through the above operation, one converting operation is completed. As mentioned earlier, the potentials of the signals 220-226 have the relationship of signal 220 > signal 221 > signal 222 > signal 223 > signal 224 > signal 225 > signal 226. Table 3 shows possible combinations of the outputs of the comparators 103-109, and the relationship between the signals 253-255 association with the combinations. The shortcoming of the A/D converter shown in Fig. 1 will now be discussed. When the difference between the potentials of the two input signals to each of the comparators 103-109 is sufficient large with respect to noise in the A/D converter, the comparators 103-109 can stably perform comparison without being affected by the noise. When the level of the internal noise of the A/D converter is equal to or greater than the difference between the potentials of the two input signals to each of the comparators 103-109, the comparators 103-109 may output erroneous comparison results due to the noise. Table 4 shows three examples of the relationship between the output signals of the comparators 103-109 and the output signals 253-255 of the encoder 501 when the comparators 103-109 output erroneous signals due to noise. It is apparent from Table 4 that when the output signals of the comparators 103-109 are in error due to noise, the conversion results (253-255) have the wrong values. To overcome this shortcoming, it is necessary to reduce noise in the A/D converter. With the use of a converter with high resolution precision, it is difficult to sufficiently reduce noise with respect to the resolution level. Because of the above problem, a semi-flash type A/D converter, which can theoretically perform high-speed conversion at high precision, is actually susceptible to noise and has a difficulty in accomplishing high-precision conversion. "Electrical Design News, vol. 36, No. 8, April 11, 1991" discloses subranging AID converters which offer performance levels difficult to obtain with successive-approximation or flash converters. Architecture and operation of these devices are explored. "US-A-5,029,305" discloses a method and an apparatus for error correction in thermometer code arrays. The correction of errors in the data array produced by comparators is accomplished by an array of majority error correction gates which is placed between the array of comparators and the encoder in the A/D converter. It is an object of the present invention to provide a semi-flash type A/D converter capable of accurately converting an analog signal into a digital signal. It is another object of this invention to provide a semi-flash type A/D converter which is susceptible to noise. The present invention is defined in claims 1 and 7. Dependent claims 2 to 6 and 8 to 10 define particular embodiments of the invention. According to one embodiment of this invention, there is provided a semi-flash type analog/digital converter comprising digital/analog conversion means for outputting a predetermined first group of analog signals for producing predetermined upper bits of an analog/digital conversion result, and a second group of analog signals which are to produce predetermined lower bits of the analog/digital conversion result and are associated to the predetermined upper bits; a selector for selecting one of the first group of analog signals and the second group of analog signals, and supplying the selected group of analog signals; a plurality of comparators for each comparing a voltage of an associated one of the output signals of the selector with a voltage of an analog signal to be converted into digital data; first encoding means for encoding output signals of the plurality of comparators which are associated with the first group of analog signals to acquire the predetermined upper bits of the analog/digital conversion result, and supplying signals corresponding to the predetermined upper bits to the digital/analog conversion means; and second encoding means for encoding output signals of the plurality of comparators which are associated with the second group of analog signals to acquire the predetermined lower bits of the analog/digital conversion result, the second encoder having means for correcting any of the output signals of the plurality of comparators when that output signal is in error, and encoding the corrected signal. According to a further embodiment of this invention, there is provided a semi-flash type A/D converting method comprising a step of sampling an analog signal to be converted into a digital signal; a step of producing a first group of analog signals having predetermined mutually different voltages; a first comparison step of comparing each of the first group of analog signals with the analog signal sampled in the sampling step and outputting signals corresponding comparison results; a first encoding step of encoding signals output in the first comparison step; a step of producing a second group of analog signals having mutually different voltages in association with digital data acquired in the first encoding step; a second comparison step of comparing each of the second group of analog signals with the analog signal sampled in the sampling step and outputting signals corresponding comparison results; a second encoding step of encoding signals output in the second comparison step, the second encoding step including a step of correcting any of the output signals of the second comparison step when that output signal is in error, and encoding the corrected signal; and a step of linking digital signals acquired in the second encoding step to acquire a conversion result. With the above structures, when the output signal of the converter or converting step have an abnormal value (the value that cannot actually occur), the encoding means or the second encoding step corrects this output signal to have a value that is estimated as correct, and encodes the corrected signal. Even when the output signal of the converter or the converting step is in error due to noise, therefore, this converter and the converting method can convert the analog input signal into a digital signal more accurately than the prior art. Description of the preferred embodiments The invention will now be described in more detail and with reference to the accompanying drawings, which show: Fig. 1 is a block diagram exemplifying the structure of a conventional semi-flash type A/D converter; Fig. 2 is a circuit diagram showing an example of the structure of a D/A converter shown in Fig. 1; Fig. 3 is a block-diagram showing an example of the structure of an encoder 113 shown in Fig. 1; Fig. 4 is a block diagram showing an example of the structure of an encoder 501 shown in Fig. 1; Figs. 5A through 5K are timing charts for explaining the function of the conventional semi-flash type A/D converter and a semi-flash type A/D converter according to one embodiment of this invention; Fig. 6 is a block diagram illustrating the structure of a semi-flash type A/D converter according to one embodiment of this invention; Fig. 7 is a block diagram showing an example of the structure of an encoder 114 shown in Fig. 6; and Fig. 8 is a block diagram showing another example of the structure of the encoder 114 shown in Fig. 6. A preferred embodiment of the present invention will now be described referring to the accompanying drawings. Fig. 6 illustrates the structure of a semi-flash type 6-bit A/D converter according to one embodiment of the present invention. This A/D converter performs two consecutive comparing operations by three bits to convert an analog input signal into 6-bit digital data. Fig. 6 uses the same reference numerals or symbols as used in Fig. 1 to denote corresponding or identical portions. As shown in Fig. 6, the A/D converter of this embodiment comprises a D/A converter 101, a selector 102, seven comparators 103 to 109, a sample and hold circuit 110, latches 111 and 112, an encoder 113, a correction encoder 114, and registers 115 and 116 for storage of the conversion results. Signals S0, S1, S2, CLK and EOC are timing signals for controlling the converting operation, and are generated inside this semi-flash type A/D converter. The D/A converter 101 have a structure as shown in, for example, Fig. 2, and outputs signals 210 to 216 and signals 220 to 226. The selector 102 selects the signals 210-216 during the L-level duration of the timing signal S2. During the H-level duration of the timing signal S2, the selector 102 selects the signals 220-226 and supplies the selected signals to inverting input terminals of the comparators 103-109. Supplied to an analog input terminal AIN is an analog signal, which is to be converted into a digital signal. The sample and hold circuit 110 samples the potential of the analog signal supplied to the analog input terminal AIN during the H-level duration of the timing signal S0, and holds the sampled potential and supplies the sampled potential to the non-inverting input terminals of the comparators 103-109 during the L-level duration of the timing signal S0. The comparators 103-109 each compare the potentials of the two input signals with each other. Each of the comparators 103-109 outputs an L-level signal when the potential of the signal supplied to the inverting input terminal is higher than that of the signal supplied to the non-inverting input terminal and outputs an H-level signal when the potential of the signal supplied to the inverting input terminal is lower than that of the signal supplied to the non-inverting input terminal. The latch 111 latches the output signals of the comparators 103-109 while the timing signals S1 and CLK are both at an H level, and outputs the latched signals as signals 230 to 236 during the other period. The latch 112 latches the output signals of the comparators 103-109 while the timing signals S2 and CLK are both at an H level, and outputs the latched signals as signals 240 to 246 during the other period. The encoder 113, which is a logic circuit having a structure as shown in, for example, Fig. 3, produces signals 250 to 252 as well as the signals 200 to 207 from output signals 230 to 236 of the latch 111. The correction encoder 114 is a conventional encoder additionally provided with a priority control function. When the comparators 103-109 output abnormal signals, the correction encoder 114 do not encode them directly, but correct them to proper signals before encoding them, and outputs the encoded results as signals 253 to 255. For instance, it seems that the correct value of the outputs of the comparators, "0001011," shown in Table 4 is "0001111" or "0000111." Accordingly, the correction encoder 114 corrects the input data "0001011" to "0001111" and then encodes the corrected data. The registers 115 and 116 respectively receive the signals 250-252 and the signals 253-255 during the H-level duration of the control signal EOC, and holds the received signals during the other period. The function of the flash type A/D converter with the above-described structure will be described below. The converting operation of the A/D converter in Fig. 6 is executed in three stages of period 1, period 2 and period 3 shown in Fig. 5A, as in the prior art. Period 1: As shown in Figs. 5A through 5E, the timing signal S0 keeps a high level while the timing signals CLK, S1, S2 and EOC keep a low level. Consequently, the sample and hold circuit 110 samples the analog input signal. Period 2: The timing signal S0 becomes an L level as shown in 5B, so that the sample and hold circuit 110 supplies the potential of the analog signal sampled in the period 1 to the non-inverting input terminals of the comparators 103-109. As the timing signal S2 has an L level as shown in Fig. 5D, the selector 102 selects the signals 210-216. The comparators 103-109 respectively compare the potentials of the signals 210-216 supplied from the selector 102 with the potential of the signal supplied from the sample and hold circuit 110, and outputs the comparison results as shown in Fig. 5F. When the outputs of the comparators 103-109 become stable, the timing signal CLK becomes an H level as shown in Fig. 5A. As a result, the latch 111 latches the output signals of the comparators 103-109 and outputs the latched signals as the signals 230-236 as shown in Fig. 5G. Upon reception of the signals 230-236, the encoder 113 encodes those signals and outputs the signals 200-207 and the signals 250-252 shown in Fig. 5H. Period 3: The timing signal S2 becomes an H level as shown in Fig. 5D, and the selector 102 selects the signals 220-226. The comparators 103-109 respectively compare the signals 220-226 with the potential of the output of the sample and hold circuit 110, and outputs the comparison results as shown in Fig. 5F. When the outputs of the comparators 103-109 become stable, the timing signal CLK becomes an H level as shown in Fig. 5A. As a result, the latch 111 latches the comparison results and outputs the signals 240-246 as shown in Fig. 5I. The encoder 114 encodes the signals 240-246, and produces the signals 253-255 as shown in Fig. 5J. The signals 253-255 are lower three bits of the conversion result, the signal 255 indicating the least significant bit (LSB). When the comparators 103-109 output data (error data) as given in Table 4 due to noise, the correction encoder 114 correct the data and encodes the corrected data. When the operation up to this point is complete, the timing signal EOC becomes an H level as shown in Fig. 5E, and at this timing, the register 115 latches the upper three bits of the conversion result while the register 116 latches the lower three bits of the conversion result as shown in Fig. 5K. Through the above operation, one converting operation is complete. According to this embodiment, when the comparators 103-109 output abnormal data due to noise or the like, the correction encoder 114 corrects the data and converts the corrected data into code data. Accordingly, the acquired digital data accurately corresponds to the analog input signal. In other words, the present invention provides a semi-flash type A/D converter which is insusceptible to noise. A description will now be given of an example of the structure of the correction encoder 114 referring to Fig.7. In Fig. 7, the signal 240 is supplied to AND gates 1143 to 1148 via an inverter. The signal 241 is supplied to the AND gate 1143 directly and to the AND gates 1144-1148 via an inverter. The signal 242 is supplied to the AND gate 1144 directly and to the AND gates 1145-1148 via an inverter. The signal 243 is supplied to the AND gate 1145 directly and to the AND gates 1146-1148 via an inverter. The signal 244 is supplied to the AND gate 1146 directly and to the AND gates 1147 and 1148 via an inverter. The signal 245 is supplied to the AND gate 1147 directly and to the AND gate 1148 via an inverter. The signal 246 is directly supplied to the AND gate 1148. An OR gate 1140 receives the signal 240 and the output signals of the AND gates 1143, 1144 and 1145, and outputs the signal 253. An OR gate 1141 receives the signal 240 and the output signals of the AND gates 1143, 1146 and 1147, and outputs the signal 254. An OR gate 1142 receives the signal 240 and the output signals of the AND gates 1144, 1146 and 1148, and outputs the signal 254. The correction encoder 114 shown in Fig. 7 has the input/output characteristics given in Table 5. In Table 5, a region A indicates the output of this encoder 114 when the correct outputs are obtained from the comparators 103-109, and a region B indicates the output of this encoder 114 when the wrong outputs are obtained from the comparators 103-109. It is apparent from Table 5 that even when the outputs of the comparators 103-109 are abnormal, the encoder having the structure shown in Fig. 7 can output correctly encoded signals. Even with large noise, therefore, this A/D converter can output correct digital data. Generally speaking, the encoder shown in Fig. 7 is a circuit which considers all of those bits whose digits are equal to or lower than that of the most significant bit having an H("1") level, as having H levels, when receiving abnormal data. Therefore, the output data "0001011" and "0001101" of the comparators 103-109 are treated as "0001111" and the output data "0101101" is treated as "0111111," as shown in Table 5. Another example of the structure of the correction encoder 114 will be described below referring to Fig. 8. In Fig. 8 the encoder 114 comprises four full adders 301a to 301d. The full adder 301a adds the signals 240, 241 and 242. The full adder 301b adds the signals 243, 244 and 245. The full adder 301c adds the carry outputs C of the full adders 301a, 301b and 301d. The full adder 301d adds the sum outputs S of the full adders 301a and 301b, and the signal 246. The carry output C of the full adder 301c becomes the signal 253, the sum output S of the full adder 301c becomes the signal 254, and the sum output S of the full adder 301d becomes the signal 255. The correction encoder 114 shown in Fig. 8 has the input/output characteristics given in Table 6. In Table 6, a region A indicates the output of this encoder 114 when the correct outputs are obtained from the comparators 103-109, and a region B indicates the output of this encoder 114 when the wrong outputs are obtained from the comparators 103-109. It is apparent from Table 6 that even when the outputs of the comparators 103-109 are abnormal, the encoder having the structure shown in Fig. 8 do not encode the abnormal data directly, but convert the data to code data corresponding to the data that is estimated as correct. Even with large noise, therefore, this A/D converter can output correct digital data. Generally speaking, the encoder shown in Fig. 8 is a circuit which considers the most significant bit of bit data having an H("1") level as having an L level and treats all the bits lower than that bit as having an H level. Therefore, the output data "1011111" of the comparators 103-109 is treated as "0111111," the output data "0101111" is treated as "0011111," the output data "0001011" is treated as "0000111" and the output data "0110111" is treated as "0011111." In the field of digital signal processing, generally, averaging (which performs A/D conversion plural times and obtains the average of the resultant converted values) is employed to eliminate a white-noise oriented variation in the converted value at the time of A/D conversion. The use of the correction encoder shown in Fig. 8 can eliminate such a white-noise oriented variation in the converted value, and can improve the conversion precision of the A/D converter itself. The present invention is not limited to the above-described embodiments. For instance, although digital data after A/D conversion has six bits in this embodiment, the digital data may have a different number of bits, e.g., 8 bits or 12 bits.

Claims: A semi-flash type analog/digital converter comprising: digital/analog conversion means (101) for outputting a predetermined first group of analog signals (210-216) for producing predetermined upper bits (250-252) of an analog/digital conversion result, and a second group of analog signals (220-226) which are to produce predetermined lower bits (253-255) of said analog/digital conversion result and are associated to said predetermined upper bits; a selector (102) for selecting one of said first group of analog signals (210-216) and said second group of analog signals (220-226), and supplying said selected group of analog signals; a plurality of comparators (103-109) for each comparing a voltage of an associated one of said output signals of said selector with a voltage of an analog signal to be converted into digital data; first encoding means (113) for encoding output signals (230-236) of said plurality of comparators (103-109) which are associated with said first group of analog signals to acquire said predetermined upper bits (250-252) of said analog/digital conversion result, and supplying signals (200-207) corresponding to said predetermined upper bits to said digital/analog conversion means (101); and second encoding means (114) for encoding output signals (240-246) of said plurality of comparators (103-109) which are associated with said second group of analog signals to acquire said predetermined lower bits (253-255) of said analog/digital conversion result, said second encoding means (114) having means for correcting any of said output signals (240-246) of said plurality of comparators when that output signal is in error, and encoding said corrected signal. The semi-flash type analog/digital converter according to claim 1, characterized in that said correction encoding means (114) comprises an encoder having a priority control function. The semi-flash type analog/digital converter according to claim 1, characterized in that said correction encoding means (114) comprises means for judging that all of signals from said comparators whose digits are equal to or lower than a digit of a most significant bit signal having said first logic level, as having said first logic level, and encoding judged signals. The semi-flash type analog/digital converter according to claim 3, characterized in that said correction encoding means (114) includes: AND gates (1143-1148) for receiving associated ones of a plurality of signals supplied from said comparators and inverted signals of all signals at upper positions than said associated signals; and means (1140-1142) for encoding output signals of said AND gates. The semi-flash type analog/digital converter according to claim 1, characterized in that said correction encoding means (114) comprises an adder circuit for adding input signals to acquire a predetermined output signal. The semi-flash type analog/digital converter according to claim 5, characterized in that said correction encoding means (114) comprises means for judging that a most significant bit signal of those signals from said comparators which have a first logic level has a second logic level and that those signals at lower positions than said most significant bit signal have said first logic level, and encoding said signals. A semi-flash type A/D converting method comprising: a step of sampling an analog signal to be converted into a digital signal; a step of producing a first group of analog signals (210-216) having predetermined mutually different voltages; a first comparison step of comparing each of said first group of analog signals with said analog signal sampled in said sampling step and outputting signals corresponding comparison results; a first encoding step of encoding signals (230-236) output in said first comparison step; a step of producing a second group of analog signals (220-226) having mutually different voltages in association with digital data acquired in said first encoding step; a second comparison step of comparing each of said second group of analog signals with said analog signal sampled in said sampling step and outputting signals corresponding comparison results; a second encoding step of encoding signals (240-246) output in said second comparison step, said second encoding step including a step of correcting any of said output signals (240-246) of said second comparison step when that output signal is in error, and encoding said corrected signal; and a step of linking digital signals (250-255) acquired in said first and second encoding steps to acquire a conversion result. The method according to claim 7, characterized in that said second encoding step includes a step of judging that all of signals acquired in said second comparison step whose digits are equal to or lower than a digit of a most significant signal having said first logic level, as having said first logic level, and a step of encoding judged signals. The method according to claim 7, characterized in that said second encoding step includes an adding step for adding outputs signals acquired in said comparison steps to acquire a predetermined output signal. The method according to claim 7, characterized in that said second encoding step includes a step of judging that a most significant bit signal of those signals acquired in said second comparison step which have a first logic level has a second logic level and that signals at lower positions than said most significant bit signal have said first logic level, and encoding said signals.

Inventors: SAWAI YASUNORI, SAWAI, YASUNORI, Sawai, Yasunori, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H03M1
IPC codes: H03M1