DEMODULATING LOGARITHMIC AMPLIFIER

Abstract: A logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal. The gain stage includes a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal. A full-wave detector having an input coupled to the intermediate output of the transistor amplifier receives the intermediate output signal and supplies the output signal wherein the detector includes a rectifier comprising transistors having different effective emitter areas. A topology for a logarithmic amplifier is also provided, including a first series-coupled chain of N gain stages having a first input, a second series-coupled chain of M gain stages having a second input, an attenuator coupled between the first input and the second input, a series-coupled chain of summers, each summer receiving an output signal from a respective gain stage in the first series-coupled chain and the second series-coupled chain and supplying a summed signal. A circuit including an output amplifier having an inverting input and a non-inverting input, the inverting input receiving an output of the plurality of gain stages, the non-inverting input receiving a voltage having a negative coefficient of temperature, the output amplifier providing at an output thereof the output signal having a temperature-stable log intercept.

Description: DEMODULATING LOGARITHMIC AMPLIFIER BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the field of logarithmic amplifiers. More particularly, the present invention relates to a high performance, low power logarithmic amplifier cell for use in a multi-stage logarithmic amplifier providing accurate logarithmic intercept and slope response. 2. Discussion of the Related Art Until recently, logarithmic amplifiers were practically unavailable which are useful for both low frequency and high frequency applications, and which are inherently free of sensitivity to temperature variations and production tolerances of the devices comprising the active elements so as to provide high accuracy log-law performance over a wide temperature range and in the presence of large production variations. U.S. Patent Nos. 4,929,909 and 4,990,803 (hereafter "the '909 patent" and "the "803 patent", respectively) , assigned to the same assignee as the present invention and incorporated herein by reference, describe a logarithmic amplifier which does not suffer from the above-noted limitations. FIG. 1 is a block diagram of the logarithmic amplifier disclosed in the '803 patent. The amplifier includes a plurality of amplifier/limiter/detector stages (hereinafter referred to as "gain" stages or "logarithmic amplifier gain stages") 100-1 through 100-n, a gain bias generator 102, a scale bias generator 104, and an offset generator 106, which are common to all gain stages. All of the gain stages working together produce a logarithmic output signal corresponding to the input signal. FIG. 2 is a block diagram for each of the gain stages 100-1 through 100-n. Each gain stage 100-i includes an emitter follower 112-i, having a differential input and balanced output, a full-wave detector 114-i, and a limiting amplifier 116-i. The emitter follower 112-i introduces a slight gain loss of approximately 0.07 dB. The limiting amplifier 116-i can be designed to provide a gain of 10.07 dB, so that the overall stage gain is 10 dB. Although the logarithmic amplifier of the '909 and '803 patents performs well, that demodulating logarithmic amplifier requires relatively complicated gain stages having a relatively large number of active components, both positive and negative power supplies and requires approximately 300 milliwatts of power for a ten stage amplifier. SUMMARY OF THE INVENTION The present invention provides, in accordance with one aspect thereof, a logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal. Alternatively, in response to an alternating input signal, the gain stage produces a demodulated output signal corresponding to a logarithmic value of the input signal. The logarithmic amplifier gain stage includes a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal; and a full-wave detector having an input coupled to the intermediate output of the transistor amplifier that receives the intermediate output signal, and an output that supplies the output signal. The full-wave detector includes a rectifier comprising transistors having different effective emitter areas. The different emitter areas can be formed by physical differences in emitter areas of the rectifier transistors. In another embodiment of the invention, the effect of different emitter areas can be synthesized by using a bias voltage between a base and an emitter of at least one transistor in the rectifier. Other embodiments of the invention include means for extending the usable frequency range by increasing a slew rate of the gain stage without consuming additional power. The logarithmic amplifier gain stage further includes means for reducing a variation in a phase of the output signal with a variation in a level of the input signal. The logarithmic amplifier gain stage of the present invention is less complex and consumes less power than the prior art, and requires power from only a single polarity power supply. In the present invention, the gain stage has been simplified and the full-wave detector performs the demodulating function and also drives the input of the succeeding gain stage with DC level-shifting. The logarithmic amplifier gain stage of the present invention is particularly well suited to use in a multiple stage, logarithmic amplifier system. The response of each stage can be tailored so that the overall logarithmic amplifier has a desired response. A topology for a logarithmic amplifier is also provided, including a first series-coupled chain of N gain stages having a first input, a second series-coupled chain of M gain stages having a second input, an attenuator coupled between the first input and the second input, and a series-coupled chain of summers, each summer receiving an output signal from a respective gain stage in the first series-coupled chain and the second series-coupled chain and supplying a summed signal. A circuit for stabilizing the log intercept with temperature is also provided. The circuit includes an output amplifier having an inverting input and a non-inverting input, the non-inverting input receiving an output of a plurality of gain stages, the inverting input receiving a voltage that has a negative coefficient of temperature, the output amplifier providing at an output thereof the output signal having a temperature-stable log intercept. The features and advantages of the present invention will be more readily understood and apparent from the following detailed description of the invention, which should be read in conjunction with the accompanying drawings, and from the claims which are appended at the end of the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, which are incorporated herein by reference and in which like elements have been given like reference characters, FIG. 1 is a block diagram of a prior art logarithmic amplifier illustrated in the '909 and '803 patents; FIG. 2 is a simplified block diagram of each of the gain stages 100-i illustrated in FIG. 1; FIG. 3 is a simplified block diagram of a logarithmic amplifier gain stage of the present invention which can be used in the basic logarithmic amplifier design illustrated in FIG. 1; FIG. 4 is a simplified schematic circuit diagram of the full-wave detector and limiting amplifier illustrated in FIG. 3; FIG. 4A illustrates another embodiment of the full-wave detector showing how different emitter areas can be generated electrically; FIG. 4B illustrates slew rate limitations in the detectors of FIGS. 4 and 4A; FIG. 4C illustrates a modification to the full-wave detectors of FIGS. 4 and 4A which overcome slew rate limitations without consuming additional power; FIG. 5 is a detailed schematic circuit diagram for an embodiment of the gain stage of the present invention; FIG. 6 is an overall block diagram of a logarithmic amplifier in accordance with one aspect of the present invention; FIG. 7 is a graph depicting the response of the two amplifier chains illustrated in FIG. 6; FIG. 7A is a graph illustrating the total output signal of the logarithmic amplifier of FIG. 6; FIG. 8 is a block diagram of a typical bias circuit that may be used in a logarithmic amplifier in accordance with one aspect of the present invention; FIG. 9 is a simplified block diagram of an output circuit that may be used in the logarithmic amplifier of the present invention; and FIG. 10 is a detailed schematic circuit diagram for an embodiment of the output circuit of FIG. 9. DETAILED DESCRIPTION FIG. 2 illustrates the configuration of each of the gain stages 100-i in the logarithmic amplifier of the '803 patent. There is a separate emitter follower circuit 112-i, a full-wave detector circuit 114-i, and a limiting amplifier 116-i in each stage. Reference is now made to FIG. 3 which shows a simplified block diagram of the logarithmic amplifier gain stage of the present invention. Each of the gain stages 200-i of FIG. 3 replaces gain stages 100-i illustrated in FIG. 2 in an amplifier of the type shown in Fig. 1. The gain stages 200-i each include a limiting amplifier 216-i and a full-wave detector 214-i. The separate emitter follower circuit in FIG. 2 is not used; its function is incorporated into full-wave detector circuit 214-i. Thus, in the present invention, the gain stages have been simplified and the transistors in the full-wave detector perform both the demodulating function and provide power-gain and DC-level translation to the input of the succeeding gain stage. Reference is now made to FIG. 4, which is a simplified circuit schematic of the gain stage 200-i illustrated in FIG. 3. Although the present invention is illustrated as being implemented using bipolar NPN transistors, PNP transistors can be used where the gain stage is powered by a negative single polarity power supply. Gain stage 200-i is powered by a single polarity power supply which may be, for example, a +5 volt supply. Plus 5 volts is applied to terminal 232. Limiting amplifier 216-i includes a long tail pair 220 comprising transistors 222 and 224 and resistors 226 and 228. An input signal V. is applied across nodes 221 and 223. Resistors 226 and 228 are equal valued resistors. A tail current generator 230 generates a tail current I which is essentially proportional to absolute temperature (PTAT) . Tail current generator 230 may operate in the manner described in the '909 and '803 patents for limiting amplifier 116-i. The full-wave detector 214-i is composed of transistors 234, 236, 238, and 240. Resistors 242 and 244 bias base node 246 between transistors 236 and 238. Transistors 234 and 240 function as emitter followers supplying current to drive a succeeding amplifier stage connected to nodes 248 and 250, as well as functioning as part of the full-wave detector. Transistors 234 and 236 form a first half-wave detector and transistors 238 and 240 form a second half-wave detector so that the entire envelope of the input signal can be demodulated. The demodulated logarithmic output appears as a current at node 252. An additional benefit to the topology of the present invention is the elimination of the cascode transistors 162 and 164 used in detector 114-i in the '803 patent. As will be explained in greater detail, the voltage at node 246 is independent of the signal. Consequently, there is no displacement current due to base-collector capacitances of transistors 236 and 238 that could disturb the output node 252. As a result, cascode transistors 162 and 164 are not needed. Detector current generators 254 and 256 generate a temperature-stable detector bias current, I, in the manner described in the "803 patent. In the gain stage of the '803 patent, the bias currents of the emitter follower circuit 112-i 'were made PTAT. By contrast, in the present invention, the bias current I, of emitter followers 234 and 240, since they are now incorporated into the full-wave detector and function as part of the detector circuit as well as emitter followers, correspond to the stable detector-scaling currents of the '803 patent. Since the common base node 246 is biased by resistors 242 and 244, the effective value of load resistors, R , which, determines the gain A is equal to the parallel combination of the value of the collector resistor 226 or 228 in each leg of the long tail pair and the value of the base resistors 242 or 244. Thus, the effective load resistance, R_, of the gain stage may be found from the following equation; (1) R. *a = R c + where: R c - the resistance of either resistor 226 or 228 R b = the resistance of either resistor 242 or 244 This topology is useful because the values of R and R, can be chosen over a wide range as long as the resulting effective value R provides the desired gam. It does not matter if resistances R, are made low and resistances are made high or vice versa. The presence of high resistances in the base circuit has no essential impact on the slew rate of the circuit, since the base charge required to change the current in either transistor 236 or 238 is provided by the opposite member of this pair, not by the current in the base resistors 242 and 24 . That is, if transistor 238 is turning on, the base charge is provided from transistor 236, which at that time is turning off, due to the symmetry of the voltage drive at the respective emitters of transistors 236 and 238. In the same manner, high values of resistors 226 and 228 allow the introduction of a DC voltage drop across the collector loads, which can be used to establish a preferred bias level at the amplifier output nodes 248 and 250, without adversely affecting the slew rate of the logarithmic amplifier gain stage. An additional benefit of this flexibility in the partitioning of the net load R between resistors Rb, and Rc allows the collector and base resistors to be fabricated as integer multiples of some unit value, which value is used elsewhere in the biasing system for the overall logarithmic amplifier, to thereby insure very accurate calibration even when the unit value is considerably different from the target value. As long as all of the unit values are the same, compensation can be provided for variations of the unit value from the target value. That is, the relative values of the resistors are more important than the absolute values of the resistors. Alternatively, the signal across nodes 258 and 260 can be connected directly to the next gain stage in the logarithmic amplifier. However, extra compensation circuitry is required to compensate for the sensitivity to the beta of transistors 222 and 224, since the succeeding gain stage would directly load the preceding gain stage. A key feature of the full-wave detector 214-i of the present invention is that the effective emitter areas of transistors 236 and 238 are smaller than the effective emitter areas of transistors 234 and 240. This emitter area ratio between transistor pairs 234,236 and 238,240 is represented by \, where λ is greater than 1. That is, if transistors 112 and 114 had an emitter area of "e," then transistors 110 and 116 would have emitter area ratios of (λ)(e). The term "effective emitter area" is used because, as will be described hereinafter, the difference in emitter area or area ratio can be achieved by physical variations in emitter area, or by electrical control of the detector transistors. For zero-signal conditions, there is essentially no voltage difference between the bases of transistors 234 through 240. The portion of the detector bias currents I , is divided in proportion to the emitter areas of the respective detector transistors as follows: (2) T-C234 = I C240 = ~, 1 + λ C where: C234 = "t ^ ιe co ^ ector current of transistor 234 I C240 = tιe collector current of transistor 240 ( 3 ) IC236 ~ I C238 = ~, 1 + λ ( where: I C236 = the col l ec'tor current of transistor 236 I C238 = the collector current of transistor 238 Transistors 238 and 240 respond to signals having one polarity, while transistors 234 and 236 respond to signals having an opposite polarity. Since detector 214-i is a full-wave detector, if the signal has one polarity, transistors 238 and 240 are conducting, while transistors 234 and 236 will be cutoff. Conversely, if the signal has the opposite polarity, transistors 234 and 236 are conducting, while transistors 238 and 240 are cutoff. As illustrated by equations (2) and (3), the proportion of the detector bias current I, which reaches the output node 128 is»a function of the emitter area ratios in each of the pairs of transistors (234,236 or 238,240) in the full-wave detector. There is an "optimum" value of , meaning the value of λ that results in the maximum change in the detector output, between zero signal and full-limiting for any given value of the bias current I,. Optimizing the value of λ results in the maximum detector "efficiency," which reduces power requirements since the largest output signal is produced for a given detector bias current. "Efficiency" in this context means the relationship between the quantity of output current for a given bias current. In addition, operating the detector circuit at the optimum value of reduces the sensitivity of the detector to small errors in λ that may occur during the circuit fabrication process, One skilled in the art will appreciate that the detector efficiency is zero when λ equals 1 because there is no even-order nonlinearity in the detector stage and therefore no rectification occurs at any signal level. At the other extreme, when λ is very large, the detector efficiency again approaches zero because the voltage output from limiting amplifier 216-i at nodes 258 and 260 cannot overcome a built-in offset voltage, V OS, due to the area ratio, between the bases of transistors 234,236 and 238,240. This offset voltage can be expressed as follows: (4) V os = kT In λ where: k = Boltzmann's constant T = absolute temperature q = the electronic charge Consider the case where λ equals 100. Using equation 4, the effective offset voltage at T = 300°K would be [25.85 millivolts] • [ln(100)], or 119 millivolts. If the gain of amplifier 216-i is 10 dB, the peak output voltage across the collectors of transistors 222 and 224 is 163.5 millivolts (for ideal transistors at 300°K); therefore, the peak differential drive to either transistor pair 234,236 or 238,240 (due to the splitting of the collector signal by resistors 242 and 244) is 81.75 millivolts. Since 81.75 millivolts is less than the offset voltage of 119 millivolts, there is very little rectified output voltage from the detector for such a high value of λ. There is an "optimum" (as previously defined) value of the detector offset voltage, V , or equivalently, the emitter-area ratio, λ, for any given gain, A, of the gain stage. Table I illustrates examples of the optimum value of λ for a given value of the gain A. Operation at the optimum value of λ results in two benefits: (1) small errors in the value of λ which occurred due to production tolerances will not grossly alter the efficiency of the full-wave detector and (2) the detector output current variation between the zero-signal and fully-limiting conditions is the largest possible fraction of the detector bias current . Consequently, the optimum value of λ results in the largest detector output signal at node 252 with the smallest consumption of power. In the logarithmic amplifier gain stage of the present invention, transistors 234 and 236 are used as part of full-wave detector 214-i but also function as emitter followers which supply the current to drive the next succeeding gain stage in a multi-stage logarithmic amplifier. This results in some signal attenuation to the succeeding gain stage. This attenuation must be known in order to accurately determine the overall stage gain between the input nodes 221,223 and the output nodes 248,250. Although the operation of transistors 234 and 236 will be explained, the explanation applies with equal force to the operation of transistors 238 and 240. The voltage at node 246 is essentially fixed because the output from amplifier stage 216-i is fully differential. Consequently, for small signals, an incremental voltage ΔV cl3u s conveyed to output node 248 by an attenuator composed of the dynamic emitter resistances of transistors 234 and 236, which produces a smaller output voltage, Δ v e234 - Since the detector bias current splits among the detector transistors according to equations (2) and (3) the dynamic emitter resistances of transistors 234 and 236 are: <5) r e234 - * = 1 + λ V t J C234 τ d where: r e 234 = the dynamic emitter resistance of transistor 234 V t = kT T- C234 = the collector current of transistor 234 Ij = the detector bias current (6) r Θ236 = V t* = 1 λ + + λ λ V T I C236 d where: r 2 _ 6 = the dynamic emitter resistance of transistor 236 V t = kT I C236 = t ^ ιe c °ll ector current of transistor 236 I, = the detector bias current Consequently, the dynamic emitter resistances for small signals are in the ratio: (7) r e236 = λ r e234 The dynamic emitter resistances are independent of either V or I,. The dynamic emitter resistances are in the same ratio as the ratio of the emitter areas. As a result, the signal ΔV_ 130 is attenuated by a factor λ/(l + λ) . This loss is predictable and compensation can readily be provided by using a slightly higher gain in amplifier 216-i. This higher gain is denoted as A' and is: (8) A' = 2(kT)/q 1 + λ An important performance advantage of the topology of the gain stage of the present invention arises from the fact that the voltage at node 246 is essentially independent of the signal because of the inherent symmetry of gain stage 216-i. The signal voltages at the input nodes 221 and 223 cause the collectors of transistors 222 and 224 to change by exactly equal increments, but with opposite polarity. Consequently, since the voltage at node 246 is essentially fixed, no displacement currents due to the input signal are generated by the collector-base capacitances of transistors 236 and 238. This absence of capacitive coupling to the logarithmic output is very important in high frequency logarithmic amplifiers, since these displacement currents can seriously degrade logarithmic accuracy at high frequencies. As referred to earlier, this is the reason why cascode transistors 162 and 164 can be eliminated. Reference is now made to FIG. 4A which illustrates an alternate embodiment of the logarithmic gain stage of the present invention. The operation of the gain stage illustrated in FIG. 4A is exactly the same as that described in connection with the embodiment illustrated in FIG. 4. However, in FIG. 4A, transistors 234A, 236A, 238A, and 240A are identical and have the same emitter areas. Thus, the physical ratio of emitter areas is 1. However, the effect of different emitter areas can be achieved by adding or subtracting a voltage to the V_ E of a transistor. Thus, in FIG. 4A, an effective non-unity emitter area ratio between transistors 234A,236A and 238A,240A can be achieved by adding or subtracting a voltage to node 246A. Lowering the voltage at node 246A causes transistors 236A and 238A to behave as if their emitter areas are physically smaller than the emitter areas of transistors 234A and 240A, respectively. In the same manner, raising the voltage at node 246A causes the transistors 236A and 238A to behave as if their emitter areas they are physically larger than the emitter areas of transistors 234A and 240A. This is referred to as "synthesizing" the area ratio between the transistors. As illustrated in FIG. 4A, the addition of another current source 270A that supplies a current I, acts to lower the voltage at node 246A so that the emitters of transistors 236A and 238A conduct a smaller current than they normally would for the given bias voltage at node 246A. Thus, the emitters of transistors 236A and 238A behave as if they are physically smaller than the respective emitters of transistors 234A and 240A. The current generated by current source 270A (i.e., I. ) must be PTAT so that the "synthesized area ratio" between transistors 234A,236A and 238A,240A is stable over temperature. Synthesizing an area ratio by the use of a voltage allows the physical size of transistors 236A and 238A to be reduced, thereby lowering their respective base-collector capacitances. Reducing the base collector capacitances lowers the capacitive loading on amplifier stage 216—i, resulting in higher bandwidth. Furthermore, any area ratio can be synthesized by changing the values of resistors 242A and 244A and/or the current I. , The values of resistors 242A and 244A and the magnitude of the current can be combined in any proportion to synthesize a desired area ratio. Additionally, physical area ratios and synthesized area ratios can be combined in any proportion to achieve a desired overall area ratio. This particular feature allows for flexibility in producing a monolithic integrated circuit because different die sizes and space considerations can be accommodated by choosing the respective proportions of physical and synthesized area ratio. The present invention is designed to provide a logarithmic amplifier gain stage that consumes only a small fraction of the power of a comparable logarithmic gain stage, as described, for example, in the '803 patent. However, as the power consumed by the logarithmic gain stage is lowered, the available dynamic range begins to decrease partly due to the parasitic capacitances of the transistors. In the present invention, the upper frequency at which accurate logarithmic performance can be obtained is limited by the finite slew rate at nodes 248A and 250A (or 248 and 250) as the detector currents I, are reduced to reduce power consumption. FIG. 4B illustrates this slew rate limitation in the circuit of FIG. 4A. (Although this slew rate limitation will be explained with reference to the circuit of FIG. 4A, the explanation applies with equal force to the circuit of FIG. 4.) Capacitances 280B and 282B represent the total output node capacitance due to parasitic effects and input capacitances of succeeding circuits at nodes 248B and 250B, respectively. When the base of one of the emitter follower transistors 234B or 240B is abruptly switched negative, the voltage at its emitter decreases at a rate determined by the node capacitance and the detector current I j . For example, as shown in FIG. 4B, a positive-going input signal 284B is applied to node 258B. In the same manner, a negative-going signal 286B is applied to node 260B. The voltage at node 248B increases almost immediately, as shown by waveform 290B, charging node capacitance 280B. By contrast, node 250B has to decrease in voltage and is limited by the rate at which node capacitance 282B can be discharged. This delay is shown by waveform 288B. Consequently, during the time interval when the voltage at node 250B is decreasing, transistor 238B remains essentially nonconducting and cannot contribute to the net detector and stage output at node 252B. The overall result of this phenomenon is a decrease in the effective gain as the frequency of the input signal increases, which in turn limits the useful bandwidth of the gain stage. Although primarily due to the low power consumed by the gain stage, the situation is exacerbated in the case where the logarithmic amplifier gain stage is powered by a single polarity power supply, since there is no negative supply voltage that could be used to rapidly discharge node capacitance 280B. Reference is now made to FIG. 4C, which illustrates a full-wave detector circuit that overcomes the slew rate limitation of the circuit in FIG. 4B. In the detector circuit of FIG. 4C, transistor 300C and resistor 302C embody current source 254C while transistor 304C and resistor 306C embody current source 256C. An appropriate temperature-stable bias voltage is applied to terminal 299C. A capacitor 308C is connected between node 310C and 312C. A second capacitor 314C is connected between nodes 316C and 318C. When signal 284C is applied to the base of transistor 234C (node 258C) , a pulse of charge Q equal to (ΔV 310C ) • ( C 282( -J appears at the collector of transistor 234C. > * The impedance of capacitor 308C to the fast rising edge of signal 286C is much lower than the impedance of load resistor 318C, so almost all of the charge Q is transmitted to node 312C. Node 312C also presents a low impedance to this current pulse. The voltage at node 312C decreases, causing transistor 304C to conduct an amount of current for a sufficient time to convey charge Q . Thus, node capacitance 280C is charged without delay by current from transistor 304C. The current provided to node 312C is exactly the current required to move node 250C by the change in voltage caused by signal 286C, while still leaving the appropriate fraction of bias current for the detector cell. This topology allows the node capacitance of the negative-going output terminal to be charged by a current from the positive-going portion of the detector without requiring any additional power from the power supply. Reference is now made to FIG. 5, which is a detailed schematic circuit diagram of one embodiment of the logarithmic amplifier gain stage 200-i of the present invention. The circuit of FIG. 5 is a very low power gain stage powered by a single polarity power supply and typically consuming less than one tenth the power of one of the gain stages in the '803 patent. Stage 200-i includes limiting amplifier 216-i and full-wave detector 214-i. The stage operates from a single 5-volt supply, with +5 volts supplied to terminal 330 and a ground connected to terminal 332. The logarithmic input signal is applied between terminals 334 and 336 and the logarithmic output signal is available at terminals 338 and 340. A demodulated output signal is available at terminal 382. Transistors 342 and 344, along with resistors 346, 348, and 350 form the differential limiting amplifier stage 216-i. Transistor 352, resistors 354 and 356, and capacitor 358 form the PTAT current source for the transistor amplifier. A PTAT beta-compensated bias voltage, generated in the manner described in the '803 and '909 patents, is supplied at terminal 360. Transistors 362, 364, 366, and 368, along with resistors 370, 372, 374, 376 and capacitors 378 and 380 comprise the full-wave detector stage. Resistors 346, 348, 350, 370, and 372 are all unit value resistors as described earlier. Terminal 382 may also be used to receive a current for adjusting the intercept of the logarithmic amplifier gain stage. In the embodiment illustrated in FIG. 5, transistors 362, 364, 366, and 368 all have equal emitter areas. Transistor 384 along with resistors 386, 388, 390, and 392 is used to synthesize an area ratio between transistors 362,364 and 366,368 at node 365 in the manner described in connection with FIG. 4A. Transistor 368 receives the necessary PTAT bias voltage from terminal 360 via resistor 392. Slew rate enhancing capacitors 394 and 396 are connected and operate in the manner described in connection with FIG. 4C to enhance the high frequency response of the gain stage. Transistors 398 and 404, resistors 400 and 406, and capacitors 402 and 408 comprise the temperature-stable current sources for the full-wave detector. A temperature-compensated bias voltage, generated in the manner described in the '803 and '909 patents, is applied to terminal 410 and biases the bases of transistors 398 and 404 via resistor 412. Diode-connected transistor 414, pinch resistor 416, and capacitor 418 are used to lower the DC level at output terminals 338 and 340, further increasing the bias "headroom" for the detector transistors and providing power supply-line decoupling at high frequencies. In particular, pinch resistor 416, being a 16K resistor and capacitor 418, being a 10 picofarad capacitor, provides a relatively very long time constant to filter any disturbances on the power supply line. The use of transistor 414 having its base coupled to resistor 416 allows the resistance of resistor 416 to be smaller than would otherwise be required to provide the relatively very long time constant. This filter has a corner frequency of approximately 1 MHz and therefore higher frequency disturbances on the order of 100 MHz or higher are heavily attenuated and provide extra noise filtering for the differential amplifier. Because the value of pinch resistor 416 is multiplied by beta (NM X 16K) , the filter avoids the use of large value capacitors that would otherwise be required to provide filtering with changes in temperature. When the logarithmic amplifier gain stage is used in a complete logarithmic amplifier system having multiple cascaded stages, it is necessary to control the variation of phase with changes in the input signal level to maintain accurate performance. As is well-known, phase errors arise because of the natural build up of phase lag that occurs in any multi-pole system. However, the phase lag is much more difficult to predict in a non-linear system such as a logarithmic amplifier. Feedback capacitors 420 and 422 minimize the variation of phase with variations in input signal level. In accordance with another aspect of the present invention, the logarithmic amplifier gain stage may be particularly advantageously used in a logarithmic amplifier comprising two amplification chains. Although the disclosed logarithmic amplifier gain stage may be used in this amplifier organization, this is not a requirement. Other logarithmic amplifier gain stages, such as those disclosed in the '803 patent may be used as well. FIG. 5 of the "803 patent illustrates a parallel array of limiter elements driven via gain stages (the K gain elements) or attenuator stages (the J attenuators) . The outputs of each of the limiter stages are directly summed to provide the logarithmic output signal. This parallel chain works well for input signals having a large amplitude that require no further amplification. However, since the outputs of the limiter cells are immediately summed to provide the output signal and provide no further amplification, the usefulness of this type of circuit topology in the case of small amplitude input signals is limited. FIG. 6 of the '803 patent illustrates a series chain of amplifier stages 32-n that provides an average output signal by summing the output of the chain and the outputs of each individual amplifier stage. This circuit topology provides amplification for small signal inputs, but large amplitude input signals will typically cause all of the stages in the chain to go into limiting and therefore the overall circuit may not provide a correct corresponding output signal. Although it would be desirable to modify the gain stages to extend the dynamic range, when designing a high accuracy logarithmic amplifier, noise considerations typically preclude this modification of the gain stages because these modifications tend to increase the circuit noise level. This is especially true with a multi-stage logarithmic amplifier in which the stages are DC coupled rather than AC coupled as is conventional. Since the AC coupling is not available to provide bypass filtering for the noise in a preceding amplifier stage, noise from each stage is transmitted through the entire amplifier chain causing deterioration in available dynamic range. FIG. 6 illustrates a logarithmic amplifier circuit topology that extends the dynamic range of the logarithmic amplifier in order to handle input signals having relatively large amplitudes while providing amplification of relatively small amplitude input signals and maintaining an adequate noise margin to provide high performance. The circuit 500 of FIG. 6 provides two logarithmic amplifier chains 502, 504. Each of the logarithmic amplifier chains 502, 504 includes a number of logarithmic amplifier chain stages 506-i, 507-i. Amplifier chain 502 has N stages while amplifier chain 504 has M stages. N and M may be the same or different. The output of each stage number 506-i, 507-i is applied- o a summer 508-i (for example, an analog summer). The output of each summer is in turn supplied to a succeeding summer until the last summer in the chain, 508-n, provides the logarithmic output. The input signal V. is supplied directly to amplifier chain 502 and through an attenuator 510 to amplifier chain 504. Thus, the magnitude of the signal supplied to amplifier chain 504 will be smaller than that applied to amplifier chain 502. FIG. 7 illustrates the operation of amplifier chains 502, 504. Amplifier chain 502, since it receives the input signal directly, provides an output corresponding to curve 512. On the other hand, amplifier chain 504 provides an output corresponding to curve 514. The displacement between curves 512 and 514 along the input signal axis is a function of the amount of attenuation A (in dB) provided by attenuator 510. As illustrated in FIG. 7, amplifier chain 504 does not begin responding until a signal of sufficient magnitude has been applied to attenuator 510 and the input signal reaches point 516. For smaller inputs, however, amplifier chain 502 has been responding to input signal V. and provides an output corresponding to curve portion 518. At an input signal level large enough to cause all stages in amplifier chain 502 to be in limiting, due to the increased amplitude of input signal v., amplifier chain 504 begins responding to the input signal V. as indicated by curve portion 520. FIG. 7A illustrates the output provided at summer 508-n. Curve 522 is simply the sum of curves 512 and 514. Thus, the topology of FIG. 6 allows the logarithmic amplifier to respond to small amplitude inputs signals and provide amplification with minimum noise, while at the same time extending the dynamic range to be able to accurately respond to larger amplitude input signals. As was noted in the '803 patent, the logarithmic intercept of the system described herein may be temperature-stabilized by either employing a PTAT attenuator ahead of the complete amplification system or by introducing at the output node (a current summing junction) a current which varies with temperature in such a way as to offset intercept movement which otherwise would be generated. In accordance with another aspect of the present invention, the log intercept is temperature-stabilized when the output is a voltage. The use of a long-tailed pair as the amplifier stage is illustrated in FIG. 5 and includes transistors 342, 344, and resistors 346, 348, and 350. One consequence of the use of the long-tailed pair is that the log intercept will be proportional to temperature. Analysis indicates that the intercept of the resulting log function increases with temperature by an amount equivalent to approximately 0.0289dB/°C at approximately 27°C. Therefore, to ensure that the log intercept is stable over temperature, a correction corresponding to -0.0289dB/°C needs to be added at the output of the logarithmic amplifier. Additionally, some applications may require amplification of the output signal in order to provide the proper range for successive circuits, such as CMOS analog-to-digital converter. In addition, when using this type of circuitry, it is often desirable that the output of the logarithmic amplifier be able to go down to ground (i.e., "0" volts) (particularly in the case where the amplifier is powered by a single polarity power supply) . Finally, some post-demodulation filtering of the output may be required for certain applications. FIG. 8 illustrates a bias circuit that may be used in accordance with the output amplifier of the 'present invention to be described in greater detail hereinafter. Bias circuit 600 is coupled to the supply voltage at terminal 602 and to ground at terminal 604. Bias circuit 600 provides bias power at terminal 606. One of the consequences of using such as bias circuit is that the bias signal at terminal 606 will have a slight negative temperature coefficient because of the base emitter voltage of transistor 608. This temperature coefficient is approximately -2 millivolts/°C. The bias voltage at terminal 606, given the choice of components illustrated, is approximately 1/4 of the supply voltage plus the base-emitter voltage that includes this temperature coefficient. FIG. 9 illustrates an output amplifier that provides temperature compensation of the log intercept, post-demodulation filtering, any necessary gain, and allows the output of the amplifier to go down to ground (0 volts). In circuit 700, the output of the logarithmic amplifier gain stage at, for example, terminal 338 or 340 is applied to terminal 702 (the non-inverting input of opamp 712). A Sallen-key filter, if node 702 is current driven, for example by a current mirror disposed between the output of a gain stage and node 702, is provided by resistors 704, 706 and capacitors 708, 710 and opamp 712 to provide post-demodulation filtering capability. The gain of amplifier 712 is set by the choice of resistors 714, 716, 718, and 720. Bias power is provided to terminal 722 from the bias circuit of FIG. 8. The use of resistors coupled to the inverting input of opamp 712 in conjunction with a bias voltage having a negative temperature coefficient provides a voltage having a well-defined negative coefficient of temperature that is added to the logarithmic voltage output provided by the gain stages that offsets the effect of temperature on the transistor amplifier in the gain stages. The values of the resistors are chosen to provide the proper temperature coefficient. However, resistors 714, 716, 718, 720 may additionally provide other functions. In the illustrated embodiment, the resistances of resistors 714, 716, 718, and 720 are chosen to simultaneously satisfy three conditions, as will be explained in greater detail hereinafter. The values are chosen to first provide the necessary log intercept correction to maintain the log intercept stable with temperature. Second, the values of the resistors are chosen to set the gain of amplifier 712, depending upon the specific application requirements. Third, the values of the resistors are chosen to allow the output node 724 to go down to zero volts. Although a specific bias circuit and temperature compensation circuit has been illustrated, it is to be appreciated that other circuits* for supplying a voltage having a well-defined negative coefficient of temperature to the inverting input of opamp 712 may also be used. The overall concept is to supply a voltage having a well-defined negative coefficient of temperature to the inverting input of the output amplifier (which may simply be a buffer amplifier) that purposely compensates for the temperature coefficient of the long-tailed pair in the gain stage (or stages) to a supply log output having a temperature-compensated log intercept at the output of the output amplifier. A specific example will serve to illustrate. FIG. 10 illustrates a specific example of a circuit that satisfies the above conditions. Circuit 800 in FIG. 10 allows output node 802 to have an output of zero volts, provides an amplification factor of 2 and provides the necessary correction voltage to stabilize the log intercept over temperature. In circuit 800, terminal 804 is coupled to the supply voltage and terminal 806 is coupled to ground. Terminal 811 provides a separate ground to enhance noise performance. Bias power from circuit 600 is applied to terminal 808. The logarithmic signal from an amplifier stage is applied to terminal 810. In the manner described in connection with FIG. 5, terminal 812 may be used to supply a current for adjusting the intercept of a logarithmic amplifier gain stage ' . One particular advantage of the circuit of FIG. 10 is that operational amplifier 712 is composed of transistors QN1, QN2, QN4, and QN3, a simple design that is easy to implement. However, this circuit has the disadvantage of not being able * 'to properly supply a zero volt signal at terminal 810, since the base emitter voltage of QN4 will cause the collector of transistor QN1 to become forward biased. However, as will be explained, the choice of the resistors in the negative feedback path allows this simple output amplifier to be used while still allowing output node 802 to reach zero volts. The Sallen-key filter of FIG. 9 is provided in FIG. 10 by capacitor CN1, capacitor CN2, resistor RN2, and resistors RN1A, RN1B, and RN1C. Resistor 714 is provided by resistor RN5 and resistor 716 is provided by resistors RN6A and RN6B. Resistor 718 is provided by resistors RN7A and RN7B. Resistor 720 is provided by resistors RN12A, RN12B, RN12C, and RN12D. Transistor QN5, QN6, QN7 along with resistor RN4 and capacitor CN4 are used to drive output node 802. Resistor RN4 prevents drive current from the QN4, QN3 current mirror from being diverted from QN6. At an. input-related logarithmic slope of 18.75 mv/dB, a correction of +0.0289 X 18.75 mv/°C must be introduced into the input of output amplifier to ensure that the log intercept is stable over temperature. This correction amounts to -0.542 mv/°C at the inverting input of amplifier 712 (the base of transistor QN2) . The voltage at terminal 808 is approximately 2V DC (the bias voltage plus 0.7V BE at 27°C) minus 1.67mv/°C (the temperature coefficient of the base emitter voltage of transistor 608 in circuit 600). Given this value, the values of resistors RN12A, RN12B, RN12C, RN12D, RN7A, RN7B, RN5, RN6A, and RN6B are chosen to provide the necessary temperature compensation as well as a gain*-of 2 for the output stage. This circuit advantageously also shifts the DC level or the output at node 802 lower by approximately 1.32V, thus allowing the input voltage to the opamp to always be above ground by a high enough voltage to avoid common-mode range limitations of this amplifier, while still allowing output node 802 to have a minimum output of zero volts. This output circuit allows introduction of correction factors into the inverting input of the output operational amplifier to provide temperature-stabilization of the log intercept, control the gain of the output amplifier, and provide a DC level shift of the output amplifier node. Although the circuit has been described in conjunction with a demodulating logarithmic amplifier, it is to be appreciated that the technique for temperature-stabilizing the log intercept may also be applied to baseband logarithmic amplifiers that respond to the instantaneous input in those cases where only the magnitude and not the sign of the input signal varies. Having thus described one particular embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only is not intended as limiting. The invention is limited only as defined in the following claims and equivalents thereto. What is claimed is:

Claims: CLAIMS 1. A logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal, comprising: a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal; a full-wave detector having an input coupled to the intermediate output of the transistor amplifier that receives the intermediate output signal and an output that supplies the output signal, the detector including a rectifier comprising transistors having different effective emitter areas for demodulating a signal applied to the input of the full-wave detector. 2. The logarithmic amplifier gain stage of claim 1, further comprising means for increasing a slew rate of the gain stage without consuming additional power. 3. The logarithmic amplifier gain stage of claim 2, wherein the full-wave detector comprises two half-wave rectifiers that respectively respond to input signals having different polarities. 4. The logarithmic amplifier gain stage of claim 3, wherein the means for increasing the slew rate comprise capacitors coupled between the half-wave rectifiers. 5. The logarithmic amplifier gain stage of claim 1, further comprising means for reducing a variation in a phase of the output signal with a variation in a level of the input signal. 6. The logarithmic amplifier gain stage of claim 5, wherein the means for reducing a variation in a phase of the output signal with a variation in a level of the input signal comprise at least one capacitor coupled between the input and the output. 7. The logarithmic amplifier gain stage of claim 1, wherein the gain stage requires power from only a single polarity power supply. 8. The logarithmic amplifier gain stage of claim 1, wherein the different emitter areas are formed by physical differences in emitter areas of the rectifier transistors. 9. The logarithmic amplifier gain stage of claim 1, further comprising means for controlling a voltage between a base and an emitter of at least one transistor in the rectifier to synthesize the different emitter areas. 10. A logarithmic amplifier, comprising: a first series-coupled chain of N gain stages having a first input, each gain stage supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal; a second series—coupled chain of M gain stages having a second input, each gain stage supplying, in response to the instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal; an attenuator coupled between the first input and the second input; and a series-coupled chain of summers, each summer receiving an output signal from a respective gain stage in the first series-coupled chain and the second series-coupled chain and supplying a summed signal. 11. The logarithmic amplifier of claim 10, wherein each gain stage in the chain of N gain stages and the chain of M gain stages comprises: a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal; a full-wave detector having an input coupled to the intermediate output of the transistor amplifier that receives the intermediate output signal and an output that supplies the output signal, the detector including a rectifier comprising transistors having different effective emitter areas for demodulating a signal applied to the input of the full-wave detector. 12. The logarithmic amplifier gain stage of claim 11, further comprising means for increasing a slew rate of the gain stage without consuming additional power. 13. The logarithmic amplifier gain stage of claim 12, wherein the full-wave detector comprises two half-wave rectifiers that respectively respond to input signals having different polarities. 14. The logarithmic amplifier gain stage of claim 13, wherein the means for increasing the slew rate comprise capacitors coupled between the half-wave rectifiers. 15. The logarithmic amplifier gain stage of claim 11, further comprising means for reducing a variation in a phase of the output signal with a variation in a level of the input signal. 16. The logarithmic amplifier gain stage of claim 15, wherein the means for reducing a variation in a phase of the output signal with a variation in a level of the input signal comprise at least one capacitor coupled between the input and the output. 17. The logarithmic amplifier gain stage of claim 11, wherein the gain stage requires power from only a single polarity power supply. 18. The logarithmic amplifier gain stage of claim 11, wherein the different emitter areas are formed by physical differences in emitter areas of the rectifier transistors. 19. The logarithmic amplifier gain stage of claim 11, further comprising means for controlling a voltage between a base and an emitter of at least one transistor in the rectifier to synthesize the different emitter areas. 20. A logarithmic amplifier, comprising: a plurality of gain stages, each gain stage supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal; each gain stage including a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal and a full-wave detector having an input coupled to the intermediate output of the transistor amplifier that receives the intermediate output signal and an output that supplies the output signal, the detector including a rectifier comprising transistors having different effective emitter areas for demodulating a signal applied to the input of the full-wave detector; and an output amplifier having an inverting input and a non-inverting input, the non-inverting input receiving an output of the plurality of gain stages, the inverting input receiving a voltage having a negative coefficient of temperature, the output amplifier providing at an output thereof the output signal having a temperature-stable log intercept. 21. The logarithmic amplifier of claim 20, wherein the voltage having a negative coefficient of temperature is provided by at least two resistors having a predetermined ratio of resistances. 22. The logarithmic amplifier of claim 21, wherein the output amplifier further has a gain determined by the predetermined ratio of resistances. 23. The logarithmic amplifier of claim 22, wherein the output amplifier is a long-tailed pair differential amplifier powered by a single polarity power supply and the predetermined ratio of resistances further allows the output of the output amplifier to reach a ground voltage without exceeding a common-mode range of the differential amplifier. 24. The logarithmic amplifier gain stage of claim 1, further comprising a noise-filtering circuit including a beta-multiplied pinch resistor and a capacitor coupled to the transistor amplifier.

Inventors: GILBERT BARRIE, GILBERT, BARRIE
Applicants: ANALOG DEVICES INC, GILBERT BARRIE, ANALOG DEVICES, INC.
Application year: 1993
Main classification: H03G7
IPC codes: H03D1, H03G7, H03G11