Count unit for non volatile memories

Abstract: A count unit (1) for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter (8) and a number of registers (9, 10) equal in number to the count functions involved. The registers (9, 10) store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter (8) which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One (10) of the registers presents a second parallel input (ADDR) for externally loading an initial data which may be transferred to the other registers (9) via the counter (8).

Description: The present invention relates to a a count unit, in particular for nonvolatile memories, like flash-EPROMS, according to the preamble of claim 1. As is known, flash type nonvolatile memories involve a particularly complex erasure procedure: firstly, the entire memory must be preprogrammed to "0", then actually erased and possibly also any incorrectly erased cells are checked and adjusted. To perform these operations, flash type memories contain a sequencer implemented by a state machine and connected to a signal interpreter. The operations to be performed -involve various count operations which, to avoid an excessive increase in the number of states or complexity of the state machine, cannot be performed directly by the sequencer. For this purpose, the memory features an oscillator which supplies a time base for both the count operations and rendering the control logic fully synchronous. By way of example, the count functions absolutely essential in a flash memory of the type described are: a) scanning of the address of all the memory locations for programming and/or content checking after each modification pulse; b) duration of programming and erase pulses, and slow signal stabilizing delay times (not controllable using straightforward analog delays); c) number of programming and/or erase attempts made for each request from the signal interpreter: the specification of this type of memory always provides for a maximum modification time after which an external error flag must be supplied; d) scanning various voltages at which to set the circuit of cells for adjustment, which may be achieved by decoding the outputs of a counter which thus controls a variable-voltage source. At present, each of the above functions is performed using a separate binary or polynomial counter. Though widely adopted, such an approach involves considerable expenditure in terms of layout for forming the counters, and, what is more, in terms of test time, by virtue of all the counters having to be tested singly, preferably by scanning all the possible configurations involved. A count unit according to the preamble of claim 1 and as disclosed in FR-A-2 606 183, is intended for a multitasking or multiprocessing systems and comprises a plurality of registers connected to a shared counter. The known count unit is not intended for use in a nonvolatile memory and does not disclose in detail the way the storage elements of the registers are controlled for loading the data in the shared counter elements of the shared counter and storing data from the shared counter elements after the counting step. It is an object of the present invention to provide a count unit designed to overcome the aforementioned drawbacks. According to the present invention, there are provided a count unit for nonvolatile memories as claimed in Claim 1. A preferred non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of the unit according to the present invention; Figure 2 shows a detail of Figure 1; Figure 3 shows a diagram of the circuit by which the single control steps of the Figure 1 blocks are generated. Figure 1 shows part of an N-bit count unit implementing four count functions and indicated as a whole by 1. As the cells all present the same structure and are provided according to the maximum number of bits of the count functions, Figure 1 shows only three cells 2 0 , 2 1 , 2 2 of unit 1, each corresponding to one bit. In the example shown, unit 1 performs four count functions, indicated SV, ST, SP, SA in Figure 3, but may implement any number of count functions by providing an appropriate number of individual cell components, as explained later on. As shown in Figure 1, each cell 2 i , where i = 0...2, presents a number of input/output terminals at which is present a corresponding number of signals referred to generally by the same name as the corresponding terminal, with the exception of those indicated below. More specifically, each cell 2 i presents an external data (initialization) input ADDR connected to an external bus 3; a CK input supplied with a clock signal; a TOGIN input explained later on; a carry bit input DAIN; inputs ALE, LDA, STA, STAR, LDT, STT, LDP, STP, LDV, STV supplied with signals of the same name as explained later on; a reset input RES; data outputs AX i , TX i , PX i , VX i ; a carry bit output DAOUT; and a carry signal output TOGOUT. The TOGIN input of cell 2 0 is supplied with a CINCROW signal for incrementing a given count content, as explained later on; while the TOGOUT output of each cell 2 i is connected to the TOGIN input of a higher-order cell 2 i+1 . Similarly, the DAIN input of cell 2 0 is connected to a reference potential line V DD , and the DAOUT output of each cell 2 i is connected to the DAIN input of a higher-order cell 2 i+1 . In general, each cell also comprises further inputs and/or outputs, e.g. for supplying signals inverted in relation to those shown, or for other functions extraneous to the present invention and therefore not shown. Figure 2 shows the structure of a generic cell 2 i in the case of a count unit according to the present invention implementing four count functions as indicated. As shown in Figure 2, each cell 2 i comprises a counter element 8, and four register elements, all relative to one bit. Of the four register elements, three, indicated by 9, are identical, while the fourth, indicated by 10, is more complex and provides for externally loading an initial configuration. Register elements 9, 10 are parallel connected to a data (bit) input line 11 and a data (bit) output line 12. More specifically, each register element 9, 10 presents an input INC connected to line 11, and an output OUT1 connected to line 12. Lines 11, 12 are connected respectively to the DAOUT output and IN input of counter element 8, and represent local buses. Register elements 9, 10 each present two inputs L and S supplied with specific load and store signals LDA, STA, LDP, STP, LDT, STT, LDV, STV; and an output OUT at which the stored bit is supplied - signal AX, PX, TX, VX. Register element 10 also comprises a further three inputs ADDR, ALE, STAR which are supplied with corresponding data and signals for externally loading an initial bit (one for each cell). More specifically, ADDR specifies the bit to be loaded; ALE controls storage of the external bit; and STAR controls a switch (not shown) for holding the data (in the absence of storage instructions from the counter or externally). Counter element 8 presents the DAIN, RES, CK and TOGIN inputs already described with reference to Figure 1; an IN input connected to line 12; a DAOUT output connected to line 11 (and the higher-order cells, as shown in Figure 1); and a TOGOUT output connected to the higher-order cells (Figure 1). The internal structure of register elements 9, 10 and counter element 8 may be designed in various ways and, not being the object of the present invention, is therefore not shown in detail. Typically, register elements 9 may be composed of known D-latch circuits, and register element 10 substantially in the same way, but with the addition of the INA input controlled by the ALE signal. Counter element 8 forms part of a binary counter which may be in the form of a ripple or advance carry counter or any other type of counter, and which represents an arithmetical-logic unit (ALU) with a minimum operation set including incrementation of the stored value (TOGIN = 1), reset (RES = 0) and no operation (TOGIN = 0). The steps relative to each register are conveniently generated from general load and store instructions and address signals, e.g. by means of a logic circuit of the type shown in Figure 3. In Figure 3, the circuit by which the control steps of register elements 9, 10 are generated is indicated as a whole by 15, and comprises a number of NAND circuits 16 with three inputs supplied respectively with clock signal CK, a register store signal STO, and one of four address signals (SA for register element 10, and SP, ST and SV for each of register elements 9); and a further number of NAND circuits 17 with three inputs supplied respectively with clock signal CK, counter load signal LD, and one of address signals SA, SP, ST and SV. The output of each NAND circuit 16, 17 is connected to an inverter 18, 19, the output of which presents a respective control signal for each register, which is supplied to all the cells 2 i in Figure 1. Circuit 15 also comprises a further NAND circuit 20, one input of which is connected to the output of the NAND circuit 16 generating the inverse of signal STA, and the other input of which is connected to the output of an inverter 21 supplied with external load signal ALE. The count unit described above operates as follows. The register to be altered is specified externally by generating a sequence such as LD-CINCROW (or RES)-STO and the address SA, SP, ST or SV of the register in question. As a result, the data contained in the relative register element 9, 10 of all of cells 2 i is loaded into respective counter element 8 over line 12; and the respective bit is incremented (possibly repeatedly throughout the time available) or erased, and back-stored in the same register element over line 11. For externally loading a data into a given register, register element 10 is employed, for which purpose, the ALE signal is supplied externally, and the data over line 3. In this way, the single bits of the data are loaded into register elements 10 and possibly transferred, by means of load signal LDA, to respective counters 8 where they may be modified using the available operators (increment and reset) and finally re-transferred by means of storage signal STA, STP, STT, STV to the respective register. The advantages of the unit according to the present invention are the following. Firstly, it provides for a reduction in the number of components used, in direct proportion to the number of count functions involved. In fact, a counter always requires master-slave control of its registers, whereas a simple storage register may be a D-latch type if loading may be carried out on one level and does not require loading at a switching edge of the clock signal. Consequently, considering that, in CMOS technology, a master-slave circuit requires two D-latch circuits, M binary counters of N bits require M*2*N D-latch cells (plus the carry generating logics). According to the present invention, on the other hand, the same number of count functions require 2*N counters and M*N registers, i.e. a total of 2*N+M+N=N(M+2) which, for M>2, means a saving in the number of latches required. Moreover, both the incrementing and reset operations require additional circuitry (carry propagating and reset logics) which in this case are provided only once on the counter. As the various count functions may not require the same number of counter bits, cells 2 i containing varying numbers of register elements 9 may be constructed so as to form a structure with as many cells as the bits in the longest count function. In this case, the lower-order cells (equal in number to the bits in the shortest count function) will contain all the registers, while those of increasingly higher order will contain increasingly fewer registers, thus enabling optimization of the overall size of the count function. Checking or testing the count functions is simplified greatly by being limited to only one binary counter per cell; and may be further simplified by the possibility of loading counters 8 of unit 1 with a random or specific configuration with which to check the performance of the counters in particular situations, e.g. when the carry is generated. This provides for a drastic reduction in test time by eliminating the need to perform 2 N incrementing steps (corresponding to 2 N stroke of the clock) to test operation of an N-order counter. Moreover, the buses between each counter element 8 and respective register elements 9, 10 are local, and the carry is propagated between adjacent cells 2 i , thus reducing the layout requirement for the connecting lines. Appropriate solutions may be devised for compensating for the greater complexity of the count instructions (which, as opposed to a simple incrementing signal, require a succession of loading, incrementing and re-storage signals). For example, said succession may be generated as a subroutine of the state machine (possibly exploiting the architecture of the machine itself) or with the aid of simple dedicated logics external to the state machine and capable of producing the desired sequence from an enabling signal, which involves very little expenditure in terms of layout. Whichever the case, the availability of the three loading, incrementing and storage signals provides for greatly enhanced testing as described above. It will be clear that changes may be made to the unit as described and illustrated herein without, however, departing from the scope of the present invention. For example, any suitable type of register may be employed; and the type of counter may also differ, though, in the case of flash type nonvolatile memory applications, it must be a binary and cannot be a polynomial type, by virtue of address scanning requiring an orderly as opposed to pseudo-random progression to conform with certain data programming and check strategies typical of this type of memory. At any rate, even in the event of applications involving other types of memories not requiring the above type of address scanning, any effort to improve layout would be defeated by a nonbinary structure in the case of different count modules involving different feedback logics. Moreover, the instructions implemented may be so integrated as to take into account the requirements of particular applications, or modified to meet specific requirements. For example, reset signal RES may be replaced by a system of reset signals for selectively resetting the counter so that only some of the counter bits are reset, leaving the others unchanged. This may be useful for example in the case of a flash type memory in which, at present, the address register contains row address bits and others column address bits, the value of some of which also identifies the selected array sector. It is useful therefore to dispose of a selective reset for the row or column identification bits, and for the row and column bits not identifying the sector.

Claims: An n-bit count unit having a counter for performing a predetermined number of count functions and having a plurality of registers corresponding in number to said plurality of count functions, said counter being a shared counter for said registers in that each of said registers is for storing a counted value of said shared counter according to one of said count functions, said shared counter being composed of n shared counter elements and each of said registers being composed of n storage elements, characterised in that said count unit is provided for nonvolatile memories and comprises n counting cells (2 0 ,..,2 n ), each counting cell (2 i ) comprising a number of said storage elements (9,10) equal in number to said predetermined number of count functions; one of said shared counter elements (8); means (11, 12) for connecting said number of storage elements and said shared counter element; and control means (15, CK, TOGIN, DAIN, RES, ADDR) connected to said number of storage elements and said shared counter element, for transferring stored data to be updated from at least one given of said number of storage elements (9, 10) to said shared counter element (8) according to a predetermined count function, and for transferring updated data to be stored from said shared counter element to said at least one given of said number of storage elements in that each said storage element (9, 10) comprises a first and a second control input (L, S); and in that said control means comprises load generating means (17) connected to said first control input (L) of said storage elements for generating a selective load signal; operating signal input means (CK, TOGIN, DAIN, RES) connected to said shared counter element (8); and storage generating means (16) connected to said second control input (S) of said storage elements for generating a selective storage signal. A unit as claimed in Claim 1, characterized by the fact that each said storage element (9, 10) comprises at least a first data input (INC), and a first data output (OUT1); and by the fact that said connecting means comprise a first connecting line (11) interposed between an output of said shared counter element (8) and said first data input of said storage elements; and a second connecting line (12) interposed between said first data output of said storage elements and an input of said shared counter element. A unit as claimed in Claim 1 or 2, characterized in that said operating signal input means comprise a first input element (TOGIN) for an incrementing signal (CINCROW), and a second input element for a reset signal (RES). A unit as claimed in Claim 1 or 2 or 3, characterized in that said load generating means comprise a first number of logic circuits (17) equal in number to said predetermined number of count functions and connected to a load control line (LD) and to address lines (ST, SV, SP, SA); and in that said storage generating means comprise a second number of logic circuits (16) equal in number to said predetermined number of count functions and connected to a storage control line (STO) and to said address lines. A unit as claimed in any one of the foregoing Claims, characterized in that at least one of said storage elements (10) comprises a second data input (ADDR) and a third control input (ALE) for receiving external initializing data. A unit as claimed in Claim 5, characterized in that said control means comprise initializing generating means (20) connected to said at least one storage element (10) for generating a parallel storage signal. A unit as claimed in any one of the foregoing Claims, characterized in that each said storage element (9, 10) comprises a second data output (OUT) connected to output terminals of said count unit (1). A unit as claimed in any one of the foregoing Claims, characterized in that said storage elements (9, 10) form a D-latch register. A unit as claimed in any one of the foregoing Claims, characterized in that said counter element (8) is a binary counter. A unit as claimed in any one of the foregoing Claims, characterized in that each of said counting cells (2 i ) is of a given rank, cascade connected to one another, and each relative to a data portion of different rank.

Inventors: MACCARRONE MARCO, OLIVO MARCO, MACCARRONE, MARCO, OLIVO, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C11
IPC codes: H03K21, G11C16, G11C8