Current sense circuit

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Description: BACKGROUND OF THE INVENTION This invention relates to an improved sense circuit capable of sensing a small input current signal and producing a large voltage output swing and to a novel negative-resistance circuit. The well-known advantage of using current signals with small voltage swings in integrated circuits is that these signals can be transmitted quickly over long interconnecting lines. In a read-only memory (ROM), static random-access memory (SRAM), or dynamic random-access memory (DRAM), for example, current signals can be used for rapid transfer of data over data lines. Sense circuits must then convert the data signals from current to voltage form in order to drive transistors, and to enable the memory device to output the data in a standard voltage-signal mode. A conventional sense circuit of this type comprises the following elements coupled in series between a power-supply terminal and ground: a first resistance, an input terminal, a transistor, an output terminal, and a second resistance. The transistor is controlled by an amplifier that receives input from the output terminal, creating a positive feedback loop. Positive feedback enables a small change in current at the input terminal to produce a large voltage change at the output terminal. Fig. 1 shows part of a DRAM using this conventional sense circuit. The symbols V CC and GND indicate the power-supply potential and ground, respectively. The switching circuit 1 is one of a large number of similar switching circuits coupled to a data line DL, which feeds the input terminal IN of a sense circuit 2. The output terminal OUT of the sense circuit 2 is coupled to a next-stage differential voltage amplifier (not shown in the drawing). The switching circuit 1 comprises n-channel metal-oxide-semiconductor field-effect transistors (hereinafter, N-MOSFETs) 1a and 1b coupled in series between data line DL and ground. The gate of N-MOSFET 1a is coupled to a column select line CL; the gate of N-MOSFET 1b is coupled to a bit line BL. The sense circuit 2 has been divided for explanatory purposes into three blocks: a data-line load circuit 3, a current-to-voltage converter 4, and an inverting amplifier 5. In the load circuit 3, a p-channel metal-oxide-semiconductor field-effect transistor (hereinafter, P-MOSFET) 3a with its gate coupled to ground provides a load resistance between V CC and the input terminal IN. In the current-to-voltage converter 4, a P-MOSFET 4a and N-MOSFET 4b are coupled in series between the input terminal IN and ground. The drain of P-MOSFET 4a, the drain and gate of N-MOSFET 4b, and the output terminal OUT are coupled at a node N 1 . The N-MOSFET 4b provides a current-sensing resistance between node N 1 and ground. The gate of P-MOSFET 4a is coupled to a node N 2 . The inverting amplifier 5 has an input node A in coupled to node N 1 and an output node A out coupled to node N 2 , and comprises a P-MOSFET 5a and N-MOSFET 5b coupled in series between V CC and ground. The gate and drain of P-MOSFET 5a are coupled to the output node A out . The drain of N-MOSFET 5b is coupled to the output node A out , and its gate is coupled to the input node A in . During normal operation, the data line DL is biased to a potential near V CC , the potential being controlled by the current flow through the load P-MOSFET 3a. A certain bias current I flows from V CC through the load circuit 3 to the current-to-voltage converter 4. Little or no current flows between the load circuit 3 and data line DL. If read access results in activation of CL and BL, turning on transistors 1a and 1b in the switching circuit 1, then some of this bias current I is diverted from the current-to-voltage converter 4 to the data line DL. The resulting reduction -ΔI in current flow through the current-to-voltage converter 4 reduces the potential at node N 1 , so the potential at the input terminal A in of the Inverting amplifier 5 falls. The potential at the output terminal A out (node N 2 ) therefore rises, reducing the conductance of P-MOSFET 4a. Current flow through the current-to-voltage converter 4 is thereby reduced still further, setting up positive feedback that quickly produces a large voltage swing at the output terminal OUT. The reduction in current flow through the current-to-voltage converter 4 is partly balanced by the increased current flow on the data line DL, so the change in the current flowing through the load circuit 3 is small. The change in potential at the input terminal IN is therefore slight; the voltage swing on the data line DL is kept small. Ideally, the current increase ΔI on the data line DL equals the current decrease -ΔI in the current-to-voltage converter 4, as shown in Fig. 1, in which case a large output voltage swing is obtained with no voltage swing on the data line LD. The conventional sense circuit 2, however, is not ideal. It has problems from the standpoints of both design and operation, as discussed next. One problem arises from the similarity between the left side of the circuit, comprising the load 3 and current-to-voltage converter 4 and denoted as circuit A in Fig. 1, and the right side, comprising the inverting amplifier 5 and denoted as circuit B. Circuit B has A in is its input and A out as its output. The input-output characteristic of circuit B is such that the potential at A out falls when the potential at A in rises, and the potential at A out rises when the potential at A in falls. Circuit A can be viewed as having node N 2 as its input and node N 1 as its output. Circuit A then has a similar input-output characteristic: the potential at node N 1 falls when the potential at node N 2 rises, and rises when the potential at node N 2 falls. Circuit A and circuit B are cross-coupled: the input node of each is coupled to the output node of the other. They therefore operate at a point where their input-output characteristics intersect, but due to the similarity of their characteristics, the point of intersection may not be uniquely defined. This can cause the sense circuit 2 to oscillate between two operating points. The cross-coupled configuration in Fig. 1 is furthermore similar to the configuration of a latch comprising two inverters coupled in a loop. The sense circuit 2 has a corresponding tendency to latch up, remaining in the high or low output state regardless of changes in current at the input terminal IN. Another problem is that a large output voltage swing at the output terminal OUT entails a large swing at the input node A in of the inverting amplifier 5, hence at its output node A out , increasing the gain of the positive-feedback loop. The output voltage swing accordingly cannot be designed independently of the loop gain; the one depends on the other. A further problem with the conventional sense circuit 2 becomes evident when it is used in a DRAM having a page mode, in which a word line remains active while memory cells in different columns on that word line are accessed. During such page access, at first the voltage swings on the bit lines are small, and only slight changes occurs in the current flowing on the data line DL. As access to the same word line continues, however, the voltage swings on the bit lines increase, with corresponding larger changes in current flow on the data line DL. If the load P-MOSFET 3a is designed for reliable sensing of small current changes on data line DL, then when the current changes become larger, P-MOSFET 3a may begin to saturate, allowing unwanted large potential changes on data line DL. That is, the sense circuit 2 has inadequate dynamic range for page-mode operation in a DRAM. The dynamic range can be widened by using an N-MOSFET with interconnected gate and drain as the load transistor. If this type of load is employed, however, it becomes impossible to bias the data line DL close to V CC . This leads to problems regarding operating speed and operating margin, particularly at low supply voltages, From US-A-4 758 749 a current sense amplifier using N-channel transistors is known. An input terminal is directly coupled to the gate of a first transistor which operates as a high gain inverter. A depletion load transistor develops a signal resulting from the current flow in the first transistor. The drain of the first transistor is directly coupled to the gate of a still further transistor, the source of which is coupled back to the input terminal. This circuit configuration produces a high gain negative feedback loop around the input terminal, the voltage of which is stablized at close to the threshold of the first transistor. SUMMARY OF THE INVENTION One object of the present invention is accordingly to provide a sense circuit suitable for operation at low supply voltages. Another object is to provide a sense circuit with stable operation. Yet another object is to provide a sense circuit with a wide dynamic range. Still another object is to provide a sense circuit with high gain. Yet another object is to provide a sense circuit with a simple configuration. Still another object is to provide a sense circuit that can be easily fabricated. Yet another object is to provide a sense circuit with independently designable loop gain and output swing. A first aspect of the invention is defined in claim 1. A second aspect of the invention is defined by claim 5. According to a further aspect of the invention, an inverting amplifier comprises an input node, an output node, a negative-resistance circuit that provides a variable negative resistance between the output node and a fixed potential, responsive to the potential of the input node, and a resistance circuit coupled between the output node and a second fixed potential. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a conventional sense circuit. Fig. 2 is a schematic diagram of a first sense circuit. Fig. 3 is a schematic diagram of a second sense circuit. Fig. 4 illustrates input-output characteristics of circuit A and circuit B in Figs. 2 and 3. Fig. 5 is a schematic diagram of a third sense circuit. Fig. 6 is a schematic diagram of a fourth sense circuit. Fig. 7 illustrates the load curve of the load circuit in Fig. 6. Fig. 8 is a schematic diagram of a fifth sense circuit. Fig. 9 illustrates volt-ampere characteristics of various transistors in Fig. 8. Fig. 10 is a schematic diagram of a sense circuit of a first embodiment according to the invention. Fig. 11 illustrates volt-ampere characteristics of the negative-resistance circuit and resistance circuit in the amplifier of Fig. 10. Fig. 12 is a redrawing of the amplifier circuit in Fig. 10. Fig. 13 illustrates input-output characteristics of circuit A and circuit B in Fig. 12. Fig. 14 is a schematic diagram of a sense circuit of a second embodiment according to the invention. Fig. 15 illustrates a modification of the amplifier circuit in Fig. 8. Fig. 16 illustrates a modification of the amplifier circuit in 15, identical to the amplifier circuit in Fig. 14. Fig. 17 is a schematic diagram of a resistance circuit. Fig. 18 is a schematic diagram of a negative-resistance circuit. Fig. 19 is another schematic diagram of the negative-resistance circuit of Fig. 24, illustrating currents and potentials. Fig. 20 illustrates volt-ampere characteristics of transistors in Figs. 18 and 19. Fig. 21 illustrates a volt-ampere characteristic of the negative-resistance circuit in Figs. 18 and 19. Fig. 22 illustrates further volt-ampere characteristics of the negative-resistance circuit in Figs. 18 and 19. Fig. 23 illustrates a modification of the negative-resistance circuit in Fig. 18. Fig. 24 illustrates another modification of the negative-resistance circuit in Fig. 18. DETAILED DESCRIPTION OF THE INVENTION Embodiments of the invention will be described with reference to the attached illustrative drawings. These drawings do not restrict the scope of the invention. In the discussions of circuit characteristics, it will be assumed unless otherwise stated that N-MOSFETs are formed in a grounded substrate, and P-MOSFETs in a substrate biased at V CC , as is customary in complementary metal-oxide-semiconductor (CMOS) circuits. All transistors will be enhancement-mode MOSFETs unless otherwise noted. V TNN will denote the threshold gate-source voltage of an N-MOSFET with arbitrary source potential; V TN will denote the threshold gate-source voltage when the source is grounded. Assuming a grounded substrate, if the source potential is higher than ground, then V TNN > V TN . Similarly, V TPP will denote the (negative) threshold gate-source voltage of a P-MOSFET with arbitrary source potential, and V TP the threshold gate-source voltage when the source is coupled to V CC . Assuming a substrate biased at V CC , if the source potential is less than V CC , then |V TPP | > |V TP |. In CMOS circuits V TN and |V TP | are usually substantially equal. This also will be assumed. 1st example Fig. 2 shows a sense circuit The input terminal IN of this sense circuit is coupled to a node N 11 . A resistive load circuit 10 is coupled between node N 11 and V CC . A current-to-voltage converter 12 is coupled between node N 11 and ground. The current-to-voltage converter 12 comprises a P-MOSFET 14 and a resistance circuit 16 coupled in series. The source of P-MOSFET 14 is coupled to node N 11 , its gate is coupled to a node N 12 , and its drain is coupled to one end of the resistance circuit 16 and to the output terminal OUT of the sense circuit. The other end of the resistance circuit 16 is coupled to ground. Nodes N 11 and N 12 are coupled to the input node A in and output node A out , respectively, of an inverting amplifier 18. The inverting amplifier 18 comprises a depletion-mode P-MOSFET 20 coupled in series with a resistance circuit 22. The source of the depletion-mode P-MOSFET 20 is coupled to V CC , its gate is coupled to the input node A in , and its drain is coupled to one end of the resistance circuit 22 and to the output node A out . The other end of the resistance circuit 22 is coupled to ground. Next the operation of this sense circuit will be described. Depending on other external circuits (not shown) to which the sense circuit is connected, under normal conditions a small (possibly zero) bias current I 1 will flow in or out at the input terminal IN. In the drawing, the input terminal IN is considered to be a current source with respect to external circuits, I 1 flowing outward. If the flow is actually inward, then I 1 is negative. The sense circuit and its connected circuits are preferably designed so that under normal conditions, input terminal IN is biased at a potential close to V CC . This can be done, for example, by providing P-MOSFET 14 and resistance circuit 16 with sufficiently high resistance values. A second bias current I 2 flows from the data-line load circuit 10 to the current-to-voltage converter 12. P-MOSFET 14 is designed to saturate under normal operating conditions, making I 2 dependent on the gate-source voltage rather than the drain-source voltage of P-MOSFET 14. The potential of the input terminal IN depends on the total current flow (I 1 + I 2 ) through the load circuit 10. Suppose now that a current signal is received at input terminal IN, causing the current I 1 to increase by ΔI 1 . The increased current produces a greater voltage drop across the load circuit 10, so the potential of input terminal IN (and of node N 11 ) decreases slightly. This decrease is inverted and amplified by the inverting amplifier 18, raising the level of node N 12 . Since the source potential of P-MOSFET 14 has fallen and its gate potential has risen, its gate-source voltage is reduced in absolute value. The reduced gate-source voltage produces a corresponding reduction in the conductance of P-MOSFET 14. The current I 2 flowing through the current-to-voltage converter 12 decreases by an amount ΔI 2 . The result is a potential change of -ΔI 2 ·R at output terminal OUT, where R is the resistance value of the resistance circuit 16. A desired output voltage swing can be obtained by suitable selection of R. The sense circuit can be designed so that ▵I 1 and ▵I 2 are substantially equal, in which case the net change in current flow through the load circuit 10 is approximately zero. The potential of input terminal IN then remains substantially fixed. An output signal with a large voltage swing can accordingly be obtained from an input current signal while causing only a slight voltage swing at the input terminal IN. This sense circuit is well suited for use at a low supply voltage V CC . One reason is that the depletion-mode P-MOSFET 20 conducts even when its gate potential is V CC . This enables the input terminal IN to be biased at a level arbitrarily close to V CC without forcing the inverting amplifier 18 into cut-off. A potential close to V CC can therefore be applied to the current-to-voltage converter 12, providing adequate operating speed and margin even if V CC is low. Because the input node A in of the inverting amplifier 18 is coupled to the input terminal IN instead of the output terminal OUT, the sense circuit also excels in stability of operation. In particular, it has no positive feedback loops, hence no tendency to latch up. Feedback exists between nodes N 11 and N 12 , but this feedback loop is negative; it tends to steady the potentials of these nodes. Further details will be shown in Fig. 4. The circuit parameters are also easy to design. To adjust the output voltage swing, it suffices to adjust the resistance value of the resistance circuit 16. To adjust the loop gain between nodes N 11 and N 12 , it suffices to adjust the gain of the inverting amplifier 18, or adjust the saturation of P-MOSFET 14 by altering the bias potential of its gate. A particular advantage is that the loop gain and output voltage swing can be adjusted independently. 2nd example This example, shown in Fig. 3, is a more specific implementation of the first example. The load circuit 10 now comprises a P-MOSFET 24 with grounded gate. The resistance circuit in the current-to-voltage converter 12 comprises an N-MOSFET 26 with interconnected gate and drain. The resistance circuit in the inverting amplifier 18 comprises an N-MOSFET 28 with interconnected gate and drain. Otherwise, the configuration is the same as in Fig. 2, and the same reference numerals are employed. An advantage of the circuit configuration of Fig. 3 is that use of the N-MOSFET 28 with interconnected gate and drain as the resistance element in the inverting amplifier 18 restricts the voltage swing at the amplifier output node A out . This reduces the loop gain, but provides a wider dynamic range, enabling greater potential fluctuations to be tolerated at the input terminal IN while keeping P-MOSFET 14 in saturation. Since the second example is an instance of the first example, it inherits the advantages noted in the first example: suitability for use at low supply voltages, independent adjustability of the output voltage swing and loop gain, and stability of operation. Stability will now be described in more detail. In Figs. 2 and 3, the sense circuit can be divided into a circuit A, consisting of the load circuit 10 and current-to-voltage converter 12, and a circuit B, consisting of the inverting amplifier 18. Circuit A can be regarded as having node N 11 as its input and node N 12 as its output, while circuit B has A in as its input and A out as its output. Circuits A and B are mutually cross-coupled; the input of each is coupled to the output of the other. Fig. 4 is a diagram of the input-output voltage characteristics of circuits A and B. The horizontal axis indicates the potential of node N 12 (A out ), which is the input node of circuit A and the output node of circuit B. The vertical axis indicates the potential of node N 11 (A in ), which is the output node of circuit A and the input node of circuit B. Curve C A is the input-output characteristic of circuit A; curve C B is the input-output characteristic of circuit B. Circuit A operates as a source-follower: as its input potential at node N 12 rises, its output potential at node N 11 also rises. Circuit B is an inverting amplifier: as its input potential at node A in rises, its output potential at node A out V falls. Accordingly, characteristic curves C A and C B are oriented in substantially perpendicular directions and intersect at a single operating point P. Since only a single operating point P exists, an extremely stable circuit is obtained, with no tendency to oscillate. 3rd example This example, shown in Fig. 5, is another implementation of the first example, and is identical to the second example except for the configuration of the inverting amplifier 30. Elements common to Figs. 2 and 3 have the same reference numerals. The inverting amplifier 30 in Fig. 5 differs from the inverting amplifier 18 in Fig. 3 in that the gate of N-MOSFET 28 is coupled to input node A in , instead of to the drain of N-MOSFET 28. Otherwise, the circuit configuration is the same as Fig. 3. By coupling the gate of N-MOSFET 28 to the amplifier input node A in , this example increases the gain of the inverting amplifier 30. The loop gain of the sense circuit is therefore improved, although its dynamic range is somewhat narrowed. This example is basically similar in operation to the first and second examples, and provides similar advantages, so further details will be omitted. 4th example This example is illustrated in Fig. 6. Elements common to Figs. 2, 3, and 5 have the same reference numerals. This sense circuit comprises a load circuit 32, and the same current-to-voltage converter 12 and inverting amplifier 18 (now indicated by a single symbol) as in Fig. 2. Its basic operation is the same as in the first three examples. A description of the identical circuit elements and the basic operation will be omitted in order to concentrate on the characteristics of the load circuit 32. The load circuit 32 comprises a P-MOSFET 24 coupled between V CC and a load input node L in , which is coupled to node N 11 . The gate of P-MOSFET 24 is coupled through a level shifter 34 to the same node L in . The level shifter 34 receives an input potential from node L in , shifts this potential downward by an amount V SHF , and provides the down-shifted potential as output to the gate of P-MOSFET 24. The absolute value |V SHF | of the shift should be greater than |V TP |, so that the input terminal IN and node L in can be biased close to V CC without cutting off current flow through P-MOSFET 24. When the input potential is |V SHF |, the output potential of the level shifter is substantially zero volts. Beyond this point the output potential remains substantially constant, because the level shifter 34 cannot generate output potentials below the ground potential. Fig. 7 shows the volt-ampere load curve of the load circuit 32. The horizontal axis in indicates the potential of input node L in , denoted V LIN ; the vertical axis indicates current flowing through P-MOSFET 24 from V CC to node L in . The solid curve L 1 is the actual load curve of the load circuit 32. The dotted curves L 2 and L 3 are added for explanation: curve L 2 is the load curve if the gate potential V G of P-MOSFET 24 is held at its maximum attainable value of V CC - V SHF ; curve L 3 is the load curve if the gate of P-MOSFET 24 is grounded (V G = 0 V). Curve L 3 is therefore the load curve of the load circuit 10 in Figs. 3 and 5. Around V LIN = V CC , the gate potential V G of P-MOSFET 24 is near V CC - V SHF , and curve L 1 is close to curve L 2 . At a point where V LIN = V SHF , since V G = 0, curve L 1 merges with curve L 3 . Between these two values, curve L 1 is substantially linear. It can be seen that curve L 1 remains linear down to smaller values of V LIN than does curve L 2 . As a whole, the load circuit 32 behaves like a P-MOSFET with an expanded triode region and a reduced saturation region. Compared with the load circuit 10 in Figs. 3 and 5, and with the prior art shown in Fig. 1, if all these load circuits are designed to begin saturating at equal current values, the load circuit 32 of the fourth example has a higher equivalent resistance value. That is, given the same maximum allowable current swing, the circuit in Fig. 6 can sense small current signals more reliably. Alternative, for a given equivalent resistance value, the load circuit 32 in Fig. 6 can tolerate greater current and voltage swings before saturation of characteristics begins. In short, the fourth example has a wider dynamic range. The load circuit 32 in Fig. 6 is applicable not only to sense circuits; it is also effective when used as a load in various other circuits that require volt-ampere characteristics with improved linearity. 5th example This example, shown in Fig. 8, is similar to the fourth example, except that the level shifter is now disposed in the amplifier circuit. Elements common to Figs. 2, 3, 5, and 6 have the same reference numerals. This sense circuit comprises a load circuit 35 with a P-MOSFET 24, a current-to-voltage converter 12 as in Fig. 2, and an amplifier circuit 36. The amplifier circuit 36 has an input node A in coupled to the input terminal IN, a first output node A out1 coupled to the gate of P-MOSFET 14, and a second output node A out2 coupled to the gate of P-MOSFET 24. This amplifier circuit 36 implements the level shifter 34 and inverting amplifier 18 of Fig. 6 in a single circuit, comprising a depletion-mode P-MOSFET 38 with gate coupled to input node A in , an N-MOSFET 40 with gate likewise coupled to input node A in , and a current mirror 42 consisting of N-MOSFETs 46 and 48. The source of the depletion-mode P-MOSFET 38 is coupled to V CC . Its drain is coupled to a current input node I in of the current mirror 42, and to the first output node A out1 . The drain of N-MOSFET 40 is coupled to V CC , and its source is coupled to a current output node I out of the current mirror 42 and to the second output node A out2 . The sources of the N-MOSFETs 46 and 48 in the current mirror 42 are coupled to ground. Their gates are coupled to the first output node A out1 , and to the current input node I in . The drain of N-MOSFET 46 is coupled to the current input node I in . The drain of N-MOSFET 48 is coupled to the current output node I out . N-MOSFETs 46 and 48 are designed to saturate when the input potential at input node A in is near V CC , so that current flow through them is controlled by their gate potential. Descriptions will next be given of (1) the output potential at the first output node A out1 , (2) the output potential at the second output node A out2 , and (3) the operation and advantages of this sense circuit. (1) Output potential at A out1 An inverting amplifier comprising the depletion-mode P-MOSFET 38 and N-MOSFET 46 is coupled between input node A in and the first output node A out1 . This part has the same structure as the inverting amplifier 18 in Fig. 3. The potential at input node A in (the potential at input terminal IN) is inverted, amplified, and output to output node A out1 . (2) Output potential at A out2 Fig. 9 is a volt-ampere diagram for describing the operation of output node A out2 in Fig. 8. Current is indicated on the vertical axis and voltage on the horizontal axis. It is assumed that N-MOSFETs 46 and 48 in the current mirror 42 have equal current-driving capabilities. Curves C Na and C Nb are volt-ampere characteristics of the N-MOSFET 40 when its gate is biased at two potentials V a and V b , with V a > V b . V a and V b are potentials of input node A in . For these two curves, the horizontal axis represents the source potential of N-MOSFET 40 (the potential of output node A out2 ). On curve C Na , current begins to flow when the source potential of N-MOSFET 40 is V a - V TNN , and the current increases as this potential decreases. Current flow on curve C Nb begins when the source potential of N-MOSFET 40 is V b - V TNN . Curves L a and L b are corresponding volt-ampere characteristics of N-MOSFET 48 when the potential of input node A in is V a and V b , respectively. For these two curves also, the horizontal axis represents the potential of output node A out2 . As the potential at A in rises, the gate potential of N-MOSFET 48 falls, so curve L a shows less current flow than curve L b . Curve C b is the volt-ampere characteristic of P-MOSFET 38. For this curve, the horizontal axis represents the potential of input node A in , e.g. V a or V b . On the vertical axis, I a is the current flowing through P-MOSFET 38 when the potential of input node A in is V a . This current I a must also flow through N-MOSFET 46 and, since N-MOSFETs 46 and 48 constitute a current mirror 42, through N-MOSFET 48. The characteristic curve L a of N-MOSFET 48 and the characteristic curve C Na of N-MOSFET 40 must therefore intersect at a point P a where the current value is I a . This point P a is the operating point of output node A out2 when the potential of input node A in is V a . The voltage value V outa of the operating point P a is the potential of the output node A out2 . Similarly, I b is the current flowing through P-MOSFET 38 when the potential of input node A in is V b . Curves L b and C Nb must intersect at a point P b where the current value is I b , and the voltage value V outb of this point P b becomes the potential of the output node A out2 . From Fig. 9 it can be seen that the input voltage at A in is shifted down at output terminal A out2 (V outa < V a and V outb < V b ). The input voltage swing V a - V b is also amplified ( V outa - V outb > V a - V b ). Amplification occurs only if the input potential at A in is close enough to V CC for N-MOSFET 48 to be saturated, but this is not a serious restriction, because the circuit is intended for use at input potentials close to V CC . In a conventional level shifter, N-MOSFET 48 is replaced by a constant-current source providing a current I a . When the potential of input node A in is V a , the operating point is still P a and the potential of output node A out2 is V outa , but when the potential of input node A in is V b , the operating point becomes P bb , and the potential of output node A out2 becomes V outbb . The output voltage swing V outa - V outbb is less than V outa - V outb . For signals with the same input voltage swing, the amplifier circuit 36 of this example produces a shifted output potential having a larger output swing than would a conventional level shifter. (3) Operation and advantages of sense circuit Basically, the fifth example operates as did the fourth, with the amplifier circuit 36 in Fig. 8 performing the functions of both the inverting amplifier 18 and level shifter 34 in Fig. 6. The only difference is the greater voltage swing obtained at output node A out2 in Fig. 8. This enables the sense circuit to tolerate lower voltages and higher currents at the input terminal IN without saturation of P-MOSFET 24; that is, the fifth example has an even wider dynamic range than the fourth example. Incorporation of the shifting function into the amplifier circuit 36 also enables the sense circuit to be configured with fewer circuit elements than the circuit in Fig. 6. Applications of the amplifier circuit 36 of this example are not restricted to use in sense circuits. It is effective if used as a level shifter in a variety of situations requiring amplified, shifted output: for example, in interface circuits or the like. 1st embodiment of the invention Fig. 10 shows a first embodiment of the invented sense circuit. Elements common to Fig. 2 have the same reference numerals. This sense circuit comprises the same load circuit 10 and current-to-voltage converter 12 as in Fig. 2, and an inverting amplifier 50 with a structure differing from Fig. 2. The inverting amplifier 50 has an input node A in coupled to the input terminal IN and an output node A out coupled to the gate of P-MOSFET 14, and comprises a resistance circuit 22 and a novel negative-resistance circuit 52. The negative-resistance circuit 52 has a control terminal G and input/output terminals S and D, the control terminal G being coupled to input node A in , the first input/output terminal S to V CC , and the second input/output terminal D to one end of the resistance circuit 22 and to the output node A out . The other end of the resistance circuit 22 is coupled to ground. The negative-resistance circuit 52 comprises a P-MOSFET 54 coupled between the input/output terminals S and D, and N-MOSFETs 56 and 58 coupled in series between V CC and ground. P-MOSFET 54 has its source coupled to the first input/output terminal S, its gate to an internal node X, and its drain to the second input/output terminal D. N-MOSFET 56 has its drain coupled to V CC , its gate to control terminal G, and its source to node X. N-MOSFET 58 has its drain coupled to node X, its gate to the second input/output terminal D, and its source to ground. The negative-resistance circuit 52 provides a variable negative resistance between input/output terminals S and D. Negative resistance means that, beyond a certain point, as the voltage between terminals S and D increases, current flow between terminals S and D decreases. (Strictly speaking, the differential resistance is negative.) The conductance of the negative-resistance circuit also depends on the input potential at the control terminal G: as this input potential increases, the conductance decreases. This is what is meant herein by saying that the negative resistance is variable. The operation of a negative-resistance circuit of this type will be explained in more detail later, in Figs. 19 to 22. Here the operating characteristics and advantages of the sense circuit in Fig. 10 will be described with reference to Figs. 11 to 13. First, the operation of the inverting amplifier 50 will be described. Fig. 11 is a diagram of operating characteristics of the inverting amplifier 50. The vertical axis represents current flowing between the input/output terminals S and D of the negative-resistance circuit 52, hence through the resistance circuit 22. The horizontal axis represents the potential of node A out , hence at input/output terminal D. In Fig. 11, curves NR a and NR b are volt-ampere characteristics of the negative-resistance circuit 52 when the potential of input node A in is V a and V b , respectively, where V a < V b . On both curves NR a and NR b , as the potential of the output node A out falls, the current first increases, then decreases. More current (higher conductance) is obtained with the lower V a than with the higher V b . Curve L R in Fig. 11 is a volt-ampere characteristic of the resistance circuit 22 when implemented by, for example, an N-MOSFET with interconnected gate and drain. The operating point of the circuit when the potential of input node A in is V a is the intersection P a of curves NR a and L R , at which the potential of output node A out becomes V outa . The operating point of the circuit when the potential of input node A in is V b is the intersection P b of curves NR b and L R , at which the potential of output node V out becomes V outb . For an input voltage swing V a - V b , that is, an output voltage swing V outa - V outb is obtained. The gain of the inverting amplifier 50 of the present embodiment can be compared with the gain of the inverting amplifier 18 in Fig. 2, in which the negative-resistance circuit 52 is replaced with a depletion-mode P-MOSFET. Curves C aa and C bb , indicated by dotted lines in Fig. 11, are volt-ampere characteristics of a depletion-mode P-MOSFET when its gate potential is V a and V b , respectively. The operating point when the potential of input node A in is V a becomes P aa , and the operating point when the potential of input node A in is V b becomes P bb . For an identical input swing from V a to V b , the output voltage swing of inverting amplifier 18 in Fig. 2 is V outaa - V outbb , which is less than the V outa - V outb voltage swing of inverting amplifier 50 in Fig. 10. Configuring the inverting amplifier 50 in the present embodiment from a negative-resistance circuit 52 and resistance circuit 22 therefore improves its gain. Another advantage is that the negative-resistance circuit 52 has no depletion-mode transistors, so no special fabrication steps are needed to form them. The potential of internal node X in Fig. 10 is always less than the potential of control node G by at least V TNN , so P-MOSFET 54 in the negative-resistance circuit 52 does not cut off, even when the potential at nodes A in and G is V CC . The input terminal IN can therefore be biased close to V CC , just as in the first to fifth examples, which is an advantage for operation at low supply voltages. Next, the stability of operation of the inverting amplifier 50 will be discussed with reference to Fig. 12. Fig. 12 is simply a redrawing of the inverting amplifier 50 in Fig. 10, showing the resistance circuit 22 consisting of an N-MOSFET with interconnected gate and drain as mentioned above. N-MOSFETs 56 and 58 are regarded as constituting a circuit A with input node N 42 and output node N 40 . P-MOSFET 54 and the resistance circuit 22 are regarded as constituting a circuit B with input node N 40 and output node N 42 . Circuits A and B are mutually cross-coupled. Node N41 (terminal G in Fig. 10) is biased to a suitable potential, e.g. a potential close to V CC . Fig. 13 shows the input-output characteristics of circuits A and B. The vertical axis in Fig. 13 represents the potential of node N 40 , which is the output node of circuit A and the input node of circuit B. The horizontal axis represents the potential of node N 42 , which is the input node of circuit A and the output node of circuit B. Curve C A is the input-output characteristic curve of circuit A; curve C B is the input-output characteristic curve of circuit B. In circuit A, as the input potential (node N 42 ) falls, the output potential (node 40) rises. When the input potential becomes V TN , the output potential reaches and remains fixed at V CC - V TNN . In circuit B, as the input potential (node 40) rises, the output potential (node N 42 ) falls. When the input potential becomes V CC - |V TP |, the output potential reaches and remains fixed at V TN . The characteristic curves C A and C B therefore intersect at an operating point P. When the potential of node 40 is V CC - V TNN , N-MOSFET 56 in circuit A is strongly back-biased, so V TNN is much greater than V TN . Under normal CMOS fabrication conditions with V TN approximately equal to |V TP |, V TNN is also much greater than |V TP |. This condition ensures that characteristic curves C A and C B do not intersect at points other than P. Operation of the inverting amplifier 50 is therefore stable. 2nd embodiment of the invention This embodiment, shown in Fig. 14, combines the fifth example and the first embodiment. Elements common to Figs. 8 and 10 have the same reference numerals. This sense circuit differs from Fig. 8 only in the structure of its amplifier circuit 60. Externally, the amplifier circuit 60 has the same input and output nodes as in Fig. 8, with input node A in coupled to the input terminal IN, output node A out1 coupled to the gate of P-MOSFET 14, and output A out2 coupled to the gate of P-MOSFET 24. Internally, the amplifier circuit 60 comprises a resistance circuit consisting of an N-MOSFET 62 with interconnected gate and drain, and a negative-resistance circuit 64. The negative-resistance circuit 64 is identical to the negative-resistance circuit 52 shown in Fig. 10, except that the internal node X has been led out to an output terminal TX. Output terminal TX is coupled to the second output node A out2 of the amplifier circuit 60. Input/output terminal D is coupled to the first output node A out1 , and input/output terminal S to V CC . Control terminal G is coupled to the input node A in . The amplifier circuit 60 operates like the amplifier circuit 50 in Fig. 10, so to describe the operation of this sense circuit, all that remains is to describe the relationship of the second output node A out to the input node A in . This relationship can be understood by considering the modified circuit shown in Fig. 15, which is obtained from the amplifier circuit 36 of Fig. 8 by replacing the depletion-mode P-MOSFET 38 with a negative-resistance circuit 52 identical to the negative-resistance circuit 52 in Fig. 10. The part of Fig. 15 consisting of the negative-resistance circuit 52 and N-MOSFET 46 has the same configuration as the inverting amplifier 50 in Fig. 10. Accordingly, the voltage swing at input node A in is inverted, amplified, and obtained at the second input/output terminal D. As explained in Fig. 10, the gain is larger than when a depletion-mode P-MOSFET is used. Since this second input/output terminal D controls the gate of N-MOSFET 48, it provides a shifted output from the second output node A out2 , with a larger voltage swing in Fig. 15 than in Fig. 8. In Fig. 15, the gate potentials of N-MOSFETs 40 and 56 are always equal, and the gate potentials of N-MOSFETs 48 and 58 are always equal. If the capability of the N-MOSFET 56 in Fig. 15 (defined by the drain current that can be produced by a drain-source voltage for a fixed gate voltage, for example) is equal to the capability of N-MOSFET 40, and the capability of N-MOSFET 58 is equal to the capability of N-MOSFET 48, then the gate potential of P-MOSFET 54 and the potential of the second output node A out2 are always equal. A simpler equivalent circuit can therefore be obtained by connecting the gate of P-MOSFET 54 to the second output node A out2 and eliminating N-MOSFETs 40 and 48, as shown in Fig. 16. The circuit in Fig. 16 is none other than the amplifier circuit 60 of Fig. 14. The amplifier circuit 36 in Fig. 8 and the amplifier circuit 60 in Fig. 14 both comprise four transistors, but the amplifier circuit 60 in Fig. 14 is easier to fabricate because it has no depletion-mode transistors. Moreover, it provides a higher gain for the shifted output at the second output node A out2 . Other features of the 2nd embodiment are as already noted in the first to fifth examples and in the first embodiment, including stability of operation, suitability for use at low supply voltages, and a wide dynamic range. Applications of the amplifier circuit 60 in Fig. 14 are not restricted to sense circuits; it is effective when used as a level shifter and inverting amplifier in various other types of circuits as well. The preceding sense circuits can be used in a semiconductor memory (e.g. DRAM, SRAM, or ROM) by coupling their input terminal IN to a data line as shown, for example, in Fig. 1. The load circuit 10, 32, or 35 then becomes a data-line load circuit that biases the data line to a potential near V CC . The examples and embodiments so far have shown a sense circuit with a single input terminal, but in memory circuits, differential data signals are often employed. 3rd embodiment Fig. 18 shows a variation of a negative-resistance circuit in which the roles of P-MOSFET and N-MOSFET are interchanged and which can form part of the amplifier of the first and second embodiment. An N-MOSFET 140 is now coupled between the first and second input/output terminals S and D. Two P-MOSFETs 142 and 144 are coupled in series between V CC and ground. The gate of N-MOSFET 140 is coupled to internal node X, between P-MOSFETs 142 and 144. The gate of P-MOSFET 142 is coupled to control terminal G. The gate of P-MOSFET 144 is coupled to the second input/output terminal D. Incidentally, terminals S, G, and D are analogous to the source, gate, and drain of a transistor. Terminals S and D are in fact the source and drain of N-MOSFET 140, while terminal G, via P-MOSFET 142, exerts control over the gate of N-MOSFET 140. Overall, the negative-resistance circuit operates much like a depletion-mode N-MOSFET, except that as the drain potential at terminal D rises, at a certain point the drain-source current, instead of merely saturating, starts to decline. Fig. 19 is an explanatory diagram of potentials and currents in this negative-resistance circuit. The static operation of this circuit can be described by assuming that input/output terminal S is grounded, and introducing three voltage sources E 1 , E 2 , and E 3 . The first voltage source E 1 generates a voltage V NDS between the input/output terminals D and S. The second voltage source E 2 generates a voltage V NGS between control terminal G and input/output terminal S. The third voltage source E 3 provides the power-supply potential V CC applied to the source of P-MOSFET 144. V GS0 denotes the gate-source voltage of N-MOSFET 140. The gate-source voltage of P-MOSFET 142 is V NGS . The gate-source voltage of P-MOSFET 144 is V NDS - V CC , denoted V GS4 . Fig. 20 shows volt-ampere characteristics of P-MOSFETs 142 and 144 in Fig. 19 when V NGS is zero volts. The vertical axis indicates the current I BIAS flowing through P-MOSFETs 142 and 144; the horizontal axis indicates the potential V X of node X. Curve C 2 in Fig. 20 is the voltampere characteristic of P-MOSFET 142. Curves C 4a , C 4b , and C 4c are volt-ampere characteristics of P-MOSFET 144 when V NDS has respective values of V a , V b , and V c (where V a < V b < V c ). As potential V NDS increases from V a to V c , the gate-source voltage |V GS4 | of P-MOSFET 144 decreases, reducing the current flow through P-MOSFET 144. The operating point of node X when V NDS = V a is the point Q A , at which the potential V X of node X is V A . Similarly, the operating point when V NDS = V b is Q B , at which V X = V B . The operating point when V NDS = V c is Q C , at which V X = V C . As V NDS increases from V a to V c , the potential V X of node X decreases: V A > V B > V C . The potential V X of node X is the gate-source voltage V GS0 of N-MOSFET 140. Fig. 21 is a static characteristic diagram of the negative-resistance circuit 10 when V NGS is again zero volts. The vertical axis indicates the current I NDS flowing from input/output terminal D to input/output terminal S. The horizontal axis indicates the voltage V NDS between the input/output terminals D and S. In Fig. 21, the solid-line curve C NR is the volt-ampere characteristic of the negative-resistance circuit 10. The dotted-line curves C OA , C OB , and C OC are the volt-ampere characteristics of N-MOSFET 140 when its gate-source voltage V GS0 is fixed at V A , V B , and V C , respectively. If V NDS is V a , then V GS0 is V A , so curve C OA applies and the circuit operates at point P a . If V NDS is V b , then V GS0 is V B , so curve C OB applies and the circuit operates at point P b . Similarly, if V NDS is V c , then V GS0 is V C , so curve C OC applies and the circuit operates at point P c . When voltage V NDS is sufficiently small, i.e. V NDS = V a , the gate-source voltage V GS0 of N-MOSFET 140 is sufficiently large that N-MOSFET 140 is in a non-saturated state in the vicinity of its operating point P a . The current I NDS is therefore determined mainly by the voltage V NDS , and as voltage V NDS increases, the current I NDS increases. At a larger value of V NDS , specifically at V NDS = V b , the gate-source voltage V GS0 of N-MOSFET 140 becomes small enough that N-MOSFET 140 enters saturation, and the current I NDS peaks at operating point P b . If V NDS increases further, to V c for example, the gate-source voltage V GS0 of N-MOSFET 140 decreases further and the N-MOSFET 140 becomes more deeply saturated. In the deeply saturated state around operating point P c , current I NDS is determined mainly by the gate-source voltage V GS0 of N-MOSFET 140, which is decreasing as V NDS increases. Accordingly, as voltage V NDS increases, current I NDS decreases, and a negative resistance characteristic is obtained. When V NDS reaches V CC - V TP , P-MOSFET 144 turns off, V GS0 holds steady at V TPP , and curve C NR levels out parallel to the horizontal axis. Fig. 22 shows volt-ampere characteristics of the negative-resistance circuit 10 for three more values of V NGS . As in Fig. 21, the vertical axis represents current I NDS and the horizontal axis represents voltage V NDS . Curve C NR1 applies when V NGS has a certain value between ground and V TN . Curve C NR2 applies when V NGS = V TN . Curve C NR3 applies when V NGS has a certain value exceeding V TN . Referring again to Fig. 20, when voltage V NGS is greater than zero, the characteristic curve C 2 of P-MOSFET 142 is shifted to the right by an amount equal to V NGS . Therefore, the values of the gate-source voltage V GS0 of N-MOSFET 140 (V A , V B , V C ) corresponding to given values of its drain-source voltage V NDS (V a , V b , V c ) also shift to the right (increase). In Fig. 22, this means that as V NGS rises, the increasing gate-source voltage of N-MOSFET 140 causes it to enter saturation at a later point, and causes overall current flow to rise. The characteristic curves therefore peak at higher values, with the peak occurring further to the right, a shown. To summarize, for sufficiently large voltages between its input/output terminals S and D, the circuit in Fig. 18 shows negative resistance between these terminals, current flow decreasing as the voltage increases. The conductance of the negative-resistance circuit also varies with the potential of the control terminal G, the conductance increasing as the potential of terminal G increases. A similar description applies to the negative-resistance circuits in Figs. 10 to 22, with the roles of V CC and ground interchanged, so that conductance decreases as the potential of terminal G increases. The negative-resistance circuit has several advantages. One is a simple configuration and easy fabrication, since it consists only of three enhancement-mode MOSFETs. Another is a high current-driving capability, because only a single MOSFET (N-MOSFET 140 in Fig. 18, P-MOSFET 54 in Fig. 10) is coupled in series between the input/output terminals S and D. Yet another advantage is that the gate bias of this MOSFET can be designed independently of its drain-source current I NDS , by appropriate selection of the parameters of the other two MOSFETs (P-MOSFETs 142 and 144 in Fig. 18, N-MOSFETS 56 and 58 in Fig. 10). This affords a high degree of freedom in design, in particular with respect to differential voltampere characteristics (change in I NDS over change in V NDS ). If necessary, depletion-mode MOSFETs can be used for one or more of the transistors in this negative-resistance circuit. Although there is a fabrication-cost penalty, this enables circuits with various useful characteristics to be designed. For example, if P-MOSFET 142 in Fig. 18 is of the depletion type, then the characteristic curves in Fig. 22 are shifted downward and the current I NDS can be made to cut off when V NGS is zero volts. A so-called enhancement-mode negative-resistance circuit can also be obtained easily. 4th embodiment Referring to Fig. 23, a switch 148 can be added between P-MOSFET 144 and V CC . When switch 148 is in the on-state, the negative-resistance circuit is enabled and operates as described above in Figs. 18 to 22. When switch 148 is in the off-state, the negative-resistance circuit is disabled and bias current flow through P-MOSFETs 142 and 144 is cut off, reducing power dissipation. Regardless of the potential of control terminal G, the potential of node X does not go below |V TPP |. When node X is at this potential, |V TPP | >> V TN = V TP (approximately), so N-MOSFET 140 is in the on-state even if switch 148 is in the off-state. 5th embodiment Referring to Fig. 24, the negative-resistance circuit in Fig. 18 can also be modified to have N-MOSFET 140 cut off when the circuit is disabled. In Fig. 24 a P-MOSFET 150 is coupled in series between node X and the drain of p-MOSFET 144, and an N-MOSFET 152 is coupled between node X and ground. The gates of both P-MOSFET 150 and N-MOSFET 152 are coupled to a terminal . P-MOSFET 150 and N-MOSFET 152 function as switches that switch the negative-resistance circuit on and off. When terminal  is high (at the V CC potential), P-MOSFET 150 is in the off-state and N-MOSFET 152 is in the on-state. The off-state of the P-MOSFET 150 cuts off the bias current flowing through P-MOSFETs 142 and 144. Since N-MOSFET 152 is switched on, node X is at ground potential, and N-MOSFET 140 is in the off-state. The negative-resistance circuit is completely disabled; no current flows through it, either between V CC and ground or between the input/output terminals D and S. When terminal  is low (at ground potential), P-MOSFET 150 is in the on-state and N-MOSFET 152 is in the off-state. The negative-resistance circuit now operates as in Figs. 18 to 22. An advantage of the switching scheme in Fig. 24 is that it does not impair the current-driving capability of the circuit, because as before, only a single N-MOSFET 140 is coupled between the input/output terminals S and D. Modifications This invention is not restricted to the above embodiments, but allows various modifications such as, for example, the following. Circuits with similar effects are obtained if N-MOSFET is replaced by P-MOSFET, P-MOSFET by N-MOSFET, V CC by ground, and ground by V CC in any of the preceding embodiments. Current consumption in the circuits of Figs. 2 to 16 can be reduced by inserting switching transistors or other switching means to cut off current flow in the disabled state, as shown in Figs. 17, 23, and 24. In Figs. 2 to 16, another possibility is to switch off the load circuit in the disabled state, and provide other means for biasing the input terminals or their connected data lines in this state. Those skilled in the art will recognize that further modifications can be made without departing from the scope of the invention

Claims: A sense circuit for sensing a current signal received at an input terminal (IN) and generating a voltage signal at an output terminal (OUT), comprising: a first resistance circuit (16) coupled between said output terminal (OUT) and a first fixed potential (GND), for producing a potential at said output terminal (OUT) responsive to current flow through said first resistance circuit (16); a first field-effect transistor (14) having a source coupled to said input terminal (IN), a gate, and a drain coupled to said output terminal (OUT); and an amplifier circuit (18, 30, 36, 50 or 60) having an input node (A in ) coupled to said input terminal (IN) and a first output node (A out or A out1 ) coupled to the gate of said first field-effect transistor (14), for inverting and amplifying said input potential, thereby producing a potential at said first output node (A out or A out1 ), characterized by a load circuit (10, 32 or 35) coupled between said input terminal (IN) and a second fixed potential (V CC ), for producing an input potential at said input terminal (IN) responsive to current flow through said load circuit, and wherein said amplifier circuit comprises: a negative-resistance circuit (52 or 64) coupled to provide a variable negative resistance between said second fixed potential and said first output node (A out or A out1 ) responsive to the input potential received from said input terminal (IN) at said input node (A in ); and a second resistance circuit (22) coupled between said first output node (A out or A out1 ) and said first fixed potential. The circuit of claim 1, wherein said negative-resistance circuit (52) comprises a first input/output terminal (S), a second input/output terminal (D), a control terminal (G) an internal node (X), a first field-effect transistor (54, 115a, 140) of first channel type, with a source coupled to said first input/output terminal (S), a gate coupled to said internal node (X) and a drain coupled to said second input/output terminal (D), a second field-effect transistor (56, 115b, 142) of a second channel type, with a source coupled to said internal node (X), a gate coupled to said control terminal (G), and a drain coupled to a fixed potential, and a third field-effect transistor (58, 115c, 144) of said second channel type, with a source coupled to a further fixed potential, a gate coupled to said second input/output terminal (D), and a drain coupled to said internal node, the negative-resistance circuit having its first input/output terminal (S) coupled to receive said second fixed potential, its second input/output terminal (D) coupled to said first output node (A out or A out1 ), and its control terminal (G) coupled to said input node (A in ). The circuit of claim 1, wherein said load circuit (10, 32 or 35) comprises a second field-effect transistor (24) having a source coupled to receive said second fixed potential, a gate and a drain coupled to said input terminal (IN), wherein said amplifier circuit (36 or 60) has a second output node (A out2 ) coupled to the gate of said second field-effect transistor (24), and amplifies and shifts said input potential, thereby producing a potential at said second output node (A out2 ), and wherein said amplifier circuit (60) comprises: a negative-resistance circuit (64) coupled to provide a variable negative resistance between said second fixed potential and said first output node (A out1 ) responsive to the input potential received at said input node (A in ), and to amplify and shift said input potential, thereby producing a potential at said second output node (A out2 ); and a second resistance circuit (62) coupled between said first output node (A out1 ) and said first fixed potential. The circuit of claim 3, wherein said negative-resistance circuit (64) is as described in claim 2 and further comprises an output terminal (TX) coupled to said internal node (X), having its first input/output terminal (S) coupled to said second fixed potential, its second input/output terminal (D) coupled to said first output node (A out1 ), its control terminal (G) coupled to said input node (A in ), and its output terminal (TX) coupled to said second output node (A out2 ). A sense circuit for sensing a current signal received at an input terminal (IN) and generating a voltage signal at an output terminal (OUT), comprising: a first resistance circuit (16) coupled between said output terminal (OUT) and a first fixed potential (GND), for producing a potential at said output terminal (OUT) responsive to current flow through said first resistance circuit (16); a first field-effect transistor (14) having a source coupled to said input terminal (IN), a gate, and a drain coupled to said output terminal (OUT); and an amplifier circuit (18, 30, 36, 50 or 60) having an input node (A in ) coupled to said input terminal (IN) and a first output node (A out or A out1 ) coupled to the gate of said first field-effect transistor (14), for inverting and amplifying said input potential, thereby producing a potential at said first output node (A out or A out1 ), characterized by a load circuit (10, 32 or 35) coupled between said input terminal (IN) and a second fixed potential (V CC ), for producing an input potential at said input terminal (IN) responsive to current flow through said load circuit, wherein said load circuit (10, 32 or 35) comprises a second field-effect transistor (24) having a source coupled to receive said second fixed potential, a gate and a drain coupled to said input terminal (IN), wherein said amplifier circuit (36 or 60) has a second output node (A out2 ) coupled to the gate of said second field-effect transistor (24), and amplifies and shifts said input potential, thereby producing a potential at said second output node (A out2 ), and wherein said amplifier circuit comprises: a depletion-mode field-effect transistor (38) with a source coupled to receive said second fixed potential, a gate coupled to said input node (A in ), and a drain coupled to said first output node (A out1 ); a third field-effect transistor (40) with a source coupled to said second output node (A out2 ), a gate coupled to said input node (A in ), and a drain coupled to receive said second fixed potential; and a current mirror (42) coupled to allow a current flow between the source of said third field-effect transistor (40) and said first fixed potential, responsive to a current flow between the drain of said depletion-mode field-effect transistor (38) and said first fixed potential.

Inventors: TANOI SATORU, TANOI, SATORU, TANOI, SATORU, C/O OKI ELECTRIC INDUSTRY CO., LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY COMPANY, LIMITED
Application year: 1993
Main classification: G01R19
IPC codes: G01R19, G11C11