FIR filter apparatus for processing of time division multiplexed signals

Abstract: FIR filter circuitry for processing time division multiplexed sampled signals includes parallel sets of delay elements (D SP , D HP ), for delaying respective signals to be filtered, each set having a plurality of taps. Corresponding taps of the respective sets of delay elements are coupled to common weighting (Wn+i) and summing structure (Adder). A time division multiplexed signal is coupled to the parallel sets of delay elements, respective sets being exclusively (Dsp Clk, Dhp Clk) clocked on the occurrence of corresponding signals.

Description: This invention relates to apparatus for time multiplexed processing of signals. From FR-A-2,532,130 it is already known to provide an arrangement of a sample data filter for the chrominance component in a composite video signal, which uses fixed coefficients and a single cascaded clement delay line. The invention will be described in the environment of an advanced definition television receiver (ADTV) of the type for processing HDTV signals proposed by the Advanced Television Research Consortium (ATRC), however it is to be understood that practice of the invention is not limited to such systems, but is applicable to other systems having harmonically related amplitude modulated carriers. FIGURE 1 illustrates a television signal in the ADTV system format. This signal is constrained to have a 6 MHz bandwidth in conformance with NTSC standards. Unlike NTSC television signal however, the ADTV signal consists of two quadrature amplitude modulated carriers, one of which is located in the lower one quarter of the 6 MHz channel space and the other which is located in the upper three quarters of the 6 MHz channel space. The upper carrier has a bandwidth which is four times as wide as the bandwidth of the lower carrier. The upper carrier frequency is exactly four times the lower carrier frequency (related to a predetermined reference). In the FIGURE 1 example both carriers are modulated 16 QAM. FIGURE 2 illustrates a portion of a typical ADTV receiver apparatus including the tuner IF and QAM demodulation circuitry. A detailed description of this apparatus will not be herein provided but may be found in W092/14343 (U.S. Patent Application 650,329 filed 4 Feb. 1991). What is to be noted however, is the parallel processing circuitry (elements 118, 120, 122, 124, 126, 128, and elements 119, 121, 123, 125, 127, and 129) for processing the two QAM signals respectively. Each of these parallel processing paths consist of relative large and complex, and therefore expensive hardware. The present invention is directed toward reducing such parallel hardware, in order to make such a system affordable to the typical consumer. More particularly the invention is directed toward utilizing filters in time division multiplexed fashion to eliminate at least a portion of the parallel processing circuitry utilized to process frequency division multiplexed signals such as the two QAM signals illustrated in FIGURE 1. The present invention includes FIR filter circuitry for processing time division multiplexed sampled signals. The filter circuitry includes sets of delay elements, for delaying respective signals to be filtered, each set having a plurality of taps. Corresponding taps of the respective sets of delay elements are coupled to common weighting and summing structure. Time division multiplexed signal is coupled to the sets of delay elements, respective sets being exclusively enabled on the occurrence of corresponding signals. BRIEF DESCRIPTION OF THE DRAWINGS FIGURE1 is a graphical representation of the spectrum of an ADTV signal. FIGURE 2 is a block diagram of a portion of an ADTV receiver including the tuner and QAM demodulation circuitry. FIGURE 3 is a block diagram of circuitry for processing plural QAM signals in a time division multiplexed embodying the present invention. FIGURE 4 is a block diagram of an input weighted FIR filter for the time division multiplexed filtering of two signals. FIGURE 5 is a schematic diagram of one stage of the filter of FIGURE 4. FIGURE 6 is a timing diagram of respective clocking signals for operation of the circuitry of FIGURE 5. FIGURE 7 is a block diagram of the I, Q DEMUX AND MUX element 20 of FIGURE 3. FIGURE 8 is a block diagram of an output weighted FIR filter for the time division multiplexed filtering of two signals. Refer to FIGURE 3 which illustrates a portion of a more cost effective ADTV receiver. In FIGURE 3, a broadcast signal having the spectral characteristics of the signal illustrated in FIGURE 1 is applied to the tuner/IF circuitry 10. The local oscillator in the IF stage is selected to down convert the the center of the standard priority (SP) channel to the SP channel's symbol rate. The IF frequency is chosen to be 43.5 MHz, which places the center of the baseband SP channel at 3.84 MHz. The down converted ADTV signal is applied to an analog-to-digital converter (ADC) 12. The ADC 12 is clocked at a rate of four times the SP channel's symbol rate or 15.36 MHz. The sampling clock applied to the ADC (and the other system clocks) are generated in the clock element 14. Element 14 may include a VCXO incorporated in a phase locked loop for phase locking the system clocks and the sampling clock to one of the QAM carriers. The 15.36 MHz samples generated by the ADC 12 are applied to a low pass filter 16, having a pass band to attenuate the wideband (SP) QAM carrier, and pass the narrower (HP) QAM carrier. The lowpass filtered high priority (HP) samples are applied to the circuit element 20, and to the subtrahend input port of a subtracter 18. The 15.36 MHz ADTV samples from the ADC 12 are applied to the minuend input port of the subtracter 18. The differences passed by the subtracter represent the SP portion of the ADTV signal, that is the combination of the lowpass filter 16 and the subtracter 18 provides a high or bandpass filter function which attenuates that part of the spectrum occupied by the HP signal component. The SP signal component provided by the subtracter 18 is also applied to the circuit element 20. Element 20 demodulates the respective HP and SP QAM signals into their respective in-phase (I) and quadrature-phase in-phase(Q) components. It also time division multiplexes the components of the SP an HP signals, and time division multiplexes the quadrature-phase components of the SP and HP signals. The symbol rate of the SP signal is exactly four times the symbol rate of the HP signal. In addition the ADTV signal was sampled at four times the SP symbol rate (16 times the HP symbol rate) and the sampling instants are phase locked to the SP carrier. Therefore, alternate samples of the SP signal correspond to in-phase and quadrature-phase signal components. The SP signal may be separated to its in-phase and quadrature-phase components merely by parsing alternate samples into an I signal path and a Q signal path. The in-phase and quadrature-phase components of the HP signal may be separated by selecting every fourth sample from the HP sample stream, and then parsing alternate ones of these samples into an I signal path and a Q signal path. For every I (or Q) sample in the separated HP signal, there are four I (or Q) samples in the separated SP signal. The SP I or Q samples occur at a 7.68 MHz rate and the HP I or Q samples occur at a 1.92 MHz rate. Element 20 time division multiplexes the I (Q) component samples at in the ratio of four SP samples to one HP sample, and couples the multiplexed I (Q) samples to a Nyquist or symbol shaping filter 22. FIGURE 7 illustrates exemplary circuitry for the element 20. In FIGURE 7, the bandpass filtered SP signal from the subtracter 18 is applied to a one-to-two multiplexer 30, and the lowpass filtered HP signal is applied to the one-to-two multiplexer 31. Both the SP and HP signals occur at the 15.36 MHz rate. The control inputs C, of the respective multiplexers 30 and 31 are clocked at 7.68 MHz conditioning the multiplexers to couple alternate input samples to the I and Q output ports of the respective multiplexers, thus separating the I and Q components. Note, however, that even though the multiplexers 30 and 31 separate the I and Q components of the HP and SP signals, the I and Q signals are not demodulated as alternate samples which correspond to 180 degree phases. Demodulation is performed by multiplying successive I samples and successive Q samples by 1, -1, 1, -1, 1, -1, 1, etc. This multiplication is performed by the exclusive OR gates XOR 35 and 36 which have first input ports coupled to receive the I and Q samples and second input ports coupled to a clock signal having a frequency of one half the output sample rate from the multiplexers. Demodulation need not necessarily be performed at this point in the system. Whether it is or not affects the form of the succeeding filter functions. If demodulation is performed at this point, the following Nyquist filters will have lowpass transfer functions. Alternatively, if demodulation is performed after the Nyquist filters, then the Nyquist filters will have bandpass transfer functions. The HP and SP in-phase components output from the respective multiplexers are at a 7.68 MHz rate. The SP I samples are coupled to a serial-input-parallel output shift register 32, which shifts samples at the 7.68 MHz rate. Successive output ports of the register 32 are coupled to the latter four input ports of a five-input parallel-input-serial-output shift register 34. The HP I samples are applied to a compensating delay stage 33 which shifts samples at the 7.68 MHz rate. Output samples from the stage 33 are applied to the fifth input port of the register 34. The load input of the register 34 is pulsed at a rate of 15.36/8 MHz to load a set of four successive SP and one HP I component samples. The register 34 is then clocked at 9.62 MHz to provide a serial stream of time division multiplexed SP and HP in-phase component samples. The quadrature-phase samples are separated and multiplexed in a similar manner with similar circuitry (not shown). The demodulated and multiplexed I and Q samples, from element 20, are applied to square root Nyquist filters 22. The signal illustrated in FIGURE 1 is transmitted with excess bandwidth, which bandwidth is tailored by Nyquist filters at the transmitter. In order to minimize signal noise at the receiver, the received signal is filtered with Nyquist filters having transfer functions substantially matched to the Nyquist filters incorporated at the transmitter. These filters are of the finite impulse response (FIR) type and typically have 30 or more taps and associated weighting circuits. Such filters are very hardware intensive. Arranging the filters to operate in time division multiplexed (TDM) fashion to process the time division multiplexed I and Q samples significantly reduces the required hardware. FIGURE 4 illustrates in block form an example of a portion of one of the I and Q filters 22. The filter is arranged as an input weighted FIR filter. Assume that the time multiplexed I samples from the element 20 are applied to the bus designated INPUT. These samples are applied to each of the weighting circuits Wn+i wherein they are weighted by respective coefficients Cn+i. The weighted samples from the respective weighting circuits are coupled to respective adders, which adders are interconnected by delay stages D SP (D HP ). The delay stages are clocked at the sample rate to successively process the applied samples, and provide a filtered signal at the output at the right end of the filter. Recall that the samples occur in the sequence SP, SP, SP, SP, HP, SP, SP, SP, SP, HP, etc. When an SP sample is applied to the input, the delay stages D SP are enabled or clocked, and when an HP sample is applied to the input the D HP delay stages are enabled or clocked. In this manner the SP (HP) samples are filtered independently of the HP (SP) samples. Each time a particular sample type SP (HP) is applied to the input, only those delay stages storing like type samples SP (HP) are interconnected between adder circuits forming a filter operative on only that type sample. That is, when SP (HP) samples are applied to the input, the D HP (D SP ) delay stages are effectively removed from the circuit (the information contained therein however is retained). The general timing of the two types of delay stages is shown in the FIGURE and labelled Dsp CLOCK and Dhp CLOCK for the sample sequence indicated above. The system is illustrated with sources of weighting coefficients Cn+i having two coefficients Cn+i and C'n+i, which applies to the general case for a time division multiplexed filter. In this instance the coefficients are switchable for the different types of samples, if desired. That is, the filter may be arranged to provide different transfer functions for the different signals by using alternate coefficients for the different signals. Thus, if the HP and SP signals are to be processed with different filter functions, for example, the set of coefficients Cn+i (C'n+i) will be applied to the weighting circuits Wn+i when the HP (SP) samples are applied to the filter input. Switching of the coefficients is effected by the coefficient control signal (e.g., signal CB of FIGURE 6). FIGURE 5 illustrates in more detail exemplary circuitry which may be implemented for the delay stages D SP and D HP . The circuitry shown is arranged to accommodate only one bit of the signal samples. In practice a number of such circuits, equal to the number of bits in the applied samples, will be arranged in parallel. Clock and/or control signal waveforms required to operate the FIGURE 5 circuitry are illustrated in FIGURE 6. In FIGURE 6 the row of boxes designated SP, HP etc represent sample intervals and the respective sample type applied to the input of the filter during respective sample intervals. In FIGURE 5 the transistors T1, T2, T3, T7, and inverters INV1 and INV2 form the circuitry of one bit of the D SP delay stage, and the transistors T4, T5, T6, T8, and inverters INV3 and INV4 form the circuitry of one bit of the D HP delay stage. Clock signal CSP1 is applied to the transistors T1 and T3 to couple the SP signal samples to inverter INV1 from the preceding adder and to couple SP signal samples from inverter INV2 to the succeeding adder. The sample coupled to the inverter INV1 is stored on the stray capacitance Cs associated with the gate electrodes of the inverter INV1. The sample is retained on this gate capacitance when the transistor T1 is turned off. Antiphase clock CSP2 is applied to transistor T2 to condition T2 to couple the output of the inverter INV1 to the input of the inverter INV2. This occurs immediately after transistor T1 turns off. The sample value applied to the inverter INV2 is stored on the stray capacitance Cs associated with the gate electrodes of INV2. During the first half of a sample period n, INV2 is storing sample n-1 and provides sample n-1 to the output adder during the portion of sample period n that transistor T3 is conditioned to conduct by clock CSP1. Simultaneously sample n from the input adder is applied to the inverter INV1 via transistor T1. Transistors T1 and T3 are turned off at about the midpoint of sample period n with sample n being stored on the gate capacitance of INV1 and sample n-1 being output by INV2. During the second half of the sample interval n, transistor T2 is turned on, coupling the output potential of INV1 to the gate electrodes of INV2, at which time both the input to INV1 and the output of INV2 exhibit the same potential (corresponding to the state of sample n). Since the same potential occurs at the input of INV1 and the output of INV2, these points may be interconnected to retain the potential thereon indefinitely. However, in between successive sample periods it is not necessary to make such connection to retain the sample information, as the gate capacitances are sufficiently large to hold the values at the frequencies the samples occur. Transistor T7 is provided to make such connection, but in this example T7 is only conditioned to conduct during the sample periods that HP samples are applied to the filter. Note that when transistors T1 and T3 are conditioned to not conduct, the circuitry between transistors T1 and T3 is effectively removed from the system, however the data stored therein is not lost. The circuitry of transistors T4 and T6 and the elements therebetween operate in a similar fashion except they are controlled by the clocks CHP1, CHP2 and CB, and as can be seen from FIGURE 6 are arranged to operate when the opposite circuitry is idled. Referring again to FIGURE 3, the output of the Nyquist filter 22 is applied to an element 24 which may include an equalizer and/or a deghoster. These functions may be performed on the time division multiplexed signals from the filter 22. In an embodiment of this type, the equalizer and deghoster may be provided a reference basis corresponding to the time division multiplexed signal for generating appropriate coefficients for the correcting filters. Since such a deghoster and/or equalizer are trained with reference to a time multiplexed signal, they may take any of the known configurations. Alternatively, the HP and LP samples may be demultiplexed and applied to independent parallel equalizer and deghoster circuits, before being coupled to decompression circuitry for storage or display. FIGURE 8 illustrates an output weighted FIR filter for processing time division multiplexed signals. In FIGURE 8 as in FIGURE 4, the delay elements Dsp and Dhp are clocked or enabled to the exclusion of each other when the appropriate samples are applied to the input connection. The output will be a time division multiplexed signal wherein the individual components are independently filtered. As in the FIGURE 4 arrangement provision is made to apply different coefficients to the weighting elements, if desired, for filtering the multiplexed signals according to different transfer functions. FIGURES 4 and 8 show two sets of delay elements (Dsp, Hsp) for filtering two multiplexed signals. It will be readily apparent to those skilled in the art of circuit design that filters of this type may be arranged with M sets of paralleled delay elements for filtering M different multiplexed signals.

Claims: An FIR filter for filtering time division multiplexed sampled signals comprising: first and second sets of delay elements (D SP , D HP ), the delay elements of each set arranged to provide successively delay samples at successive taps; a common set of weighting (Wn+i) and combining means coupled at the respective taps of said first and second sets of delay elements for weighting and summing samples at respective taps; an output terminal coupled to said combining means; and means (Dsp Clk, Dhp Clk) for exclusively enabling said first set of delay elements when samples of a first signal of said time division multiplexed signal occur, and for exclusively enabling said second set of delay elements when samples of a second component of said time division multiplexed signal occur, whereby said first and second signals are independently filtered in said common set of weighting and combining means; characterized in that said weighting means includes means for weighting samples of a first signal with a first set of weighting coefficients when said first set of delay elements are enabled and weighting samples of a second signal a with a second set of weighting coefficients when said second set of delay elements are enabled. The FIR filter set forth in claim 1 characterized in that respective delay elements of said first set are paralleled with respective delay elements of said second set. The FIR filter set forth in claim 2 characterized in that output connections are made at each of said paralleled delay elements, which output connections are coupled to respective weighting and combining means to form a time multiplexed output weighted FIR filter. The FIR filter set forth in claim 2 characterized in that said combining means includes respective adder circuits coupled between successive paralleled delay elements, said respective adders having a first input port coupled to an output connection of a preceding pair of paralleled delay elements, an output connection coupled to an input port of a succeeding pair of delay elements and a second input port coupled to an output connection of one of said set of weighting means, said weighting means having respective input ports coupled to a common input terminal for applying said time division multiplexed sampled signals, said delay elements, adders and weighting means forming an input weighted FIR filter structure. The FIR filter set forth in claim 2 characterized in that said respective delay elements of the paralleled delay elements are arranged to exhibit sample output values when enabled and to exhibit a high impedance state when not enabled. The FIR filter set forth in any preceeding claims characterized in that respective delay elements of said first set are coupled in cascade to form a first tapped delay line, respective delay elements of said second set are coupled in cascade to form a second tapped delay line, and respective taps of said first and second delay lines are applied to respective multiplexing means, each of said multiplexing means being coupled to weighting and combining means to form a time multiplexed output weighted FIR filter.

Inventors: CHRISTOPHER LAUREN ANN, CHRISTOPHER, LAUREN ANN
Applicants: THOMSON CONSUMER ELECTRONICS, THOMSON CONSUMER ELECTRONICS, INC.
Application year: 1993
Main classification: H03H17
IPC codes: H04N5, H03H17, H04L27