A printed circuit board mounted with electric elements thereon

Abstract: Electric elements such as a resistance chip, a capacitor chip, a semiconductor device package, and a connector are mounted on a printed circuit board by using at least two methods selected from the re-flow method using cream solder, the chip-on board method using bonding wires, the outer lead bonding method, and the thermal pressing method using heat-seal. The printed circuit board is provided with lands having surface layers of a non-electrolysis Ni-Au plate, a soft Au plate and an electrolysis solder plate, each corresponding to a selected mounting method.

Description: FIELD OF THE INVENTION This invention relates to a printed circuit board mounted with electric elements thereon, and more particularly to, a printed circuit board mounted with electric elements thereon by at least two different mounting methods and surface treating methods. BACKGROUND OF THE INVENTION A conventional printed circuit board (PCB) has lands for surface-mounted devices (SMDs), wherein the lands each comprises a predetermined pattern of copper foils, and non-electrolysis Ni-Au plates covering the copper foils. In mounting SMDs such as resistance and capacitor chips, small outline packages (SOPs), connectors, quad flat packages (QFPs), etc. on the PCB, cream solder is supplied to the lands on the PCB for a re-flow process carried out by heating the PCB, so that the SMDs are mounted on the PCB in accordance with the bonding to the patterned SMD lands. The PCB thus mounted with the SMDs is connected to an external circuit by using a flexible printed circuit (FPC) connector. However, the conventional PCB has disadvantages in that only packaged devices can be mounted thereon due to the application of heat for the re-flow process, high density mounting of the SMDs can not be realized, due to the use of the FPC connector, and the thickness, volume and weight are significantly greater than is desirable. In consideration of the disadvantage as described above, an outer lead bonding (OLB) method using tape carrier packages, and a chip on board (COB) method using bonding wires have been adopted in place of the re-flow method using cream solder, and the FPC connector has been replaced by a thermal pressing method providing heat-seal. In this situation, surface-treatments for PCBs adapted to the above described methods will be explained below. (1) Non-electrolysis Ni-Au plate All conventional SMDs can be mounted on a PCB by using SMD lands covered with the non-electrolysis Ni-Au plates. In this type of PCB , although no problem occurs in the thermal pressing method providing heat-seal, some problems occur in the OLB method using tape carrier packages and the COB method using bonding wires. In the OLB method using the tape carrier packages, one of the problems is the occurrence of bridges among fine and narrowly spaced outer leads caused by local re-flow of cream solder supplied on the non-electrolysis Ni-Au plates covering patterned copper foils. In case where no cream solder is used, electrodes of tape automated bonding (TAB) devices are required to be plated by non-electrolysis Ni-Au layers, so that the TAB devices are directly bonded to the PCB. However, this increases the cost of fabricating device-mounted PCBs due to the adoption of the non-electrolysis Ni-Au plates on the TAB electrodes. In the COB method using bonding wires, Au bonding wires are bonded to the non-electrolysis Ni-Au plates of the SMD lands on the PCB mainly by the bonding between Ni and Au, because Au thickness of the non-electrolysis Ni-Au plates is very thin. As a result, the mechanical strength of the Ni-Au bonding portions is very low resulting in low reliability. (2) Electrolysis solder plate The electrolysis solder plate is of an uniform surface having no roughness thereon, so that the aforementioned bridges can be avoided, even if cream solder is supplied on mounting lands to carry out the re-flow process, although it is difficult to deal with any surplus solder on the PCB. The electrolysis solder plate can be used in the OLB method using tape carrier packages without any problem. In other words, although it can be used for the SMDs and the TABs, it has a problem, when it is used for the COB method using bonding wires, because the surface uniformity thereof as required in the bonding process is not obtained. Further, the bonding strength is not high and stable among terminals due to the usage of solder, thereby resulting in deterioration in quality. As a matter of course, electrodes for applying a voltage across plating portions are required to be provided. As a result, density of circuit patterns is lowered due to the provision of the electrodes. (3) Soft Au plate The soft Au plate is basically provided by chemical reaction. Therefore, electrodes are required to be provided for the same reason as described in the item (2). Further, Au plate treatment is required to be made even on the side of TAB in the OLB method using tape carrier packages. As a result, the increase is inevitable in cost. As discussed in the items (1) to (3), devices or parts to be mounted on a PCB are limited in kind dependent on what kind of a plating layer is used on the PCB. Consequently, a PCB mounted with electric elements is difficult to be fabricated with high density, thin and small configuration, and high quality. JP 4-051582 describes a hybrid integrated circuit device in which a semiconductor chip is die bonded to an electric-component mounting part of a flexible wiring board and a chip capacitor is soldered and mounted on a wiring part of the wiring board. Printed Circuit Design, vol. 8, no. 2, February 1991 pages 36-41 describes how high-pin-count chip on board and tape automatic bonding methods may be used to help reduce overall PCB rises. SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to provide a PCB in which an element mounting density becomes high, and thin and small size configuration is realized. It is a further object of the invention to provide a PCB in which reliability is increased. The present invention provides a printed circuit board comprising lands for mounting electric elements on the printed circuit board, characterised in that said lands comprise at least two of: (a) a land to be used in reflow and thermal pressing methods to mount electric elements on the printed circuit board, said land comprising a portion of a predetermined pattern of copper foil covered by a non-electrolysis Ni-Au plate layer; (b) a land to be used in an outer lead bonding method to mount electric elements on the printed circuit board; said land comprising a portion of said predetermined pattern of copper foil covered by said non-electrolysis Ni-Au plate layer, said Ni-Au plate being in turn covered by an electrolysis solder plate layer; and (c) a land to be used in a chip on board method to mount electric elements on the printed circuit board, said land comprising a portion of said predetermined pattern of copper foil covered by said non-electrolysis Ni-Au palter layer, said Ni-Au plate being in turn covered by a soft AU palter layer. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be explained in more detail in conjunction with appended drawings, wherein: Figs. 1A to 1C show a conventional PCB mounted with electric elements thereon, wherein Fig. 1A is a top surface perspective view, Fig. 1B is a bottom surface perspective view, and Fig. 1C is a cross-sectional view, Figs. 2A to 2C, and Figs. 3A to 3C show PCBs mounted with electric elements thereon in first and second preferred embodiments according to the invention, respectively, wherein Figs. 2A and 3A are top surface perspective views, Figs 2B and 3B are bottom surface perspective views, and Figs. 2C and 3C are cross-sectional views, Figs 4A and 4B show a top surface view and a bottom surface perspective view of another printed circuit board and Figs. 5A and 5B, Figs. 6A and 6B, Figs. 7A and 7B, Figs. 8A and 8B, Figs. 9A and 9B, Figs. 10A and 10B, Figs. 11A and 11B, Figs. 12A and 12B show PCBs mounted with electric elements thereon in third to tenth preferred embodiments according to the invention, respectively, wherein Figs. 5A to 12A are top surface-perspective views, and Figs 5B to 12B are bottom surface-perspective views. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before explaining a PCB mounted with electric elements thereon in the first preferred embodiment according to the invention, the aforementioned conventional PCB mounted with electric elements thereon will be explained. Fig. 1A shows the conventional PCB 12, on the top surface of which various SMDs including chips 1 such as resistances and capacitors which are molded by ceramic, plastic, etc., a SOP 2 which is packaged by plastic, etc., a connector 3 for connecting internal circuits on the PCB to external circuits, and a QFP 9 are provided. Figs. 1B and 1C show the PCB having a through-hole (only in Fig. 1C) and SMD lands 5, wherein each of the SMD lands 5 comprises a predetermined pattern of a copper foil 51 and a non-electrolysis Ni-Au plate 52 functioning as a surface-treating layer, provided that Fig. 1C does not correspond to Fig. 1B precisely, and only has illustrative purpose. In fabrication, cream solder is supplied on the SMD lands 5 on the PCB 12, and the SMDs 1, 2, 3 and 9 are positioned thereon. Then, thermal treatment is carried out by heating the PCB 12 at a predetermined temperature. Thus, the re-flow process takes place to fabricate the PCB 12 mounted with electric elements thereon. Fig. 2A shows a PCB mounted with electric elements thereon in the first preferred embodiment according to the invention, wherein like parts are indicated by like reference numerals as used in Fig. 1A. In the first preferred embodiment, a TAB for mounting a tape carrier package 4 which is a semiconductor device other than IC and LSI is provided on the PCB 12 in addition to the aforementioned SMDs 1, 2 and 3. Figs. 2B and 2C show the PCB 12 having a through-hole (only in Fig. 2C), SMD lands 5 and a TAB land 6, wherein the TAB land 6 comprises a predetermined pattern of a copper foil 61, a non-electrolysis Ni-Au plate 62, and an electrolysis solder plate 63. In fabrication, the TAB package 4 is mounted on the TAB land 6 by the OLB method, so that the tape carrier package is mounted on the PCB 12 in accordance with local re-flow process of the electrolysis solder plate 63 using no cream solder. On the other hand, the SMDs 1, 2 and 3 are mounted in the same manner as in Figs. 1A, 1B and 1C. Fig. 3A shows a PCB 12 mounted with electric elements thereon in the second preferred embodiment according to the invention, wherein like parts are indicated by like reference numerals as used in Figs. 1A and 2A. In the second preferred embodiment, a COB device 7 (a pair of ICs) is provided on the PCB 12 in addition to the SMDs 1, 2 and 3. Figs. 3B and 3C show the PCB 12 having a through-hole (only in 3C), SMD lands 5 and a COB land 8, wherein the COB land 8 comprises a predetermined pattern of a copper foil 81, a non-electrolysis Ni-Au plate 82, and a soft Au plate 83. In fabrication, the pair of ICs are mounted on the PCB 12 by using Au bonding wires (not shown) to be bonded to the soft Au solder 83 of the COB land 8. On the other hand, the SMDs 1, 2 and 3 are mounted on the PCB 12 in the same manner as in Figs. 1A, 1B and 1C. Fig. 4A shows a PCB 12 mounted with electric elements thereon wherein like parts are indicated by like reference numerals as used in Figs. 1A, 2A and 3A. In this printed circuit board a heat-sealed connector 10 for connecting internal circuits on the PCB 12 to external circuits is provided on the PCB 12. Fig. 4B shows the PCB 12 having SMD lands 5 and a heat-seal land 11, wherein the heat seal connection is realized in accordance with local re-flow of non-electrolysis Ni-Au plate, as shown in Fig. 1C, functioning as a surface-treating layer by thermal pressing method using thermal setting adhesive. Fig. 5A shows a PCB 12 mounted with electric elements thereon in the third preferred embodiment according to the invention, wherein like parts are indicated by like reference numerals as used in Figs. 1A to 4A. Fig. 5B shows the PCB 12 having a TAB land 6 and a COB land 8 which are explained before. Fig. 6A shows a PCB 12 mounted with electric elements thereon in the fourth preferred embodiment according to the invention, wherein like parts are indicated by like reference numerals as used in Figs. 1A to 5A. Fig. 6B shows the PCB 12 having a TAB land 6 and a heat-seal land 11 which are explained before. Fig. 7A shows a PCB 12 mounted with electric elements thereon in the fifth preferred embodiment according to the invention, wherein like parts are indicated by like reference numerals as used in Figs. 1A to 6A. Fig. 7B shows the PCB 12 having a COB land 8 and a heat-seal land 11 which are explained before. Fig. 8A and 8B show a PCB 12 in the sixth preferred embodiment according to the invention, wherein a TAB package 4, a COB-IC 7, and a heat-sealed connector 10 are mounted on the PCB 12 by the OLB method using a tape carrier package, the COB method using Au bonding wires, and the thermal pressing method providing heat-seal, as described before. The TAB land 6 has an electrolysis solder plate, the COB land 8 has a soft Ni-Au plate, and the heat seal land 11 has a non-electrolysis Ni-Au plate, respectively, as surface-treating layers. Figs. 9A and 9B show a PCB mounted with IC thereon in the seventh preferred embodiment according to the invention, wherein resistance and capacitor chips 1 and a connector 3, a TAB package 4, and a COB-IC 7 are mounted on the PCB 12 by the re-flow method using cream solder, the OLB method for mounting a tape carrier package, and the thermal pressing method providing heat-seal, respectively. The SMD lands 5 has a non-electrolysis Ni-Au plate, the TAB land 6 has an electrolysis solder plate, and the COB land 8 has a soft Au plate, respectively, as surface-treating layers. Figs. 10A and 10B show a PCB mounted with electric elements thereon in the eighth preferred embodiment according to the invention, wherein resistance and capacitor chips 1 and a SOP 2, a TAB package 4 and a heat-sealed connector 10 are mounted on the PCB 12 by the re-flow method using cream solder, the OLB method for mounting a tap carrier package, and the thermal pressing method providing heat-seal, respectively. The SMD lands 5 and the heat-seal land 11 have non-electrolysis Ni-Au plates and the TAB land 6 has an electrolysis solder plate, respectively, as surface-treating layers. Figs. 11A and 11B show, a PCB mounted with electric elements thereon in the ninth preferred embodiment according to the invention, wherein resistance and capacitor chips 11, a SOP 2, a COB-IC 7, and a heat-sealed connector 10 are mounted on the PCB 12 by the re-flow method using cream solder, the COB method using Au bonding wires, and the thermal pressing method providing heat-seal, respectively. The SMD lands 5, and the heat-seal land 11 have non-electrolysis Ni-Au plates, and the COB land 8 has a soft Au plate, respectively, as surface-treating layers. Figs. 12A and 12B show a PCB mounted with electric elements thereon in the tenth preferred embodiment according to the invention, wherein resistance and capacitor chips 1, a TAB package 4, a COB-IC 7, and a heat-sealed connector 10 are mounted on the PCB 12 by the re-flow method using cream solder, the OLB method for mounting a tape carrier package, the COB method using Au bonding wires, and the thermal pressing method providing heat-seal, respectively. The SMD lands 5 and the heat-seal land 11 have non-electrolysis Ni-Au plates, the TAB land 6 has an electrolysis solder plate, and the COB land 8 has a soft Au plate, respectively, as surface-treating layers. Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and alternative constructions that may be occur to one skilled in the art which fairly fall within the basic teaching here is set forth.

Claims: A printed circuit board comprising lands for mounting electric elements on the printed circuit board, characterised in that said lands comprise at least two of: (a) a land (5; 11) to be used in reflow and thermal pressing methods to mount electric elements on the printed circuit board, said land comprising a portion (51) of a predetermined pattern of copper foil covered by a non-electrolysis Ni-Au plate layer (52); (b) a land (6) to be used in an outer lead bonding method to mount electric elements on the printed circuit board; said land comprising a portion (61) of said predetermined pattern of copper foil covered by said non-electrolysis Ni-Au plate layer (62), said Ni-Au plate layer being in turn covered by an electrolysis solder plate layer (63); and (c) a land (8) to be used in a chip on board method to mount electric elements on the printed circuit board, said land comprising a portion (81) of said predetermined pattern of copper foil covered by said non-electrolysis Ni-Au plate layer (82), said Ni-Au plate layer being in turn covered by a soft AU plate layer (83). A printed circuit board according to Claim 1, comprising a plurality of electric elements mounted thereon, said electric elements comprising at least two electric elements selected from a resistance chip, a capacitor chip, a semiconductor device package and a connector. A method of fabricating a printed circuit board comprising lands (5, 6, 8, 11) for mounting electric elements on the printed circuit board, said lands comprising a predetermined pattern of copper foil (51, 61, 81) covered by a non-electrolysis Ni-Au plate layer (52, 62, 82) to allow electric elements to be mounted by reflow and thermal pressing methods on the lands covered by the Ni-Au plate layer, characterised by said method comprising at least one of the steps of: covering said non-electrolysis Ni-Au plate layer (62) of some of the lands (6) with an electrolysis solder plate (63) to allow electric elements to be mounted by a local reflow method on the lands (6) covered by the electrolysis solder plate layer (63); and covering said non-electrolysis Ni-Au plate layer (82) of others of the lands (8) with a soft Au plate layer (83) to allow an electric elements to be mounted by a chip on board method on the lands (8) covered by the soft Au plate layer (83).

Inventors: KAWAGUCHI JOJI, KAWAGUCHI, JOJI, Kawaguchi, Joji, c/o NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H05K1
IPC codes: H05K3, H01L21, H05K1