Accumulating multiplication circuit executing a double precision multiplication at a high speed

Abstract: An accumulating multiplication circuit comprises a multiplication part receiving first and second input data, each composed of "n" bits, so as to output a first 2n-bit data of a partial product of the first and second input data, and a shifter for shifting the "2n-bit" data, which is the subject of the arithmetical operation, rightward by "n" bits. An arithmetical operation part receives the first 2n-bit data and the right-shifted 2n-bit data so as to output a third 2n-bit data. Thus, a double-precision multiplication can be efficiently executed.

Description: Background of the Invention Field of the invention The present invention relates to an accumulating multiplication circuit, and more specifically to an accumulating multiplication circuit having a function of executing a double-precision multiplication at a high speed. Description of related art A conventional accumulating multiplication circuit is basically constituted of a multiplication part and an arithmetical operation part, and operates as follows: The multiplication part receives two items of data of for example "n" bits, and outputs data of "2n" bits. The arithmetical operation part receives the data of "2n" bits outputted by the multiplication part and another data of "2n" bits, and outputs data of "2n" bits. By using this conventional accumulating multiplication circuit, a multiplication of "2n" bits × "2n" bits expressed in the 2'complement, that is, a double-precision multiplication will be executed as follows: Here, supposing that a multiplicand and a multiplier are A and B, respectively, in the case of executing the multiplication of two numbers of "2n" bits, expressed in the 2'complement, the multiplicand and the multiplier can be expressed in the following formulas: Supposing that a product of A and B is P, P is shown by the following formula: Here, supposing that Q, R, S and T are expressed by the formulas (6) to (9), respectively, P can be shown by the following formula (10): P = ( Q + 2 -n • S ) • ( R + 2 -n • T) = Q • R + 2 -n • ( Q • T + S • R ) + 2 -2n • S • T Thus, the double-precision multiplication of "2n" bits can be executed by executing the following four kinds of single-precision multiplication and also executing the shift and addition for weighting of 2 -2n or 2 -n in accordance with the formula (10). Q • R : 2'complement × 2'complement Q • T : 2'complement × Absolute value S • R : Absolute value × 2'complement S • T : Absolute value × Absolute value In this case, the total number of the operations is six in the whole, that is, one accumulating multiplication of a 2'complement × a 2'complement, two accumulating multiplications of a 2'complement × an absolute value, one multiplication of an absolute value × an absolute value and two n-bit shifts. Namely, the required operation time is six times longer than that of the single-precision operation. As mentioned above, in the case of executing a double-precision operation to obtain the operation results of "2n" bits, the conventional accumulating multiplication circuit as mentioned above requires the operation time six times as long as that of the single-precision multiplication. Further, it requires two times of saving of data carried over by the shifting in order to obtain the operation result of "4n" bits. ELECTRONIC DESIGN. vol. 34, no. 25, October 1986, HASBROUCK HEIGHTS, NEW JERSEY R. OWEN "ECL MAC slashes system processing times by 80%" shows an accumulating multiplication circuit with a 16-bit right shifter which is connected to accumulator registers. A multiplier-accumulator is provided which adds or subtracts existing data contained in the accumulator registers. In particular, this accumulating multiplication circuit is constituted of a multiplication part and an arithmetical operation part, wherein said multiplication part comprises: first to four registers for holding the most significant "n" bits of a multiplier, where "n" is a positive integer, the least significant "n" bits of said multiplier, the most significant "n" bits of a multiplicand, and the least significant "n" bits of said multiplicand, respectively, selection means for selecting either an output data of said first register or an output data of said second register so as to supply the selected output data, and for selecting either an output data of said third register or an output data of said fourth register, so as to supply the selected output data, a multiplier receiving said selected output data to perform nxn bit multiplication and said arithmetical operation part comprises an arithmetical operation circuit receiving an output of said multiplier and an output of a multiplexor, for outputting a "2n-bit" output data being a result of the operation, the output of said arithmetical operation circuit being supplied to fifth and sixth registers respectively receiving and holding the most significant "n" bits and the least significant "n" bits of said "2n-bit" output data outputted from said arithmetical operation circuit, and said multiplexer having a first input receiving the content of said fifth and sixth registers and a second input receiving the value zero and a third input connected to a n-bit right shifter receiving the content of said fifth and sixth registers. Summary of the Invention It is an object of the present invention to provide an accumulating multiplication circuit which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide an accumulating multiplication circuit capable of shortening the operation time required for obtain a double-precision operation result. These objects are solved by the subject matter of claim 1. Further improvements are given by the subject matter of claim 2. An accumulating multiplication circuit having a function of executing a double precision multiplication comprises a multiplication part to execute an operation for first and second input data, composed of "n" bits, respectively, and to output a first 2n-bit data, an arithmetical operation part to execute an operation for said first 2n-bit data and a second 2n-bit data and to output a third 2n-bit data, and a shifter for shifting said second 2n-bit data rightward by "n" bits so as to generate input data for said arithmetical operation part. More specifically, the multiplication part comprises: first to four registers for holding the most significant "n" bits of a multiplier, where "n" is a positive integer, the least significant "n" bits of the multiplier, the most significant "n" bits of a multiplicand, and the least significant "n" bits of the multiplicand, respectively, a first multiplexor for selecting either an output data of the first register or an output data of the second register, so as to supply the selected output data, a Booth's decoder receiving the selected output data outputted from the first multiplexor, a second multiplexor for selecting either an output data of the third register or an output data of the fourth register, so as to supply the selected output data, a partial product generating circuit receiving an output of the Booth's decoder and an output of the second multiplexor, for generates a partial product, and a partial product adder circuit summing the partial product from the partial product generating circuit. In addition, the arithmetical operation part comprises: fifth and sixth registers for respectively holding the most significant "n" bits and the least significant "n" bits of data used for the arithmetical operation with the product generated in the multiplication part a third multiplexor having a first input receiving the "2n" bit-data held in the fifth and sixth registers, a second input receiving 0 and a third input, a shifter receiving an output data of the third multiplexor for shifting the received data rightward by "n" bits, a fourth multiplexor selecting either the output data of the third multiplexor or an output data of the shifter 31 so as to supply the selected data, an arithmetical operation circuit receiving an output of the fourth multiplexor and an output of the partial product adder circuit, for outputs a "2n-bit" output data which is a result of the operation, an output of the arithmetical operation circuit being supplied to the third input of the third multiplexor, and seventh and eighth registers respectively receiving and holding the most significant "n" bits and the least significant "n" bits of the "2n-bit" output data outputted from the arithmetical operation circuit. In one preferred embodiment, the arithmetical operation part further includes ninth and tenth registers for receiving and holding data including the first bit to the "n-th" bit of the data outputted by the shifter, and data including the (n-1)th bit to "2n-th" bit of the data outputted by the shifter. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a block diagram illustrating a first embodiment of the accumulating multiplication circuit in accordance with the present invention; and Figure 2 is a block diagram illustrating a second embodiment of the accumulating multiplication circuit in accordance with the present invention. Description of the Preferred embodiments Referring to Figure 1, there is shown a block diagram illustrating a first embodiment of the accumulating multiplication circuit in accordance with the present invention. The shown accumulating multiplication circuit is constituted of a multiplication part 1 and an arithmetical operation part 3. The multiplication part 1 comprises registers 11 to 14 for holding the most significant "n" bits XH of a multiplier, the least significant "n" bits XL of the multiplier, the most significant "n" bits YH of a multiplicand, and the least significant "n" bits YL of the multiplicand, respectively, a multiplexor 15 for selecting either an output data of the register 11 or an output data of the register 12, so as to supply the selected output data to a Booth's decoder 17, and a multiplexor 16 for selecting either an output data of the register 13 or an output data of the register 14, so as to supply the selected output data to a partial product generating circuit 18. This partial product generating circuit 18 also receives an output of the Booth's decoder 17, and generates a partial product to a partial product adder circuit 19. The arithmetical operation part 3 comprises registers 21 and 22 for holding the most significant "n" bits ZH and the least significant "n" bits ZL of data used for the arithmetical operation with the product, respectively, and a multiplexor 23 for selecting one from the "2n" bit-data held in the registers 21 and 22, 0 and an output of an arithmetical operation circuit 24. The arithmetical operation part 3 further comprises a shifter 31 receiving the output data of the multiplexor 23 for shifting the received data rightward by "n" bits, and a multiplexor 32 selecting either an output data of the multiplexor 23 or an output data of the shifter 31 so as to supply the selected data to an arithmetical operation circuit 24. The arithmetical operation circuit 24 also receives an output of the partial product adder circuit 19, and outputs a "2n-bit" output data which is a result of the operation. A pair of registers 25 and 26 respectively hold the most significant "n" bits RH and the least significant "n" bits RL of the "2n-bit" output data outputted from the arithmetical operation circuit 24. Now, operation of this embodiment will be described. At first, the multiplexor 15 of the multiplication part 1 selects either the "n-bit" data XH held in the register 11 or the "n-bit" data XL held in the register 12, and supplies the selected data to the Booth's decoder 17. The multiplexor 16 also selects either the "n-bit" data YH held in the register 13 or the "n-bit" data YL held in the register 14, and supplies the selected data to the partial product generating circuit 18. The partial product generating circuit 18 generates a partial product of an output of the Booth's decoder 17 and an output of the multiplexor 16. The partial product adder circuit 19 sums the partial product generated by the partial product generating circuit 18, and outputs the summed result to the arithmetical operation part 3 as a "2n-bit" data. The multiplexor 23 of the arithmetical operation part 3 selects one from the "2n-bit" data ZH and ZL held in the registers 21 and 22, 0 and an output of the arithmetical operation circuit 24, and outputs the selected data to the shifter 31 and the multiplexor 32. The shifter 31 shifts the data supplied from the multiplexor 23 rightward by "n" bits, and supplies the shifted data to the multiplexor 32. The multiplexor 32 selects either the output of the shifter 31 or the output of the multiplexor 32, and outputs the selected output to the arithmetical operation circuit 24. The arithmetical operation circuit 24 receives the output data of the partial product adder circuit 19 of the multiplication part 1 and the output data of the multiplexor 32, and at least calculates a sum of the two received outputs so as to output the operation results RH and RL to the registers 25 and 26 and the multiplexor 23, respectively. In the case of executing a double-precision multiplication by the accumulating multiplication circuit of this embodiment, the operation will be executed as follows; R1 = 0 + XL × YL R2 = 2 -n × R1 + XH × YL R3 = R2 + XL × YH R4 = 2 -n × R3 + XH × YH Namely, it is possible to execute a double-precision operation, which had required six instructions in the conventional accumulating multiplication circuit, by four instructions as mentioned above. In addition, the shift processing in the arithmetical operation part 3 can be carried out in parallel with the operation performed in the multiplication part 1, so that the operation time never increases. Then, a second embodiment of the present invention will be explained. Figure 2 is a block diagram illustrating a second embodiment of the accumulating multiplication circuit in accordance with the present invention. In Figure 2, elements similar to those shown in Figures 1 are given the same Reference Numerals, and explanation thereof will be omitted. The circuit of the second embodiment differs from that of the first embodiment in that, the arithmetical operation part 3 is replaced with an arithmetical operation part 4 which includes, in addition to the elements included in the arithmetical operation part 3, registers 41 and 42 for holding data RSH including the first bit to the "n-th" bit of the data outputted by the shifter 31, and data RSL including the (n-1)th bit to "2n-th" bit of the data outputted by the shifter 31, respectively. With this arrangement, the result of the multiplication is held as follows: The registers 25, 26, 41 and 42 hold the data from (4n-1)-th bit to "3n-th" bit, the data from (3n-1)-th bit to "2n-th bit", the data from (2n-1)-th bit to "n-th" bit, and the data from (n-1)th bit to "0th" bit, respectively. Further, similarly to the first embodiment, the shift processing in the arithmetical operation part 3 can be executed in parallel with the operation in the multiplication part, so that the operation time never increases. In addition, since the saving of the data carried over by the shift processing can be effected, it is possible to execute a double-precision multiplication without deteriorating the precision. As mentioned above, the accumulating multiplication circuit in accordance with the present invention comprises a shifter for shifting the "2n-bit" data, which is the subject of the arithmetical operation, rightward by "n" bits, so as to generate an input data for the arithmetical operation part, so that the the shift processing in the arithmetical operation part can be executed in parallel with the operation in the multiplication part, which permits it to efficiently execute a double-precision multiplication. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures.

Claims: An accumulating multiplication circuit having a function of executing a double precision multiplication and being constituted of a multiplication part (1) and an arithmetical operation part (3), said multiplication part (1) comprising: first to fourth registers (11, 12, 13, 14) for holding the most significant "n" bits of a multiplier, where "n" is a positive integer, the least significant "n" bits of said multiplier, the most significant "n" bits of a multiplicand, and the least significant "n" bits of said multiplicand, respectively, a first multiplexor (15) for selecting either an output data of said first register (11) or an output data of said second register (12), so as to supply the selected output data, a Booth's decoder (17) receiving said selected output data outputted from said first multiplexor (15), a second multiplexor (16) for selecting either an output data of said third register (13) or an output data of said fourth register (14), so as to supply the selected output data, a partial product generating circuit (18) receiving an output of said Booth's decoder (17) and an output of said second multiplexor (16), for generating a partial product, and a partial product adder circuit (19) summing said partial product from said partial product generating circuit (18), and said arithmetical operation part (3) comprising fifth and sixth registers (21, 22) for respectively holding the most significant "n" bits and the least significant "n" bits of data used for the arithmetical operation with the product generated in said multiplication part (1), a third multiplexor (23) having a first input receiving the "2n" bit-data held in said fifth and sixth registers (21, 22), a second input receiving 0 and a third input, a shifter (31) receiving an output data of said third multiplexor (23) for shifting the received data rightward by "n" bits, a fourth multiplexor (32) selecting either said output data of said third multiplexor (23) or an output data of the shifter (31) so as to supply the selected data, an arithmetical operation circuit (24) receiving an output of said fourth multiplexor (32) and an output of said partial product adder circuit (19), outputting a "2n-bit" output data which is a result of the operation, an output of said arithmetical operation circuit (24) being supplied to said third input of said third multiplexor (23), and seventh and eighth registers (25, 26) respectively receiving and holding the most significant "n" bits and the least significant "n" bits of said "2n-bit" output data outputted from said arithmetical operation circuit (24). An accumulating multiplication circuit according to Claim 1 wherein said arithmetical operation part (4) further includes ninth and tenth registers (41, 42) for receiving and holding data composed of the first bit to the "n-th" bit of the data outputted by said shifter (31), and data composed of the (n-1)th bit to "2n-th" bit of the data outputted by said shifter (31).

Inventors: OHTOMO HIROYASU, OHTOMO, HIROYASU, Ohtomo, Hiroyasu, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: G06F7
IPC codes: G06F7