Circuit for converting level of low-amplitude input

Abstract: A level converting circuit for an input clock signal having a relatively low amplitude comprising a level converting circuit for converting the input clock signal to an output clock signal having a relatively high amplitude, the level converting circuit having an input transistor which has a predetermined threshold voltage, and detecting/offsetting circuit for detecting the threshold voltage of the input transistor and adding an offset voltage in response to the detected threshold voltage to the input clock signal and then for providing the offset input clock signal to the level converting circuit. The novel setup performs clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example. This allows to fully cope with a recent trend of ever reducing operating voltage of a CMOS gate array constituting an external timing generator, eliminating necessity for building a pulse amplifier based especially on high dielectric-strength MOS process into the gate array to eventually reduce size of the chip.

Description: BACKGROUND OF THE INVENTION: Field of the Invention: The present invention relates to a level converting circuit and, more particularly, to a circuit for converting a level of a low-amplitude input which, built in a thin-film transistor integrated circuit or the like, functions as its clock interface and pulse-amplifies a low-amplitude input clock signal. Description of the Related Art: Fig. 6 shows an example of a conventional level converting circuit. This level converting circuit 101 is built in a thin-film transistor (TFT) integrated circuit 102 to function as its clock interface. The level converting circuit 101 comprises a current mirror circuit containing a pair of input transistors mnl and mn2 and a pair of load transistors mp1 and mp2. Each of the input transistors is the thin-film transistor of n-channel field-effect transistor (FET) type. Each of the load transistors is the thin-film transistor of p-channel FET type. Gates of the pair of input transistors mn1 and mn2 are supplied with a clock signal CK1 and a clock signal CK2 respectively. These clock signals are opposite to each other in phase. The current mirror circuit is applied with a supply voltage VDD to output a pulse-amplified output clock signal Vout in response to the input clock signals CK1 and CK2. The output clock signal Vout is used as an internal clock of the thin-film transistor integrated circuit 102. The thin-film transistor integrated circuit 102 has a relatively high operating voltage, the supply voltage VDD being about 11 V to 14 V for example. The pair of input clock signals CK1 and CK2 are supplied from a timing generator (TG) 103. The timing generator 103 is generally composed of a CMOS gate array formed on a silicon chip, its supply voltage being relatively low. Referring to Fig. 7, a problem to be solved by the invention will be briefly described. As shown in (a) of Fig. 7, the conventional level converting circuit 101 pulse-amplifies the output clock signal Vout in response to the input clock signal CK1. At this time, an amplitude (a peak potential) of the input clock signal CK1 needs to be somewhat higher than a threshold value Vth of the input transistor mn1. For example, if the threshold value Vth is 3 V, the peak potential of the input clock signal needs to be 4 V or higher. As shown in (b) of Fig. 7, if the peak potential of the input clock signal CK1 is lower than the threshold value Vth, the input transistor mn1 does not conduct sufficiently, providing no proper output clock signal Vout. The external timing generator 103, which supplies the input clock signal, is made up of a CMOS gate array in general. Recently, a supply voltage necessary for driving the gate array has been lowering quickly from conventional 5 V to 3.3 V or lower. A clock signal supplied by such a low-voltage timing generator as mentioned above is sometimes lower than the TFT threshold value on the thin-film transistor integrated circuit. This problem makes it very difficult for directly interfacing between the low-voltage CMOS gate array and the thin-film transistor integrated circuit. In a conventional example shown in Fig. 6, the level converting circuit is operated by using two-phase input clocks CK1 and CK2 opposite to each other in polarity. This consequently requires a pair of connecting terminals as clock interface. As the number of necessary internal clocks increases, the number of clock interface connecting terminals increases, complicating a wiring job and preventing compact device packaging. To solve these problems, a level converting circuit which operates on a single-phase input clock signal has been proposed. Fig. 8 shows an example of such a circuit. Basically, this circuit has generally the same constitution as that of the two-phase input level converting circuit shown in Fig. 6. In the figure, common parts are assigned with common reference numerals for ease of understanding. The single-phase input level converting circuit is different from the single-phase counterpart in that a gate of the input transistor mn2 is applied with a fixed DC bias VG instead of the inverted input clock signal CK2. Referring to Fig. 9, an operation of the single-phase input level converting circuit of Fig. 8 will be described briefly. When the input clock signal CK goes high, the input transistor mn1 and the load transistor mp2 conduct, upon which the pulse-amplified output clock signal Vout rises. Then, when the input clock signal CK goes low, the load transistor mp2 stops conducting and, at the same time, the input transistor mn2 applied with the fixed bias VG operates, causing the output clock signal Vout to fall. To perform this operation stably, it is necessary to properly set the fixed bias VG based on the peak potential of the input clock signal CK and the threshold voltage of the input transistor mn2. Actually, however, it is extremely difficult to set the fixed bias VG in an internal circuit approach. Also, even if the fixed bias VG is externally applied, very fine adjustment is required, thereby hampering practicality. Like the two-phase input level converting circuit of Fig. 6, the single-phase input level converting circuit of Fig. 8 cannot provide the proper output clock signal Vout if the peak potential of the input clock signal goes below the threshold voltage of the input transistor. The EP-A-0 235 499 discloses an interface circuit between bipolar transistor logic levels and field effect transistor logic levels, including a level shifting and multiplying circuit. Said level shifter is made up a sensing transistor for adding an offset voltage more or less equal to a predetermined threshold voltage to an input signal and is then providing the offset input signal to said multiplier for converting the offset input signal to an output signal having a relatively high amplitude, said multipier having an input transistor which has said predetermined threshold voltage. OBJECTS AND SUMMARY OF THE INVENTION: It is therefore an object of the present invention to provide a level converting circuit which operates stably for a single-phase input clock signal having a relatively low amplitude. In carrying out the invention and according to one aspect thereof, there is provided a circuit for converting an input level having a low amplitude comprising a detecting/offsetting block disposed in a front stage therein and a level converting block disposed in a rear stage therein. The level converting block includes two input transistors having predetermined threshold values and amplifies an input signal having a relatively low amplitude to an output clock signal having a relatively high amplitude. The detecting/offsetting block compensates the threshold values of the above-mentioned input transistors, adds an offset according to the threshold value to the input signal, respectively, and supplies respective resultant signals to the above-mentioned level converting block, the input signal of one input transistor is the single-phase input clock signal and the input signal of the other input transistor is zero level. This constitution includes an auxiliary element for lowering a driving capacity of one input transistor lower than that of the other input transistor when the input clock signal switches to zero level, thereby stabilizing inversion of an output clock signal. According to one mode of the invention, the above-mentioned detecting/ offsetting block comprises respective sensing elements for sensing the threshold values of the input transistors to respectively add an offset according to the sensed threshold values to the input signals. A gate of one input transistor is applied with the single-phase input clock signal with a predetermined offset added by a corresponding sensing element. A gate of the other input transistor is applied directly with the predetermined offset via a corresponding sensing element. In this case, the single-phase input clock signal to be supplied to the gate of one input transistor is also supplied to the source of the other input transistor. Each sensing element comprises a sensing transistor formed to have a threshold value equivalent to the threshold value of the respective input transistor. An offset according to a threshold level voltage produced between a source and gate of the sensing transistor is applied to the input signal of the respective input transistor. The detecting/offsetting block is also provided with a current source for driving this sensing transistor. The current source comprises, for example, a transistor or a resistor connected in series between a supply line and the sensing transistor. The level converting block having the above-mentioned constitution comprises a current mirror circuit for example. Alternatively, a flip-flop circuit is used for the level converter. The above-mentioned auxiliary element is composed of an auxiliary transistor whose source and drain are connected to the source of the above-mentioned one input transistor and the gate of the above-mentioned the other input transistor respectively. A gate of the auxiliary transistor is commonly connected to the gate of the above-mentioned the other input transistor. The low-amplitude input level converting circuit according to the invention is contained in a thin-film transistor integrated circuit device for example to function as its clock interface. For example, as such a thin-film transistor integrated circuit device, there is an active-matrix liquid crystal display device comprising an active-matrix display containing liquid crystal elements and thin-film transistors for driving the elements, a peripheral driving circuit containing a horizontal shift register for controlling supply of an image signal to these thin-film transistors and a vertical shift register for supplying a select signal, and the low-amplitude input level converting circuit for supplying an input clock signal to these registers, all the circuits formed on a single substrate. In this case, the low-amplitude input level converting circuit is formed by integrating field-effect thin-film transistors. It should be noted that the present invention is not limited to the field-effect thin film transistor; it also applies to a MOS transistor using bulk silicon or a transistor whose semiconducting material is GaAs. According to the present invention, the low-amplitude input clock signal is internally offset to a proper level based on a threshold of the thin-film transistor; then a resultant signal is level-converted. While the conventional constitution requires an input clock signal amplitude higher than the threshold level, the constitution according to the invention sufficiently allows a pulse amplifying operation at peak potential below the threshold level. Therefore, the low-amplitude input level converting circuit according to the invention directly provides clock interface even for a timing generator comprising a low-power operating CMOS gate array. Additionally, this invention is providing a single-phase input level converting circuit. When the invention is used as the clock interface, the number of connecting terminals is reduced with advantage. BRIEF DESCRIPTION OF THE DRAWINGS: The above and other objects, features and advantages of the present invention will become more apparent from the following description taken in connection with the accompanying drawings, in which: Fig. 1 is a circuit diagram of the low-amplitude input level converting circuit practiced as one embodiment of the invention; Fig. 2 is a diagram illustrating a constitution of a detecting/offsetting circuit to be built in the embodiment of Fig. 1; Fig. 3 is a circuit diagram of an example of a particular circuit constitution of the embodiment of Fig. 1; Fig. 4 is a waveform diagram illustrating a simulation result of the embodiment of Fig. 3; Fig. 5 is a block diagram illustrating an application example of the low-amplitude input level converting circuit of the invention; Fig. 6 is a circuit diagram of an example of a conventional level converting circuit; Fig. 7 is a waveform diagram for describing an operation of the conventional level converting circuit; Fig. 8 is a circuit diagram of another example of the conventional level converting circuit; Fig. 9 is a waveform diagram for describing an operation of the conventional level converting circuit; DESCRIPTION OF THE PREFERRED EMBODIMENT: This invention will be described in further detail by way of a preferred embodiment thereof with reference to the accompanying drawings. Referring to Fig. 5, an application example of the low-amplitude input level converting circuit will be described. In this example, the low-amplitude input level converting circuit is contained in an active-matrix liquid crystal display device 51 to function as clock interface for an external timing generator 52. As shown, the active-matrix liquid crystal display device 51 has a an active-matrix display composed of many liquid crystal pixels LC arranged in a matrix, each liquid crystal pixel LC being driven by a thin-film transistor TFT. A load capacity CS is connected to each pixel LC in parallel. A drain of each TFT is connected to a pixel pole providing one end of a corresponding LC. A source of each TFT is connected to one of a plurality of signal lines 53. A gate of each TFT is connected to one of a plurality of gate lines 54. The other end of each LC is connected to an opposite pole COM. The plurality of gate lines 54 is connected to a vertical shift register 55 to receive a select signal from it. The plurality of signal lines 53 is connected each through a sampling switch SW to a common data line 56 to receive an image signal Vsig from it. Each sampling switch SW is connected through a corresponding gate circuit 57 to a horizontal shift register 58. The shift registers 55 and 58 constitute a peripheral drive circuit block. The vertical shift register 55 sequentially selects the plurality of gate lines 53. The horizontal shift register 58 sequentially makes the sampling switches SW conduct through the corresponding gate circuits 57 to distribute the image signal Vsig to each signal line 53. When one of the gate lines 54 is selected, all thin-film transistors TFT on the selected line conduct simultaneously. Through these conducting transistors, the image signal Vsig sampled from each signal line 53 is written to the corresponding liquid crystal pixel LC. When the selection of the gate line is cleared, the image signal written to the liquid crystal LC is held without change until a next selecting operation. The horizontal register 58 is activated in response to a horizontal start signal HST and sequentially transfers the horizontal start signal HST in synchronization with horizontal clock signals HCK1 and HCK2 which are opposite in phase to drive the sampling switch SW. The vertical shift register 55 is activated in response to a vertical start signal VST and transfers the vertical start signal VST in synchronization with vertical clock signals VCK1 and VCK2 to sequentially select the plurality of gate lines 54. These horizontal start signal HST, horizontal clock signals HCK1 and HCK2, vertical start signal VST and vertical clock signals VCK1 and VCK2 are internally generated by the above-mentioned low-amplitude input level converting circuits 61 through 64. However, when generating the pair of horizontal clocks HCK1 and HCK 2 or the pair of vertical clock signals VCK1 and VCK 2, an inverter is required to internally generate an inverted signal. The above-mentioned low-amplitude input level converting circuits 61 through 64 are each supplied with a two-phase input clock signal having a suitably adjusted period and phase from the external timing generator 52. In the application example of Fig. 5, the low-amplitude input level converting circuits 61 through 64 are of two-phase input constitution. Therefore, a total of eight connecting terminals are required between the timing generator 52 and the clock interface composed of the two-phase input level converting circuits 61 through 64. If single-phase input level converting circuits, instead of the two-phase input level converting circuits, are used for the clock interface, the number of the connecting terminals can be reduced by half. Especially, the single-phase input constitution is intrinsically suitable for the level converting circuit 61 which outputs the horizontal start signal HST and the level converting circuit 63 which outputs the vertical start signal VST. In this respect, Fig. 1 shows a single-phase input level converting circuit practiced as an embodiment of the invention. As shown, the level converting circuit according to the invention comprises detecting/offsetting circuits 1A and 1B disposed in a front stage therein and a level shifting circuit 2 (a level converting block) disposed in a rear stage therein. The level shifting circuit 2 contains an input register mnl having a predetermined threshold value Vth and operates to amplify an input clock signal CK having a relatively low amplitude up to an output clock signal Vout having a relatively high amplitude. It should be noted that, in the embodiment, the input transistor mnl is composed of a n-channel field-effect type thin-film transistor. The detecting/offsetting circuit 1A detects the threshold value Vth of the input transistor mn1, adds an offset based on the detected Vth to the input clock signal CK, and supplies a resultant signal to the level shifting circuit 2. This detecting/offsetting circuit 1A is provided with a detecting element. The detecting element is in turn provided with a detecting transistor mnA formed to have a threshold value substantially equal to that of the above-mentioned input transistor mn1. The detecting element adds an offset based on a voltage of a threshold level produced between a source and a gate of the transistor to the input clock signal CK. The detecting element is also provided with a current source Io for driving the detecting transistor mnA. This transistor is composed of an n-channel field-effect type thin-film transistor whose drain and gate are connected to each other and to a gate of the corresponding input transistor mnl. The gate of the input transistor mnl is supplied with the input clock signal CK. The detecting transistor mnA conducts when the voltage between the source and the gate exceeds the threshold, causing the current source Io to flow a current. When the current flows, a potential at node A drops, making the detecting transistor mnA stop conducting. Consequently, in a normal state, the voltage between the source and the gate of the detecting transistor mnA is kept at the threshold voltage plus something. Since the threshold value of the detecting transistor has been set to be substantially equal to that of the input transistor mnl, the threshold value of the input transistor mnl has been detected as a result. As apparently seen from Fig. 1, the gate of the input transistor mnl is always applied with a bias of the threshold value Vth plus something, so that a DC offset according to this bias is added to the input clock signal CK. As shown, a single-phase input clock signal CK is supplied to a detecting/ offsetting circuit 1A whose constitution is generally shown in Fig. 2. Fig. 2 is a circuit diagram illustrating particular constitutional examples of the detecting/ offsetting circuit 1A of Fig. 1. In the example (a), a current source connected to a detecting transistor mnA is composed of a gate-grounded p-channel field-effect type transistor mp3. In the example (b), the current source is composed of a high-resistance element. Likewise, a detecting/offsetting circuit 1B contains a sensing transistor mnB of n-channel type. Unlike the detecting transistor mnA, a source of the sensing means mnB is grounded. The level shifting circuit 2 is connected between both the detecting/offsetting circuits 1A and 1B. In the embodiment, the level shifting circuit 2 is composed of a differential current mirror circuit. As shown, the level shifting circuit 2 contains a pair of input transistors mn1 and mn2 and a pair of load transistors mp1 and mp2. Like the input transistor mn1, the input transistor mn2 is composed of a n-channel field-effect type thin-film transistor and is connected to the corresponding detecting/ offsetting circuit 1B. The load transistors mp1 and mp2 are each composed of a p-channel field-effect type thin-film transistor. A gate of the input transistor mn1 is applied with the single-phase input clock signal CK with a predetermined offset added by the sensing transistor mnA. A gate of the input transistor mn2 is directly applied with the predetermined offset via the detecting transistor mnB. At the same time, this single-phase input clock signal CK is supplied to a source of the input transistor mn2. The level shifting circuit 2 further contains an auxiliary element to lower a driving capacity of the input transistor mn1 below that of the input transistor mn2 when the single-phase input clock signal CK has changed to zero level, thereby stabilizing inversion of an output clock signal Vout. The above-mentioned auxiliary element is composed of an auxiliary transistor mnX of n-channel type. A source of the auxiliary transistor mnX is connected to the source of the input transistor mn2. A drain of the mnX is connected to the gate of the input transistor mn1. A gate of the mnX is commonly connected to the gate of the input transistor mn2. Referring again to Fig. 1, an operation of the single-phase input level converting circuit will be described in detail. When the single-phase input clock signal CK goes high, the input transistor mn1 conducts via the detecting transistor mnA, pulling a gate voltage of a drive transistor mp2 down to a ground level side. Consequently, the drive transistor mp2 conducts to pull a potential at an output node C up to a supply voltage VDD side, causing the output clock signal Vout to rise. Then, when the single-phase input clock signal CK falls to zero level, a voltage at offset level is applied to the gate of the input transistor mnl. The gate of the input transistor mn2 is always applied with the voltage of offset level by the detecting transistor mnB. Consequently, since no potential is produced at a differential input of the current mirror circuit constituting the level shifting circuit 2, the potential at the node C becomes unstable or reaches an intermediate level between the supply voltage VDD and a ground potential (GND). To overcome this problem, an auxiliary transistor mnX is incorporated in the differential current mirror circuit to lower a potential at node A sufficiently below a potential at node B when the single-phase input clock signal CK is at zero level. Like the input transistor mn2, this auxiliary transistor mnX is nearly in a cutoff state when the single-phase input clock signal CK is high, so that charging of the output node C is not hampered. On the other hand, when the single-phase input clock signal CK is at zero level, the potential at the node A is lowered to put the detecting transistor mnA, the input transistor mn1, and the load transistors mp1 and mp2 near a cutoff state to improve discharging characteristic of the output node C, thereby stabilizing the state of the output clock signal Vout. Here, it is important, in terms of design considerations, to optimize a size of the auxiliary transistor mnX to a certain degree. For example, if the size is too large, the potential at the node A can be pulled down sufficiently when the single-phase input clock signal CK is at zero level, while when the single-phase input clock signal CK is at high level a leak current of the auxiliary transistor mnX prevents the potential at the node A from rising sufficiently, thereby posing the risk of adversely affecting the charging characteristic of the output node C. Fig. 3 shows a further particularization of the circuit constitution of the fourth embodiment of Fig. 1. In this particular example, the supply voltage VDD is set to 12 V. A current mirror constitution composed of transistors mp3, mp5, and mn6 is used as a current source for a detecting transistor mnA. Especially, the transistor mn6 is used as a high-resistance element for current control. Likewise, a current mirror constitution composed of transistors mp4, mp5 and mn6 is used as a current source for a detecting transistor mnB. An output node C is connected with a load capacity via an inverter composed of a pair of transistors mp7 and mn7. This inverter functions as an output buffer. Fig. 4 indicates a result of a simulation performed on the single-phase input level converting circuit of Fig. 3. In the figure, (1) indicates a simulation result obtained when the single-phase input clock signal CK having an amplitude of 5 V is supplied. A pulse width of the input clock signal CK is about 200 ns. The output clock signal Vout rises sufficiently near the supply voltage level in response to the input clock signal CK. To the load capacity, an inverted output voltage VLD is applied. (2) indicates a simulation result obtained when the amplitude of the single-phase clock signal CK has been lowered to 3 V. As compared with the result of (1), generally equally excellent output clock signal Vout and output voltage VLD are obtained. In another embodiment, the level shifting circuit is composed of a flip-flop circuit instead of the current mirror circuit. That is, a drain of an input transistor mn1 is connected to a gate of an opposite load transistor mp2. A drain of an input transistor mn2 is connected to a gate of an opposite load transistor mp1. As described and according to the invention, an input clock signal having a low amplitude is internally offset to a suitable level and then a pulse-amplitude level conversion is performed to perform clock interfacing of a thin-film transistor integrated circuit device represented by an active-matrix liquid crystal display device at a relatively high speed at a low voltage below 3 V for example. This allows to fully cope with a recent trend of ever reducing operating voltage of CMOS gate array constituting an external timing generator, eliminating necessity for building a pulse amplifier based especially on high dielectric-strength MOS process into the gate array to eventually reduce size of the chip. Further, direct connection to the CMOS gate array enhances product attractiveness of an active-matrix liquid crystal display kit. Additionally, according to the invention, a simple setup of adding an auxiliary element to a two-phase- input level converting circuit allows to convert the two-phase system into a single-phase system, providing stable and high-speed pulse amplification. Use of the single-phase-input level converting circuit easily implements level conversion of a single-phase signal such as a shift register start pulse. Further, use of the single-phase-input level converting circuit as clock interface reduces the number of connecting terminals as compared with the prior-art technique. While the preferred embodiment of the invention has been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the scope of the appended claims.

Claims: A level converting circuit for an input clock signal (CK) having a relatively low amplitude, said circuit comprising: level converting means (2) for converting the input clock signal (CK) to an output clock signal (Vout) having a relatively high amplitude, said level converting means (2) having first and second input transistors (mn1, mn2) which have a predetermined threshold voltage (Vth), respectively; characterized by first and second detecting/offsetting means (1A, 1B) having first and second sensing elements (mnA, mnB), respectively, for compensating the threshold voltages (Vth) of the first and second input transistors (mn1, mn2) respectively, by respectively adding an offset voltage to an input signal for the respective input transistor (mn1, mn2) and then providing the respective offset input signal to a gate of said first and second input transistors (mn1, mn2) in said level converting means (2), the input signal for the first input transistor (mn1) being the input clock signal (CK) and the input signal for the second input transistor (mn2) being zero level; and an auxiliary element (mnX) for lowering a driving power of said first input transistor (mnl) lower than that of said second input transistor (mn2) when the input clock signal (CK) changes to zero level, thereby stabilizing inversion of the output clock signal (Vout). A level converting circuit as claimed in claim 1, wherein said first and second sensing elements are for sensing the threshold voltages (Vth) of said first and second input transistors (mn1, mn2); said level converting means (2) receives a single-phase input clock signal (CK) being added with said offset voltage by the corresponding first sensing element, the offset voltage being applied to a gate of the second input transistor (mn2) through the corresponding second sensing element. A level converting circuit as claimed in claim 1 or 2, wherein said auxiliary element comprises an auxiliary transistor (mnX), a source of said auxiliary transistor (mnX) being connected to a source of said second input transistor (mn2), a drain of said auxiliary transistor (mnX) being connected to the gate of said first input transistor (mn1), a gate of said auxiliary transistor (mnX) being connected to the gate of said second input transistor (mn2). A level converting circuit as claimed in claim 2 or 3, wherein each of said first and second sensing elements comprises a sensing transistor (mnA, mnB) having a threshold voltage substantially equal to that of the respective first and second input transistor (mn1, mn2) and a current source (I 0 ) for driving the sensing transistor (mnA, mnB), respectively. A level converting circuit as claimed in claim 4, wherein said current source (I 0 ) comprises a transistor element (mp3) connected in series between a voltage source line and the sensing transistor (mnA, mnB). A level converting circuit as claimed in claim 4, wherein said current source (I 0 ) comprises a resistor element (R). A level converting circuit as claimed in claim 1, wherein said level converting means (2) comprises a current mirror circuit. A level converting circuit as claimed in claim 1, wherein said level converting means (2) comprises a flip-flop circuit. A level converting circuit as claimed in claim 1, wherein said level converting circuit (2) is included in a thin-film transistor integrated circuit. An active-matrix liquid crystal display device (51) comprising: a display region comprising a plurality of pixels (LC), each pixel (LC) being associated with a thin-film transistor (TFT); a peripheral driving circuit comprising a horizontal shift register (58) for controlling provision of video signals to the thin-film transistors (TFT) and a vertical shift register (55) for providing a selecting signal; and interface means (61 - 64) for providing clock signals to the horizontal and vertical shift registers (58, 55), said interface means (61 - 64) comprising a level converting circuit according to anyone of the preceding claims for converting an outer input clock signal having a relatively low amplitude to an inner output clock signal having a relatively high amplitude.

Inventors: HAYASHI YUJI, MAEKAWA TOSHIKAZU, HAYASHI, YUJI, MAEKAWA, TOSHIKAZU, HAYASHI, YUJI, C/O SONY CORPORATION, MAEKAWA, TOSHIKAZU, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H03K19
IPC codes: G09G3, H03K5, H03K19, H03K3