A DEVICE FOR CONVERSION OF A BINARY FLOATING-POINT NUMBER INTO A BINARY 2-LOGARITHM OR THE OPPOSITE

Abstract: The present invention concerns a device for conversion of a binary floating-point number into a binary fix-point 2-logarithm number or the opposite. This is done in the case of conversion of a binary floating-point number by making the invention include an input register where the floating-point number is stored, an output register for the calculated logarithm, a device that transfers the exponent of the floating-point number from the input register to the output register, where it directly forms the characteristic of the logarithm, a device that transfers the fractional part of the mantissa of the floating-point number from the input register to an adder and also to one or more part circuits that form additional parts, a device that transfers the additional parts to the adder, said adder that adds the fractional part of the mantissa of the floating-point number and said additional parts and a device that transfers the sum from the adder to the output register where it forms the fractional part of 2-logarithm. The conversion from logarithm is carried out in a similar manner and with the same components.

Description: A Device for Conversion of a Binary Floating-point number into a Binary 2-Loqarithm or the Opposite. The present invention concerns a device for conversion of a binary floating-point number into a binary fix-point 2-logarithm number or the opposite. A present trend in radar system design is to move the digital signal processing as close to the antenna as possible. There are two reasons for this. Firstly the system will be less sensitive for interfering signals (disturbances) and secondly digital circuits are cheaper than corresponding analog circuits. Digital signal processing for systems such as radar, radio and tele¬ phone require fairly high dynamic range, but can often tolerate a more limited relative accuracy. A method that reduces the number of bits used and in so doing is based on logarithmic conversion is therefore of interest. The main benefit of logarithmic conversion lies in the fact that multiplications and divisions are reduced to additions and subtractions, and powers and roots become simple shifts. The most common method to implement a logarithmic conversion is based on look-up tables. Read-Only Memories (ROM) can be used as tables, but most often they become large and introduce too large a delay for the systems in question. Another way to convert an analog signal into a logarithmic one is known from Radar Handbook (2 ed.), M. Skolnik, 1990, McGraw-Hill, page 3.28-3.30. Here a piece-wise linear approximation is shown. A binary floating-point number has the form (sign) * mantissa * 2 eχ P° nent , where the mantissa and the exponent in the following calculations consist of a fixed number of bits. The exponent is determined by the position of the Most Significant Bit (MSB) in the binary number. The mantissa is the MSB followed by the remaining bits as the fractional part. In the following only unsigned numbers will be considered, it is however not difficult to extend the method to signed numbers, which is immediately obvious to a man skilled in the art. Example: Bi nary number 0 1 0 1 1 1 0 1 1 0 Posi ti on 9 8 7 6 5 4 3 2 1 0 The MSB is in position 8 which gives the exponent β jec = lOOObin- The mantissa is 1.011lOllO^ n- A logarithm have the form an integer part, the characteristic, and a fractional part, the mantissa of the logarithm, whereby both the characteristic and the mantissa in the following calculations consist of a fixed number of bits. The known method of linear approximation is based on the resemblance between a binary floating-point number and a 2-logarithm in the binary fix-point format, cf. figure 1. Thus, the exponent of the floating point number and the integer part of the logarithm are equal. Further, the fractional part of the mantissa of the floating-point number can be used as an approximation of the mantissa of the logarithm. Example: Decimal floating-point number 1.03 10 2 Binary floating-point number 1.100 lOliP- Approxi ation of the logarithm 110.100 Figure 2 shows the graph of the 2 log (x) and the linear approximation that is obtained if one uses the known method. It can be noted that the approximation gives the true value only in the points x = 2 n . Further it is evident that the approximation of the integer part of the logarithm always have the right value, where as the fractional part is always smaller or equal to the true value. Since the approxi¬ mation always is smaller or equal to the true value, this known method of approximation is less suitable in relation with arithmetical opera¬ tions. The present invention is based on the latter method and means that it is corrected to reduce the error and, at a suitable choice of input system constants, distribute it on the whole evenly on both sides of the true value, which is what you wish. This is done by designing the invention according to the following independent claim. Further, the invention can, in an especially advantageous embodiment, be directly implemented on a digital VLSI-circuit. In the following, the invention will be described in detail with reference to the attached drawings, where fig 1 shows in principle how the conversion from a binary floating-point number into the 2-logarithm in binary form is performed, fig 2 shows the graph of the function f(x) = 2 log(x) and a known linear approximation of this function, fig 3 shows a principle design according to the invention of how the conversion from the floating-point mantissa into the fractional part of the improved approximation of the logarithm can be done with additional parts in parallel, fig 4 shows a principle design according to the invention of how the conversion from the floating-point mantissa into the fractional part of the improved approximation of the logarithm can be done with additional part in series, fig 5 shows the principle design according to the invention of a part circuit that computes an additional part accord ing to figure 3, 4, 11, and 12, fig 6 show a concrete embodiment of the invention that performs a conversion from binary floating-point number into a 2-logarithm in binary form, at which one addi¬ tional part and a constant = 0,25<j ec are used, fig 7 shows the graph of the function f(x) = 2 log(x) and an approximation according to the invention of this, at which one additional part and a constant = 0,25<j ec are used, fig 8 shows a simplified flow chart of a computation accord¬ ing to the invention of A= 2 log jl 2 + Q 2 , fig 9 shows how the error was distributed at a computation according to figure 8, fig 10 shows in principle how the conversion from the true 2- logarith in binary form or the improved approximation of the same into a binary floating-point number is performed, fig 11 shows a principle design according to the invention of how the conversion from the mantissa of the logarithm into the floating-point mantissa can be done with the additional parts in parallel, fig 12 shows a principle design according to the invention of how the conversion from the mantissa of the logarithm into the floating-point mantissa can be done with the additional parts in series, fig 13 show a concrete embodiment of the invention that per¬ forms a conversion from a 2-logarithm in binary form into a binary floating-point number, at which one addi¬ tional part and a constant = - 0,25<j ec are use d » It can be noted directly from figure 2 that since the integer part in the known approximation always has the right value, it is the frac¬ tional part that needs to be improved. This can be done by an addition of one or more additional parts T in the form of further linear approximations, cf. figure 3 and 4. In figure 2 one can see, that if a function resembling a saw-tooth is added to the approximation, the error in relation to the true value can be reduced considerably. The present invention utilizes this idea. If one observes the known approximation of the logarithm in an inter¬ val where the fractional part goes from 0 to 1 (i.e. the integer part increases from n to n+1), one can observe that it is possible to create the wanted saw-tooth function by letting the most significant bit in the fractional part control a number of XOR-gates, cf. figure 5. The input signals to the XOR-gates are the remaining bits in the fractional part. This means that the remaining bits in the fractional part will be inverted, when the most significant bit in the fractional part of the known approximation of the logarithm is an one. The concrete implementation of the idea will be further introduced below. At first the idea will be introduced in a more mathematical form in the following way. The saw-tooth function s n is generated from the fractional part Xf of the well-known approximation according to m tn + l .n.„..1, where -^ ≤ x f < λ , m = 0, 1, 2, ..., 2'^ - 1 The saw-tooth function is then multiplied with coefficients C n in such a way that the sum of the additional part or parts and the original linear approximation is as close to the true value of the logarithm as one wishes. The accuracy of the approximation of the logarithm created in this way is determined by the number of additional parts in the form of saw-tooth functions that are used, as well as how well the coefficients are chosen. The general equation for the approximation of the logarithm improved according to the invention 2 log ap (x) is shown below. The known approximation of the 2-logarithm is called 2 log ex (x) and its integer part x-j and its fractional part Xf. 2 log ex ) = x ± + x f 2 loq ap (x) = x ± + X f + C n • ε n , is the number of terms used. The opposite to the above, i.e. the conversion from the 2-logarithm in binary fix-point form into a binary floating-point number, in the form of an antilog function, is performed in a similar way. One subtracts one or more "additional parts" in the form of saw-tooth functions from the true logarithm or, as the case may be, the approximation of the logarithm improved according to the earlier computations, and obtains the known simple linear approximation of the logarithm according to figure 2. Then it is possible to go backwards from the integer part of the known approximation to the exponent of the binary floating-point number and from the fractional part of the known approximation to the fractional part of the mantissa of the floating-point number, which fractional part, after supplementing with an integer one, becomes the expression of the entire mantissa of the floating-point number. The saw-tooth function a n is generated from the fractional part, the mantissa, logf(x) of the correct logarithm or, the according to the invention computed, improved logarithm according to where — I—- ^ < ^ l -.og f ( .x) . < —m 5 + 3 -1 , m = 0, 1, 2, ..., 2 n n + ι - 1 The general equation for the according to the invention improved approximation of the fractional part xf of the antilogarithm antilog ap (x) is shown below. k x f = log f (x) - 2- 4 C n ' ε n i k i s the number of terms used rt-O anti log ap ) = (l.0 + x f ) ■ 2 xi As is evident from the equations for s n and a n the same coefficients C n can be used. A great advantage with the present invention is that it can easily be transferred into hardware in the form of an Application Specific Integrated Circuit, an ASIC. This digital circuit becomes smaller (and less complicated) as well as faster and more precise than earlier known circuits for the same application. The construction can be made with the help of registers, XOR-gates, multipliers and adders. From the beginning, the exponent and mantissa of the floating-point number are placed in a register, cf. figure 1. The exponent is guided from this to a register designed to store the improved approximation of the logarithm after the conversion and is stored there directly as the integer part of this approximation. The fractional part of the mantissa of the floating-point number is guided, both directly to an adder, and also to one or more part circuits forming additional parts 1, 2, 3, ... . To the first part circuit all the bits of the frac¬ tional part are guided, to the second part circuit bit number two and the following bits of the fractional part are guided, to the third part circuit bit number three and the following bits of the fractional part are guided and so forth. In figure 3 it is shown how several such additional parts are added in parallel while figure 4 shows an addition in series of the additional parts. Normally it is suitable to carry out the addition in parallel. These part circuits, cf. figure 5, comprises a number of XOR-gates. To one of the inputs of these XOR-gates the most significant bit of the bits that are guided to each part circuit is guided and to the other input of each XOR-gate different following bits of the fractional part are guided, which means that the following bits are inverted when the most significant bit is 1 and are unchanged when this is 0. The outputs from the XOR-gates will then be multiplied with a suitable scale factor, the constants Cj, Cg, ••-, so the error is minimized. This can, as is shown in figure 5, be done by a multiplication in a multiplier. In the adder or adders respectively the fractional part of the floating-point mantissa is added to the different additional parts, at which permanent zeros are put on the not connected inputs, also CIN (carry-in) is zero. The background for CIN to be put to zero, is that it is evident that the approximation is improved a little if the second flank of the saw-tooth function is somewhat lowered. A simple way to do this is to put CIN to zero instead of the normal one. The result of the addition is guided to the register that stores the improved approximation of the logarithm after the conversion, where it forms the fractional part of this approximation. It has become apparent that for practical needs often only one addi¬ tional part is needed and that the error becomes very small if the constant is chosen to 0,25,j ec . This is very fortunate since this corresponds to a shift two steps of the input of the additional part into the adder, as 0,25^ is equal to 0,01βi n , cf. figure 6. In this case no special multiplier is needed, the multiplication can be done in the routing of the circuit. In the same manner the multiplication could be carried out in the routing for other constants, in the cases when these are an even power of two. Accordingly, in all these cases the circuit gets simpler. Figure 7 shows the graph of 2 log(x) and the improved approximation of it that is obtained by the present invention, when using one addi¬ tional part and the constant = 0,25d ec according to the above. Through a direct comparison between figure 7 and figure 2 it is possible to see how much better the improved method of conversion is than the known. The method of conversion according to the invention has also been tested by simulated calculations of a common radar algorithm that computes the amplitude A from the real part I and the imaginary part Q of the amplitude, The input signal and output signal of the processor were 11-bit and 8- bit respectively. Figure 8 shows a simplified flow chart of the implementation of the computations. The incoming signals I and Q are already in floating¬ point form. The exponent uses 4 bits and the mantissa (without sign) 7 bits. In the first blocks FLC the floating point value is converted into logarithmic form in accordance with the method of the invention. Then the squaring is performed as a simple shift in logarithmic form. In the next blocks LFC the logarithms are converted back to floating¬ point form, as the next computation step is an addition. After the addition there is once again a conversion into logarithmic form in a FLC block, whereupon the square root is computed as a simple shift. Both the integer part and the fractional part of the logarithm output use 4 bits. The simulation was carried out using 400.000 different complex num¬ bers, all from the first quadrant of the complex plane. The result of the calculations performed according to the above was compared to the correctly calculated and rounded value of the amplitude. Figure 9 shows the distribution of the errors. It is evident that the calcula¬ tion according to the invention never created a greater error than 1 bit in the mantissa of the logarithm and that in about 80% of the cases there is no error at all. Further it is evident that existing errors are relatively equally divided on both sides of the true value. Then looking at the opposite, i.e. the conversion from the 2-logarithm in fix-point binary form into a binary floating-point number, the circuit in principle looks the same. From the beginning, the characteristic and mantissa of the logarithm are placed in a register, cf. figure 10. The characteristic, the integer part, is guided from this to a register designed to store the floating-point number after the conversion and is stored there directly as its exponent. The mantissa of the logarithm is guided, cf. figure 11 and 12, both directly to an adder, and also to one or more part circuits forming additional parts 1, 2, 3, ... . To the first part circuit all the bits of the fractional part are guided, to the second part circuit bit number two and the following bits of the fractional part are guided, to the third part circuit bit number three and the following bits of the fractional part are guided and so forth. In figure 11 it is shown how several such additional parts are added in parallel while figure 12 shows an addition in series of the additional parts. Normally it is suitable to carry out the addition in parallel . These part circuits are identical to those that are used in the conversion from floating-point number into logarithm, cf. figure 5, and comprises a number of XOR-gates. To one of the inputs of these XOR-gates the most significant bit of the bits that are guided to each part circuit is guided and to the other input of each XOR-gate differ¬ ent following bits of the fractional part are guided, which means that the following bits are inverted when the most significant bit is 1 and are unchanged when this is 0. The outputs from the XOR-gates will then be multiplied with a suitable scale factor, the constants Cj, C , ..., so the error is minimized. Note that the constants in this case are negative. This can, as is shown in figure 5, be done by a multiplication in a multiplier. In the adder or adders respectively an initial one, which is to be the integer one (the MSB of the binary number) of the resulting binary floating-point number, is added to the fractional part of the real logarithm or the improved approximation of it and the different additional parts (that have negative sign), at which permanent ones are put on the not connected inputs, also CIN (carry-in) is one. The background for CIN to be put to one, is that it is evident that the approximation is improved a little if the second flank of the saw¬ tooth function is somewhat raised. A simple way to do this is to put CIN to one instead of the normal zero. The result of the addition is guided to the register that stores the floating-point number after the conversion, where it forms the man¬ tissa of the floating-point number. It has become apparent that for practical needs often only one addi¬ tional part is needed and that the error becomes very small if the constant is chosen to -0,25<j ec . This is very fortunate since this corresponds to a shift two steps of the input of the additional part into the adder, as 0,25<j ec is equal to 0,01bi n » cf. figure 13. In this case no special multiplier is needed, the multiplication can be done in the routing of the circuit. In the same manner the multiplication could be carried out in the routing for other constants, in the cases when these are an even power of two. Accordingly, in all these cases the circuit gets simpler. The negative sign of the constant is here obtained by using an inverter. In figure 13 this is shown by the inverter that is located in the connection for the most significant bit, the bit that is guided to every XOR-gate within a part circuit, when computing the different additional parts.

Claims: Cl aims : 1. A device for conversion of a binary floating-point number into a binary 2-logarithm, characterized in that it includes an input register where the floating-point number is stored, an output register for the calculated logarithm, a devise that transfers the exponent of the floating-point number from the input register to the output register, where it directly forms the characteristic of the logarithm, a device that transfers the fractional part of the mantissa of the floating-point number from the input register to an adder and also to one or more part circuits that forms additional parts, a device that transfers the additional parts to the adder, said adder that adds the fractional part of the mantissa of the floating-point number and said additional parts and a device that transfers the sum from the adder to the output register where it forms the fractional part of 2-logarithm. 2. A device according to claim 1, characterized in that CIN on the adder is put to zero. 3. A device according to claim 1 or 2, characterized in that all bits in the fractional part of the mantissa of the floating-point number are arranged to be guided to the first part circuit, bit number two and the following are arranged to be guided to the possibly exist¬ ing second part circuit, bit number three and the following are arranged to be guided to the possibly existing third part circuit and so forth. 4. A device according to claim 3, characterized in that every part circuit comprises a number of XOR-gates, to the number of one less than the number of bits that are guided to the part circuit in question, at which the most significant bit of the bits that are guided to each part circuit is arranged to be guided to the first input of all XOR-gates of this part circuit and the second bit is arranged to be guided to the second input of the first XOR-gate of this part circuit, the third bit to the second input of the second XOR-gate of this part circuit, the fourth bit to the second input of the third XOR-gate of this part circuit and so forth. 5. A device for conversion of a binary 2-logarithm into a binary floating-point number, characterized in that it includes an input register where the 2-logarithm is stored, an output register for the calculated floating-point number, a devise that transfers the characteristic of the logarithm from the input register to the output register, where it directly forms the exponent of the floating-point number, a device that transfers the mantissa of the logarithm from the input register to an adder and also to one or more part circuits that forms additional parts, a device that transfers the additional parts to the adder, said adder that adds the mantissa of the logarithm and said additional parts in order to create the fractional part of the mantissa of the floating-point number and adds this to an integer one and a device that transfers the sum from the adder to the output register where it forms the mantissa of the floating-point number. 6. A device according to claim 5, characterized in that CIN on the adder is put to one. 7. A device according to claim 5 or 6, characterized in that all bits in the mantissa of the logarithm are arranged to be guided the first part circuit, bit number two and the following are arranged to be guided to the possibly existing second part circuit, bit number three and the following are arranged to be guided to the possibly existing third part circuit and so forth. 8. A device according to claim 7, characterized in that every part circuit comprises a number of XOR-gates, to the number of one less than the number of bits that are guided to the part circuit in question, at which the most significant bit of the bits that are guided to each part circuit is arranged to be guided to an inverter and then to the first input of all XOR-gates of this part circuit and the second bit is arranged to be guided to the second input of the first XOR-gate of this part circuit, the third bit to the second input of the second XOR-gate of this part circuit, the fourth bit to the second input of the third XOR-gate of this part circuit and so forth. 9. A device according to claim 4 or 8, characterized in that the output signals from the XOR-gates are arranged to be multiplied with a suitable scale factor, the constants Cj, C2 etc. 10. A device according to one of the previous claims, characterized in that the different additional parts are arranged to be added in parallel . 11. A device according to one of the previous claims, characterized in that the device is designed to use constants that are even powers of two and to carry out the multiplication with the help of the routing. 12. A device according to claim 11, characterized in that the device is arranged to use only one part circuit, which gives only one addi¬ tional part, to use the constant 0,25, ec = 0,01fc,-j n , and to carry out the multiplication by adding in the adder the additional part shifted two steps to the mantissa of the floating-point number. 13. A device according to one of the claims 11 or 12, characterized in that it is carried out as an Application Specific Integrated Circuit.

Inventors: HERTZ ERIK, HERTZ, ERIK
Applicants: FOERSVARETS FORSKNINGSANSTALT, HERTZ ERIK, HERTZ, ERIK
Application year: 1993
Main classification: H03M7
IPC codes: G06F7, G06F17, H03M7