Non-voltaile memory device having means for supplying negative programming voltages

Abstract: A method for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device provides for charging a capacitor (C;C1-Cn) to a positive high voltage by connecting, through first switching means (TX,TY;TE1-TEn,TF1-TFn), a first plate (A;A1-An) of the capacitor (C;C1-Cn) to a positive high-voltage supply (Vpp) and connecting, through second switching means (TB;TZ;TD1-TDn), a second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn), which is also operatively connected to the control gate of at least one memory cell, to a reference voltage supply (GND), and for successively connecting, through said first switching means (TX,TY;TE1-TEn,TF1-TFn) the first plate (A;A1-An) of the capacitor (C;C1-Cn) to the reference voltage supply (GND) and disconnecting the second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn) from the reference voltage supply (GND) to obtain a negative voltage on said second plate (B;B';B1-Bn) voltage.

Description: The present invention relates to a non-volatile memory device comprising a structure for supplying negative programming voltages to non-volatile memory cells in said non-volatile memory device. It is known that EEPROM and Flash EEPROM memory devices can be programmed in one or another of two logical states by respectively introducing electrons into or removing electrons from the memory cells' floating gates. This latter operation is termed "writing" in EEPROMs, while in Flash EEPROMs it is referred to as "erasure". The removal of electrons from a cell's floating gate is accomplished by tunnelling electrons from the floating gate into an underlying N+ diffusion, which in the case of a Flash EEPROM device constitute the source region of the cell while in an EEPROM device can represent either the source or the drain region of the cell, through a thin oxide region called "tunnel oxide"; electron tunnelling takes place if the potential difference between the floating gate and said underlying diffusion is made negative and its absolute value exceeds a value depending on the cells' characteristics. A common technique provides for grounding the cell's control gate (which is capacitively coupled to the floating gate), while raising the underlying diffusion potential to a value generally higher than 10 V. When however the diffusion potential is raised to such values, band-to-band tunnelling causes significant leakage currents to appear, thereby making it impossible to program the memory device by just supplying it one single voltage supply, or to use the memory device in a battery-supplied environment. To overcome such a problem, a different technique has been introduced, which provides for lowering the control gate potential to a negative value (with respect to the ground reference voltage) ranging from -6 V to -8 V and generated by a circuitry internal to the memory device, and raising the potential of the N+ diffusion under the tunnel oxide to a moderately high value, for example corresponding to the voltage supply value of the memory device. A circuit implementing this technique is described in the US Patent 5,077,691, and comprises three P-channel MOSFETs, two of which are connected in series between the output of a positive high voltage (Vpp) source and an N-channel MOSFET having a source connected to ground, while the third is connected between the common node of the previous two MOSFETs and the output of a negative high voltage (Vnn) source; the common node to which the three MOSFETs are connected represents a control gate line or word line which is connected to the control gates of the cells to be programmed; the Vpp and Vnn sources are constituted by charge pumps or voltage boosters internal to the memory device, and generally located at the periphery of the chip. To transfer electrons to the floating gates of the cells to be programmed, the charge pump for generating Vpp is activated, and the MOSFET connected between Vpp and the control gate line is on; the remaining two MOSFETs are instead kept off, and the charge pump for generating Vnn is deactivated. It is thus possible to transfer the voltage Vpp to the control gate line. To remove electrons from the floating gates of the cells to be programmed, the charge pump generating Vnn is activated, the two serially-connected MOSFET are kept off, and the third MOSFET is on, so that Vnn can be transferred to the control gate line. The voltage effectively transferred to the control gate line is actually given by the voltage applied to the gate of the third MOSFET minus the MOSFET threshold voltage (which is negative since P-channel MOSFETs are used); the gate voltage of the third MOSFET is never equal to Vnn, since voltage drops always occur between the output of the Vnn charge pump and the gate of the third MOSFET, due to the long interconnection line and the presence of selection transistors: the gate voltage of the third MOSFET is therefore, in an absolute value sense, lower than Vnn. Since moreover the third MOSFET has its source connected to the control gate line and the body (i.e. the N well in which the P-channel MOSFETs are obtained) connected to ground, the MOSFET threshold voltage increases (in absolute value) and the voltage effectively transferred to the control gate line can be 2 or 3 V higher than the voltage applied to the gate of the MOSFET. This value could be not sufficiently negative to start tunnelling of electrons. A possible solution to the abovementioned problem provides for voltage boosting the gate of the third MOSFET, at the expense of an increase in both the complexity of the circuit and in the total memory chip area. US-A-5,077,691 discloses a Flash EEPROM device with a memory cell array, a +12V charge pump, a -2V charge pump, a -12V charge pump, and a plurality of gate switch circuits, one for each word line of the array, for selectively coupling the respective word line to either the +12V, or the -2V, or the -12V common voltage rails. US-A-4,797,899 discloses a monolithic integrated circuit including a positive voltage doubler, a voltage inverting portion for generating a negative voltage, and in RS-232-transmitter/receiver. The capacitors for the positive voltage doubler and the inverting circuit portion are not integrated in the chip, but are external. EP-A-0 456 623 discloses a Flash EEPROM memory having a unique negative charge pump, coupled to the word lines through respective MOSFETs, each MOSFET being controlled by a respective bootstrapping circuit. In view of the state of the art just described, the object of the present invention is to provide a structure for supplying negative voltages to non-volatile memory cells in a non-volatile memory device which, without increasing significantly the total chip area, is not affected by the abovementioned problems. According to the present invention, such object is attained by means of a non-volatile memory device as set forth in claim 1. Thanks to the above mentioned structure, said elementary circuit occupies a limited area making it possible to accomplish a memory device in which each word line is closely connected, at its ends, to a respective elementary circuit (which works as a "local" negative voltage charge pump) so that the negative voltage required to program the memory cells connected to a selected word line is generated directly on such word line; in this case, it is only necessary to provide the memory device with a positive voltage charge pump. The features of the present invention shall be made more evident by the following detailed description of an embodiment, illustrated as a non-limiting example in the annexed drawing, wherein: Figure 1 is a schematic diagram of a structure according to an embodiment of the invention. In Figure 1, an elementary circuit 1 according to the invention for generating a negative voltage starting from a positive high voltage supply Vpp is shown. The circuit 1 comprises a first MOSFET TX whose drain and source are respectively connected to a positive high voltage supply line Vpp and to a first node A, a second MOSFET TY with drain and source respectively connected to node A and to a reference voltage line GND, a third MOSFET TB whose drain and source are respectively connected to the reference voltage line GND and to a second node B representing a negative voltage output of the elementary circuit 1 and to which in this embodiment a control gate line CG (constituting a word line of the memory matrix) is also connected, and a capacitor C connected between node A and node B. Non-volatile memory cells (not shown) are connected to the control gate line CG by their control gates. A fourth MOSFET TA with source and drain respectively connected to Vpp and to node B is also shown, and is used in a per se know way to transfer to the control gate line CG the voltage Vpp when electrons are to be transferred to the floating gates of the memory cells connected to CG. TA and TB are P-channel MOSFETs, while in the example of Figure 1 TX and TY are high-voltage N-channel MOSFETs, but could as well be both P-channel MOSFETs, or one a P-channel and the other an N-channel MOSFET. The high voltage supply line Vpp can be connected to an external high-voltage supply, or to the output of a conventional charge pump not shown in the drawings, which starting from a supply voltage applied externally to the memory device raises it to a value sufficient to determine the transfer of electrons, either by tunnelling (EEPROMs) or by hot electrons injection (Flash EEPROMs) to the floating gates of the memory cells. Said charge pump is normally located at the periphery of the memory device chip. When electrons are to be transferred to a floating gate of a selected cell whose control gate is connected to the control gate line CG, TA is turned on by applying to its gate electrode the reference voltage GND, while TB is kept off by applying to its gate electrode the high voltage Vpp. In this condition the control gate line CG voltage is raised to Vpp. In order to reduce the parasitic capacitances to be charged in this phase, TX and TY should also be kept in the off state so that node A is left floating. When electrons are to be extracted from a floating gate of a selected cell belonging to the word line CG, TA is turned off, while TB and TX are turned on by applying to their gate electrodes the voltages GND and Vpp, respectively; this causes node A to be connected to Vpp and node B to be grounded; this fact determines the charging of capacitor C to the voltage Vpp. Obviously, in the case that TX is a P-channel MOSFET, the reference voltage GND must be applied to its gate electrode to turn TX on. After capacitor C has been charged, TX and TB are turned off and TY is turned on, so that the potential on node A is lowered from Vpp to ground. This causes, by charge conservation, the potential on node B (i.e. on the control gate line CG) to drop to a negative potential given by the partition of the charge stored in the capacitor C between C and the parasitic capacitances associated to the control gate line CG, and to TA and TB: the higher the value of C compared to said parasitic capacitances, the better said negative potential approximates -Vpp. Since the control gate capacitance of a memory cell is essentially determined by the active area region of the cell (which actually represents a small portion of the total cell area), and since negative potentials on the control gate line CG ranging from -0.5Vpp to -0.7Vpp are sufficient to start electron tunnelling, the value of capacitor C does not have to be very high, and the total memory chip area is not exagerately increased. If for example the memory device is fabricated in a 0.8 µm technology and the capacitor C is obtained using as plates the two polysilicon layers constituting the floating gate and the control gate of the memory cells, a negative potential of about -0.5Vpp can be obtaned on the control gate line CG provided that C has at least an area of 3 µm 2 per bit, i.e. per each cell connected to the control gate line CG; this value should be compared to the cell's area, which in the case of an EEPROM device ranges from 15 µm 2 to 20 µm 2 . while for Flash EEPROMs it ranges from 7 µm 2 to 12 µm 2 . The capacitor C could also be obtained using as plates one polysilicon layer and an underlying N type diffusion. As a third possibility, the capacitor can be obtained between a polysilicon layer and an inversion layer in the P-type substrate since potential on node A never falls to negative values. The MOSFET TA must be able to sustain a voltage of 2Vpp between source and drain; alternatively, the source of MOSFET TA could be disconnencted from the output of the charge pump generating Vpp before TY is turned on. Furthermore, it is possible to control the shape of the voltage pulse applied to CG, i.e. to sharpen or to smooth its edges, by just modulating the conductivity of TY. By providing each word line of the memory matrix with a respective elementary circuit 1, no negative voltage charge pumps are required to program the memory cells, since the negative voltage is generated directly on the selected word line of cells to be programmed by the elementary circuit 1.

Claims: A non-volatile memory device comprising a structure for supplying negative programming voltages to non-volatile memory cells in said non-volatile memory device, said non-volatile memory cells each comprising a floating gate and a control gate, said matrix comprising a plurality of word lines (CG) each of which is connected to a plurality of control gates of respective memory cells, characterized in that said structure comprises a plurality of elementary circuits (1;2;VB1-VBn) each elementary circuit being constituted by a capacitor (C), first switching means (TX,TY) for alternatively connecting a first plate (A) of the capacitor (C) to a positive high-voltage supply (Vpp) or to a reference voltage supply (GND), and second switching means (TB) for respectively connecting or disconnecting a second plate (B) of the capacitor (C), which second plate is also connected to at least one word line, to the reference voltage supply (GND), the second plate (B) of the capacitor (C) of each elementary circuit being directly connected to a respective word line (CG) to supply said word line (CG) with a negative voltage suitable to remove electrons stored on the floating gates of the memory cells connected to said word line (CG). The device according to claim 1, characterized in that said first switching means comprises a first transistor (TX) connected between the positive high voltage supply (Vpp) and the first plate (A) of the capacitor (C) and a second transistor (TY) connected between said first plate (A) and the reference voltage supply (GND), and the second switching means comprises a third transistor (TB) connected between the second plate (B) of the capacitor (C) and the reference voltage supply (GND). The device according to claim 2, characterized in that said first (TX) and second (TY) transistors are N-channel MOSFETs, while said third transistor (TB) is a P-channel MOSFET. The device according to claim 2, characterized in that said first (TX), second (TY) and third (TB) transistors are P-channel MOSFETs. The device according to claim 2, characterized in that said first (TX) and third (TB) transistors are P-channel MOSFETs, while said second transistor (TY) is an N-channel MOSFET. The device according to claim 2, characterized in that said first transistor (TX) is an N-channel MOSFET, while said second (TY) and third (TB) transistors are P-channel MOSFETs. A device according to claim 1, characterized in that said capacitor (C) has the first plate (A) represented by a first polysilicon layer from which the floating gates of the memory cells are also obtained and the second plate (B) represented by a second polysilicon layer from which the control gates of the memory cells are also obtained. A device according to claim 1, characterized in that said capacitor (C) has the first plate (A) represented by a semiconductor region, and the second plate (B) represented by a polysilicon layer superimposed on and insulated from said semiconductor region by a dielectric layer.

Inventors: BALDI LIVIO, PIO FEDERICO, BALDI, LIVIO, PIO, FEDERICO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C16
IPC codes: H01L29, H01L21, G11C16, H01L27, G11C17