Look up table implementation of fast carry for adders and counters

Abstract: Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter.

Description: Background of the Invention This invention relates to logic devices employing look up tables, and more particularly to improving ways of providing fast carry functions in such devices when the devices are to be used for such purposes as performing addition, subtraction, and counting. Programmable logic devices are known in which programmable look up tables are used to perform relatively elementary logic functions (see, for example, Wahlstrom US patent 3,473,160 (Figure 8) and commonly assigned US patent 5,260,610). A look up table may provide as an output any desired logical function of several inputs. The outputs of several such look up tables may be combined (e.g. by other similar look up tables) in any desired way to perform much more complex logic functions. Look up tables which are a good size for performing many elementary logic functions in programmable logic devices tend to be too large for performing the extremely simple functions required to provide two-input adders (including subtracters) and various kinds of counters. For example, four-input look up tables are a very good size for general use, but are larger than necessary for use in the individual binary places of adders and counters. Nevertheless, adders and counters are very often required in digital logic. It is therefore wasteful to use four-input look up tables for adders and counters. This is especially so when fast carry logic is used because for each binary place one four-input look up table is required to provide the sum out bit, and another four-input look up table is required to provide the carry out bit. Neither of these look up tables is being fully utilized. Moreover, if large numbers of bit positions or places are required, the need to use two look up tables per bit position may exact a significant speed penalty because of the extensive use which must be made of the interconnect circuitry to interconnect the large number of look up tables involved. In view of the foregoing, it is an object of this invention to provide improved ways of implementing adders (including subtracters) and counters in programmable logic devices made up of programmable look up tables. It is a more particular object of this invention to provide programmable logic devices made up of look up tables in which adders and counters can be implemented more efficiently and with less waste of look up table resources. It is still another more particular object of this invention to provide ways of achieving faster adders and counters in programmable logic devices made up of look up tables. Summary of the Invention According to the invention as defined in claim 1 there is provided a programmable look up table apparatus which includes a plurality of programmable data storage cells, each of which produces a cell output signal indicative of the data stored in that cell, and normal selecting circuitry for normally selecting from all of said cell output signals any one of said cell output signals as a normal output signal on a normal output lead of said look up table apparatus, said normal selecting circuity being responsive to a plurality of input signals such that each of said input signals normally controls a respective one of a plurality of successive selection subcircuits which collectively comprise said normal selecting circuitry, a first of said selection subcircuits selecting one of two mutually exclusive and collectively exhaustive subsets of said cell output signals, and each succeeding selection subcircuit selecting one of two mutually exclusive and collectively exhaustive subsets of the cell output signals selected by the preceding selection subcircuit until a final one of said selection subcircuits produces said normal output signal on said normal output lead, characterised by: a first group of said programmable data storage cells for providing sum out digit signals; a second group of said programmable data storage cells for providing carry out digit signals; an auxiliary output lead separate from said normal output lead; first selection circuitry comprised of a plurality of portions of said selection subcircuits and responsive to a carry in digit signal and two binary digit signals for providing on said normal output lead one of: (1) a sum out digit signal from said first group of said programmable data storage cells, and (2) a carry out digit signal from said second group of said programmable data storage cells when said look up table apparatus is used to perform addition; and second selection circuitry comprised of a plurality of portions of said selection subcircuits distinct from said plurality of portions of said selection subcircuits in said first selection circuity and responsive to said carry in digit signal and said two binary digit signals for providing on the auxiliary output lead the other one of: (1) said sum out digit signal from said first group of said programmable data storage cells, and (2) said carry out digit signal from said second group of said programmable data storage cells when said look up table apparatus is used to perform addition. Additionally, logic may be added to selectively feed back the output of a flip-flop associated with each look up table to an input of that look up table to facilitate the use of the look up table as a counter stage. Still further logic may be added to facilitate loading and/or clearing of the flip-flop associated with each look up table to simplify the provisions of loadable and/or clearable counters. Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments. Brief description of the Drawings Figure 1 is a schematic block diagram of illustrative prior art look up table apparatus; Figure 2 is a schematic block diagram illustrating how the look up table of Figure 1 can be modified in accordance with the principles of this invention; and Figure 3 is a schematic block diagram of illustrative apparatus constructed in accordance with this invention which uses the look up table apparatus of Figure 2. Detailed Description of the Preferred Embodiments Figure 1 shows a conventional four-input look up table 10. Look up table 10 has 16 storage locations or function control elements ("FCEs") 12-1 through 12-16, each of which stores one binary digit of information. Each FCE 12 may be a flip-flop (as in FIG. 8 of Wahlstrom U.S. patent 3,473,160), a random access memory ("RAM") cell, or any other type of storage device such as an SRAM, a DRAM, a cell of a first-in first out ("FIFO") memory, an EPROM, an EEPROM, a ferro-electric memory cell, a fuse (e.g., a laser fuse), an anti-fuse, or the like. The contents of FCEs 12 may be fixed or programmable, and if programmable may be programmable only once or repeatedly. The logic connected to the outputs of FCEs 12 allows the four inputs J-M to select one and only one of the FCE outputs as the final output O/P of the look up table. The output of each FCE 12 is applied to one input of a respective one of AND gates 14-1 through 14-16. Input J is applied to the other input of AND gates 14-1, 14-3, 14-5, 14-7, 14-9, 14-11, 14-13, and 14-15, and, after inversion by inverter I1, to the other input of AND gates 14-2, 14-4, 14-6, 14-8, 14-10, 14-12, 14-14, and 14-16. Accordingly, half of AND gates 14 are enabled by input J, while the other half of these AND gates are not enabled. OR gates 16 pass the outputs of enabled AND gates 14 to the next level of AND gates 18. Input K is applied to one input of AND gates 18-1, 18-3, 18-5, and 18-7, and, after inversion by inverter I2, to one input of AND gates 18-2, 18-4, 18-6, and 18-8. Accordingly, input K enables half of AND gates 18 and disables the other half of those AND gates. Input K therefore selects four of the eight FCE 12 outputs selected by input J. OR gates 20 pass the four FCE outputs selected by input K to the next level of AND gates 22. Input L is applied to one input of AND gates 22-1 and 22-3, and, after inversion by inverter I3, to one input of AND gates 22-2 and 22-4. Input L therefore enables half of AND gates 22 and disables the other half of those AND gates. Accordingly, input L selects two of the four FCE 12 outputs selected by input K. OR gates 24 pass the two FCE outputs selected by input L to the next level of AND gates 26. Input M is applied to one input of AND gate 26-1, and, after inversion by inverter I4, to one input of AND gate 26-2. Accordingly, input M makes a final selection of one of the two FCE 12 outputs selected by input L. OR gate 28 passes this finally selected FCE output to look up table output lead O/P. It will be apparent from the foregoing that look up table 10 can provide any single logical function of its four inputs J-M. For example, if it is desired that the output of look up table 10 should be 1 when J and L are 0 and K and M are 1, then FCE 12-6 is programmed or otherwise set to store binary 1 so that this value will appear at output O/P when AND gates 14-6, 18-3, 22-2, and 26-1 are enabled. If look up table 10 is to be used as one stage of a two-input adder (which term is used herein as a generic term for both adders and subtracters), it really has more capabilities than are needed to provide either the sum out or carry out value. Accordingly, look up table 10 is modified in accordance with this invention as shown in FIG. 2 so that it can provide both the sum out on normal output lead O/P and important precedents to the carry out value on leads X and Y. Prior art input K is split into two inputs K and K'. Input K continues to be applied in true or complement form to AND gates 18-5 through 18-8. Input K' is applied in true form to AND gates 18-1 and 18-3, and in complement form provided by inverter I2' to AND gates 18-2 and 18-4. An additional switch 170 is included between the output of OR gate 24-2 and the input of AND gate 26-2. Switch 170 is controlled by FCE 172 (which can be similar to any of FCEs 12) to apply either the output of OR gate 24-2 or the "data" input to AND gate 26-2. When look up table 10 is used as part of a loadable counter, the "data" input to switch 170 is used as the source of the data to be loaded into the counter. Figure 3 shows how the modified look up table 10 of Figure 2 can be used with other circuitry in accordance with this invention to provide an extremely flexible and powerful logic module 8 for use in programmable logic arrays (e.g. the logic arrays shown in commonly assigned US patent 5,260,611). Logic module 8 has four regular data inputs A-D. It also has a carry in input, typically from the carry out output of another adjacent logic module which is used for the next less significant arithmetic place when logic module 8 is used for one place of binary addition, subtraction, or counting. The remaining input to logic module 8 is the cascade connect input, also typically from another adjacent logic module. As described in commonly assigned US patent 5,258,668, the cascade connect input allows the cascade connect output signal of another logic module to be combined with the output of look up table 10 in logic module 8 if that is desired. Logic module 8 has three outputs. These are its regular data output from output driver 202, the cascade connect output which bypasses elements 196 through 202, and the carry out signal. The cascade connect output signal of logic module 8 is applied to the cascade connect input of another, typically adjacent logic module. The carry out signal of logic module 8 is similarly applied to the carry in input of another, typically adjacent logic module which performs the next more significant place of binary addition, subtraction, or counting when any of those operations are performed. When logic module 8 is used to perform normal logic rather than addition, subtraction, or counting, switch 120 is controlled by FCE 122 to apply the A input of the logic module to the J input of look up table 10, switch 124 is controlled by FCE 126 to apply the B input to the K' as well as the K inputs of table 10, and switch 128 is controlled by FCE 130 to apply the C input to the L input of table 10. (FCEs 122,126 and 130 may be similar to any of the above-described FCEs). The D input is applied at all times to the M input of table 10. Switch 170 is controlled by FCE 172 to apply the output of look up table portion 10b to switch 26/28, and switch 174 is controlled by FCE 176 to apply the cascade connect input to AND gate 178. (Again, FCEs 172 and 176 may be similar to any of the above-described FCEs). As is discussed in above-mentioned US patent 5,258,668, the cascade connect input may be tied to logic 1 by other elements not shown herein if the cascade connect feature is not being used. As a result of the foregoing, look up table 10 in Figure 3 operates just like the prior art look up table 10 in Figure 1 and can produce any logical function of inputs A-D. The output signal of look up table 10 is applied to AND gate 178. After inversion and level adjustment by circuit 194, the output signal of AND gate 178 is applied to the main data output terminal of logic module 8 either directly or via flip-flop 196 as determined by switch 198 which is controlled by FCE 200 (similar to any of the above-described FCEs). The output signal of circuit 194 is also applied to the cascade connect output terminal of the logic module. When it is desired to use logic module 8 to perform one place of binary addition, the two digits to be added are applied to the A and B inputs. The carry from the next less significant place of the addition operation (preferably performed by another logic module similar to logic module 8) is applied to the carry in input. (Above-mentioned US patent 5,260,611, which is hereby incorporated by reference herein, shows how multiple logic modules can be connected to one another in a carry chain when operations such as addition, subtraction, and counting are to be performed). Switches 120,124 and 174 are set as described above for normal logic, but switch 128 is set to apply the carry in input to the L input of table 10, and also to the control input of switch 160. The setting of switch 170 is of no consequence. The cascade connect input is tied to logic 1. Input D is used to control switch 26/28 to apply the output of look up table portion 10a to AND gate 178. The FCEs of look up table portion 10a (generally the portion above chain dotted line 11 in Figure 2) are programmed to apply the sum of A,B and carry in to switch 26/28. This sum out signal passes through elements 26/28,178,194, etc., to the main output terminal for the logic module. The FCEs 12 of look up table portion 10b (generally the portion below chain dotted line 11 in Figure 2) are programmed to provide the NOR and NAND of A and B on leads X and Y. These signals are inverted by inverters 156 and 158, and switch 160 selects the appropriate one for use as the carry out signal based on the carry in signal which controls that switch. The carry out signal of this logic module is the carry in signal of another similar logic module which performs the next more significant place of the arithmetic operation. (See again above mentioned US patent 5,260,611, which shows how the carry out signal of each logic module is connected as the carry in signal of the arithmetically next more significant logic module). Accordingly, with the modifications described above, a single logic module 8 can provide both the sum out and carry out signals for one place of binary addition. Another capability of logic module 8 in accordance with this invention is to provide one stage of a binary up/down counter which can also be loaded to any value. This counter stage operates by adding the Q output of flip-flop 196 and the carry in input from the logic module providing the next less significant counting stage. Accordingly, switches 198 and 120 are set to apply the Q output to look up table input J, switch 124 is set to apply the A input to look up table input K', and switch 128 is set to apply the carry in input to look up table input L. Input B continues to be applied to look up table input K, input C continues to be applied to switch 170, and input D continues to be applied to look up table input M to control switch 26/28. Switch 170 is programmed to pass the applied C input to switch 26/28. Switch 174 is set to apply the cascade connect input to one input of AND gate 178. The cascade connect input signal is tied to logic 1 as described above. The FCEs 12 of look up table portion 10a are programmed so that the A input can selectively enable counting. The FCEs 12 of look up table portion 10b are programmed so that the B input can control whether the counter counts up or down. The up/down counter can be loaded with data from input C by using input D to momentarily cause switch 26/28 to apply the output of switch 170 to AND gate 178. Flip-flop 196 stores the output of AND gate 178 synchronously or asynchronously, depending on how the flip-flop is configured and what control signals are applied to it. Still another capability of logic module 8 in accordance with this invention is to provide one stage of a clearable binary counter which can also be loaded to any value. This type of counter also counts by adding its Q output to the carry in input from the counter stage of next lower numerical significance. Unlike the above-described up/down counter, however, the clearable counter can only count up. To provide the clearable counter, switches 120, 124, 128, 170, and 198 are all set as described above for the up/down counter. Switch 174 is set to apply the B input to AND gate 178. The FCEs 12 of look up table portion 10a are programmed so that input A can selectively enable the counting action. Input B must also be logic 1 for the counter to count or hold its count. When it is desired to clear the counter, input B is switched to logic 0 which applies to 0 to the D input of flip-flop 196. Again, this clears flip-flop 196 either synchronously or asynchronously, depending on how the flip-flop is configured and what control signals are applied to it. The counter can be loaded with any desired value from the C input in the same way that the up/down counter can be loaded. It will be understood that the foregoing is merely illustrative of the principles of this invention, and that various modifications can be made by those skilled in the art without departing from the scope of the invention as defined in the claims. For example, there are many other ways in which the apparatus of this invention can be configured and/or programmed to perform the functions described above. As one illustration of this, X and Y could be the NOR and NAND of one of inputs A and B and the carry in input, with the other one of inputs A and B being used to control switch 160.

Claims: A programmable look up table apparatus which includes a plurality of programmable data storage cells (12-1 ..., 12-16), each of which produces a cell output signal indicative of the data stored in that cell, and normal selecting circuitry for normally selecting from all of said cell output signals any one of said cell output signals as a normal output signal on a normal output lead (O/P) of said look up table apparatus, said normal selecting circuitry being responsive to a plurality of input signals (J,K,L,M) such that each of said input signals normally controls a respective one of a plurality of successive selection subcircuits (14-1, ..., 14-16, 16-1, ..., 16-8, 18-1, ..., 18-8, 20-1 ..., 20-4, 22-1, ..., 22-4, 24-1, 24-2, 26-1, 26-2, 28) which collectively comprise said normal selecting circuitry, a first of said selection subcircuits selecting one of two mutually exclusive and collectively exhaustive subsets of said cell output signals, and each succeeding selection subcircuit selecting one of two mutually exclusive and collectively exhaustive subsets of the cell output signals selected by the preceding selection subcircuit until a final one of said selection subcircuits produces said normal output signal on said normal output lead, characterised by: a first group of said programmable data storage cells (12-1, 12-2, ..., 12-8) for providing sum out digit signals; a second group of said programmable data storage cells (12-9, 12-10 ..., 12-16) for providing carry out digit signals; an auxiliary output lead (CARRY OUT) separate from said normal output lead (O/P); first selection circuitry (14-1, 14-2, ..., 14-8, 16-1, 16-2, ..., 16-4, 18-1, 18-2, ..., 18-4, 20-1, 20-2, 22-1, 22-2, 24-1, 26-1, 28) comprised of a plurality of portions of said selection subcircuits and responsive to a carry in digit signal and two binary digit signals for providing on said normal output lead one of : (1) a sum out digit signal from said first group of said programmable data storage cells, and (2) a carry out digit signal from said second group of said programmable data storage cells when said look up table apparatus is used to perform addition; and second selection circuitry (14-9, 14-10, ..., 14-16, 16-5, 16-6, ..., 16-8, 18-5, 18-6, ..., 18-8, 20-3, 20-4, X, Y, 156, 158, 160) comprised of a plurality of portions of said selection subcircuits distinct from said plurality of portions of said selection subcircuits in said first selection circuitry and responsive to said carry in digit signal and said two binary digit signals for providing on the auxiliary output lead the other one of: (1) said sum out digit signal from said first group of said programmable data storage cells, and (2) said carry out digit signal from said second group of said programmable data storage cells when said look up table apparatus is used to perform addition. The apparatus defined in claim 1 wherein said second selection circuitry further comprises: a first lead (X) connected to a predetermined one of said selection subcircuits (18-1 ..., 18-8, 20-1, ..., 20-4), wherein said predetermined one of said selection subcircuits (18-1 ..., 18-8, 20-1, ..., 20-4) provides on said first lead a first signal indicative of a first logical function of two of said two binary signals and said carry in digit signal; and a second lead (Y) connected to said predetermined one of said selection subcircuits (18-1, ..., 18-8, 20-1, ..., 20-4), wherein said predetermined one of said selection subcircuits (18-1, ..., 18-8, 20-1, ..., 20-4) provides on said second lead a second signal indicative of a second logical function of said two of said two binary digit signals and said carry in digit signal. The apparatus defined in claim 2, wherein said first signal is indicative of the logical NOR of said two of said two binary digit signals and said carry in digit signal and said second signal is indicative of the logical NAND of said two of said two binary digit signals and said carry in digit signal, said second selection circuitry further comprising a switch circuit (156, 158, 160) for using the remaining one of said two binary digit signals and said carry in digit signal to select one of said first and second signals as said carry out digit signal. The apparatus defined in claim 3, wherein said two of said two binary digit signals and said carry in digit signal are said two binary digit signals. The apparatus defined in claim 1 wherein said look up table apparatus (10) is a four-input look up table (10) for selecting any one of 16 programmable cell output signals stored in said programmable data storage cells (12-1, ..., 12-16) as the normal output signal on said normal output lead (O/P). The apparatus defined in claim 1 further comprising: a register (196) for storing the output signal which appears on said normal output lead (O/P); and a feedback path from said register for providing the output of said register as one of said input signals, wherein said look up table apparatus (10) forms one stage of a counter by accepting the carry in digit from a counter stage of lesser numerical significance as another of said input signals, said look up table apparatus combining the output of said register (196) and the carry in digit signal to produce a new count value on said normal output lead (O/P) and the carry out digit signal for application to a counter stage of greater numerical significance. The apparatus defined in claim 6, wherein a predetermined one of said selection subcircuits (18-1, 18-2, ..., 18-8, 20-1, 20-2, ..., 20-4) is divided into mutually exclusive first and second portions, said first portion (18-1, ..., 18-4, 20-1, 20-2) receiving a first predetermined control signal (K') and said second portion (18-5, ..., 18-8, 20-3, 20-4) receiving a second predetermined control signal (K). The apparatus defined in claim 7, wherein apparatus forms one stage of a binary up/down counter, said first predetermined control signal (K') selectively enabling counting and said second predetermined control signal (K) controlling the direction of counting. The apparatus defined in claim 8 further comprising: a data switch (170) having an output connected as an input to said final selection subcircuit (26-1, 26-2, 28) and first and second data switch inputs, said first data switch input normally receiving one of the two cell output signals from the selection subcircuit (22-1, 22-2, ..., 22-4, 24-1, 24-2) preceding said final selection subcircuit and said second data switch input (DATA) receiving data for loading into said binary up/down counter when said data switch (170) is switched to receive said data from said second data switch input (DATA). The apparatus defined in claim 7 wherein said apparatus forms one stage of a binary up counter, said first predetermined control signal (K') selectively enabling counting and said second predetermined control signal (K) controlling when the apparatus counts and when the apparatus is cleared. The apparatus defined in claim 10, further comprising: an AND gate (178) having a gate output connected to said register (196) and first and second gate inputs, said first gate input being connected to said normal output lead (O/P) and said second gate input being connected to receive said second predetermined control signal, wherein said AND gate provides the signal from said normal output lead to said register during counting and said AND gate provides a logic O to said register when a logic O is applied to said second gate input as said second predetermined control signal to clear said counter.

Inventors: CLIFF RICHARD G, COPE L TODD, PEDERSEN BRUCE B, VEENSTRA KERRY, CLIFF, RICHARD G., COPE, L. TODD, PEDERSEN, BRUCE B., VEENSTRA, KERRY
Applicants: ALTERA CORP, ALTERA CORPORATION
Application year: 1993
Main classification: G06F7
IPC codes: H03K19, H03K23, G06F1, G06F7, H03K21