Multiple-metal-level integrated device and fabrication process thereof

Abstract: An integrated device (1) comprising two metal levels (6, 8) separated by a layer of insulating material (3) and connected (10) electrically at respective contact pads (5, 7) located one over the other. The two pads (5, 7) are connected electrically by a number of parallel contact regions (10) having a much smaller cross sectional area as compared with the contact pads (5, 7). The contact regions (10) are so formed as to terminate close to the side of the lower contact pad (5) from which a respective metal line (4) extends, and are covered by the final passivation layer (12).

Description: The present invention relates to a multiple-metal-level integrated device and fabrication process thereof, according to the preamble of claim 1 and, respectively, claim 3. As known, when fabricating integrated devices comprising thin oxide layers, these are subject to damage at various stages of the dry etching processes, thus impairing the efficiency and/or reliability of the devices. Especially critical is the plasma etching process for forming the contacts between the lower metal levels and the upper level. On multiple-metal-level devices, in fact, the bottom layers are contacted by means of an electric connecting structure through the intermediate insulating layers. In particular, in the areas in which the electric contacts of the device are formed, the underlying metal levels are patterned into bonding pads of appropriate and fairly extensive area, and the contacts are formed by plasma etching the intermediate dielectric layers over the pads, so as to form openings with a cross section of slightly less than the pad area, and then depositing a metal layer to fill the openings and form the contact. Plasma etching the contacts towards the first metal level is especially critical by virtue of the first level, at which etching is stopped, contacting the thin oxide layers (less than 150 Å thick for tunnel oxides, and not much thicker for gate oxides), and being connected to the upper armatures of the capacitors. The extensive contact area of the bonding pads permits capture by the metal pad of a substantial electric charge (antenna effect) highly capable of resulting in electrostatic discharge through the thin oxide layers. To safeguard the thin oxides against electric discharge, provision is currently made for structures formed on the same die and designed to absorb high voltage peaks without transferring them to the active circuits. Such structures, however, are not provided on process characterization test devices, particularly for direct measurement of the deficiency and reliability of the oxide layers, so that, in these cases at least, other techniques are required for safeguarding the oxide layers during fabrication. In general, however, straightforward structures are desirable, capable of eliminating or at least partly solving the problem of electrostatic discharge resulting from the capture of electric charges. An integrated device of the type defined in the preamble of claim 1 is disclosed in EP-A-0 519 665, wherein, for planarizing a multi-layer metal bonding, a contact structure is proposed, including a plurality of metal layers and interposed dielectric layers having a multitude of vias. The vias extend at the entire surface of the pad. also under the contact opening in the protection layer. Thus this known device does not solve the above explained problem of electrostatic discharge. The object of the present invention is to avoid these disadvantages It is an object of the present invention to provide a device and fabrication process thereof designed to solve the above problem. According to the present invention, there is provided a device as claimed in Claim 1. According to the present invention, there is also provided an integrated device fabrication process as claimed in Claim 3. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Fig.1 shows a plan view of a portion of one embodiment of an integrated device in accordance with the present invention; Fig.2 shows a cross section of the Fig.1 device. Number 1 in the accompanying drawings indicates an integrated device of which is shown only the portion wherein a metal line forming part of the first metal level is connected. Device 1 comprises in known manner a substrate 2 of semiconductor material underlying an oxide layer 3 fully surrounding, at least in the portion shown, a metal line 4 terminating at a first pad 5 of a given area (typically 50-150 µm square). Metal line 4 and pad 5 form part of a first metal level indicated as a whole by 6. Over oxide layer 3, there is provided a second pad 7 forming part of a second metal level (indicated as a whole by 8), and located over and of substantially the same area as first pad 5. According to the present invention, pads 5 and 7 are mutually connected by a number of small-area contact regions 10 through oxide layer 3, and the size of which (ranging from 0.5 to 3 µm) depends on the fabrication process employed. Over second metal level 8, there is provided a passivation layer 12 having an opening 13 at top pad 8, for welding the pad by means of a wire (not shown) to a pin (not shown) at the final assembly stage. As shown particularly in Fig.2, contact regions 10 (also known as "vias") are located close to the edge of pads 5, 7 for protection by the final passivation layer; and are aligned parallel and close to the edge from which metal line 4 originates, so as to enable uniform distribution of the injected current and prevent current crowding. The number of vias 10 depends on the maximum current of the structures connected over metal line 4 to pad 5. In general, the current density of vias made of aluminium alloy based metal is necessarily 2x10 5 A/cm 2 , and may be as high as 1x10 6 A/cm 2 for tungsten plugged types. The process for fabricating the Fig.1-2 structure is as follows. After being deposited in known manner, the first metal layer is masked and etched to form, in addition to the connecting lines, first-level pads 5 of conventional size and in normal manner. Using known deposition, heat treatment and etching techniques, the insulating layer between the two metal levels is then formed, and together with the oxide layer beneath the first metal level, forms layer 3. At this point, the vias between the two metal levels are opened by masking and subsequent etching. Thereby, according to the present invention, for each pad 5 a number of openings are formed, terminating at first pad 5, on the side from which the respective metal line originates, as already described. A metal layer is then deposited to fill the openings and produce vias 10 and, possibly, second metal level 8, and is subsequently masked to form the second-level metal lines (not shown) and top pads 7. Finally, passivation layer 12 is deposited and subsequently masked and patterned to expose top pads 7, with the exception of the periphery, and more specifically the portions overlying and protecting vias 10, to give the structure shown in the drawings. The advantages of the device and fabrication process according to the present invention will be clear from the foregoing description. Firstly, by virtue of contact between the two metal levels being achieved by means of a number of regions, the total area of which is considerably less than that of the respective pads (the area ratio of the pads and vias 10 typically ranges between 0.001 and 0.01), the possibility of electric charges being captured during the critical stages, particularly when plasma etching the vias, is drastically reduced. Secondly, location of the vias along the edge of the pads provides for protecting them by means of the passivation layer during the final fabrication stages of the device; while, as already stated, location along the side from which the respective metal line originates prevents current crowding. Thirdly, the structure as described involves no complex, high-cost alterations to fabrication processes or machinery, the fabrication process in fact requiring only redesigning of the mask for opening the vias. Finally, the solution described is both straightforward and reliable. To those skilled in the art it will be clear that changes may be made to the device and process as described and illustrated herein without, however, departing from the scope of the present invention. In particular, the number and area of the vias may vary depending on current flow, the materials used, and achievable process dimensions.

Claims: A multiple-metal-level integrated device (1) comprising: a substrate (2) of semiconductor material; at least one first metal level (6) overlying said substrate (2) and defining at least one metal line (4) terminating in a first contact pad (5), said first contact pad (5) being polygonal and presenting a perimeter; a second metal level (8) defining at least one second contact pad (7) substantially overlying said first contact pad (5); and a protection layer (12) extending over said second metal level (8) and having at least one opening at said second contact pad (7); said first and second contact pads (5, 7) being separated by a layer of insulating material (3) and being connected electrically by a contact structure (10) extending through said layer of insulating material and between said first and second contact pads, said contact structure comprising a number of parallel contact regions (10) having a much smaller cross sectional area as compared with said first and second contact pads (5, 7), characterized in that all said contact regions (10) are located close to said perimeter, beneath said protection layer (12), and are offset laterally with respect to said opening such that portions of said protection layer overlie said contact regions. A device as claimed in Claim 1, wherein said polygon of said first contact pad (5) comprises a side with which blends said at least one metal line (4); characterized in that said contact regions (10) terminate close to said side of said polygon. A process for fabricating an integrated device (1) as claimed in one of the foregoing Claims, said process comprising the steps of: forming, over a substrate (2) of semiconductor material, a first metal level (6) comprising at least one metal line (4) terminating in a first contact pad (5) shaped into a polygon having a perimeter forming a layer of insulating material (3) over said first metal level; forming, over said layer of insulating material, a second metal level comprising at least one second contact pad (7) substantially overlying said first contact pad; and forming, through said layer of insulating material, a contact structure (10) extending between and electrically connecting said first and second contact pads (5, 7), said contact structure comprising a number of parallel contact regions (10) having a much smaller cross sectional area as compared with said first and second pads (5, 7), forming a protection layer (12) extending over said second metal layer (8) and having at least one opening at said second contact pad (7); wherein said steps of forming said second metal level (8) and said contact structure (10) comprise the steps of forming, in said layer of insulating material (3), a number of openings having a much smaller area as compared with said first contact pad (5) and extending up to said first pad; depositing a metal layer (8) to fill said openings; and patterning said metal layer to form said second contact pad (7), characterized in that all said contact regions (10) are located close to said perimeter, beneath said protection layer (12), and are offset laterally with respect to said opening such that portions of said protection layer overlie said contact regions. A process according to claim 3, characterized in that said polygon of said first contact pad (5) comprises a side blending with said at least one metal line (4) and in that said contact regions (10) terminate close to said side of said polygon.

Inventors: CAPRILE CANDIDA, DE SANTI GIORGIO, CAPRILE, CANDIDA, DE SANTI, GIORGIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H01L23
IPC codes: H05K3, H01L23