Synchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallel

Abstract: A synchronous processing system including a plurality of processors (1) and a communication (2) network. Each processor (1) includes a synchronization combination storage element (11), a synchronous status storage element (12), a storage control element 8a, a synchronous judging element (13a) and a processing shifting element (8b). The synchronization combination storage element (11) stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element (12) stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element (8a) transmits the synchronous status information to all other processors (1). A judging element judges whether the group of processors are in synchronization based on the synchronization combination information and the transmitted status information. A processing shifting element (8b) shifts (when the group of processors are judged to be in synchronism) all the processors in the group to the next process of the program.

Description: The present invention relates to a synchronous processing method and apparatus for a plurality of processors, and more particularly, to a method and apparatus in which a plurality of processors execute a plurality of programs in parallel and in synchronism. In recent years, with demands for increases both in speed and in capacity of computer systems, there has been developed a distributed processing technology for distributing processes to a plurality of processors. For example, in multiprocessor systems, in which a plurality of processors are connected together, the respective processors can execute processes in parallel. In such multiprocessor systems the respective processors communicate with each other via a communications unit, operate in parallel and execute a certain batch process on the whole. By use of such multiprocessor systems, programs can be processed at higher speed. Furthermore, in previously proposed multtiprocessor systems the individual processors for effecting the parallel processing have to execute processes containing a plurality of phases in some cases. This synchronous processing is conducted by the following actions. To start with, the processor which has finished its processing the earliest detects that a synchronous waiting status is reached, and waits for an end of the processing by another processor before synchronization begins, i.e. this processor waits until all other processors reach the synchronous waiting status, so that the processors may become synchronized. Then, upon detecting that all the processors have reached the synchronous waiting status, all the processors execute the synchronization process discussed below. Synchronous processing is conducted by a synchronous processing element provided in each processor. This synchronous processing element includes a synchronous status register, a synchronous receiving element and a synchronous detecting element. At the first onset, the processor which has finished its processing earliest sets, in its synchronous status register, a piece of synchronous status information (e.g., "1") indicating that the processor has reached the synchronous waiting status. Then, this synchronous status information is transmitted via a communication unit to all other processors. The synchronous status information is set in the synchronous receiving elements in all other processors. Next, the processors which have finished their processings set the synchronous status information in their own synchronous status register. This synchronous status information is transmitted to all other processors. Further, the transmitted synchronous status information is set in the synchronous receiving elements in all of the other processors. Subsequently, the processor which has terminated its processing last sets the synchronous status information in its status register. This synchronous status information is then transmitted to the synchronous receiving elements in all other processors. At this point, the synchronous detecting element in each processor detects all of the synchronous status information, corresponding to the number of processors, which have been received in the synchronous receiving element. Then, the processors shift to the next processing on the assumption that all the processors are now synchronized. The above-mentioned synchronous processing element includes a synchronous status register, a synchronous receiving element and a synchronous detecting element, each capable only of storing the data "1". Therefore, only one process (one program) can be executed by one processor. Further, the synchronous processing element is incapable of assigning a certain program to one group of processors to be synchronized among the group of processors and assigning another program to a second group of processors to be synchronized among the second group. For this reason, it is impossible to execute, with high efficiency, a plurality of parallel processing programs. Another synchronous processing apparatus, described in EP-A-0475282, may be considered to comprise: a plurality of processing elements for executing processes of a plurality of programs, a group of the processing elements being assignable to a corresponding one of the programs so that processes of that program can be executed in parallel and in synchronism by the processing elements of the said processor-element group, each processing element belonging to such a group being operable, when it completes one of the said processes of the program corresponding to that group, to transmit synchronous status information indicating that it has reached a synchronization waiting status; communication means through which information is transferred between the processing elements of the said plurality; synchronization combination storage means for storing synchronization combination information indicating the processing elements of the said plurality that belong to such a group; synchronous receiving means for receiving the transmitted synchronous status information; synchronous judging means for judging whether such a group of processing elements are in synchronism based on the received synchronous status information transmitted from all of the said processing elements and on the said stored synchronization combination information; and shifting means operable, when said synchronous judging means judges that such a group of processing elements are in synchronism, to cause the processing elements of the group to execute a next process in the program corresponding to that group. In this apparatus, a synchronous processing circuit is provided in common for all the processing elements. This circuit receives synchronization status information from all of the processing elements as well as synchronization combination information indicating a group of processing elements required to operate in synchronizm. The circuit processes the two sets of information and applies a synchronization indicating signal to the processing elements of the group upon detecting that all the elements of the group have reached the synchronization waiting status. In this apparatus it is problematic to add additional processing elements to the apparatus because the capacity of the external synchronous processing circuit is confined to a certain number of processing elements. Synchronous processing apparatus embodying a first aspect of the present invention is characterised in that each said processing element of the said plurality includes synchronous processing means having: synchronous status storing means for storing the said synchronous status information of the processing element concerned; storage control means for controlling said synchronous status storing means to store said synchronous status information and for simultaneously transmitting said stored synchronous status information of the processing element concerned via the said communication means to all of the other processing elements of the said plurality; its own said synchronous receiving means for receiving the transmitted synchronous status information of each other processing element of the said plurality; its own said synchronous judging means for judging whether the processing elements of the group to which the processing element concerned belongs are in synchronism based on the received synchronous status information transmitted to the processing element concerned by the other processing elements of that group and also based on the synchronization combination information stored by the processing element concerned; and its own said shifting means operable, when the said synchronous judging means of the processing element concerned judges that such a group is in synchronism, to cause the processing element concerned to execute its next process in the program corresponding to that group, whereby the processing elements of that group are caused to execute the processes in the said corresponding program in parallel and in synchronism with one another. In such synchronous processing apparatus described above, for example, the program process may be executed while each processing element becomes synchronized by transferring the status information between the plurality of processing elements. The processing elements are, e.g., processors and the communication means are, e.g., a communication network. Further, a storage control element may cause the synchronous status storage element repeatedly and alternately to store synchronous status information "1" and synchronous status information "0" per processing. The storage control element may also cause the synchronization combination storage element to store the synchronization combination information. Further, the storage control element and the processing shift element may be provided in an instruction processing element for executing a plurality of instructions. The synchronous receiving element for receiving the synchronous status information transmitted from all the processing elements and for outputting the received synchronous status information to the synchronous judging element may be a register, the bit number of which corresponds to the number of the plurality of processing elements. This register stores, when receiving the synchronous status information, the synchronous status information in bit strings corresponding to the plurality of processing elements. The synchronous judging element may include a logic operation circuit for performing a logic operation between the synchronous status information given from the synchronous receiving element and the synchronization combination information given from the synchronization combination storage element, thereby determining whether the processing elements indicated by the synchronization combination information are synchronized. The synchronization combination storage element may be a register the bit number of which corresponds to the number of the plurality of processing elements. This register may store synchronous status information "1" in a bit string corresponding to all the processing elements indicated by the synchronization combination information among the bit strings corresponding to the plurality of processing elements. The processing shifting element may be provided with a synchronous indicating register for storing synchronous indicating information for indicating whether the processing elements indicated by the synchronization combination information are synchronized. provided further in the processing element may be a control register for allocating this register to each processing element. The control register may be a 1-bit register which allocates the processing elements to take two kinds of synchronization information in accordance with pieces of control information "1" and "0" for executing the processing of two programs. The synchronous receiving element may be provided with a parity error detecting element for detecting a parity error of the information on the broadcasting line through which the information is broadcasted to the respective processing elements. The processing elements, when the parity error detecting element detects the 1-bit error, may continue the processing without interrupting the processing of the programs. However, when further detecting a 1-bit error after detecting the former 1-bit error, the processing may be interrupted in the processing element. According to a second aspect of the present invention, there is provided synchronous processing apparatus comprising: a plurality of processing elements for executing processes of a plurality of programs, a group of the processing elements being assignable to a corresponding one of the programs so that processes of that program can be executed in parallel and in synchronism by the processing elements of the said group, each processing element belonging to such a group being operable, when it completes one of the said processes of the program corresponding to that group, to transmit synchronous status information indicating that it has reached a synchronization waiting status; communication means through which information is transferred between the processing elements of the said plurality; synchronous judging means for judging whether such a group of processing elements are in synchronism; and shifting means operable, when said synchronous judging means judges that such a group of processing elements are in synchronism, to cause that group of processing elements to execute a next process in the program corresponding to that group; characterised in that each said processing element of the said plurality includes synchronous processing means having: a plurality of synchronous status storage means, corresponding to different respective said programs, each of which programs has assigned thereto its own corresponding group of processing elements including the processing element concerned, and each said synchronous status storage means serving to store, for its said corresponding program, the said synchronous status information for the processing element concerned; storage control means for controlling the said synchronous status storage means of the said plurality to store the said synchronous status information and for simultaneously transmitting the said stored synchronous status information of the processing element concerned via the said communication means to all of the other processing elements of the said plurality; its own plurality of such synchronous judging means, corresponding respectively to the said synchronous status storage means of the said plurality, each operable to judge whether the processing elements of one of the said groups to which the processing element concerned belongs are in synchronism; and its own said shifting means operable, when any one of the said plurality of synchronous judging means of the processing element concerned judges that one of the said groups to which the processing element concerned belongs is in synchronism, to cause the processing element concerned to execute its next process in the program corresponding to that group, whereby that group of processing elements executes processes in the corresponding program in parallel and in synchronism. In this second aspect of the invention, the plurality of synchronous status storage elements are provided corresponding to a plurality of programs. The synchronous status storage elements respectively store synchronous status information showing that a synchronization waiting status is reached when a self-processing element finishes the processing. A storage control element may cause each of the plurality of synchronous status storage elements to store the synchronous status information and transmits the synchronous status information to all the processing elements. A plurality of synchronous judging elements are provided corresponding to the plurality of synchronous status storage elements. The synchronous judging elements respectively judge whether the other processing elements are synchronized. A processing shifting element, when any one of the plurality of synchronous judging elements judges that the processing elements are synchronized, shifts all the processing elements to the next processing of the program corresponding to that synchronous judging element. Provided further may be a selecting element for selecting any one of synchronous processing of a plurality of programs and synchronous processing of one program, which is to be performed by the plurality of synchronous status storage elements and by the plurality of synchronous judging elements. The selecting element may be a register controlled by the storage control element. The synchronous judging element may include a plurality of synchronous receiving elements for receiving the synchronous status information transmitted from all the processing elements and storing the received synchronous status information. A plurality of synchronous broadcasting lines may be further provided through which the synchronous status information is transmitted corresponding to the plurality of synchronous receiving elements and a mode circuit for connecting each broadcasting line to the synchronous receiving element corresponding to the broadcasting line when processing a plurality of programs and connecting each broadcasting line to one synchronous receiving element when processing one program. The stored synchronization combination information indicates the combination of the processing elements to take the synchronization per program in order to process some programs by the plurality of processing elements. Stored subsequently may be the synchronous status information showing that the synchronous waiting status is reached when the self processing element has finished the processing. The synchronous status information is transmitted to all other processing elements. The next step is to judge whether the processing elements indicated by the synchronization combination information are synchronized. When receiving the synchronous status information from all the processing elements indicated by the synchronization combination information, all the processing elements indicated by the synchronization combination information are shifted to the next processing of the program corresponding to the synchronization combination information. That is, it is possible to designate the combination of the processing elements to take the synchronization per program on the basis of the synchronization combination information. Some parallel processing programs of a plurality of users can therefore be executed with high efficiency by the plurality of processing elements. According to a third aspect of the present invention there is provided a synchronous processing method for use in synchronous processing apparatus having a plurality of processing elements, a group of which processing elements can be assigned to execute a corresponding program so that processes of the program can be executed in parallel and in synchronism by the processing elements of the group, which method comprises the steps of: storing, at each processing element of the said plurality, synchronization combination information indicating the processing elements of the said plurality that belong to such a group; when a processing element belonging to such a group completes one of the said processes of its corresponding program, storing, in the processing element concerned, synchronous status information indicating that the processing element concerned has reached a synchronization waiting status; transmitting the stored synchronous status information from each processing element of the said plurality to all of the other processing elements of the said plurality; at each processing element, receiving the transmitted synchronous status information from the other processing elements of the said plurality; at each processing element, judging whether the processing elements of the group to which the processing element concerned belongs are in synchronism based on the received synchronous status information transmitted to the processing element concerned by the other processing elements of the said group and also based on the stored synchronization combination information held by the processing element concerned; and if it is judged that the group is in synchronism, causing the processing element concerned to execute a next process in the said corresponding program, whereby the processing elements of that group are caused to execute the processes in the corresponding program in parallel and in synchronism. Reference will now be made, by way of example, to the accompanying drawings, in which:- FIGURE 1 is a block diagram showing the principle operation of a synchronous processing apparatus embodying the present invention; FIGURE 2 is a flowchart showing the principle operation of a synchronous processing method embodying the present invention; FIGURE 3 is a block diagram illustrating an architecture of the synchronous processing apparatus of a first embodiment of the invention; FIGURE 4 is a block diagram showing a configuration of a processor; FIGURE 5 is a block diagram showing a configuration of a synchronous processing element; FIGURE 6 is a diagram showing a configurational example of a synchronous mask register; FIGURE 7 is a diagram showing contents of the synchronous mask register when running two programs, of the first embodiment of the invention; FIGURE 8 is a flowchart showing the processing of a program A in the first embodiment; FIGURE 9 is a block diagram illustrating a configuration of a synchronous detecting element for setting "1" in a synchronous indicating register; FIGURE 10 is a block diagram showing the configuration of a synchronous detecting element for setting "0" in the synchronous indicating register; FIGURE 11 is a block diagram illustrating the configuration of a synchronous processing element in a second embodiment of the present invention; FIGURE 12 is a diagram showing contents of a synchronous mask register and of a synchronous mask control register when running two programs in the second embodiment; FIGURE 13 is a flowchart showing the processing of a program A in the second embodiment; FIGURE 14 is a diagram showing contents of the synchronous mask register and of the synchronous mask control register when running three programs; FIGURE 15 is a block diagram showing the configuration of a synchronous processing element of a third embodiment of this invention; FIGURE 16 is a block diagram showing the processing of a program A in the third embodiment; FIGURE 17 is a block diagram illustrating the configuration of an synchronous processing element of a fourth embodiment; FIGURE 18(a) is a flowchart showing the processing of program A within one processor, FIGURE 18(b) is a flowchart showing the processing of program B within one processor; FIGURE 19 (a) is a flowchart showing the processing of subprogram C1 within one processor, FIGURE 19(b) is a flowchart showing the processing of subprogram C2 within one processor; FIGURE 20 is a block diagram illustrating a configuration of a synchronous processing element according to a fifth embodiment; FIGURE 21 is a diagram showing a data format of a 2-process mode on a synchronous broadcasting line in the fifth embodiment; FIGURE 22 is a diagram showing a data format of a 1-process mode on the synchronous broadcasting line in the fifth embodiment; FIGURE 23 is a block diagram illustrating a configuration of a synchronous processing element of a sixth embodiment; FIGURE 24 is a diagram showing a data format on the synchronous broadcasting line; and FIGURE 25 is a block diagram illustrating a configurations of a parity error detecting element and its peripheral portions. FIGURE 1 illustrates a concept of a synchronous processing apparatus embodying the present invention. Processing elements 1 communicate with each other through communication network 2. Each processing element 1 includes a synchronous status storage element 12, a synchronization combination storage element 11, a synchronous judging element 13a, a processing shifting element 8b and a storage control element 8a. FIGURE 2 is a flowchart illustrating a concept of a synchronous processing method according to the present invention. Specific embodiments of the present invention will hereinafter be discussed. FIGURE 3 is a block diagram showing an architecture of the synchronous processing apparatus in a first embodiment of this invention. FIGURE 4 is a block diagram illustrating a configuration of a processor in the first embodiment. As shown in FIGURE 3, according to the first embodiment, the synchronous processing apparatus is provided with a plurality of processors for executing program instructions. The synchronous processing apparatus is also provided with a communication network 2 for connecting the plurality of processors 1-0∼1-(n-1) to each other and transmitting receiving data and information between the processors 1. The communication network 2 includes a transfer network element 21 and a synchronizing broadcasting element 22. The transfer network element 21 effects a transfer of data to a data transfer element 9, shown in FIGURE 4, provided in each of the processors 1-0∼ 1-(n-1). The synchronizing broadcasting element 22 broadcasts a synchronous status of each of the processors 1-0 ∼ 1-n to a synchronous processing element 10, shown in FIGURE 4. Each of the processors 1-0∼1-n(n-1), as shown in FIGURE 4, includes a main memory 7, an instruction processing element 8, a data transfer element 9 and a synchronous processing element 10. The main memory 7 stores a program including a plurality of instructions and also stores data. The instruction processing element 8 connected to the main memory 7 fetches an instruction out of the program of the main memory 7 and executes this instruction. The data transfer element 9 is connected to the main memory 7, the instruction processing element 8 and the transfer network element 21. The data transfer element 9 transfers the data between the main memory 7 and the transfer network element 21. Instruction processing element 8 corresponds to storage control element 8a and processing shifting element 8b of FIGURE 1. FIGURE 5 is a block diagram showing a construction of the synchronous processing element 10. The synchronous processing element 10 is connected to the instruction processing element 8 and the synchronizing broadcasting element 22. The synchronous processing element 10 performs synchronous processing for each processor. Synchronous processing element 10 includes a synchronous status register 12, a synchronous mask register 11, a synchronous receiving element 15, a synchronous detecting element 13 and a synchronous indicating register 14. The synchronous status register 12 is accessed by the instruction processing element 8. The synchronous status register 12 is defined as a 1-bit length register for storing synchronous status information indicating that a synchronization waiting status for synchronization with another processor is reached, when the processor completes an execution of a program process. The synchronous status register 12 stores, e.g., a piece of synchronous status information "1", in accordance with the program when reaching the status to be synchronized with another processor by ending a program process. The synchronous mask register 11, corresponding to synchronization combination storage element 11 of FIGURE 1, is accessed by the instruction processing element 8 and is an n-bit length register for storing synchronization combination information. Herein, the symbol n represents the number of processors. This synchronous mask register 11 stores, e.g., the synchronization combination information "1", with respect to other processors that are to be synchronized with its processor. The synchronous mask register 11, however, also stores synchronization combination information "0" with respect to other processors that are not to be synchronized with its processor. The synchronous receiving element 15 is connected to the synchronizing broadcasting element 22. The synchronous receiving element 15 is a register for receiving the synchronous status information of the other processors' synchronous status registers 12 which is broadcast from the synchronizing broadcasting element 22 and for retaining this synchronous status information. The synchronous detecting element 13 is connected to the synchronous mask register 11 and the synchronous receiving element 15. Synchronous judging element 13a of FIGURE 1 corresponds to synchronous detecting element 13, synchronous receiving element 15, and synchronous indicating register 14 of Figure 5. Synchronous detecting element 13 is a combination circuit for detecting a status where the synchronous status information is all "1" and a status where the synchronous status information is all "0". The synchronous indicating register 14 is a 1-bit length register for indicating synchronous statuses of all the processors conceived as targets. The synchronous indicating register 14 is accessed by the instruction processing element 8 and set or reset by the synchronous detecting element 13. The synchronous detecting element 13 transmits a set signal to the synchronous indicating register 14. The set signal is transmitted when the synchronous status information of all of the processors to be synchronized is "1". These processors, for which the synchronous status information must all be "1"s, are the processors for which the synchronization combination information of the synchronous mask register 11 is "1". Synchronous detecting element 13 sets "1" in synchronous indicating register 14 by a logic operation of the synchronization combination information "1" and the synchronous status information "1" from all of the processors to be synchronized. Instruction processing element 8 shifts to a next process when "1" is set in synchronous indicating register 14. Instruction processing element 8 then resets synchronous status register 12 to "0". Further, the synchronous detecting element 13 transmits a reset signal to the synchronous indicating register 14 in the next process. The reset signal is transmitted when the synchronous status information is all "0" for the processors to be synchronized, i.e. the processors for which the synchronization combination information of the synchronous mask register 11 is "1". Synchronous detecting element 13 resets synchronous indicating register 14 to "0" by the logic operation of the synchronization combination information "1" and the synchronous status information "0" from all of the processors to be synchronized in the next process. Instruction processing element 8 shifts to a next process by resetting synchronous indicating register 14 to "0". Instruction processing element 8 sets synchronous status register 12 to "1". This way, synchronous status register 12 alternately repeats the above-described set or reset action. Synchronous indicating register 14 also alternately repeats the above-described set or reset action. FIGURE 6 is a diagram illustrating an example of a configuration of the synchronous mask register 11. As illustrated in FIGURE 6, a bit string i corresponds to a processor i. Next, a synchronous processing method implemented by the above constructed synchronous processing apparatus will be explained. Discussed below is a description of the processes to be executed while synchronizing two different user's parallel programs, e.g., a program A and a program B. FIGURE 7 is a diagram showing contents of the synchronous mask register 11 when running the two programs A and B. FIGURE 8 is a flowchart showing the processing of the program A. As illustrated in FIGURE 7, it is assumed that e.g., eight processors 1-0 ∼ 1-7 are available. It is also presumed, in this example, that the program A is executed by the processors 1-0, 1-1, 1-3, 1-4, 1-5, while the program B is executed by the processors 1-2, 1-6, 1-7. To start with, before the processors 1-0, 1-1, 1-3, 1-4, 1-5 execute the program A while being synchronized, an 8-bit pattern "11011100", indicating processors 1-0, 1-1, 1-3, 1-4, and 1-5, is set as a piece of synchronization combination information in the synchronous mask register 11 included in each of the processors 1-0, 1-0, 1-3, 1-4, 1-5 (step 101). Further, before the processors 1-0, 1-1, 1-3, 1-4, 1-5 execute the program A while being synchronized, the synchronous status information of the synchronous status register 12 of each processor and the information of the synchronous indicating register 14 thereof are set to "0". Next, the processors 1-0, 1-1, 1-3, 1-4, 1-5 start executing processing k (step 102). Herein, k is initially 1, however, its value is incremented when repeating the process. After each of the processors 1-0, 1-1, 1-3, 1-4, 1-5 in which the program A is executed has finished its processing, the processors are at a status to take processor-to-processor synchronization on the program A. At this point, the instruction processing element 8 sets the synchronous status information of the synchronous status register 12 to "1" (step 103). The synchronous status information "1" of the synchronous status register 12 is transmitted to the synchronizing broadcasting element 22 in the communication network 2 under control of the instruction processing element 8 (step 104). The synchronous status information "1" is broadcast to all other processors from the synchronizing broadcasting element 22. The synchronous receiving elements 15 of the respective processors receive pieces of synchronous status information "1" of the synchronous status registers 12 of all the processors. Subsequently, the synchronous detecting element 13 performs a logic operation with respect to the synchronous status information of the synchronous receiving element 15 and the synchronization combination information of the synchronous mask register 11, thereby detecting synchronization (step 105). If synchronization is not detected, there is a waiting period for receiving the next synchronous status information (step 106). At this time, the instruction processing element 8 of each processor executing the program A has already set "1" in the synchronous status register 12. The instruction processing element 8, if some processes unnecessary for the synchronization with other processors remain unexecuted, executes those processes. Then, the instruction processing element 8 monitors the synchronous indicating register 14 and judges whether or not 1 is set in the information of the synchronous indicating register 14 (step 107). Herein, if 1 is not set in the information of the synchronous indicating register 14, there is a waiting period until the information becomes 1 (step 106). Next, when receiving the synchronous information from all the processors indicated by the synchronization combination information, the information of the synchronous indicating register 14 becomes "1". The action thereof will be explained below. FIGURE 9 is a block diagram showing a configuration of the synchronous detecting element 13 for setting "1" in the synchronous indicating register 14. Provided in FIGURE 9 are OR circuits 81-0 ∼ 81-(n-1), NOT circuits 82-0∼ 82-(n-1), a NOT circuit 83 and an AND circuit 84. The synchronous status information of the processors 1-0 ∼ 1-(n-1) which has been inputted from the synchronous receiving element 15 is inputted to the corresponding OR circuits 81-0 ∼ 81-(n-1). For instance, the synchronous status information of the processor 1-1 is inputted to the OR circuit 81-1 from the synchronous receiving element 15. Synchronization combination information "11011100" from bit 0 to bit n-1 which has been outputted from the synchronous mask register 11 is inputted to the corresponding NOT circuits 82-0 ∼ 82-(n-1). Further, information "0" from the synchronous indicating register 14 is inputted to the NOT circuit 83. Then, in the eight processors shown in this embodiment, when the synchronous status information of all the processors 1-0, 1-1, 1-3, 1-4, 1-5 is "1" (irrespective of statuses of other processors), "1" is set in the synchronous status information of the processor 1-0 which is supplied from the synchronous receiving element 15 and when the synchronization combination information of the synchronous mask register 11 is "1" for the processor 1-0, an output of the CR circuit 81-0 is 1. Further, when the synchronous status information of the processor 1-2 which is supplied from the synchronous receiving element 15 is "0", and, when the register 11 is "0" for the processor 1-2, an output of the OR circuit 81-2 is 1. Hence, if pieces of the synchronous status information of the processors 1-0, 1-1, 1-3, 1-4, 1-5 all become "1", the outputs of all the OR circuits are "1", and an output of the AND circuit 84 comes to "1". Accordingly, "1" is set in the synchronous indicating register 14. Next, when the information of the synchronous indicating register 14 becomes "1", the instruction processing element 8 recognizes that all the processors 1-0, 1-1, 1-3, 1-4, 1-5 relative to the program A have reached the synchronous status. Next processing k+1 consecutively continues (step 108). Next, the instruction processing element 8, when reaching a processor-to-processor synchronization status, sets "0" in the synchronous status register 12 (step 109). The synchronous status information "0" of the synchronous status register 12 is transmitted to the synchronizing broadcasting element 22 on the network 2 (step 110). The synchronous status information "0" is broadcast to all other processors from the synchronizing broadcasting element 22. The synchronous receiving elements 15 of the respective processors receive pieces of synchronous status information "0" of the synchronous status registers 12 of all other processors. Then, the synchronous detecting element 13 executes the logic operation with respect to the synchronous status information of the synchronous receiving element 15 and the synchronization combination information of the synchronous mask register 11, thereby detecting the synchronization (step 111). Herein, if the synchronization is not detected, there is a waiting period for receiving the synchronous status information (step 112). At this time, the instruction processing element 8 of each processor executing the program A has already set "0" in the synchronous status register 12. If there are some processes which it is not necessary to synchronize with other processors that remain unexecuted, the instruction processing element 8 executes those processes. Then, the instruction processing element 8 monitors the synchronous indicating register 14 and judges whether or not 0 is set in the information of the synchronous indicating register 14 (step 113). Herein, if 0 is not set in the information of the synchronous indicating register 14, there is a waiting period until the information becomes 0 (step 114). Next, upon receiving the synchronous status information from all the processors indicated by the synchronization combination information, the information of the synchronous indicating register 14 becomes "0". The action thereof is explained below. FIGURE 10 is a block diagram showing a configuration of the synchronous detecting element 13 for setting "0" in the synchronous indicating register. Provided in FIGURE 10 are AND circuits 85-0 ∼ 85-(n-1), a NOT circuit 86, an OR circuit 87 and a NOT circuit 88. The synchronous status information of the processors 1-0 ∼ 1-(n-1) which has been inputted from the synchronous receiving element 15 is inputted to the corresponding AND circuits 85-0 ∼ 85-(n-1). Synchronization combination information "11011100" from bit 0 to bit n-1 which has been outputted from the synchronous mask register 11 is inputted to the corresponding AND circuits 85-0 ∼ 85-(n-1). Further, information "1" from the synchronous indicating register 14 is inputted to the NOT circuit 86. Then, in the eight processors shown in this embodiment, when the synchronous status information of the processors 1-0, 1-1, 1-3, 1-4, 1-5 is all "0", "0" is set in the synchronous indicating register 14. It is because the output of the OR circuit 87 becomes 1, and an output of the NOT circuit 88 becomes "0". Next, when the information of the synchronous indicating register 14 becomes "0", the instruction processing element 8 recognizes that all the processors 1-0, 1-1, 1-3, 1-4, 1-5 relative to the program A reach the synchronous status. Subsequently, the next processing proceeds. Note that whether or not the processes are all finished is judged at this moment (step 114). Herein, if the processes are not all finished, the action goes back to step 101. Processes from steps 101 ∼ 114 are executed. Thus, processes in the program proceed in parallel by repeating the synchronization based on the synchronous status information "1" and the synchronization based on the synchronous status information "0". On the other hand, the program B is allocated to the processors 1-2, 1-6, 1-7 absolutely independently of the action of the program A described above. A bit pattern "00100011" is set as synchronization combination information in the synchronous mask registers 11 of the processors 1-2, 1-6, 1-7. Parallel processing of the program B also proceeds in the same way as program A in accordance with a processing flow shown in FIGURE 8. This processing proceeds while taking the synchronization based on the synchronous status information "1" and the synchronization based on the synchronous status information "0". In this manner, the processing of the programs A and B can be highly efficient, while repeating the synchronous processing absolutely independently of each other. Described above is the synchronous mask register for storing the synchronization combination information indicating a combination of the processors to be synchronized per program. It is therefore possible to execute the parallel processing programs of a plurality of users which are fewer in number than the processors. Next, the second embodiment of the present invention will be discussed. A change in the configuration of the synchronous processing element 10 is a characteristic point of the second embodiment in contrast with the first embodiment. The configurations other than the synchronous processing element are the same as those in the first embodiment. The same elements as those shown in the first embodiment are marked with like numerals, and detailed explanations thereof will be omitted. FIGURE 11 is a block diagram showing a construction of a synchronous processing element 10b in the second embodiment. Referring to FIGURE 11, a synchronous mask register 16 is accessed from the instruction processing element 8. The synchronous mask register 16 is a register having a bit length corresponding to one-half of the number of the processors. The synchronous mask register 16 designates the relevant processor and a processor to be synchronized. In accordance with the second embodiment, for instance, the number of the processors is 8, and hence the synchronous mask register 16 may be a 4-bit length register, corresponding to four processors to be synchronized. The processor corresponding to a bit "1" among 4 bits executes the program. A synchronous mask control register 17 is a 1-bit length register accessed by the instruction processing element 8. Control information "1" or "0" is required for designating one of the program A executed by the four processors 1-0 ∼ 1-3, for example, and the program B executed by the four processors 1-4 ∼ 1-7, for example. Synchronous mask control register 17 stores pieces of control information "1" and "0" for designating one of the two programs executed by the plurality of processors. This synchronous mask control register 17 designates the program A of two programs A, B executed by the eight processors in accordance with the control information "0". Synchronous mask control register 17 designates the program B of the two programs A, B executed by the eight processors in accordance with the control information "1". Next, a synchronous processing method carried out by the above constructed synchronous processing apparatus will be explained. Given herein is a description of the processes of two different user's parallel programs, i.e., the programs A and B, while being synchronized. FIGURE 12 is a diagram showing an example of contents of the synchronous mask register 16 when running the two programs A and B. FIGURE 13 is a flowchart showing the processing of the program A. As illustrated in FIGURE 12, it is assumed that e.g., eight processors 1-0 ∼ 1-7 are available. It is also presumed that the program A is executed by the processors 1-0, 1-1, 1-2, 1-3 in accordance with synchronization combination information "1110" among the processors 1-0, 1-1, 1-2, 1-3. The program B is executed by the processors 1-4, 1-5, 1-6, 1-7 in accordance with synchronization combination information "0111" among the processors 1-4, 1-5, 1-6, 1-7. Four-bit synchronous mask registers 16 are provided in the eight processors 1-0 ∼ 1-7. At the first onset, before the processors 1-0, 1-1, 1-2, 1-3 execute the program A while taking the synchronization, a bit pattern "1110" is set as a piece of synchronization combination information in the synchronous mask register 16 included in each of the processors 1-0, 1-1, 1-2, 1-3 (step 201). "0" is set in the synchronous mask control register 17, to denote that the bits of the synchronous mask register 16 correspond to the processors 1-0, 1-1, 1-2, 1-3. Further, before the processors 1-0, 1-1, 1-2, 1-3 execute the program A while being synchronized, both the values of the synchronous status register 12 and the synchronous indicating register 14 of each processor are set to "0". Next, the processors 1-0, 1-1, 1-2, 1-3 start executing the process of program A (step 202). Each of the processors 1-0, 1-1, 1-2, 1-3 in which the program A is being executed sets, when a "to be synchronized" status in program A is reached, "1" in its synchronous status register 12 (step 203). The synchronous status information "1" of the synchronous status register 12 is transmitted to the synchronizing broadcasting element 22 in the communication network 2 (step 204). The synchronous status information "1" is broadcast to all other processors from the synchronizing broadcasting element 22. The synchronous receiving elements 15 of the respective processors receive pieces of synchronous status information "1" of the synchronous status registers 12 of all the processors. Subsequently, the synchronous detecting element 13 performs a logic operation with respect to the synchronous status information of the synchronous receiving element 15 and the synchronization combination information of the synchronous mask register 16, thereby detecting the synchronization (step 205). Herein, if the synchronization is not detected, there is a waiting period for receiving the synchronous status information (step 206). The instruction processing element 8, see FIGURE 4, of each processor executing the program A eventually sets "1" in the synchronous status register 12. If there are processes which do not need to be synchronized with other processors that remain unexecuted, the instruction processing element 8 executes those processes. Then, the instruction processing element 8 monitors the synchronous indicating register 14 and judges whether or not 1 is set in the information of the synchronous indicating register 14 (step 207). Herein, if 1 is not set in the information of the synchronous indicating register 14, there is a waiting period until the information becomes 1 (step 206). Next, upon receiving the synchronous information from all the processors indicated by the synchronization combination information, the information of the synchronous indicating register 14 becomes "1". The action thereof is the same as that shown in FIGURE 9. Then, in the eight processors shown in this embodiment, when the synchronous status information of the processors 1-0, 1-1, 1-2 is all "1", "1" is set in the synchronous indicating register 14. When the information of the synchronous indicating register 14 becomes "1", it is recognized that all the processors 1-0, 1-1, 1-2, 1-3 associated with the program A have reached the synchronous status. Herein, it is determined that synchronization has been achieved regardless of the synchronization of the processor 1-3, because the synchronization combination information of the synchronous mask register corresponding to the processor 1-3 is "0". Then, the next process k+1 consecutively continues (step 208). The processors assigned to the program A are the processors 1-0, 1-1, 1-2, 1-3. The actual program A is executed by the processors 1-0, 1-1, 1-2. At this time, the synchronization combination information is "1110". The 3 higher-order bits (which are set to "1") of this synchronization combination information correspond to the processors 1-0, 1-1, 1-2. The lowest-order bit corresponds to the processor 1-3. Note that the processors assigned to the program B are the processors 1-4, 1-5, 1-6, 1-7. When the synchronous status information of all the processors 1-0, 1-1, 1-2 is "1", synchronous indicating register 14 is set with "1". Instruction processing element 8 thereby recognizes the synchronism even if the processor 1-3 does not synchronize with the processors 1-0, 1-1, 1-2. In accordance with the program A, upon reaching a time required for taking the processor-to-processor synchronization, "0" is set in the synchronous status register 12 (step 209). The synchronous status information "0" of the synchronous status register 12 is transmitted to the synchronizing broadcasting element 22 in the network 2 (step 210). The synchronous status information "0" is broadcast to all other processors from the synchronizing broadcasting element 22. The synchronous receiving elements 15 of the respective processors receive pieces of synchronous status information "0" of the synchronous status registers 12 of all other processors. Then, the synchronous detecting element 13 executes the logic operation with respect to the synchronous status information of the synchronous receiving element 15 and the synchronous mask register 16, thereby detecting the synchronization (step 211). Herein, if the synchronization is not detected, there is a waiting period for receiving the synchronous status information (step 212). At this time, the instruction processing element 8 of each processor executing the program A has already set "0" in its synchronous status register 12. If some processes which it is not necessary to synchronize with other processors remain unexecuted, the instruction processing element 8 executes those processes. Then, the instruction processing element 8 monitors the synchronous indicating register 14 and judges whether or not 0 is set in the information of the synchronous indicating register 14 (step 213). Herein, if 0 is not set in the information of the synchronous indicating register 14, there is a waiting period until the information becomes 0 (step 212). Next, Upon receiving the synchronous information from all the processors indicated by the synchronization combination information, the information of the synchronous indicating register 14 becomes "0". The action thereof is the same as that shown in FIGURE 10. When the value of the synchronous indicating register 14 becomes "0", it is recognized that all the processors 1-0, 1-1, 1-2, 1-3 assigned to the program A have reached the synchronous status. The next processing is consecutively processed. Furthermore, whether or not the processes in program A are all finished is judged at this moment (step 214). Herein, if the processes are not all finished, the action goes back to step 201. Processes form steps 201 - 214 are executed. Thus, the processing of program A by the processors 1-1, 1-2, 1-3 and 1-4 proceeds in parallel by repeating the synchronization based on the synchronous status information "1" and the synchronization based on the synchronous status information "0". On the other hand, the program B is allocated to the processors 1-4, 1-5, 1-6, 1-7 absolutely independently of the action of the program A described above. Synchronization combination information "0111" is set in the synchronous mask registers 16 of the processors 1-4, 1-5, 1-6, 1-7, while a bit pattern "1" is set in the synchronous mask control register 17. "1" is set in the synchronous mask control register 17, whereby the 4 bits of the synchronous mask register 16 correspond to the processors 1-4, 1-5, 1-6, 1-7. Parallel processing of the program B also proceeds as in the same way as program A while taking the synchronization based on the synchronous status information (flag) "1" and the synchronization based on the synchronous flag "0". In this manner, the processing of the programs A and B is highly efficient while repeating the synchronous processing of programs A and B absolutely independently of each other. As discussed above, the synchronous processing apparatus of the second embodiment for effecting the processor-to-processor synchronization includes a synchronous mask register 16 having a smaller number of bits than the number of the processors, the register 16 serving to designate a combination of the processors, to take the synchronization. The synchronous mask register 16 is controlled by the synchronous mask control register 17. A plurality of user's parallel processing programs can be executed at high efficiency through the synchronous mask registers, the number of bits of which is smaller than the number of processors. Further, when executing two or more programs in parallel, the following steps may be performed. For instance, as illustrated in FIGURE 14, when executing three programs, the synchronous mask control register 17 involving the use of a 2-bit length register stores pieces of 2-bit information "00", "01, "10". The synchronous mask control register 17 allocates "00" to the synchronous mask registers of the processors 1-0 ∼ 1-3. The synchronous mask control register allocates "01" to the synchronous mask registers of the processors 1-4 ∼ 1-7 and "10" to the synchronous mask registers of the processors 1-8 ∼ 1-11. The three programs can be thereby executed in parallel. FIGURE 15 is a block diagram showing a construction of a synchronous processing element 10c in a third embodiment. FIGURE 16 is a flowchart showing processes of the program A in the third embodiment. The synchronous processing element 10c in the third embodiment includes synchronous status registers 12a and 12b, synchronous mask registers 11a and 11b, synchronous receiving elements 15a and 15b, synchronous detecting elements 13a and 13b and synchronous indicating registers 14a and 14b. One group of elements and registers 11a, 12a, 13a, 14a, and 15a are employed for the synchronous processing of the program A, while the other group of elements and registers 11b, 12b, 13b, 14b, and 15b are for the synchronous processing of the program B. Referring to FIGURE 15, a synchronous status register 12a, a synchronous mask register 11a, a synchronous receiving element 15a, a synchronous detecting element 13a and a synchronous indicating register 14a are provided for executing the processes of the program A while being synchronized. A synchronous status register 12b, a synchronous mask register 11b, a synchronous receiving element 15b, a synchronous detecting element 13b and a synchronous indicating register 14b are provided for executing the processes of the program B while being synchronized. Further, the synchronous status registers etc. are provided in pairs. Hence, the number of the processors provided in the third embodiment is one-half of the number of the processors provided in the first embodiment. Next, a synchronous processing method carried out by the above constructed synchronous processing apparatus will be explained. Given herein is a description of the processes wherein two different user's parallel programs, i.e., the programs A and B,are executed while being synchronized. It is assumed that e.g., four processors 1-0 ∼ 1-3 are available. It is also presumed that both of the programs A and B are executed by the processors 1-0, 1-1, 1-2, 1-3. To begin with, before the processors 1-0, 1-1, 1-2, 1-3 execute the program A while taking the synchronization, a bit pattern "1111" is set in the synchronous mask registers lla included in each of the processors 1-0, 1-1, 1-2, 1-3 (step 301). Further, before the processors 1-0, 1-1, 1-2, 1-3 execute the program A while taking the synchronization, the respective values of both the synchronous status register 11a and the synchronous indicating register 14a of each processor are set to "0". Next, the processors 1-0, 1-1, 1-2, 1-3 start executing the process k (step 302). Each of the processors 1-0, 1-1, 1-2, 1-3 in which the program A is being executed sets, when a status to take the synchronization on the program A is reached, "1" in the synchronous status register 12a (step 303). The synchronous status information "1" of the synchronous status register 12a is transmitted to the synchronizing broadcasting element 22 on the communication network 2 (step 304). The synchronous status information "1" is broadcast to all other processors from the synchronizing broadcasting element 22. The synchronous receiving elements 15a of the respective processors receive pieces of synchronous status information "1" of the synchronous status registers 12a of all the processors. Subsequently, the synchronous detecting element 13a performs a logic operation with respect to the synchronous status information of the synchronous receiving element 15a and the synchronization combination information of the synchronous mask register 11a, thereby detecting the synchronization (step 305). Note that if the synchronization is not detected, there is a waiting period for receiving the synchronous status information (step 306). It is next judged whether the value of the synchronous indicating register 14a is set to 1 or not (step 307). Note that the synchronous detecting element for setting "1" in the synchronous indicating register 14a is constructed the same as in FIGURE 9. Then, in the four processors shown in this embodiment, when the synchronous status information of all the processors 1-0, 1-1, 1-2, 1-3 is "1", "1" is set in the synchronous indicating register 14a. When a value of the synchronous indicting register 14a becomes "1", it is recognized that all the processors 1-0, 1-1, 1-2, 1-3 associated with the program A have reached the synchronous status. The next process k+1 consecutively continues (step 308). In accordance with the program A, upon reaching a time required for taking the processor-to-processor synchronization, "0" is set in the synchronous status register 12a (step 309). The synchronous status information "0" of the synchronous status register 12a is transmitted to the synchronizing broadcasting element 22 on the network 2 (step 310). The synchronous status information "0" is broadcast to all other processors from the synchronizing broadcast 22. The synchronous receiving elements 15a of the respective processors receive pieces of synchronous status information "0" of the synchronous status registers 12a of all other processors. Then, the synchronous detecting element 13a executes the logic operation with respect to the synchronous status information of the synchronous receiving element 15a and the synchronization combination information of the synchronous mask register 11a, thereby detecting the synchronization (step 311). It is then judged whether or not the value of the synchronous indicating register 14a is set to 0 (step 313). The synchronous detecting element for setting "0" in the synchronous indicating register 14a is constructed the same as in FIGURE 10. When the value of the synchronous indicating register 14a becomes "0", it is recognized that all the processors 1-0, 1-1, 1-2, 1-3 associated with the program A have reached the synchronous status. The next processing is consecutively proceeded to. However, if the processes are not all finished, the action returns to step 301. The processes from steps 301 ∼ 314 are executed. Thus, the processes are executed in parallel by repeating the synchronization based on the synchronous status information "1" and the synchronization based on the synchronous status information "0". On the other hand, the program B is allocated to the processors 1-0, 1-1, 1-2, 1-3 absolutely independently of the action of the program A described above. A bit pattern "1111" is set in the synchronous mask registers 11b of the processors 1-0, 1-1, 1-2, 1-3. Parallel processing of the program B is also executed the same way as with the program A while taking the synchronization based on the synchronous status information "1" and the synchronization based on the synchronous status information "0". As discussed above, in the third embodiment of the synchronous processing apparatus for performing the processor-to-processor synchronization, the synchronous processing element includes a plurality of the synchronous status registers, the synchronous mask registers, the synchronous indicating registers, etc. The plurality of user's parallel processing programs can be highly efficiently executed by a small number of processors. Next, a fourth embodiment of the present invention will be discussed. FIGURE 17 is a block diagram illustrating a construction of the synchronous processing element 10d in the fourth embodiment. The fourth embodiment has a construction in which a plurality of processes are executable. In the case of executing, for instance, only one process, however, this involves the use of one group of registers. The other group of registers are useless. Under such circumstances, the parallel processing programs are executed by switching over the plurality of processes and one process in accordance with the fourth embodiment. Referring to FIGURE 17, a synchronous processing element 10d in the fourth embodiment includes a synchronous status register 12a, a synchronous mask register 11a, a synchronous receiving element 15a, a synchronous detecting element 13a and a synchronous indicating register 14a. The synchronous processing element 10d further includes a synchronous status register 12b, a synchronous mask register 11b, a synchronous receiving element 15b, a synchronous detecting element 13b and a synchronous indicating register 14b. A synchronous side control register 18 accessed by the instruction processing element 8 is a 2-bit length register. The synchronous side control register 18 stores 2- or 1-process information for designating any one of two processes (two programs) or one process (one program) for one processor. The synchronous side control register 18 imparts the 2-or 1-process information to the synchronous status registers 12a, 12b, the synchronous mask registers 11a, 11b, the synchronous receiving elements 15a, 15b,the synchronous detecting elements 13a, 13b and the synchronous indicating registers 14a, 14b. FIGURE 18 shows an action flow of two processes by one processor. When executing the programs A and B in parallel, the instruction processing element 8 sets 2-process information "01" in the synchronous side control register 18. The synchronous status register 12a, the synchronous mask register 11a, the synchronous receiving element 15a, the synchronous detecting element 13a and the synchronous indicating register 14a execute the processes of the program A. These processes are executed while taking the synchronization on the basis of the 2-process information "01". As shown in FIGURE 18(a), the instruction processing element 8 performs an arithmetic operation A of the program A within one processor (step 401). Then, the synchronous processing element 10d executes synchronization A (step 402). The data transfer element 9 effects a transfer A of data of an arithmetic result to other processors (step 403). Further, the action proceeds to the next process, and steps 404, 405 are to be conducted. Further, "10" is set in the synchronous side control register 18. The synchronous status register 12b, the synchronous mask register 11b, the synchronous receiving element 15b, the synchronous detecting element 13b and the synchronous indicating register 14b execute the processes of the program B. These processes are executed while taking the synchronization on the basis of the 2-process information "10". As shown in FIGURE 18(b), the instruction processing element 8 performs an arithmetic operation B of the program B within one processor (step 411). Then, the synchronous processing element 10d executes synchronization B (step 412). The data transfer element 9 effects a transfer B of data of an arithmetic result to other processors (step 413). Further, the action proceeds to the next process, and steps 414, 415 are to be conducted. Namely, the 2-process actions are effected by one processor. FIGURE 19 shows an action flow of one process by one processor. Given next is an explanation of a case where one program C is divided into subprograms C1, C2 which are to be executed in parallel. One-process information "11" is set in the synchronous side control register 18. Hereat, the synchronous status register 12a, the synchronous mask register 11a, the synchronous receiving element 15a, the synchronous detecting element 13a and the synchronous indicating register 14a execute the process of the subprogram C1. This process is executed while taking the synchronization on the basis of the 1-process information "11". As shown in FIGURE 19(a), the instruction processing element performs an arithmetic operation C1 of the subprogram C1 within one processor (step 421). Then, the synchronous processing element executes synchronization C1 (step 422). The data transfer element effects a transfer C1 of data of an arithmetic result to other processors (step 423). Further, the action proceeds to the next process, and steps 424, 425 are to be conducted. Further, the synchronous status register 12b, the synchronous mask register 11b, the synchronous receiving element 15b, the synchronous detecting element 13b and the synchronous indicating register 14b execute while taking the synchronization on the basis of the 1-process information "11". As shown in FIGURE 19(b), the instruction processing element performs an arithmetic operation C2 of the subprogram C2 within one processor (step 431). Then, the synchronous processing element executes synchronization C2 (step 432). The data transfer element effects a transfer C2 of data of an arithmetic result to other processors (step 433). Further, the action proceeds to the next process, and steps 434, 435 are to be conducted. Namely, the 1-process actions are effected by one processor. As discussed above, it is possible to efficiently execute the parallel processing programs of a plurality of users and the parallel processing program of one user by switching over the actions of the 2-process by one processor or the actions of 1-processor by the processor. Next, a fifth embodiment of the present invention will be discussed. The synchronous processing apparatus shown in the third embodiment described above comprises processors each provided with pairs of registers, etc. When executing the plurality of parallel processing programs, the broadcasting line through which the synchronous status information of each processor is broadcast is set per process. In the case of executing one process, however, only the 1-set broadcasting line is used. In this case, one process undergoes processing by use of a plurality of broadcasting lines, thereby speeding up the processing. The fifth embodiment aims at processing one process while taking the synchronization by using the plurality of broadcasting lines. FIGURE 20 is a block diagram illustrating a construction of a synchronous processing element 10e in the fifth embodiment. The synchronous processing element 10e in the fifth embodiment includes, as in the case of the synchronous processing element 10c in the third embodiment, pairs of the registers, etc. The synchronous processing element 10e also includes two broadcasting lines 23a, 23b corresponding respectively to the synchronous receiving elements 15a, 15b. A mode circuit 19 is connected to the instruction processing element 8 and the synchronous receiving elements 15a, 15b. The mode circuit 19 is defined as a 1-bit length register in which 1-mode information "0" or 2-mode information "1" is set when switching on a power supply of a processor synchronous processing apparatus. The mode circuit 19 works to connect the synchronous broadcasting lines 23a, 23b to the synchronous receiving element 15a when the 1-mode information "0" is set. The mode circuit 19 further works to connect the synchronous broadcasting line 23a to the synchronous receiving element 15a in the case of the 2-mode information "1" as well as connecting the synchronous broadcasting line 23b to the synchronous receiving element 15b. FIGURE 21 is a diagram showing a data format of a 2-process mode on the synchronous broadcasting line in the fifth embodiment. FIGURE 22 is a diagram showing a data format of a 1-process mode on the synchronous broadcasting line in the fifth embodiment. Based on the construction given above, the 2 processes are processed in parallel by use of a couple of synchronous status registers 11a, 11b. This parallel processing will be explained with reference to FIGURES 20 and 21. At first, the instruction processing element 8 sets 2-mode information "1" in the mode circuit 19. Hereupon, the mode circuit 19 works to connect the synchronous broadcasting line 23a to the synchronous receiving element 15a and the synchronous broadcasting line 23b to the synchronous receiving element 15b. Then, as depicted in FIGURE 21, a header is broadcasted through the synchronous broadcasting line 23a. Further, a piece of synchronous status information a of the synchronous status register 12a is broadcast therethrough. In this parallel action, the header is broadcast via the synchronous broadcasting line 23b. Furthermore, a piece of synchronous status information b is broadcast via the same line. Hereupon, the synchronous receiving element 15a receives the synchronous status information a of the synchronous status register 12a. The synchronous receiving element 15b receives the synchronous status information b of the synchronous status register 11b. The two processes are thereby executable in parallel. Next, there will be explained a case where one process is processed by use of one synchronous status register 12a, etc. with reference to FIGURES 20 and 22. When the instruction processing element 8 sets 1-mode information "0" in the mode circuit 19, the mode circuit 19 works to connect the synchronous broadcasting lines 23a, 23b to the synchronous receiving element 15a. Then, the synchronous status information of the synchronous status register 12a is broadcast via the two synchronous broadcasting lines 23a, 23b. For example, as shown in FIGURE 22, with respect to the synchronous status information, a piece of synchronous status information al is transmitted from the broadcasting line 23a, and, after a given time has elapsed, a piece of synchronous status information a2 is transmitted from the broadcasting line 23b. That is, the pieces of information are transmitted with a phase shift due to a serial bit. In the synchronous receiving element 15a of each processor, the synchronization can be taken based on the synchronous status information in which timings are matched in the two broadcasting lines 23a, 23b. The apparatus capable of executing the 2 processes in this manner is provided with the mode circuit 19 which can set the two modes, i.e., the 1- and 2-process modes. When executing only the 1-process mode, the mode circuit 19 sets the 1-process mode. Namely, the synchronous status information is transferred by use of the two broadcasting lines 23a, 23b during the 1-process mode. The synchronization can be therefore taken at a high speed, and the parallel processing programs are executable at a high efficiency. Next, the sixth embodiment of the present invention will be explained. The synchronous status information is serially transferred in bits through the synchronous broadcasting lines. A 1-bit parity error may, however, be caused due to an influence of noises, etc. with respect to the synchronous status information on the synchronous broadcasting lines. Conventionally, the processor in which the parity error is detected is disconnected from the network 2, and hence the execution of the program is interrupted. If the execution of the program is interrupted due to such a non-serious error, the execution of the processing becomes inefficient. In the sixth embodiment, if the 1-bit error is produced in the broadcasting line, the processing is executed without interrupting the program. FIGURE 23 is a block diagram illustrating a construction of a synchronous processing element 10f. FIGURE 24 shows a data format on the synchronous broadcasting line. As shown in FIGURE 24, the data such as a header, synchronous status information of the processors 1-0 ∼ 1-7 and a parity P are transmitted in serial via the synchronous broadcasting line. The synchronous receiving element 15 is a register for receiving the synchronous status information which has been broadcast in 1-bit serial from the synchronous broadcasting element 22. At the same time, the synchronous receiving element 15 receives the 1-bit parity per 8 bits and hold these items of information. A parity error detecting element 20 checks whether or not an error exists in the 1-bit parity received per 8 bits by the synchronous receiving element 15. FIGURE 25 is a block diagram illustrating configurations of the parity error detecting element 20 and its peripheral portion. The operation of the sixth embodiment will be explained referring to FIGURES 23 and 25. A 1-bit length flip-flop (FF) 31 receives the synchronous status information broadcast in 1-bit serial via the synchronizing broadcasting line 23 from the synchronous broadcasting element 22. The synchronous status information is 1-bit information of "0" or "1". This synchronous status information is broadcasted via the synchronous broadcasting line to each processor. When this synchronous status information passes through the synchronous broadcasting line, it may happen that, for example, a bit "1" is changed into "0" due to outside noises. Parity error detecting element 20 checks whether or not an error is caused in the 8-bit synchronous status information received by synchronous receiving element 15 by use of the 1-bit parity bit P. FF32 adds a 1 parity bit to 8 bits of the synchronous status information. Parity checker 34 (PCHK) checks whether or not an error is produced in a tuple of 8 bits of synchronous status information and 1 parity bit, which is given by FF32. For instance, if a total sum of 8 bits of synchronous status information and 1 parity bit is to be an odd number parity checker 34 judges an error to exist if the given-by-FF32 total sum of 8 bits of synchronous status information and 1 parity bit is not an odd number. The following is an explanation of how the parity error is detected when the data from the synchronous broadcasting line is such data that the content of synchronous indicating register 14 is not changed. To start with, the data sent from the synchronous broadcasting line is, for instance, "110000001". The 8 higher-order bits are the synchronous status information, while lowest-order bit is the parity bit. In this case, the total sum of bits having the "1" level is 3 bits, i.e., an odd number. It is also assumed that the data from FF32 is "110000011". In this case, the total sum of "1" bits is 4 bits, i.e., an even number. Parity checker 34 therefore judges that there is an error. In this instance, the error information from parity checker 34 is transferred via FF35, FF36 to FF37. FF37 informs instruction processing element 8 of system retaining ("SR") information indicating that the system is not interrupted. At this time, FF38 retains parity error information. In addition, if parity checker 34 again detects the error, AND40 ANDs error information of parity checker 34 through FF35 and error information already stored in FF38. FF41 notifies instruction processing element 8 of system-down information with an AND output of AND40. In this case, the processor which detects the error is disconnected from network 2. Further, a parity generator 42 modifies the parity bit "1" of the data "110000011" from FF32 to "0", thereby generating data "110000010". This data "110000010" is inputted via FF33 to AND43. AND43 ANDs the data "110000001" stored in synchronous mask register 11 and the above data "110000010" and outputs the result to synchronous indicating register 14 via FF44, FF45. In this instance, the data "110000001" from synchronous mask register 11 is different from the above data "110000010" from FF33. Therefore, if the parity error is produced, a value of synchronous indicating register 14 remains "0", because it does not change. The following is an explanation of how the parity error is detected when the data from the synchronous broadcasting line is such data as to change the content of synchronous indicating register 14. First, it is assumed that the data sent from the synchronous broadcasting line is, e.g. "100000000". In this case, a total sum of bits is 1 bit. The data from FF32 is, it is also assumed, "110000000". Further, parity generator 42 modifies the parity bit "0" of the data "110000000" from FF32 to "1", thereby generating data "110000001". This data "110000001" is inputted via FF33 to AND43. AND43 ANDs the data "110000001" stored in synchronous mask register 11 and the above data "110000001" and outputs the result to synchronous indicating register 14 via FF44, FF45. In this case, the data "110000001" from FF33 is identical with the data "110000001" from synchronous mask register 11, and hence the value of synchronous indicating register 14 changes from "0" to "1". Note that the value of synchronous indicating register 14 reversely changes from "1" to "0" as the case may be. Further, AND 39 ANDs the data from FF36, the data from synchronous indicating register 14 and the data from FFs 47a-47n through AND46. If the parity error is present, AND39 is turned ON and modifies instruction processing element 8 of the system-down information. Therefore, when the 1-bit parity error is caused in the data on the broadcasting line due to the influence of the noises, etc., the processing can be executed without interrupting the program, so that parallel processing of a program can be executed with high efficiency.

Claims: Synchronous processing apparatus comprising: a plurality of processing elements (1) for executing processes of a plurality of programs (A,B), a group of the processing elements (e.g. 1-0, 1-1, 1-3, 1-4, 1-5) being assignable to a corresponding one of the programs so that processes of that program can be executed in parallel and in synchronism by the processing elements of the said processor-element group, each processing element belonging to such a group being operable, when it completes one of the said processes of the program corresponding to that group, to transmit synchronous status information indicating that it has reached a synchronization waiting status; communication means (2) through which information is transferred between the processing elements of the said plurality; synchronization combination storage means (11;16) for storing synchronization combination information indicating the processing elements of the said plurality that belong to such a group; synchronous receiving means (15) for receiving the transmitted synchronous status information; synchronous judging means (13) for judging whether such a group of processing elements are in synchronism based on the received synchronous status information transmitted from all of the said processing elements and on the said stored synchronization combination information; and shifting means (8) operable, when said synchronous judging means (13) judges that such a group of processing elements are in synchronism, to cause the processing elements of the group to execute a next process in the program corresponding to that group; characterised in that each said processing element (1) of the said plurality includes synchronous processing means (10; 10a; 10b; 10f) having: synchronous status storing means (12) for storing the said synchronous status information of the processing element concerned; storage control means (8) for controlling said synchronous status storing means (12) to store said synchronous status information and for simultaneously transmitting said stored synchronous status information of the processing element concerned via the said communication means (2) to all of the other processing elements of the said plurality; its own said synchronous receiving means (15) for receiving the transmitted synchronous status information of each other processing element of the said plurality; its own said synchronous judging means for judging whether the processing elements of the group to which the processing element concerned belongs are in synchronism based on the received synchronous status information transmitted to the processing element concerned by the other processing elements of that group and also based on the synchronization combination information stored by the processing element concerned; and its own said shifting means operable, when the said synchronous judging means of the processing element concerned judges that such a group is in synchronism, to cause the processing element concerned to execute its next process in the program corresponding to that group, whereby the processing elements of that group are caused to execute the processes in the said corresponding program in parallel and in synchronism with one another. Apparatus as claimed in claim 1, wherein the said shifting means (8) includes a synchronous indicating register (14) which stores synchronous indicating information indicating that said group of processing elements are in synchronism. Synchronous processing apparatus ccmprising: a plurality of processing elements (1) for executing processes of a plurality of programs (A, B), a group of the processing elements being assignable to a corresponding one of the programs so that processes of that program can be executed in parallel and in synchronism by the processing elements of the said group, each processing element belonging to such a group being operable, when it completes one of the said processes of the program corresponding to that group, to transmit synchronous status information indicating that it has reached a synchronization waiting status; communication means (2) through which information is transferred between the processing elements of the said plurality; synchronous judging means (13a, 13b) for judging whether such a group of processing elements are in synchronism; and shifting means (8) operable, when said synchronous judging means (13a, 13b) judges that such a group of processing elements are in synchronism, to cause that group of processing elements to execute a next process in the program corresponding to that group; characterised in that each said processing element (1) of the said plurality includes synchronous processing means (10c; 10d; 10e) having: a plurality of synchronous status storage means (12a, 12b), corresponding to different respective said programs (A,B), each of which programs has assigned thereto its own corresponding group of processing elements including the processing element concerned, and each said synchronous status storage means (12a, 12b) serving to store, for its said corresponding program, the said synchronous status information for the processing element concerned; storage control means (8) for controlling the said synchronous status storage means (12, 12b) of the said plurality to store the said synchronous status information and for simultaneously transmitting the said stored synchronous status information of the processing element concerned via the said communication means to all of the other processing elements of the said plurality; its own plurality of such synchronous judging means (13a, 13b), corresponding respectively to the said synchronous status storage means (12a, 12b) of the said plurality, each operable to judge whether the processing elements of one of the said groups to which the processing element concerned belongs are in synchronism; and its own said shifting means operable, when any one of the said plurality of synchronous judging means (13a, 13b) of the processing element concerned judges that one of the said groups to which the processing element concerned belongs is in synchronism, to cause the processing element concerned to execute its next process in the program corresponding to that group, whereby that group of processing elements executes processes in the corresponding program in parallel and in synchronism. Apparatus as claimed in claim 3, wherein the said shifting means (8) includes a plurality of synchronous indicating registers (14a, 14b), each for storing synchronous indicating information indicating that one of the said groups to which the processing element concerned belongs is in synchronism. Apparatus as claimed in claim 3 or 4, further comprising a selecting means (18) for selecting whether the said plurality of synchronous status storage means (12a, 12b) and the said plurality of synchrcnous judging means (13a, 13b) are to perform synchronous processing of a plurality of programs (A, B) or synchronous processing of one program (C1, C2). Apparatus as claimed in claim 5, wherein the said selecting means (18) includes a register controlled by the said storage control means (8). Apparatus as claimed in claim 3, 4, 5 or 6, further including: a plurality of synchronous receiving means (15a, 15b) corresponding respectively to the said synchronous status storage means (12a, 12b) of the said plurality, for receiving the synchronous status information transmitted from all of the said processing elements of the said plurality and for storing the received synchronous status information; and a plurality of synchronization combination storage means (11a, 11b) corresponding respectively to the said synchronous status storage means (12a, 12b), each serving to store, for the program corresponding to the synchronous status storage means concerned, synchronous combination information indicating the processing elements of the said plurality that belong to the group to which that program corresponds. Apparatus as claimed in claim 7, further including: a plurality of synchronous broadcasting lines (23a, 23b) through which the said synchronous status information is transmitted and corresponding respectively to the synchronous receiving means (15a, 15b) of the said plurality; and a mode circuit (19) operable, when processing a plurality of programs, to connect each said broadcasting line to its said corresponding one of the said synchronous receiving means and also operable, when processing one program, to connect both of the said broadcasting lines (23a, 23b) to the same one of the said synchronous receiving means (15a). Apparatus as claimed in any one of claims 1, 2, 7 and 8, wherein the or each said synchronous receiving means (15; 15a, 15b) includes means for storing the said received synchronous status information. Apparatus as claimed in claim 9, wherein the or each said synchronous receiving means (15; 15a, 15b) includes a register having bits corresponding respectively to the processing elements of the said plurality, which register stores, upon receipt by the processing element concerned of such synchronous status information from one of the other processing elements of the said plurality, the received synchronous status information in that one of the bits of the register that corresponds to that other processing element. Apparatus as claimed in any one of claims 1, 2 and 7 to 10, wherein the or each said synchronous judging means (13; 13a, 13b) includes a logic operation circuit (81 to 84; 85 to 88) for performing logic operations upon said synchronous status information supplied from said synchronous receiving means (15; 15a, 15b) and said synchronization combination information supplied from said synchronization combination storage means (11; 16; 11a, 11b), thereby judging whether such a group of processing elements are in synchronism. Apparatus as claimed in any one of claims 1, 2 and 7 to 11, wherein the or each said synchronous receiving means (15; 15a, 15b) includes a parity error detecting element (20) for detecting a parity error of said synchronous status information resulting from transmission of that information through a broadcasting line of the said communication means (2). Apparatus as claimed in claim 12, wherein when the said parity error detecting element (20) detects a one-bit error, the processing element concerned continues processing without interrupting the processing of the or each program. Apparatus as claimed in any one of claims 1, 2 and 7 to 13, wherein the said storage control means (8) controls the or each said synchronization combination storage means (11; 16) to store the said synchronization combination information. Apparatus as claimed in any one of claims 1, 2 and 7 to 14, wherein the or each said synchronization combination storage means (11) includes a register having bits (n) corresponding respectively to the processing elements (1-0,...,1(n-1)) of the said plurality, which register serves to store synchronous combination information "1" in those bits thereof that correspond to the processing elements of the said plurality that belong to such a processor-element group. Apparatus as claimed in any one of claims 1, 2 and 7 to 14, wherein the or each said synchronization combination storage means (16) includes a register having a number (n/2) of bits corresponding to half the number (n) of processing elements in the said plurality, and each of the said processing elements further includes a control register (17) for designating a correspondence between the bits of the said register (16) and the said processing elements. Apparatus as claimed in claim 16, wherein the said control register (17) is a one-bit register which selectively stores control information "1" or "0", where "1" denotes that the synchronization combination storage means (16) presently corresponds to a first such group (1-0 to 1-3) of the processing elements of the said plurality, and "0" denotes that the synchronization combination storage means (16) presently corresponds to a second such group (1-4 to 1-7) of the processing elements of the said plurality. Apparatus as claimed in any preceding claim, wherein the or each said synchronous status storing means (12; 12a, 12b) alternately stores synchronous status information "1" and synchronous status information "0" for each completed process in the said corresponding program. Apparatus as claimed in any preceding claim, wherein the or each said synchronous status storing means (12; 12a, 12b) includes a register having a length of one bit. A synchronous processing method for use in synchronous processing apparatus having a plurality of processing elements (1), a group of which processing elements (e.g. 1-0, 1-1, 1-3, 1-4, 1-5) can be assigned to execute a corresponding program so that processes of the program can be executed in parallel and in synchronism by the processing elements of the group, which method comprises the steps of: storing, at each processing element of the said plurality, synchronization combination information indicating the processing elements of the said plurality that belong to such a group; when a processing element belonging to such a group completes one of the said processes of its corresponding program, storing, in the processing element concerned, synchronous status information indicating that the processing element concerned has reached a synchronization waiting status; transmitting the stored synchronous status information from each processing element of the said plurality to all of the other processing elements of the said plurality; at each processing element, receiving the transmitted synchronous status information from the other processing elements of the said plurality; at each processing element, judging whether the processing elements of the group to which the processing element concerned belongs are in synchronism based on the received synchronous status information transmitted to the processing element concerned by the other processing elements of the said group and also based on the stored synchronization combination information held by the processing element concerned; and if it is judged that the group is in synchronism, causing the processing element concerned to execute a next process in the said corresponding program, whereby the processing elements of that group are caused to execute the processes in the corresponding program in parallel and in synchronism. A method as claimed in claim 20, wherein the synchronous status information storing step includes the step of alternately storing synchronous status information "1" and synchronous status information "0" for each completed process in the said corresponding program. A method as claimed in claim 20 or 21, wherein the judging step includes the step of storing the received synchronous status information in a register (15; 15a, 15b). A method as claimed in any one of claims 20 to 22, wherein the judging step includes the step of performing logic operations upon the received synchronous status information and the said stored synchronization combination information. A method as claimed in any one of claims 20 to 23, wherein the step of causing execution of the next process includes the step of storing synchronous indicating information for indicating that the said group of processing elements are in synchronism. A method as claimed in any one of claims 20 to 24, wherein the judging step includes the step of detecting a parity error in the synchronous status information transmitted to the processing element concerned via a broadcasting line.

Inventors: DEWA MASAMI, IKEDA MASAYUKI, ISHIZAKA KENICHI, KOBAYAKAWA KAZUSHIGE, NAGASAWA SHIGERU, SHINJO NAOKI, TAKAMURA MORIYUKI, UENO HARUHIKO, UTSUMI TERUO, DEWA, MASAMI, IKEDA, MASAYUKI, ISHIZAKA, KENICHI, KOBAYAKAWA, KAZUSHIGE, NAGASAWA, SHIGERU, SHINJO, NAOKI, TAKAMURA, MORIYUKI, UENO, HARUHIKO, UTSUMI, TERUO, DEWA, MASAMI, C/O FUJITSU LIMITED, IKEDA, MASAYUKI, C/O FUJITSU LIMITED, ISHIZAKA, KENICHI, C/O FUJITSU LIMITED, KOBAYAKAWA, KAZUSHIGE, C/O FUJITSU LIMITED, NAGASAWA, SHIGERU, C/O FUJITSU LIMITED, SHINJO, NAOKI, C/O FUJITSU LIMITED, TAKAMURA, MORIYUKI, C/O FUJITSU LIMITED, UENO, HARUHIKO, C/O FUJITSU LIMITED, UTSUMI, TERUO, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1993
Main classification: G06F9
IPC codes: G06F15, G06F9