METHODS OF FORMING A LOCAL INTERCONNECT AND A HIGH RESISTOR POLYSILICON LOAD

Abstract: Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects (74) are formed by depositing a layer of polysilicon (70) over CoSi2 (62) in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of CoSi2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer (64) to form contact windows before application of the polysilicon layer (70). Another oxide layer (78) is deposited over the polysilicon (70) and patterned before application of the cobalt layer (82) to define the areas which create the resistor load.

Description: METHODS OF FORMING A LOCAL INTERCONNECT AND A HIGH RESISTOR POLYSILICON LOAD BACKGROUND OF THE INVENTION The present invention relates to processes for forming local interconnects and polysilicon resistors on MOS devices. More particularly, the present invention relates to processes of forming local interconnects and polysilicon resistors by reacting cobalt with polysilicon. THE PRIOR ART High performance TJLSI microprocessors require large capacity, on chip SRAM while following the standard technology shrink path from previous generation devices. Polysilicon resistor load four-transistor (4-T) SRAM cells are desirable since they provide the system with the density required for performance enhancement. However, a simplified local interconnect is necessary in order to keep the shrink path from one technology to the next. The local interconnect technique has been suggested as a means to reduce the SRAM cell area by reducing the number of contacts used for interconnects and to provide a reliable alternative method to the buried contact scheme. Previous local interconnect schemes have concentrated around TiN processes in which the TiN was sputtered on or grown from TiSi 2 . Other techniques were based on PVD silicon films sputtered over titanium and the simultaneous formation of suicide and local interconnect structures. These techniques have not been reliable enough to be implemented in ULSI processes. The use of TiN over TiSi 2 has been suggested by Holloway et al. in U.S. Patent No. 4,657,628 and by Tang et al. in U.S. Patent No. 4,676,866. This technique, however, suffers from many processing problems which prevent the reliable manufacturing of these devices . TiN films which are grown from TiSi 2 are very thin for patterning and low sheet resistance. TiN also suffers from the lack of etch selectivity to TiSi 2 which makes it extremely hard to control subsequent dry and wet etch processes . Another shortcoming of this technique is the inability to strip the resist off of the wafer without degrading the line width control of the TiN local interconnect strap. Hydrogen peroxide, which is used to strip the photoresist mask, can also severely attack the TiN layer. Another technique has been suggested by Deveraux et al. in, "A New Device Interconnect Scheme For Sub-Micron VLSI," 84 IEDM pages 118-121. In this technique, a thin layer of refractory metal and amorphous silicon are deposited sequentially in the same pump down. The amorphous silicon is patterned and then the wafer is annealed whereby the refractory metal reacts with the amorphous silicon as well as single crystal silicon and polysilicon to form a suicide. The unreacted metal is then removed by wet etching. This technique suffers from limitations such as oxidation of the titanium film during the silicon dry etch which contains oxygen species. Additionally, the photoresist stripping agent showed a tendency for attacking the refractory metal which in this case was titanium. Polysilicon loads have been used in MOS devices for a substantial period of time. Published reports on polysilicon load processes have concentrated on two or more polysilicon layers used in conjunction with first layer polycided gate structures rather than salicided (both gate and drain) structures. A common process for forming polysilicon loads involves the following steps: gate oxide growth; deposition of polysilicon/tungstεn gate material; patterning of polysilicon/tungsten gate; etching of polysilicon/tungsten gate; patterning and implantation of N+ source/drain/gate; poly 1/poly 2 dielectric deposition; patterning of polysilicon contact; deposition of a second layer of polysilicon; patterning and etching of polysilicon resistor; patterning and implantation of N+ contact. This technique does not allow the use of salicide processes which are essential for low sheet resistance of gate and source/drain regions for high performance systems. Although tungsten suicide gate material with low sheet resistance has been used extensively, the source/drain regions exhibited very high sheet resistance requiring expensive circuit solutions to get around this limitation in high performance systems . In order to produce an acceptable contacting scheme between the second level polysilicon resistor and the first polysilicon gate or source/drain regions, it is necessary to solve the problems encountered with silicon to silicon or silicon to polysilicon interfaces. The native oxide films which are grown upon exposure of the substrate to ambient air can result in high contact resistance and process variations which significantly effect yields. Accordingly, the foregoing process was based on suicide free junctions in direct contact with the second polysilicon layer which is also free of suicide. This was followed by the resistor definition and contact patterning, followed by doping implantation at the contact region to reduce the electrical resistance of the second layer of polysilicon contact. SUMMARY OF THE INVENTION The invention in its broad form resides in a process as recited in claim 1 and also in a semiconductor device as in claim 2. In one preferred embodiment, the present invention provides a process for forming a local interconnect on an MOS device. An isolation step is performed to electrically isolate various devices from each other on an integrated circuit. A polysilicon gate material is deposited on the gate oxide, patterned and etched to form N and P channel CMOS transistors. Next, N+ and P+ doping provide the gate and source/drain control regions of the CMOS transistor. A thin oxide/nitride spacer is then formed on the sides of the gate regions. A layer of cobalt film is then deposited over the first layer of polysilicon and the active areas . This is followed by a rapid thermal anneal at 450°C. The cobalt which is in close contact with the polysilicon or the active areas forms a CoSi layer, while the cobalt in contact with the oxide or nitride does not react. The unreacted cobalt is subsequently etched from the device. The device is then subjected to another, high temperature anneal to form a low sheet resistant CoSi 2 film. Next, a thin layer of undoped LPCVD polysilicon film is deposited, patterned and etched to form the various components of the local interconnect straps . A second layer of cobalt film is then deposited over the entire surface and is reacted with the second layer of polysilicon through one or two annealing steps. The cobalt reacts with all of the second layer of thin polysilicon to form CoSi 2 interconnects with no polysilicon remaining. The cobalt in contact with the oxide or with the previously formed CoSi 2 does not react and is removed by etching. In a second embodiment of the present invention, a high resistor LPCVD polysilicon load is formed on a CMOS device either alone or simultaneously with the formation of the local interconnect described above. In this embodiment, the gate and source/drain regions of transistors are formed by conventional processes. A layer of cobalt■ is then deposited over the device and annealed to form CoSi 2 over the gate and source/drain regions. A layer of oxide is then deposited on the wafer, patterned and etched to provide a contact region for the ( second level polysilicon film which will form the resistor. The polysilicon film is then deposited on the wafer, patterned and etched to form the resistor region and the local interconnect. Another oxide layer is then deposited on the device, patterned and etched to expose the areas of the polysilicon resistor for which silicidation is desired to reduce the electrical contact resistance between the different levels of interconnect. Another layer of cobalt is then deposited on the device and annealed to form a second layer of CoSi 2 . The unreacted cobalt is subsequently stripped off of the device. BRIEF DESCRIPTION OF THE DRAWINGS Reference is next made to the drawings in which like parts are designated with like numerals throughout, and in which: FIGURES 1A - II are elevation views, in section, of a small part of a semiconductor wafer at successive stages of manufacture showing the formation of a local interconnect for an MOS transistor. FIGURES 2A - 2M are elevation views, in section, of a small part of a semiconductor wafer at successive stages of manufacture showing the formation of a high resistor polysilicon load and a local interconnect. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the method of making a local interconnect for an MOS integrated circuit device is illustrated in Figures 1A - II. The method includes forming a transistor in a face of a silicon wafer 10 by applying a polysilicon gate 12 over a gate oxide coating 14 in an active area surrounded by field oxide 18. Gate 12 as well as polysilicon gate 20 are formed by depositing a layer of polysilicon on the entire face of the wafer and patterning it by photomasking and etching in the usual manner. Source/drain regions 16 are created by ion implantation using standard techniques. The present invention can be used on N, P or CMOS devices. A thin oxide/nitride spacer is then formed on the sides of the gate regions as illustrated in FIGURES IB and IC. In the preferred embodiment, the spacers are formed by depositing a layer of oxide 22 followed by a layer of nitride 24. These layers are then selectively etched to leave the spacers on the side of the gate regions as illustrated in FIGURE IC. While the preferred embodiment uses a combination of an oxide layer and a nitride layer, it will be appreciated by tho.se skilled in the art that the spacer could be formed from oxide or nitride alone. In high-density devices, the depth of the source/drain regions is shallow, and so suicide is needed to lower the sheet resistivity. In the preferred embodiment, a self aligned suicide (salicide) is formed by first depositing a coating of cobalt 26 on the surface of the wafer as illustrated in FIGURE ID. Cobalt layer 26 can be formed by sputtering and is generally formed to a thickness of about 100 to 500 A. The device is then subjected to a rapid thermal anneal at about 450°C. The cobalt which is in close contact with the polysilicon and with the active areas forms a CoSi layer. Part of the silicon of the gate and the source/drain regions will be consumed as the suicide is formed. The cobalt which is in contact with the oxides and nitrides does not react and is subsequently etched in a solution of phosphoric, nitric and acetic acids and hydrogen peroxide. A second heat treatment is then performed at a temperature of 'from about 550 to 800°C and preferably at about 700°C to convert the CoSi to a low resistivity CoSi 2 layer 28. Next, as illustrated in Figures IF and 1G, a thin layer of undoped LPCVD polysilicon film 30 is deposited over the wafer to a thickness of about 300 to 2,000 A. The polysilicon is then patterned with a mask 32 and etched to form the various components of the local interconnect strap 34. Excellent etch selectivity is found between the polysilicon and the cobalt suicide. While the preferred embodiment uses polysilicon, it should also be appreciated that amorphous silicon can be used. A second layer of cobalt 36 is then deposited over the entire surface of the device as illustrated in Figure 1H. This layer of cobalt generally has a thickness of about 100 to 500 A. The wafer is again subjected to annealing to create cobalt suicide local interconnect 38. The annealing process can be performed in either one or two steps. It is presently preferred to use two steps. Sufficient cobalt should be provided to completely react with the polysilicon strap 34 leaving no polysilicon layer. The cobalt in contact with the oxide or with the previously processed CoSi 2 does not react and can be removed by a wet etch as discussed above. Accordingly, thicker cobalt layers can be used with no detrimental effect since the reaction will stop as soon as the second CoSi 2 layer comes in contact with the first CoSi 2 layer. The cobalt conversion to CoSi 2 stops when all of the silicon has been consumed and the second level suicide reaches and joins with the first layer of suicide. This means that the first CoSi 2 layer does not get any thicker and the reverse junction leakage current of the N+ and P+ junctions does not increase as a result of this second silicidation step. Reference is next made to FIGURES 2A - 2M which illustrate the simultaneous formation of a high resistor polysilicon load and a local interconnect on a semiconductor wafer. Referring first to FIGURE 2A, a pair of transistors are formed in a silicon wafer 50 and include polysilicon gates 52 and source/drain regions 56 which are surrounded by field oxide 58. Additional gates 60 are formed on portions of the field oxide. Each of the gates and source/drain regions includes a layer of cobalt suicide 62 which is formed according to the process described above. Referring now to FIGURE 2B, a layer of silicon oxide 64 is next deposited on the surface of the wafer 50 to a thickness of about 2,000 A. The oxide layer is then patterned and etched as illustrated in FIGURES 2C through 2E using masks 66 to provide a contact region for the second level polysilicon film. As illustrated in Figure 2F, a second layer of polysilicon 70 is then formed over the surface of the wafer. This layer of polysilicon film generally has a thickness of about 300 to 2,000 A. Polysilicon 70 is then patterned and etched using masks 72 to simultaneously form the local interconnect 74 and the resistor region 76 as illustrated in FIGURES 2G and 2H. In order to form a selective suicided polysilicon resistor, a new layer of oxide 78 with a thickness of about 1,000 A is next deposited on the wafer. As illustrated in FIGURES 21 through 2K, this oxide layer is then patterned and etched using a mask 80 to shield the portions of the polysilicon which will not be subjected to silicidation. Referring now to FIGURE 2L, a cobalt layer 82 is then formed over the surface of the wafer. This cobalt layer has a thickness of about 100 - 400 A and is annealed in a rapid thermal annealing system to form a second layer of CoSi 2 to form the CoSi 2 local interconnect 84 and the high resistor polysilicon load 86. The resistivity of the resistor is determined by the thickness of the polysilicon layer and the size of the oxide mask 88. With the present invention, no dopant is needed in the resistor contact region or in the resistor body since the second CoSi 2 layer is in close contact with the first CoSi 2 layer, providing good electrical contact. Since no dopant is used, prior art problems of lateral diffusion into the resistor is eliminated. Accordingly, the present invention permits the formation of very short resistors with high values . While the present invention has been described with reference to the preferred embodiments, the description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments will be apparent to persons skilled in the art upon reference to this description. For example, it will be readily apparent that the high resistor polysilicon load can be formed independent of the local interconnects. Additionally, the process of depositing polysilicon, converting it to CoSi 2 can be repeated many times to provide many different layers of interconnects. It is intended that the following claims be interpreted to embrace any and' all such modifications and changes .

Claims: WHAT IS CLAIMED IS: 1. A process for forming a local interconnect on a semiconductor device, comprising the steps of: providing a partially fabricated semiconductor device having a first layer of CoSi 2 (28) in the gate and source/drain regions; depositing a layer of silicon (30) on the surface of said device; patterning and etching said silicon to define an area as a local interconnect (34) ; depositing a layer of cobalt (36) over the surface of said device; and annealing said device at conditions such that said silicon and said cobalt react to form a second layer of CoSi 2 in close contact with said first layer of CoSi 2 . 2. A semiconductor device having a local interconnect formed by a process comprising: providing a partially fabricated semiconductor device having a first layer of CoSi 2 (28) in the gate and source/drain regions; depositing a layer of silicon (30) on the surface of said device; patterning and etching said silicon (30) to define an area as a local interconnect (34) ; lδ depositing a layer of cobalt (36) over the surface of said device; and annealing said device at conditions such that the layer of cobalt and silicon react to form a second layer of CoSi 2 in close contact with said first layer of CoSi 2 . 3. A process for forming a high resistor polysilicon load on a semiconductor device, comprising the steps of: providing a partially fabricated semiconductor device having a first layer of CoSi 2 (62) in the gate and source/drain regions; depositing an oxide layer (64) on a surface of said device; patterning said oxide layer to form contact windows extending to the surface beneath said oxide layer; depositing a layer of polysilicon (70) over the surface of said device; patterning and etching the polysilicon to form a resistor region (76) ; depositing and patterning an oxide layer (78) to form a mask over a portion of the polysilicon which will provide the resistive load; depositing a layer of cobalt (82) over said device; and annealing said device under conditions such that the cobalt and polysilicon react to form a second layer of CoSi 2 in close contact with said first layer of CoSi 2 . 4. A semiconductor device having a high resistor polysilicon load formed by a process comprising: providing a partially fabricated semiconductor device having, a first layer of CoSi 2 (62) in the gate and source/drain regions; depositing an oxide layer (64) on a surface of said device; patterning said oxide layer to form contact windows extending to the surface beneath said oxide layer; depositing a layer of polysilicon (70) over the surface of said device; patterning and etching the polysilicon to form a resistor region (76) ; depositing and patterning an oxide layer (78) to form a mask over a portion of the polysilicon which will provide the resistive load; depositing a layer of cobalt (82) over said device; and annealing said device under conditions such that the cobalt and polysilicon react to form a second • layer of CoSi 2 in close contact with said first layer of CoSi 2 . 5. A process for simultaneously forming a local interconnect and a high resistor polysilicon load on a semiconductor device, comprising the steps of: providing a partially fabricated semiconductor device having a first layer of CoSi 2 (62) in the gate and source/drawin regions; depositing an oxide layer (64) on a surface of said device; patterning and etching said oxide layer to form contact windows extending to the surface beneath said oxide layer; depositing a layer of polysilicon (70) over the surface of said device; patterning and etching the polysilicon to define areas as a local interconnect region (74) and a resistor region (76) ; depositing and patterning an oxide layer (78) to form a mask over a portion of the polysilicon in said resistor region which will supply the resistive load; depositing a layer of cobalt (82) over said device; and annealing said device at conditions such that the cobalt and polysilicon react to form a second layer of CoSi 2 in close contact with said first layer of CoSi 2 .

Inventors: NASR ANDRE I, NASR, ANDRE, I.
Applicants: DIGITAL EQUIPMENT CORP, DIGITAL EQUIPMENT CORPORATION
Application year: 1993
Main classification: H01L21
IPC codes: H01L21, H01L27