Input circuit for an integrated circuit

Abstract: An input circuit arrangement for an integrated circuit includes an input circuit (12₁) which includes a first series summing amplifier having a first input which is connected to an input pad (16₁) for the integrated circuit and a second input which is connected to an output line (44) of a control voltage generating means (14). The control voltage generating means (14), which sets a highly stable, accurate threshold voltage for the input circuit (121), includes a second series summing amplifier having a first input connected to a voltage divider (42) which supplies a reference voltage, and a second input connected to the output line (44). The second series summing amplifier includes series-connected FETs (20,21,24,25) having transconductances matched to corresponding FETs (50₁,51₁,54₁,55₁) in the first series summing amplifier.

Description: This invention relates to an input circuit for an integrated circuit. Integrated circuits are designed using standard cells from a standard cell library. Standard cell libraries are not readily developed. Rather, such libraries must be labouriously worked out transistor by transistor and cell by cell by the designers. A typical library development cycle consists of defining the physical sizes of the devices, specifying the desired performance parameters, e.g. speed, noise margin, etc., designing the cells, simulating the cell designs, making prototype integrated circuits using the cell designs, and measuring the actual characteristics of the prototype integrated circuits. Usually the characteristics are used to go back and revise the design of various cells so that the desired performance parameters are met. This revision requires a second prototype set of integrated circuits and a measurement of the characteristics of the revised integrated circuits. One of the more important cells in a library is the pad input cell. One of the harder things to do is design a library that is manufacturing process independent. It is an object of the present invention to provide input means for an integrated circuit, whereby a stable, accurate threshold voltage is provided for discriminating between input signal logic levels. The features set out in the preamble portion of Claim 1 are known from PATENT ABSTRACTS OF JAPAN, Vol 12, No. 115, (E-599) [2962] for JP-A-62 243 422. The present invention is characterized in that the second series summing amplifier means includes a second series summing amplifier coupled to an inverter which is coupled to another inverter and which provides the said output thereof. One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which:- Fig. 1 is a block diagram showing the application of the invention to an integrated circuit; Fig. 2 is a schematic diagram of a CMOS embodiment of the invention; Figs. 3 and 4 show the use of the invention in forming more complex Schmitt trigger binary circuits using the invention; and Fig. 5 is a schematic diagram of a second CMOS embodiment of the invention. Referring now to Fig. 1, part of an integrated circuit 10 is shown. Integrated circuit 10 has a number of binary input circuits 12 1 -12 N , each of which is connected to a common reference control voltage supply 14. Each of the binary input circuits 12 1 -12 N is connected to a respective pad 16 1 -16 N where an input lead (not shown) is physically and electrically connected in order to provide a binary input signal voltage. Reference control voltage supply 14 provides a reference control voltage that is derived from voltages commonly present on binary integrated circuits. This reference control voltage is used to precisely set the threshold voltage of each of the binary input circuits 12 1 -12 N . A data input voltage at or above the threshold voltage causes the binary input circuit 12 1 to respond with a binary logic high output, while an input voltage below the threshold level causes the binary input circuit 12 1 to respond with a binary logic low output. The remaining binary input circuits 12 2 -12 N respond in substantially the same manner. Referring now to Fig. 2, a CMOS embodiment of the reference control voltage circuit 14 is shown in detail, as is one embodiment of the binary input circuit 12 1 of the plurality of binary input circuits 12 1 -12 N . All of the plurality of binary input circuits 12 1 -12 N are substantially the same, differing by manufacturing variations, so only binary input circuit 12 1 will be described in connection with Fig. 2. Those skilled in the integrated circuit art will recognize that the embodiment shown in Fig. 2 could be readily adapted to other logic families such as BiCMOS, TTL, etc. Reference control voltage circuit 14 is made up of three stages. The first stage is a series summing amplifier stage. The series summing amplifier is made up of two p-channel field effect transistors (FETs) 20, 21 and two n-channel FETs 24, 25. Those skilled in the art of CMOS logic will recognize that each FET channel has a channel terminating electrode (CTE) at each of the two channel ends and a gate as the control electrode. Since in CMOS integrated circuits the FETs are highly symmetrical, CTE is more descriptive because there is no difference between the source electrode and the drain electrode, except for voltage connections. P-channel FET 20 has its first CTE connected to the positive supply voltage bus V DD of the integrated circuit chip 10. A second CTE of p-channel FET 20 is connected in series with a first CTE of p-channel FET 21. A second CTE of p-channel FET 21 is connected in series with a first CTE of n-channel FET 24. A second CTE of n-channel FET 24 is connected in series to a first CTE of a second n-channel FET 25. A second CTE of the n-channel FET 25 is connected to circuit ground of the integrated circuit 10. A gate of p-channel FET 20 is connected to a gate of n-channel FET 25. A gate of p-channel FET 21 is connected to a gate of n-channel FET 24. FETs 21, 22, 24 and 25 connected in this manner form a series summing amplifier 26. The common connection of the gates of FETs 21 and 24 is the first inverting input and the common connection of the gates of FETs 20 and 25 is the second inverting input of the series summing amplifier 26. The output of this series summing amplifier 26 is the common connection of the second CTE of FET 21 and the first CTE of FET 24. The output of the series summing amplifier 26 is connected to a CMOS inverter 30. CMOS inverter 30 is made up of a p-channel FET 32 and n-channel FET 34. A first CTE of FET 32 is connected to V DD . A second CTE of FET 32 is connected in series to a first CTE of FET 34. A second CTE of FET 34 is connected to circuit ground. A gate of FET 32 is connected to a gate of FET 34, and together they form the input of CMOS inverter 30. The output of CMOS inverter 30 is the common connection of the second CTE of FET 32 and the first CTE of FET 34. The output of the inverter 30 is connected to another CMOS inverter 36. CMOS inverter 36 is made up of a p-channel FET 38 and n-channel FET 40. A first CTE of FET 38 is connected to V DD . A second CTE of FET 38 is connected in series to a first CTE of FET 40. A second CTE of FET 40 is connected to circuit ground. A gate of FET 38 is connected to a gate of FET 40, and together they form the input of CMOS inverter 36. The output of CMOS inverter 36 is the common connection of the second CTE of FET 38 and the first CTE of FET 40. The first inverting input of the series summing amplifier 26 is connected to a voltage reference 42, which in this embodiment is a pair of resistors R 1 and R 2 , connected in a voltage divider configuration dividing the difference in potential between V LOGIC OUTPUT HIGH and V LOGIC OUTPUT LOW . The output of the voltage reference 42 is (V LOH -V LOL )(R 2 )/(R 1 +R 2 ) according to the well known law of voltage division. Resistors R 1 and R 2 can be manufactured such that their ratio is within 1% of the design center value. Thus, the voltage divider output will be within 1% of the desired division of the potential between V LOH and V LOL . Further, because R 1 and R 2 are manufactured on the same chip by the same process, variations related to the manufacturing process will occur equally to both resistors resulting in a voltage division ratio that is highly accurate and very stable. The logic HIGH and logic LOW levels are nominally 5.0 volts, i.e. V DD , and 0.0 volts, i.e. V SS , for typical CMOS digital integrated circuits; however, it may be desirable to provide a logic HIGH voltage that is different from the 5.0 volt V DD and the 0.0 volt V SS in order to reduce power dissipation. The circuit shown in Fig. 2 is particularly adaptable to operate with a logic HIGH of 2.0 volts and a logic LOW of 1.0 volts in order to provide low power dissipation binary signal levels between integrated circuits. The voltage of the voltage reference 42 is applied to the first inverting input of series summing amplifier 26, where it is inverted and amplified. An inverted and amplified version of the input, that is present at the output of series summing amplifier 26, is applied to the input of inverter 30, where the voltage is inverted and amplified a second time. An inverted and amplified version of the input, that is present at the output of inverter 30, is applied to the input of inverter 36 where the voltage is inverted and amplified a third time. The output of the inverter 36, which is an inverted and amplified version of the voltage of reference voltage 42, is fed back to the second inverting input of the series summing amplifier 26. Since the voltage that is fed back has a net inversion with respect to its inverting inputs and since the fed back voltage is applied to the second inverting input of series summing amplifier 26, this is a negative feedback voltage. Connected in this manner, if FETs 20, 21, 24, and 25 all had the same magnitude of transconductance, then the dynamics of reference voltage circuit 14 would drive the output voltage thereof towards the level of the reference voltage 42 impressed upon its first input. However, the transconductance of FETs 20, 21, 24, and 25 are selected by adjusting their channel widths such that the operating point of the first inverting input of reference voltage circuit 14 is centered about (V LOH - V LOL )/2 and the operating point of the output, i.e. the second inverting input, is centered about V DD /2. To effect these operating points, the magnitude of the transconductance of FET 20 is matched to that of FET 25 and the magnitude of the transconductance of FET 21 is matched to that of FET 24, and the ratio of the transconductance magnitudes of FETs 21, 24 to FETs 20, 25 are adjusted until the two desired operating points are achieved. Since the desired operating points are set by transconductance ratios, they tend to be manufacturing process independent. This is because any manufacturing variations tend to affect the transconductance magnitudes of FETs 20, 25 proportionately the same as the transconductance magnitudes of FETs 21, 24, thereby maintaining the desired ratios and operating points. This is in addition to the stability and accuracy that the negative feedback provides to voltage reference circuit 14. The stable and accurate voltage outputted by voltage reference circuit 14 is connected to conductor 44, which is connected to the binary input circuit 12 1 , as will be described below. Binary input circuit 12 1 has a series summing amplifier that is made up of two p-channel FETs 50 1 , 51 1 and two n-channel FETs 54 1 , 55 1 . P-channel FET 50 1 has its first CTE connected to the positive supply voltage bus V DD . A second CTE of p-channel FET 50 1 is connected in series with a first CTE of p-channel FET 51 1 . A second CTE of p-channel FET 51 1 is connected in series with a first CTE of n-channel FET 54 1 . A second CTE of n-channel FET 54 1 is connected in series to a first CTE of a second n-channel FET 55 1 . A second CTE of the n-channel FET 55 1 is connected to circuit ground. A gate of p-channel FET 50 1 is connected to a gate of n-channel FET 55 1 . A gate of p-channel FET 51 1 is connected to a gate of n-channel FET 54 1 . FETs 51 1 , 52 1 , 54 1 and 55 1 connected in this manner form a series summing amplifier stage. The common connection of the gates of FETs 51 1 and 54 1 is the first inverting input of the summing amplifier stage and the common connection of the gates of FETs 50 1 and 55 1 is the second inverting input of the summing amplifier stage. The output of this series summing amplifier stage is the common connection of the second CTE of FET 51 1 and the first CTE of FET 54 1 . Another CMOS inverter stage is comprised of a p-channel FET 62 1 and an n-channel FET 64 1 . A first CTE of FET 62 1 is connected to V DD . A second CTE of FET 62 1 is connected in series to a first CTE of FET 64 1 . A second CTE of FET 64 1 is connected to circuit ground. A gate of FET 62 1 is connected to a gate of FET 64 1 to form the input of this inverter stage. The input of this inverter stage is connected to the output of the summing amplifier at the common connection of the second CTE of FET 51 1 and the first CTE of FET 54 1 . The output of this CMOS inverter stage is taken from the common connection of the second CTE of FET 62 1 and the first CTE of FET 64 1 . This output is also called Binary Output 1 of the binary input circuit 12 1 . A binary input pad 16 1 is connected to the first inverting summing amplifier input that is also one of the non-inverting inputs of the binary input circuit 12 1 because of the additional inversion performed by the CMOS inverter stage formed by FETs 62 1 , 64 1 . Similarly, the second non-inverting summing amplifier input is a second non-inverting input of the binary input circuit 12 1 . The second inverting input of the binary input circuit 12 1 is connected via conductor 44 to the output of the reference control voltage supply 14. Reference control voltage supply 14 is also connected to all of the other binary input circuits 12 2 -12 N (as shown in Fig. 1). The reference control voltage supply 14 by connection to the second inverting input of binary input circuit 12 1 sets a threshold beyond which the voltage level that the voltage on the first inverting input must equal or exceed before a change in the binary input level will be experienced by the series summing amplifier formed by FETs 50 1 , 51 1 , 54 1 , and 55 1 . FETs 50 1 and 55 1 are crafted to have the same characteristics as FETs 20 and 25 respectively. Similarly, FETs 51 1 and 54 1 are crafted to have the same characteristics as FETs 21 and 24 respectively. Thus, the threshold voltage of the input circuit 12 1 will be set to substantially (V LOH V LOL )/2 by the similarities of characteristics and structure with the reference voltage supply 14. Once the threshold voltage set by reference voltage supply 14 is equalled or exceeded, by the voltage input on pad 16 1 the high gain of the series summing amplifier of FETs 50 1 , 51 1 , 54 1 , and 55 1 cascaded with the inverter of FETs 62 1 , 64 1 causes the output of binary input circuit 12 1 to be amplified all the way to a logic high voltage. Conversely, as long as the voltage input on pad 16 1 is less than the threshold voltage of the high gain of the series summing amplifier of FETs 50 1 , 51 1 , 54 1 , and 55 1 cascaded with the inverter of FETs 62 1 , 64 1 causes the output of binary input circuit 12 1 to be amplified all the way to a logic low voltage. Since the output voltage of the reference voltage supply 14 is accurately set by resistors R 1 and R 2 and maintained by a negative feedback circuit 26, 30, 36 that is stable relative to temperature and process variations, the lower data threshold can be accurately and stably set. Further because FETs 50 1 , 51 1 , 54 1 , and 55 1 are similar in characteristics and structure to FETs 20 1 , 21 1 , 24 1 , and 25 1 , the operation of FETs 50 1 , 51 1 , 54 1 , and 55 1 will be immune from manufacturing process variations as long as the characteristics of FETs 50 1 , 55 1 maintains the desired ratio of their respective transconductances with FETs 51 1 , 54 1 . Simulations of the embodiment shown in Fig. 2 have shown that this binary input circuit will tolerate variations in the intrinsic threshold voltage of the FETs (V T ) by 100 millivolts. This is many times the 5 to 10 millivolt variation in V T that normally occurs across an integrated circuit chip. Thus, a CMOS embodiment of an binary input circuit of an integrated circuit cell library may has been described where the input logic switching characteristic is set substantially by a pair of resistors in a voltage divider arrangement. Referring now to Fig. 3, another embodiment of a binary input circuit, called a Schmitt trigger circuit 80, is shown. Schmitt trigger circuit 80 has first and second binary input circuits 12', 12", which are both substantially the same as the binary input circuit 12 1 shown in Fig. 2. First binary input circuit 12' has its first inverting input connected to an input pad 16', which is substantially the same as the input pad 16 shown in Fig. 2. Input pad 16' is also connected to a first inverting input of binary input circuit 12". A reference voltage supply 14', which is substantially the same as reference voltage supply 14 shown in Fig. 2, is connected to a second inverting input of binary input circuit 12' by conductor 44'. Reference supply voltage 14' is also connected to a second inverting input of binary input circuit 12". Since binary input circuits 12' and 12'' have their inputs connected identically, the FETs connected to the first and second inputs of binary input circuit 12' are provided with different transconductance ratios than the FETs connected to the first and second inputs of binary input circuit 12' in order to provide two different switching points for the same threshold voltage. Connected in this manner, if the input voltage impressed on pad 16' is below the lower switch point, then the output of input circuit 12'' will be an active low and the output of the inverter 81 attached to the output of the input circuit 12' will be an inactive high. Thus, RS flip-flop 82 will be reset. If the voltage impressed on pad 16' is equal to or greater than the lower switch point but below the upper switching point, the output of the input circuit 12'' will change to an inactive high and the output of inverter 81 will remain at an inactive high. Thus, the RS flip-flop 82 will remain in its present state, which in this case is reset. If the voltage impressed on pad 16' is equal to or greater than the upper switching point, the output of input circuit 12'' will remain at inactive high and the output of inverter 81 attached to input circuit 12' will be an active low. Thus, the Schmitt trigger circuit 80 has both upper and lower switch points set by the output of the single reference voltage supply 14'. Referring now to Fig. 4, a Schmitt trigger 80' is shown. Schmitt trigger 80' is a variation of the Schmitt trigger circuit 80 shown in Fig. 3. The difference is that Schmitt trigger 80' has the first inverting input of binary input circuit 12'' connected by conductor 44'' to a second reference voltage supply 14". The second reference voltage supply 14'' has its voltage divider ratio selected such that the output voltage of the second reference voltage supply 14'' is higher than the output voltage of the first reference voltage supply 14'. The first reference voltage supply 14' sets the lower Schmitt trigger threshold switching point and the second reference voltage supply 14'' sets the upper Schmitt trigger threshold switching point. Since the reference voltage supplies 14' and 14'' setting the upper and lower switching points, the input FETs of the binary input circuits 12', 12'' could be equivalent in respective transconductances to each other. Alternatively, the input FETs of the binary input circuits 12', 12'' could be adjusted such that each would have its operating point centered around its respective switching point. Referring now to Fig. 5, a reference voltage supply 14A which may be used instead of the reference voltage supply 14 shown in Fig. 2 on the integrated circuit 10. Reference voltage supply 14A is the same as reference voltage supply 14 with the addition of resistor R 3 and FETs 90, 91, 92 and 93. FET 90 has its gate connected to one CTE and its other CTE connected to V DD . Similarly, FET 91 has its gate connected to one CTE and its other CTE connected to circuit ground. Resistor R 3 has a first lead connected to the gate-CTE junction of FET 90 and a second lead connected to the gate-CTE junction of FET 91. In this configuration, FET 90 will act as a diode having its anode connected to V DD and its cathode connected to the first lead of resistor R 3 . Similarly, FET 91 will act as a diode having its anode connected to the second lead of the resistor and its cathode connected to circuit ground. The output inverter 36A is substantially the same as the output inverter 36 shown in Fig. 2 with the addition of FETs 92 and 93. FET 92 is a p-channel type and has a first CTE connected to V DD . A second CTE of FET 92 is connected to a first CTE of FET 38A. A second CTE of FET 38A is connected to a first CTE of FET 40A as with FETs 38 and 40 shown in Fig. 2. FET 93 is an n-channel type and has a first CTE connected to circuit ground and a second CTE connected to a second CTE of FET 40A. A gate of FET 92 is connected to the first lead of resistor R 3 and a gate of FET 93 is connected to the second lead of resistor R 3 . FETs 90, 91, 92, and 93 and R 3 form a current mirror circuit in which the current through FET 90 is mirrored by, i.e. is substantially the same as, the current in FET 92 and the current in through FET 91 is mirrored by the current in FET 93. The current through FETs 92 and 93 is reduced to a low value by making R 3 as large as possible. This reduced current reduces any tendency of the feedback signal to induce oscillator behaviour. The reference voltage circuit 14A because of the added components has a better voltage regulation than the reference voltage supply 14 shown in Fig. 2, but at the cost of the extra components and the extra integrated circuit chip area occupied by the additional components. Thus, in Figs 2 and 5 a trade-off is provided to the integrated circuit designer between voltage regulation and smoothness provided by the reference voltage circuit and the area occupied by the voltage reference circuit. Thus, it will now be understood that there has been disclosed a binary input circuit for an integrated circuit that has a high tolerance for manufacturing and environmental variations by using a reference voltage supply to select the switching threshold. A single reference voltage supply can set the switching threshold for a plurality of such input circuits.

Claims: Input means for an integrated circuit, comprising an input circuit (12 1 ) including first series summing amplifier means having a first input connected to receive an input signal to said integrated circuit, a second input (44) connected to receive a control voltage provided by control voltage generating means (14), and an output, wherein the logic level provided on said output is determined by whether the input signal voltage of input signal is above or below a threshold voltage determined by said control voltage, the control voltage generating means (14) including a second series summing amplifier means (26, 30, 36) having a first input connected to receive a reference voltage provided by a voltage reference circuit (42), a second input and an output, and wherein the output of said second series summing amplifier means (26, 30, 36) provides said control voltage and is connected to said second input of said second series summing amplifier means (26, 30, 36) via a negative feedback connection, and characterized in that the second series summing amplifier means (14) includes a second series summing amplifier (26) coupled to an inverter (30) which is coupled to another inverter (36) and which provides the said output thereof. Input means according to Claim 1, characterized in that said first series summing amplifier means includes a first series summing amplifier coupled to a first inverter connected to said output of first series summing amplifier means. Input means according to Claim 2, characterized in that said first series summing amplifier includes first, second, third and fourth FETs (50 1 , 51 1 , 54 1 , 55 1 ) connected in series, wherein said first and second FETs (50 1 , 51 1 ) are p-channel FETs and second third and fourth FETs (54 1 , 55 1 ) are n-channel FETs and wherein said first input of said first series summing amplifier means is connected to the gates of said second and third FETs (51 1 , 54 1 ) and said second input of said first series summing amplifier means is connected to the gates of said first and fourth FETs (50 1 , 55 1 ). Input means according to Claim 3, characterized in that said second series summing amplifier includes fifth, sixth, seventh and eighth FETs (20, 21, 24, 25) connected in series, wherein said fifth and sixth FETs are p-channel FETs and said seventh and eighth FETs are n-channel FETs, and wherein said first input of said second series summing amplifier means is connected to the gates of said sixth and seventh FETs (21, 24) and said second input of said second series summing amplifier means is connected to the gates of said fifth and eighth FETs (20, 25). Input means according to Claim 4, characterized in that the transconductances of said first, second, third and fourth FETs (50 1 , 51 1 , 54 1 , 55 1 ) are matched to the transconductances of said fifth, sixth, seventh and eighth FETs (20, 21, 24, 25), respectively. Input means according to Claim 5, characterized in that said first, second and third inverters include respective series-connected p-channel and n-channel FET pairs (62 1 , 64 1 ; 32, 34; 38, 40). Input means according to Claim 5, characterized by current mirror means (90-93) connected to the series connected FETs of said third inverter (36A). Input means according to Claim 7, characterized in that said voltage reference circuit (42) includes a voltage divider (R 1 , R 2 ). Input means according to any one of the preceding claims, characterized by at least one further input circuit (12 N ) substantially identical to said input circuit (12 1 ) and coupled to receive said control voltage provided by said control voltage generating means (14).

Inventors: CRAFTS HAROLD S, CRAFTS, HAROLD S.
Applicants: HYUNDAI ELECTRONICS AMERICA, NCR INT INC, SYMBIOS LOGIC INC, SYMBIOS LOGIC INC.
Application year: 1993
Main classification: H03K19
IPC codes: H03K19, H03K17, H03K3, H03K5