Data transmission apparatus

Abstract: An ADRC encoder generates, regarding an ADRC block of 4x4 pixels, DR, MIN and quantized data corresponding to each pixel. A macro block formatting circuit generates code data DR, MIN and DT of four ADRC blocks. An adding circuit generates sum data (DR =DR1 + DR2 + DR3 + DR4, same calculation regarding MIN) of important data in the macro block. Mixing circuits insert the sum data into recording data as additional data. The sum data and the important data are distributed and recorded in plural channels. If one of the important data has an error and the remaining important data and the sum data have no error, the important data with the error can be completely corrected. Error correction of the important data and the quantized data generated by block encoding is effected with restrained increase in redundancy. Input data which has been reproduced and DCT-decoded is supplied to and is converted into 3x3 block format by a 3-line memory and block formatting circuit . An ADRC encoding circuit generates encoded data DTx of a center pixel data and data DT which is made up of peripheral 8 pixel data. A timing aligning circuit generates class information comprising 8 pixel data and the class information is supplied to a memory as a read address. Memory stores existing-range data and predicted data DTx^ through in-advance training. An error is detected by comparing the existing-range data and reproduced data DTx and when there is an error, predicted data DTx is selected. Error correction of received or reproduced image data is effected without using an error correction code.

Description: This invention relates to data transmission apparatus for transmitting (including recording and/or reproducing) code data, and is applicable for example to a digital video tape recorder (VTR) where digital video signals are encoded by block encoding to compress the amount of data so that the digital video signals are divided into small blocks and are processed block by block. When digital video signals are recorded on a recording medium such as a magnetic tape, it is conventional to compress the digital video signals by high-efficiency encoding in order to make the transmission rate low enough to record/reproduce, because the data amount of the digital video signals is large. Block encoding, such as ADRC (Adaptive Dynamic Range Coding) and DCT (Discrete Cosine Transform), which divide digital video signals into small blocks and encodes them block by block, are known as high-efficiency encoding techniques. EP-A-0 318 244 discloses an image data encoding apparatus in which pixel data is organised into blocks and processed to compress the amount of data. The pixel data of each block is processed to determine the minimum (MIN) and maximum (MAX) pixel values, the average value mo and encoded pixel data ID. The data MIN, MAX, mo and ID are transmitted in a serial data packet. US-A-4,984,076 also encodes pixel data organised in blocks. The number of bits per block in a frame of N blocks is controlled by computing a value A = i =1 N a i where a i is the difference between the maximum and minimum pixel values of a block i , and N is the number of blocks in a frame. The number of bits b i per block i is controlled according to where B is the total number of bits allocated to a frame, Neither EP-A-0 318 244 not US-A-4 984 076 is concerned with correcting errors in the data relating to a block. ADRC is a high-efficient encoding which calculates a dynamic range defined by maximum and minimum levels of pixel data among plural pixels included in a two-dimensional block, and encodes the pixel data in accordance with the dynamic range, as described in Japanese Laid-open patent 61-144989. DCT is to cosine-transform pixels in a block, to re-quantize co-efficient data obtained by the cosine-transformation, and to encode them by variable-length encoding. Another encoding method has been suggested in which data averages of every blocks and the difference between each pixel data and the average in each block are vector-quantized. Code outputs resulting from a block encoding do not have equal importance. In ADRC, if dynamic range information is unknown at the reproducing side, errors extend to all pixels of that block. Therefore, the dynamic range information which is obtained for every blocks is more important than the code signal which is obtained for every pixels. In one type of ADRC in which the number of bits for quantization varies depending upon the dynamic range, if there is an error about the dynamic range, the number of bits for quantization of that block cannot be identified at the receiving side. As a result, the boundaries between that block and other blocks become unknown so that errors extend to the other blocks. Among coefficient data generated in DCT encoding, a DC (direct current) component is more important than AC (alternating current) components. A refresh data in DPCM encoding is also important data. When outputs of block encoding are recorded/reproduced by a digital VTR, for example, an error correction code is used to protect data against recording/reproducing errors. When an important data happens to have an error which the error correction code cannot correct, the error extends to the whole block. To cure the problem, the same important data is recorded twice at locations separate enough to be not subject to a burst error. However, redundancy would increase and efficiency of data compression would be lowered. With respect to a block having an error in important data, the error of the important data is statistically presumed based upon spacial correlation between that block and peripheral blocks. In the more concrete, A least-squares method using the code data of the error block and the decoded data located at boundaries of the peripheral blocks may be also used to presume the important data in the error block. The maximum and minimum values of boundary data of the peripheral blocks may be used to presume the important data. The presumed important data is used for decoding. Even though the important data is presumed with high accuracy, original important data cannot be restored completely. In addition, finding boundaries between each data block correctly is necessary to presume the important data. Therefore, if an error extends to several blocks, the important data cannot be presumed. When digital video signals are recorded/reproduced in a digital VTR for example, it is also conventional to use error correction coding for correcting errors. As an error correction code, simple parity, Read-Solomon code and a combination of these and interleaving have been practically used. However, when an error correction code is used, redundancy of data increases due to an increase in the number of parity bits in order to improve an error correction ability. When the error cannot be corrected by the error correction code, a conceal circuit would be necessary to interpolate pixel having an error with peripheral correct pixel data. Data such as a computer software generally has no correlation. However, video signals have a correlation in space and in time. According to the present invention there is provided data encoding apparatus for encoding pixel data comprising means for encoding blocks of pixels to compress the amount of data, the encoding means producing, for each block, encoded pixel data relating to individual pixels of the block and block data relating to all the encoded pixel data of the block and without which the encoded pixel data cannot be correctly decoded characterised by means for producing sum data representing a sum, or respective sums, of block data associated with a plurality of the said blocks, and means for transmitting the, or each, said sum data separately from the said block data of the said plurality of blocks. The term "transmitting" is used as a generic term for transmitting and recording and/or reproducing. By providing the said sum data, an error in the block data may be corrected using the sum data and other, correct, block data. The number of bits needed to represent the sum data is less than the number of bits needed, for example, to record block data redundantly as in the prior art. By transmitting the sum data separately from the block data, the likelihood of it being lost with the block data is reduced. In ADRC, the block data is dynamic range DR and minimum value MIN. In an embodiment of the invention the sum data of n dynamic range data DR and the sum data of n minimum data MIN are inserted into transmitted data. If one of DRs and MINs has an error and the sum data and the other important data have no error, the correct important data can be reproduced at the receiving side. Redundancy can be lower than when the same important data is recorded several times. The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of an example of a recording circuit for a digital VTR to which the present invention can apply. Fig. 2 shows an example of a recording pattern in an embodiment of the present invention. Fig. 3 shows an example of a construction of a ADRC block in an embodiment of the present invention. Fig. 4 shows an example of a construction of a macro block in an embodiment of the present invention. Fig. 5 is a block diagram of an example of a reproducing circuit for a digital VTR to which the present invention can apply. Fig. 6 is a block diagram of an example of a sum data generating circuit in an embodiment of the present invention. Fig. 7 is a timing chart for explanation of a sum data generating circuit in an embodiment of the present invention. Fig. 8 is a block diagram of another example of a mixed sum data generating circuit. Fig. 9 is a timing chart for explanation of another example of a mixed sum generating circuit. Fig . 10 is a block diagram of further example of a mixed sum generating circuit. Fig. 11 is for explanation of further example of a mixed sum generating circuit. Fig. 12 is a timing chart for explanation of further example of a mixed sum generating circuit. Fig. 13 is a block diagram of still further example of a mixed sum generating circuit. Fig. 14 is a timing chart for explanation of still further example of a mixed sum generating circuit. Fig. 15 is a drawing for explanation of a mixed sum generating circuit which applies to quantized data. An embodiment of the present invention will be described hereinafter. Fig. 1 shows an embodiment, that is, an outline construction of signal processing for a digital VTR. Digital video signals are supplied from an input terminal 1. This input signals have 8-bit data for each pixel, for example. The input digital video signals are supplied to a block-formatting circuit 2. In this embodiment, block-formatting circuit 2 divides a valid area of one frame into blocks each having 4×4 pixels, 8×8 pixels, 4×8 pixels or similar. Block-formatting circuit 2 supplies to an ADRC encoder 3 digital video signals which had been scan-converted in the order of the blocks. ADRC encoder 3 compresses pixel data block by block. ADRC encoder 3 supplies encoded output to a macro-block-making circuit 4. A macro block comprises a plurality of ADRC blocks which have been made by block-formatting circuit 2. ADRC encoder 3 detects dynamic range DR and minimum value MIN of each block. ADRC encoder 3 requantizes the video data less minimum value MIN by a quantizing step. In ADRC using a fixed 4-bit length, quantizing step Δ can be obtained by dividing dynamic range DR by 16. The video data less the minimum value is divided by quantizing step Δ. Integral part of quotient is a quantized data DT. Dynamic range DR, minimum value MIN and quantized data DT are output data of ADRC encoder 3. Each block has dynamic range DR and minimum value MIN as important data. Macro block-formatting circuit 4 generates coded data of macro blocks. Quantized data DT of the macro blocks are supplied to an error correction encoder 5. Dynamic range DR and minimum value MIN of the macro blocks are supplied to an adding circuit 6. Adding circuit 6 generates the sum data DRΣ of plural dynamic ranges DRs and the sum data MINΣ of plural minimum values MINs included in a macro block. These sum data are supplied through memories 7 and 8 to mixing circuits 9 and 10. Original important data (DR, MIN), which have been through adding circuit 6, are supplied to mixing circuits 9 and 10. The outputs of mixing circuits 9 and 10 are supplied to error correction encoder 5. The output data of ADRC encoder 3 is supplied to error correction encoder 5. Error correction encoder 5 generates a parity of an error correction code. A product code can be utilized as an example of the error correction code. In a product code, data are arranged as a matrix and error correction encoding applies to each of horizontal and vertical directions of the matrix. Block synch signal (SYNC) and ID signal are added to the code data and the parity. Record data having continual synch blocks are supplied to a channel encoder 11 which channel-encodes the record data in order to reduce a direct current component. The output data of channel encoder 11 is supplied to a head interleave circuit 12. Head interleave circuit 12 generates six channels of record data. Head interleave circuit 12 supplies each channel of the record data through a recording amplifier 13 to rotary heads H1-H6. Head interleave circuit 12 interleaves the recording data among the plural channels. Rotary heads H1-H6 simultaneously form six tracks on a magnetic tape T. Fig. 2 shows a recording pattern formed on magnetic tape T. Respective slant tracks corresponding to respective heads H1 - H6 have respective references CH1 - CH6. In this embodiment, as shown in Fig. 3, one ADRC block has (4×8) pixels. Assuming that a valid area of one field of video has (240 lines × 720 pixels), (60 × 90) ADRC blocks are formed in one field, as shown in Fig. 4. Further assuming that a macro block has (2×2 = 4) ADRC blocks, adding circuit 6 carries out the following adding calculations to generate the sum data DRΣ and MINΣ. DRΣ = DR1 + DR2 + DR3 + DR4 MINΣ = MIN1 + MIN2 + MIN3 + MIN4 When each important data is 8-bit data, 10-bit sum data is generated. As shown in Fig. 4, head interleave circuit 12 distributes four important data and their sum data into different channels. For example, when each code data of four ADRC blocks of an upper-left cornered macro block in Fig. 4 is recorded in CH1, CH2, CH3, and CH4, respectively, the sum data DRΣ and MINΣ, which are the sum of the important data of these ADRC blocks, are recorded in the first channel (CH6) of the following macro block (right hand sided macro block). In this way, the four important data and the sum data of them are recorded in different channels. Therefore, even if the whole data of the first channel cannot be reproduced due to a head clog, for example, the important data of the first channel can be corrected as follows. DR1 = DRΣ - DR2 - DR3 - DR4 MIN1 = MINΣ - MIN2 - MIN3 - MIN4 When important data of each block is recorded twice, as in prior art, additional 16 bits are necessary per one ADRC block. On the other hand, according to the present invention, since additional 20 bits are necessary per one macro block, only additional 5 bits are necessary one ADRC block and perfect correction can be achieved. Referring to Fig. 5, a reproducing circuit which corresponds to the recording circuit as shown in Fig. 1 will be described. Each channel of reproduced data reproduced from magnetic tape T by six rotary heads H1-H6 is supplied through a reproducing amplifier 14 to a head de-interleave circuit 15. Head de-interleave circuit 15 de-interleaves the reproduced data which had been interleaved by head interleave circuit 12 at the recording side. Head de-interleave circuit 15 supplies its output data to a channel decoder 16 which channel-decodes the supplied data. Channel decoder 16 supplies its output data to an error correction circuit 17 which decodes the product code. The output data of error correction circuit 17 includes, in addition to the reproduced data, an error flag to show whether an error exists after the error correction. Important data DR and MIN included in the output data of error correction circuit 17 are corrected by the above algorithm. Dynamic range DR of a macro block is supplied to a separation circuit 18. Separation circuit 18 separates the sum data DRΣ and DRi. A latch 19 latches the sum data DRΣ and the error flag and a memory 20 stores DRi and the error flag. Latch 19 supplies the sum data DRΣ through a gate circuit 21 to an operating circuit 25. Latch 19 also supplies the error flag to a detecting circuit 22 whose output is supplied to gate circuit 21 and operating circuit 25. Memory 20 supplies DRi and the error flag to a gate circuit 23 and a detecting circuit 24. Gate circuit 23 is controlled by a detecting signal from detecting circuit 24. Outputs of gate circuit 23 and detecting circuit 24 are supplied to operating circuit 25. The same circuit construction as the above-explained one for the error correction of dynamic range DR is provided for the error correction of minimum value MIN. Circuit blocks for minimum value MIN will have reference numerals which are made up by adding ten and the reference numerals used for the circuit blocks for dynamic range DR. Explanation thereof will be omitted. Corrected dynamic range from operating circuit 25, corrected minimum value MIN from operating circuit 35 and code data DT from error correction circuit 17 are supplied to a macro block deformatting circuit 26. Macro block deformatting circuit 26 deformats the supplied data into reproduced data of every ADRC block. The reproduced data of each ADRC block are supplied to an ADRC decoder 27 where ADRC decoding process is done. In ADRC decoding where the bit number of quantized code is 4 bits, decoded data Li is generated for every pixel. Decoded data Li is expressed as follows : Li = [(DR / 2 4 ) x xi + MIN + 0.5] = [Δ × xi + MIN + 0.5] Xi is a value of code signal, Δ is a quantizing step and [ ] means a gaussian mark. Calculation inside [ ] mark can be achieved by using a ROM, for example. ADRC decoder 27 has a function of adding minimum value MIN. ADRC decoder 27 supplies its output to a block deformatting circuit 28. Block deformatting circuit 28 changes back the order of data from a block order to a raster-scan order. The reproduced data is obtained at an output terminal 29 of block deformatting circuit 28. If necessary, output terminal 29 may have an error interpolation circuit. The error interpolation circuit interpolates a pixel data having an error with peripheral pixel data. Fig. 6 shows one example of gate circuits 21 and 23 and operating circuit 25. DRi is supplied to an input terminal 41. The detect signal from detecting circuit 24 is supplied to an input terminal 42. The sum data DRΣ is supplied to an input terminal 43. The detect output from detecting circuit 22 is supplied to an input terminal 44. Gate circuit 23 supplies DRi to an accumulating circuit 47 and an arrangement control circuit 48. The accumulated output of accumulating circuit 47 and the output of gate circuit 21 are supplied to a subtracting circuit 49. Subtracting circuit 49 supplies its output to arrangement control circuit 48. Corrected important data (dynamic range DR) is derived at an output terminal 50 of arrangement control circuit 48. As an example case, if DR3 among DR1 - DR4 has an error, as shown in Fig. 7, gate circuit 23 receives the detect signal which becomes high level at the location corresponding to DR3. When a control signal is high level, gate circuit 23 is OFF so that accumulating circuit 47 and arrangement control circuit 48 receive DRi other than DR3. Because it is assumed here that DRΣ has no error, DRΣ will pass through gate circuit 21. Accumulating circuit 47 generates an accumulated output ( DR1 + DR2 + DR4 ). Accordingly, subtracting circuit 49 subtracts the accumulated output from DRΣ1 and generates a corrected DR3 at its output. Arrangement control circuit 48 substitutes DR3 in original DRi with the corrected one and generates it. Regarding minimum value MIN, MIN having an error is corrected by operating circuit 35 in the same manner as explained above. The correction is possible when the sum data has no error and only one of plural important data constituting the sum data has an error. In the above embodiment, one macro block has (2×2) four ADRC blocks. It is possible to change the size of the macro blocks. It is also possible to record the sum data and the plural important data constituting the sum data at separate channels among plural channels so that an error correction ability against a burst error in one channel can be higher. For example, if one macro block comprises sixteen ADRC blocks and six channels of data can be recorded in parallel, sum data of 12-bit is generated as follows: DRΣ = DR1 + DR2 + ------------ + DR16 MINΣ = MIN1 + MIN2 + -------------- + MIN16 DR1 - DR6 and MIN1 - MIN6 are recorded into channels CH1 - CH6, respectively. DR7 - DR12 and MIN7 - MIN12 are recorded into channels CH1 - CH6. DR13 - DR16 are recorded into channels CH1 - CH4 and the sum data is recorded into channel CH5. There is only 1.5 bit increase per ADRC block. In this way, when the size of macro block becomes bigger, important data can be completely corrected with restrained increase of redundancy, when a burst error happens due to a tape damage or like that. As explained above, when the sum data generated by simple adding is recorded, the bit number increases such as from 8-bit to 10-bit. One of methods to avoid this problem is to record the average (8 bits) of the sum data. When the average is used, an error is generated by rounding. In order to avoid the problem, the sum data of plural important data which had been weighted is averaged to form the average. When one macro block comprises four ADRC blocks, the sum data is obtained by the following equation. The sum data of minimum values MIN is obtained in the same way. DRΣ = (DR1 × 2 + DR2 × 1 + DR3 × 1 + DR4 × 1) / 5 Fig. 8 shows an example of circuits to achieve this calculation. DRi is supplied to an input terminal 51. DRi is then supplied to a circuit 52 for multiplying twice and a circuit 53 (merely having a buffer function). Circuits 52 and 53 supply their outputs to two input terminals of a switching circuit 54. Switching circuit 54 is controlled by a control signal supplied from a terminal 55. As shown in Fig. 9, switching circuit 54 selects the output of circuit 52 at the timing of DR1 and selects the output of circuit 53 otherwise. Switching circuit 54 supplies its output to an accumulating circuit 56 and the sum data of weighted DRi is derived at an output terminal 57. Although not shown in Fig. 9, a division circuit for dividing by 5 is connected to the output of operating circuit 56. In forming the average of the weighted sum, an important data which is more important than any other important data would have a bigger weighting factor. In forming four ADRC blocks, for example, if the first ADRC block comprises pixel data in the frame, the second ADRC block comprises the difference data of pixel data between the first and second ADRC blocks and the third and fourth ADRC blocks similarly comprise the difference data, important data DR1 and MIN1 of the first ADRC block comprising pixels having original pixel data are considered more important. When plural sums data of important data are formed, some of important data constituting the sum data may be used to form both the sum data. Figs. 10 and 11 show such an example. As shown in Fig. 11, let us assume two macro blocks adjacent to each other in the vertical direction. If same reference numeral are put to important data generated from each ADRC block, the sum data are formed as follows : DRΣ = DR1 + DR2 + DR3 + DR4 + DR1' DRΣ' = DR1' + DR2' + DR3' + DR4' + DR1 The sum data of minimum values are similarly formed. In this way, when both DR1 and DR2 have errors, they can be corrected if other data have no error. Although the data DR1 and DR1' are both used in both equations, the data DR to be used in such a way may change regularly. Referring to Fig. 10, an example of circuit construction for forming the sum data will be described. ADRC decoder supplies its code output to macro block-formatting circuit 4. Dynamic range DR, minimum value MIN and quantized data DT are generated by circuit 4 for every macro block. Dynamic range DR and minimum value MIN are supplied to sum data generating circuits 60a and 60b, respectively. In mixed sum data generating circuit 60a, as shown in Fig. 11, a timing aligning circuit 65 aligns timings of two macro blocks adjacent to each other in the vertical direction. Timing aligning circuit 65 outputs from one output terminal dynamic range DRs of a macro block comprising ADRC blocks 1-4. Timing aligning circuit 65 outputs from the other output terminal dynamic range DR's of a macro block comprising ADRC blocks 1' - 4'. Timing aligning circuit 65 comprises four line memories. DRs of one macro block are supplied to an adding circuit 66 and a gate circuit 70. DR's of the other macro block are supplied to an adding circuit 69 and a gate circuit 67. Through terminals 68 and 71, control signals are supplied to gate circuits 67 and 70 so that only DR1 passes through gate circuit 70, as shown in Fig. 12. Although not shown in figures, the control signal is supplied to gate circuit 67 so that only DR's pass through gate circuit 67. Accordingly, adding circuit 66 generates a result of addition ( DR1 + DR2 + DR3 + DR4 + DR1' ) and adding circuit 69 generates a result of addition ( DR1' + DR2' + DR3' + DR4' + DR1 ). The output of adding circuit 66 is supplied to a mixing circuit 73 through a delay circuit 72 having a delay of one macro block and is mixed by mixing circuit 73 with an undelayed signal. Similarly, the output of adding circuit 69 is supplied through a delay circuit 74 to a mixing circuit 75 so that mixed sum data is obtained at the timing of the first ADRC block of the next macro block. The output of mixing circuit 73 is supplied to a rearranging circuit 76 and the output of mixing circuit 75 is supplied through delay circuit 77 to rearranging circuit 76. Delay circuit 77 has a delay of two lines. At an output terminal 62 of rearranging circuit 76, an output data composed of important data and their mixed data is generated. Regarding minimum value MIN, mixed sum data generating circuit 60b similar to the above-explained is provided. Minimum value MIN and their mixed sum data are derived from an output terminal 63. Quantized code DT is derived from an output terminal 64 after getting through a delay circuit 61 for timing. By adding plural upper bits of important data to produce sum data, an increase in the number of bits forming the sum data can be restrained without degrading a quality of video. For example, when an macro block has sixteen ADRC blocks, the bit number forming the sum data increases from 8 bits to 12 bits in a case of simple adding. But, if upper 4 bits of sixteen DC components are added, the bit number of the sum data can remain to be 8 bits. If the number of bits selected downward from MSB, accuracy would be lowered, but nearly correct data from can be restored. Figs. 13 and 14 are used to explain for forming the sum data from upper 4 bits. Fig. 13 shows a construction of circuits for dynamic range DR only. Dynamic range DR from macro block formatting circuit 4 is supplied to a gate circuit 81. Gate circuit 81 is controlled by a control signal supplied from an input terminal 82. The output of gate circuit 81 is supplied to an accumulating circuit 83. Fig. 14 shows the control signal from input terminal 82 to control gate circuit 81. Serial bits of DR1, DR2, DR3, DR4, ..... are supplied to gate circuit 81 and the control signal is at high level during the upper 4 bits periods of DRi. Only during the period of the high level, gate circuit 81 is ON so that accumulating circuit 83 generates the sum data of the upper 4 bits of DRi. Not only important data, sum data of pixel data may be formed. Fig. 15 shows a construction of (4 × 4) ADRC block. Reference numerals are put on quantized data DT (4 bits) of respective pixels. The sum data is formed according to the following equation: DTΣ = DT1 + DT2 + DT3 + ........+ DT15 + DT16 Sum data DTΣ of these quantized data is also transmitted. According to this method, DR, MIN, DTΣ and quantized data generated in one ADRC block are transmitted so that one error of quantized data can be corrected. In addition, errors of two quantized data can be interpolated. For example, when DT7' and DT10' have errors, interpolated data is formed by using peripheral pixel data. That is : DT7* = ( DT3 + DT6 + DT8 + DT11) / 4 DT10* = ( DT6 + DT9 + DT11 + DT14) / 4 (Mark * means interpolation ). Ratio of these interpolated data is calculated and the sum data DTΣ is apportioned according to the ratio. In this way, proper interpolation can be archived. According to the above-described embodiments of the present invention, because sum data of plural important data are recorded, redundancy slightly increases due to the recording of the sum data. However, the redundancy is lower than when the same important data is recorded several times.

Claims: A data encoding apparatus for encoding pixel data comprising means (2,3) for encoding blocks of pixels to compress the amount of data, the encoding means (2,3) producing, for each block, encoded pixel data (DT) relating to individual pixels of the block and block data (DR, MIN) relating to all the encoded pixel data of the block and without which the encoded pixel data cannot be correctly decoded characterised by means (6) for producing sum data representing a sum, or respective sums, of block data associated with a plurality of the said blocks, and means (11, 12, 13) for transmitting the, or each, said sum data separately from the said block data of the said plurality of blocks, thereby enabling error correction at the receiving side. Apparatus according to claim 1,wherein the encoding means (2,3) produces a plurality of block data (DR, MIN) for each block, the sum data providing mean (6) produces respective sum data representing the sums of the respective block data associated with the plurality of blocks, and the transmitting means (11, 12, 13) transmits the respective sum data separately from the block data of the said plurality of blocks. Apparatus according to claim 1 or 2, wherein the or each said sum data is a weighted average of the or each respective block data associated with the plurality of blocks. Apparatus according to claim 1, 2 or 3, wherein a said block data is represented by n bits and the corresponding sum data represents the sum of the block data of the said plurality of blocks wherein each block data of the sum is represented by its m most significant bits where m is less than n . Apparatus according to claim 1, 2, 3 or 4, wherein the said blocks are organised by the encoding means into units of b blocks, and the said plurality of blocks comprises b blocks from one unit plus at least one block from another unit. Apparatus according to claim 5, wherein sum data is produced for each of a said plurality of blocks in succession, each plurality comprising the b blocks of one unit and at least one block selected from the b blocks of another unit, the selection changing regularly. Apparatus according to any preceding claim, wherein the transmitting means (11, 12, 13) comprises means for recording the sum data, encoded pixel data and block data on a recording medium. Apparatus according to claim 7, wherein the recording means comprises inter leaving means (12) for distributing the block data of a said plurality of blocks and the corresponding sum data into different recording channels. Apparatus according to any one of claims 1 to 6, wherein the transmitting means transmits the, or each, said sum data in time and space different from that of the corresponding block data. Apparatus according to any one of claims 1 to 6, wherein the transmitting means transmits the, or each, said sum data in a channel different to channels in which the corresponding block data are transmitted. Apparatus according to claim 10, wherein the number of channels is greater than the number of blocks in the said plurality of blocks. Apparatus according to any one of claims 1 to 11, in combination with means (14-17) for receiving the transmitted data, means for detecting an error in the block data associated with a block of a said plurality of blocks, and means responsive to the detection of said error to restore the erroneous block data from the sum data and the other block data of the said plurality of blocks. Apparatus according to any one of claims 1 to 12, further comprising means for forming sum data (DTΣ) representing the sum of the encoded pixel data (DT) of a said block, the transmitting means (11, 12, 13) being for also transmitting the said sum data of the encoded pixel data. Apparatus according to claim 13, when dependent on claim 12, comprising means for detecting an error in encoded pixel data of a block, and error correcting means responsive to a detected error in pixel data for correcting the erroneous encoded pixel data using the sum data representing the sum of the encoded pixel data of the block and the other encoded pixel data of the block. Apparatus according to claim 14, wherein the error correcting means is responsive to the detection of a plurality of erroneous encoded pixel data of a block to produce, for each erroneous encoded pixel data, a value interpolated from adjacent pixel data of the block, and to correct the erroneous pixel data in dependence upon the sum data representing the sum of the encoded pixel data of the block and the interpolated values.

Inventors: KONDO TETSUJIRO, KONDO, TETSUJIRO, KONDO, TETSUJIRO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H04N7
IPC codes: H04N7, H04N5