Solid state image pickup apparatus

Abstract: A solid state image pickup apparatus is constructed by arranging a plurality of photoelectric converting pixels each for accumulating charges produced by receiving a light energy and for amplifying the charges and generating. Timings to start and finish the accumulation of the charges for each pixel in a photoelectric converting section are set to be equal to or slightly deviated from the accumulation timing. For this purpose, the apparatus has: a signal accumulating section in which signal accumulating cells having transistors (21) are arranged; transfer sections 26, 29, and 31 each for transferring the signals of the photoelectric converting pixels as voltages to the control electrodes of the signal accumulating cells; and a reading circuit for outputting the signal from one of the main electrodes of the transistors of the signal accumulating cells.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a solid state image pickup apparatus and, more particularly, to a solid state image pickup apparatus using a photoelectric converting device of the amplifying type for amplifying photoelectrically converted siqnal charges. Related Background Art In recent years, in a solid state image pickup apparatus or the like, examination has been made with respect to a photoelectric converting device of the amplifying type for amplifying photoelectrically converted signal charges. As one of such photoelectric converting device of the amplifying type, there is a solid state image pickup apparatus using a photoelectric converting device (for example, bipolar transistor, MOS transistor, JFET (Junction Field Effect Transistor), STT (Static Induction Transistor), etc.) which is constructed in a manner such that a unit pixel has a construction similar to that of a transistor and the charges produced by the light irradiation are accumulated in a control electrode region, and an amplified signal is output from a main electrode region. Fig. 1 is a circuit constructional diagram of a photoelectric converting section and a signal reading section of a solid state image pickup apparatus using a bipolar type sensor comprising, for example, a bipolar transistor as a photoelectric converting device. In Fig. 1, reference numeral 1 denotes a bipolar type sensor (equivalently, bipolar transistor); 2 a capacitor to control a base potential of the bipolar type sensor 1; and 3 a PMOS transistor to reset the base potential of the bipolar type sensor 1. One unit pixel is constructed by the bipolar type sensor 1, capacitor 2, PMOS transistor 3. Reference numeral 4 denotes a vertical output line; 5 a horizontal drive line; 6 an MOS transistor to reset the vertical output line 4; 7 a capacitor to accumulate an output signal from the pixel; 8 an MOS transistor to transfer an output from the pixel to the capacitor 7; 9 a horizontal output line; 10 an MOS transistor to transfer an output of the capacitor 7 to the horizontal output line 9; 11 an MOS transistor for buffering which is selected by a vertical shift register and is used to apply a drive pulse to the pixel; 12 a preamplifier to generate a sensor output; 13 an input terminal to apply a pulse to a gate of the MOS transistor 6; 14 an input terminal to apply a pulse to a gate of the MOS transistor 8; 15 an input terminal to apply a drive pulse to the MOS transistor 11; and 16 an output terminal. Fig. 2 is a timing chart for explaining the operations of a photoconductive converting section and a signal reading section. As shown in Fig. 2, for example, while a pulse  VC which is supplied to the input terminal 13 is maintained at the high level at time t 1 , a pulse  T which is supplied to the input terminal 14 is set to the high level and the MOS transistor 8 is turned on. In this state, since the vertical output line 4 is connected to the ground GND through the MOS transistor 6, the capacitor 7 is also reset to the GND. Subsequently, the pulse  VC is set to the low level at time t 2 , the MOS transistor 6 is turned off, and the vertical output line 4 and capacitor 7 are set into a floating state. In this state, when a pulse  R which is supplied to the input terminal 15 is set to the high level at t 3 , a base potential of the bipolar type sensor 1 is raised through the capacitor 2. A signal is output from the emitter at a potential corresponding to the base potential in the base region, in which the light carriers have been accumulated. The pulses  T ,  R , and  VC are respectively set to the low level, middle level, and high level at time t 4 . Then the pulse  R is set to the low level at time t 5 , the PMOS transistor 3 is turned on and the base of the bipolar type sensor 1 is connected to ground. After that, when the level of the pulse  R is changed to the high level through the middle level for a time interval from t 6 to t 7 , a portion between the base and emitter of the sensor 1 is set into a forward biasing state and the base potential decreases owing to a base current. When the level of the pulse  R is changed from the high level to the middle level at time t 8 , the base potential drops by the capacitive coupling through the capacitor 2. The junction between the emitter and base is reversely biased and the accumulation of the light carriers is started. As described above, a series of operations, such as a reading operation, a resetting operation, and an operation of starting the accumulation, are sequentially executed for every line. According to such a solid state image pickup apparatus, the light carriers accumulated in the base of the bipolar type sensor constructing the pixels can be amplified and read out. Thus, there is an advantage such that the output signal is hardly influenced by noises of the reading circuit system. It is also possible to construct the apparatus in a manner such that the amplifying type photoelectric converting device such as a foregoing bipolar type sensor or the like is used and all of the pixels are reset together. The apparatus can be also applied to a still video or the like. Fig. 3 is a circuit constructional diagram of the photoelectric converting section and signal reading section of the solid state image pickup apparatus in case of using the foregoing bipolar type sensor. In Fig. 3, the same component elements as those shown in the solid state image pickup apparatus in Fig. 1 are designated by the same reference numerals and only the component elements with different constructions will be explained hereinbelow. In Fig. 3, reference numeral 50 denotes an MOS transistor to reset the horizontal output line 9; 33 an emitter follower circuit to set a source potential of the PMOS transistor in order to execute the clamping operation of a pixel S (comprising the bipolar type sensor 1, capacitor 2, and PMOS transistor 3); 35 a PMOS transistor to set a base potential of the emitter follower circuit 33; and 34 a terminal to apply a pulse to a gate of the PMOS transistor 34. The operation of the above solid state image pickup apparatus will now be described hereinbelow. First, the pulse at the low level is applied to a terminal 35 and the PMOS transistor 34 is turned on, thereby setting an output of the emitter follower circuit 33 to a positive potential. The output of the emitter follower circuit 33 is connected to a source of the PMOS transistor 3 of the pixel S. When the source potential of the PMOS transistor 3 rises so as to be sufficiently higher than a gate potential of the PMOS transistor 3, and the PMOS transistor 3 is sufficiently set into the ON state as much as possible, holes are implanted into the base of the bipolar type sensor 1 of the pixel through the PMOS transistor 3. Subsequently, by applying the pulse at the high level to the terminal 35, the PMOS transistor 34 is turned off and an output of the emitter follower circuit 33 is set into the grounding potential GND. In this instance, by applying the pulse at the high level to the terminal 13, the MOS transistor 6 is turned on and the vertical output line 4 is set to GND (the processes until now are called a first reset). In this state, the vertical shift register is subsequently driven and a pixel reset pulse is applied to the terminal 15, thereby sequentially resetting to pixels every line. The bases of the bipolar type sensors 1 of all of the pixels are set into a predetermined potential and are reversely biased (the processes until now are called a second reset). After the accumulating operation of the light carriers was executed, the pulse at the low level is applied to the terminal 13, thereby turning off the MOS transistor 6. A read pulse is applied from the terminal 15 to every line selected by the output of the vertical shift register. The signal output is accumulated into the capacitor 7 through the MOS transistor 8. The signal output accumulated in the capacitor 7 is transferred to the horizontal output line 9 through the transferring MOS transistor 10 selected by the horizontal shift register and is outputted from the output terminal 16 via the preamplifier 12. In the solid state image pickup apparatus using the amplifying type photoelectric converting device as mentioned above, the operations such as reading operation, resetting operation, and charge accumulating operation are sequentially executed every horizontal line by the vertical shift register. Therefore, when it takes a time to perform the resetting operation and reading operation, a scanning time by the vertical shift register becomes slow. Consequently, there is a large deviation between the start and end times of the accumulation of the charges of one horizontal line and the start and end times of the accumulation of the charges of the next horizontal line. In the reading operation, it takes a predetermined time for the operations to transfer the signal to the capacitor 7 and to read out the accumulated charges therefrom through the preamplifier 12. Therefore, a predetermined time is also required for the scanning operation by the vertical shift register. Accordingly, in the case where a light source is to be turned on for only about one field period of time and the field image information at that time is obtained, the overlap period of time between the accumulating period of each line and the light on period differs for every line. There is, consequently, a problem such that even if the light intensity from the turned-on light incident on the sensor is equal for all of the lines, the amount of signal charges generated in response to the turned-on light differs for every line. US-A-5146339 and JP-A-3-162183 disclose an arrangement in which bipolar photosensitive transistors are arranged in a plurality of rows, and the outputs from the emitters of the photosensitive transistors are provided to column lines. Each column line has a signal storage capacitor, so that during a reading operation the photosensitive transistors of a selected row are read onto the respective column lines and the signals on the column lines are stored in the respective capacitors. Each column line is terminated at the base of a respective Darlington double transistor, and the storage capacitor for each column line is connected to the base of the respective Darlington double transistor. In a horizontal scan operation the signals stored in the storage capacitors are read out in turn to a horizontal output line, via the respective Darlington double transistors. Because of the high current amplification factor of the Darlington double transistors, it is not necessary to reset the horizontal output line, thereby increasing the speed of operation of the device. After the horizontal scan is completed, the bipolar photosensitive transistors of the selected row are reset, and then the accumulation of photo-induced charges is started. Then the next row of photosensitive bipolar transistors is selected to be read to the column lines and the storage capacitors. SUMMARY OF THE INVENTION According to the present invention there is provided photoelectric conversion apparatus as set out in claim 1. Optional features are set out in the remaining claims. In an embodiment there is provided a solid state image pickup apparatus which is constructed by arranging a plurality of photoelectric converting pixels for accumulating the charges which are produced by receiving light energy and for amplifying and outputting the charges, wherein the solid state image pickup apparatus comprises: a signal accumulating section in which signal accumulating cells having transistors are arranged; transfer means for transferring signals of the photoelectric converting pixels to control electrodes of the signal accumulating cells as voltages; and reading means for outputting the signal from one of the main electrodes of the transistors of the signal accumulating cells. The transfer means optionally comprises: means for outputting the signal of the photoelectric converting pixel to one of the main electrodes of the transistor of a signal accumulating cell as a voltage value at a low impedance; and means for setting the control electrode of the transistor into a floating state of a potential higher than that of the main electrode, wherein the potential of the control electrode is set to a potential that is higher than the potential of the main electrode by only a predetermined voltage by a current flowing in the control electrode, thereby enabling the signal to be transferred to the control electrode of the signal accumulating cell. As many transistors as the number of cells of the photoelectric converting section are provided as signal accumulating sections in the other regions different from the photoelectric converting section, and the signals of the cells of the photoelectric converting sections are transferred into the control voltage regions of the cells of the signal accumulating section and can be accumulated and held therein or can be read out therefrom. According to such a construction, the operations such as to transfer the signal into the accumulating capacitor and to read out the signal via the preamplifier can be executed independently of the operation of the photoelectric converting section. The timings to start and finish the accumulation of the charges of each pixel in the photoelectric converting section can be set to timings which are equal to or are only slightly deviated from each other. Further, it is also possible to provide a function for separating the signal to be obtained from a background output and for taking out such a signal. Embodiments of the present invention will be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit constructional diagram of a photoelectric converting section and a signal reading section of a solid state image pickup apparatus using a bipolar type sensor; Fig. 2 is a timing chart for explaining the operations of the photoelectric converting section and signal reading section; Fig. 3 is a circuit constructional diagram of a photoelectric converting section and a signal reading section of a solid state image pickup apparatus using a bipolar type sensor; Fig. 4 is a circuit constructional diagram of a photoelectric converting section and a signal reading section according to the first embodiment of a solid state image pickup apparatus of the invention; Fig. 5 is a timing chart for pulses which are supplied to pulse terminals in order to execute the operation of the solid state image pickup apparatus shown in Fig. 4; Fig. 6 is a circuit constructional diagram of a photoelectric converting section and a signal reading section of a part of the second embodiment of the solid state image pickup apparatus of the invention; Fig. 7 is a diagram showing the operation order of the solid state image pickup apparatus shown in Fig. 6; and Fig. 8 is a diagram showing the operation order of the third embodiment of the solid state image pickup apparatus of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail hereinbelow with reference to the drawings. In the solid state image pickup apparatus embodying the invention, it is sufficient to use a photoelectric converting device of the amplifying type and the device is not particularly limited to a bipolar type sensor. [Embodiment 1] Fig. 4 is a circuit constructional diagram of a photoelectric converting section and a signal reading section of a solid state image pickup apparatus embodying the invention. In the embodiment, a construction of only four pixels has been shown for simplicity of explanation. However, the invention is not obviously limited to the number of pixels. In Fig. 4, the same component elements as those shown in the solid state image pickup apparatus of Fig. 1 are designated by the same reference numerals and their detailed descriptions are omitted here. In the diagram, reference numerals 21, 22, and 23 denote a bipolar transistor, a capacitor, and a PMOS transistor. One cell is formed by the same construction as that of the bipolar type sensor 1, capacitor 2, and PMOS transistor 3. Reference numeral 24 denotes a vertical output line connected to an emitter of the bipolar transistor 21; 25 a horizontal drive line to control a base potential of the bipolar transistor 21 through the capacitor 22; 17 a buffering MOS transistor which is selected by a vertical shift register II and is used to apply a drive pulse to the cell; 18 an input terminal to apply a drive pulse  W to the MOS transistor 17; 26 an MOS transistor to control a potential of the vertical output line 4; 27 an input terminal to apply a pulse to a gate of the MOS transistor 26; 28 a power source terminal to supply a potential at a positive level higher than a ground potential GND to a source of the MOS transistor 26; 29 a bipolar transistor whose base is connected to the vertical output line 4 and whose emitter is connected to the vertical output line 24; 31 an MOS transistor whose source is connected to the ground GND and whose drain is connected to the vertical output line 24; 32 a terminal to apply a pulse to a gate of the MOS transistor 31; 33 the emitter follower circuit whose emitter output is commonly connected to drains of the PMOS transistors 3 and 23 arranged on the left and right sides in a photoelectric converting cell and an accumulating cell; 34 the PMOS transistor whose source is connected to a base of the emitter follower circuit 33; 35 the terminal to apply a pulse to a gate of the PMOS transistor 34; and 36 a power source terminal to supply a positive potential to a base of the emitter follower circuit 33 through the PMOS transistor 34. Fig. 5 shows a timing chart for pulses which are supplied to the pulse terminals in order to execute the operation of the solid state image pickup apparatus shown in Fig. 4. First, the pulse which is applied to the terminal 35 is set to the low level and the potential of the base of the emitter follower circuit 33 is fixed to the positive potential of the power source terminal 36. Thus, peripheral source sections of the PMOS transistors 3 and 23 constructing the pixels at the periphery of the photoelectric converting region and the periphery of the accumulating region are set to a positive potential. Thus, all of the PMOS transistors 3 and 23 are made conductive and all of the bases of the bipolar type sensor 1 and bipolar transistor 21 are set to the same positive potential as that of the output of the emitter follower circuit 33. Subsequently, since the pulses which are supplied to the terminals 13 and 32 are set to the high level, the potentials of all of the emitters connected to the vertical output lines 4 and 24 are grounded. The base potentials of the sensor 1 and bipolar transistor 21 is reduced to about V BE , namely, about 0.6 V. The processes up to now are called a clamping operation. Subsequently, the pulse which is supplied to the terminal 27 is set to the high (H) level and the vertical output line 4 is fixed to the power source potential of the power source terminal 28. In this state, the pulse which is supplied to the terminal 15 is set to the H level. When the horizontal drive line 5 selected by a vertical shift register I is set to the H level, the base potential of the sensor 1 of the selected line is raised in the positive direction by the capacitive coupling of the capacitor 2. However, since the emitter potential is fixed to the power source potential of the power source terminal 28, the base potential decreases to a certain predetermined level by the base current flowing in the circuit. When the pulse which is supplied to the terminal 15 is set to the low level, the base potential decreases to a value lower than the emitter potential by the capacitive coupling through the capacitor 2 and the accumulation of the light carriers is started. The processes up to now are called a resetting operation. The resetting operation, however, is sequentially executed for the row selected by the vertical shift register I. At the time of the completion of the resetting operation, the accumulating operation is started and the signal is accumulated into the base of the bipolar type sensor 1. After that, the transferring operation, such that the base potential of the sensor 1 is written into the base potential of the bipolar transistor 21 is performed in the following manner. First, the vertical output line 4 is set to the power source potential of the power source terminal 28 through the MOS transistor 26. After that, the vertical output line 4 is set into a floating state. In this state, by setting the pulses which are supplied to the terminals 15, 18, and 32 to the H level, the signal of the sensor cell is read out to the vertical output line 4. Thus, the vertical output line 24 acts as an output line of the emitter follower circuit comprising the bipolar transistor 29 and MOS transistor 31, and is set to the potential corresponding to the output potential of the sensor 1. The output impedance of the emitter follower circuit is small, and when the pulse which is supplied to the terminal 18 is set to the H level, the base potential of the bipolar transistor 21 is raised. Therefore a base current flows and the resetting operation of the bipolar transistor 21 is executed. However, the base potential upon completion of the resetting operation is set to the level which is obtained by adding a certain predetermined potential to the potential of the vertical output line 24 corresponding the output voltage of the bipolar type sensor). Consequently, the signal potential of the photoelectric converting cell of the row selected by the vertical shift register I is transferred to be stored as the base potential of the accumulating cell of the row selected by the vertical shift register II. The above transferring operation is sequentially executed with respect to each row. After that, the reading operation from the accumulating cell is performed. The terminal 27 is set to the H level and the base potential of the bipolar transistor 29 is fixed to the power source potential of the power source terminal 28. The pulse is supplied to the terminal 32 and the vertical output line 24 is set to the predetermined potential. After that, the vertical output line 24 is set into a floating state. The terminal 18 is set to the H level. The base potential of the bipolar transistor 21 of the row selected by a vertical shift register II is increased by the capacitive coupling through the capacitor 22. A portion between the emitter and base of the bipolar transistor 21 is forwardly biased. A potential corresponding to the base potential of the bipolar transistor 21 is outputted to the vertical output line 24. The read-out output is outputted from the preamplifier 12 through the horizontal output line 9 by scanning the horizontal shift register and by sequentially turning on the transfer MOS transistors 10. [Embodiment 2] Fig. 6 is a circuit constructional diagram of a photoelectric converting section and a signal reading section of a part of a second embodiment of the solid-state image pickup apparatus of the invention. In Fig. 6, the same component elements as those shown in the solid state image pickup apparatus of Fig. 4 are designated by the same reference numerals and their detailed descriptions are omitted here. In the diagram, reference numeral 37 denotes an emitter follower circuit to give a source potential of the PMOS transistor 23 in the signal accumulating section; 38 a PMOS transistor connected to a base of the emitter follower circuit 37; 39 a terminal to supply a pulse to a gate of the PMOS transistor 38; 40-1 a capacitor to hold the output of the cell in the signal accumulating section; 40-2 a capacitor to hold an output of the cell in the photosensitive section; 41-1 an MOS transistor to transfer the output of the bipolar transistor 21 from the vertical output line 24 to the capacitor 40-1; 41-2 an MOS transistor to transfer the output of the bipolar type sensor 1 from the vertical output line 24 to the capacitor 40-2; and 10-1 and 10-2 MOS transistors for transferring potentials of the capacitors 40-1 and 40-2 to the horizontal output line 9. Fig. 7 is a diagram showing the operation order of the solid-state image pickup apparatus shown in Fig. 6. When comparing Fig. 7 with the first embodiment shown in Fig. 5, the operations up to the clamping operation, resetting operation, accumulating operation, and transferring operation are substantially the same. Since the emitter follower circuit to execute the clamping operation for the light receiving section differs from that for the signal accumulating section, the MOS transistors 34 and 38 are simultaneously turned on in the first clamping operation. After completion of the transferring operation, the clamping and resetting operations are executed for the light receiving section. With respect to the reading operation, when the signal is read out from the cell of the signal accumulating section as shown in Fig. 5 the output voltage is accumulated in the capacitor 40-1 through the MOS transistor 41-1. Subsequently, the reading operation is executed from the cell in the light receiving section corresponding to the cell in the signal accumulating section from which the signal has been read, while the cell in the light receiving section is in the reset state. The output of the bipolar transistor 29 which has received the output potential of the vertical output line 4 is accumulated into the capacitor 40-2 through the MOS transistor 41-2. Subsequently, the potentials of the capacitors 40-1 and 40-2 are outputted through the horizontal output line 9 from the preamplifier 12 by a horizontal shift register. The output of the cell in the light receiving section after reset is an offset output corresponding to the offset in the signal transferred to the cell in the signal accumulating section. Therefore an output that is obtained by subtracting the output of the capacitor 40-2 from the output of the capacitor 40-1 becomes a signal voltage without an offset variation of the bipolar type sensor 1 and bipolar transistor 29 in the light receiving section, namely, a signal voltage of a good S/N ratio. [Embodiment 3] Fig. 8 is an operation timing chart showing the third embodiment of the solid state image pickup apparatus of the invention. In the third embodiment, the sensor system which is used is substantially the same as that in the second embodiment. In the operation, however, the optical signal accumulating operation of the cell in the light receiving section is executed again after the transferring operation and before the reading operation. In the first optical signal accumulating operation, the light source such as an LED or the like is turned on. In the later optical signal accumulating operation, however, the LED is OFF. Therefore the subtraction output, which is derived after completion of the reading operation, comprises only the image formed using light emitted from the LED and reflected to the solid state image pickup, because not only the offset variation of the bipolar type sensor of the light receiving section but also the output of a background object were subtracted. As for the base of the sensor 1 of the cell of a light receiving section, in order to increase the signal output voltage to the optical signal charges, a higher sensitivity is obtained if a capacitance the capacitor connected to the base is as small as possible. As for the cell in the signal accumulating section, since the signal voltage is transferred, a larger amount of signal charges can be accumulated if the capacitance of the capacitor connected to the base is as large as possible. Therefore, the sensor system in which the capacitance of the capacitor 22 is set to be larger than that of the capacitor 2 provides a higher S/N ratio. However, when the capacitance of the capacitor 22 is increased, the signal transferring speed to the bipolar transistor 21 becomes slow. Therefore, by setting h FE of the bipolar transistor 21 to be higher than h FE of the bipolar type sensor 1, a sensor of a high S/N ratio and a high transfer speed is realized in the embodiments 1, 2, and 3 of the invention. As will be appreciated by those skilled in the art, various other arrangements are possible as variations or modifications of the illustrated embodiments. For example, the capacitor 2, is not essential (and in the embodiments of Figure 4, capacitor 22 is not essential) in an arrangement in which each transistor 1,21 has a separate emitter line. In this arrangement the base and emitter of the photosensitive transistor 1 are not reverse biassed during accumulation but instead they both float and the emitter potential rises with the base potential during accumulation. Similarly, after transfer of the signal to transistor 21 in Figure 4, its emitter is allowed to float at the signal potential as determined by emitter follower action by the potential transferred to the base. Other types of transistor, such as SITs or JFETs may by used instead of bipolar transistors. As can be seen, the illustrated embodiments embody the general concepts set out in the claims.

Claims: Photoelectric conversion apparatus comprising: a plurality of lines of photoelectric conversion transistors (1) each of which stores charge carriers in a control region in response to incident radiation and provides an output at a main electrode region in accordance with the quantity of charge carriers stored in the control region; and a plurality of further transistors (21) each coupled to receive a signal in accordance with the output of the main electrode region of a said photoelectric transistor (1) and to store the signal as a quantity of charge carriers in the control region of the further transistor (21), characterised in that there are as many of said further transistors (21) as there are of said photoelectric conversion transistors (1). Apparatus according to claim 1 in which each further transistor (21) is coupled to receive the said signal on a main electrode region thereof, and the apparatus comprises control means arranged to forward bias the control region of the further transistor (21) relative to its said main electrode region while the signal is applied to its main electrode region so that the control region adopts a potential in accordance with the signal on the main electrode region, and subsequently to reverse bias the control region thereby to preserve the signal on the control region after the signal is removed from the main electrode region. Apparatus according to claim 2 in which the control region of the further transistor (21) is capacitively coupled to a control electrode, and the control means forward and reverse biasses the control region by varying the potential applied to the control electrode. Apparatus according to claim 2 or claim 3 in which a plurality of coupling bipolar transistors (29) are connected as emitter followers to receive the said outputs from respective said photoelectric conversion transistors (1) at their bases and output the said signals to respective said further transistors (21) from their emitters. Apparatus according to any one of claims 2 to 4 in which the first main electrode region of each said further transistor (21) is connected to a first capacitor (40-1) through a first MOS transistor (41-1) and is connected to a second capacitor (40-2) through a second MOS transistor (41-2), whereby a signal output from the further transistor (21) can be stored on the first capacitor (40-1) and a signal in accordance with the output from the corresponding photoelectric conversion transistor (1) can be stored on the second capacitor (40-2). Apparatus according to claim 5 in which the control means is arranged (i) to reset the photoelectric conversion transistor (1) after a signal in accordance with its output has been stored in the control region of the further transistor (21), and (ii) to control the photoelectric conversion transistor (1) and the further transistor (21) in a reading operation to read a signal from the further transistor (21) and store it on the first capacitor (40-1) and to generate an output from the photoelectric conversion transistor (1) and store a signal in accordance therewith on the second capacitor (40-2); the control means being arranged to prevent accumulation of charge carriers in the control region of the photoelectric conversion transistor (1) between the time it is reset and the time an output is generated from it during the reading operation. Apparatus according to claim 5 in which the control means is arranged (i) to reset the photoelectric conversion transistor (1) after a signal in accordance with its output has been stored in the control region of the further transistor (21), and (ii) to control the photoelectric conversion transistor (1) and the further transistor (21) in a reading operation to read a signal from the further transistor (21) and store it on the first capacitor (40-1) and to generate an output from the photoelectric conversion transistor (1) and store a signal in accordance therewith on the second capacitor (40-2); the control means being arranged to permit accumulation of charge carriers in the control region of the photoelectric conversion transistor (1) between the time it is reset and the time an output is generated from it during the reading operation. Apparatus according to any one of the preceding claims in which the said further transistors (21) are bipolar transistors. Apparatus according to claim 8 in which the photoelectric conversion transistors (1) are bipolar transistors.

Inventors: SHINOHARA MAHITO, SHINOHARA, MAHITO, SHINOHARA, MAHITO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: H04N3
IPC codes: H01L27, H04N5, H04N3