Display control apparatus

Abstract: The invention intends to provide a display control apparatus which can perform the flickerless display at a high precision without changing a construction of the electrodes or the like of a display apparatus even when a display speed in the high precision display of a liquid crystal display apparatus is insufficient for the flickerless display in the non-interlace drawing. The display control aparatus 50 has a VRAM and a partial rewrite display control section. Since a WS (host computer) 1 prevents a flicker of the display in the animation image display, for an object which is drawn at a high speed, when image data stored in the VRAM is partially rewritten by the non-interlace, the partial rewrite display control section adds data indicative of the display position of the portion rewritten by the WS 1 to the image data and sync signal of such a rewritten portion and, after that, supplies the image data to a liquid crystal display apparatus 3 at the timing synchronized with the display to the CRT.

Description: The present invention relates to a display control apparatus for a liquid crystal display apparatus. Hitherto, a cold cathode ray tube display apparatus (hereinafter, abbreviated to "CRT") has generally been used as a display apparatus which is applied to a personal computer (hereinafter, abbreviated to "PC") or a work station (hereinafter, abbreviated to "WS"). To improve the understanding by the sense of sight on the basis of the human engineering, the graphic function such as a window function or the like is expanded. A high resolution and a large display screen are needed to realize such an expanded graphic function. On the other hand, in recent years, a liquid crystal display apparatus (hereinafter, also abbreviated to "LCD") having a TN (Twisted Nematic) or STN (Super Twisted Nematic) structure or the like has been used in a lap-top type PC or the like due to predominance of light weight and thin size according to its construction. As for the LCD having such a TN or STN structure or the like, in the case where the number of scan lines is increased to realize a high resolution, a liquid crystal material having sharp electro/optical characteristics is needed to assure a margin of a display contrast. A ferroelectric liquid crystal having bistability is known as a liquid crystal material of such an LCD. In case of the ferroelectric liquid crystal (FLC) which is known at present, when an operation temperature is low, a flickering occurs due to its temperature characteristic because the FLC doesn't have enough high display speed in a high precision display mode. To prevent the flicking, a method of drawing by a high-order interlace (hereinafter, referred to as "multi-interlace") is known. According to the multi-interlace drawing, when an animation image is displayed, a flicker occurs in display modes such as pointing device, pop-up menu, scroll, and the like and a display quality is deteriorated. Therefore, to prevent such flicker of the display, a method of partially rewriting a picture plane by a non-interlace for an object which is drawn at a high speed is known. The above partial writing method, however, is realized by using special hardware and software which are used only for the LCD. Therefore, hitherto, a display control apparatus for the LCD is installed on a mother board or an expansion slot of a host computer and is directly coupled to an address bus, a data bus, and a control signal line of a central processing unit (hereinafter, abbreviated to "CPU") of the host computer and needs a special software driver which is used only for the LCD. As mentioned above, the display control apparatus for the conventional LCD has a problem such that it needs the special software driver. An example of such a display apparatus and display control apparatus may be found in document EP-A-0 318 050. The present invention, therefore, is made in consideration of the above problems and it is an object of the invention is to provide a display control apparatus in which even in the case where a display speed in the high precision display mode of a liquid crystal display apparatus is insufficient for a flickerless display in the non-interlace drawing, the flickerless display can be executed at a high precision without changing a construction of electrodes or the like of the display apparatus. To accomplish the above object, according to the present invention, there is provided a display control apparatus as defined in claim 1. Moreover, this object is achieved by a display control method as set out in claim 7. Advantageous further developments of the invention are set out in the dependent claims. With the present invention in order to prevent the flicker of the display in the animation image display, when the host computer partially rewrites the image data stored in the video memory by the non-interlace method for an object to be drawn at a high speed, the partial rewrite display control section adds the data indicative of the display position of the rewritten portion to the image data and sync signal of the portion rewritten by the host computer and, after that, supplies the resultant image data to the liquid crystal display apparatus at a timing synchronized with the display to the cold cathode ray tube display apparatus. Due to this, even in the case where a display speed in the high precision display mode of the LCD is insufficient for the flickerless display in the non-interlace drawing, the flickerless display can be executed at a high precision without changing a construction of electrodes or the like of the display apparatus. According to the invention, there is provided a display control apparatus which supplies data indicative of the display position, image data, and sync signal to the LCD for a drawing period of time and a vertical blanking period of time of an effective display region of the cold CRT. With the above construction, the data indicative of the display position of the rewritten portion, image data, and sync signal can be supplied to the LCD for the drawing period of time and vertical blanking period of time of the effective display region of the cold CRT, so that the image data can be smoothly drawn by the LCD. Fig. 1 is a constructional diagram of a display system showing an application example of a display control apparatus according to an embodiment of the present invention; Fig. 2 is a schematic constructional diagram of the display control apparatus of the embodiment of the invention; Fig. 3 is a schematic constructional diagram of the display control apparatus of the embodiment of the invention; Fig. 4 is a constructional diagram of a liquid crystal display apparatus; Fig. 5 is a diagram showing a read timing of partial rewrite data in a CRT display period of time; Fig. 6 is a diagram showing a read timing of partial rewrite data in a CRT non-display period of time; Fig. 7 is a diagram showing an output format of image data in the partial rewriting mode; Fig. 8 is a diagram showing a partial rewrite timing; Fig. 9 is a flowchart showing a flow of control of a partial rewrite display control section; and Fig. 10 is a table from explaining the functions of symbols which are used in the display control apparatus of the embodiment of the invention. An embodiment of the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 1 is a constructional diagram of a display system showing an application example of a display control apparatus 50 according to an embodiment of the present invention. In the display system shown in Fig. 1, the display control apparatus 50 is connected through a bus interface 2 to a work station (hereinafter, abbreviated to "WS") 1 as a host computer. A liquid crystal display apparatus (also referred to as an LCD hereinafter) 3 is connected to the display control apparatus 50. The WS 1 has an expansion slot and supplies address information, image data, and control signals to the bus interface 2 from a CPU (central processing unit) in the WS 1. The bus interface 2 comprises: a decoder which has conventionally been used as an interface with the WS 1 and a CRTC (GSP) 58 in the display control apparatus 50, which will be explained hereinlater; a data transceiver; and the like. Fig. 4 is a constructional diagram of the LCD 3. (E) in Fig. 4 denotes that it is connected to (E) in Fig. 2, which will be explained hereinbelow. Each symbol shown in the diagram denotes the denomination of a signal line for connecting the display control apparatus 50 and a drive controller 90 (which will be explained hereinlater) of the LCD 3 as shown in Fig. 10. Those signal lines have the functions as shown in Fig. 10. The LCD 3 shown in Fig. 4 comprises: the drive controller 90; a temperature sensor 113; a common driver 110; segment drivers 111 and 112; a power controller 100; and a display 130. The drive controller 90 is constructed so that it can correspond to 1024 x 5120 dots and drives a frame 140, common driver 110, and segment drivers 111 and 112. The drive controller 90 thins out digital image data which is supplied at the same timing as that of the CRT in order to perform the drawing of the multi-interlace on the basis of temperature information from the temperature sensor 113 and, after that, the thinned-out image data is supplied to the common driver 110 and segment drivers 111 and 112. The temperature sensor 113 is attached at a proper position of the display 130 and supplies the temperature information which is very important in the driving of a ferroelectric liquid crystal (hereinafter, also referred to as an "FLC") to the drive controller 90. The display 130 comprises the ferroelectric liquid crystal having bistability and is constructed in the following manner. A ferroelectric liquid crystal having a bistable state is sealed in a space between glass plates having transparent electrodes such as ITO or the like connected to two scan line lead-out electrodes and polarizing plates are arranged in a cross nicol. Pixels are constructed by 1024 x 2560 dots of 1024 scan line electrodes and 2560 information line electrodes. The pixels of the display 130 are driven by an electric field generated by driving waveforms which are supplied to the common driver 110 and segment drivers 111 and 112 and are display by a "light" state or a "dark" state. The power supply controller 100 properly transforms an input power source on the basis of the signal which is set by the drive controller 90 and supplies the transformed voltages to the common driver 110 and segment drivers 111 and 112. The segment drivers 111 and 112 and common driver 110 apply the voltages supplied from the power supply controller 100 to each electrode of the display 130. In the diagram, the display control apparatus 50 is constructed so that it can correspond to 1024 x 5120 dots. When image data is drawn on the display 130 of the LCD 3 by the multi interlace, the display control apparatus 50 supplies a sync signal, a clock signal, display data, an enable signal, and image data to the drive controller 90 of the LCD 3. On the other hand, when image data is partially rewritten, an external sync signal which is integer times as high as CRT1H synchronized with a horizontal sync signal is supplied from the drive controller 90 at a writing speed of the display 130 or less. A scan line address and image data are supplied to the driver controller 90. A construction of the display control apparatus 50 will be further explained with reference to Figs. 2 and 3. Figs. 2 and 3 are constructional diagrams of the display control apparatus 50. In Figs. 2 and 3, reference symbols (A), (B), (C), and (D) denote that they are connected with each other. The display control apparatus 50 shown in Figs. 2 and 3 comprises: a CRT display control section 40 to perform a CRT display control; and a partial rewrite display control section 60 to perform a partial rewrite display control. The CRT display control section 40 comprises: an MPU 57 (processing section) to control each section of the display control apparatus 50 in accordance with a control procedure shown in Fig. 9; a VRAM 51 as a video memory which has a serial register and stores the image data generated from the WS 1 through the bus interface 2; the CRTC 58 to generate a CBLNK singal, an HBLNK signal, an HSYNC signal, and a VSYNC signal; an S/P converter 61 to convert serial data into pixel data; a tri-state 62; a 1/2 frequency divider 64; a serial clock generator 77; and a memory ROM 70 to store a control procedure shown in Fig. 9 which is executed by the MPU 57. The partial rewrite display control section 60 comprises: a partial rewrite circuit 52; an access address detector 53 to discriminate whether the operation to store data into a second register 54b of an SRAM 54 has been finished or not; the SRAM 54 which detects the scan address which has been updated from the WS 1 to the VRAM 51 for a predetermined period of time (refer to Fig. 8) and has a first register 54a and the second register 54b and stores scan address information; a parameter calculator 55 to calculate address information such as block number, start address and the like from the scan address information which has been read out from the second register 54b of the SRAM 54 for a predetermined period of time; an FIFO memory 56 which has a first stacker 56a and a second stacker 56b and functions as an address information memory to store the address information such as block number, start address, and the like; a clock generator 59; and a 1/2 frequency divider 84. The partial rewrite circuit 52 reads out the partial rewrite image data from the VRAM 51 as shown below. The read timing will now be described with reference to Figs. 5 and 6. Fig. 5 is a diagram showing a read timing of the partial rewrite data in a CRT display period of time. Fig. 6 is a diagram showing a read timing of the partial rewrite data in a CRT non-display period of time. There are two kinds of reading operations to read out the partial rewrite image data from the VRAM 51. Either one of the two reading operations is determined on the basis of the operating state of the CRTC 58 when the partial rewrite circuit 52 reads out the partial rewrite image data from the VRAM 51. As shown in Fig. 5, the first operation relates to the reading operation to read out the image data from the VRAM 51 in an effective display period of time in the CRT display, that is, when the vertical blank (VBLNK) signal is set to the high level. In this state, the CRTC 58 controls RAS, CAS, TRQE, WE, and address bus and reads out the image data to refresh the screen from the VRAM 51 when the HBLNK signal is set to the low level. The timing to refresh the screen is shown by parentheses of "ACCESS FROM CRTC TO VRAM" in Fig. 5. After the elapse of time T g after the HBLNK signal had been set to the low level, the read cycle to the serial register of the VRAM 51 starts. In case of the partial rewriting, after the elapse of time T a after completion of the read cycle, the reading operation is again executed to the serial register in the VRAM 51. The VRAM read timing of the partial rewrite circuit 52 is shown by parentheses "ACCESS FROM PARTIAL REWRITE CCT 52 TO VRAM" in Fig. 5. The RAS, CAS, TRQE, WE, and address bus are controlled at timings similar to those for the refreshing operation mentioned above. ADRMPX denotes a timing signal to switch a line connection of the address bus by a row address and a tap point. G1 denotes a signal for pending the operation such that the CRTC 58 executes the refreshing operation of the VRAM 51. By the above control, the partial rewrite data can be read out in place of the image data for the ordinary screen refresh operation of the CRTC 58. As shown in Fig. 6, the second operation is executed for a non-display period of time in the CRT display, namely, when the vertical blank signal is set to the low level. In this state, the CRTC 58 doesn't reads out the image data from the VRAM 51. When the partial rewriting operation is active for such a period of time, after the elapse of time T a after the HBLNK signal had been set to the low level, the read cycle to the serial register in the VRAM 51 starts. The VRAM read timing by the partial rewrite circuit 52 is shown by parentheses "ACCESS FROM PARTIAL REWRITE CCT TO VRAM" in Fig. 6. The timings of the RAS, CAS, TRQE, WE, and address bus are similar to those in the image data reading operation for the partial rewriting operation in the effective display period of time. ADRMPX denotes the timing signal to switch the line connection of the address bus by the row address and tap point. By the above control, in case of the CRT, the image data can be also supplied to the dipslay. 130 for the vertical blanking period of time during which no data is displayed. In the partial rewriting mode, the partial rewrite circuit 52 generates the image data by an output format shown in Fig. 7. That is, the display 130 is constructed by the pixels of 2560 x 1024 dots and the image data is shown by D0 to D2559. Scan addresses A0 to A15 of sixteen bits are added to the image data and, after that, the image data is supplied from the display control apparatus 50 to the drive controller 90 by signal lines PD0 to PD15 having a 16-bit width. Those signals are transmitted synchronously with an FCLK signal. A pulse signal of AH/DL is supplied to the drive controller 90 synchronously with the transmission of the head address data A0 to A15. The transmission timing of the image data of one line is synchronized with the HSYNC signal of the CRT. The operation of the partial rewrite display control section 60 will now be described in accordance with a control flow of Fig. 9 also with reference to a diagram showing the partial rewrite timing of Fig. 8. The access address detector 53 detects the scan address which has been updated from the WS 1 to the VRAM 51 (refer to Fig. 8) and a check is made to see if the operation to store the image data into the second register 54b of the SRAM 54 has been finished or not (step S1). If YES, step S2 follows. If NO, the processing routine advances to step S9, which will be explained hereinlater. A processing in step S2 is executed by the following procedure. First, the SRAM 54 performs a flag access to set "1" into the updating address, so that the access of the same address is convolved and stored. For the high-level period of time of the signal of the 1/2 frequency divider 84, the parameter calculator 55 reads out the scan address information stored in the second register 54b of the SRAM 54. Subsequently, the parameter calculator 55 calculates the block number, start address, end address, line number, and total line number from the scan address information and writes into the second stacker 56b of the FIFO memory 56. In step S2, a check is made to see if the above operation has been completed or not. When a predetermined operation is finished in step S2, the MPU 57 reads out the block number calculated by the parameter calculator 55 from the second stacker 56b in the FIFO memory 56 (S3). The MPU 57 subsequently reads out the block number calculated by the parameter calculator 55 from the first stacker 56a in the FIFO memory 56 (S4). A difference between the numbers of addresses stored in the stackers 56a and 56b can be known by comparing the block numbers in the first and second stackers 56a and 56b which have been read out by the MPU 57 in steps S3 and S4 (S5). If YES in step S5, step S6 is executed in accordance with the following procedure. First, the MPU 57 sets the PH/RL signal line to the high level and instructs the drive controller 90 to write. Subsequently, the drive controller 90 sets a BUSY signal line to the low level at the timing synchronized with the horizontal sync signal at the liquid crystal response speed of the display 130 or less and requests the scan line address information and the image data to the display control apparatus 50. The partial rewrite circuit 52 reads out the partial rewrite image data from the VRAM 51. The above operation is determined by the operating state of the CRTC 58 and differs in dependence on a mode for the effective display period of time in the CRT display, namely, when the vertical blank signal is at the high level and a mode for the non-display period of time, namely, when the vertical blank signal is at the low level. The level of the vertical blank signal is judged from the CBLNK signal which is supplied from the CRTC 58. When the vertical blanking period of time of the CBLNK signal supplied from the CRTC 58 is at the high level, namely, in case of the effective display period of time of the CRT, the CRTC 58 reads out the image data of one line from the VRAM 51 to the serial register in the VRAM 51 for the horizontal blanking period of time for the CRT display. After completion of the above operation, the partial rewrite circuit 52 disables the tri-state 62 and supplies the address information indicative of the partial rewrite data to the VRAM 51, thereby newly reading out the image data to the serial register in the VRAM 51. When the vertical blanking period of time of the CBLNK signal supplied from the CRTC 58 is at the low level, the partial rewrite circuit 52 disables the tri-state 62 for the horizontal non-display period of time on the basis of the HBLNK signal which is supplied from the CRTC 58 and supplies the address information indicative of the partial rewrite data to the VRAM 51, thereby reading out the image data to the serial register in the VRAM 51. The image data read out to the serial register in the VRAM 51 is read out every eight pixels (two bits/pixel) by the serial clock generator 77 by using the scan line address which is supplied from the MPU 57 as a head address. The read image data is supplied to the drive controller 9. By the above operation, the content of the address information detected by the first register 54a in the SRAM 54 is drawn on the display 130. If NO in step S5, step S7 is executed in accordance with the following procedure in a manner similar to step S6 mentioned above except a different point such that the content of the address information detected in the second register 54b in the SRAM 54 is drawn on the display 130 by the above operation. A check is made to see if the contents of all of the address information detected in the registers 54a and 54b in the SRAM 54 have been drawn by the display 130 or not (S8). If NO in step S8, the processing loop in steps S5, S6, and S8 or the processing loop in steps S5, S7, and S8 is repeated until the contents of all of the address information are displayed. After the contents of all of the address information were displayed on the display 130, the processing routine is returned to step S1. If NO in step S1, that is, when the sampling of the data in the second register 54b is not finished yet, a check is made to see if the sampling of the data in the first register 54a has been finished or not (S9). If NO in step S9, the processing routine is returned to step S1. If YES, a processing in step S10 is executed. The processing in step S10 is executed in accordance with a procedure similar to step S6 mentioned above. By the operation in step S10, the content of the address information detected in the second register 54b in the SRAM 54 is drawn on the display 130. A check is made to see if the contents of all of the address information detected in the first register 54a in the SRAM 54 have been drawn on the display 130 or not (S11). If NO in step S11, a processing loop in steps S10 and S11 is repeated until the contents of all of the address information are displayed. After the contents of all of the address information were displayed on the display 130, the processing routine is returned to step S1. A CREF signal is supplied from the drive controller 90 to the MPU 57 as an exceptional processing of the forced refresh. The CREF signal is a signal to forcedly refresh the screen by the multi interlace because in the case where the partial writing operation to the display 130 is continued, the contrast of the scan line which is not accessed rises (S12). When the CREF signal is supplied, the display control apparatus 50 sets the PH/RL signal to the low level and supplies the image data to the drive controller 90 at the display timing of the CRT. The partial rewrite display control is executed as mentioned above. According to the display control apparatus 50 of the embodiment with the above construction, the following effects are obtained. (a) Since the multi interlace drawing is used, the flickerless display can be performed in the high precision display. (b) For a drawing object which moves at a high speed, by using a partial rewriting method of partially rewriting the screen by the non-interlace, a flicker of the display of an animation image by the high-order interlace can be prevented. (c) By using the (video memory) and the screen refresh function which the conventional CRT display control apparatus has without changing and by adding the partial rewriting function, the image data writing operation of the WS (host computer) 1, the refreshing operation of the VRAM 51, and the video data reading-out operation for reading out and rewriting the video data of the CRT are executed by the arbitration of the VRAM 51. Therefore, the timing of the image data which is supplied to the LCD 3 coincides with the display timing of the CRT. The display control apparatus 50 when it is seen from the WS (host computer) 1 side is equivalent to the conventional CRT display control apparatus. Therefore, there is no need to use any special software driver for the LCD 3 and the software driver of the conventional CRD display control apparatus can be used as it is. (d) In case of the conventional CRT display control apparatus, no image data is drawn in the vertical blanking period, namely, in a beam blanking period of time. However, in the vertical blanking period as well, since the image data is read out from the VRAM 51 synchronously with the horizontal blank signal, the image data can be smoothly drawn on the LCD 3. According to the present invention described in detail above, the data indicative of the display position of the rewritten portion is added to the image data and sync signal of the portion which has been rewritten by the host computer by the non-interlace, and after that, the resultant image data is supplied to the LCD at the timing synchronized with the display to the cold CRT. Therefore, even in the case where the display speed in the high precision display of the LCD is insufficient to perform the flickerless display in the non-interlace drawing, the display control apparatus which can perform the flickerless display at a high precision without changing a construction of the electrodes or the like of the display apparatus can be provided. According to the present invention, in addition to the effects disclosed in Claim 1, the data indicative of the display position of the rewritten portion, the image data, and the sync signal can be supplied to the LCD for the drawing period of time of the effective display region of the cold CRT and for the vertical blanking period, so that the image data can be smoothly drawn on the LCD.

Claims: A display control apparatus comprising: memory means (51) for storing image data which is supplied from a host computer (1) to a designated position; monitoring means (53, 54, 54a, 54b) for monitoring said designated position; reading means (52) for reading out the image data from said memory means; characterized by data adding means (55) for adding the data indicative of the position to the image data read out by said reading means when it is determined by the monitoring of said monitoring means that a continuous region has been designated; and display control means (60) for allowing the image data to be displayed by a liquid crystal display apparatus (3; 90, 100, 110, 111, 112, 113, 120, 130, 140), wherein, on the basis of said data indicative of the position, the image data are supplied to said liquid crystal display apparatus at the timing synchronized with the display to a cathode ray tube. An apparatus according to claim 1, characterized by switching means (71) for switching a partial rewriting mode to partially read out the image data which is read out from said reading means and a refreshing mode to sequentially read out the image data; and wherein said data adding means adds the data indicative of the position in the partial rewriting mode. A display control apparatus according to claim 1, characterized in that said display control means (60) displays on the basis of a sync signal for a cathode ray tube apparatus. A display control apparatus according to claim 3, characterized in that said display control means (60) displays the image data for a drawing period of time of an effective display region for a cathode ray tube apparatus and for a blanking period of time of a vertical sync signal. A display control apparatus according to claim 1, characterized in that said liquid cristal display apparatus comprises a ferroelectric liquid cristal. A display control apparatus according to claim 1, characterized in that a parameter calculator (55) for calculating said data indicative of the position is provided. A display control method comprising the steps of: storing (S1) image data which is supplied from a host computer (1) to a designated position in a memory means (51); monitoring (S2, S9) said designated position; reading out (S3, S4) the image data from said memory means; characterized by the further steps of adding (S5) the data indicative of the position to the imaqe data read out when it is determined by the monitoring step that a continuous region has been designated; and controlling (S6, S7, S10) the displaying for allowing the image data to be displayed by a liquid crystal display apparatus, wherein, on the basis of said data indicative of the position, the image data are supplied to said liquid crystal display apparatus at the timing synchronized with the display to a cathode ray tube.

Inventors: YUKI OSAMU, YUKI, OSAMU, Yuki, Osamu, c/o Canon Kabushiki Kaisha
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: G09G3
IPC codes: G09G3, G02F1