DESYNCHRONIZER AND METHOD FOR SUPPRESSING POINTER JITTER IN A DESYNCHRONIZER

Abstract: The invention relates to a method for suppressing pointer phase jitter in a desynchronizer comprising a data buffer means (1); a write address counter (2) controlled by a write clock (CLK1); a read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop (4, 5, 7) for phase-locking the read clock to the write clock. The method according to the invention comprises modulating (61, 64) the pointer phase jitter to a frequency substantially higher than the bandwidth of the phase-locked loop.

Description: Desynchronizer and method for suppressing pointer jitter in a desynchronizer Field of the Invention The invention relates to a method for suppress¬ ing pointer phase jitter in a desynchronizer compris¬ ing a data buffer means; a data buffer write address counter controlled by a write clock; a data buffer read address counter controlled by a read clock; and a phase-locked loop for phase-locking the read clock to the write clock. Background of the Invention The CCITT recommendations G.707, G.708 and G.709 specify a synchronous digital hierarchy SDH, which enables the multiplexing of the signals of existing PCM systems, such as 2, 8, 34 and 140 Mbit/s, into a synchronous frame of 155 Mbit/s called STM-1 (synchronous transfer module). The structure of the STM-1 frame is illustrated in Figure 1. The frame is usually shown as a unit comprising nine lines each having 270 bytes. The first nine bytes on each line contain a section overhead and AU pointer bytes. The remaining portion of the transfer frame STM-1 con- tains one or more administration units AU. In this specific case, there is an administration unit AU-4 of the highest level, in which a virtual container VC-4 similarly of the highest level is placed, and e.g. a 139264 kbit/s plesiochronous information signal can be mapped directly in the virtual con¬ tainer VC-4. Alternatively, the transfer frame STM-1 may contain several lower-level administration units AU in each one of which a corresponding virtual con¬ tainer VC of the lowest level is placed. In Figure 1, the VC-4 comprises a 1-byte path overhead POH and a 240-byte information bit group at the start of both of which a special control byte is placed. Some of the control bytes are used e.g. for performing inter¬ face justification in connection with mapping when the rate of the information signal to be mapped devi¬ ates to some extent from its nominal value. Mapping of the information signal into the transfer frame STM-1 is described e.g. in the patent applications AU-B-34639/89 and FI-914746. Each byte in the unit AU-4 has a position number. The above-mentioned AU pointer contains the position of the first byte of the container VC-4 in the unit AU-4. In addition, by means of the pointers, so-called positive or negative pointer justifications can be performed at the different locations of the SDH network. If a VC having a certain clock frequency is applied to a network node operating at a clock frequency lower than the above-mentioned clock fre¬ quency of the VC, the data buffer will be filled up. This requires negative justification: one byte is transferred from the received VC into the overhead section while the pointer value is decreased by one. If the rate of the received VC is lower than the clock rate of the node, the data buffer tends to be emptied, which calls for positive justification in which a stuff byte is added to the VC and the pointer value is incremented by one. Bit justification (interface justification) used in mapping as well as pointer justification cause phase jitter, which should be compensated for by the desynchronizer on leaving the SDH network. Phase jitter and its compensation are described e.g. in Simulation Results and Field Trial Experience of Justification Jitter, Ralph Urbansky, 6th World Tele- communication Forum, Geneva, 10-15 October 1991, International Telecommunication Union, Part 2, Vol III, p. 45 to 49. For this purpose the prior art desynchronizers comprise a data buffer with an associated analog phase-locked loop (PLL) which phase-locks the read clock of the data buffer to the write clock. As the PLL operates in the same way as a lowpass filter, it removes jitter except for jitter components of the lowest frequency. For instance, the pointer justi- fication of the SDH typically generates much more intensive jitter components than bit justification as individual phase discontinuities in the pointer jus¬ tification are e.g. 8 or 24 frame intervals UI and as the frequency of occurrence of phase discontinuities induced by pointer justifications may represent a very low frequency difficult to filter in the PLL of the desynchronizer. Adequate suppression of pointer jitter by filtering would require that the bandwidth of the loop should be very low (the absolute value depends on the rate of the interface) . Figures 2 and 3 show how the jitter peaks induced by two pointer justifications of 24 UI (measured from the output of the desynchronizer through a measuring filter spe¬ cified by the CCITT) can be reduced to an acceptable maximum level of about 0.2 UI by drastic filtering when the bandwidth of the PLL at e.g. 140 Mbit/s is about 2 Hz. However, no pointer justifications are needed in normal operation, and only bit justifica¬ tions are active. Accordingly, the dimensioning of the phase-locked loop of the desynchronizer on the basis of pointer justifications is unreasonable as the bandwidth of the PLL could be even ten times higher from the viewpoint of bit justification. The locking of the PLL would thereby also be more reliable and the locking time would be substantially shorter. One prior art solution to the problem is bit leaking, in which pointer induced phase discontinu¬ ities are removed by a non-linear process (in the time domain), whereby incoming data bits are process¬ ed by a separate serial buffer so that the phase of the write clock and data applied to the buffer of the desynchronizer is advanced (or retarded) periodical¬ ly, and so a stepwise phase shift is converted into a linear phase shift taking place over a longer period of time. The pointer justifications are thereby pro¬ cessed separately by a bit leaking buffer so that the bandwidth of the phase-locked loop of the desynchron¬ izer itself can be increased so as to meet the re- quirements of the bit justifications. A problem with bit leaking is the bit-level serial data processing and the relatively complicated logic. It is further to be noted that it is not adequate that one pointer at a time can be processed but, in the worst case, the logic should be able to operate with tens of overlapping pointer justifications at different decay stages. Therefore the use of this technique in a high-rate 140 Mbit/s desynchronizer is not advisable due to the increased power consumption, for instance. Disclosure of the Invention The object of the invention is to provide a simple and economical arrangement for suppressing pointer jitter peaks, which is also suitable for the rate of 140 Mbit/s and even higher rates. This is achieved by means of a method according to the invention, comprising modulating the phase jitter induced by the pointer justifications occurring in the input signal of the desynchronizer to a frequency substantially higher than the band- width of the phase-locked loop. As mentioned above, the frequency of occurrence of phase discontinuities induced by pointer justi¬ fications may represent a very low frequency dif- ficult to filter in the phase-locked loop of the de¬ synchronizer. The idea of the invention is that, in place of the pointer suppression at the "baseband" like in the bit leaking technique, the pointer jitter frequencies are modulated to a higher frequency so that they will be filtered off in the phase-locked loop. In the signal processing according to the in¬ vention, the data is in the form of 8-bit parallel bytes inherent to the SDH and also used elsewhere in the desynchronizer. The byte-by-byte integration or suppression of phase discontinuities over a longer period of time enables a simple CMOS logic implemen¬ tation at 140 Mbit/s and even higher rates, or even a common data buffer with the phase-locked loop. In the preferred embodiment of the invention the modulation comprises the shifting of the phase of the read clock derived from the input signal of the desynchronizer in 8-bit steps in one direction e.g. at a frequency fl substantially higher than the effective bandwidth of the phase-locked loop, and in the opposite direction at a frequency fl±df, where df is a parameter varying according to the occurrence of the pointer justifications. The parameter df is zero when no pointer justifications occur, and a positive or negative increment is added to the parameter df for a predetermined period of time in response to each positive or negative pointer justification, respectively. The invention also relates to the desynchron- izers according to claims 5 and 7. Brief Description of the Drawings The invention will be described more closely in the following by means of illustrating embodiments with reference to the attached figures, in which Figure 1 illustrates the transfer frame STM-1 of the SDH system; Figures 2 and 3 illustrate a phase dis¬ continuity occurring in the input of a prior art de¬ synchronizer and phase jitter present in the output, respectively, when the transmission rate is 140 Mbit/s and the bandwidth of the phase-locked loop is about 2 Hz; Figure 4 is a block diagram illustrating a typical desynchronizer without pointer jitter suppression; Figure 5 is a block diagram illustrating a pointer jitter suppression circuit according to the invention; and Figure 6 is a block diagram illustrating an- other pointer jitter suppression circuit according to the invention as applied to the desynchronizer shown in Figure 4; and Figure 7 is a signal diagram illustrating threshold modulation. Detailed Description of the Invention In the following the invention will be de¬ scribed in connection with signals complying with the synchronous digital hierarchy SDH defined in the CCITT recommendations G.707, G.708 and G.709, but it can also be applied to other similar digital signals employing the justification technique, such as the synchronous optical network SONET. The frame structure STM-1 of the SDH system, the framing and the pointer and bit justifications were described above with reference to Figure 1. In addition, the above-mentioned CCITT recommendations, the above-mentioned article by Ralph Urbansky, and the patent applications FI-914746 and AU-B-34639/89 are referred to. The SONET system is described e.g. in To Know Your Sonet , Know Your VTs by Stephen Fleming, TE&M, June 15, 1989, p. 62 to 75. Figure 4 shows a prior art desynchronizer. A digital synchronous signal DATA, such as an SDH signal consisting of STM-1 frames, is received at the input of a buffer memory 1, from where it is written in parallel form byte by byte in accordance with addresses generated by a write address counter 2 to the buffer memory 1, and further read byte by byte in accordance with addresses generated by a read address counter 3 in parallel form byte by byte out of the buffer 1 so that a digital output signal DATA OUT with a desired transmission rate, e.g. 140 Mbit/s, is obtained from the desynchronizer. The write address counter 2 generates write addresses in synchronization with a write clock CLKl. Correspond¬ ingly, the read address counter 3 generates read addresses in synchronization with a read clock CLK2. The read clock CLK2 is phase-locked to the write clock CLKl by a phase-locked loop (PLL) comprising a phase detector, a lowpass filter and a voltage-con¬ trolled oscillator. Signals CLK1/N and CLK2/N derived from the write and read clocks by dividing are applied to the phase detector 4 from the counters 2 and 3, where N is a divisor dimensioned in accordance with the length of the buffer and the active range of the phase detector. The phase detector 4 produces a voltage signal VI proportional to the phase dif¬ ference between the signals CLKl/N and CLK2/N, and this voltage signal is applied through a resistor R3 to an operational amplifier Al. The operational amplifier Al with associated resistors R3, R5, R6, R7, C3 and condenser C4 forms a loop filter which determines the loop gain of the phase-locked loop. The loop gain is selected so that an appropriate bandwidth is obtained. The operational amplifier Al generates a control voltage V 3 applied to the control input of the voltage-controlled oscillator 5 so as to determine the frequency of the read clock CLK2 gener- ated by the oscillator 5. The phase-locked loop tends to adjust the frequency of the read clock CLK2 so that the phase difference between the clocks CLKl and CLK2 is sufficiently small. A desynchronizer cir¬ cuit of this type and different variations thereof are well-known to one skilled in the art. The PLL of the desynchronizer shown in Figure 4, however, is not as such able to sufficiently suppress phase discontinuities, called pointer jus¬ tifications herein, induced by the pointer justifica- tions occurring in the incoming digital signal DATA. As mentioned above in connection with Figures 2 and 3, the pointer jitter in the output DATA OUT of the desynchronizer can be suppressed satisfactorily by limiting the bandwidth of the PLL but the speed and reliability of the locking of the PLL are deteriorat¬ ed at the same time. In the invention this problem is solved by mod¬ ulating the phase jitter caused by the pointer justifications occurring in the input signal DATA of the desynchronizer from its normal frequency of occurrence to a higher frequency which is substan¬ tially higher than the bandwidth of the phase-locked loop of the desynchronizer, and so the phase-locked loop is able to efficiently suppress the pointer phase jitter in the output signal DATA OUT of the desynchronizer. Figure 5 shows a byte-by-byte phase discontinu¬ ity suppression circuit (byte leaking) according to the preferred embodiment of the invention, which, when connected in series before the desynchronizer shown in Figure 4, forms a desynchronizer operating in accordance with the invention. Generally -speaking, the purpose of the suppression circuit of Figure 5 is to advance or retard the phase of the digital signal DATA and the clock CLKl applied to the desynchronizer of Figure 4 in response to the occurrence of the pointer justifications so that the maximum amplitude of the pointer phase jitter in the output signal DATA OUT of the desynchronizer 1 of Figure 4 will be suppressed. In Figure 5, a digital synchronous signal DATA IN, such as an SDH signal consisting of STM-1 frames, is received at the input of a buffer memory 21 (from now on called an auxiliary buffer), from where it is written in parallel form byte by byte in accordance with addresses generated by a write address counter 22 to the auxiliary buffer 21 and further read in accordance with read addresses generated by a read address counter 23 in parallel form byte by byte from the auxiliary buffer 21, thus obtaining a digital signal DATA applied to the input of the data buffer 1 (Figure 4) cascaded with the buffer 21. The write address counter 22 generates write addresses in syn¬ chronization with a write clock CLK and, correspond- ingly, the read address counter 23 generates read addresses in synchronization with a read clock CLKl. THe circuit of Figure 5 further comprises a control logic which receives at its inputs a write address from the counter 22, a read address from the counter 23 and a frame synchronizing address FSYNC, a positive pointer justification detection signal +P and a negative pointer justification detection signal -P from the digital section of the desynchronizer. As is well-known in the art, the desynchronizer produces signals indicating the time of occurrence and direction of each pointer justification for internal use, and these signals can be utilized in the implementation of the present invention. The signals applied to the control circuit 24 are the same as those used in typical bit leaking implementations. The output signal of the control logic 24 is the read clock CLKl, which controls the read address counter 23 and the read address counter 2 shown in Figure 4. The control logic 24 shifts the phase of the read clock CLKl, e.g. advances the phase, substan¬ tially at uniform intervals at a predetermined fre¬ quency fl, and performs opposite phase shifts, e.g. retards the phase, substantially at uniform intervals at another frequency fl±df. In this way "artificial" phase discontinuities are produced in the signal DATA at the frequency fl, which are filtered off in the phase-locked loop of the desynchronizer when fl is substantially higher than the bandwidth of the phase- locked loop. As the parameter df is variable in response to the occurrence of pointer justifications, the fre¬ quency of occurrence of artificial opposite pointer phase justifications effected can be adjusted by the actual pointer justifications, and so the baseband phase jitter caused by the actual pointer justifications can be shifted to the frequency fl. In the preferred embodiment of the invention the control means 24 adjusts the parameter df in accordance with the occurrences of the pointer justifications indicated by the signals +P and -P in the following way: the control logic 24 resets the parameter df when no pointer justifications occur. Thereby artificial phase shifts occur in the clock signal CLKl at the same frequency fl both onwards and back- wards. When a positive pointer justification occurs in the signal DATA IN, the control logic 24 adds a positive increment to the parameter df for a pre¬ determined period of time, as a result of which the artificial backward phase shifts of the signal CLKl take place at a frequency slightly higher than the frequency of the onward phase shifts. Corresponding¬ ly, the control logic 24 adds a negative increment to the parameter df for a predetermined period of time, i.e. decreases its value, as a result of each negative pointer justification occurring in the signal DATA IN. In the invention the bandwidth of the phase- locked loop at 140 Mbit/s is e.g. 20 Hz and the fre¬ quency fl is e.g. about 1 kHz. The phase locked loop may, of course, also be a digital phase locked loop with a digital loop filter. For the sake of clarity, the byte leaking technique described in this specific example utilizes a dedicated elastic buffer. Naturally, the invention can also be integrated in a prior art desynchronizer so that a single common elastic buffer with the associated drivers is needed. Figure 6 also shows a byte leaking circuit ac¬ cording to the invention, which utilizes the same buffer 1 as a desynchronizer of the type shown in Figure 4. In this way the separate pointer buffer 21 shown in Figure 5 can be omitted. The circuit of Figure 6 comprises a parallel subtractor 61 which receives the count (write address) from the write address counter 2 and subtracts it from an offset count Dl present at its second input and applies the difference CLK1A/N to the phase comparator 4. Other¬ wise the phase-locked loop is similar to that shown in Figure 4. The circuit in Figure 6 further com- prises a control logic 64 which receives the signals +P, -P and FSYNC and the write clock CLKl at its in¬ puts and performs artificial phase shifts at the fre¬ quencies fl and fl+df, as described in connection with Figure 5. In addition, the control logic 64 generates a signal Dl which, at intervals of l/(f±df), gets a difference value corresponding to the pointer justification. The difference value is subtracted from the write address CLK1/N in the subtractor circuit 61. At other time instants the value of the signal Dl is 0. The value of the para¬ meter df is again dependent on the occurrence of the pointer justifications, and it is adjusted similarly as in the embodiment of the Figure 5. In this way the phase jitter will be converted from the baseband fre- quency to the frequency fl. In the circuits of Figures 5 and 6, the control logic 24 and 64, respectively, may generate phase discontinuities e.g. by threshold modulation, which is illustrated in Figure 7. The unbroken lines 71 and 72 represent upper and lower thresholds, respectively, which change in a saw-tooth-like manner as a function of time and the values of which continuously differ from each other in an amount cor¬ responding to the signal amplitude of the phase signal 73. The upward transitions 71A and 72A of the saw-tooth wave signals 71 and 72, respectively, take place at the frequency fl. When the slightly sliding phase signal 73 reaches the upper threshold, a down¬ ward (backward) phase shift is performed, and when it reaches the lower threshold, an upward (onward) phase shift is performed. In this specific example, the upward phase shifts 73A always fall within the steep transitions 72A of the saw-tooth wave, thus occurring at the constant frequency fl. The downward phase shifts 73B of the phase signal 73 take place at a point which slides onwards along the back slope of the saw-tooth wave 71 at the frequency fl-df. Finally, in accordance with the invention, artificial phase shifts occurring at the frequencies fl and fl±df will be obtained. The justification frequency in bit justification may represent the worst possible jitter frequency passing through the phase-locked loop, but as the duration of the phase discontinuities in bit justification is only one time interval, the low phase jitter induced by them has been insignificant as compared with the pointer jitter. In the compen¬ sation circuit according to the invention, the pointer jitter is suppressed, and so the jitter caused by bit justification may also become problematic. The circuits of Figures 4 and 6 may also be used for compensating the jitter induced by bit justification concurrently with the compensation of the pointer jitter. The parameter df thereby also depends on the occurrence of bit justifications, and whenever a bit justification takes place, an increment is added to the parameter df for a period of time which is e.g. 1/8 or 1/24 of the corresponding period of time of the increment induced by an 8-bit or 24-bit pointer justification. On the basis of the above description, the dif¬ ferent practical implementations and modifications for realizing the pointer jitter modulation according to the invention are obvious to one skilled in the art. The figures and the description related to them are only intended to illustrate the present inven¬ tion. In its details the method and desynchronizers according to the invention may vary within the spirit and scope of the attached claims.

Claims: Claims: 1. Method for suppressing pointer phase jitter in a desynchronizer comprising a data buffer means; a data buffer write address counter controlled by a write clock; a data buffer read address counter con¬ trolled by a read clock; and a phase-locked loop for phase-locking the read clock to the write clock, c h a r a c t e r i z e d in that the method com- prises modulating the phase jitter induced by the pointer justifications occurring in the input signal of the desynchronizer to a frequency substantially higher than the bandwidth of the phase-locked loop. 2. Method according to claim 1, c h a r a c - t e r i z e d in that the modulation comprises shifting the phase of the read clock derived from the input signal of the desynchronizer byte by byte in one direction at a frequency fl substantially higher than the bandwidth of the phase-locked loop, and in an opposite direction at a frequency fl±df, where df is a parameter varying according to the occurrence of the pointer justifications. 3. Method according to claim 1 or 2, c h a r ¬ a c t e r i z e d in that the modulation is perform- ed by threshold modulation. 4. Method according to claim 1, 2 or 3, c h a r a c t e r i z e d in that the parameter df is zero when no pointer justifications occur, and that a positive or negative increment is added to the parameter df for a predetermined period of time as a result of each positive or negative pointer justi¬ fication, respectively. 5. Desynchronizer comprising a pointer buffer means (21) and a data buffer means (1) in a cascade; a pointer buffer write address counter (22) con- trolled by a first write clock (CLK); a pointer buffer read address counter (23) controlled by a first read clock (CLKl); a data buffer write address counter (2) controlled by said first read clock; a data buffer read address counter (3) controlled by a second read clock (CLK2); a phase-locked loop (4, 5, 7) for locking said second read clock to the first read clock; and phase shifting means (24) for advanc¬ ing and retarding the phase of the read clock in response to the occurrence of the pointer justifica¬ tions so as to suppress the pointer jitter, c h a r¬ a c t e r i z e d in that the phase of the first read clock is shifted by the phase shifting means (24) in a first direction substantially at uniform intervals at a first frequency fl and in an opposite direction at uniform intervals at a frequency fl±df, where df is a parameter varying according to the occurrence of the pointer justifications. 6. Desynchronizer according to claim 5, c h a r a c t e r i z e d in that the phase shifting means (24) is responsive to the occurrence of the pointer justifications, resetting the parameter df when no pointer justifications occur, and adding a positive or negative increment to the parameter df for a predetermined period of time as a result of each positive or negative pointer justification, respectively. 7. Desynchronizer comprising a data buffer means (1), a data buffer write address counter (2) controlled by a write clock (CLKl) ; a data buffer read address counter (3) controlled by a read clock (CLK2); and a phase-locked loop comprising a phase comparator means (4) comparing the readings of the read and write counters; a loop filtering means (7); and a voltage-controlled oscillator means (5), for locking the read clock to the write clock, c h a r¬ a c t e r i z e d in that the desynchronizer com¬ prises means (61, 64) for subtracting a difference value from the write address of the write counter (2) at a frequency fl±df substantially higher than the bandwidth of the phase-locked loop, and for applying the resulting address to the phase comparator means (4), where df is a parameter varying according to the occurrence of the pointer justifications. 8. Desynchronizer according to claim 7, c h a r a c t e r i z e d in that the subtraction means (61, 64) are responsive to the occurrence of the pointer justifications, resetting the parameter df when no pointer justifications occur, and adding a positive or negative increment to the parameter df for a predetermined period of time as a result of each positive or negative pointer justification.

Inventors: URALA REINO, URALA, REINO
Applicants: NOKIA TELECOMMUNICATIONS OY
Application year: 1993
Main classification: H04L7
IPC codes: H04J3, H04Q11