LOGIC CELL WHICH CAN BE CONFIGURED AS A LATCH WITHOUT STATIC ONE'S PROBLEM

Abstract: A latch may be formed as a two-part structure, one part for data input and one part for feeding back the data to form the latch. A clock signal controls whether data from a data input terminal will be forwarded to the output or whether the output signal will be provided as input and forwarded, thus forming the latch. A problem called the static ones hazard, namely registering a logical 0 when data input is logical 1, can occur with a latch of this logic structure when the circuit is entering the latch mode. In accordance with the invention, this static ones hazard is avoided by controlling trip points in the gates of the cell and input buffers of the cell so that the cell implements a make-before-break transition.

Description: LOGIC CELL WHICH CAN BE CONFIGURED AS A LATCH WITHOUT STATIC ONE'S PROBLEM FIELD OF THE INVENTION The invention relates to programmable logic devices formed in integrated circuit chips. More particularly, the invention relates to logic cells which are part of field programmable gate array chips. BACKGROUND OF THE INVENTION In integrated circuit devices, sequential functions such as flip flops are typically formed from latches. A latch may be formed as a two-part structure, one part for data input and one part for feeding back the data to form the latch. A clock signal controls whether data from a data input terminal will be forwarded to the output or whether the output signal will be provided as input and forwarded, thus forming the latch. A problem called the static ones hazard, namely registering a logical 0 when data input is logical 1, can occur with a latch of this logic structure when the circuit is entering the latch mode. This occurs because a switching latch enable signal can cause a logical 0 signal to appear at the output of the data input section before the logical 1 data has been captured into the feedback section. Thus a logical 0 is erroneously captured. Such an error must of course be avoided. One prior art method of avoiding the static ones hazard is to add an extra gate. John F. Wakerly in a textbook entitled "Digital Design Principles and Practices" published in 1990 by Prentice Hall, Inc. describes the static one's hazard at pages 413-415, and shows a circuit having a gate which independently receives the data input signal. This extra gate does successfully avoid the static one's hazard. However, the extra gate adds silicon area and also slows the response time, and for those reasons is undesirable. It is preferable to avoid the static one's hazard without increasing silicon area or reducing performance. SUMMARY OF THE INVENTION According to the present invention, this static ones hazard is avoided by controlling trip points in the gates of the cell so that the cell implements a make-before-break transition. The trip point is the input voltage at which the output voltage changes between logical 0 and logical 1, and may be defined for an inverter as that voltage at which the input voltage is equal to the output voltage. Clock input signals are applied to each part of the two- part structure, one clock signal being inverted and the other noninverted. Logic gates in each part combine the clock signal and the input or feedback signal to generate an intermediate output. Intermediate outputs of the two parts are combined in another logic gate to generate a latch output signal. If the inverter which receives the clock signal has a relatively low trip point and the logic gate which receives the clock signal has a relatively high trip point, a static ones' error is found to occur. If the inverter has a higher trip point and the logic gate has a lower trip point, the Q output signal is found to properly follow the D input signal through the positive and negative shifts of the clock signal. By manufacturing inverters at the gate inputs to have higher trip points than trip points of the logic gates which receive the clock signal and the input data or the feedback data, the static one's problem is avoided. This combination of trip points produces correct results for both a fast-changing clock signal and a slow-changing clock signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a logic cell which can implement the static latch of the present invention. Figs. 2A and 2B show a latch with clear and its implementation using the cell of Fig. 1. Figs. 2C shows the equivalent circuit formed by the circuit of Fig. 2B. Figs. 2D and 2E show a latch with clear having the opposite clock polarity from that of Figs. 2A-2C. Fig. 2F shows the equivalent circuit formed by the circuit of Fig. 2E. Fig. 3A shows a timing diagram of signals in the circuit of Figs 2A-2C, illustrating a static-ones problem. Fig. 3B shows a timing diagram which avoids the static ones problem of Fig. 3A by properly controlling the trip points of the inverters and NAND gates of Fig. 1. DETAILED DESCRIPTION OF THE INVENTION The logic cell of Figure 1 comprises four major sections: (1) a programmable input inverter stage 300, (2) a cascade-in first combinational stage 310, (3) a feedback first combinational stage 320, and (4) a second combinational stage 330. Overview of the Four Sections of Fiσ. 1 Input buffer stage 300 comprises four input buffers 301 through 304, each of which can be inverting or non-inverting as selected by the user. Cascade-in first combinational stage 310 comprises a 3- input NAND gate 311 and a 2-input OR gate 312. OR gate 312 receives a cascade enable control input 313 and a cascade input 314 from an adjacent cell. OR gate 312 provides input to NAND gate 311. Also provided as input to NAND gate 311 are outputs from selectively inverting input buffers 301 and 302. Feedback first combinational stage 320 also comprises a three-input NAND gate 321 fed by output signals from selectively inverting input buffers 303 and 304. NAND gate 321 further receives input from OR gate 322 which receives on one of its input terminals a feedback signal 332 and on another input terminal a feedback enable control input 323. Second combinational stage 330 can be programmed to provide a NAND or a NOR function of outputs from the cascade combinational stages 310 and 320. Second combinational stage 330 provides an output signal 332 which can be fed back by OR gate 322 to AND gate 321, can further be provided as a cascade OUT signal which becomes a cascade IN signal to an adjacent cell, and which is provided to output driver stage 340, where it can be driven onto the interconnect structure and used as input to other cells. Latch with Clear and Solution to Static Ones Problem Fig. 2A shows a latch with clear which can be implemented by the circuit of Fig. 1. Fig. 1 can be configured several ways to implement the static latch, however only one method will be described. As shown in Fig. 2B, the D (data) input of Fig. 2A is provided on line Al of Fig. 1. Latch enable signal LE of Fig. 2A is applied to lines A2 and A3. Optional inverter 302 is set to be inverting and optional inverter 303 is set to be noninverting. The Reset input of Fig. 2A is provided to line A4. Feedback control unit CCU7 stores a logical 1 which enables the feedback path by applying a logical 0 to the C input of OR gate 322. The Q output signal is thus fed back through the D input of OR gate 322 to NAND gate 321. AND gates ANDl and AND2 and OR gate ORl of Fig. 2A are achieved (according to DeMorgan's theorem) by configuring second combinational stage 330 as a NAND gate. A problem called the static ones hazard can occur with a latch of this logic structure when the circuit is entering the latch mode. The problem can be understood more clearly in conjunction with Figs. 2A through 2C, 3A, and 3B. Depending upon the particular transistors used to implement the gates of Fig. 2B, a transition of latch enable signal LE from low to high may cause a logical zero to be latched when a logical one was present on the data input line. This occurs because a rising LE signal can cause logical zero signals to appear simultaneously (albeit only momentarily) on inputs to both of NAND gates 311 and 321. If these logical 0 signals appear simultaneously at NAND gate 330, a logical 1 data signal will be latched as a logical 0, causing an error. Such an error must be avoided of course, and this can be assured in the circuit of Fig. 1 (Fig. 2B) by controlling trip points in optional inverter 302 and the trip point of NAND gate 321. Fig. 2D illustrates a latch with clear in which the latch enable signal LE has the opposite polarity of that in Fig. 2A. Both polarities are needed when sequential latches are needed, for example in a flip flop. Fig. 2E shows the implementation of the latch of Fig. 2D in the Fig. 1 circuit, and Fig. 2F shows the equivalent circuit which results. Optional inverter 302 is configured to pass the LE signal through to the A input of NAND gate 311 and optional inverter 303 is configured as an inverter, passing the complement of A3 to the A input of NAND gate 321. Figs. 3A and 3B show two different timing diagrams which can result from the circuit of Fig. 2C. The timing diagram of Fig. 3A has a break-before-make characteristic, which exhibits the static ones problem. The timing diagram of Fig. 3B has a make-before-break characteristic, which avoids the static ones problem. By manufacturing optional inverters 302 and 303 of Fig. 1 to have higher trip points than trip points of NAND gates 311 and 321, the timing diagram of Fig. 2B is achieved and the static one's hazard is avoided. Figs. 2A and 2B are now explained. In the circuit of Figs. 2A through 2C, the input signals are the data input signal D and the latch enable signal LE. (Figs. 3A and 3B may also represent the timing diagrams for the master portion of a D or JK flip flop) . As shown in Figs. 3A and 3B, at time t 0 , the D input is logical 1 and the latch enable signal LE is low, so that the D input signal is being passed through to the Q output. Shortly before time ti, latch enable signal LE begins to go high. Because this signal comes from the interconnect structure, which has some capacitance and resistance, latch enable signal LE is shown as having a gradual rise to logical 1. The description which follows also applies to a latch enable signal which switches quickly with respect to the switching time of inverters and NAND gates within the cell. This LE signal is applied to optional inverter 302 which passes the inverted LE signal to input A of NAND gate 311. Optional inverter 303 is set to be noninverting and thus passes the LE signal to NAND gate 321. In Fig. 3A, curve 3, labeled LE-L, shows how the LE signal is interpreted if the element (inverter or NAND gate) receiving the signal has a low trip point, and curve 4, labeled LE-H, shows how the LE signal is interpreted if the element receiving the signal has a high trip point. In the case of Fig. 3A, inverter 302 has a relatively low trip point and NAND gate 321 has a relatively high trip point. A static ones' error is shown to occur. Curve 5 represents LE-L; the output of optional inverter 302 begins going low at time ti because optional inverter 302 is assumed to have a low trip point. Curve 6 represents the ANDl output of Fig. 9A, the complement of which is calculated in the implementation of Figs. 9B and 9C by NAND gate 311. Curve 7, which represents the AND2 output signal,the complement of which is generated by NAND gate 321, responds to the signal LE, which was low at time t 0 . Since NAND gate 321 has a relatively high trip point, curve 7 doesn't go high at time ti. Since D*LE-L goes low before LE-H goes high, the logical 1 value on D is lost before it is latched as the Q output, and a logical 0 is erroneously latched as Q from a time after ti to a time after t 4 . In the case of Fig. 3B, inverter 302 has a higher trip point and NAND gate 311 has a lower-trip point. Curve 5 shows the LE-H output signal of optional inverter 302 when manufactured to have a high trip point. Curve 6 shows the ANDl signal D*LE-H, the complement of which is generated by CLAIMS I claim: 1. A transparent latch having circuits for receiving inverting and noninverting clock input signals, said circuit for receiving said inverting clock input signal having a higher trip point than said circuit for receiving said noninverting clock input signal. 2. A transparent latch comprising: a data input section which receives a data input signal and a clock signal, and generates a data output signal; a feedback section which receives a feedback input signal and the complement of said clock signal, and generates a feedback output signal; means for passing said clock signal to said data input section and generating said complement of said clock signal; and a second section which generates an output signal from signals provided by said data input section and said feedback section, said output signal serving as said feedback input signal; said means for generating said complement of said clock signal comprising an inverter having a first trip point, and said data input section and said feedback section comprising logic gates having a second trip point lower than said first trip point. 3. A transparent latch as in Claim 2 in which: said means for passing said clock signal comprises an optional inverter, and said means for generating said complement of said clock signal comprises said optional inverter.

Claims: NAND gate 311. Curve 7 shows the AND2 output function Q*LE- L, the complement of which is generated by NAND gate 321. Finally, curve 8 shows the Q output function over the time interval o through t 9 . The Q output signal is seen to properly follow the D input signal through the positive and negative shifts of the D and LE signals. This is because the LE-L and LE-H signals are never low at the same time. This ensures one of the two NAND gates 311 or 321 will be allowed to propagate its input at all times, thereby providing the needed make-before-break characteristic. Other embodiments of the invention will become obvious to those skilled in the art in light of the above description. These other embodiments are intended to fall within the scope of the present invention. nsparent latch as in Claim 2 in which: said data input section comprises a two-input AND gate, one input receiving said data input signal and the other input receiving said clock signal; said feedback section comprises a two-input AND gate, one input receiving said feedback input signal and the other receiving said complement of said clock signal; and said output section comprises a two-input OR gate, one input receiving said data output signal and the other receiving said feedback output signal.

Inventors: GOETTING F ERICH, GOETTING, F., ERICH
Applicants: XILINX INC, XILINX, INC.
Application year: 1993
Main classification: H03K3
IPC codes: H03K3, H03K19