Wired-OR logic circuit

Abstract: A wired-OR logic circuit has a plurality of logic circuits (L₁ - L n ) connected to a common signal line (2). Each of the plurality of logic circuits includes an output bipolar transistor (T₁ - T n ) for outputting a logical output signal to the common signal line, and a constant-current source (4₁ - 4 n ) forming an emitter-follower circuit together with the output bipolar transistor and being turned-on or turned-off in response to an output select signal (E₁ - E n ). Each of the logic circuits may include a base potential setting circuit which applies different base potentials to a base of the output bipolar transistor. The outputs of the same level from all the logic circuits can be outputted to an output terminal without being influenced by voltage drops caused by distributed wiring resistances inherently existing in the signal line.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a wired-OR logic circuit, and more particularly to a wired-OR logic circuit constituted by a plurality of logic circuits each of which outputs a logic signal through an emitter-follower bipolar transistor. (2) Description of the Related Art An example of a conventional wired-OR logic circuit of the kind to which present invention relates is shown in Fig. 1. As shown therein, the wired-OR logic circuit includes a plurality (n) of logic circuits L 1 - L n which are selected by output select signals E 1 - E n (wherein n is an integer). An emitter of each of signal output transistors T 1 - T n in such logic circuits is an output terminal of each of such logic circuits, and each of outputs Q 1 - Q n is outputted to a common output terminal 3 through the same signal line 2 having distributed wiring resistances r 1 - r n-1 . The signal line 2 is connected to a low potential power source 5 of the lowest potential through a constant-current source 4 common to the plurality of logic circuits L 1 - L n . The operation of the above conventional wired-OR logic circuit is now explained. First, an output Q m of m'th logic circuit L m (wherein m is an integer of 1 ≦ m ≦ n) selected may take a state of high level (hereinafter referred to as "V H ") or a state of low level (hereinafter referred to as "V L "). Outputs of other non-selected logic circuit are fixed to the low level V L . Since the outputs of the logic circuits are in a wired-OR connection, a high level signal or a low level signal corresponding to an output Q m of the logic circuit L m is outputted to the output terminal 3. Now, assuming that the n'th logic circuit L n is selected and all the other remaining logic circuits are non-selected , a voltage value V OUT appearing at the output terminal 3 as an output Q n of the logic circuit L n is substantially V OUT = V H or V OUT = V L since the value is not influenced by the distributed wiring resistances r 1 - r n-1 . Next, assuming that the first logic circuit L 1 which is farthest from the output terminal 3 is selected and all the other remaining logic circuits are non-selected, a voltage value V OUT appearing at the output terminal 3 becomes V OUT = V H - (r 1 + r 2 +...+ r n-1 )·I or V OUT = V L - (r 1 + r 2 +...+ r n-1 )·I (wherein I is a current value of the constant-current source 4) according to an output state of the logic circuit L 1 due to a voltage drop since the path through which the current flows then is from the collector to the emitter of the transistor T 1 , through the distributed wiring resistances r 1 , r 2 , ..., r n-1 and from the constant-current source 4 to the lowest potential power source 5. Generally, when the m'th logic circuit L m is selected by the output select signal E m and the logic signal inputted to the base of the output transistor T m within the logic circuit L m is outputted as an output signal of the logic circuit L m from the emitter of the transistor T m through the output terminal 3, the voltage value V OUT at the output terminal 3 becomes V OUT = V H - (r m + r m+1 +...+ r n-1 + r n ) ·I or V OUT = V L - (r m + r m+1 +...+ r n-1 + r n ) ·I in accordance with an output state of the relevant logic circuit L m since the current passes through the collector and the emitter of the transistor T m and through the distributed wiring resistances r m , r m+1 , r n-1 , r n (wherein, for the sake of simplicity, r n = 0) and then flows from the constant-current source 4 into the lowest potential power source 5. In the conventional wired-OR logic circuit described above, a number of logic circuits share a common signal line 2 and a constant-current source 4 and it is so arranged that outputs Q 1 - Q n from the respective logic circuits are switched by the output select signals E 1 - E n . Consequently, even where the outputs Q 1 - Q n themselves of the logic circuits L 1 - L n are of the same signal level all through, the output signal level V OUT out from the logic circuit L 1 whose wiring length from the constant-current source 4 becomes long suffers a voltage drop due to distributed wiring resistances in the signal line 2. The voltage drop when compared with the output signal level from the output Q n of the logic circuit L n which is nearest to the constant-current source 4 will be in the amount or level of (r 1 + r 2 +... + r n-1 ) .I. As a result, there is a possibility that, in some occasions, the sufficient signal level, e.g., the minimum signal level, required for the next stage cannot be obtained by the conventional wired-OR logic circuit. This is a problem to be solved by the invention, in the conventional wired-OR logic circuit. US-A-5 093 587 discloses a logic circuit comprising an output transistor Q 1 coupled between circuit ground and an output terminal and a constant current source connected to the output transistor and which pulls down the emitter of the output transistor when a drive signal inputted to the base of the output transistor goes to a low level. SUMMARY OF THE INVENTION It is therefore, an object of the present invention to overcome the problem explained above and to provide an improved wired-OR logic circuit in which output signals from the respective logic circuits constituting the wired-OR logic circuit are maintained at the same level irrespective of differences in the lengths of wirings to the common output terminal and which, preferably, allows wide operational margins. Accordingly, the present invention provides a wired-Or logic circuit having a plurality of logic circuits connected to a common signal line in a wired-OR form, each of said plurality of logic circuits comprising: an output transistor having a collector connected to a constant-potential node and an emitter connected to an output terminal, for driving said output terminal in accordance with a level of an internal signal; and a constant-current source connected to the emitter of said output transistor, said constant current source being activated in response to a control signal of a first logic level so as to provide a predetermined current to said output transistor and being deactivated in response to said control signal of a second logic level; characterised in that each of said plurality of logic circuits further comprises an input circuit having an input node to which an input signal is applied and an output node which is connected to a base of said output transistor for producing said internal signal, said input circuit being activated in response to said control signal of the first logic level so that said internal signal of a first level or a second level is produced in accordance with a level of said input signal, and being deactivated in response to said control signal of the second logic level so that, irrespective of the level of said input signal, said internal signal is fixed to a third level which is different from both the first and second levels. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention explained with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing a conventional wired-OR logic circuit; Fig. 2 is a block diagram showing an arrangement according to a first embodiment of the invention; Fig. 3 is a circuit diagram showing a logic circuit in a transistor level; Fig. 4 is a circuit diagram showing the logic circuit of a first embodiment in a transistor level; Figs. 5A and 5B are diagrams for illustrating output states of logic circuits; and Fig. 5C is a graph showing I E - V BE characteristics of the output bipolar transistor, for explaining effects of the first embodiment. PREFERRED EMBODIMENTS OF THE INVENTION Now, preferred embodiments of the invention are here-inafter explained with reference to the accompanying drawings. Fig. 2 is a block diagram showing an arrangement according to a first embodiment of the invention. In Fig. 2, elements or portions corresponding to those in Fig. 1 showing the conventional wired-OR logic circuit are denoted by the same or similar references. In the arrangement shown in Fig. 2, the difference when compared with the conventional arrangement shown in Fig. 1 is that, whereas the constant-current source 4 is common to all the logic circuits L 1 - L n in the conventional arrangement, the constant-current sources 4 1 - 4 n are provided respectively between the emitters of the output bipolar transistors T 1 - T n and the low potential power sources 5 in each of the logic circuits L 1 - L n . These constant-current sources 4 1 - 4 n are switched ON and OFF, respectively, in accordance with states of the output select signals E 1 - E n and constitute emitter-follower circuits together with the output bipolar transistors T 1 - T n . Now, the operation of circuit arranged as above is explained. In Fig. 2, if only the output select signal E 1 is selected and all the other output select signals E 2 - E n are in "non-selected" modes, the constant-current source 4 1 becomes ON at the same time as the logic circuit L 1 is selected and the constant-current I 1 flows accordingly. On the other hand, the constant-current sources 4 2 - 4 n within the logic circuits L 2 - L n which are in "non-selected" modes turn OFF, so that no current flows therein. Generally, where the output select signal E m (wherein m is an integer of 1 ≦ m ≦ n) is selected, the constant-current source 4 m within the logic circuit L m becomes ON, but all the other constant-current sources are in OFF states so that no current flows therein. In this case, the current I m flows passing from the collector to the emitter of the bipolar transistor T m and to the low potential power source line 5 through the constant-current source 4 m , so that no voltage drop is caused by the distributed wiring resistances inherently existing in the signal line 2. Fig. 3 is a circuit diagram showing, in a transistor level, the arrangement of a logic circuit of an emitter-coupled logic (ECL) type being used as an example. In this circuit when a level at an output select terminal 6 is high with respect to an input reference voltage V R , that is, in the case of the "non-selected" mode, since the base potential of a transistor N 3 is higher than the reference voltage VR, the base potential of a transistor N 5 becomes higher than the base potential of a transistor N 6 , so that the transistor N 5 turns ON and the transistor N 6 turns OFF. Consequently, there is no flow of current between the emitter of an output transistor T and the collector of the transistor N 6 with the state being the same as that when the constant-current source is in an OFF state. Also, in this "non-selected" mode, since the base potential of a transistor N 1 is higher than the base potential of a transistor N 2 which receives at its base the reference voltage V R , the transistor N 1 turns ON and the current I E1 flows in a resistor R 1 . At this time, assuming that the potential across the base and emitter of the output transistor T is V f , the potential of the output Q becomes V Q = -(R 1 · I E1 + V f ) and becomes a low level. Next, contrary to the above, if the level at the output select terminal 6 is low, that is, in the case of the "selected" mode, since the emitter potential of the transistor N 4 is higher than that of the transistor N 3 , the base potential of the transistor N 6 is higher than that of the transistor N 5 so that the transistor N 6 turns ON and the transistor N 5 turns OFF. Consequently, the current I E2 flows from the emitter of the transistor T to the collector of the transistor N 6 . Also, in this "selected" mode, since the base potential of the transistor N 1 is lower than the base potential (reference voltage V R ) of the transistor N 2 , the path for the current I E1 changes according to a value of an input D which is the base voltage of the transistor N 9 . That is, the transistor N 9 turns ON when a high level potential is inputted to the input terminal D and, at this time, the current I E1 flows from a ground line, passes through the resistor R 1 and then flows from the collector to the emitter of the transistor N 9 . Thus, as the base potential of the transistor T becomes -(R 1 · IE 1 ), the potential Q at the output node is low and becomes -(R 1 · I E1 + V f ). On the other hand, when the input D is low, the current I E1 flows from the ground line, passes through the resistor R 2 and then flows from the collector to the emitter of the transistor N 2 . Thus, since no current flows in the resistor R 1 , the base potential of the transistor T equals the ground potential and, thus, the output potential Q is high with the potential of -V f being outputted. Next, an embodiment according to the invention is explained. Fig. 4 is a circuit diagram showing the logic circuit of this embodiment in a transistor level. As is seen in Fig. 4, the logic circuit according to this embodiment of the present invention is different from that shown in Fig. 3 in the point wherein, in the former, there is inserted a resistor R 7 in addition to the resistor R 1 between the collector of the transistor N 9 and the ground line, and the collector of the transistor N 9 is connected with the common junction node of the transistors R 1 and R 7 . According to this embodiment, as in the circuit shown in Fig. 3, when the output select terminal 6 is high ("non-selected" mode), the transistor N 5 turns ON and the transistor N 6 turns OFF, so that no current flows from the emitter of the transistor T to the collector of the transistor N 6 . At this time, if the transistor N 1 turns ON, the current I E1 flows in the resistors R 1 and R 7 so that, assuming that the potential across the base and emitter of the transistor T is V f , the output potential Q becomes V Q = -{(R 1 + R 7 ) .I E1 + V f }. That is, the potential of the output Q is lower by the magnitude or level of the -(R 7 · I E1 ) as compared with the circuit shown in Fig. 3 in which the resistor R 7 is not provided. It should be noted that the resistor R 2 , the series resistors R 1 and R 7 , and the transistors N 1 , N 2 and N 9 constitute a base potential setting circuit for supplying different base potentials to a base of the output bipolar transistor T by selecting a first and a second current path in accordance with a state of the input signal D and also a state of the output select signal OE . In the circuit shown in Fig. 3 the output Q of the logic circuit under the "non-selected" mode is fixed to a low level which is the same low level as the low level of the output Q of the logic circuit under the "selected" mode so that, as shown in Fig. 5A, a current path is formed in each of the logic circuits. This means that, as can be appreciated from the emitter current vs. base-emitter voltage (I E -V BE ) characteristics of a transistor shown in Fig. 5C, the emitter current is reduced whereby the potential difference across the base and emitter of the transistor becomes small. That is, the voltage V f across the base and emitter of the transistor concerned in Figs. 3 and 4 decreases and a low level of the output, Q , rises. On the other hand, according to the embodiment of the present invention shown in Fig. 4, since the potential V LL of the output Q of the logic circuit under the "non-selected" mode is caused to be lower than the low level potential V L of the logic circuit under the "selected" mode, no current flows to the emitter of the output transistor under the "non-selected" mode as shown in Fig. 5B and, thus, the low level of the output Q of the logic circuit under the "non-selected" mode becomes the output level of the entire circuit. This allows a larger operational margin. As explained above, according to the invention, a constant-current source together with an output bipolar transistor forming an emitter-follower circuit is provided in each of a plurality of logic circuits constituting a wired-OR logic circuit. This constant-current source is so constructed as to allow the current to flow only when the logic circuit to which it belongs is selected. According to the invention, when an output signal from among a plurality of logic circuits is outputted to a common signal line after being switched by output select signals, the necessary constant-current source is selected in response to such output signals and the current is allowed to flow only to the emitter-follower circuit for the selected logic circuit, so that the outputs of the same level from all of the logic circuits can be outputted to the output terminal without being influenced by voltage drops caused by distributed wiring resistances in the signal line from any of the logic circuits to the output terminal. Furthermore, by providing, in one preferred embodiment, in each of the logic circuits constituting a wired-OR logic circuit, a circuit which causes the output signal level under the "non-selected" mode to become lower than the low level of the output signal under the "selected" mode, the low level of the output signal from the selected logic circuit can be prevented from rising and this allows to widen the operational margin of the circuit. While the invention has been described in its preferred embodiments, it is to be understood that the scope of the invention is defined by the appended claims.

Claims: A wired-OR logic circuit having a plurality of logic circuits (L 1 -L n ) connected to a common signal line (2) in a wired-OR form, each of said plurality of logic circuits comprising: an output transistor (T) having a collector connected to a constant-potential node (GND) and an emitter connected to an output terminal, for driving said output terminal in accordance with a level of an internal signal ( Q ); and a constant-current source (N 3 -N 6 ,N 8 ,R 3 ,R 4 ,R 6 ) connected to the emitter of said output transistor, said constant current source being activated in response to a control signal ( OE ) of a first logic level so as to provide a predetermined current to said output transistor and being deactivated in response to said control signal ( OE ) of a second logic level; characterised in that each of said plurality of logic circuits further comprises an input circuit (N 1 ,N 2 ,N 9 ,R 1 ,R 2 ,R 7 ) having an input node to which an input signal (D) is applied and an output node which is connected to a base of said output transistor, for producing said internal signal ( Q ), said input circuit being activated in response to said control signal ( OE ) of the first logic level so that said internal signal ( Q ) of a first level or a second level is produced in accordance with a level of said input signal (D), and being deactivated in response to said control signal ( OE ) of the second logic level so that, irrespective of the level of said input signal (D), said internal signal ( Q ) is fixed to a third level which is different from both the first and second levels. A logic circuit according to Claim 1, wherein said input circuit comprises first, second and third current paths each having a resistor (R 1 ,R 2 ), and a selection circuit (N 9 ,N 1 ,N 2 ) for selecting one of said first, second and third current paths so that said internal signal of one of said first, second and third levels is outputted to said output node. A logic circuit according to Claim 1, wherein said input circuit comprises: a first transistor (N 9 ) having a collector connected to said base of said output transistor (T), a base connected to said input node, and an emitter connected to a constant-current source (N 7 ); a second transistor (N 1 ) having a collector connected to said base of said output transistor, a base for receiving said control signal ( OE ), and an emitter connected to said constant-current source; a first resistor (R 1 ) connected between said collector of said second transistor and said constant-potential node (GND); a third transistor (N 2 ) having a collector, a base for receiving a reference potential, and an emitter connected to said constant-current source; and a second resistor (R 2 ) connected between the collector of said third transistor and said constant-potential node. A logic circuit according to Claim 1, wherein said input circuit comprises: a first transistor (N 9 ) having a collector, a base connected to said input node, and an emitter connected to a constant-current source (N 7 ); a second transistor (N 1 ) having a collector connected to said base of said output transistor (T), a base for receiving said control signal ( OE ), and an emitter connected to said constant-current source; a first and a second resistor (R 1 ,R 7 ) connected in series between said collector of said second transistor and said constant-potential node (GND), said collector of said first transistor being connected to a junction node of said first and second resistors; a third transistor (N 2 ) having a collector, a base for receiving a reference potential, and an emitter connected to said constant-current source; and a third resistor (R 2 ) connected between the collector of said third transistor and said constant-potential node.

Inventors: NAKAIGAWA SACHIO, NAKAIGAWA, SACHIO, NAKAIGAWA, SACHIO C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H03K19
IPC codes: H03K19