Microprocessor and data processing system with register file

Abstract: A microprocessor having a register file (7) inside is so combined with an external memory (2) through a dedicated high-speed bus that the memory operates as a bank for said register file. This microprocessor further has means (12) for controlling a data transfer with said memory (2) or peripheral devices (30). When an address information to access said memory (2) is input to this microprocessor in order to control a data transfer between said memory (2) and a peripheral device (30), said control means (12) finds if the accessed area in said memory (2) is now in use as a bank for said register file (7), or not. When it is in use, said control means (12) controls a data transfer between said peripheral device (30) and said register file (7), instead of controlling the data transfer between said memory (2) and said peripheral device (30). So, said peripheral device can always access the newest information in said memory.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a microprocessor, which has a bank structure, and a data processing system in which said microprocessor is incorporated. In particular, this invention relates to a microprocessor which has a structure to conduct data processings by connecting a particular memory (bank RAM), which is mapped on an address map of a data processing system, with a group of registers contained in this microprocessor, and the data processing system itself. Description of Prior Arts Generally speaking, in a data processing system, such as a microprocessor system, memory devices having high-speed access ability and multi-ports are incorporated as general purpose registers in the microprocessor (referred to as MPU, below). The number of such devices which can be contained in the MPU is limited by the size of a semiconductor chip. In the prior art a number of these devices is known, cf. e.g. US-A-4 352 157 and MICROPROCESSORS AND MICROSYSTEMS, vol. 13, no. 9, November 1989, London, GB; I. HAY et al.: "TRON-Compatible 16/32-Bit Microprocessor". Consequently, a microprocessor system having a bank structure has been proposed. In this system, the word 'bank' means a group of registers which are mainly used for operations in the MPU. In usual, the number of banks for one task is determined according to the MPU program. In actuality, a several banks are incorporated in the MPU. When a task is switched into another, a group of registers, that is, a bank, is switched into another. As mentioned above, the number of banks incorporated in the MPU is limited according to the chip size of this MPU. Therefore, many banks cannot be incorporated in the MPU. In order to increase the number of banks which can be utilized by the MPU, a system having an external memory is proposed. In this system, banks are saved in areas of a special memory (bank RAM) mapped on the address map of this MPU. When a particular bank saved in a certain area of the bank RAM is recalled by the MPU, the data in said area is taken out from the memory and loaded on the bank in the MPU. In this case, if the data transfer between a bank inside the MPU and the bank RAM outside the MPU is carried out through external buses, the MPU must stop for a long time until the bank exchange is completed. Therefore, the data transfer between the bank in the MPU and the bank RAM is conducted through a dedicated bus at a high speed. As mentioned above, in the microprocessor system having the bank structure, bank exchange between the bank RAM outside the MPU and the bank in the MPU is conducted through the dedicated high speed bus, instead of external buses. In this system, however, the following problem arises. When a peripheral device of the MPU accesses the bank RAM through external buses, the device does not recognize whether the content in the accessed area of the bank RAM is now in use by the MPU as a bank or not. Only the MPU recognizes whether the content accessed by said peripheral device is now in use by itself, or not. Accordingly, when the MPU uses the bank RAM as a bank, the peripheral device is able to access only the old information of the bank RAM. In other words, when the MPU uses the bank RAM as a bank, the Peripheral device cannot access the newest information in the bank RAM. SUMMARY OF THE INVENTION This invention has been made to overcome the above mentioned disadvantage of the prior art microprocessor and data processing system. Therefore, the objective of the present invention is to provide a microprocessor which can be incorporated in a data processing system having a bank structure and has a function to effectively control the data transfer between itself and an external memory, in order that a peripheral device is able to access the newest information in said external memory, as set out in the appended claims. This and other objectives, features, and advantages of the present invention will be more apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows the principle of the present invention; and Fig. 2 shows the structure of a microprocessor and a data processing system according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS Fig. 2 shows the structure of a microprocessor according to one embodiment of the present invention, and a data processing system in which said microprocessor is incorporated. As shown in the figure, the data processing system is comprised of a microprocessor (referred to as MPU, below) 1, bank RAM 2, an external address bus ABUS, an external data bus DBUS, an external control bus CBUS, and at least one peripheral device 30. MPU 1 is connected with said buses as shown in Fig. 2. On the other hand, bank RAM 2 is connected with data bus DBUS. This bank RAM 2 is also connected with MPU 1 through dedicated high-speed bus 17 and bank RAM address control signal 18. In this system, at least one peripheral device 30, such as an I/O, a ROM, and a RAM, each of which is mapped on the address map of MPU 1 through external address bus ABUS, data bus DBUS, and control bus CBUS, is connected to MPU 1. MPU 1 is comprised of the following: a bus interface unit (BIU) 3; an instruction queue 4; a micro-ROM 5; an arithmetic and logical unit (ALU) 6; a register file (REG) 7; a bank interface unit 8; and a bank control unit 9. In reality, the signal connection among bus interface unit 3, instruction queue 4, micro-ROM 5, arithmetic and logical unit 6, and register file 7 is very complicated. However, this connection is not related to the main purpose of this invention, so that it is shown briefly. Bank RAM 2 is connected with bus interface unit 8 in MPU 1 through dedicated high-speed bus 17. However, bank RAM 2 is controlled by MPU 1 or peripheral device 30 through bank RAM address control signal 18 which is output from bank control unit 9 in MPU 1. Bank RAM 2 is also connected with external data bus DBUS in order to exchange data with MPU 1 or peripheral device 30, in the similar manner as that of a ROM and a RAM (not shown) which are mapped on the address map of the data processing system. Bank interface unit 8 contains a current bank pointer (CBP) 10 and a previous bank pointer (PBP) 11. Current bank pointer 10 holds the data (or the address itself) indicating a particular address area of bank RAM 2, the area which is now in use as a bank in register file 7. On the other hand, previous bank pointer (PBP) 11 holds the data (or the address itself) indicating another particular address area of bank RAM 2, the area which is the return area of another bank to be recalled by register file 7 at the completion of the task under operation. Bank control unit 9 contains an adder-subtracter 25 which controls arithmetic operations between the data from current bank pointer 10 and external address bus ABUS. These operations in adder-subtracter 25 are carried out in order to find if peripheral device 30 accesses the address area of the bank, now in use by MPU 1, in bank RAM 2, as well as to transfer data between register file 7 and bank RAM 2 at a high speed using dedicated bus 17, which has the maximum data width between register file 7 and bank RAM 2. Such a high-speed data transfer takes place when bank exchange between register file 7 and bank RAM 2 is required. Because a subtraction can be carried out by an addition, an adder is used instead of said adder-subtracter 25. Usually, under the control by register file address control signal 24 output from micro ROM 5, register file 7 transfers data with MPU 1 itself, or peripheral device 30 through bank interface unit 3, which is connected with register file 7 via internal X bus 14, Y bus 15, and Z bus 16. On the other hand, in order to carry out bank exchange at a high speed according to a requirement from micro ROM 5, the data transfer between bank RAM 2 and register file 7 is controlled through bank interface unit 8. Also, according to a requirement from peripheral device 30, the data transfer between external data bus DBUS and register file 7 is controlled through bank interface unit 8. In an ordinary occasion, the data transfer between bank RAM 2 and external data bus DBUS is executed under the control by bank RAM address control signal 18 from bank control unit 9. This control by signal 18 is based on instructions obtained from peripheral device 30 through external address bus ABUS and control bus CBUS. Bank RAM 2 also has a function to connect external DBUS with dedicated high speed bus 17, when said instructions obtained through external address bus ABUS and control bus CBUS are concerned about the return area of a bank in bank RAM 2, the bank which is now in use in register file 7. Bank RAM 2 has another function to exchange data with register file 7 through dedicated high speed bus 17, when MPU 1 itself requires high-speed bank exchange. Next, the operation of the data processing system shown in Fig. 2 will be explained in the following cases: (1) the high speed data transfer between bank RAM 2 and register file 7; (2) the data transfer between bank RAM 2 and peripheral device 30; and (3) the data transfer between register file 7 and peripheral device 30. (1) In the case of a high speed data transfer between bank RAM 2 and register file 7 The high speed data transfer between bank RAM 2 and register file 7 takes place at the exchange of banks. Such exchange of banks occurs in the following situations: when an interruption occurs according to the control by a program or signals applied from outside MPU 1; when a program requires to do so; and when an original program is recalled after the completion of an interruption. In said situations, unlike a RAM and a ROM outside MPU 1, bank RAM 2 should operate in the same way that register file 7 in MPU 1 is accessed. Therefore, like register file 7, bank RAM 2 should transfer data at a very high speed which is almost the same as the operating speed of MPU 1. To that end, dedicated high speed bus 17, which has a larger bus width than that of external data bus DBUS, is used in order to transfer data at a high speed between bank RAM 2 and register file 7.Exchange of banks is controlled in order to store a bank, now in use by MPU 1, into bank RAM 2 due to the generation of interruption. Such exchange is also controlled in order to transfer a bank, to be used in an interrupt routine, from bank RAM 2 to register file 7. In actuality, when an interruption occurs, bank control unit 9 generates address information 21 for register file 7 and bank RAM address control signal 18 for bank RAM 2 in every data transfer unit one after another, so as to store banks into bank RAM 2. In this case, address information 21 and bank RAM address control signal 18 are produced in adder-subtracter 25 contained in bank control unit 9, by executing arithmetic operations on the content in current bank pointer 10. As mentioned before, current bank pointer 10 holds the data (or the address itself) indicating the address area of a bank in bank RAM 2, the bank which is now in use by MPU 1.In said case, if the interruption takes place under the control by external signals, the contents in a program status word PSW, a stack pointer PC, and previous bank pointer 11 should also be stored into bank RAM 2. As mentioned before, previous bank pointer 11 holds the data (or the address itself) indicating the return area of another bank in bank RAM 2, the bank which is to be recalled by register file 7 at the completion of the task under operation. On the other hand, in the case of interruption by program, the contents in program counter (PC), program status word (PSW), and previous pointer 11 should be stored into a stack memory.Next, the content in current bank pointer 10 is copied into previous bank pointer 11. Thereafter, according to the generation of an interruption, new bank information based on the interrupt vectors is processed to produce a new address data of bank RAM 2, the data which correspond to a new bank to be newly used in the interrupt routine. In this address of bank RAM 2, a new bank, which will be available in MPU to execute the interrupt routine, is stored. The new address information thus obtained is then transferred into current bank pointer 10.The new content in current bank pointer 10 obtained as mentioned above is processed in adder-subtracter 25 in bank control unit 9. Thus, bank control unit 9 again produces address information 21 for register file 7 and bank RAM address control signal 18 for bank RAM 2 in every data transfer unit one after another, so as to transfer a required bank from bank RAM 2 to register file 7. In this case, if the interruption occurs according to the control by a program, the content in previous pointer 11 is changed to be specially fixed data. According to these data, it is recognized that program pointer PC, program status word PSW, and previous bank pointer 11, which are required to return from the interruption, are stored not in bank RAM 2 but in the stack memory.The bank exchange by program is controlled when a programmer manages banks with intention using a subroutine. In this case, only the content in current bank pointer 10 should be changed. Therefore, in the same manner as that of the interruption process mentioned above, bank control unit 9 controls arithmetic operations to the content in current bank pointer 10 using adder-subtracter 25, according to control signals from micro ROM 5. Thus, address information 21 for register file 7 and bank RAM address control signal 18 for bank RAM 2 are produced in unit 9 every data transfer unit one after another, so as to transfer a required bank from bank RAM 2 to register file 7.The bank exchange for the return from the interruption is controlled according to a return instruction. Control signal 22 from micro ROM 5 is generated according to said return instruction. In this case, bank control unit 9 transfers the data in previous bank pointer 11 into current bank pointer 10. Thereafter, unit 9 controls arithmetic operations on the new content in current bank pointer 10 using adder-subtracter 25, and then, produces new address information 21 for register file 7 and bank RAM address control signal 18 for bank RAM 2 in every data transfer unit one after another. Thus, the bank to be recalled is transferred from bank RAM 2 to register file 7. In this case, if the interruption was made by external signals, program counter PC, program status word PSW, and previous bank pointer 11, each of which have been stored in bank RAM 2 at the generation of the interruption, are transferred into register file 7. On the other hand, in order to store the bank, which has been used in register file 7, the content in the bank should be transferred from register file 7 to bank RAM 2 using the bank exchange process by program. In the case of interruption by program, program counter PC, program status word PSW, and previous bank pointer 11 are recalled from the stack memory. (2) In the case of a data transfer between bank RAM 2 and peripheral device 30 The data transfer between bank RAM 2 and peripheral unit 30 is an indispensable function for bank RAM 2 to operate in the same manner as a RAM or a ROM which are mapped on the address map of this data processing system. In this transfer, bank RAM 2 is connected with external address bus ABUS, data bus DBUS, and control bus CBUS. In said case, however, bank RAM 2 is the body storing the data concerning about banks. Accordingly, if peripheral device 30 accesses a particular area in bank RAM 2, the area which corresponds to the bank now in use by MPU 1, it is not always true that the current content in this area is the newest information. This is because the content in the bank now in use by MPU 1 will always be restored into said area of bank RAM 2, as explained in (1). Accordingly, when said particular area, which corresponds to the bank now in use in register file, is accessed by peripheral device 30 in this embodiment, the bank exchange process (3) described below is executed between register file 7 and peripheral device 30, instead of this process (2). (3) In the case of a data transfer between register file 7 and bank RAM 2 In a usual data processing system, data transfer between a MPU and a peripheral device, such as a RAM or a ROM, which is mapped on the address map of the MPU, or between peripheral devices are controlled using external address bus ABUS, data bus DBUS, and control bus CBUS. In actuality, address and control signals output from bus interface unit 3 in MPU 1 are supplied to external address bus ABUS and control bus CBUS respectively. Then, the peripheral device responds to these signals, and then, the data transfer between peripheral devices is carried out through external data bus DBUS. When a data transfer control apparatus, such as a DMA controller, is connected to external address bus ABUS, data bus DBUS, and control bus CBUS, the data transfer between peripheral devices should be controlled by this DMA controller. Accordingly, contrary to the bank exchange request from inside MPU 1, the data transfer request from MPU 1 or the DMA controller through the external buses will be considered as the request from the periphery of MPU 1. The process (2) or (3) is executed when a peripheral device accesses bank RAM 2. In other words, either one of said operations is executed when an address to specify bank RAM 2 is supplied on external address bus and when signals contained in external control bus CBUS, such as a bus start signal, a chip select signal, and a data read-write signal, become active. The operations (2) and (3) will be explained next using one example. In this example, both current bank pointer 10 and previous bank pointer 11 have 8 bits, register file 7 has 32 bytes, external address bus ABUS has 24 bits (address 000000H to FFFFFFH, H means the hexadecimal representation), the address map of bank RAM 2 has 0 to 2K bytes (address 000000H to 0007FFH), external data bus DBUS has 16 bits, and dedicated high-speed bus 17 has 64 bits. In addition, external control bus CBUS has a bus start signal to indicate the beginning of a bus cycle, a read-write signal to indicate that data are input to or output from external data bus DBUS, and a chip select signal to activate a ROM or a RAM, which are provided around MPU 1. The 8 bit data, which are obtained by shifting the 3 bits of current bank pointer 10 to the left, are set at the higher 8 bits, and the 3 bit data '000' are set at the lower 3 bits, thus providing 11 bit data. These data indicate the lower 11 bits of the first address of an address area in bank RAM 2, the area which corresponds to the bank now in use by MPU 1. The data transfer between register file 7 and bank RAM 2 for the exchange of banks is carried out as follows. The 8 bit data, which are obtained by shifting the 3 bits of current bank pointer 10 to the left, are incremented to produce 8 byte address signals. These address signals are supplied into bank RAM 2 through bank RAM address control signal 18. Then, the data are transferred four times by 64 bit width through dedicated high-speed bus 17 between bank RAM 2 and register file 7. In this case, the address for register file 7 is incremented four times by 8 bytes. In other words, the continuous data of bank RAM 2 beginning from said 11 bit address are loaded on the bank. Said 11 bit address data are produced as follows. The 8 bit data, which are obtained by shifting the 3 bits of current bank pointer 10 to the left, are set at the higher 8 bits, and the 3 bit data '000' are set at the lower 3 bits, thus providing said 11 bit address data. Bank control unit 9 in MPU 1 monitors the lower 11 bits of external address bus ABUS and external control bus CBUS. When bank RAM 2 is accessed via the chip select signal on external control bus CBUS, adder-subtracter 25 in bank control unit 9 conducts a subtraction between the higher 8 bits of the lower 11 bits of external address bus ABUS and the 8 bits of current bank pointer 10. If the result of said subtraction is between 0 to 3, it means that the content in bank RAM 2 accessed by the peripheral device is now in use in register file 7 as a bank. If the result is not between 0 to 3, the content in bank RAM 2 accessed by the peripheral device is not in use in register file 7. When the content in bank RAM 2 accessed by the peripheral device is not in use by MPU 1 as a bank, bank control unit 9 outputs the lower 11 bits of external address bus ABUS to bank RAM 2 without a change. Also, bank control unit 9 processes the bus start signal, read-write signal, and chip select signal contained in external control bus CBUS, and then, outputs the resulting signal as bank RAM address control signal 18. Thus, the content in bank RAM 2 is transferred into peripheral unit 30 through external data bus DBUS. On the contrary, when the content in bank RAM 2 accessed by the peripheral device is in accord with the content in register file 7 which is now in use by MPU 1, bank control unit 9 outputs register file address control signal 21 to register file 7. This signal 21 is produced from external control bus CBUS and a 5 bit address signal, in which the higher 2 bits of the operation result in adder-subtracter 25 are placed in its higher part, and the lower 3 bits of external address bus ABUS are placed in its lower part. On the other hand, bank interface unit 8 connects the data bus from register file 7 with dedicated high-speed bus 17. In said occasion, bank control unit 9 also controls bank RAM 2 using bank RAM address control signal 18, so that dedicated high speed bus 17 is connected with external data bus DBUS. However, the bus width of dedicated high-speed bus 17 differs from that of external data bus DBUS. Accordingly, in order to connect high-speed bus 17 with data bus DBUS, the essential 16 bits data are taken out from dedicated high-speed bus 17 using the higher 2 bits among the lower 3 bits of external address bus ABUS. Then, said 16 bit data are made to run on external data bus DBUS. In this case, the content in bank RAM 2 is not accessed at all. As explained above, when the content in bank RAM 2 accessed by a peripheral device is in accord with the content in register file 7, which is now in use as a bank by MPU 1, the data transfer is controlled between the peripheral device and register file 7 instead of bank RAM 2. In this case, the data in register file 7 run on external data bus DBUS in the same timing as that of the access for bank RAM 2. In addition, when the content in bank RAM 2 accessed by the peripheral device is in accord with the content in register file 7, which is now in use as a bank by MPU 1, register file 7 is accessed instead of bank RAM 2. In this case, bank wait signal 23 notifies MPU 1 that register file 7 is now being accessed. Thus, the operation of MPU 1 is not influenced by said operation of the peripheral device. As explained above, the data processing system of this embodiment stores, into current bank pointer 10, of information concerning about the first address of an address area in bank RAM 2, the area which corresponds to the bank now in use in register file 7. The content in current bank pointer 10 is, then, compared with the address information which is input from peripheral device 30, so as to find if peripheral device 30 accesses a particular area in bank RAM 2, the area which corresponds to the bank now in use in register file 7, or not. As a result of said comparison, if the area in bank RAM 2 accessed by peripheral device 30 is found to correspond to the address area of the bank now in use in register file 7, data access is executed for register file 7 instead of bank RAM 2. Thus, peripheral device can always access the newest information in bank RAM 2. In summary, the control means contained in the microprocessor of this invention has a function to find if a peripheral device or the microprocessor itself accesses a particular area in an external memory, the area which corresponds to the bank now in use by this microprocessor itself, or not. In the case where said area in the external memory is accessed, the control means controls a data transfer between a register file (bank) and said peripheral device or the microprocessor itself, instead of a data transfer between said external memory (bank RAM) and said peripheral device or the microprocessor itself. As a result, the microprocessor itself or said peripheral device can access the newest information in said external memory, even in the case where said area, corresponding to the bank now in use by this microprocessor, is accessed by them. In addition, said data transfer between the register file and the peripheral device or the microprocessor can be carried out through a dedicated high speed bus. So, this invention can provide a microprocessor and a data processing system, in which the newest information in an external memory can be correctly and efficiently accessed by a peripheral device or the microprocessor itself.

Claims: A microprocessor system comprising a.1) a microprocessor (1) a.2) having a register file (7); b) an external bank memory (2) connected to the microprocessor (1) through a first bus means (17); and c) second bus means (ABUS, DBUS) for connecting the microprocessor (1) and a peripheral device (30); characterized by d) control means (12) for controlling the data transfer between the peripheral device (30) and either the bank memory (2) or the file register (7); e1) such that, if the peripheral device (30) accesses an address area in bank memory (2) which corresponds to the bank currently in use in register file (7), e.2) the control means (12) controls the data transfer between the peripheral device (30) and the register file (7); f.1) whereas, if the peripheral device (30) accesses an address area in bank memory (2) which does not correspond to the bank currently in use in file register (7), f.2) the control means (12) controls the data transfer between the peripheral device (30) and the bank memory (2). A microprocessor system as claimed in claim 1, wherein said control means (12) has a pointer (10), which holds the first address of said address area which corresponds to the bank now in use in said register file (7), and wherein said control means (12) compares the content in said pointer (10) with the address information input from said peripheral device (30) so as to find if said address area in said bank memory (2) is accessed by said peripheral device (30). A microprocessor system as claimed in claim 2, wherein said pointer (10) increases or decreases its value every data transfer unit which is selected at the maximum data width between said bank memory (2) and said register file (7). A microprocessor system as claimed in claim 2 or 3, wherein said control means (12) further has an adder-subtractor (25) or adder for performing a subtraction between a part of said address information from the peripheral device (30) and the content in said pointer (10), so as to compare said address information with the content in said pointer (10). A microprocessor system as claimed in claim 1, wherein the microprocessor comprises: a bank interface unit (8) connected to the bank memory (2) constituted as a bank RAM, through the first bus means (17) constituted as a dedicated high-speed bus, which bank interface unit (9) has a current bank pointer (10) for holding the first address of an address area in said bank RAM, which address area corresponds to the bank currently in use in said register file (7); said control means (12) is constituted as a bank control unit (9) having an adder-subtractor (25) or an adder for comparing the content of said current bank pointer (10) with address information supplied through an external address bus (ABUS) contained in said second bus means (ABUS, DBUS); and wherein said bank control unit (9) determines from the result of said comparison whether said address information corresponds to said address area in said bank RAM or not, and when it corresponds to said address area, said bank control unit (9) gives instructions to said register file (7) and said bank interface unit (8) to supply an external data bus (DBUS) contained in said second bus means (ABUS, DBUS) with the data in said register file (7) through said dedicated high-speed bus. A microprocessor system as claimed in claim 5, further comprising: a bus interface unit (3) for connecting the microprocessor (1) with the second bus means (ABUS, DBUS), an instruction queue (4); a micro ROM (5) which stores instructions for said register file (7) and said bank control unit (9); an arithmetic and logical unit (6); and internal buses (14,15,16) which connect said bus interface unit (3), arithmetic and logical unit (6), register file (7), and bank interface unit (8). A microprocessor system as claimed in claim 5 or 6, wherein said bank interface unit (8) further has a previous bank pointer (11) which holds the first address of an address area in bank RAM,, which address area corresponds to another bank used before in said register file (7).

Inventors: KAWASAKI SOICHI, KAWASAKI, SOICHI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: G06F9
IPC codes: G06F9, G06F12