Information recording and/or reproduction apparatus

Abstract: In an information recording/reproducing apparatus, a data train of 1 and 0 as recording information is precoded to be converted into a recording data train. The recording data is recorded on a recording medium. A reproduction signal from the recording medium on which the recording data is recorded is obtained by partial response waveform equalization. The recording information has at least one data change from 0 to 1 or 1 to 0 within a predetermined period.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an information recording/reproduction apparatus for reproducing an information as an (N+1)-value reproduction data train, and extracting a reproduction clock from the reproduction data train and, more particularly, to an information recording/reproduction apparatus for generating a reproduction signal by equalizing a partial response waveform. Related Background Art Conventionally, when information is recorded in an information recording/reproduction apparatus, input information is code-converted into a recording data train by a predetermined modulation method, and the recording data train is recorded as a recording signal on a recording medium. When recorded information is reproduced, a reproduction signal is compared with one slice level V 0 to discriminate data "1" or "0". The reproduction process will be described below with reference to Fig. 1. In the following description, for the sake of simplicity, an original data train to be recorded is called input information, a data train which is converted according to a predetermined code-conversion rule, and is to be input to a precoder or an NRZI converter, is called an input data train, NRZI-converted data to be actually recorded on a recording medium is called a recording data train, a signal which is reproduced from the recording medium, and is subjected to waveform equalization is called a reproduction signal, and data obtained by binarizing the reproduction signal and detected as binary data by a reproduction clock is called reproduction data. (a) of Fig. 1 shows a recording data train. A recording data waveform shown in (b) of Fig. 1 is generated according to the recording data train, and is recorded as a recording signal on a recording medium. When the recorded information is reproduced, a reproduction signal waveform shown in (c) of Fig. 1 is obtained. When the reproduction signal waveform is binarized by comparing it with the slice level V 0 , a reproduction data waveform shown in (d) of Fig. 1 is generated. (e) of Fig. 1 shows a reproduction clock, and a reproduction data train shown in (f) of Fig. 1 is detected using the reproduction clock. The reproduction clock is extracted under the PLL control using the reproduction data. Therefore, unless data bits "0" continuously appear in the recording data train, an edge is generated in the reproduction data, and the clock can be extracted from the reproduction data itself. Recently, a high density and high transfer rate are required for an information recording/reproduction apparatus. However, when a high density and high transfer rate are realized in the information recording/reproduction apparatus, inter-code interference cannot be ignored due to narrowing of the detection window width, and the apparatus becomes complicated if the interference is to be removed, resulting in an increase in cost. As a means for solving this problem, recently, a means adopting partial response is proposed. The partial response is a technique for reproducing information without removing inter-code interference by defining inter-code interference caused by transfer characteristics of a recording/reproduction system of the information recording/reproduction apparatus to be convolution of information. A reproduction system of an information recording/reproduction apparatus which adopts class 1 partial response (PR(1, 1)) will be described below with reference to the accompanying drawings. Fig. 2 shows signal waveforms of the reproduction system for an isolated bit. (a) of Fig. 2 shows a recording data train, and (b) of Fig. 2 shows a recording data waveform which is recorded on a recording medium. The recorded information is reproduced, and waveform equalization is performed, so that a reproduction signal has a reproduction signal waveform shown in (c) of Fig. 2. The bit interval of transfer data is T b , and a reproduction signal for two bits becomes 1 with respect to 1-bit data "1" when viewed from the reproduction signal. More specifically, data "1" has 1 as an inter-code interference in the next bit. Fig. 3 shows reproduction signal waveforms obtained when arbitrary data is recorded upon execution of such waveform equalization. (a) of Fig. 3 shows input data. When the input data is precoded to prevent error transmission, a recording data train shown in (b) of Fig. 3 is obtained. (c) of Fig. 3 shows a recording data waveform of this recording data train, which waveform corresponds to a signal recorded on a recording medium. When the recorded signal is reproduced, and is subjected to the above-mentioned waveform equalization, a reproduction signal shown in (d) of Fig. 3 is obtained. This reproduction signal is ternary-detected by level-slicing this signal by two slice levels V 1 and V 2 shown in (d) of Fig. 3, thereby generating a ternary data train, as shown in (f) of Fig. 3. As a result of ternary detection, when data "1" is determined in correspondence with level 1, and data "0" is determined in correspondence with level 0 or 2, a reproduction data train can be generated, as shown in (g) of Fig. 3. Note that (e) of Fig. 3 shows a reproduction clock. In the case of coding without partial response, PLL control is executed using a reproduction data signal obtained by comparing the reproduction signal with the slice level V 0 , as described above, thereby generating reproduction data synchronous with a reproduction clock. Therefore, the time interval required for the reproduction signal to cross the slice level, i.e., a change point of recording data from "1" to "0" or vice versa, e.g., as for NRZI codes, how many "0"s are present between two "1"s before NRZI conversion, determines the performance of codes in terms of controllability of PLL. However, when the above-mentioned partial response is used, if "1"s continuously appear in input data, since the level of the reproduction signal is kept at level 1, the reproduction signal crosses neither the slice level V 1 nor V 2 . This state will be described below with reference to Fig. 4. (a) of Fig. 4 shows input data. When such data including continuous "1"s is to be recorded, a precoded recording data waveform shown in (c) of Fig. 4 is obtained. When this data is recorded, is reproduced, and is then subjected to waveform equalization, a reproduction signal waveform becomes as shown in (d) of Fig. 4. As can be seen from (d) of Fig. 4, the reproduction signal waveform crosses neither the slice level V 1 nor V 2 as long as "1"s continuously appear in the data. For this reason, in a self-clock system for extracting a reproduction clock from an edge of data, a reproduction clock cannot be extracted. This problem will be discussed in more detail below. In this case, DC-free 8-9 NRZI codes will be exemplified. In the case of 8-9 NRZI codes, input information is divided into 8-bit blocks X i . For example, assume that X 1 is 01001110. A flag bit "0" or "1" is added to the beginning of each block to generate input data Y i as a 9-bit data block. In this case, the data Y i is 001001110 or 101001110. Furthermore, the data Y i is NRZI-converted into a recording data train Z i . In this case, this data conversion is performed under an assumption that the bit at the end of the immediately preceding Z i is "0". Z i is 001110100 or 110001011. As can be understood from this example, the recording data train Z i becomes bit-reversed patterns depending on the flag bit "0" or "1", and depending on this conversion result, DSV (Digital Sum Variation: a difference between the total number of data bits "0" and the total number of data bits "1" of the recording data train) of the NRZI-converted recording data bit train is calculated. The flag bit "0" or "1" is then determined, so that the DSV approaches 0. When input information is converted by this conversion rule, and the converted information is recorded, a conventional reproduction detection means can extract a reproduction clock from reproduction data itself since data bits "0" do not continuously appear in recording data. However, when the partial response is used, if input data includes continuous "1"s, since a recording data train also includes continuous "1"s, it is difficult to extract a reproduction clock from a reproduction signal for the above-mentioned reasons. IEEE Translation Journal on Magnetics in Japan, vol. 6 (1991) August, no. 8, New York, USA, pages 698-708, and an article by H. Osawa et al "Performance of Partial Response System for (2,7) RLL code", discloses a recording code wherein the data is reproduced using partial response equalization in which the reproduction signal is compared with two slice levels. This prior art reflects the preambles of claims 1 and 7. EP-A-0143553 discloses a method of deriving a digital signal having a predetermined maximum number of consecutive digital zeros. This is achieved by dividing the digital signal into blocks which are then converted into an n-bit converted code including a number of primary combinations having a DC component substantially equal to zero when NRZI-coded, and a number of secondary combinations having a DC component having a value of two when NRZI-coded. JP-A-59-094214 and the corresponding Patent Abstracts of Japan, vol. 8, no. 211 (p-303)[1648], published 26 September 1984, discloses the production of a digital signal in which the DC component is eliminated. A flag of value of either "0" or "1" is added to each block of data. The weight cumulative value DSV of the preceding block of data is calculated in order to select which flag is used. SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-mentioned problems, and has as its object to provide an information recording/reproduction apparatus and an information recording/reproduction method, which can extract a reproduction clock from a reproduction signal even when partial response waveform equalization is adopted. According to a first aspect of the present invention, there is provided an apparatus for producing a recording data train for recording on a recording medium, wherein information representative of the data is reproduced using partial response equalization in which the reproduction signal is read out from the recording medium as an (N+1)-value digital information signal, where N is an integer equal to or larger than 2, and the reproduction signal is compared with N slice levels; the apparatus being characterised by comprising means for adding a flag bit to each block of a predetermined number of binary data bits of an information data train; code conversion means for converting the information data train including the flag bits into a recording data train; and flag bit value means for causing the flag bit for each block to have a value such that the reproduction signal derived from the data bits in each block after recording information representative of the recording data train on a recording medium will cross at least one of the slice levels at least once within a predetermined period. According to a second aspect of the present invention, there is provided a method for producing a recording data train for recording on an information recording medium wherein information representative of the recording data train is reproduced by partial response equalization in which the reproduction signal is compared with N slice levels, where N is an integer equal to or larger than 2, to generate a reproduction signal having N+1 digital levels, characterised by the steps of adding a flag bit to each block of a predetermined number of binary data bits of an information data train; converting the information data train including the flag bits into a recording data train; and causing the flag bit value for each block to be such that the reproduction signal derived from the data bits in each block after recording information representative of the recording data train on a recording medium will cross at least one of the slice levels at least once within a predetermined period. Other methods and arrangements of the present invention will become apparent from the following discussion. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a chart for explaining recording and reproduction processes of a conventional information recording/reproduction apparatus; Fig. 2 is a chart for explaining the principle of partial response waveform equalization; Fig. 3 is a chart for explaining recording and reproduction processes adopting the partial response waveform equalization; Fig. 4 is a chart showing signals in the recording and reproduction processes obtained when "1"s continuously appear in input information in the partial response waveform equalization; Fig. 5 is a block diagram showing an embodiment of an information recording/reproduction apparatus according to the present invention; Fig. 6 is a block diagram showing the details of a flag bit reversing device shown in Fig. 5; and Fig. 7 is a timing chart showing the operation of the embodiment shown in Fig. 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described in detail hereinafter with reference to the accompanying drawings. Fig. 5 is a block diagram showing an embodiment of an information recording/reproduction apparatus of the present invention. Fig. 5 illustrates only an arrangement of a recording data modulation processing system as main part of the present invention. Note that this embodiment adopts 8-9 NRZI conversion as a code conversion method. Referring to Fig. 5, a flag bit adding circuit 1 adds a flag bit to input information sent from an external apparatus. In this case, input information is input in units of 8-bit blocks, and a 1-bit flag bit is added to the beginning of data of each block by the flag bit adding circuit 1. The flag bit to be added is fixed to be "0" in this embodiment. An NRZI converter 2 NRZI-converts output data from the flag bit adding circuit 1. A DSP determination circuit 3 detects a DC component (DSP; Disparity) of codes for one block in units of 8-bit blocks. More specifically, the DSP determination circuit 3 determines a difference between the numbers of data "1" and "0" in units of block data. If the number of "1"s is larger than the number of "0"s, the circuit 3 determines positive; otherwise, the circuit 3 determines negative. A flag bit reversing device 4 changes the flag bit added by the flag bit adding circuit 1 on the basis of determination results of the DSP determination circuit 3 and a DSV determination circuit 6 (to be described later). The arrangement of the bit reversing device 4 will be described in detail later. An NRZI converter 5 NRZI-converts output data from the flag bit reversing device 4 to generate recording data. The DSV determination circuit 6 detects a total DC component (DSV) of the recording data output from the NRZI converter 5. As described above, the DSV determination circuit 6 calculates a difference between the numbers of data bits "1" and "0" of a total recording data train. If the number of "1"s is larger than the number of "0"s, the circuit 6 determines positive; if the number of "0"s is larger than the number of "1"s, the circuit 6 determines negative; and if the number of "0"s is equal to the number of "1"s, the circuit 6 determines 0. Fig. 6 is a block diagram showing the detailed circuit arrangement of the flag bit reversing device 4. The flag bit reversing device 4 comprises a 9-bit shift register 7, and a positive/negative determination circuit 8 for comparing the determination results from the DSP determination circuit 3 and the DSV determination circuit 6, and determining whether or not the two determination results coincide with each other, i.e., whether or not the two positive or negative determination results coincide with each other. The device 4 also comprises a 0 determination circuit 9 for detecting the determination result of 0 from the DSV determination circuit 6. More specifically, the DSV determination circuit 6 detects a difference between the numbers of data bits "1" and "0" of total data, and determines 0 if these numbers are equal to each other. The 0 determination circuit 9 also detects the DSV of 0. The operation of this embodiment will be described below. Input information is sequentially transferred to the flag bit adding circuit 1, and a flag bit "0" is added to the beginning of each 8-bit block data. The data added with the flag bit by the flag bit adding circuit 1 is supplied to the flag bit reversing device 4, and is transferred to the 9-bit shift register 7 in units of block data (8-bit data + 1-bit flag bit). On the other hand, data output from the flag bit adding circuit 1 is also supplied to the NRZI converter 2. After the data is NRZI-converted by the NRZI converter 2, the converted data is supplied to the DSP determination circuit 3. The DSP determination circuit 3 performs DSP determination by detecting the difference between the numbers of data bits "1" and "0" in units of block data, and outputs the determination result to the positive/negative determination circuit 8 of the flag bit reversing device 4. The positive/negative determination circuit 8 also receives the determination result from the DSV determination circuit 6. More specifically, the output data from the flag bit reversing device 4 is converted by the NRZI converter 5, and the converted data is output as a recording data train. In this case, the DSV determination circuit 6 detects the DSV of total data, as described above, and outputs the determination result to the positive/negative determination circuit 8. The determination result from the DSV determination circuit 6 is also output to the 0 determination circuit 9 in the flag bit reversing device 4. If the determination results from the DSP determination circuit 3 and the DSV determination circuit 6 coincide with each other, when the flag bit has been shifted to a flip-flop, corresponding to the end bit, of the shift register 7, the positive/negative determination circuit 8 in the flag bit reversing device 4 resets the flip-flop to change the flag bit to "1". On the other hand, if the determination results from the two determination circuits do not coincide with each other, the positive/negative determination circuit 8 does not perform a resetting operation of the flip-flop, and hence, data with the flag bit "0" is supplied to the NRZI converter 5. Furthermore, the 0 determination circuit 9 monitors the determination result from the DSV determination circuit 6. If the DSV from the DSV determination circuit 6 is 0, the 0 determination circuit 9 maintains the flag bit to be 0. More specifically, in this case, the 0 determination circuit 9 supplies data with the flag bit "0" to the NRZI converter 5 independently of a coincidence or non-coincidence of the determination results from the DSP determination circuit 3 and the DSV determination circuit 6. In this manner, the flag bit of input data is changed in units of blocks based on the determination results from the DSP determination circuit 3 and the DSV determination circuit 6. Thereafter, NRZI conversion is performed, and the converted data is supplied as a recording data train to the next demodulation processing circuit. Fig. 7 shows signal waveforms of the respective units obtained when the above-mentioned flag bit changing processing is performed. Fig. 7 exemplifies a case wherein data bits "1" continuously appear in input information. (a) of Fig. 7 shows output data from the flag bit reversing device 4. As can be seen from (a) of Fig. 7, even when data bits "1" continuously appear, a bit "0" is inserted once per 18 bits since a flag bit is changed by the flag bit reversing device 4 based on the DSP and DSV determination results. Therefore, when this input data train is precoded, a recording data train shown in (b) of Fig. 7 is obtained, and furthermore, a recording data waveform shown in (c) of Fig. 7 is obtained. This recording data is recorded on an information recording medium (not shown). When the recorded data is reproduced, a reproduction signal shown in (d) of Fig. 7 can be obtained. As can be seen from (d) of Fig. 7, even when input information includes continuous bits "1", since a bit "0" is inserted once per 18 bits, the reproduction signal crosses a slice level V 2 once per 18 clocks. The obtained reproduction signal is compared with slice levels V 1 and V 2 to be converted into a ternary data train shown in (f) of Fig. 7. Furthermore, when this ternary data train is determined to be "1" in correspondence with level 1 and to be "0" in correspondence with level 0 or 2, a reproduction data train shown in (g) of Fig. 7 is generated. In this manner, according to this embodiment, when bits "1" continuously appear in an information data train over a predetermined period, the flag bit is set to be "0" on the basis of the DSP and DSV determination results, so that a bit "0" is inserted in the information data train at least once within the predetermined period. Thus, a reproduction signal can cross one of N slice levels at least once within the predetermined period. The above-mentioned embodiment exemplifies a case wherein bits "1" continuously appear in input information. However, when bits "0" continuously appear in input information, the flag bit is changed, so that a bit "1" is inserted at least once within the predetermined period. Therefore, in this case as well, a reproduction signal crosses the slice level at least once within the predetermined period. As described above, according to the present invention, even when bits "1" or "0" continuously appear in input information, since a reproduction signal crosses the slice level at least once within the predetermined period, a reproduction clock can be extracted from the reproduction signal. Therefore, the present invention allows extraction of a reproduction clock when the partial response is adopted, which extraction is difficult to achieve in the conventional method. Therefore, data reproduction by the self-clock system can be satisfactorily performed. The above embodiment exemplifies 8-9 NRZI codes. However, the present invention can be applied to other conversion rules such as 8-10 conversion. It is important to precode input data so that a reproduction signal crosses a slice level at least once within a predetermined period.

Claims: An apparatus for producing a recording data train for recording on a recording medium, wherein information representative of the data is reproduced using partial response equalisation in which the reproduction signal is read out from the recording medium as an (N+1)-value digital information signal, where N is an integer equal to or larger than 2, and the reproduction signal is compared with N slice levels; the apparatus being characterised by comprising: means (1) for adding a flag bit to each block of a predetermined number of binary data bits of an information data train; code conversion means (5) for converting the information data train including the flag bits into a recording data train; and flag bit value means (4) for causing the flag bit for each block to have a value such that the reproduction signal derived from the data bits in each block after recording information representative of the recording data train on a recording medium will cross at least one of the slice levels at least once within a predetermined period. An apparatus according to claim 1 including: DSP determination means (3) for detecting the DC component of each of the blocks of data bits; DSV determination means (6) for detecting the DC component of the recording data train; and wherein said flag bit value means (4) is arranged to change the flag bit in accordance with the DC components detected by the DSP determination means (3) and the DSV determination means (6). An apparatus according to either of the preceding claims in which the recording medium is a magneto-optical recording medium. An apparatus according to any one of the preceding claims in which the code conversion means (2) is arranged to perform NRZI code conversion. A recording apparatus including an apparatus according to any one of the preceding claims for producing a data train and means for recording the recording data train on a recording medium. A system comprising a recording apparatus according to claim 5 and means for reproducing the recording data train using partial response equalisation in which the reproduction signal is read out from the recording medium as an (N+1)-value digital information signal, where N is an integer equal to or larger than 2, and the reproduction signal is compared with N slice levels. A method for producing a recording data train for recording on an information recording medium wherein information representative of the recording data train is reproduced by partial response equalization in which the reproduction signal is compared with N slice levels, where N is an integer equal to or larger than 2, to generate a reproduction signal having N+1 digital levels, characterised by the steps of: adding a flag bit to each block of a predetermined number of binary data bits of an information data train; converting the information data train including the flag bits into a recording data train; and causing the flag bit value for each block to be such that the reproduction signal derived from the data bits in each block after recording information representative of the recording data train on a recording medium will cross at least one of the slice levels at least once within a predetermined period. A method according to claim 7 including the steps of: detecting the DC component of each of the blocks of data bits by a DSP determination means; detecting the DC component of the recording data train by a DSV determination means; and said causing step comprises determining the flag bit value in accordance with the DC components detected by the DSP determination means (3) and the DSV determination means (6). A method according to claim 7 or 8 in which the recording medium is a magneto-optical recording medium. A method according to any one of claims 7 to 9 in which the code conversion is NRZI code conversion. A recording method including a method according to any one of claims 7 to 10 for producing a recording data train, and the step of recording the recording data train on a recording medium. A recording and reproducing method comprising a recording method according to claim 11; and a step of reproducing the recording data train using partial response equalisation in which the reproduction signal is read out from the recording medium as an (N+1)-value digital information signal, where N is an integer equal to or larger than 2, and the reproduction signal is compared with N slice levels.

Inventors: HIRAMATSU MAKOTO, HIRAMATSU, MAKOTO, HIRAMATSU, MAKOTO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: G11B20
IPC codes: G11B20, G11B11, H03M5, H04L25