COMPACT LOGIC CELL FOR FIELD PROGRAMMABLE GATE ARRAY CHIP

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

Description: COMPACT LOGIC CELL FOR FIELD PROGRAMMABLE GATE ARRAY CHIP FIELD OF THE INVENTION The invention relates to programmable logic devices formed in integrated circuit semiconductor chips. More particularly, the invention relates to logic cells which are part of field programmable gate array chips. BACKGROUND OF THE INVENTION Programmable devices are currently available in several different architectures. Earliest of the programmable devices are the programmable logic array (PLA) devices which comprise a plurality of AND gates programmably connected to a second plurality of OR gates. These devices can generate any combinational logic function, because any combinational logic function can be written as a sum of products, the products being generated in the AND array and the sums being generated in the OR array. These two level logic devices (one AND level and one OR level) are simple to program, and it is easy to predict the time delay for generating an output. However, the silicon area needed to calculate a complex logic function can be undesirably large. More recently, programmable logic devices called field programmable gate arrays or FPGAs have been developed. These devices comprise an array of programmable logic cells which can be interconnected by programmable interconnect lines to generate complex logic functions. In an FPGA device, a function need not be calculated as a two-level sum of products because it is possible to feed the output of any one logic cell to an input of any other logic cell, and thereby form a chain, generating a function which has multiple levels of logic. Thus it is possible to implement complex logic in a smaller physical area. Several architectures of these field programmable logic devices are available today. The various devices differ in the complexity of a single logic cell. Some manufacturers offer devices having logic cells such as shown in Fig. 1 which are quite small (fine grained architecture) . Others offer devices having logic cells such as shown in Fig. 2 which are considerably larger and which handle larger functions within a single logic block (coarse grained architecture) . A small logic cell such as shown in Fig. 1 has the advantage of being able to be completely filled by the logic of a user, and thereby not leave unused logic resources within the cell. It may be possible to generate either combinational or sequential functions from a plurality of small logic cells. However, with fine grained architectures made up of small logic cells, it requires many logic cells to generate a complex logic function. A function which must make use of more than one logic cell must use programmable interconnect line to generate the function. When the signal path passes through resistive programmable elements, the time delay associated with capacitive and resistive interconnect line considerably slows down the response of the sequential function. The larger celled (coarse grained) logic devices can generate complex functions quickly within a single logic block. However, if the user specifies a set of functions which do not make full use of the rather large logic cell, portions of the logic cell will be unused. Also, some of the fairly large logic cells include separate resources for generating combinational functions and for generating sequential functions. The cell of Fig. 2 is such a cell. If a user wants a circuit which uses many combinational functions and few sequential functions, many sequential resources will be unused. Likewise, if the user wants many sequential functions and few combinational functions, many combinational functions will go unused. Another significant consumer of silicon faced by designers is that signals must be inverted, and using a configurable cell to generate an inverter consumes resources otherwise available for more powerful functions. Prior efforts have been made to provide dedicated hardware for the invert function. A structure described by Quicklogic in a publication entitled pASIC™ 1 Family ViaLink™ Technology Very High Speed CMOS FPGAs published May 1991 shows a programmable structure using two-input AND gates which have one inverted input and one non-inverted input. This structure thus gives a choice of applying a signal to the inverted or the non-inverted input. Though this solution allows for applying signals to both the inverted and noninverted inputs, when used simply to offer an optional inversion, this solution doubles the number of input lines needed. Thus using the above structure to achieve optional inverters adds considerable silicon area and complexity to a cell. SUMMARY OF THE INVENTION It is the goal of the present invention to provide a logic cell which is flexible, dense and fast, that is, which implements many useful functions, which allows a user's logic to be implemented in a small silicon area and which is fast at generating an output signal in response to an input signal. There are two families of digital logic functions which have different logical properties. Functions such as AND, NAND, OR, NOR can all be generated from AND gates by selectively inverting inputs and outputs. Functions such as sum-of products, product-of-sums, XOR, and XNOR can be generated from a sum-of-products function generator by selectively inverting inputs and outputs, but can not be made equivalent to functions generated from AND gates.The novel cell of the present invention offers an option between two types of functions which can not be made equivalent through inversion of inputs or outputs. The novel cell of the present invention includes an internal feedback loop which can be enabled for performing sequential functions or disabled for performing combinational functions. The internal aspect of the feedback loop avoids the delay and the resource consumption of using general interconnect for feedback. The optional aspect of the feedback loop allows high density utilization of the chip since no area is wasted by having the wrong ratio of dedicated resources for combinational and sequential functions. The cell also includes an optional feed forward connection from the output of one cell to an input of an adjacent cell. Speed of generating wide functions and certain sequential functions is enhanced by this feed-forward or cascade connection. The cell further includes optional inverters on all inputs, eliminating the need to use up more powerful programmable chip resources for the simple invert function. One embodiment of the present invention provides pumped input buffer control and pumped 3- state output control. Functions which can be generated by a single cell of the present invention include a two-input multiplexer, exclusive-or and exclusive-nor gates, a two-input sum of two- input products, a latch with clear, a set/reset latch, and two- to four-input AND functions. For any of these functions, any combination of inputs can be inverted. Larger functions can be generated by combining adjacent cells using a cascade feature discussed below. Large functions can also use the general interconnect structure which was used to form large functions with prior art cells. For example, a JK flip flop can be generated using three adjacent cells and one piece of general interconnect line. Optional Internal Feedback To form a latch, the internal feedback loop is enabled, providing the output signal from the second combinational section as input to the feedback section. An input signal is provided to the cascade section, and a clock signal selects between the two sections. Thus when the clock signal selects the feedback section, the input signal is latched into the feedback section. With this optional internal feedback loop, sequential functions may be formed without placing any programmable interconnect means or any input or output buffers in the signal path, resulting in a high speed, small implementation of a sequential function. When the feedback option is not used, the cell can generate decoders, multiplexers, or other combinational functions. Optional Cascade It is possible to combine adjacent cells for performing certain functions without inserting any interconnect means or any input or output buffer means into the signal path. The output of one cell is programmably provided as input to an adjacent cell, bypassing the input/output buffering means. This allows the designer to generate wide functions without adding significant delay beyond the delay of using a single cell. For implementing logic gates which have only one source and one destination, the improvement is valuable because the gates can be implemented in adjacent cells which are connected through the cascade path, again avoiding the input/output buffering means. Thus the gate delay can be minimized. A significant speed and density improvement is thus provided by this cascade feature. Optional Input Inverters The cell includes buffers which pass signals to and from an interconnect line. The input buffers for each input to the logic cell of the present invention are optionally inverting. This selective inversion allows the designer to use inverters without consuming resources available for other functions, and eliminates the need for output inverters. Since any number of inputs to the cell can be inverted, the cell can decode any address equally fast, and a designer can therefore rely on the time required to decode an address regardless of the ratio and arrangement of 0'ε and l's (inversions and noninversions) in the address. Also a signal which fans out from an output port and is inverted at some destinations and not others is handled easily with the present invention, because providing inverters on all inputs allows full flexibility. A combination of the cascade and inverting features allows most wide Boolean functions to be generated without using the programmable interconnects in the signal path. Logic Family Selector For selecting between logic families, the cell includes a first stage of NAND gates which receive input signals including the optional feedback and cascade signals, and provides outputs which are received by a second stage circuit which can be programmed to implement either the NOR function or the NAND function. hen set to implement the NAND function, this second stage in combination with the first stage implements functions in the sum-of-products (SOP) category. When set to implement the NOR function, the combination implements functions in the AND category. Output Buffer with High Impedance State An output buffer stage includes a high impedance capability for controlling connection of the cell output signal to an interconnect line or lines. High impedance output is useful both for electrical isolation of the logic cell from the interconnect structure (for example, during programming of antifuses in the interconnect structure) , and for logical control of the cell output when the cell output is connected to a bus. (A bus receives output signals from multiple cells but only one at a time.) Both electrical and logical isolation are accomplished by the output buffer stage. Unit for Programming Interconnect, Configuring the Cell, and Testing the Array The novel cell of the present invention is preferably one of many in an array. The cells of the array are preferably interconnected by means of a programmable antifuse interconnect structure to form a field programmable integrated circuit device. In such a device the cell includes configuration control units (CCUs) which not only store data for establishing the function of the cell, but also control the programming of the antifuse interconnect structure, and capturing array status. (The array status can be used for testing the array or debugging a design. ) The CCUs are connected together into a shift register. Additionally, each CCU controls application of voltage to one horizontal or vertical interconnect line. At intersections of horizontal and vertical interconnect lines are antifuses. By loading logical l's into two CCUs, one CCU which controls voltage to a horizontal line and one CCU which controls voltage to a vertical line, it is possible to address the antifuse at the intersection of the two interconnect lines. Then a voltage difference can be directed to the two terminals of that antifuse for programming the antifuse. This antifuse programming information is shifted through the shift register of CCUs. After all or a set of antifuses are programmed, configuration information is shifted into the CCUs to establish the configuration of the cells. These same CCUs can be used to capture the logical states of each of the interconnect lines, each CCU capturing one signal present on an interconnect line to which that CCU connects. The captured data can then be shifted out through the same shift register which initially shifted configuration information into the CCUs. Programming Technologies The invention is particularly useful for an array in which the interconnect structure is interconnected by antifuses and the cells are configured by memory cells which control pass transistors. However, the invention is also applicable to other programming technologies, and retains many of its efficiencies with the other interconnect technologies as well, including transistors, back-to-back diodes, floating gate (EEPROM) transistors, and even mask- programmed via interconnects. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art logic cell having a small cell size. Fig. 2 shows a prior art logic cell having a large cell size as used in the Xilinx 3000 series parts. Fig. 3 shows a logic cell according to the present invention. Fig. 4 shows a very small field programmable integrated circuit device made up of the cells of Fig. 3. Figs. 5A and 5B show a two-input multiplexer and its implementation using the cell of Fig. 3. Figs. 6A and 6B show an exclusive-OR gate and its implementation using the cell of Fig. 3. Figs. 7A and 7B show an exclusive-NOR gate and its implementation using the cell of Fig. 3. Figs. 8A and 8B show a sum-of-products circuit and its implementation using the cell of Fig. 3. Figs. 9A and 9B show a latch with clear and its implementation using the cell of Fig. 3. Figs. 9C shows the equivalent circuit formed by the circuit of Fig. 9B. Figs. 9D and 9E show a latch with clear having the opposite clock polarity from that of Figs. 9A-9C. Fig. 9F shows the equivalent circuit formed by the circuit of Fig. 9E. Figs. 10A and 10B show a set-reset latch and its implementation using the cell of Fig. 3. Figs. 11A and 11B show a 4-input AND gate with one inverted input, and its implementation using the cell of Fig. 3. Figs. 12A and 12B show an 8-input AND gate with some inverted inputs, and its implementation using two of the cells of Fig. 3 interconnected using the cascade feature. Figs. 13A-13C show a D flip flop and its implementation using two of the cells of Fig. 3 interconnected using the cascade feature, and latching using the feedback feature of the cells. Figs. 14A-14C show a JK flip flop and its implementation in three cells of Fig. 3, using the cascade and feedback functions to form the master-slave portions of the flip flop and a third cell connected through general interconnect to form the J and K functions of the flip flop. Fig. 15, which comprises Figs. 15A and 15B, shows a first embodiment of the cell of Fig. 3 including the configuration control units which configure the cell, and showing a first output buffer circuit. Fig. 16 shows an alternative output buffer for circuit 340 of Fig. 15A. Figs. 17A-17C show a 3-state buffer, its implementation in the cell of Figs. 15A and 15B or the cell of Fig. 16, and the equivalent circuit. Figs. 18A and 18B show a commonly used D-flipflop with a 3-state buffer on its output, and its implementation using the present invention. Fig. 19 shows a register file having read and write control lines and data lines constructed using an array of circuits of Fig. 3. Fig. 20 shows a quad output enable circuit which generates the QOE signal for controlling the output buffer circuit 340 of Fig. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The logic cell of Figure 3 comprises seven major sections: (1) a programmable input inverter stage 300, (2) a cascade-in first combinational stage 310, (3) a feedback first combinational stage 320, (4) a second combinational stage 330, (5) an output driver stage 340, (6) a selective global reset circuit 350, and (7) a set of configuration control units CCU1 through CCU7 for controlling the configuration of the cell. Overview of the Seven Sections of Fig. 3 Input buffer stage 300 comprises four input buffers 301 through 304, each of which can be inverting or non-inverting as selected by the user. Providing optional inverters at every input allows the elimination of inverters at the outputs, thus combinational logic resources never need be used simply for the purpose of inverting a signal. Cascade-in first combinational stage 310 comprises a 3- input NAND gate 311 and a 2-input OR gate 312. OR gate 312 receives a cascade enable control input 313 and a cascade input 314 from an adjacent cell. OR gate 312 provides input to NAND gate 311. Also provided as input to NAND gate 311 are outputs from selectively inverting input buffers 301 and 302. Feedback first combinational stage 320 also comprises a three-input NAND gate 321 fed by output signals from selectively inverting input buffers 303 and 304. NAND gate 321 further receives input from OR gate 322 which receives on one of its input terminals a feedback signal 332 and on another input terminal a feedback enable control input 323. Second combinational stage 330 can be programmed to provide a NAND or a NOR function of outputs from the cascade combinational stages 310 and 320. Second combinational stage 330 provides an output signal 332 which can be fed back by OR gate 322 to AND gate 321, can further be provided as a cascade OUT signal which becomes a cascade IN signal to an adjacent cell, and which is provided to output driver stage 340, where it can be driven onto the interconnect structure and used as input to other cells. Output driver stage 340 includes a buffer 341 of sufficient strength to drive the output signal onto an interconnect structure represented in Fig. 3 by interconnect lines II and 12. The connection from a cell output to an interconnect line includes means 349 for providing a high impedance to the interconnect line. That way, an interconnect line can serve as a bus, receiving signals alternately from a plurality of sources, which is a common structure in large circuits. In one embodiment a second means ISOB provides a high impedance to the interconnect line. Global reset circuit 350 allows the cell to be reset when used as a latch or flip flop. Circuit 350 includes means for pulling low the output 332 of second combinational stage 330 in response to a global reset signal. It is necessary to reset only the cells which are used as latches or flip flops in the array. Thus circuit 350 provides a reset voltage only when feedback stage 320 is configured as a latch, and only at the part of a clock cycle when the cell is latching and is not in the data receive mode. The circuit adds minimum capacitance when inactive and draws minimum power when resetting the array. Configuration control units CCUl through CCU7 are used for three purposes: first for applying programming voltages to antifuses in the interconnect structure, second for storing configuration information which configures the cell during normal operation, and third for allowing a user to capture the status of all signals on interconnect lines and shift these out of the chip to be examined by the user. As shown in Fig. 4, the cells of Fig. 3 are preferably grouped into blocks of eight cells CELL_1 through CELL_8 with a ninth cell CELL_9 comprising a plurality of CCUs. The nine cells of a block combine with an antifuse interconnect structure (antifuses are represented by black dots) which can be programmed to interconnect the cells to each other to implement a circuit design desired by a user. Four cell blocks are shown in Fig. 4. A typical integrated circuit array will comprise 100 to 1000 of these cell blocks such as shown in Fig. 4 , plus peripheral I/O circuitry, clock oscillators, and other overhead circuitry usually positioned along the perimeter of the cell. Logic implemented in each cell CELL_1 through CELL_8 is controlled by the CCUs, as discussed below. Example Implementations of the Circuits of Figs. 5A through 14A Shown in Figs. 5B through 14B Respectively Figs. 5A through 11A show some of the functions which can be implemented in a single cell of Fig. 3. Figs. 5B through 11B show the configuration control bits which are applied to the cell of Fig. 3 to implement the respective functions. It can be seen by tracing the signal path through the cell of Fig. 3 that none of the functions implemented in the cell of Fig. 3 use a signal path through an antifuse or other interconnect configuration means. Thus the cell offers fast implementation of these functions. For example, Fig. 5A shows a two-input multiplexer having two inputs INO and INI, and a select input SEL. Fig. 5B shows an implementation of this two-input multiplexer. Input INO is applied to line Al and input INl is applied to line A4. Select input SEL is applied to lines A2 and A3. A logical 0 stored in the memory cell which controls configuration control unit CCU3 causes optional inverter 301 to be noninverting. (The configuration control units are discussed in more detail below. ) Thus the value of INO is provided by optional inverter 301 to the B input of NAND gate 311. A logical 1 stored in the memory cell which controls configuration control unit CCU4 causes optional inverter 302 to invert the SEL select signal on line A2 and apply the inverted signal to the A input of NAND gate 311. The logical 0 controlling optional inverter 303 allows the SEL signal to be applied to the A input of NAND gate 321. Finally, the logical 0 controlling inverter 304 allows input INl to be passed noninverted to the B input of NAND gate 321. Three more memory cells control the cell of the invention, as represented by CCU1, CCU2, and CCU7. A logical 0 in CCU2 is inverted at the input to OR gate 312, causing OR gate 312 to apply a high signal to NAND gate 311 regardless of the signal on line 314. Thus NAND gate 311 is configured as the logical equivalent of a two-input NAND gate, as shown in Fig. 5A. A logical 0 in CCU7, inverted at the input to NAND gate 321 disables the feedback loop, so that NAND gate 321 operates as a two-input NAND gate as shown in Fig. 5A. Finally, a logical 1 in CCUl causes second combinational stage 330 to operate as a NAND gate. Recall that by deMorgan's theorem a NAND gate with inverted inputs is equivalent to an OR gate, thus NAND gates 311 and 321 in combination with NAND gate 330 form the AND gates and OR gate shown in Fig. 5A. Thus the circuit of Fig 3 configured as shown in Fig. 5B implements the multiplexer of Fig. 5A. Implementation of XOR, XNOR, Sum-of-Products of Fiσs. 6A. 7A, and 8A Shown in Figs. 6B. 7B, and 8B, Respectively Figs. 6B, 7B, and 8B show the arrangement of logical O's and l's in the seven CCUs of the cell of Fig. 3 to implement the functions shown in Figs. 6A, 7A, and 8A respectively. An understanding of these implementations can be understood from the detailed multiplexer description above. Figs. 9A through 9F: Latch with Clear and Solution to Static Ones Problem Fig. 9A shows a latch with clear which can be implemented by the circuit of Fig. 3. Fig. 3 can be configured several ways to implement the static latch, however only one method will be described. As shown in Fig. 9B, the D (data) input of Fig. 9A is provided on line Al of Fig. 3. Latch enable signal LE of Fig. 9A is applied to lines A2 and A3. Optional inverter 302 is set to be inverting and optional inverter 303 is set to be noninverting. The Reset input of Fig. 9A is provided to line A4. Feedback control unit CCU7 stores a logical 1 which enables the feedback path by applying a logical 0 to the C input of OR gate 322. The Q output signal is thus fed back through the D input of OR gate 322 to NAND gate 321. AND gates ANDl and AND2 and OR gate ORl of Fig. 9A are achieved (according to DeMorgan's theorem) by configuring second combinational stage 330 as a NAND gate. Fig. 9D illustrates a latch with clear in which the latch enable signal LE has the opposite polarity of that in Fig. 9A. Both polarities are needed when sequential latches are needed, for example in a flip flop. Fig. 9E shows the implementation of the latch of Fig. 9D in the Fig. 3 circuit, and Fig. 9F shows the equivalent circuit which results. Optional inverter 302 is configured to pass the LE signal through to the A input of NAND gate 311 and optional inverter 303 is configured as an inverter, passing the complement of A3 to the A input of NAND gate 321. In the circuit of Figs. 9A through 9C, the input signals are the data input signal D and the latch enable signal LE. Set/Reset Latch Fig. 10A shows a set/reset latch which can be implemented as shown in Fig. 10B using the cell of Fig. 3. 4-Input AND Gate Figs. 11A and 11B show a 4-input AND gate with one inverted input, and its implementation using the cell of Fig. 3. Note that second combinational stage 330 is configured as a NOR gate by a logical 0 from CCUl. With the two inverted inputs (the inverted outputs of NAND gates 311 and 321) second combinational stage provides the AND function. In the example of Fig. 11A, the A2 input is inverted. Therefore, a logical 1 in CCU4 causes optional inverter 302 to act as an inverter. Clearly any combination of inverted inputs may be selected. Example Wide AND Function, Figs. 12A and 12B Using Cascade Fig. 12A shows an 8-input AND gate with inputs A2 , A3, A6, and A8 inverted. As shown in Fig. 12B this 8-input AND gate is implemented using two cells of Fig. 3 connected using the cascade feature. Users may cascade more than two adjacent cells together to form wider or larger functions. Lines Al through A8 provide the eight inputs, while the AND function is provided as the X output. The logical 0 in cascade-in control unit CCU2a causes cell 7a to ignore the signal on line 314a. Optional inverter 301a is caused by a logical 0 in CCU3 to provide a noninverted version of Al . Optional inverter 302a is caused by the logical 1 in CCU4a to invert the A2 signal. Logical l's at CCU5a, CCU4b, and CCU6b also cause inversion of A3, A6, and A8. Feedback control unit CCU7a provides a logical 1, which causes 320a to ignore Q output signal 332a. The logical 0 control signal from control unit CCUla causes second combinational stage 330a to provide the NOR function of stages 310a and 320a. Thus, by deMorgan's theorem, the output signal placed on line 332a is the AND function of Al through A4. Configuration control unit CCU2b carries a logical 1, which causes the cascade 332a output signal from cell 7a to be provided as input D to cascade unit 310b of cell 7b. Thus cascade unit 310b provides the NAND function of three inputs, A5, A6, and the AND output of cell 7a. Importantly, the AND output of cell 7a arrives at the input of cascade unit 310b without passing through any programmable interconnect. Thus this cascade connection reduces delay as well as saving interconnect resources. Cell 7b also has a logical 0 in CCUlb and CCU7b. The result is that the output B2 of cell 7b is an AND function of eight inputs Al through A8. In particular, B2 = Al * A2~ * A3~ * A4 * A5 * " A * A7 * A8~ Though the cascade path connecting output line 332a to cascade-in line 314b avoids the delay of output buffer 340a and input buffer 300b, nevertheless for maximum speed of the system using a wide AND gate such as implemented in Fig. 12B it is preferable to apply signals requiring minimum delay to inputs A5-A8 because these signals will not have to be processed through two cells before reaching the output at B2. Because an extra cascade-in input signal can be used, it is not necessary to use one of the inputs A5-A8 to receive the output from 332a (the AND function of A1-A4) to compute an AND function. Thus two cells having four inputs each can be used to calculate an 8-input AND (or other) function. Without the cascade path, not only would the performance be slower and some of the interconnect resources be used up, but the two cells with together 8 inputs could only calculate a 7-input function because one input would be required for forwarding the output of the first stage. Example D Flip, Flop Figs. 13A-13C Figs. 13A, 13B, and 13C show a D flip flop and its implementation in Fig. 3. This flip flop uses two of the cells of Fig. 3, each indicated by one of the dotted lines 7a and 7b. The flip flop is formed by cascading two transparent latches; in this case, the latch of Figs. 9A-9C forms the master while the latch of Figs. 9D-9F forms the slave. The implementation shown is only one of several ways available with a pair of cells as in Fig. 3. The D input of Fig. 13A is provided on line Al of Fig. 13B. Clock input CK of Fig. 13A is provided on lines A2 , A3, A6 and A7 , and is inverted by buffers 302a and 303b but not by buffers 303a or 302b. Reset input R is provided on lines A4, A5, and A8, and inverted by all three of buffers 304a, 301b, and 304b. In both cells, second combinational stages 330a and 330b are configured as NAND gates. Cascade enable unit 312b carries a logical 1, enabling the output signal on line 332a from the master section of the flip flop to be passed by OR gate 312b to NAND gate 311b. Logical 1 signals from feedback control units CCU7a and CCU7b enable the internal feedback paths. Thus the circuit of Fig. 13B formed from two cells of Fig. 3 implements the D flip flop of Fig. 13A. This circuit is formed from two cells connected by a direct connect path without using the general interconnect structure, and therefore the signal path does not pass through any input or output buffers or any programmable interconnect means. Example JK Flip Flop. Figs. 14A-14C Figs. 14A-14C show a JK flip flop and its implementation. This flip flop uses three of the cells of Fig. 3, each indicated by one of the dotted lines 7a, 7b, and 7c of Fig. 14B. Cells 7b and 7c implement a D flip flop, and are configured similarly to cells 7a and 7b of Fig. 13B. Cell 7a implements a multiplexer as in Figs. 5A- 5C. Connection of the multiplexer to the D flip flop occurs through the cascade connection between cells 7A and 7B as caused by the 1 in CCU2b. However a connection L7 between the first and last cells is also needed to feed the Q output back to cell 7a, and is formed using the general interconnect. Therefore general interconnect line L7 is programmably connected to output line B3 of cell 7c at programmable interconnect 171, and to cell 7a at input lines A2 and A3 at programmable interconnects 172 and 173. As with other examples, the 0's and l's in each of the CCUs shows the configuration of each part of each cell to achieve the JK flip flop of Fig. 14A. Detail of Output Buffer Stage 340 Output buffer stage 340 preferably comprises plural means for providing a high impedance output signal X. Electrical isolation during antifuse programming and logical isolation during cell operation are both provided by output buffer stage 340. Electrical Isolation. First Embodiment. Using Isolation Transistor Fig. 15, comprising Figs. 15A and 15B, shows one embodiment of the cell of the present invention. Elements of Fig. 15 which correspond to elements of Fig. 3 are given the same reference numerals. Fig. 15A, shows the detail of one embodiment of output driver stage 340, which comprises buffer 341 and high impedance control unit 349. In a first embodiment, shown in Fig. 15A, electrical and logical isolation are controlled separately. An electrical isolation transistor 342 is positioned adjacent the interconnect line for the purpose of isolating transistors 343 and 344 from the high voltages present on the interconnect structure during programming of antifuses in the interconnect structure. Transistor 342 allows transistors 343 and ' 344 to be of minimum channel length when used with an antifuse interconnect structure programmed at higher voltage. Transistor 343 is a P-channel transistor, thus it must be isolated from the interconnect structure during antifuse programming. This is because the interconnect structure must receive a 10-volt signal (or other programming voltage) during programming, but the P-N junction between the drain and substrate of transistor 343 would create a forward-biased diode which would pull down the interconnect voltage and prevent the programming voltage from being applied. Isolation transistor 342 can be turned off from a global control source ISOB. Transistor 342 remains on during normal operation of the device. During operation, the voltage on the control terminal of transistor 342 is pumped above the supply voltage so that the full rail-to-rail voltage swing of the logic signal on line 332 propagates through transistor 342. Thus a full rail-to-rail voltage swing is available to the input of a next cell in the logic design. Electrical Isolation, Second Embodiment, No Isolation Transistor Fig. 16 shows another embodiment of the output buffer 340 used with an antifuse interconnect structure having reduced interconnect voltage. In the embodiment of Fig. 16, no isolation transistor 342 is provided. Both electrical isolation and logical high impedance are provided by a pair of N-channel pull-up and pull-down transistors 363 and 364. Logical Isolation In either embodiment (Figs. 15A and 15B or Fig. 16), for logical control during cell operation, the cell can operate as a 3-state buffer, or the cell can perform a selected function and the high impedance state can be controlled by an enable signal QOE. This QOE enable signal preferably controls multiple cells and can be used for controlling multiple cells connected to a bus. Referring to Fig. 15A, during operation of the cell, transistors 343 and 344 can simultaneously be turned off by a high signal from high impedance control unit 349. On the other hand, a low output signal from control unit 349 allows the Q output signal on line 332 to determine which of transistors 343 and 344 will be on and therefore which of power and ground will be supplied through transistor 342 as output signal X. The second embodiment operates in an analogous manner. Configuring the Cell as a 3-State Buffer NAND gate 348 decodes a particular combination of configuration control signals, preferably a combination not otherwise used to set up a useful configuration, and causes the output buffer (transistors 343 and 344) to provide high impedance output in response to a data signal when this combination of configuration signals is present. In the embodiment shown in Fig. 15A and 15B, when the logic cell is configured for sequential functions, the output of CCU7 is a logical 1. A pair of input lines, one for each of sections 310 and 320 are used to provide clock signals of opposite polarities. For example, A2 and A3 may be connected to provide a clock signal and opposite values loaded into CCU3 and CCU4 such that one of optional inverters 302 and 303 is inverting and one is noninverting. Since the outputs of CCU4 and CCU5 are always of opposite polarity, the combination decoded by NAND gate 348 is not otherwise used. NAND gate 348 receives three configuration control signals from configuration control units CCU4, CCU5, and CCU7, and one enable signal from selective inverter 304. NAND gate 348 generates a low output signal (generating a high impedance output) in response to one condition, namely when outputs of CCU4, CCU5, and CCU7 as well as the output of optional inverter 304 are all logical 1. Thus this combination of configuration signals configures the cell to be a 3-state buffer. NAND gate 348 provides high impedance control of the individual cell without requiring a separate input signal to the cell. In the embodiment of Fig. 15A and 15B, the 3-state buffer configuration is invoked by configuration signals indicating that a sequential function is to be used (CCU7 holds a logical 1) and that both of the signals on lines A2 and A3 (normally used for clock signals) are to be inverted. NAND gate 348 decodes this combination of configuration signals and causes the cell to respond to an input signal on line A4 which enables or disables the high impedance state. Other combinations of configuration signals can alternatively be used to invoke a high impedance output. Implementation of Logic Cell as 3-State Buffer Figs. 17A through 17C show an implementation of the logic cell as a 3-state buffer. Fig. 17A shows the 3-state buffer circuit. Fig. 17B shows its implementation in the circuit of Fig. 15A and 15B or the circuit of Fig. 16. Fig. 17C shows the equivalent circuit formed by the circuit of Fig. 17B. Input signal IN is applied to line Al and a logical 0 in configuration control unit CCU3 makes optional inverter 301 noninverting so the input signal passes to NAND gate 311. Lines A2 and A3 are tied to ground, and logical 1 in configuration control units CCU4 and CCU5 sets them both to be inverting. The enable signal EN is applied to line A4, and CCU6 is set by a logical 1 to be inverting. (With an active low enable signal, CCU6 would be set by a logical 0 to be noninverting.) The logical 1 in CCU7 in combination with logical l's in CCU4 and CCU5 enable NAND gate 348 to respond to the EN signal output from inverter 304. Thus when EN is low, the high impedance state is enabled, and when EN is low the signal IN is passed to output line X. The signal to be buffered is a function of an input signal on line Al, and the 3-state control is provided on line A4. Thus the circuit of Fig. 17C performs as shown in Fig. 17A. The feedback of the Q output signal occurs as a side effect of the implementation and has no effect on the 3-state output signal X. Since the particular combination of configuration states in CCU4, CCU5 and CCU7 does enable the feedback, configuration unit CCUl must be set to logical 1 (NAND) so that the cell will feed through the IN signal when output is enabled. The novelty here is the detection of unused CCU configuration patterns to provide a 3-state buffer with minimal additional use of resources. Example Application of the Cell as 3-State Buffer Figs. 18A and 18B show a commonly used circuit and its implementation. Fig. 18A shows a D-flipflop with a 3-state buffer on its output. As shown in Fig. 18B, three adjacent logic cells 22a through 22c are used in this implementation. Cells 22a and 22b form the master and slave portions of the D- flipflop and cell 22c forms the 3-state buffer. Note that the cascade feature is used to connect the flip flop Q output to the 3-state buffer input. Grouped 3-Stating Capability In addition to the ability to configure an individual logic cell as a 3-state buffer, the present invention provides the ability to disable groups of logic cells using a single 3-state control line. This allows the cells in the group to be configured to perform any selected function while at the same time allowing 3-state control of the cell outputs without using additional cells for the 3-state control. Returning to Fig. 15A, NAND gate 346 causes transistors 343 and 344 to provide a high impedance in response to either the low signal from NAND gate 348 or a low output enable signal QOE. The QOE signal allows the cell to be configured to generate a desired logic function, and for the function output to be placed on a bus when selected. As shown in Fig. 4, the logic cells are grouped into blocks of eight cells, four cells CELL_1 through CELL_4 above and four cells CELL_5 through CELL_8 below. A single QOE signal enables four cells simultaneously. Cells CELL_1 through CELL_4 are enabled by one QOE signal and cells CELL_5 through CELL_8 are enabled by another QOE signal. The QOE signal lines are shown more clearly in Fig. 27, which comprises Figs. 27A through 27J. The QOE signals are generated in cell CELL_9 , which comprises a plurality of configuration control units. Fig. 20 shows a circuit in cell CELL_9 for generating a QOE signal. NOR gate NOR13 receives a global 3-state signal GTS and a selectable input signal. A high global 3-state signal GTS always causes the QOE signal to place a high impedance on the cell outputs. When GTS is low, the QOE signal is a selectable function. The circuit shown in Fig. 20 selects between a signal on interconnect line Ii and a constant signal, shown as ground, as controlled by configuration control unit CCU13, and selectively inverts the signal, as controlled by configuration control unit CCU14. Since each QOE line controls four logic cells, logic cells which are controlled by the same QOE line should be used to implement bits of the same word (addressed by the same read and write enable lines) . Use of Grouped 3-Stating Capability for Reading Registers An example of the usefulness of this feature is a register file. Fig. 19 shows a register file having read and write control lines and data lines. One 5-bit bus carries three address lines A 0 -A 2 , one write enable line WE, and one read enable line RE. Fig. 19 represents 8 columns of cells, columns 0 through 7 for storing 8 words. In this case three address bits A 0 -A 2 address the eight columns. AND gates ANDWO through ANDW7 in the eight columns are each programmed to decode different addresses. (See Figs. 11A- lie and 12A-12C for discussion of configuring a cell as an AND gate and inverting selected inputs.) In response to a high WE signal and an address matching that programmed into AND gate ANDWO, output of AND gate ANDWO on output line WRITE_WORD0 enables data on lines D 0 through D n to be written into respective latches LOO through LOn. The grouped 3- stating capability is useful for the reading operation. For reading, 3-state buffers TOO through TOn are controlled by the signal READ_WORD0 and, in response to a high READ_WORD0 signal, place data from latches L00 through LOn onto data lines D 0 through D n . The QOE feature allows both the latch and the tristate buffer to be implemented in a single logic cell. The circuit of Fig. 19 can be effectively implemented with the cell of the present invention using the high impedance buffer control unit 349 of Fig. 15A. A cell such as shown in Fig. 15A will be called one logic cell. Each latch and its 3-state output buffer is implemented in one logic cell. Each write enable gate ANDWO through ANDW7 is implemented in one logic cell and each read enable gate ANDRO through ANDR7 is implemented in one logic cell. To implement such a circuit, antifuses in the interconnect structure are programmed to form the lines shown in Fig. 19. The AND gates are formed as discussed above in connection with Figs 11A and 11B. The latches are formed as discussed in connection with Fig. 9B. Making use of one of the 3-state output controls of Fig. 15, namely the QOE signal, 3-state output buffers TOO through T7n of Fig. 20 are implemented. Detail of Global Reset Stage 350 Stage 350 comprises series transistors including global reset transistor 351, transistor 352, and NOR gate 353. A global reset signal GRST is provided to every cell, and will be received regardless of the configuration of the cell. The selectivity comes from controlling transistor 352 from the same configuration control unit which controls whether feedback will be provided, that is, the control unit which controls whether the latch feature of the cell will be used. Only when the cell is used as a latch will a reset signal be applied to line 332. Further, even if the cell is being used as a latch, the master or slave which is not in the latched mode does need to be reset to override the current value. If a global reset signal were received when the clock signal was causing line 332 to receive the D input signal provided on line Al, and the D input signal were logical 1, a contention between the pull-up provided by combinational stage 330 (a logical 1) and the pull-down provided by reset stage 350 connecting line 332 to ground (the reset signal) would draw high current during the time the reset signal is present. Thus it is not desirable to provide a reset signal when line 332 is forwarding the D input signal. In a D flip-flop comprising two connected D latches (as in Fig. 13B) , at a given clock level, one latch will be transparent while the other will be latching. The GRST signal will reset only the latch which is in its latched state (when the output of optional inverter 302 is low) . When the master (Fig. 13B, cell 7a) is latched, it will be reset, and this low value will propagate through the transparent slave to the output. When the slave (Fig. 13B, cell 7b) is latched, it will be reset, causing the output to go low. Thus in the cell of Fig. 3, when the cell is in the feedback (latch) configuration, a logical 1 GRST signal to all transistors 351 of the array allows circuit 350 to pull line 332 to ground in those cases where reset is necessary and not when unnecessary or when power drain would be high. NOR gate 353 assures that transistor 352 turns on only when necessary, and thus a selective reset for latch and flip flop configurations is achieved. The global reset signal is preferably applied to transistor 351 adjacent line 332 because during most of the operation of the circuit, the global reset signal is off (logical low) , and the capacitance added by circuit 350 is only that of one source/drain region of transistor 351. Other embodiments of the invention will become obvious to those skilled in the art in light of the above description. These other embodiments are intended to fall within the scope of the present invention.

Claims: CLAIMS 1. A programmable logic cell comprising: means for receiving a plurality of input signals and providing an output signal; means for generating two functions of said input signals, said two functions being functions which can not be made equivalent by inversion of selected input signals or output signals; and a function selector which selects between said two functions and causes a selected one of said two functions to be provided as said output signal. 2. A programmable logic cell as in Claim 1 in which said two functions are the AND function and the sum-of-products function. 3. A programmable logic cell as in Claim 2 in which said means for generating two functions comprises: two NAND gates, each of which receives some of said inputs and generates intermediate output signals; and a gate which receives said intermediate output signals, which can be programmed as a NAND gate and a NOR gate, and which generates said output signal. 4. A programmable logic cell as in Claim 1 further comprising: means for controlling whether one of said input signals is applied to a first one of said NAND gates; and means for controlling whether said output signal is applied as another one of said input signals to a second of said NAND gates. 5. A programmable logic cell as in Claim 4 in which: said means for controlling whether one of said input signals is applied to said first NAND gate and said means for controlling whether said output signal is applied to said second NAND gate each comprises a two-input OR gate, one input receiving said input or output signal and one receiving a signal from a configuration control memory means. 6. A programmable logic cell as in Claim 5 in which each of said configuration control means is a memory cell connected as part of a shift register. 7. A programmable logic cell as in Claim 5 in which each of said configuration control means is a line which is programmably connected to a high or low voltage supply. 8. For an array of configurable logic cells each of which can perform both combinational and sequential logic, a reset control circuit comprising: an optional feedback loop (332, 322); means (CCU7) for enabling said optional feedback loop; means (350) for connecting said feedback loop to a reset voltage; means (GRST) for supplying a reset control signal; means for controlling said means for connecting comprising: means (353) for enabling said means for connecting only when said means (CCU7) for enabling said optional feedback loop is enabled and said reset control signal (GRST) is provided. 9. A reset control circuit as in Claim 8 in which each of said logic cells comprises: means for receiving a clock signal, said clock signal causing said logic cell to switch modes between a transparent mode and a latch mode when said feedback loop is enabled; and said means for controlling further comprises: means for enabling said means for connecting only when said clock signal is causing said logic cell to operate in a latch mode. 10. A programmable logic cell comprising: means for performing a selected logic function; an output buffer (340); and means (CCU1-CCU7, 348) for configuring said logic cell to provide a high impedance output or to provide said selected logic function. 11. A programmable logic cell as in Claim 10 in which said means for performing a selected logic function comprises: a plurality of logic units (300, 311, 321, 330), each of which can be configured to perform a selected unit function of at least one input signal, said units being connected together such that said selected unit functions cause said logic cell to perform said selected logic cell function. 12. A programmable logic cell as in Claim 11 further comprising: means (CCU1-CCU7) for configuring each of said units to perform said selected unit function. 13. A programmable logic cell as in Claim 12 in which said means for configuring said output buffer to provide a high impedance output comprises: a logic gate (348) having a plurality of inputs and providing an output signal which in a first state causes said logic cell to provide a high impedance output and in a second state does not cause said logic cell to provide a high impedance output; means for providing as input to said logic gate at least one signal from at least one of said means for configuring each of said units (CCU4, CCU5, CCU7) ; and means for providing as input to said logic gate at least one signal related to one of said input signals (13); whereby said logic gate assumes said first state in response to one combination of said at least one signal from one of said means for configuring each of said units and said at least one signal related to one of said input signals. 14. A programmable logic cell comprising: first and second programmable logic units, each having a plurality of input terminals for receiving input signals and each having an output terminal for providing an output signal; and a third programmable logic unit having two input terminals and an output terminal, said input terminals receiving signals from said output terminals of said first and second programmable logic units, comprising: means for calculating the NAND function of signals on said output terminals of said first and second programmable logic units, means for calculating the NOR function of signals on said output terminals of said first and second programmable logic units, and means for selecting between providing on said output terminal of said third programmable logic unit said NAND function and providing on said output terminal said NOR function.

Inventors: GOETTING F ERICH, PARLOUR DAVID B, TRIMBERGER STEPHEN M, GOETTING, F., ERICH, PARLOUR, DAVID, B., TRIMBERGER, STEPHEN, M.
Applicants: XILINX INC, XILINX, INC.
Application year: 1993
Main classification: H03K19
IPC codes: H03K3, H03K19