METHOD OF AND CIRCUIT FOR CORRECTING ERRORS

Abstract: After calculation of syndrome by use of syndrome registers [S0 to S3] (15 to 18), the value of the syndrome register (15) is loaded in the syndrome registers (16 to 18), and the values of the syndrome registers (16 to 18), in the data registers [R1-R3] (22 to 24), respectively, when there is a singlet error. By use of the syndrome registers (15 to 18), power operation of µ, µ², and µ³ is repeated until coincidence detection circuits (25 to 28) detect coincidence of the values of the syndrome registers (15 to 18) with the data registers (22 to 24). A counter (29) is operated in synchronism with the power operation. When the coincidence is detected, the count value is defined as the location of data which includes an error. The error is corrected by assuming the value of the syndrome registers [S0] (15) to be its magnitude.

Description: The present invention relates to an error correction method and an error correction circuit and, particularly to an error correction method and an error correction circuit for use in error correction in digital data processing apparatus, such as reproducing apparatus for reproducing a CD (compact disc) and a DAT (digital audio tape) or the like. An error correction code of CD is formed by interleaving 2-stage Reed-Solomon codes and referred to as CIRC (Cross Interleaved Reed-Solomon Code). The 2-stage Reed-Solomon codes used in the CIRC are referred to as C1, C2, respectively. When error is corrected by the C1 code, for example, error-correction is carried out at the unit of 32 byte-data in which 4-byte parity data are added to 28-byte data. The 32-byte data are referred to as x 0 to x 31 , respectively. 4-byte parity data are selected such that all of four equations on [Equation 1] yield "0"s: Data thus generated are recorded on the disc, and recorded data contains error due to various causes when reproduced. Data (data containing errors) received by an error correction circuit after they had been read out from the disc are respectively referred to as x 0 ' to x 31 ' in order that they can be distinguished from data recorded on the disc. When error correction is implemented in actual practice, data is received and then syndromes S0 to S3 are calculated based on [Equation 2]: Galois field theorem proved that there exists a finite field having 2 8 elements. This finite field is expressed as GF(2 8 ). Codes used in the CD are defined by generator polynomial on [Equation 3]: P ( x ) = x 8 + x 4 + x 3 + x 2 + 1 Then, α is a root of equation established when P(x) = 0. Study of [Equation 2] reveals that, if received data contains no error, then S0 = S1 = S2 = S3 = 0 (parity data are added for this reason). Conversely, if any one of syndromes were not "0", data error could be detected. Although the syndrome should be calculated based on the [Equation 2] prior to the error correction, if the syndromes were calculated as described above, then the number of calculation would be increased. Therefore, [Equation 2] is modified as [Equation 4]: The syndrome S1, for example, can be calculated in accordance with an algorithm shown in FIG. 3. Other syndromes S0, S2, S3 also can similarly be calculated by changing a predetermined power of α variously. This calculation can be implemented by a circuit composed of an adder 41 supplied at one input thereof with received data, a register 42 for storing added data from the adder 41 and a multiply-by-power a circuit 43 for multiplying data stored in the register 42 with power α and supplying multiplied data to the other input of the adder 41 as shown in FIG. 4. In FIG. 4, received data are input to the circuit in the sequential order from the data x 31 ' under the condition that the register 42 is reset. Then, the value that was generated from the register 42 when the data x 0 ' is input becomes the value of the syndrome S1. Because the syndromes S0, S2, S3 are required in actual practice, as shown in FIG. 5, the syndromes are calculated by four registers 42 0 to 42 3. The multiply-by-power α circuit 43 and the adder 41 can easily be realized by a combination of exclusive-OR (EX-OR) gates based on features of Galois field as shown in FIGS. 6 and 7. It is important to detect an error amount prior to the error correction. Also, up to 2-byte error can be corrected in the code used by the CD. Heretofore, calculation for determining an error amount (0-byte, 1-byte and 2-byte or larger) is carried out after calculation of the syndromes was finished. If the received data x i ' is erroneous by an error amount e i ', then the syndromes expressed by [Equation 5] are to be calculated as will easily be understood from the parity data structure. The error amount e i and an erroneous received data location i are calculated from the syndromes thus calculated. Since the four equations of [Equation 5] has two unknowns, these equations can be solved with ease, e.g., based on [Equation 6]: However, if received data had 2-byte error or greater, the received data would be corrected erroneously. Therefore, e i α 2i and e i α 3i should be calculated by using α i and e i obtained from [Equation 5]. Then, it is necessary to confirm whether or not the calculated results are agreed with the syndromes S2, S3 of [Equation 5]. As described above, the conventional error correction circuit based on the above-mentioned algorithm should carry out at least one division and two multiplications when 1-byte error is corrected. These calculations are those that are carried out on the Galois field. Since it is customary that, when the multiplication and the division are carried out on the Galois field, number to be calculated is modified in the form of power of α, it is necessary to use a ROM in which a table of exponents and a table of logarithms for such modification are stored. Moreover, a peripheral circuit becomes complex in circuit arrangement and a circuit scale is unavoidably increased. In view of the aforesaid problem, it is an object of the present invention to provide an error correction method and an error correction circuit in which error detection and error correction can be realized by a circuit arrangement of an extremely small circuit scale. Japanese Patent Application Publication No. JP-A-4029414, a short English language abstract of which appears at DATABASE WPI Week 92/11, Derwent Publications Ltd. London, GB; AN 92-085655, JP-A-4029414, NAT. SCI. COUNCIL 'Decoding Cyclic Codes' discloses an error correction method according to the pre-characterising part of claim 1 hereof and an error correction circuit according to the pre-characterising part of claim 2 hereof. According to a first aspect of the present invention there is provided an error correction method comprising the steps of: calculating n syndromes from received data, n being a positive integer determined by a number of parity words contained in said received data, and storing a single syndrome in a single syndrome register, said single syndrome representing an error amount if error is a single-error, and storing other syndromes in n-1 syndrome registers; characterised by the following steps: after calculation of syndromes is ended, loading the values stored in said n-1 syndrome registers into n-1 data registers and loading the value stored in said single syndrome register into all of said n-1 syndrome registers; multiplying the contents of each of the n-1 syndrome registers by a power of α such that the i th syndrome register is multiplied by α i , where i is an integer from 1 to n-1 and α is a root of a generator polynomial on Galois field; repeating this multiplication step until it is detected that the value stored in each of the n-1 syndrome registers is equal to the value stored in the respective n-1 data register; incrementing a count each time the above multiplication step is performed whereby, if the value of the count is greater than the length of the received data, the error is uncorrectable, otherwise, once no more multiplication steps are performed, the value of the count is equal to the location of a single error in the received data and the value in said single syndrome register is equal to the error amount; and effecting error correction based on said error location and said error amount. According to a second aspect of the present invention there is provided an error correction circuit comprising: means for calculating n syndromes from received data, n being a positive integer determined by a number of parity words contained in said received data, and storing a single syndrome in a single syndrome register, said single syndrome representing an error amount if error is a single-error, and storing other syndromes in n-1 syndrome registers; characterised by means for implementing the following steps: after calculation of syndromes is ended, loading the values stored in said n-1 syndrome registers into n-1 data registers and loading the value stored in said single syndrome register into all of said n-1 syndrome registers; multiplying the contents of each of the n-1 syndrome registers by a power of α such that the i th syndrome register is multiplied by α i , where i is an integer from 1 to n-1 and α is a root of a generator polynomial on Galois field; repeating this multiplication step until it is detected that the value stored in each of the n-1 syndrome registers is equal to the value stored in the respective n-1 data register; incrementing a count each time the above multiplication step is performed whereby, if the value of the count is greater than the length of the received data, the error is uncorrectable, otherwise, once no more multiplication steps are performed, the value of the count is equal to the location of a single error in the received data and the value in said single syndrome register is equal to the error amount; and effecting error correction based on said error location and said error amount. The invention will now be further described, by way of illustrative and nonlimiting example, with reference to the accompanying drawings, in which: FIG. 1 is a block diagram showing an error correction circuit according to an embodiment of the present invention; FIG. 2 is a flowchart of an error correction algorithm used in the circuit according to the embodiment of the present invention; FIG. 3 is a flowchart of a calculation algorithm of syndrome S1; FIG. 4 is a block diagram showing an example of a calculation circuit for calculating syndrome S1; FIG. 5 is a block diagram showing an example of a calculation circuit for calculating syndromes S0 to S4; FIG. 6 is a block diagram showing an example of a multiply-by-power α circuit; and FIG. 7 is a block diagram showing an example of an adder which carries out addition on the Galois field. An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an error correction circuit according to an embodiment of the present invention. In FIG. 1, received data RD is supplied to each one input of four adders 11 to 14. Respective added data from these adders 11 to 14 are stored in four syndrome registers [S0 to S3] 15 to 18 that are used to calculate syndromes S0 to S3. The syndrome registers 15 to 18 are operated in synchronism with a clock CK supplied thereto. Respective data stored in the syndrome registers [S1 to S3] 16 to 18 of the four syndrome registers 15 to 18 are supplied through a multiply-by-power a circuit 19, a multiply-by-power α 2 circuit 20, a multiply-by-power α 3 circuit 21 to other inputs of the adders 12, 13, 14 and also stored in three data registers [R1 to R3] 22 to 24, respectively. Respective data stored in the data registers [R1 to R3] 22 to 24 are supplied to each one of inputs of three logic gates 25 to 27. These logic gates 25 to 27 are supplied at their other inputs with respective data stored in the syndrome registers [S1 to S3] 16 to 18 and go to logic "1" level when logic values of respective corresponding bits of the two sets of registers are all agreed. Respective outputs of the logic gates 25 to 27 are supplied to respective inputs of a 3-input AND gate 28. The AND gate 28 goes to logic "1" level when the input levels are all at logic "1" level, i.e., the outputs of the logic gate 25 to 27 are all agreed. A counter 29 is adapted to count the same clock CK as those supplied to the four syndrome registers 15 to 18. The counter 29 is reset and disabled under the control of a CPU 30. Specifically, when the number (location) i of erroneous data contained in received data and an error amount e i of the received data are calculated from the syndromes S0 to S3 thus obtained, the counter 29 is reset to "0" and disabled when the AND gate 28 detects that the levels of the logic gates are all agreed. At the completion of the error calculation, the value stored in the S0 register 15 at that very ending time point becomes the error amount e i and the count value j of the counter 29 becomes the number (location) i of erroneous data. Then, received data of the error location i stored in a buffer memory, not shown, is accessed to the received data input unit shown in FIG. 1 and thereby added with the data stored in the S0 register 15. When such processing is carried out at the completion of the calculation, data that had been error-corrected is left in the S0 register 15. Then, error-corrected data DT is output and the error correction is completed. The algorithm used in the circuit embodying the present invention will be described next with reference to a flowchart of FIG. 2. Initially, syndromes ares calculated by the adders 11 to 14, the syndrome registers [S0 to S3] 15 to 18, the multiply-by-power α circuit 19, the multiply-by-power α 2 circuit 20 and the multiply-by-power α 3 circuit 21 (at step S1). Assuming now that ith received data, for example, is erroneous by the amount e i , then [Equation 5] yields S0 = e i , S1 = e i α i , S2 = e i α 2i and S3 = e i α 3i . Then, respective data stored in the syndrome registers {S1 to S3] 16 to 18 are stored in data registers [R1 to R3] 22 to 24 and data stored in the syndrome register [S0] 15 is stored in the syndrome registers [S1 to S3], respectively (at step S2). Therefore, values of the syndrome registers [S0 to S3] 15 to 18 are S0 = S1 = S2 = S3 = e i , R1 = e i α i , R2 = e i α 2i , R3 = e i α 3i . Subsequently, the counter 29 is reset to "0" (at step S3), and it is determined whether or not S1 = R1, S2 = R2, S3 = R3 are established in the syndrome registers 16 to 18 and the data registers 22 to 24 (at step S4). If 0th received data (x 0 ') is erroneous, then the above-mentioned three conditions in the S registers and the R registers are all agreed. If the received data is not erroneous, then the above-mentioned conditions also are established. In this case, since S0 = 0, it can be determined whether or not the received data is erroneous, as will be described later on. If it is determined in step S4 that the above-mentioned conditions are not established, so long as j ≤ 31 is established (at step S5), α · S1 → S1, α 2 · S2 → S2, α 3 · S3 → S3 are calculated (at step S6). Then, the count value j of the counter 29 is incremented by one (step S7), and the processing returns to step S4. Calculations in step S6 can be realized only by inputting "0" as received data. As a result of this calculation, the values of the syndrome registers 16 to 18 are S1 = αe i , S2 = α 2 e i , S3 = α 3 e i . It is determined one more time whether or not the conditions, S1 = R1, S2 = R2, S3 = R3 are established (at step S4). If the first (x 1 ') data of the received data is erroneous, then these conditions should be established. If these conditions are not established, steps S6 and S7 are executed one more time. If calculation is carried out j times, then the syndrome registers 16 to 18 generate S1 = α j e i , S2 = α 2j e i , S3 = α 3j e i . When j is agreed with i (number of erroneous received data), S1 = R1, S2 = R2, S3 = R3. Specifically, such calculation is repeated several times. When it is determined in step S4 that S1 = R1, S2 = R2, S3 = R3 are established, so long as the condition, S1 ≠ 0 is established (step S8), the count value j of the counter 29 is set to the number of erroneous data, and the error amount is set to the value of the syndrome register [S0] 15 (at step S9). If S0 = 0 in step S8, then it is determined that received data contains no error (at step S10). If it is determined in step S5 that the S register and the R register are not agreed with each other even though the count value j of the counter 29 exceeds 31, then it is determined that received data contains 2-byte error or greater. Then, such received data is treated as data that cannot be corrected (at step S11). As set out in detail, according to the embodiment of the present invention, the syndromes are calculated by the syndrome registers S0, S1 to S(n-1). After the syndrome registers had finished calculating the syndromes, if error is the single-error, then the value of the syndrome register S0 is loaded to the syndrome registers S1 to S(n-1) and the values of the syndrome registers S1 to S(n-1) are loaded to the data registers R1 to R(n-1), respectively. Multiplications of powers α, ..., α (n-1) are repeated by using the syndrome registers S1 to S(n-1) until the values of the syndrome registers S1 to S(n-1) and the values of the data registers R1 to R(n-1) are agreed. Count operation is executed in synchronism with the multiplications of powers. The count value obtained when it is detected that the values of the syndrome registers and the values of the data registers are agreed is set to the location of data containing error and the value of the syndrome register S0 is set to the error amount. Then, error correction is carried out on the basis of the location and the error amount. Therefore, the single-error can be detected and corrected by the circuit arrangement of the extremely small circuit scale composed of n syndrome registers indispensable to calculation of syndromes, ( n-1 ) data registers, one counter and coincidence detecting circuits, each of which is added to the syndrome registers. While the present invention is applied to the apparatus for reproducing the CD with the signal format having four syndromes (S0 to S3) as described above, the present invention is not limited thereto and can be applied to the whole field of digital data processing apparatus. By way of example, when the present invention is applied to a reproducing apparatus for reproducing a DAT with a signal format having six syndromes, error can be detected and corrected similarly as described above by increasing the number of syndrome registers and data registers in response to the number of syndromes.

Claims: An error correction method comprising the steps of: calculating (S1) n syndromes from received data, n being a positive integer determined by a number of parity words contained in said received data, and storing a single syndrome in a single syndrome register, said single syndrome representing an error amount if error is a single-error, and storing other syndromes in n-1 syndrome registers; characterised by the following steps: after calculation of syndromes is ended, loading the values stored in said n-1 syndrome registers into n-1 data registers and loading the value stored in said single syndrome register into all of said n-1 syndrome registers (S2); multiplying the contents of each of the n-1 syndrome registers by a power of α such that the i th syndrome register is multiplied by α i , where i is an integer from 1 to n-1 and α is a root of a generator polynomial on Galois field (S6); repeating this multiplication step until it is detected that the value stored in each of the n-1 syndrome registers is equal to the value stored in the respective n-1 data register (S4); incrementing a count each time the above multiplication step is performed (S7) whereby, if the value of the count is greater than the length of the received data, the error is uncorrectable (S11), otherwise, once no more multiplication steps are performed, the value of the count is equal to the location of a single error in the received data and the value in said single syndrome register is equal to the error amount (S9); and effecting error correction based on said error location and said error amount. An error correction circuit comprising: means (11-21) for calculating n syndromes from received data, n being a positive integer determined by a number of parity words contained in said received data, and storing a single syndrome in a single syndrome register (15), said single syndrome representing an error amount if error is a single-error, and storing other syndromes in n-1 syndrome registers (16-18); characterised by means for implementing the following steps: after calculation of syndromes is ended, loading the values stored in said n-1 syndrome registers (16-18) into n-1 data registers (22-24) and loading the value stored in said single syndrome register into all of said n-1 syndrome registers (16-18); multiplying (19-21) the contents of each of the n-1 syndrome registers (16-18) by a power of α such that the i th syndrome register is multiplied by α i , where i is an integer from 1 to n-1 and α is a root of a generator polynomial on Galois field; repeating this multiplication step until it is detected (25-28) that the value stored in each of the n-1 syndrome registers (16-18) is equal to the value stored in the respective n-1 data register (22-24); incrementing a count (29) each time the above multiplication step is performed whereby, if the value of the count is greater than the length of the received data, the error is uncorrectable, otherwise, once no more multiplication steps are performed, the value of the count is equal to the location of a single error in the received data and the value in said single syndrome register (15) is equal to the error amount; and effecting error correction based on said error location and said error amount.

Inventors: AKITA MAMORU, AKITA, MAMORU, AKITA, MAMORU, SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H03M13
IPC codes: G11B20, H03M13, G06F11