METHOD AND CIRCUIT FOR DRIVING LIQUID CRYSTAL DEVICE, AND DISPLAY DEVICE

Abstract: In a method of driving a liquid crystal device, etc., and a display device, particularly those for gradation dispaly, the present invention aims at providing a driving method of a liquid crystal device, etc., and a display device capable of satisfactorily effecting gradation display without causing insufficient contrast, flickers, cross-talk, etc. When effecting multiplex driving of a liquid crystal device, etc., having a liquid crystal layer sandwiched between a substrate having scanning electrodes X₁, X₂,... and a substrate having signal electrodes X₁, Y₂,..., the present invention simultaneously selects sequentially a plurality of scanning electrodes, divides the selection period into a plurality of periods, and applies a weighted voltage, which is weighted in accordance with desired display data, in each of the divided selection periods so as to effect gradation display.

Description: Field of the invention The present invention relates to a multiplex driving method and a drive circuit of a matrix type liquid crystal electro-optical device such as a liquid crystal display panel, for example. The present invention further relates to a liquid crystal display device. Description of the prior art Multiplex driving based on the amplitude selective addressing scheme is one known driving method for liquid crystal devices such as those referred to above (known from e.g. EP-A-0 349 415 and EP-A-0 479 450). Prior art example 1 Fig. 45 is an applied voltage waveform diagram showing one example of a prior art driving method of multiplex driving a simple matrix type liquid crystal electro-optical device as shown in Fig. 46 by means of an amplitude selective addressing scheme; Fig. 45 (a) and (b) are the voltage waveforms applied to row electrodes X 1 , X 2 , respectively, Fig. 45 (c) is the voltage waveform applied to column electrode Y 1 , and Fig. 45 (d) is the voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 . This example sequentially selects row electrodes X 1 , X 2 ,..., X n , one at a time, and depending on whether each pixel on the selected row electrode is ON or OFF applies a corresponding column voltage waveform to each of the column electrodes Y 1 , Y 2 ,..., Y m . When the display is driven by selecting one row electrode at a time as described above, however, a good display cannot be obtained without using a relatively high drive voltage. Prior art example 2 As a means of reducing the drive voltage, a method of sequentially selecting groups of row electrodes with each group comprising a plurality of simultaneously selected row electrodes has been previously proposed (see A Generalized Addressing Technique for RMS Responding Matrix LCDs, 1988 International Display Research Conference, pp. 80 to 85). Fig. 47 is an applied voltage waveform diagram showing an example of this prior art driving method of simultaneously selecting and driving plural row electrodes, Fig. 47 (a) being the row voltage waveforms applied to the row electrodes X 1 , X 2 , and X 3 , (b) the row voltage waveforms applied to row electrodes X 4 , X 5 , and X 6 , (c) the column voltage waveform applied to column electrode Y 1 , and (d) the voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 . This example simultaneously selects three sequential row electrodes (or lines) at a time for a display pattern as shown in Fig. 46. Specifically, three row electrodes X 1 , X 2 , and X 3 are first selected by row voltages as shown in Fig. 47 (a) applied to these row electrodes X 1 , X 2 , and X 3 , and a specified column voltage is simultaneously applied to each of the column electrodes Y1 to Y m as described in more detail below. Next, row electrodes X 4 , X 5 , and X 6 in Fig. 46 are selected by row voltages such as shown in Fig. 47 (b) applied as described above, and a column voltage is simultaneously applied to each of the column electrodes Y 1 to Y m . One frame is completed when all row electrodes X 1 to X n have been selected, and this operation is then repeated. If the number of simultaneously selected row electrodes in this method is h , then 2 h row select patterns are used for the row electrode voltage waveforms. In this example, h = 3, so 2 h = 2 3 = 8 row select patterns are used. The row select patterns, i.e., when a positive pulse of a voltage waveform applied to a row electrode is defined as an ON state and a negative pulse as an OFF state, the voltage ON/OFF patterns applied to the three simultaneously selected row electrodes X 1 , X 2 , and X 3 are shown in the following table using values of 1 and 0 to represent an ON state and an OFF state, respectively. X 1 0 0 0 0 1 1 1 1 X 2 0 0 1 1 0 0 1 1 X 3 0 1 0 1 0 1 0 1 The voltage waveforms generated based on these values for application to the row electrodes are shown in Fig. 48 (a). The waveforms shown in Fig. 48 (a), however, contain several different frequency components, which can result in display ununiformity when applied. Waveforms modified by reordering the row select patterns in the array shown above to reduce the differences in the frequency components are shown in Fig. 48 (b). The prior art example shown in Fig. 47 also uses these waveforms. However, the column voltages applied to each of the column electrodes Y 1 to Y m have the same number of patterns as the row voltages, and the voltage level of each pulse in the column voltage waveform has a value corresponding to the ON/OFF states of the selected row electrodes. In this case as mentioned above, for example, an ON state is when the row voltage waveform applied to any of the simultaneously selected row electrodes X1, X2, and X3 is a positive pulse and an OFF state is when it is a negative pulse. For each column electrode, the ON/OFF states of the display data (the display data pattern) for the pixels formed at the intersections of the column electrode and each of the simultaneously selected row electrodes, are compared pixel by pixel or bit by bit with the ON/OFF states of the selected row electrodes, and the level of the column voltage waveform is set according to the number of mismatches. In other words, in Fig. 47, pulse voltages -V Y2 , -V Y1 , V Y1 , and V Y2 are applied when the number of mismatches is 0, 1, 2, and 3, respectively. Note that the voltage ratio of V Y1 to V Y2 is V Y1 :V Y2 = 1:3. Specifically, if V X1 corresponds to ON and -V X1 to OFF in the voltage waveforms applied to row electrodes X1, X2, and X3 in Fig. 47 , and ON and OFF pixels are represented with a solid and a white dot, respectively, in Fig. 46, the pixels at the intersections of row electrodes X 1 , X 2 , and X 3 and column electrode Y 1 are ON-ON-OFF, respectively, and the initial row select pattern of the voltage applied to these row electrodes X 1 , X 2 , and X 3 is OFF-OFF-OFF. Because the number of mismatches between the display data pattern, i.e. the ON/OFF pattern of the pixels, and the row select pattern is two if they are compared in sequence, voltage V Y1 as shown in Fig. 47 (c) is applied as the first pulse to the column electrode Y 1 . The second row select pattern of the voltage applied to the row electrodes X 1 , X 2 , and X 3 is OFF-OFF-ON; because each of these is a mismatch when compared sequentially with the previous ON-ON-OFF display data pattern and the number of mismatches is therefore three, voltage V Y2 is applied as the second pulse to column electrode Y 1 . Similarly, V Y1 is applied as the third pulse, -V Y1 as the fourth pulse, and the following pulses are, in sequence, -V Y2 , V Y1 , -V Y1 , -V Y1 . The next group of three row electrodes X 4 to X 6 are then selected, and when the voltages shown in Fig. 47 (b) are applied to these row electrodes X 4 to X 6 , a column voltage of the voltage level corresponding to the number of mismatches between the ON/OFF states of the pixels at the intersections of row electrodes X 4 to X 6 and the column electrode, i.e. the display data pattern, and the ON/OFF states of the voltages applied to the row electrodes X 4 to X 6 , i.e. the row select pattern, is applied as shown in Fig. 47 (c). Note that while the values 1 and 0 are used for the positive and negative selection pulses, respectively, of the row voltage waveforms, and 1 and 0 are used for the ON and OFF display data states of pixels, respectively, and the column voltage waveform is set according to the number of mismatches, the values of 1 and 0 can be exchanged for each other and further the column voltage waveform can also be set according the number of matches or according to the difference between the number of matches and the number of mismatches. As described above, this method of simultaneously selecting and driving plural sequential row electrodes allows to reduce the drive voltage while achieving the same on/off contrast ratio as the single line selection method explained with reference to Fig. 45. The general conditions, summary, and procedure of this method of simultaneously selecting and driving plural row electrodes and sequentially selecting groups of such simultaneously selected row electrodes are described in order below. A. Conditions (a) N row electrodes are divided into N/h groups. (b) Each group comprises h address lines each corresponding to one row electrode. (c) The display data pattern of each column electrode at any given time is represented by an h bit word: d k·h+1 , d k·h+2 , ..., d k·h+h ; d k·h+j = 0 or 1 where 0 ≤ k ≤ (N/h)-1 and k is the group number. In other words, the display data for one column electrode can be defined as d 1 , d 2 ,..., d h group 0 d h+1 , d h+2 ,..., d h+h group 1 d N-h+1 , d N-h+2 ,..., d N-h+h group N/h-1. (d) The row select pattern is an h bit word of a cycle 2 h : a k·h+1 , a k·h+2 ,..., a k·h+h ; a k·h+j = 0 or 1. B. Summary (1) One group is selected at a time with the row electrodes forming the group being simultaneously selected. (2) One h -bit word is selected as the row select pattern determining the voltages to be applied to the simultaneously selected row electrodes. (3) The row voltage is -Vr for logic 0 (representing the OFF state) of the row select pattern, +Vr for logic 1 (representing the ON state), and 0 V for unselected row electrodes. (4) For each column electrode the h-bit word of the row select pattern of the selected group is compared bit by bit with the h-bit word of the respective display data pattern. (5) The number of bit mismatches i between the h-bit word representing the row select pattern and that representing the display data pattern is determined. (6) The voltage applied to the column electrode is V (i) where i is the number of mismatches. (One predetermined voltage is selected according to the number of mismatches.) (7) Based on this method, the column voltages are determined (simultaneously and in parallel). (8) The row and column voltages thus determined are applied to the row and column electrodes, respectively, of the display matrix for the time duration Δt o only (where Δt o is the minimum pulse width). (9) A new row select pattern is selected and steps (4) to (6) are recalculated, and the next column voltage is determined. This voltage is also applied for Δt o only. (10) A cycle is completed when all the N/h groups have been selected once, each with all the 2 h row select patterns. 1 cycle = Δt·2 h ·( N / h ). C. Analysis The possible row electrode select patterns when there are i mismatches are considered below. The number of h-bit row-select patterns which differ from an h-bit display data pattern in i bits is given by h C i = h! / {i!(h-i)!} = Ci. For example, if h = 3 and the row select pattern is (0,0,0), the following data pattern variations are possible. No. of mismatches Data pattern (column electrode) Ci i = 0 (0,0,0) 1 pattern i = 1 (0,0,1) (0,1,0) (1,0,0) 3 patterns i = 2 (1,1,0) (1,0,1) (0,1,1) 3 patterns i = 3 (1,1,1) 1 pattern The number of Ci is determined by the number of bits in one word, and not by the row select pattern. The level V pixel of the momentary voltage applied to the pixel is defined as V pixel = (V column - V row ) or (V row - V column ) where V row is the row voltage and V column is the column voltage. assuming that V row = ±Vr and Vcolumn = V (i) , then V pixel = +Vr - V (i) or -Vr - V (i) . assuming that V row = ±Vr and Vcolumn = ±V (i) , then V pixel = Vr - V (i) , Vr + V (i) , -Vr - V (i) , or -Vr + V (i) . In other words, V pixel = V r - V (i) or V r + V (i) . Thus, the specific voltage level applied to a pixel is -(Vr + V (i) ) or (Vr - V (i) ) for a selected line (row electrode), and V (i) for unselected lines (row electrodes). (The result will be as described in the above mentioned paper if V (i) is bipolar.) In general, it is preferable in terms of achieving a high contrast ratio that the voltage applied to a given pixel be as high as possible with ON pixels and as low as possible with OFF pixels. Thus, when ON, Vr + V (i) works favorably for ON pixels, Vr - V (i) works unfavorably for ON pixels; when OFF, Vr - V (i) works favorably for OFF pixels, Vr + V (i) works unfavorably for OFF pixels, where "favorable" for ON pixels means to raise the effective voltage, and "unfavorably" for ON pixels means to act in the direction of lowering the effective voltage. As mentioned above, the number of h-bit row select patterns which differ from an h-bit display data pattern in i bits is Ci = h C i = {h!} / {i!(h-i)!} where, if i is the number of mismatches, this is the number of cases in which i bits will mismatch in a select pattern of h bits. Because the number of mismatches is i in each of the Ci row select patterns, the total number of mismatches is i · Ci. Because these mismatches are distributed through h bits, the average number of mismatches Bi per pixel (per one bit) is Bi = i · Ci/h (number/pixel). In addition, if the column voltage V (i) level increases with the increase in the number i of mismatches, then V pixel = V row - V column will decrease with the increase in the number of mismatches. If a mismatch is considered to work unfavorably for the target ON pixel, the number of mismatches will provide the number of unfavorable voltages (column voltages). Therefore, the number of unfavorable voltages per pixel (on average) is Bi = i · Ci/h. However, because i/h of Ci is unfavorable, the remainder, i.e., Ai = {(h-i)/h} · Ci works favorably. In addition, {(h-i)/h} · Ci + (i/h) · Ci = (h/h)Ci = Ci, and Ai = Ci - Bi = {(h-1)!} / {i · (h-i-1)!} where h ≥ i + 1. Summarizing the above, we obtain V ON (rms) = {(S 1 + S 2 + S 3 ) / S 4 } 1/2 V OFF (rms) = {(S 5 + S 6 + S 3 ) / S 4 } 1/2 Note also that: S 4 = 2 h ·(N/h) In addition, Vr/V (o) = N 1/2 /h row selection voltage V (i) /V (o) = (h-2i) / h = {1-(2i/h)} column voltage, and R = (V ON /V OFF ) max = {(N 1/2 + 1) / (N 1/2 - 1)} 1/2 . When plural sequential row electrodes are simultaneously selected and driven as in prior art example (2) described above, however, the pulse width applied to the row electrodes and column electrode gets narrower as the number of simultaneously selected row electrodes increases, and picture quality deteriorates as crosstalk increases due to waveform rounding. This problem is particularly noticeable when this driving method is applied to gray scale displays using pulse width modulation. The object of the present invention is to provide a driving method and a drive circuit of a matrix type liquid crystal device, and a liquid crystal display device capable of achieving a good gray scale display even when simultaneously selecting and driving plural row electrodes. Disclosure of the Invention This object is achieved with a driving method, a driving circuit and a display device, respectively, as claimed. By using the driving method according to the invention, there is little crosstalk, etc., generated and a good gray scale display can be achieved even when simultaneously selecting plural row electrodes for multiplex driving. By using a drive circuit according to the invention, the above gray scale display can be achieved simply and reliably. The display device according to the invention provides a good gray scale display with little chance of crosstalk being generated. Brief Description Of The Drawings Fig. 1 is a voltage waveform diagram showing a first embodiment of a driving method according to the present invention, Fig. 2 is a diagram showing display data and the basic configuration of a matrix type liquid crystal device, Fig. 3 is a diagram used to describe the row voltage waveforms applied to the row electrodes, Fig. 4 is a block diagram of a first embodiment of a drive circuit, Fig. 5 is a block diagram of the row electrode driver, Fig. 6 is a block diagram of the column electrode driver, Fig. 7 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 8 is used to describe the display data and operation when driving is performed while using a virtual electrode, Fig. 9 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 10 is a diagram used to describe a gray scale display achieved by means of pulse width modulation, Fig. 11 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 12 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 13 is a diagram similar to that of Fig. 2 which is used to describe the display data and location of the virtual electrodes, Fig. 14 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 15 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 16 is a diagram used to describe the display data and location of the virtual electrodes, Fig. 17 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 18 is a diagram used to describe the display data and location of the virtual electrodes, Fig. 19 is a voltage waveform diagram showing an alternative embodiment of a driving method according to the present invention, Fig. 20 is a voltage waveform diagram used to describe the voltage waveforms applied to the column electrodes in an alternative embodiment of a driving method according to the present invention, Fig. 21 shows voltage waveforms of an alternative embodiment of a driving method according to the present invention, Fig. 22 is a diagram used to describe the display data and location of the electrodes, Fig. 23 shows voltage waveforms applied to the row electrodes in the above embodiment, Fig. 24 shows voltage waveforms of an embodiment dividing the selection period in the above embodiment into plural separate subperiods for driving within each frame, Fig. 25 shows voltage waveforms applied to the row electrodes in the above embodiment, Fig. 26 shows voltage waveforms to illustrate an alternative way of dividing the selection period in the previous embodiment into plural separate subperiods for driving within each frame, Fig. 27 shows voltage waveforms to illustrate another alternative way of dividing the selection period in the previous embodiment into plural separate intervals for driving within each frame, Fig. 28 shows voltage waveforms showing an alternative embodiment of a driving method according to the present invention, Fig. 29 shows voltage waveforms of an embodiment dividing the selection period in the above embodiment into plural separate subperiods for driving within a each frame, Fig. 30 shows voltage waveforms to illustrate an alternative way of dividing the selection period in the previous embodiment into plural separate subperiods for driving within each frame, Fig. 31 shows voltage waveforms to illustrate another alternative way of dividing the selection period in the previous embodiment into plural separate intervals for driving within each frame, Fig. 32 shows voltage waveforms showing an alternative embodiment of a driving method according to the present invention, Fig. 33 is a diagram used to describe the display data and location of the electrodes, Fig. 34 shows voltage waveforms showing an alternative embodiment of a driving method according to the present invention, Fig. 35 shows voltage waveforms showing an alternative embodiment of a driving method according to the present invention, Fig. 36 shows voltage waveforms of an embodiment dividing the selection period in the above embodiment into plural separate subperiods for driving within each frame, Fig. 37 shows voltage waveforms to illustrate an alternative way of dividing the selection period in the previous embodiment into plural separate subperiods for driving within each frame, Fig. 38 shows voltage waveforms to illustrate another alternative way of dividing the selection period in the previous embodiment into plural separate intervals for driving within each frame, Fig. 39 shows voltage waveforms showing an alternative embodiment of a driving method according to the present invention, Fig. 40 shows voltage waveforms of an embodiment dividing the selection period in the above embodiment into plural separate subperiods for driving within each frame, Fig. 41 shows voltage waveforms to illustrate an alternative way of dividing the selection period in the previous embodiment into plural separate subperiods for driving within each frame, Fig. 42 shows voltage waveforms to illustrate another alternative way of dividing the selection period in the previous embodiment into plural separate intervals for driving within each frame, Fig. 43 shows voltage waveforms showing an alternative embodiment of a driving method according to the present invention, Fig. 44 shows voltage waveforms of an embodiment dividing the selection period in the above embodiment into plural separate subperiods for driving within each frame, Fig. 45 shows voltage waveforms of one prior art driving method for a liquid crystal device, etc., Fig. 46 is a diagram used to describe the display pattern, Fig. 47 shows voltage waveforms of another prior art driving method for a liquid crystal device, etc., Fig. 48 is a diagram used to describe the voltage waveform applied to the row electrodes. Description Of Preferred Embodiments The preferred embodiments of a driving method, a drive circuit, and a display apparatus with a liquid crystal device and other display devices according to the invention are described below based on the preferred embodiments shown in the figures. Embodiment 1 Fig. 1 is an applied voltage waveform diagram used to describe the first embodiment of a driving method according to the present invention, Fig. 1 (a) being the voltage waveforms applied to row electrodes X 1 , X 2 , and X 3 , (b) being the voltage waveforms applied to row electrodes X 4 , X 5 , and X 6 , (c) being the voltage waveform applied to column electrode Y 1 , and (d) being the (composite) voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 . The present embodiment simultaneously selects three sequential row electrodes to achieve the display as shown in Fig. 2. While the type waveforms shown in Fig. 48 (a) or (b) can be used as the voltage waveforms applied to the simultaneously selected row electrodes, a type of waveforms as shown in Fig. 1 (a) is used in this embodiment. The problem when voltage waveforms as shown in Fig. 48 (a) or (b) are used is that each pulse width becomes narrower. Particularly when the number of simultaneously selected row electrodes increases, there is an exponential increase in the number of row select patterns and each pulse width necessarily becomes narrower, leading to a possible rounding (waveform distortion) of the waveform actually applied to a pixel, and even possibly to crosstalk due to such rounding. In this embodiment and in the embodiments achieving a gray scale display by pulse width modulation as described below, the pulse width would be even narrower, resulting in crosstalk. In the present embodiment, therefore, the voltage waveforms applied to the row electrodes are set as described below so that the pulse width is wider. The voltage waveforms applied to the row electrodes are decided based on the conditions that: (1) each row electrode must be identifiable, (2) the frequency components of the voltage waveforms applied to the row electrodes must not differ significantly, and (3) the AC drive of the liquid crystal must be ensured, i.e. there must be no DC component in the waveform when averaged over one or plural frames. In other words, the pattern of the applied voltages is appropriately determined from a natural binary, Walsh, Hadamard, or other systems of orthogonal functions considering the above conditions. Of these conditions, the first is absolute. To satisfy this condition the voltage waveforms applied to each row electrode are generated so that they are orthogonal to each other. The applied voltage waveforms shown in Figs. 3 (a) and (b) were determined considering the above conditions. The applied voltage waveforms in Fig. 3 (a) contain different frequency components, namely X 1 : 4·Δt o X 2 : 4·Δt o , 2·Δt o X 3 : 2·Δt o . The applied voltage waveforms in Fig. 3 (b) contain different frequency components, namely X 1 : 4·Δt o , 2·Δt o X 2 : 4·Δt o , 2·Δt o X 3 : 6·Δt o , 2·Δt o . While the shortest pulse width in the waveforms shown in Fig. 48 (a) and (b) is Δt o , the narrowest pulse width in the waveforms in Fig. 3 (a) and (b) is 2Δt o , an increase by a factor of 2. It is thus possible, by increasing the pulse width, to reduce the effects of waveform rounding, decrease crosstalk, and increase the number of simultaneously selected row electrodes. It is to be noted that the waveforms shown in Fig. 3 (a) and (b) are one example and can be changed as appropriate, and that the row electrode selection sequence and sequence of the row select patterns applied to the row electrodes can also be changed using the properties of the systems of orthogonal functions. The row voltage waveforms shown in Fig. 1 (a) and (b) form the voltage waveforms applied to the three simultaneously selected row electrodes based on the waveform in Fig. 3 (b). In addition, in this embodiment, the selection period is divided into four separate selection subperiods t 1 , t 2 , t 3 , t 4 in each frame. Each of the selection subperiods t 1 , t 2 , t 3 , t 4 divided as described above is subdivided into plural intervals as shown in Fig. 1 (c), and in each of these intervals a weighted voltage is applied to the column electrodes Y1 to Y m to obtain a desired display. In other words, in this embodiment, subperiod t 1 is subdivided into two equal intervals a and b. As shown in Fig. 2, the display data for each pixel are composed of two bits representing a binary code for a gray scale display with four gradations. A column voltage specifically weighted for each bit based on the display data shown in Fig. 2 is applied, during interval a for the high or most significant bit and during interval b for the low or least significant bit as shown in Fig. 1. Specifically, if voltage V X1 applied to a row electrode represents the ON states and -V X1 the OFF state, and the display data value 0 represents OFF and 1 ON, and the ON/OFF states of the simultaneously selected row electrodes and the ON/OFF state of the display data are compared bit by bit to calculate the number of mismatches, the voltages applied for the high bit when the number of mismatches is 3, 2, 1, and 0, respectively, are V Y4 , V Y2 , -V Y2 , and -V Y4 , and the voltages applied for the low bit when the number of mismatches is 3, 2, 1, and 0, respectively, are V Y3 , V Y1 , -V Y1 , and -V Y3 . Note that the relationship between each of the voltage levels is 2·V Y1 = V Y2 2·V Y3 = V Y4 2·V Y1 = V Y3 - V Y1 2·V Y2 = V Y4 - V Y2 . For example, during subperiod t 1 in Fig. 1 (c), the selected pulses applied to row electrodes X 1 , X 2 , and X 3 are ON, ON, OFF, respectively, and the display data for the pixels at the intersections of column electrode Y 1 and row electrodes X 1 , X 2 , and X 3 are (00), (01), (10), i.e. the high bits represent OFF, OFF, ON. Comparison shows the number of mismatches is three, and voltage V Y4 is therefore applied to the column electrode Y 1 in interval a. Since the low bits represent OFF, ON, OFF, the number of mismatches compared with the row select pattern is one, and voltage -V Y1 is therefore applied in interval b. Thus for each of the column electrodes Y1 to Y m , the display data for the pixels on the row electrodes X 1 , X 2 , and X 3 is compared with the selected pulses applied to the row electrodes (the row select pattern), and a column voltage corresponding to the number of mismatches is applied. Next, row electrodes X 4 , X 5 , and X 6 are simultaneously selected and the corresponding column electrode waveforms are applied to the column electrodes. When the sequence of simultaneously selecting the row electrodes, three at a time, and applying the corresponding column electrode waveforms to the column electrodes until all row electrodes X 1 to X n have been scanned is completed, the operation returns to the first group of row electrodes X 1 , X 2 , and X 3 and the specified voltages are sequentially applied following the above sequence in subperiods t 2 , t 3 , and t 4 . When all row electrodes X 1 to X n have been scanned in each of the four subperiods t 1 to t 4 , the next frame starts and the process is repeated. Note that the polarity of the applied voltage is reversed every frame in this embodiment for a so-called alternating current drive scheme. A good gray scale display with minimal crosstalk can thus be achieved by driving as described above. It is to be noted that the sequence of the row voltage waveforms applied to the row electrodes in the above subperiods t 1 to t 4 can be changed for all frames or in single frames, and the waveforms shown in Fig. 3 (a) or other waveforms satisfying the conditions described above can be used as the row voltage waveforms applied to the row electrodes. Moreover, two kinds of waveforms can be alternately used for each group of simultaneously selected row electrodes, for example the kind of waveforms shown in Fig. 3 (a) for row electrodes X 1 to X 3 and the kind of waveforms shown in Fig. 3 (b) for row electrodes X 4 to X 6 , or a sequence of three or more kinds of waveforms can be used alternately. In addition, it is also possible to combine reordering the waveforms in subperiods t 1 to t 4 with reordering the waveforms for the groups of simultaneously selected row electrodes. While the subperiods t 1 to t 4 can be separate in each frame period as in the above embodiment, or can be consecutive in each frame, if the subperiods of the selection period are separate, i.e. distributed within one frame as in the present embodiment, the period during which a row electrode continuously stays unselected becomes shorter and the contrast can be improved. In this case, while the selection period is divided into four subperiods t 1 to t 4 in the above embodiment, any number of divisions can be used; further, each of the subperiods t1 to t4 can be subdivided into two intervals as explained above, or it can be subdivided into more than two intervals allowing more gradations. In addition, three row electrodes, sequential in position, are selected at a time in the above embodiment, but the number of the selected row electrodes can be any appropriate number and the row electrodes forming a group of simultaneously selected row electrodes do not necessarily need to be sequential in position. The above modifications can also be applied to the alternative embodiments described below. A drive circuit executing the driving method described above is described based on Figs. 4 to Fig. 6. Fig. 4 is a block diagram showing one example of a drive circuit. In this figure 1 is a row electrode driver, 2 is a column electrode driver, 3 is a frame memory, 4 is an arithmetic operation circuit, 5 is a row data generating circuit, and 6 is a latch. Fig. 5 is a block diagram of the row electrode driver, Fig. 6 is a block diagram of the column electrode driver, and in Fig. 5 and Fig. 6, 11 and 21 are shift registers, 12 and 22 are latches, 13 and 33 are decoders, and 14 and 24 are level shifters. In this configuration, each row electrode waveform is generated based on a scan data signal S3 indicating a positive selection, negative selection, or no selection, the scan data signal being generated from the row data generating circuit 5 and sent to the row electrode driver 1. In the row electrode driver 1, as shown in Fig. 5, the scan data signal S3 from the row data generating circuit 5 is sent to the shift register 11 at the scan shift clock signal S5, and after the data for each of the row electrodes in one scanning period have been entered into the shift register, the data are latched in the latch 12 at latch signal S6, the data expressing the state of each row electrode are then decoded by decoder 13, and the decoded outputs are used, via level shifter 14, to switch on one of three analog switches 15 provided for each output, and voltage V X1 , -V X1 , or 0 is selected and output to the respective row electrode when the selection is positive, negative, or no selection, respectively. For the column electrode waveforms, the display data signal S1 for the three simultaneously selected row electrodes X 1 , X 2 , and X 3 is read from frame memory 3, and the display data signal S1 and scanning data signal S3, latched in latch 6, are converted by the arithmetic operation circuit 4. This data conversion is performed as described above, and the converted data are transferred to the column electrode driver 2 as column data signal. In the column electrode driver 2, as shown in Fig. 6, the column data signal S2 from the arithmetic operation circuit 4 is sent to shift register 21 at shift clock signal S7, and after the data for each column electrode in one scanning period have been input, the data are latched in latch 22 at the latch signal S8, the data expressing the state of each column electrode are then decoded by decoder 23 whose outputs are used, via level shifter 24, to switch on one of the eight analog switches 25 provided for each output, and one of the eight voltages V Y4 , V Y3 , V Y2 , V Y1 , -V Y1 , -V Y2 , -V Y3 , and -V Y4 is output to each column electrode. A driving method as described above can thus be simply and reliably achieved by using a drive circuit as described above. If a display apparatus comprising a display device as described above comprises a drive circuit as described above to execute the driving method as described above, a display apparatus capable of achieving a good gray scale display with minimal crosstalk generated can be achieved. Embodiment 2 In the first embodiment one of four voltages is selected according to the display data and applied to the column electrodes for each bit of the display data, but by providing a virtual electrode the number of voltage levels applied to the column electrodes can be reduced. Fig. 7 is a voltage waveform diagram for an embodiment that is capable of driving by a reduced number of voltage levels applied to the column electrodes by providing a virtual row electrode in each group of simultaneously selected row electrodes, and Fig. 8 illustrates the basis for reducing the number of voltage levels applied to the column electrodes by providing a virtual electrode. This embodiment provides, for example, virtual row electrodes X n+1 , X n+2 ,... each after a corresponding group of simultaneously selected row electrodes as shown in Fig. 8, such that virtual row electrode X n+1 is selected simultaneously with row electrodes X 1 , X 2 , and X 3 , for example. The number of mismatches is calculated as in the first embodiment assuming voltage V X1 is applied to the row electrode in each ON state, -V X1 is applied in each OFF state, and the display data value 0 represents OFF and 1 ON. In this case, the number of mismatches is always 1 or 3 by appropriately changing the ON/OFF state of the virtual row electrode. When the number of mismatches between the row select pattern and the high bits of the display data pattern is 1, -V Y2 is selected, and when the number of mismatches is 3, V Y2 is selected; when the number of mismatches between the row select pattern and the low bits of the display data pattern is 1, -V Y1 selected, and when the number of mismatches is 3, V Y1 is selected. Note that the relationship between each of the voltage levels is 2·V Y1 = V Y2 . The display shown in Fig. 2 is achieved by the waveforms in Fig. 7 applying the above principle. During subperiod t 1 , the selected pulses applied to row electrodes X 1 , X 2 , X 3 and virtual row electrode X n+1 are ON, ON, OFF, ON, respectively, the display data for the pixels at the intersections of column electrode Y 1 and row electrodes X 1 , X 2 , X 3 and virtual row electrode X n+1 are (00), (01), (10), (11), and the high bits represent OFF, OFF, ON, ON. Sequential comparison shows the number of mismatches is three; conversion data S2 is therefore generated according to this number of mismatches, and voltage V Y2 is therefore applied to the column electrode Y 1 in interval a. The low bits represent OFF, ON, OFF, ON, and the number of mismatches if compared with the row select pattern is one; conversion data S2 is therefore generated according to this number of mismatches, and voltage -V Y1 is therefore applied in period b. Thus, the display data for the pixels on the row electrodes X 1 , X 2 , X 3 and virtual electrode X n+1 , i.e. the display data pattern, is compared with the selected pulses applied to the row electrodes, i.e. the row select pattern, for each of the column electrodes Y1 to Y m , and a column voltage corresponding to the number of mismatches is applied. Next, row electrodes X 4 , X 5 , X 6 and virtual row electrode X n+2 are simultaneously selected and the corresponding column electrode waveforms are applied to the column electrodes. When the sequence of simultaneously selecting the row electrodes, three row electrodes at a time plus one virtual row electrode, and applying the corresponding column electrode waveforms to the column electrodes until all row electrodes to X 1 to X n have been scanned is completed, the operation returns to the first group of row electrodes X 1 , X 2 , and X 3 and sequential scanning using the row select pattern shown in t 2 continues. One frame period is completed by scanning four times with the row select patterns shown in t 1 , t 2 , t 3 , and t 4 , and the same operation is repeated in the next frame. By thus providing virtual electrodes as above, the number of voltage levels applied to the column electrodes can be made less than that of the first embodiment. The principle of reducing the number of voltage levels applied to the column electrodes by providing virtual electrodes as described above can also be applied to each of the embodiments described below. In addition, the same drive circuit as that used in the first embodiment can be used in the present embodiment and each of the embodiments described below. In this case, the arithmetic operation circuit 4 in Fig. 4 is adapted to execute data processing according to each of the embodiments, the voltage levels of the row electrode driver in Fig. 5 and the column electrode driver in Fig. 6 are provided according to each embodiment, and one of the voltage levels is selected by analog switches 15, 25. In this embodiment, for example, the arithmetic operation circuit 4 in Fig. 4 and the row electrode driver in Fig. 5 are the same as those of the first embodiment, but while eight voltage levels V Y4 , V Y3 , V Y2 , V Y1 , -V Y1 , -V Y2 , -V Y3 , and -V Y4 are provided in the column electrode driver of the first embodiment in Fig. 6, it is sufficient to provide four voltage levels V Y2 , V Y1 , -V Y1 , and -V Y2 in the present embodiment. Embodiment 3 The above embodiment achieves a gray scale display by changing the voltage value according to the display data, but a gray scale display can also be achieved by changing the pulse width. Fig. 9 is an applied voltage waveform diagram of an embodiment achieving a gray scale display by changing the pulse width. The general procedure for achieving a gray scale display by means of pulse width modulation is described first. In general, the period Δt of each pulse is divided into f subperiods of unequal duration to achieve a gray scale display by means of pulse width modulation. Δt g = 2 g-1 / (2 f - 1), g = 1, ..., f where f is the bit number of the binary coded gradation number. For example, if f = 2, there are 2 2 = 4 gradations, and the period is divided into two subperiods: Δt 1 = (1/3)Δt o Δt 2 = (2/3)Δt o as shown in Fig. 10. The display data is then represented by f bits: The row select pattern and the display data pattern are then compared bit by bit, separately for each bit position of the display data, at an interval of Δt g . For example, when f = 2, The low or least significant bits (d 1,1 , d 2.1, ...) of the display data pattern (d 1 , d 2 ,...) and the bits of the row select pattern are first compared and column voltage waveforms corresponding to the result is applied for display for subperiod Δt 1 . The next to least significant bits d 1,2 , d 2.2 ,... and the row select pattern are then compared and corresponding column voltage waveforms applied for subperiod Δt 2 . If f > 2, this is sequentially repeated as above for each bit position. Fig. 9 based on the present embodiment achieves a four gradation gray scale display as shown in Fig. 2 using pulse width modulation as described above. In this example, the row voltage waveforms applied to the row electrodes X 1 to X n are the same as in the prior art example illustrated in Fig. 47, and the pulse widths of the column voltage waveforms applied to the corresponding column electrodes Y 1 to Y m are modulated according to the gray scale display as above. In other words, each pulse width Δt is divided into three equal parts, and a gray scale display with four gradations 0 to 3 is expressed using the 2-bit binary display data expressions (00), (01), (10), (11). The signal voltage level of two of the three pulse width parts is determined based on the number of mismatches between the ON/OFF state of the simultaneously selected row electrodes and the high bit states of the display data pattern. The signal voltage level of the remaining one part is determined based on the number of mismatches between the ON/OFF state of the row electrodes and the low bit states. Variations in the brightness of the gray scale display can be corrected by equally reducing the three parts. Specifically, if in Fig. 9 an ON state is achieved by applying voltage V X1 to the row electrode and an OFF state by applying voltage -V X1 , the first pulses applied to the row electrodes X 1 , X 2 , and X 3 generate an OFF state for all three row electrodes. Because a low bit value of 0 indicates an OFF state and a low bit value of 1 an ON state in the display data for the row electrodes X 1 , X 2 , and X3 in Fig. 2, the corresponding states are OFF, ON, OFF. The number of mismatches is therefore one, and the voltage pulse during pulse width part Δt 1 is -V Y1 . Because the high bit states are OFF, OFF, ON, the number of mismatches is one, and the voltage pulse during pulse width part Δt 2 is -V Y1 . It is thus sufficient to obtain the voltage pulse applied to the column electrodes by a comparison executed each selection pulse width part Δt. In this embodiment, the voltage for the high bit is applied during the latter two of the three pulse width parts, and the voltage for the low bit is applied during the first of the three pulse width parts. Embodiment 4 The selection period can also be divided into plural separate selection subperiods each frame as described in the first embodiment above to drive a gray scale display. An example of such application is shown in Fig. 11. The voltage waveforms of eight row select patterns (blocks) applied to the row electrodes and column electrodes in the embodiment shown in Fig. 9 are divided into eight equal selection subperiods one for each row select pattern. When the liquid crystal device is driven by dividing the selection period into plural separate selection subperiods in one frame as described above, the contrast can be improved as in the previous embodiment. Embodiment 5 The four voltage levels V Y2 , V Y1 , -V Y1 , and -V Y2 are used as the column electrode voltage levels in the third and fourth embodiments above, but this number of voltage levels can be further reduced by providing virtual row electrodes as in the second embodiment. Fig. 12 shows an example that makes use of the virtual electrodes of the third embodiment to reduce the number of voltage levels applied to a column electrode, and is driven by dividing the selection period in to plural separate selection subperiods within each frame as in the fourth embodiment. Reducing the number of voltage levels by providing virtual electrodes has already been described in the second embodiment, but is described further below, including the general method. First, of the h row electrodes in each group, e column electrodes are operated as virtual row electrodes (virtual lines). By controlling the data matching/mismatching of these virtual row electrodes, the overall number of matches/mismatches can be controlled, and the number of drive voltage levels for the column electrodes can be reduced. If the number of mismatches is Mi and Vc is an appropriate constant, the voltage V column applied to the column electrode is defined as or simply V column = V (i) , where 0 ≤ i ≤ h. In any event, V column has h + 1 levels. The case where the number of groups h = 4 and the number of virtual row electrodes e = 1 is considered by way of example below. As in the previous embodiment, the number of levels when h = 3 is four (-V Y2 , -V Y1 , V Y1 , V Y2 ). If the number of mismatches is controlled using the virtual row electrodes to be an even number, the resulting voltage levels are shown in the following table. Original voltage level Original number of mismatches Virtual row electrode Number of mismatches after correction Voltage level after correction -V Y2 0 Match 0 V a -V Y1 1 Mismatch 2 V b V Y1 2 Match 2 V b V Y2 3 Mismatch 4 V d As shown in the above table, the original four voltage levels can be reduced to three. If the number of mismatches is controlled to be odd, the number of mismatches after correction will change in the above table to 1, 1, 3, 3 (from the top), and there will be only two voltage levels (Va, Va, Vb, Vb from the top) after correction. If the number of groups h = 4 and the number of unreduced voltage levels is therefore five (-V Y2 , -V Y1 , 0, V Y1 , V Y2 ), controlling the number of mismatches to be an even number using the virtual row electrode results in the voltage levels shown in the following table. Original voltage level Original number of mismatches Virtual row electrode Number of mismatches after correction Voltage level after correction -V Y2 0 Match 0 V a -V Y1 1 Mismatch 2 V b 0 2 Match 2 V b V Y2 3 Mismatch 4 V d V Y2 4 Match 4 V d The original number of voltage levels can thus be reduced from five to three. Note that the voltage levels can also be set by controlling the number of mismatches to be odd. It is not always necessary to physically provide these virtual row electrodes because they are not normally used for display. When they are provided, however, the virtual row electrodes can be provided in an area not affecting the display. When provided in a liquid crystal display device, for example, the virtual row electrodes X n+1 ,..., are provided outside the display area R as defined in Fig. 13. Alternatively, any extra row electrodes outside the normal display area R can also be used as virtual row electrodes. The number of voltage levels can be further reduced by increasing the number e of virtual row electrodes. In the above example the number of mismatches is controlled to be divisible by two when e = 1, but if e = 2, the same result can be obtained by controlling the number of mismatches to be divisible by three. It is also possible to divide by three to leave a remainder of one or two. The maximum reduction possible with the above method is 1/( e + 1), or 1/2 when e = 1 (except for 0 V). The present embodiment as shown in Fig. 12 simultaneously selects three row electrodes and one virtual electrode to reduce the number of voltage levels applied to the column electrodes, and drives by dividing the selection period into plural separate subperiods in each frame. As shown in Fig. 12 and Fig. 14, the present embodiment divides the selection period into four separate subperiods a frame, and the number of mismatches between the row select pattern and the display data pattern is counted bit by bit for four row electrodes, including the virtual row electrode, in each of the four subperiods to adjust the number of mismatches to an odd number. The number of mismatches is thus either 1 or 3, and the voltage level of the column voltage waveform is therefore one of two levels, V Y1 or -V Y1 . Considering the display shown in Fig. 13, the virtual row electrode X n+1 , even though shown outside of the display area R, is part of the first group of simultaneously selected row electrodes including the first three selected row electrodes X 1 , X 2 , and X 3 and the virtual row electrode X n+1 as shown in Fig. 8. Again, it is not essential for the virtual row electrode to be actually existent, but when it exists, it is preferably provided outside the display area R. If a positive voltage applied to a row electrode is represented by ON and a negative voltage by OFF, each of the selection subperiods Δt is subdivided into three intervals, and the display data for the pixels on the simultaneously selected row electrodes X 1 , X 2 , and X 3 is (00), (01), (10) as shown in Fig. 13, then the display data for the virtual row electrode is (11) as shown in Fig. 8. As explained earlier, the number of mismatches between the row select pattern and the display data pattern is then counted separately for each bit position (high and low in case of 2-bit display data) to determine either voltage level V Y1 or -V Y1 , and the voltages for the high bits are applied for the latter two of the three intervals and the voltage for the low bit is applied for the first one interval. Note that, as in the third embodiment, it is also possible to apply the voltages for the high bits in the first two intervals and to apply the voltages for the low bits in the last one interval. It is therefore sufficient to determine the pulse width of voltage V Y1 or -V Y1 by a per bit comparison with the display data, and the present embodiment can reduce the number of voltage levels applied to the column electrodes, specifically to two in the above embodiment, by always setting the number of mismatches between the display data pattern and the row select pattern to 1, 3, or some other odd number. Note that an even number of mismatches can be alternatively used. Note also that while the above embodiment has been described for a gray scale display with four gradations, a display with a larger number of gradations is also possible. For example, eight gradations can be achieved by using 3-bit display data and subdividing each selection period or subperiod into three intervals the width of each weighted according to the position of a corresponding one of the display data bits. A display with 16 gradations can be achieved by using 4-bit display data and subdividing each selection period or subperiod into four correspondingly weighted intervals. Thus, different numbers of gradations of a gray scale display are possible by adapting the number of intervals each selection period or subperiod is subdivided into. Embodiment 6 The above described fifth embodiment employs the type of voltage waveforms shown in Fig. 48 (b). However, providing virtual row electrodes as in the fifth embodiment above to reduce the number of voltage levels applied to the column electrodes while also using pulse width modulation to achieve a gray scale display can also be applied to the case wherein the same type of row voltage waveforms as in the first embodiment is applied to the simultaneously selected row electrodes, and an example of this is shown in Fig. 14. The voltage waveforms applied to the simultaneously selected row electrodes are the same as that of the first embodiment shown in Fig. 1, and each of the selection subperiods t 1 to t 4 , t 5 to t 8 is subdivided into three intervals. When the display data for the pixels on the simultaneously selected row electrodes X 1 , X 2 , and X 3 are (00), (01), (10) as shown in Fig. 13, the data of the virtual row electrode may be (11) as shown in Fig. 8. The number of mismatches is then counted bit by bit in the same way as explained above to determine the voltage level, and either V Y1 or -V Y1 is applied as the voltage for the high bits in two of the three intervals and the voltage for the low bits in one interval. It is thus possible to obtain the same effects as with the fifth embodiment. It is to be noted that the selection subperiods t 1 to t 4 may be provided consecutively (forming one continuous selection period) or separately in each frame F. The same is true of selection subperiods t 5 to t 8 . Embodiment 7 Driving a gray scale display by means of a so-called frame rate control modulation is also possible in addition to dividing the selection period and reducing the number of applied voltage levels as described above, and Fig. 15 shows an embodiment wherein the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the sixth embodiment, the selection period is divided into plural separate subperiods each frame, and a gray scale display is achieved by means of frame rate control modulation. Note that while the waveforms shown in Fig. 3 (b) are used as the voltage waveforms applied to the simultaneously selected row electrodes in this embodiment, the waveforms shown in Fig. 3 (a) or Fig. 48 (a) or (b) can also be used. A gray scale display based on frame rate control modulation turns pixels ON in some frames and OFF in other frames during any given picture period, and in the example shown in Fig. 16, a gradation between on and off is displayed by applying an ON voltage during one frame F1 and an OFF voltage during another frame F2 assuming a picture period comprising two frames. In this embodiment, the brightness difference between frames F1 and F2 is reduced and flicker becomes less noticeable because the selection period is divided into four separate subperiods each frame. For example, in a gray scale display using plural frame periods as one block or picture period, the position of the selection pulses, i.e. the row select pattern, can be changed within the plural frames, and the difference between frames can be reduced by interchanging the row select patterns of subperiods t 3 and t 7 , for example, in Fig. 15. While a gray scale display is achieved by turning pixels ON in one of two frames and OFF in the other frame in the above embodiment, a picture period may be defined to have a block of more frames, for example 7 (15) frames, to achieve 8 (16) gradations by changing the number of ON and OFF frames within the block. Thus, a display with the desired number of gradations is possible depending on the number of frames of one block. Embodiment 8 Driving a gray scale display by means of frame rate control modulation is also possible in addition to dividing the selection period into separate subperiods and reducing the number of applied voltage levels as in the fifth embodiment above, and Fig. 17 shows an embodiment in which the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the fifth embodiment the selection period is divided into plural subperiods each frame, and a gray scale display is achieved by means of frame rate control modulation in combination with pulse width control. By displaying plural gradations during plural frame periods with in a given picture period, intermediate gradations between the gradations of the plural frames can be displayed. For example, by displaying (00) during the first frame F1 period of a 2-frame picture period and (01) during the next frame F2 period as shown in Fig. 18, a gradation actually between (00) and (01) can be displayed. Display flicker can be reduced and a multiple gray scale display can be achieved by thus dividing the selection period and reducing the number of applied voltage levels, and combining pulse width modulation with frame rate control modulation for the gray scale display. Note also that the order of the row select patterns can be changed as in the sixth embodiment above. While the fifth to eighth embodiments above have been described assuming the use of a virtual row electrode, it should be noted that a gray scale display can still be achieved by means of frame rate control modulation or by a combination of frame rate control modulation and pulse width modulation even when no virtual row electrode is used. Embodiment 9 Each of the above embodiments has been described as achieving a gray scale display with four gradations by applying column voltages weighted according to each bit of 2-bit display data, but as mentioned before, it is possible to drive other numbers of gradations. For example, eight gradations can be obtained using a column electrode waveform as shown in Fig. 19. In other words, Fig. 19 is the column electrode waveform when the display data for the pixels at the intersections of the row electrodes X 1 , X 2 , and X 3 and column electrode Y 1 are (001), (010), (100) and the row electrode waveform applied to each of the row electrodes in Fig. 2 is the same as that of the first embodiment. In this embodiment, the four selection subperiods t 1 to t 4 in the first embodiment are each subdivided into three equal intervals a, b, c, and the voltage waveform corresponding to the highest of the three display data bits is applied in the first interval a, the voltage waveform corresponding to the middle bit is applied in the next interval b, and the voltage waveform corresponding to the lowest bit is applied in the last interval c; each of these voltage waveforms is weighted according to each of the display data bits as in the first embodiment. Specifically, one of the voltages -V Y6 , -V Y4 , V Y4 , or V Y6 is selected for interval a according to the highest display data bit, one of the voltages -V Y5 , -V Y2 , V Y2 , or V Y5 is selected for interval b according to the middle display data bit, and one of the voltages -V Y3 , -V Y1 , V Y3 , or V Y1 is selected for interval c according to the lowest display data bit. The relationship between each of the voltage levels is defined as 4·V Y1 = 2·V Y2 = V Y4 4·V Y3 = 2·V Y5 = V Y6 2·V Y1 = V Y3 - V Y1 2·V Y2 = V Y5 - V Y2 2·V Y4 = V Y6 - V Y4 . Under these conditions, a gray scale display with eight gradations can be achieved in a manner corresponding to that in the first embodiment by generating the column electrode waveforms based on the number of mismatches calculated separately for each bit position of the display data pattern. As described above, a gray scale display with four gradations is obtained in the first embodiment by selecting a voltage for each of the two equal intervals into which the selection subperiod is subdivided, and applying this voltage to the column electrode, but in the present embodiment eight gradations are obtained by subdividing the selection subperiod into three equal intervals. In addition, sixteen gradations can be obtained by subdividing the selection period or subperiod into four equal intervals, and, as this indicates, the number of gradations can be increased by appropriately subdividing the selection period or subperiod into plural intervals and applying a voltage selected for each of these intervals to the column electrode. The brightness level of each gradation can be adjusted by changing the ratio of the voltages applied to each column electrode, or by slightly changing the duration of each interval instead of using equal intervals. Embodiment 10 In a gray scale display obtained by changing the voltages applied to the column electrodes as shown in Fig. 19 of the ninth embodiment above, a voltage is applied according to each bit of the multi-bit display data, in sequence from the high or most significant bit in the intervals a, b, c, divided according to the number of display data bits, but this sequence can be appropriately changed for each column electrode. If, for example, in the ninth embodiment above the display data for the pixels at the intersections of row electrodes X 1 , X 2 , and X 3 and column electrodes Y 2 to Y m are the same as the display data for the pixels at the intersections of row electrodes X 1 , X 2 , and X 3 and column electrode Y 1 , the column voltage waveforms applied to the column electrodes Y1 to Y m will all be identical to the waveforms shown in Fig. 19. However, rounding of the waveform applied to each pixel becomes great in this case, and display quality deteriorates. The order of the column electrode waveforms applied to each of the column electrodes Y 1 to Y m is thus changed in this embodiment as shown in Fig. 20. In other words, in the ninth embodiment the voltage corresponding to the highest of the three display data bits is applied in sequence to column electrode Y 1 during interval a in Fig. 20, the voltage corresponding to the middle bit during interval b, and the voltage corresponding to the lowest bit during interval c. The same is true of the other column electrodes Y 1 to Y m . In the present invention as shown in Fig. 20, however, if the interval in which the voltage corresponding to the highest bit is applied is a, the interval in which the voltage corresponding to the middle bit is applied is b, and the interval in which the voltage corresponding to the lowest bit is applied is c, and the voltages are applied to column electrode Y 1 in the order (a, b, c) in sequence from the highest bit as in the second embodiment, the order is changed for the next column electrodes, for example to (a, c, b) for column electrode Y 2 , (b, a, c) for column electrode Y 3 , (b, c, a) for column electrode Y 4 , (c, a, b) for column electrode Y 5 , and (c, b, a) for column electrode Y 6 , and similar combinations are repeated for Y 7 to Y m . If this method is applied, the effects of rounding rises and falls of column electrode waveforms cancel each other out, and rounding of the waveforms applied to each pixel can be reduced because waveforms in six different order combinations are applied in essentially the same number to the column electrodes, It is to be noted that any combination of waveforms applied to the column electrodes can used such that, for example, if there are six column electrode drivers, each combination of waveforms is applied to each column electrode driver. Thus, display quality can be improved if the number of rounding rises and falls cancel each other in the combination of waveforms applied to the respective column electrodes. Furthermore, changing the order of the voltages corresponding to each bit of display data for each of the column electrodes Y 1 to Y m as described above can also be applied to the various embodiments described hereinbefore and below. Embodiment 11 In the ninth embodiment a gray scale display with eight gradations is obtained using a type of waveform as shown in Fig. 1 (a), i.e. as shown in Fig. 3 (b), as the row voltage waveforms applied to the row electrodes, but the type of waveforms shown in Fig. 3 (a) or in the Fig. 48 (a) or (b) for the prior art method can also be used. The case wherein the waveforms shown in Fig. 3 (a) are used for an eight gradation gray scale display is described in further detail below. Fig. 21 is an applied voltage waveform diagram of the embodiment achieving a eight gradations based on the display data shown in Fig. 22 and using the type of waveforms shown in Fig. 3 (a) as the row voltage waveforms applied to the row electrodes. Fig. 21 (a) shows the row voltage waveforms applied to row electrodes X 1 , X 2 , and X 3 , Fig. 21 (c) is the column voltage waveform applied to column electrode Y 1 , and Fig. 21 (d) is the voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 . This embodiment also simultaneously selects three sequential row electrodes, and while only the three row electrodes X 1 , X 2 , and X 3 are shown in Fig. 21, the next three row electrodes X 4 , X 5 , and X 6 are selected after row electrodes X 1 , X 2 , and X 3 have been selected as shown in Fig. 23, and voltages are applied to these electrodes similarly to row electrodes X 1 , X 2 , and X 3 . Thereafter, the next row electrodes are selected in order, three at a time, and one frame ends when all row electrodes have been selected. By thus applying row voltage waveforms as shown in Fig. 3 (a) to the three simultaneously selected row electrodes, the minimum pulse width Δt is twice the minimum pulse width Δt o of the prior art method shown in Fig. 48 as described above, and all selection periods t for each of the row electrodes in a frame comprise four subperiods t 1 to t 4 of length Δt. The above four subperiods t 1 to t 4 are each subdivided into three intervals a, b, c according to the number of bits of display data, and a column voltage specifically weighted according to the bits of the display data is applied to the each column electrode in each of these intervals. Specifically, the high bit of the display data, which is expressed as a three digit binary number as shown in Fig. 22, corresponds to the first interval a of each subperiod t 1 to t 4 , the middle bit corresponds to the next interval b, and the low bit corresponds to the last interval c, and the specifically weighted voltage ±V Y4 or ±V Y6 is applied according to the conditions described below for the high bit, ±V Y2 or ±V Y5 is applied for the middle bit, and ±V Y1 or ±V Y3 is applied for the low bit. It is to be noted that the ratio of the above voltage values is defined as: V Y1 : V Y2 : V Y4 = 1 : 2 : 4; V Y3 : V Y5 : V Y6 = 1 : 2 : 4 V Y1 : V Y3 = 1 : 3. As the conditions for the above, ON represents the state when the voltage waveform applied to a row electrode is positive and OFF when it is negative, and a display data value of 1 represents ON and 0 represents OFF; the ON/OFF state of each of the simultaneously selected row electrodes and the ON/OFF state of the corresponding display data bit at the intersection of each selected row electrode and the column electrode to which the voltage is to be applied are compared for each bit position as explained in more detail above, and a voltage specified according to the number of mismatches is applied to the column electrode. Specifically, when the number of mismatches between ON/OFF states of the row electrodes and those of the high bits of the display data is 0, 1, 2, or 3, voltage value -V Y6 , -V Y4 , V Y4 , or V Y6 , respectively, is applied in this embodiment; when the corresponding number of mismatches for the middle bit is 0, 1, 2, or 3, voltage value -V Y5 , -V Y2 , V Y2 , or V Y5 , respectively, is applied; and when the number of mismatches for the low bit is 0, 1, 2, or 3, voltage value -V Y3 , -V Y1 , V Y1 , or V Y3 , respectively, is applied. Therefore, in the embodiment in Fig. 21, the three row electrodes X 1 , X 2 , and X 3 are first selected, and during selection subperiod t 1 the selected row electrodes X 1 , X 2 , and X 3 are OFF, OFF, ON, respectively, and the high bits of the display data at the intersections of the column electrode Y 1 and these row electrodes X 1 , X 2 , and X 3 are OFF, ON, ON. Comparing both, the number of mismatches is 1, and the voltage - V Y4 is applied to column electrode Y 1 in the first interval a of the first subperiod t 1 . A weighted voltage is simultaneously applied to the other column electrodes Y 2 to Y m in the same manner. Next, during the next interval b of the first period t 1 , the ON/OFF state of row electrodes X 1 , X 2 , and X 3 is the same OFF, OFF, ON, and the middle bits corresponding to this interval b are, in order, ON, OFF, OFF; the number of mismatches is therefore 2, and voltage V Y2 is applied. The low bits corresponding to the last interval c are OFF, ON, OFF; the number of mismatches is therefore 2, and voltage V Y1 is applied. During the next subperiod t 2 , the voltages -V Y4 , V Y2 , and - V Y3 , respectively, are applied to the column electrode Y 1 during intervals a, b, c because the ON/OFF states of row electrodes X 1 , X 2 , and X 3 are OFF, ON, OFF, the high bits of the display data at the intersections of the column electrode Y 1 and these row electrodes X 1 , X 2 , and X 3 are OFF, ON, ON, respectively, and the number of mismatches is 1 as described above, the middle bits are ON, OFF, OFF and the number of mismatches is 2, and the low bits are OFF, ON, OFF and the number of mismatches is 0. The above sequence is also followed in the next subperiods t 3 and t 4 so that a column voltage corresponding to the number of mismatches is simultaneously applied to all column electrodes Y 1 to Y m and when selection of row electrodes X 1 , X 2 , and X 3 ends, the next row electrodes X 4 , X 5 , and X 6 are selected and a specified column voltage is applied in the same manner to column electrodes Y 1 to Y m , and one frame F ends when all row electrodes have been selected. Thereafter, the first row electrodes X 1 , X 2 , and X 3 are again selected in sequence and the next frame is started. The sign of the voltage applied to the row electrodes at this time is reversed, and the sign of the voltage applied to the column electrodes is accordingly reversed, to execute the so-called alternating current drive scheme. It is to be noted that it is not essential for the above voltage ratio to conform strictly to the above conditions, and it is necessary neither for the selection subperiods t 1 to t 4 nor the intervals a, b, c to be strictly of equal lengths. They can, for example, be adjusted according to the characteristics of the liquid crystals. In addition, the sequence of the intervals a, b, c can be changed. Furthermore, display of various numbers of gradations is possible by means of the same principle described above; for example, to achieve 16 gradations, it is sufficient to apply voltages weighted according to each bit of display data expressed using four bits. This is also true of the other embodiments described below. Embodiment 12 In the above embodiment 11, even though the selection period t has been described to be subdivided into four subperiods, since these subperiods are consecutive they do in fact form one single selection period t for the row electrodes in each frame F. However, the subperiods can also divide the selection period into plural separate parts in each frame F. For example, one field can be defined as the period required for all row electrodes to be selected in any one of the subperiods t 1 to t 4 , and with the four subperiods one frame F has four fields, or these subperiods can be subdivided and the sequence repeated for all of the row electrodes for each display data bit. Fig. 24, Fig. 26, and Fig. 27 show an example of this case. Fig. 24 is an applied voltage waveform diagram showing an embodiment in which the four consecutive subperiods t 1 to t 4 of the eleventh embodiment are separated into plural discrete subperiods for display drive, and Fig. 25 are waveforms of the row voltage applied to row electrodes X 1 to X 6 . First, row electrodes X 1 , X 2 , and X 3 are selected and a column voltage corresponding to the number of mismatches, separately calculated for each of the three bit positions of the display data, is sequentially applied to column electrodes Y 1 to Y m in the same way as in the eleventh embodiment above, row electrodes X 4 , X 5 , and X 6 are next selected and a column voltage is again applied as above, and field f 1 for subperiod t 1 ends when all row electrodes have been selected. Next, the groups of row electrodes are again selected in sequence from row electrodes X 1 , X 2 , and X 3 , field f 2 corresponding to the next subperiod t 2 is executed, etc. When all four fields f 1 to f 4 corresponding to the four subperiods t 1 to t 4 are completed, one frame F is completed. Fig. 26 shows the case in which execution is grouped for each display data bit, i.e., for each of the intervals a, b, c of the four subperiods tl to t4 in the above embodiment. First, the first intervals a of the four subperiods t 1 to t 4 in Fig. 24 are treated as one field f 1 until all row electrodes have been selected, and one frame is completed when field f 2 corresponding to intervals b and field f 3 corresponding to intervals c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed every field, and the voltage applied to the column electrodes is reversed accordingly. Fig. 27 shows the case in which execution is further divided in that each group of four intervals a, four intervals b and four intervals c, respectively, is not treated as one continuous block as in Fig. 26, but separated in time within a field. In other words, during a first field f 1 all groups of simultaneously selected row electrodes are selected in sequence, each group during an interval a. This process is then repeated three times until all groups have been selected for a total of four times interval a while display is being controlled by one of the bits of the display data. During a second field f 2 the same procedure is then performed for interval b while display is controlled by another one of the display data bits, and during a third field f 3 the same is finally done for interval c based on the third bit of the display data. In this example, the effect is the same as with the frame rate control modulation applied for each display data bit in the embodiment in Fig. 21 above. When the row electrode selection is executed plural times within one frame F as described above, the period in which the selected voltage is continuously not applied to each row electrode, i.e., to each pixel, can be shortened, the variation in display brightness can be reduced, and a loss of contrast can be prevented. Embodiment 13 In the eleventh embodiment above, one selection subperiod is subdivided into the same number of intervals as the number n of bits of the display data used to represent the gradation, i.e., three, and a column voltage of one of six levels V Y1 to V Y6 is selectively applied to the column electrodes, but the number of column voltage levels can be reduced by increasing the above number of divisions. For example, the effective voltage when driving the liquid crystal elements of a liquid crystal display panel, etc., is generally determined by the voltage value and the voltage applied time (pulse width), and the panel can be equally driven whether a high voltage is applied for a short time or a low voltage is applied for a long time. It is therefore possible to drive the liquid crystal elements with equivalent effect by selecting from the plural voltage levels a low level voltage and applying this voltage for an extended period rather than using a high level voltage. For example, by using voltage levels V Y5 and V Y2 in place of voltage levels V Y6 and V Y4 in the first embodiment and increasing the apply time, the elements can be driven in the same way as in the first embodiment. It is thereby possible to reduce the number of column voltage levels. Fig. 28 is an applied voltage waveform diagram showing an embodiment in which the number of column voltage levels is decreased. Whereas the selection subperiods t 1 , t 2 , t 3 , t 4 are subdivided into n intervals, i.e., a, b, and c, in Fig. 21, each selection subperiod is subdivided into (n+1) intervals, i.e., a, a, b, c, in the present embodiment, and the first two intervals a, a are assigned to the voltage apply time of the high display data bit. Specifically, voltage levels V Y5 and V Y2 corresponding to the middle bit, which are half the level of V Y6 and V Y4 , are respectively substituted for the V Y6 and V Y4 voltage levels corresponding to the high bit in the eleventh embodiment, and the apply time is twice that of the middle bit. As a result, the voltage applied to the liquid crystal elements and the time are twice the middle bit and four times the low bit values, and the weighting ratio for each bit is 1:2:4, the same as the case shown in Fig. 1. Thus, drive equivalent to the case of the eleventh embodiment can be achieved while using one less voltage levels applied to the column electrode. It is to be noted that the two highest voltage levels V Y6 and V Y4 in the eleventh embodiment are eliminated by this embodiment, but the voltage levels V Y3 and V Y1 for the low bit can be used, respectively, in place of the middle bit voltage levels V Y5 and V Y2 in the eleventh embodiment, using an apply time twice that of the low bits in the same way as above. Furthermore, it is also possible to eliminate four or more voltage levels, and reducing the number of voltage levels as described above is a particularly effective means of simplifying the drive circuit configuration when there are many gradation levels. Embodiment 14 In the thirteenth embodiment above it is also possible to separate or distribute the selection subperiods t 1 to t 4 within a frame F as in the twelfth embodiment, and Fig. 29, Fig. 30, and Fig. 31 show examples of this case. Fig. 29 is a waveform diagram for the case in which one selection subperiod is subdivided into (n+1) intervals, i.e., 4intervals, and these selection subperiods are separated into plural parts in each frame, specifically into four fields f. Thus, the period of one field is Δt·N/h. Note, however, that the selection subperiods can also be subdivided into two or three intervals. Fig. 30 shows a case similar to that of Fig. 26 in which all intervals assigned to the same bit of the display data of all subperiods are put together in one group and are treated as one block in the selection sequence. The first ones of the two intervals a in each of the four subperiods t 1 to t 4 in Fig. 28 form a first block, and the period until all row electrodes have been selected for this block is one field f 1 . The second ones of the two intervals a in each subperiod form a second block corresponding to a second field f 2 , the intervals b a third block corresponding to a third field f 3 and the intervals c a fourth block corresponding to a fourth field f 4 . One frame is completed when after field f 1 fields f 2 , f 3 and field f 4 completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly. Fig. 31 shows the case which corresponds to that of Fig. 27 and which differs from that of Fig. 31 in that execution is further divided in that in each field the intervals are not treated as one continuous block but are separated into discrete intervals. In other words, while in the embodiment of Fig. 30 each group is selected once in a field for a subperiod Δt = 4·Δt 1 , in the embodiment of Fig. 31 it is selected four times in a field, each time for an interval of Δt 1 . The embodiments shown in Fig. 30 and Fig. 31 above achieve the same effect as a gray scale display achieved by weighting the voltage applied to the column electrodes for each field. Embodiment 15 The effective voltage when driving the liquid crystal elements as described above is generally determined by the voltage value applied and the apply time (pulse width), and the desired gray scale display can be achieved by appropriately combining the apply time and the value of the voltage applied to the column electrodes. Fig. 32 is an applied voltage waveform diagram for an embodiment achieving a gray scale display with 16 gradations based on the display data shown in Fig. 33 by appropriately combining the apply time and the value of the voltage applied to the column electrode. This embodiment also sequentially selects groups of three row electrodes, and applies a row voltage to each of the simultaneously selected row electrodes during the four selection subperiods t 1 to t 4 as in the first embodiment above. Each of these four subperiods t 1 to t 4 is subdivided into six intervals a to f, and the first two intervals a, b correspond to the highest (most significant) bit in the four digit binary display data shown in Fig. 33, the next interval c corresponds to the second bit, the next two intervals d, e to the third bit, and the last interval f corresponds to the lowest (least significant) bit. Column voltage ±V Y4 or ±V Y6 is selectively applied to the column electrodes according to the following conditions for the highest two bits, and ±V Y1 or ±V Y3 is selectively applied for the lowest two bits. Note that the voltage value ratio is defined as: V Y1 : V Y3 = 1 : 3, V Y4 : V Y6 = 1 : 3; V Y1 : V Y4 = 1 : 4. As above, the highest two bits and the lowest two bits use the same two voltage combinations, respectively, and the highest bit and the second from the lowest bit are weighted relative to the second from highest bit and the lowest bit, respectively, by doubling the respective pulse widths; the two highest bits can thus express four gradations, the two lowest bits express four gradations, and combined they express 4 · 4 = 16 gradations. As conditions for the above, ON represent the state when the voltage waveform of the row electrode is positive and OFF when it is negative, and a display data value of 1 represents ON and 0 OFF; the ON/OFF state of the simultaneously selected row electrodes and the on/off state of the corresponding display data bits at the intersections of the selected row electrodes and the column electrode to which the voltage is to be applied are compared for each bit position, and a voltage specified according to the number of mismatches is applied to the column electrode. Specifically, when the number of mismatches between ON/OFF states of the row electrodes and those of the highest bit position is 0, 1, 2, or 3, voltage value -V Y6 , -V Y4 , V Y4 , or V Y6 , respectively, is applied to the column electrode in intervals a, b in this embodiment; for the corresponding number of mismatches relative to the second bit position, the same voltages are applied to the column electrode during interval c under the same conditions as above. When the corresponding number of mismatches relative to the third bit position is 0, 1, 2, or 3, voltage value -V Y3 , -V Y1 , V Y1 , or V Y3 , respectively, is applied to the column electrode in interval d, e; and for the corresponding number of mismatches relative to the lowest bit position, the same voltages are applied to the column electrode during interval f under the same conditions as above. Therefore, in Fig. 32, the three row electrodes X 1 , X 2 , and X 3 are first simultaneously selected, and the selected row electrodes X 1 , X 2 , and X 3 are OFF, OFF, ON, respectively, and the bits of the highest bit position of the display data at the intersections of the column electrode Y 1 and these row electrodes X 1 , X 2 , and X 3 represent OFF, OFF, ON. Comparing both, the number of mismatches is 0, and the voltage -V Y6 is applied to column electrode Y 1 in the first intervals a, b of the first subperiod t 1 . Next, the bits of the second from highest bit position represent OFF, ON, OFF and the number of mismatches is 2 when compared with the OFF, OFF, ON states of the row electrodes X 1 , X 2 , and X 3 ; voltage V Y4 is therefore applied in period interval c. The bits of the second from the lowest bit position represent ON, OFF, OFF, the number of mismatches is 2, and voltage V Y1 is applied in intervals d, e. The bits of the lowest bit position represent OFF, ON, OFF, the number of mismatches is 2, and voltage V Y1 is therefore applied during interval f. A weighted voltage is applied to the other column electrodes Y 1 to Y m in the same way. A column voltage corresponding to the number of mismatches is simultaneously applied to all column electrodes Y 1 to Y m in the following subperiods t 2 to t 4 in the same way, selection of row electrodes X 1 , X 2 , and X 3 ends, the next row electrodes X 4 , X 5 , and X 6 are selected, the specified column voltages are applied to the column electrodes Y1 to Y m in the same way as described above, and when all row electrodes have been selected, one frame F ends. The sign of the voltage applied to the row electrodes is then reversed because the first row electrodes X 1 , X 2 , and X 3 are again selected in sequence and the next frame begins, and the sign of the voltage applied to the column electrodes is also reversed for the so-called alternating current drive scheme. By thus achieving the desired gray scale display by appropriately combining the time and value of the voltage applied to the column electrodes as described above, a gray scale display can be achieved with fewer voltage levels, even when there are many gradations. It is to be noted that it is not essential to set the voltage rate as described above in the eleventh embodiment strictly according to the above conditions, and the subperiods t 1 to t 4 and intervals a to f do not need to be strictly equal. In addition, the order of the intervals a to f can be changed as appropriate. Embodiment 16 In the fifteenth embodiment above, the selection subperiods can be separated into plural discrete parts within a single frame F as in the twelfth embodiment. Fig. 34 shows this case. The subperiods t 1 to t 4 in Fig. 32 are separated into four parts in a single frame F as in the twelfth embodiment, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times corresponding to four fields, one field for each subperiod, in one frame F. Though not shown in the figures, the fifteenth embodiment can also be driven blockwise for each display data bit or can be further divided as shown in Fig. 30 and Fig. 31, respectively, in the fourteenth embodiment. Embodiment 17 In the embodiments 11 to 16 above the voltage-time area of the voltage applied to the column electrodes, i.e. either the voltage level or the time of applying it or both, is weighted corresponding to the display data bits for each column electrode to achieve a gray scale display, but it is also possible to weight or change the voltage level applied to the row electrode, for a gray scale display. Fig. 35 is an applied voltage waveform diagram for an embodiment changing the voltage level applied to the row electrodes according to the display data bits to display eight gradations based on the display data shown in Fig. 22 similarly to the eleventh embodiment. As in the eleventh embodiment, the row electrodes are selected sequentially, three at a time, and voltage V X4 or -V X4 is applied to each row electrode for the high display data bit, V X2 or -V X2 is applied for the middle bit, and V X1 or -V X1 is applied for the low bit where the ratio V X1 :V X2 :V X4 is 1:2:4. The ON/OFF states of the row electrodes X 1 , X 2 , and X 3 and the display data ON/OFF states are compared bit by bit, and when the number of mismatches is 0, 1, 2, and 3, respectively, voltages -V Y3 , -V Y1 , V Y1 , and V Y3 are applied to the column electrodes Y 1 ,...; the V Y1 :V Y3 ratio is 1:3. If the number of voltage levels on the row electrode side is increased rather than increasing the voltage levels on the column electrode side as in the eleventh embodiment, the number of voltage levels applied to the column electrode can be significantly reduced, and the structure of the column electrode-side drive circuit can be simplified. Embodiment 18 In the seventeenth embodiment above, the selection subperiods can be separated into plural discrete parts within a single frame F as in the twelfth embodiment. Fig. 36, Fig. 37, and Fig. 38 show this case. Fig. 36 shows the case in which the subperiods t 1 to t 4 in Fig. 35 are separated into four parts in a single frame F as in the twelfth embodiment, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times in one frame F. Fig. 37 shows the case wherein the display is driven blockwise for each display data bit, i.e., in each of the intervals of the four subperiods t 1 to t 4 in the previous embodiment. Specifically, the first interval a in the four subperiods t 1 to t 4 in Fig. 35 is treated as one field f 1 until all row electrodes have been selected, and one frame is completed when field f 2 corresponding to the other interval b and field f 3 corresponding to interval c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly. As shown in Fig. 38, it is also possible to further divide the periods so that all row electrodes are sequentially selected in each interval. The same effects obtained with the twelfth embodiment can thus be obtained by driving the display in plural discrete parts within one frame as described above. Embodiment 19 In the seventeenth embodiment above, it is also possible to increase the number of selection period subdivisions to reduce the number of applied voltage levels as in the thirteenth embodiment. This case is illustrated in Fig. 39. Each of the subperiods t 1 to t 4 in Fig. 35 is subdivided into four intervals in one frame F as in Fig. 28 with the first two intervals being the apply time for the high bit, and the other intervals being the apply times for the middle and low bits, respectively. Note that the relationship of the applied voltages in this embodiment is V X1 : V X2 = 1:2, and V Y1 :V Y3 = 1:3. Embodiment 20 In the nineteenth embodiment above, the selection subperiods can also be separated into plural discrete parts within a single frame F. Fig. 40, Fig. 41, and Fig. 42 show this case. Fig. 40 shows the case where the subperiods t 1 to t 4 in Fig. 39 are separated into four parts in a single frame F. As in Fig. 25, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times in one frame F. Fig. 41 shows the case in which execution is grouped for each interval of the four subperiods t 1 to t 4 in the previous embodiment; the first interval a of intervals a, a in the four subperiods t 1 to t 4 in Fig. 39 is treated as one field f 1 until all row electrodes have been selected, and one frame is completed when field f 2 corresponding to the other interval a, field f 3 corresponding to interval b, and field f 3 corresponding to interval c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly. As shown in Fig. 42, it is also possible to further divide the periods so that all row electrodes are selected in each interval. The same effects obtained with the twelfth embodiment can thus be obtained by driving the display in plural parts within one frame as described above. Embodiment 21 Even in the case whereby a desired gray scale display is achieved by appropriately combining the apply time and the value of the voltage applied to the column electrodes as in the fifteenth embodiment above, drive identical to that of the fifteenth embodiment is possible by increasing the number of voltage levels on the row electrode side instead of increasing the number of voltage levels on the column electrode side as in the sixteenth embodiment. Fig. 43 shows an example of this. In this example, voltage V X4 or -V X4 is used as the applied voltage level to each row electrode for the two highest display data bits, V X1 or -V X1 is applied for the two lowest bits, and the ratio V X1 :V X4 is 1:4. The ON/OFF states of the row electrodes X 1 , X 2 , and X 3 and the display data ON/OFF states are compared bit by bit, and when the number of mismatches is 0, 1, 2, and 3, respectively, voltages -V Y3 , -V Y1 , V Y1 , and V Y3 are applied to the column electrodes Y 1 ,...; the V Y1 :V Y3 ratio is 1:3. Embodiment 22 In embodiment 21 above, the selection subperiods can also be separated into plural discrete parts within a single frame F. Fig. 44 shows this case. The subperiods t 1 to t 4 in Fig. 43 are separated into four parts in a single frame F as in Fig. 34, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times in one frame F. In this embodiment it is also possible to further divide and drive as in the previous embodiment. Though not shown in the figures, embodiment 21 can also be driven blockwise for each display data bit or can be further divided as in embodiment 20 shown in Fig. 41 and Fig. 42, respectively. It is to be noted that while each of the above embodiments has been described as simultaneously selecting three row electrodes, a gray scale display with the desired number of gradations is possible by simultaneously selecting two, four, or more row electrodes and applying the same concepts described above. For example, in an embodiment simultaneously selecting six row electrodes, selection subperiods divided into eight parts t 1 to t 8 are provided in one frame period, and voltages as shown in the table below are applied in each of the selection subperiods t 1 to t 8 to the six simultaneously selected row electrodes X 1 to X 6 . t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 X 1 V X1 V X1 V X1 V X1 -V X1 -V X1 -V X1 -V X1 X 2 V X1 V X1 -V X1 -V X1 -V X1 -V X1 V X1 V X1 X 3 V X1 V X1 -V X1 -V X1 V X1 V X1 -V X1 -V X1 X 4 V X1 -V X1 -V X1 V X1 V X1 -V X1 -V X1 V X1 X 5 V X1 -V X1 -V X1 V X1 -V X1 V X1 V X1 -V X1 X 6 V X1 -V X1 V X1 -V X1 -V X1 V X1 -V X1 V X1 Note that 0 V is applied during the unselected period. The specified row voltage is applied to each of the row electrodes X 1 to X 6 as described above, and the specified column voltage is simultaneously applied as described in the various embodiments to each of the column electrodes. In addition, the waveform of the voltages applied to the row electrodes shall not be limited to the embodiments, and the waveforms can be changed to the kind of waveforms as shown in Fig. 48 (a) and (b) or Fig. 3 (a) and (b), or the pulse widths thereof can be appropriately selected or the order changed insofar as the waveforms applied to the simultaneously selected row electrodes do not become intermixed and the row electrodes can be separately driven. The concept of simultaneously selecting plural row electrodes and dividing the selection period into plural parts (subperiods) in one frame for a liquid crystal device drive as described above can also be applied to drive liquid crystal devices using non-linear (including MIM) elements.

Claims: A method of multiplex driving a matrix type liquid crystal electro-optical device comprising a liquid crystal layer provided between a first substrate carrying row electrodes (Xl, X2,...) and a second substrate carrying column electrodes (Y1, Y2,...) said row and column electrodes defining a matrix of pixels, said method comprising: dividing said row electrodes into groups (X1, X2, X3; X4, X5, X6; X 1 , X2, X3, Xn+1; X4, X5, X6, Xn+2) simultaneously selecting, during a selection period, the row electrodes of one group by applying a respective row voltage waveform to each of them while applying a non-selection voltage to the row electrodes of all other groups, and sequentially selecting each group, wherein said row voltage waveforms are composed of a plurality of row select pulses defining a corresponding plurality of row select patterns, and applying a respective column voltage to each column electrode said column voltage determined in response to each row select pattern and display data, the method being characterized by dividing said selection period into plural subperiods (t1, t2, t3, t4; Δto; Δt; Δt1) and weighting for each subperiod, in accordance with gradation information of grey scale display data, either the pulse width and/or the level of the voltage applied to a respective column electrode, the level of the respective voltage applied to each selected row electrode or the pulse width and the level of the respective voltage applied to each selected row electrode. The method of claim 1 wherein each subperiod (t1, t2, t3, t4) is subdivided into a number of intervals (a, b; a, b, c) corresponding to the number of bits of multi-bit grey scale display data, each interval being allocated to another one of the bits and the level of the row or column voltage applied during each interval is weighted in accordance with the respective bit. The method of claim 1 wherein each subperiod (t1, t2, t3, t4) is subdivided into more intervals (a, a, b, c; a - f) than the number of bits multi-bit grey scale display data, and plural of the intervals are allocated to the same bit and the level of the row or column voltage applied during each interval is weighted in accordance with the respective bit. The method according to any one of the preceding claims wherein said subperiods of each selection period form a continuous period. (Figs. 21, 28, 32, 35, 39, 43) The method according to any one of claims 1 to 3, wherein said subperiods (Δt in Figs. 24, 29, 34, 36, 40, 44) are separated in time such that when the groups of row electrodes are sequentially selected, each is selected for the duration of a subperiod, this being repeated for each of the other subperiods. The method according to any one of claims 1 to 3 wherein each subperiod (Δt in Figs. 26, 30, 37, 41) is allocated to one bit of multi-bit grey scale display data and said pulse level or said pulse width and level of the voltage applied during each subperiod is weighted in accordance with the respective bit. The method according to claim 2 or 3, wherein said intervals (Δt1 in Figs. 27, 31, 38, 42) are separated in time such that when the groups of row electrodes are sequentially selected, each is selected for the duration of one interval, this being repeated for each of the other intervals and each subperiod. The method according to any one of claims 1 to 7 wherein, when a frame is defined as the time period equal to said selection period times the number of row electrode groups, said column voltages are modulated during a period of plural frames such as to obtain additional gradations of the gray scale display. The method according to any one of the preceding claims wherein each group of simultaneously selected row electrodes comprises at least one virtual row electrode and the display state of imaginary pixels corresponding to the virtual row electrode is set in accordance with the row select pattern and the display data corresponding to the real row electrodes such as to reduce the number of required column voltage levels. The method according to any one of the preceding claims wherein, when a frame is defined as the time period equal to said selection period times the number of row electrode groups, the order of said row select patterns is changed among the groups within each frame or is changed among the frames. The method according to any one of the preceding claims in combination with claim 2 or 3, wherein, when a frame is defined as the time period equal to said selection period times the number of row electrode groups, the order in which said intervals are allocated to said bits is changed among the column electrodes and/or among the groups within each frame or among the frames. The method of claim according to any one of the preceding claims wherein, when a frame is defined as the time period equal to said selection period times the number of row electrode groups, the polarity of the voltages applied to the row electrodes and to the column electrodes is reversed every frame or within each frame. A drive circuit of a matrix type liquid crystal electro-optical device comprising a liquid crystal layer provided between a first substrate carrying row electrodes (X1, X2,...) and a second substrate carrying column electrodes (Y1, Y2,...) said row and column electrodes defining a matrix of pixels, for performing the method of claim 1, said drive circuit comprising: a row electrode driver (1) for simultaneously selecting, during a selection period, the row electrodes of one group of said row electrodes by applying a respective row voltage waveform to each of them while applying a non-selection voltage to the row electrodes of all other groups, and sequentially selecting each group, wherein said row voltage waveforms are composed of a plurality of row select pulses defining a corresponding plurality of row select patterns, a column electrode driver (2) for applying a respective column voltage to each column electrode said column voltage determined in response to each row select pattern and display data, a scan data generating circuit (5) for generating said row select patterns, calculating means (4) receiving said row select patterns and the display data for each group of simultaneously selected row electrodes, for calculating in response to each row select pattern and each display data column voltage data, means for transferring said column voltage data to the column electrode driver (2) and for simultaneously transferring the row select pattern to the row electrode driver (1), characterized by means for dividing said selection period into plural subperiods (t1, t2, t3, t4; Δto; Δt; Δt1) and for weighting for each subperiod, in accordance with gradation information of grey scale display data, either the pulse width and/or the level of the voltage applied to a respective column electrode, the level of the respective voltage applied to each selected row electrode or the pulse width and the level of the respective voltage applied to each selected row electrode. A matrix type liquid crystal display device including a drive circuit as claimed in claim 13.

Inventors: IINO SHOICHI, ITO AKIHIKO, IINO, SHOICHI, ITO, AKIHIKO, IINO, SHOICHI SEIKO EPSON CORPORATION, ITO, AKIHIKO SEIKO EPSON CORPORATION
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1993
Main classification: G09G3
IPC codes: G09G3, G02F1