Integrated structure current sensing resistor for power MOS devices, particularly for overload self-protected power MOS devices

Abstract: An integrated structure current sensing resistor for a power MOS device consists of a doped region (20,21,50) extending from a deep body region (2) of at least one cell (1a) of a first plurality of cells, constituting a main power device, to a deep body region (2) of a corresponding cell (1b) of a second smaller plurality of cells constituting a current sensing device.

Description: The present invention relates to an integrated structure current sensing resistor for power MOS devices, particularly for overload self-protected power MOS devices. Power MOS devices can feature an integrated circuitry suitable to protect the power device against excessive current flow, due for example to output load short-circuit. A typical solution provides for a negative feedback loop, which comprises a current sensing MOSFET, whose drain and gate are respectively connected to the drain and the gate of the main power MOSFET, and whose source is connected, through a current sensing resistor, to the source terminal of the integrated component. The base-emitter junction of a bipolar junction transistor (BJT) is connected across said sensing resistor, while the collector of the BJT is connected to the common gate of the two MOSFET. A gate resistor is finally connected in series between an external gate terminal of the integrated component and said common gate. In practical implementations, both the sensing MOSFET and the main power MOSFET are made up of similar cells, even if the latter comprises a much larger number of such cells than the former. The current flowing through the sensing MOSFET, which is a small fraction of the current flowing through the main power MOSFET, generates a voltage drop across the sensing resistor whose value is chosen in such a way that when the current flowing through the power MOSFET exceeds a prescribed maximum value, the fractional current flowing through the sensing resistor generates a voltage drop sufficient to turn on the BJT. This last, by draining current from the gate resistor, causes the voltage applied to the gate of the two MOSFETs to decrease, thus preventing the current flowing through them from further increasing. Furthermore, the positive thermal coefficient of such feedback loop improves the protecting performances of this protection circuit, since at higher temperature the maximum value for the current decreases. In the International Application NO WO 91/09424 a power device is described which includes in the same substrate as the power transistor a feedback loop of the type described above. The sensing resistor is made up of a polysilicon strip obtained simultaneously with the polysilicon gate layer of the MOS cells. This solution requires a dedicated area on the surface to allocate the sensing resistor, which is external to the sequence of source cells. WO-A-8 908 928 discloses a structure substantially according to the preamble of claim 1. In view of the state of the art described, the object of the present invention is to provide a power MOS device integrated structure with integrated sensing resistor which leads to a minimum waste of area. According to the present invention, such object is attained by means of a power MOS device integrated structure as set forth in claim 1. In a first embodiment of the present invention, the integrated structure current sensing resistor comprises an extended deep body region of the first conductivity type, extending from and connecting the deep body region of said at least one cell of the first plurality to the deep body region of said corresponding cell of the second plurality. In a second embodiment of the present invention, the integrated structure current sensing resistor comprises a semiconductor region of the second conductivity type, arranged within an extended high doped deep body region of the first conductivity type extending from and connecting the deep body region of said at least one cell of the first plurality to the deep body region of said corresponding cell of the second plurality. In a third embodiment of the present invention, the integrated structure current sensing resistor comprises a low doped body region of the first conductivity type extending from and connecting the deep body region of said at least one cell of the first plurality to the deep body region of said corresponding cell of the second plurality. Thanks to the present invention, it is possible to obtain an integrated structure current sensing resistor without introducing irregularities in the array of cells of the power device, and consequently reducing the area required. Three embodiments of the present invention will now be described in greater detail with reference to the annexed drawings, wherein: Figure 1 is a cross-sectional view of an integrated structure current sensing resistor according to a first embodiment of the invention. Figure 2 is a cross-sectional view of an integrated structure current sensing resistor according to a second embodiment of the invention. Figure 3 is a cross-sectional view of an integrated structure current sensing resistor according to a variation of said second embodiment. Figure 4 is a cross-sectional view of an integrated structure current sensing resistor according to a third embodiment of the invention. Figures 5-9 are cross-sectional views of a sequence of steps in a fabrication process of a power MOS device provided with the integrated structure current sensing resistor according to the first embodiment of the invention. A power MOS device, for example an n-channel power MOSFET, is made up of a plurality of cells 1a and 1b, each comprising a high doped p + deep body region 2, extending from a top surface of a semiconductor material into a low doped n - epitaxial layer 3, grown over a high doped n + substrate 4, representing a drain region of the power MOSFET. On one side of said p + deep body region 2, a low doped p - channel regions 5 is provided, and a highly doped n + source region 6 extends partially in the p + deep body region 2 and partially in said channel region 5. A polysilicon gate layer 7, insulated from the top surface of the semiconductor by a thin gate oxide layer 8, is superimposed over said channel region 5 to allow, under particular biasing conditions, the formation of a conductive channel. An array of cells 1a, connected each other by means of a first source electrode layer Sa which contacts their p + deep body region 2 and their n + source region 6, constitutes a main power MOSFET, while a smaller array of cells 1b, which are in turn connected each other in the same way by means of a second source electrode layer Sb, constitutes a sensing MOSFET. In a first embodiment, shown in Figure 1, the p + deep body region 2 of at least one of the main power MOSFET's cells 1a is extended in order to be merged with the p+ deep body region 2 of a corresponding cell 1b of the sensing MOSFET, and an extended deep body region 20 is thus obtained which is contacted on opposite sides by the source electrodes Sa and Sb respectively. Such source electrodes Sa and Sb are thus electrically connected by the extended p + deep body region 20, which introduces, in series connection to the source electrode Sb of the sensing MOSFET, a sense resistor Rs. In a second embodiment, shown in Figure 2, the p + deep body region 2 of at least one of the main power MOSFET's cells 1a is again extended and merged with the p+ deep body region 2 of a corresponding cell 1b of the sensing MOSFET, to obtain, as in the previous embodiment, an extended deep body region 20. An extended n + semiconductor region 21 is then provided within the deep body region 20 and is merged with the n + source region 6 of said corresponding cell 1b. The source elctrodes Sa and Sb contact two sides of the extended n+ semiconductor region 21, which introduces, in series connection between the source electrodes Sa and Sb, a sense resistor Rs. The extended p + deep body region 20 insulates the extended n + semiconductor region 21 from the n - epitaxial layer 3, and is connected to the source electrode Sa to prevent all parasitic actions. The first source electrode Sa is also connected to an external source terminal S of the integrated component. The polysilicon gate layer 7 is connected, through an integrated gate resistor not shown in the drawings, to a gate terminal, while a bipolar junction transistor, equally not shown, has its base-emitter junction connected across the sense resistor Rs. A negative feedback loop of the type described before is thus obtained. In a variation of the second embodiment, shown in Figure 3, the extended p + deep body region 20 and the extended n + semiconductor region 21 are both contacted on opposite sides, thus introducing, in series connection between source electrodes Sa and Sb, two parallely connected resistors Rsp and Rsn. In a third embodiment shown in Figure 4, there is no extended p + deep body region; a p - body region 50 is formed so as to connect the deep body region 2 of at least one cell 1a of the first plurality to the deep body region 2 of a corresponding cell 1b of the second plurality. Since the resistivity of the p - regions is considerably higher than that of the p + regions, the resistance introduced by the body region 50 is considerably higher than that introduced by the region 20 of the previous embodiments. In all of the described embodiments, there can be several extended regions connected in parallel between the first and the second pluralities of cells: the resistance between the two source regions will be given by the parallel of all of them. A fabrication process suitable to obtain a power MOS device featured by the integrated structure current sensing resistor according to the first embodiment of the present invention is shown in Figures 5-9 and includes the same steps of a known process for the fabrication of a power MOS device, and starts with the growth of the low-doped epitaxial layer 3, for example of the n type, over the highly-doped semiconductor substrate 4, in this example of the n + type. After a field oxide layer 18 has been grown, a masked implantation and subsequent diffusion of a high concentration of a p type dopant is performed, in order to form the plurality of p + deep body regions 2 constituting the main and sensing cells 1a and 1b of the power MOSFET, and the extended p + deep body region 20 (Figure 5). After a masking step, active areas are defined, on the surface of the epitaxial layer 3, a thin gate oxide layer 8 is then grown over said active areas, and a polysilicon gate layer 7 is subsequently deposited over said gate oxide layer 8, and doped to achieve low resistivity (Figure 6). The polysilicon gate layer 7 is then selectively etched outside said gate regions, and after a masking step, a low concentration of a p type dopant is implanted and diffused under said gate regions to form p - type channel regions 5 of each cell 1a and 1b of the power MOSFET (Figure 7). The following step is the masked implant and diffusion of a high concentration of an n type dopant at the sides of said gate regions, to form the source regions 6 of the cells 1a and 1b, and the deposition of an insulating oxide layer 17 over the polysilicon gate layer 7 (Figure 8). The final steps of the process involve the definition of contact areas, the deposition of a conductive layer suitable to form the two source electrodes Sa and Sb, and the deposition of a passivating layer (Figure 9). The metallization of the bottom surface of the substrate 4 is also provided, in order to form a contact to the drain of the power MOSFET. As it is clear to anyone skilled in the art, the structure according to the invention can also be used in Insulated Gate Bipolar Transistors (IGBTs), simply by starting the process flow with a p-type, heavily doped substrate, on which an n-type epilayer similar to the epilayer 3 described before is then grown. Also, the invention applies to p-channel devices; in this case it is necessary to substitute p-type regions for n-type regions and viceversa. The invention applies also to integrated devices, where the drain electrode lies on the same surface as the source and gate electrodes; the modifications to the described process flow are well known to anyone skilled in the art.

Claims: A power MOS device integrated structure comprising a main power device and a current sensing device respectively made up of a first plurality and a second plurality of identical cells (1a,1b) arranged in an array, each cell comprising a high doped deep body region (2) of a first conductivity type extending from the top surface into a semiconductor material (3) of a second conductivity type, a low doped channel region (5) of said first conductivity type arranged laterally to said deep body region (2) and a source region (6) of said second conductivity type extending partially in said deep body region (2) and partially in said channel region (5), a conductive gate layer (7), insulated from a top surface of the semiconductor material (3) by a thin gate oxide layer (8) superimposed over said channel region (5), the deep body region (2) and the source region (6) of each cell (1a,1b) of said first and second pluralities being electrically connected to each other and to all the other cells (1a,1b) of the same plurality by means of respective first and second superimposed conductive source electrodes (Sa,Sb), the current sensing device comprising a current sensing resistor, characterized in that said resistor (Rs) comprises at least one doped region (20,21,50) within said semiconductor material (3) and extending from the deep body region (2) of at least one cell (1a) of the first plurality to the deep body region (2) of a corresponding cell (1b) of the second plurality. A power MOS device integrated structure according to claim 1, characterized in that said at least one doped region is an extended high doped deep body region (20) of the first conductivity type, extending from and connecting the deep body region (2) of said at least one cell (1a) of the first plurality to the deep body region (2) of said corresponding cell (1b) of the second plurality. A power MOS device integrated structure according to claim 2, characterized in that said resistor further comprises a semiconductor region (21) of the second conductivity type, arranged within said extended deep body region (20) of the first conductivity type. A power MOS device integrated structure according to claim 1, characterized in that said at least one doped region is a low doped body region (50) of the first conductivity type extending from and connecting the deep body region (2) of said at least one cell (1a) of the first plurality to the deep body region (2) of said corresponding cell (1b) of the second plurality. A power MOS device integrated structure according to anyone of the preceding claims, characterized in that said resistor comprises a plurality of parallely connected doped regions (20,21,50), each extending from the deep body region (2) of a respective cell (1a) of the first plurality of cells to the deep body region (2) of a corresponding cell (1b) of the second plurality of cells. A power MOS device integrated structure according to anyone of the preceding claims, characterized in that said first conductivity type regions (2,5,20,50) are semiconductor regions doped with acceptor impurities, while said second conductivity type regions (3,6,21) are semiconductor regions doped with donor impurities. A power MOS device integrated structure according to claim 6, characterized in that said high doped deep body regions (2) and said high doped extended deep body region (20) of a first conductivity type are p + type semiconductor regions. A power MOS device integrated structure according to claim 6, characterized in that said low doped channel regions (5) and low doped body region (50) of a first conductivity type are p - type semiconductor regions. A power MOS device integrated structure according to claim 6, characterized in that said source regions (6) of a second conductivity type are n + type semiconductor regions. A power MOS device integrated structure according to anyone of claims 1 to 5, characterized in that said first conductivity type regions (2,5,20,50) are semiconductor regions doped with donor impurities, while said second conductivity type regions (3,6,21) are semiconductor regions doped with acceptor impurities. A power MOS device integrated structure according to claim 10, characterized in that said high doped deep body regions (2) and said extended deep body region (20) of a first conductivity type are n + type semiconductor regions. A power MOS device integrated structure according to claim 10, characterized in that said low doped channel regions (5) and low doped body region (50) of a first conductivity type are n - type semiconductor regions. A power MOS device integrated structure according to claim 10, characterized in that said source regions (6) of a second conductivity type are p + type semiconductor regions. A power MOS device integrated structure according to anyone of the preceding claims, characterized in that said semiconductor material (3) of the second conductivity type is an epitaxial layer (3) grown on a semiconductor substrate (4). A power MOS device integrated structure according to claim 14, characterized in that said semiconductor substrate (4) is of said first conductivity type. A power MOS device integrated structure according to claim 14, characterized in that said semiconductor substrate (4) is of said second conductivity type.

Inventors: ZAMBRANO RAFFAELE, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1993
Main classification: H01L27
IPC codes: H01L29, H01L27