LOGIC LEVEL CURRENT AND VOLTAGE INDEPENDENT RESTRAINT SYSTEM

Abstract: A logic level current and voltage independent restraint system for generating an output drive signal which is independent of an output driver circuit includes a logic level output control circuit (12) and an output driver circuit (14). The output driver circuit (14) is formed of a first transistor (Q1), a second transistor (Q2), and a load resistor (R1).

Description: LOGIC LEVEL CURRENT AND VOLTAGE INDEPENDENT RESTRAINT SYSTEM BACKGROUND OF THE INVENTION This invention relates generally to electrical distribution systems of the type having a plurality of circuit breakers spaced upstream and downstream along the stream of the distribution system from a power supply source to a plurality of separate loads. More par- ticularly, the present invention relates to an improved logic level current and voltage independent restraint system for use in such type of electrical distribution system for generating an output drive signal which is independent of an output driver circuit. As is generally well-known in the art of electrical distribution systems, there is typically provided a plurality of protective devices such as main, tie and/or branch circuit breakers spaced upstream and downstream along the stream of distribution system from a power supply source to a plurality of electrical loads. The circuit breakers are used for interrupting excessive current flow so as to protect electrical conductors or other distribution equipment connected thereto from damage. Generally, the electrical distribution system would include an upstream protective device (i.e., main circuit breaker) located close to the power source and capable of interrupting all of the electrical loads served by the power source. Further, the upstream protective device is succeeded by a plurality of down¬ stream protective devices (i.e., branch circuit breakers) of successively lesser interrupting capability. Each of the corresponding downstream protective devices is cap¬ able of interrupting the respective electrical load that it is designed to protect. It is often desirable to open or trip the circuit breaker (i.e., branch circuit breaker) which is closest to the location of the malfunction causing a fault con¬ dition so as to isolate the fault from the power supply source rather than to interrupt a circuit breaker (i.e. , main or tie circuit breaker) further upstream of the fault. The reason for this is that if the main or tie circuit breaker is tripped electrical power would be dis¬ connected to a greater area of the entire distribution system rather than only the single load connected to the branch circuit breaker on which the fault occurred. Consequently, it is therefore desirable that the main and tie circuit breakers should have a longer delay period following detection of a fault condition before they initiate a tripping operation. The coordination of the delay times among the main, tie and branch circuit breakers for various types of faults (i.e., overcurrent, short circuit and ground) so as to isolate only the fault condition is achieved by control or restraint signals from a restraint system. For example, when a downstream circuit breaker detects a fault it sends an active state restraint signal to one or more upstream circuit breakers instructing such upstream circuit breaker(s) to carry out a selected or programmable time delay. However, if the upstream circuit breaker(s) do not receive a signal to delay or restrain from a downstream circuit breaker, they will operate immediately upon sensing the fault condition since the programmed trip delay setting will be ignored. A prior art restraint system for communication with other circuit breakers in the same electrical distribu- tion system is shown in Figure 1 which includes a single output driver device in the form of an N-channel field- effect transistor 2. An upstream restraint signal is generated at the source electrode of the transistor 2 and is connected to a plurality of restraint loads 4 via an output terminal 6. The restraint signal is used to provide information on short circuit or ground fault con¬ dition to an increased number of upstream circuit breakers. Since the restraint loads 4 are defined by any number of upstream circuit breakers, this load will be increasingly varied at different times. The amount of drive current available at the source electrode is known to be determined by the gate-to-source voltage V GS . Thus, dependent upon the number of upstream circuit breakers, as the voltage at the output terminal 6 or source electrode of the transistor 2 begins to rise due to an increasing load, the voltage V GS will begin to drop, and the transistor 2 will begin to shut-off. If the source voltage rises high enough, the transistor will finally reach a region where its drive current is limited by the voltage V GS . As a result, the voltage level at the output terminal 6 required for an active state restraint signal will not be achieved. When this happens, the upstream restraint signal being received by the various downstream circuit breakers for proper distribution of the ground fault and short circuit information will be misrepresented. Another prior art restraint system is shown in Figure 2 which includes a single output driver device in the form of an NPN-type bipolar transistor 2a. The up¬ stream restraint signal is generated at the emitter of the transistor 2a and is connected to the plurality of restraint loads 4 via the output terminal 6. Again, the amount of output drive available at the emitter is known to be limited to the DC current gain of the transistor 2a multiplied by its base current. Thus, when the restraint loads are increased the voltage at the output terminal 6 will likewise be decreased to a level below that which is required for an active state restraint signal. Therefore, it would be desirable to provide a restraint system for generating an output drive which is independent of drive voltage/current characteristics of an output driver device. Accordingly, the present in¬ vention represents an improvement over the prior art restraint systems of Figures 1 and 2. Specifically, the logic level current and voltage independent restraint system of the instant invention includes an output driver circuit formed of a first transistor, a second transistor and a load resistor. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide an improved restraint system for use in an electrical distribution system which is relatively simple and economical to manufacture and assemble, but yet overcomes the disadvantages of the prior art circuits. It is an object of the present invention to provide an improved restraint system for generating an upstream restraint signal which is independent of an output driver circuit. It is another object of the present invention to provide an improved logic level current and voltage independent restraint system for generating an output drive signal which is independent of an output driver circuit and which provides simultaneously for short circuit protection. It is still another object of the present invention to provide an improved logic level current and voltage independent restraint system which includes an output driver circuit formed of a first transistor, second transistor and a load resistor. In accordance with these aims and objectives, the present invention is concerned with the provision of a logic level current and voltage restraint system used in an electrical distribution system of the type having a plurality of circuit breakers spaced upstream and down¬ stream along the stream of the distribution system from a power source to a plurality of separate restraint loads. The restraint system generates an upstream restraint signal which is independent of an output driver circuit. The restraint system includes a logic control circuit and an output driver circuit. The logic control circuit is responsive to downstream logic signals for generating an upstream logic restraint signal. The output driver circuit is formed of a first transistor, a second transistor, and a load resistor. The first transistor has one of its conduction path electrodes connected to a power supply voltage via the load resistor and its other one of its conduction path electrodes connected to a ground potential. The first transistor has its control electrode connected to receive the upstream logic restraint signal. The second transistor has one of its conduction path electrodes con¬ nected also to the power supply voltage and its other one of its conduction path electrodes coupled to an output drive terminal for generating the upstream restraint signal. The second transistor has its control electrode connected to the junction of the load resistor and the one conduction path electrode of the first transistor. A plurality of separate restraint loads are connected to the output terminal. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects and advantages of the present invention will become more fully apparent from the following detailed description when read in con¬ junction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein: Figure 1 is a circuit diagram of a prior art restraint system utilizing a single field-effect transistor; Figure 2 is a schematic diagram of another prior art restraint system utilizing a single bipolar transistor; and Figure 3 is a circuit diagram of a restraint system, constructed in accordance with the principles of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings, there is illustrated in Figure 3 a circuit diagram of a logic level current and voltage independent restraint system 10 for use in communicating with other circuit breakers in an elec¬ trical distribution system, which is constructed in ac¬ cordance with the principles of the present invention. The restraint system 10 includes a logic level output control circuit 12 and an output driver circuit 14. The restraint system is designed to provide an output drive or restraint output signal RS on an output drive terminal 16 which is independent of the drive voltage and current characteristics of the output driver circuit 14. The restraint output signal RS provides an active or inactive information state of downstream restraint signals relating to short circuit or ground fault conditions. The output terminal 16 is connected to a plurality of separate restraint loads 18 which is variable and is formed by any multiple number of upstream circuit breakers. The logic level output control circuit 12 receives a plurality of downstream logic signals Dl, D2, ...Dn on respective input terminals 20a, 20b, ...20n for indicat¬ ing the active or inactive information state of corre¬ sponding downstream restraint signals. Each of the logic signals Dl through Dn may be at a high or low logic r level. The control circuit 12 generates on output terminal 2 an upstream logic restraint signal UR based upon the downstream logic signals. The active state of the upstream logic restraint signal UR is a high logic level, and the inactive state corresponds to a low logic level. Normally, the upstream logic restraint signal UR is inactive or restraint off (low logic level) . The output driver circuit 14 includes an N-channel field-effect transistor Ql, a P-channel field-effect transistor Q2, a first resistor Rl, and a second resistor R2. The N-channel transistor Ql has its gate electrode connected to the output terminal 22 of the control circuit 12 for receiving the upstream logic restraint signal UR. The drain electrode of the transistor Ql is connected to one end of the resistor Rl and to the gate of the P-channel transistor Q2. The other end of the first resistor Rl is connected to a power supply potential or voltage Vdd, which is typically at +5.0 volts. The source electrode of the transistor Ql is connected to a ground potential GND. The source electrode of the P-channel transistor Q2 is also connected to the power supply voltage Vdd. The drain electrode of the transistor Q2 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the output drive terminal 16 for generating the restraint output signal RS. The operation of the restraint system 10 of the present invention will now be explained. Under normal operating conditions (i.e., restraint off), the gate of the N-channel transistor Ql will be at the low logic level. Thus, the transistor Ql will be turned off which, in turn, renders the transistor Q2 to be non-conductive. Consequently, the restraint output signal RS on the output drive terminal 16 will be in the inactive state. However, when the upstream logic restraint signal UR is at the high logic level in response to one or more of the downstream logic signals being in the active state indi- eating a short circuit or ground fault condition in cor¬ responding downstream circuit breakers the transistor Ql will be turned on when its gate voltage exceeds the gate- source voltage threshold. As a result, the gate electrode of the P-channel transistor Q2 will be pulled towards the ground potential, thereby causing the transistor Q2 to be rendered conductive. Thus, drive current will now be supplied from the power supply voltage through the source-drain conduction path and the second resistor R2 to the restraint loads 18. When the restraint loads 18 are increased due to an increase in the number of upstream circuit breakers connected to the output terminal 16, the conduction state of the transistor Q2 will not be affected by the increased current drain on the restraint output signal RS in the active state since the gate-to-source voltage V GS is determined by the voltage drop across the first resistor Rl, which is independent of the restraint loads. The amount of current which is available to drive the restraint loads 18 will now be determined by the selection of the value of the resistor R2. The resistor R2 and the restraint loads 18 form essentially a voltage divider for the power supply voltage Vdd. It can be seen that this resistor R2 serves as a current-limiting resistor so as to protect the output driver circuit 14 against short circuit conditions. For completeness in the disclosure of the above- described restraint system but not for the purposes of limitations, the following representative values and component identifications are submitted. These values and components were employed in the preferred embodiment of the invention described herein. From the foregoing detailed description, it can thus be seen that the present invention provides an improved logic level current and voltage independent restraint system for generating an upstream restraint signal which is independent of an output driver circuit. The instant restraint system includes an output driver circuit which is formed of a first transistor, a second transistor, and a load resistor. While there has been illustrated and described what is at present considered to be a preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodi¬ ment disclosed as the best mode contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims: WHAT IS CLAIMED IS: 1. In an electrical distribution system of the type having a plurality of circuit breakers spaced upstream and downstream along the stream of the distribution system from a power supply source to a plurality of separate restraint loads, a restraint system for gen¬ erating an upstream restraint signal which is independent of an output driver circuit, said restraint system comprising: logic control means (12) responsive to downstream logic signals for generating an upstream logic restraint signal; an output driver circuit (14) formed of a first transistor (Ql) , a second transistor (Q2) , and a load resistor (Rl) ; said first transistor (Ql) having one of its conduction path electrodes connected to a power supply voltage (Vdd) via said load resistor (Rl) and its other one of its conduction electrodes connected to a ground potential (GND) ; said first transistor (Ql) having its control electrode connected to receive the upstream logic restraint signal; said second transistor (Q2) having one of its conduction path electrodes connected also to the power supply voltage and its other one of its conduction path electrodes coupled to an output drive terminal (16) for generating the upstream restraint output signal; said second transistor (Q2) having its control electrode connected to the junction of said load resistor and said one conduction path electrode of said first transistor; and a plurality of separate restraint loads (18) being connected to said output terminal. 2. In an electrical distribution system as claimed in Claim 1, wherein when said upstream restraint output signal is in the active state it is not affected by an increased current drain caused by the increase in the number of restraint loads connected to said output terminal. . In an electrical distribution system as claimed in Claim 1, wherein said first transistor comprises an N- channel field-effect transistor. 4. In an electrical distribution system as claimed in Claim 3, wherein said second transistor comprises a P- channel field-effect transistor. 5. In an electrical distribution system as claimed in Claim 4, further comprising current-limiting means connected between the drain of said second transistor and said output terminal for protecting said output driver circuit against short circuit conditions. 6. In an electrical distribution system as claimed in Claim 5, wherein said current-limiting means comprises a resistor (R2) . 7. In an electrical distribution system as claimed in Claim 3, wherein said one of its conduction path electrodes of said first transistor is the drain, and wherein said other one of its conduction path electrodes of said first transistor is the source. 8. In an electrical distribution system as claimed in Claim 4, wherein said one of its conduction path electrodes of said second transistor is the source, and wherein said other one of its conduction path electrodes of said second transistor is the drain. 9. In an electrical distribution system as claimed in Claim 1, wherein said plurality of separate restraint loads comprises multiple upstream circuit breakers. 10. A restraint system for generating an upstream restraint output signal which is independent of an output driver circuit, said restraint system comprising: logic control means (12) responsive to downstream logic signals for generating an upstream logic restraint signal; an output driver circuit (14) formed of a first transistor (Ql) , a second transistor (Q2) , and a load resistor (Rl) ; said first transistor (Ql) having one of its conduction path electrodes connected to a power supply voltage (Vdd) via said load resistor (Rl) and its other one of its conduction electrodes connected to a ground potential (GND) ; said first transistor (Ql) having its control electrode connected to receive the upstream logic restraint signal; said second transistor (Q2) having one of its conduction path electrodes connected also to the power supply voltage and its other one of its conduction path electrodes coupled to an output drive terminal (16) for generating the upstream restraint output signal; said second transistor (Q2) having its control electrode connected to the junction of said load resistor and said one conduction path electrode of said first transistor; and a plurality of separate restraint loads (18) being connected to said output terminal. 11. In an electrical distribution system as claimed in Claim 10, wherein when said upstream restraint output signal is in the active state it is not affected by an increased current drain caused by the increase in the number of restraint loads connected to said output terminal. 12. In an electrical distribution system as claimed in Claim 10, wherein said first transistor comprises an N-channel field-effect transistor. 13. In an electrical distribution system as claimed in Claim 12, wherein said second transistor comprises a P-channel field-effect transistor. 14. In an electrical distribution system as claimed in Claim 13, further comprising current-limiting means connected between the drain of said second transistor and said output terminal for protecting said output driver circuit against short circuit conditions. 15. In an electrical distribution system as claimed in Claim 14, wherein said current-limiting means comprises a resistor (R2) . 16. In an electrical distribution system as claimed in Claim 12, wherein said one of its conduction path electrodes of said first transistor is the drain, and wherein said other one of its conduction path electrodes of said first transistor is the source. 17. In an electrical distribution system as claimed in Claim 13, wherein said one of its conduction path electrodes of said second transistor is the source, and wherein said other one of its conduction path electrodes of said second transistor is the drain. 18. In an electrical distribution system as claimed in Claim 10, wherein said plurality of separate restraint loads comprises multiple upstream circuit breakers. 19. An output driver circuit used in a restraint system for generating an upstream restraint output signal which is independent of its drive voltage and current characteristics, said output driver circuit comprising: a first transistor (Ql) having one of its conduction path electrodes connected to a power supply voltage (Vdd) via a load resistor (Rl) and its other one of its conduction electrodes connected to a ground potential (GND) ; said first transistor (Ql) having its control electrode connected to receive an upstream logic restraint signal; a second transistor (Q2) having one of its conduction path electrodes connected also to the power supply voltage and its other one of its conduction path electrodes coupled to an output drive terminal (16) for generating the upstream restraint output signal; and said second transistor (Q2) having its control electrode connected to the junction of said load resistor and said one conduction path electrode of said first transistor. 20. An output driver circuit as claimed in Claim 19, further comprising a current-limiting resistor (R2) having its one end connected to the other conduction path electrode of said second transistor and its other end connected to said output terminal for protecting said output driver circuit against short circuit conditions.

Inventors: BAACK JERRY R, HAUN ANDY A, BAACK, JERRY, R., HAUN, ANDY, A.
Applicants: SQUARE D CO, SQUARE D COMPANY
Application year: 1993
Main classification: H02H3
IPC codes: H02H1, H02H7, H02K3, H03K17