METHOD OF CHECKING THE OPERATION OF A MICROPROCESSOR AND SYSTEM FOR IMPLEMENTING THE METHOD

Abstract: The invention relates to a method of and a system for checking the operation of a microprocessor. According to the invention, functions performing desired tests are included in the software of the microprocessor (1), microprocessor status data produced by the tests are written successively to a data bus (3) of the microprocessor, the successive status data are read from the data bus (3), each to a separate register (7a to 7n), the status data and the results of the tests are presented in parallel at outputs (a to n) of the registers (7a to 7n).

Description: Method of checking the operation of a microprocessor and system for implementing the method The invention relates to a method of checking the operation of a microprocessor and a system for implementing the method. In a solution according to the prior art, the logic of a microprocessor is tested by connecting measuring devices directly to the pins of the micro- processor. This is very cumbersome and time-consum¬ ing; expensive measuring devices are needed for these tests, which are not always very covering. The object of this invention is to provide a method and a system, by means of which the drawbacks mentioned above can be avoided. The method according to the invention is characterized by steps as fol¬ lows: - functions performing desired tests are in¬ cluded in the software of the microprocessor, - microprocessor status data produced by the tests are written successively to a data bus of the microprocessor, - the successive status data are read from the data bus, each to a separate register, - the status data and the results of the tests are presented in parallel at outputs of the regis¬ ters. By means of the solution according to the in¬ vention, it is possible to access an address and data bus of the microprocessor directly without inconve¬ nient connection of test equipments. The other preferred embodiments of the method according to the invention and the system according to the invention are characterized in what has been set forth in the appended claims. The invention will be described in greater de¬ tail in the following with reference to the attached drawing illustrating the system of the invention. The solution according to the invention is shown in the attached figure. By means of this solu¬ tion, it is possible to directly access address and data busses, 2 and 3, respectively, of the micropro¬ cessor 1 by using simple and cheap circuit solutions. Uncomplicated and fast test functions are in- eluded in the software of the microprocessor, in which statuses selected by a user may be written by means of short writing operations to a test interface of the system according to the invention (right-hand side of the figure from the vertical dash line) . These status data may be read quickly and flexibly from the test interface according to the invention by simple methods, e.g. by means of a separate display device to be connected to the interface or by guiding the status data into a display or output device of another system. In the solution according to the invention, test data are written successively to the data bus 3. After a test function has been activated, an address decoding circuit 4 generates for the test interface a circuit selecting pulse in accordance with the ad¬ dress of the circuit. This pulse starts a counter 5, during stepping of which a BIN/LIN transforming cir¬ cuit 6 generates a circuit selecting pulse alternate¬ ly for each register 7a to 7n. The test data coming successively from the data bus 3 may then be read to separate registers each, thus being readable in par¬ allel at register outputs a to n. The counter 5 may be brought to its initial state according to the figure by using a monostable multivibrator, for instance, which is triggered ac- tive by the first writing pulse. The monostable mul¬ tivibrator sets the counter to zero after a predeter¬ mined time, when data bytes to be transmitted at a time (during one update run) have been written to the register. This function makes a flexible change in the number of data bytes to be written possible, without any need to change the test interface. The writing of data bytes always begins with the first register. The counter 5 may also be set to zero by other methods. The counter may have a separate reset cir¬ cuit zeroing the counter after the maximum number of data bytes has been written. Then the number of bytes to be written is constant at each update run of the registers. The solution according to the invention may be applied to testing of all microprocessors. It is thus clear to one skilled in the art that the invention is not limited to the above example, but its various embodiments may vary freely within the scope of the claims set forth below.

Claims: Claims: 1. A method of checking the operation of a mic¬ roprocessor, c h a r a c t e r i z e d by steps as follows: - functions performing desired tests are in¬ cluded in the software of the microprocessor ( 1) , - microprocessor status data produced by the tests are written successively to a data bus (3) of the microprocessor, - the successive status data are read from the data bus (3), each to a separate register (7a to 7n), - the status data and the results of the tests are presented in parallel at outputs (a to n) of the registers (7a to 7n). 2. A method according to claim 1, c h a r a c¬ t e r i z e d in that, for writing the status data, the registers (7a to 7n) are addressed by addressing circuits (4 to 6) over an address bus (2) of the mic- roprocessor (1), which circuits synchronize the read¬ ing functions of the registers with the status data coming from the data bus (3) . 3. A system for checking the operation of a microprocessor, c h a r a c t e r i z e d in that the system comprises registers (7a to 7n) connected to a data bus (3) of the microprocessor (1), to which registers status data produced by functions included in the software of the microprocessor and performing desired tests may be written over the data bus (3), and addressing circuits (4 to 6) connected to an ad¬ dress bus (2) of the microprocessor, by which ad¬ dressing circuits the writing of the status data to the registers (7a to 7n) and a parallel presentation at outputs (a to n) of the registers may be con- trolled. 4. A system according to claim 3, c h a r a c¬ t e r i z e d in that the addressing circuits of the registers (7a to 7n) belonging to the system comprise an address decoding circuit (4), a counter (5) start¬ ed by a pulse produced by this circuit and a trans¬ forming circuit (6) producing a circuit selecting pulse alternately for each register (7a to 7n) when the counter is stepping.

Inventors: LOUKUSA JARMO, RIEPPO MIKKO, SAEYNAEJAEKANGAS SARI, TAKALUOMA ANTTI, VARANKA KAUKO, VEKI ILARI, LOUKUSA, JARMO, RIEPPO, MIKKO, SAEYNAEJAEKANGAS, SARI, TAKALUOMA, ANTTI, VARANKA, KAUKO, VEKI, ILARI
Applicants: LOUKUSA JARMO, NOKIA TELECOMMUNICATIONS OY, RIEPPO MIKKO, SAEYNAEJAEKANGAS SARI, TAKALUOMA ANTTI, VARANKA KAUKO, VEKI ILARI, LOUKUSA, JARMO, RIEPPO, MIKKO, SAEYNAEJAEKANGAS, SARI, TAKALUOMA, ANTTI, VARANKA, KAUKO, VEKI, ILARI
Application year: 1993
Main classification: G06F11
IPC codes: G06F11