Hierarchical connection method, apparatus and protocol

Abstract: A protocol and associated addressable shadow port circuitry for efficiently extending serial bus capability to the backplane environment is disclosed. The protocol is designed to co-exist and be fully compatible with existing serial bus approaches. Circuitry and a protocol operable to couple any one of the boards (BOARD1-BOARDN) on the system backplane bus to the serial bus master (SBM) is described, wherein the protocol operates to select and deselect the boards without interfering with the normal operations on the system backplane bus. The protocol and circuitry is extended to hierarchically arranged systems, so that a primary serial bus master (SBM) device can selectively access and communicate with any device positioned at any level of the hierarchy. Further disclosed embodiments utilize multiple remote serial bus masters on hierarchically arranged networks, each remote serial bus master being coupled to a primary serial bus master using the protocol and circuitry of the invention, so that autonomous testing may be performed by the remote serial bus master devices under the control of the primary serial bus master.

Description: This invention relates generally to the use of buses to communicate between devices, including circuits, systems, boards and networks, and in particular to serial backplane buses. The invention is applicable to any environment where a serial communication bus is or may be used, including circuit boards, backplanes, integrated circuits, and systems. BACKGROUND OF THE INVENTION In producing integrated circuits or circuit boards for systems, the use of a serial communication bus for test and debug is rapidly becoming a standard practice. The use of the serial bus allows the system, circuit board or integrated circuits to be tested and connections to be confirmed without the need for intrusive hardware or test probes. This is particularly important as packaging of the devices reaches higher densities and for multiple integrated circuits packaged on a single module, or for systems where the circuitry is not available for physical access for other reasons. Industry has developed and continues to develop standard protocols for serial busses of this kind. The standards are necessary and desirable to insure that parts and boards acquired from various vendors will be able to communicate on a common bus. In general, the concepts of this invention apply to any type of serial bus. However, to clarify the description of the invention it will be described as being a feature added to a well understood and documented IEEE/ANSI standard serial bus designed for testing ICs at the board level, referred to as IEEE/ANSI standard 1149.1 or more commonly as the JTAG boundary scan standard. The IEEE/ANSI 1149.1 standard describes a 4-wire serial bus that can be used to transmit serial data to and receive serial data from multiple ICs on a board. While the 1149.1 serial bus was originally developed to serially access ICs at the board level, it can also be used at the backplane level to serially access ICs on multiple boards. The 1149.1 standard describes a 4-wire serial bus that can be used to transmit serial data between a serial bus master and slave device. While 1149.1 was developed to serially access ICs on a board, it can be used at the backplane level to serially access boards in a backplane. 1149.1 has two serial access configurations, referred to as "ring" and "star", that can be used at the backplane level. In a backplane 1149.1 ring configuration, all boards in the backplane directly receive the control outputs from a primary serial bus master (PSBM) and are daisy chained between the PSBM's data output and data input. During scan operation, the PSBM outputs control scan data through all boards in the backplane, via its test data output (TDO) and test data input (TDI) bus connections. The problem associated with the ring configuration is that the scan operation only works if all the boards are included in the backplane and are operable to scan data from their TDI input to TDO output signals. If one of the boards is removed or has a fault, the PSBM will be unable to scan data through the backplane. Since the ring configuration does not allow access to remaining boards when one is removed or disabled, it does not fully meet the needs of a serial bus for backplane and large system applications. In a backplane 1149.1 star configuration, all boards in the backplane directly receive the test clock (TCK) and TDI signals from the PSBM and output a TDO signal to the PSBM. Also each board receives a unique test mode select (TMS) signal from the PSBM. In the star configuration only one board is enabled at a time to be serially accessed by the PSBM. When a board is enabled, the TMS signal associated with that board will be active while all other TMS signals are inactive. The problem with the star configuration is that each board requires its own TMS signal. In a backplane with 100 boards, the PSBM would have to have 100 individually controllable TMS signals, and the backplane would have to have traces for each of the 100 TMS signals. Due to these requirements, star configurations are typically not considered for backplane applications. IRE Wescon Conference Record, November 1989, Vol 33, pages 294 to 299, describes the use of the 1149.1 standard serial bus in both ring and star configurations. Two IEEE serial bus standards, P1149.5 and P1394, are in development for use in system backplanes. Since these standards are being specifically designed for backplane applications, they appear to overcome the problems stated using the 1149.1 standard bus as a backplane bus. However, the protocols of these anticipated standards are different from the 1149.1 protocol and therefore methods must be defined to translate between them and 1149.1. The IEEE P1149.5 standard working group is currently defining a module test and maintenance bus that can be used in system backplane environments. P1149.5 is a single master/multiple slave bus defined by a 5-wire interface. The P1149.5 bus master initiates a data transfer operation by transmitting a data packet to all slave devices. The data packet consists of an address and command section. The slave device with a matching address is enabled to respond to the command section of the data packet as described in the P1149.5 standard proposal. Interfacing an P1149.5 bus into an 1149.1 bus environment requires new additional system hardware and software, and designers with a detailed understanding of both bus types. Therefore, in using P1149.5 to interface into an 1149.1 environment, an unnecessary complication is added to an otherwise simple serial access approach. Another problem is that the bandwidth of the 1149.1 serial data transfer will be adversely affected by the 1149.5 to 1149.1 protocol conversion process and hardware. The IEEE P1394 standard working group is currently defining a 2-wire high-speed serial bus that can be used in either a cable or system backplane environment. The P1394 standard, unlike P1149.5, is not a single master/multiple slave type bus. In P1394, all devices (nodes) connected to the bus are considered to be of equal mastership. The fact that P1394 can operate on a 2-wire interface makes this bus attractive in newer 32-bit backplane standards where only two wires are reserved for serial communication. However, there are problems in using P1394 as a backplane test bus to access 1149.1 board environments. First, P1394 is significantly more complex in operation than P1149.1, thus devices designed to translate between P1394 and 1149.1 may be costly. Second , P1394 is not a full time test bus, but rather it is a general purpose serial communication bus, and its primary purpose in a backplane environment is to act as a backup interface in the event the parallel interface between boards becomes disabled. While 1149.1 test access can be achieved via P1394, it will be available only during time slices when the bus is not handling functional operations. Thus on-line 1149.1 test bus access will be limited and must be coordinated with other transactions occurring on the P1394 bus. This will require additional hardware and software complexity. Another method of achieving a backplane to board level interface is to extend the protocol defined in the 1149.1 standard. Such an approach has been described in a paper presented at the 1991 International Test Conference by D. Bhavsar, entitled "An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes". The Bhavsar paper describes a method of extending the protocol of 1149.1 so it can be used to access an interface circuit residing between the backplane and board level 1149.1 buses. The interface circuit responds to 1149.1 protocol transmitted over the backplane bus to load an address. If the address matches the address of the interface circuit, the interface circuit is connected to the backplane. After the interface circuit is connected to the backplane, additional 1149.1 protocol is input to the interface circuit to connect the backplane and board level 1149.1 buses. Following this connection procedure, the board level 1149.1 bus can be controlled by the backplane 1149.1 bus. Bhavsar's approach also has problems that limit its effectiveness as a general purpose 1149.1 bus backplane to board interface. Bhavsar's approach does not allow selecting one board, then selecting another board without first resetting the backplane and board level 1149.1 buses, by transitioning them into their test logic reset (TLRST) states. Entering the TLRST state causes test conditions setup in the ICs of a previously selected board to be lost due to the test reset action of the 1149.1 bus on the test access ports (TAPs) of the ICs. Also, it is often desirable to select and initiate self-tests in a selected group of backplane boards. However, since the Bhavsar approach requires resetting the 1149.1 bus each time a new board is selected, it is impossible to self-test more than one board at a time, because resetting the bus aborts any previously initiated self-test. Thus, a need exists for a simple, efficient and effective means to provide support for the use of an 1149.1 standard serial bus in a multiple-board backplane environment. The invention provides a system comprising a master device and a plurality of slave devices connected by a communication bus; each slave device comprising an addressable port circuit operable to connect the communication bus to or disconnect the communication bus from a bus of the slave device that uses the same bus protocol as the said communication bus; each addressable port circuit comprising: a primary port to which the communication bus is connected; a secondary port to which the bus of the slave device is connected; connection means connected to said primary and secondary ports and operable to connect the communication bus to or disconnect the communication bus from the said bus of the slave device in response to a control signal; and control circuitry to generate said control signal in response to a selection sequence issued by the master device; wherein when said communication bus is not used for normal communication according to the bus protocol the master device can send out a selection sequence on the said communication bus using a protocol different from the normal communication protocol to specify the logical address of a slave device to be selected next; and the control circuitry in each slave device is arranged to check whether or not an address issued by the master device corresponds to the logical address of that slave device; if that address does not correspond the control circuitry is arranged to send a message to the connection means to disconnect the bus of that slave device from the communication bus; and if that address does correspond the control circuitry is arranged to send a message to the connection means to connect the bus of that slave device to the communication bus, in such a way that they are perceived by the system as a single communication bus. The invention also provides a method in accordance with claim 4. Generally, and in one form of the invention, a backplane access approach which provides a method of using the 1149.1 bus at the backplane level without incurring the problems previously described is disclosed. Using this approach, it is envisioned that one homogeneous serial bus may be used throughout a system design, rather than translating between multiple serial bus types. Employing a common serial bus in system designs can simplify software and hardware engineering efforts, since only an understanding of one bus type is required. In a first embodiment of the invention a circuit, called an addressable shadow port (ASP), and a protocol, called a shadow protocol, is described which provides a simple and efficient method of directly connecting 1149.1 backplane and board buses together. When the 1149.1 backplane bus is in either its run test/idle (RT/IDLE) or test logic reset (TLRST) states, the ASP circuit can be enabled, via the shadow protocol of the invention, to connect a target board's 1149.1 serial bus up to the backplane 1149.1 serial bus. After the shadow protocol herein described has been used to connect the target board and backplane buses together, the protocol of the invention becomes inactive and becomes transparent to the operation of the 1149.1 bus protocol. The use of the invention results in several improvements over the use of the 1149.1 standard in a system or backplane environment or the other prior art extension approaches in terms of the efficiency of data transfers, the ability to remove boards or support backplanes where not all slots are populated, the ability to keep the 1149.1 bus in the idle state when selecting and deselecting boards, and the advantageous use of the well understood 1149.1 serial bus without the need for additional bus design or translator circuitry to accomplish these improvements. An additional embodiment is disclosed wherein a single board contains multiple 1149.1 scan paths, each coupled to the backplane serial bus by means of an individually addressable shadow port, for additional flexibility in scan path and testability design. Other preferred embodiments and enhancements are also disclosed. Further embodiments extend the ASP circuit and protocol to allow the local serial bus to be selectively controlled by a remote serial bus master circuit or alternatively by a primary serial bus master located on the backplane serial bus. The ASP capabilities are extended to allow input and output of parallel data to a memory via the ASP and the primary serial bus master. The ASP circuit and protocol are further extended to allow interrupt, status and command information to be transferred between a remote serial bus master and a primary serial bus master, to support sophisticated commands and remote functions autonomously executed by the remote serial bus master. The invention is then applied to hierarchically organized systems, wherein multiple backplane systems are linked together through networks coupled in a multiple level environment. The ASP capabilities are extended to allow the primary serial bus master to directly select and send and receive data and commands to any board within the hierarchy. An additional embodiment is disclosed wherein the circuitry and protocol of the invention is adapted for use with the proposed two wire serial backplane busses being considered by some in industry. Modifications and enhancements to make the invention compatible with such a bus are described. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: FIG. 1 depicts a typical backplane to board connection using the 1149.1 bus standard; FIG. 2 depicts a state diagram of the states the 1149.1 bus transitions through in operation; FIG. 3 depicts a typical prior art ring configuration of an 1149.1 standard bus used in a backplane environment; FIG. 4 depicts a typical prior art star configuration of an 1149.1 bus in a backplane environment; FIG. 5 depicts an embodiment of a connection between a serial bus master and a single board in a backplane environment using the 1149.1 standard bus and incorporating the addressable shadow port of the invention; FIG. 6 depicts a system backplane having multiple boards connected to a serial bus master with a 1149.1 serial bus using the protocol and hardware of the invention; FIG. 7 depicts a block level diagram of the circuitry required to implement the addressable shadow port circuit of the invention; FIG. 8 depicts the timing of a transfer of an IDLE bit-pair of the protocol of the invention; FIG. 9 depicts the timing of a transfer of a SELECT bit-pair of the protocol of the invention; FIG. 10 depicts the timing of a transfer of a logic 1 data bit-pair of the protocol of the invention; FIG. 11 depicts the timing of a transfer of a logic 0 data bit-pair of the protocol of the invention; FIG. 12 depicts the transactions which occur between the serial bus master and the addressable shadow port of the invention during the select and acknowledge transactions of the shadow protocol; FIG. 13 depicts the signal transitions on the serial bus lines which occur during the select and acknowledge transactions between the addressable shadow port and the serial bus master using the protocol of the invention; FIG. 14 is a state diagram depicting the states the transmitter circuitry resident in the serial bus master and the addressable shadow port of the invention transitions through during the transactions of the protocol; FIG. 15 is a state diagram depicting the states the receiver circuitry resident in the serial bus master and the addressable shadow port of the invention transitions through during the transactions of the protocol; FIG. 16 is a state diagram depicting the states the master control circuitry of the serial bus master circuit transitions through during the transactions of the protocol of the invention; FIG. 17 is a state diagram depicting the states the slave control circuitry of the addressable shadow port circuit transitions through during the transactions of the protocol of the invention; FIG. 18 depicts the subcircuits required in one preferred embodiment of the addressable shadow port circuit of the invention; FIG. 19 depicts an alternative embodiment wherein an integrated circuit with multiple secondary ports contains several independently addressable shadow port circuits each connected to a single primary port coupled to the serial bus; FIG. 20 depicts an integrated circuit incorporating the invention and containing the addressable shadow port of the invention, a primary port coupled to the serial backplane bus, and an internal serial bus coupled to a plurality of application specific logic circuitry blocks. Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Within this specification, the following abbreviations are used hereafter: SBM indicates the serial bus master of the invention, a circuit capable of addressing and accessing other boards coupled to the serial bus; PSBM indicates the primary serial bus master; ASP indicates the addressable shadow port hardware of the invention; TAP indicates a test access port, the standard hardware interface of devices coupled to the 1149.1 bus; TMS indicates the Test Mode Select line, the control line of the 1149.1 bus; TDO indicates the Test Data Output line, one of the lines the 1149.1 bus transfers serial data on; TDI indicates the Test Data Input line, one of the lines the 1149.1 bus transfers data on; TCK indicates the Test Clock line, the common clock line used by all of the devices coupled to the 1149.1 serial bus to synchronize transfers between devices. A serial bus slave is a circuit or device that can be enabled and communicated to by a serial bus master via the serial bus network. A serial bus slave as used in this application refers to any well defined logic block or circuitry having input and output circuitry operable to allow it to be interfaced onto a serial bus. For simplicity, this application treats serial bus slaves as being printed circuit boards, comprised of multiple ICs that are plugged into a system backplane. However, it should be understood that the invention could be used in applications which define serial bus slaves as being: (1) sub-circuits in an IC, (2) ICs on a common substrate (i.e. multi-chip modules), (3) ICs on a printed circuit board, (3) boards plugged into a system backplane, (4) backplanes in a subsystem (5) subsystems in a system, or (6) systems connected to other systems. A serial bus master is a circuit or device that can output the necessary control signals to enable communications with a serial bus slave via the serial bus network. Throughout the remainder of this application, the serial bus master will be referred to as an SBM. In FIG. 1, an SBM 1 is depicted as connected to an example board 3 via a connector 2 coupled to the standard 4-wire 1149.1 serial bus as contemplated by the existing art. Inside board 3, the 4-wire serial bus is connected to various integrated circuits (ICs) IC1, IC2, ICN via a standard IC level serial interface circuit referred to as a test access port (TAP). The TAP consists of a control circuit that responds to the 4-wire serial bus to enable and disable serial access to the IC. The TAP pins used to connect up to the serial bus consist of a serial test data input (TDI) pin, a serial test data output (TDO) pin, a test clock (TCK) pin, and a test mode select (TMS) pin. The TAP's TDI pin is a unidirectional data input signal used for shifting serial data bit streams into the IC. The TAP's TDO pin is a unidirectional data output signal used for shifting serial data bit streams out of the IC. The TAP's TCK pin is a unidirectional clock input signal used for clocking the serial data bit streams into and out of the IC, via the TDI and TDO pins. The TAP's TMS pin is a unidirectional control input signal used for enabling the shifting of the serial data bit streams into and out of the IC. In operation, board 3 is plugged into a backplane, and the TAP of each IC IC1, I2, etc. is connected in parallel to the TMS and TCK backplane serial bus signals from the SBM. Also each IC's TAP is serially linked or daisychained, via their TDI and TDO pin connections, to form a single serial data path between the backplane's TDI input and TDO output signals. From the backplane, the SBM can drive TMS and TCK signals into the board to cause the TAPs of the ICs to serially shift data from the SBM's TDO output signal, into the board, through each IC on the board, from the board, and back into the SBM's TDI input signal. To understand the relationship between the invention and the standard 1149.1 serial bus, an overview of the 1149.1 serial bus operation is required. In Figure 2 a simplified diagram of the operation of the 1149.1 serial bus is shown. Referring to Figure 1, in operation the SBM outputs TMS and TCK control signals to the controllers of the TAPs of each IC on the board to cause the ICs to operate in step with the serial bus states of Figure 2. The TAP of each IC operates synchronous to the TCK clock output from the SBM and responds to the TMS control output from the SBM, to transition into and out of the serial bus states of Figure 2. The serial bus states include: RESET, IDLE, Select Data Scan (SELDS), Data Scan Sequence (DSS), Select Command Scan (SELCS), and Command Scan Sequence (CSS). Referring to the board example depicted in Figure 1, a description of each of the 1149.1 bus states is given in the following paragraphs. The board of Figure 1 is comprised of ICs 5, with each IC having a TAP interface 7 and connection to the 1149.1 bus via the backplane connector 2. The TAP interfaces of each IC on board 3 are designed to receive and respond to the serial bus states of Figure 2 to control serial access of the ICs. The SBM 1 connected to the backplane is designed to generate and transmit the serial bus states of Figure 2 to serially access the ICs on the board. RESET state - In response to a TMS input, the TAP of each IC on the board can be made to transition from any state into the RESET state as shown in Figure 2. While in the RESET state, the TAP forces test logic in the IC into a disabled condition so that the test logic cannot interfere with the normal operation of the IC. The serial bus forces the TAP of each IC to remain in the RESET state while the TMS signal is high. IDLE state - In response to a TMS input, the TAP of each IC can be transitioned from any state into the IDLE state. While in the IDLE state, the TAP responds to TMS control input to: (1) remain in the idle state, (2) enter into the data scan sequence, (3) enter into the command scan sequence, or (4) enter the reset state. Data Scan Sequence - In response to TMS input, the TAP of each IC can be transitioned from the IDLE state into a data scan sequence (DSS), via the select data scan (SELDS) state. While the TAP is in the DSS state, additional TMS control is input to cause data to be shifted through the ICs test data register from TDI to TDO. After the shift operation is completed, additional TMS control is input to cause the TAP to exit the DSS and enter the IDLE state. Command Scan Sequence - In response to a TMS signal input, the TAP of each IC be transitioned from the IDLE state into a command scan sequence (CSS), via the SELDS and Select Command Scan (SELCS) states. While the TAP is in the CSS, additional TMS control is input to cause data to be shifted through the ICs test command register from TDI to TDO. After the shift operation is completed, additional TMS control is input to cause the TAP to exit the CSS and enter the IDLE state. In summary, the ICs on the board, when connected to the backplane 1149.1 serial bus signals, operate in step with the serial bus as it transitions through or operates in any of its defined states. The TMS signal, output from the SBM, is used to control the operation of the TAP of each IC on the board. Figure 3 depicts a backplane with boards BOARD1, BOARD2 to BOARDN coupled to the 1149.1 standard or JTAG bus in the prior art "ring" configuration, which is further coupled to serial bus master SBM. In the prior art backplane ring configuration, any number of boards N are coupled to the 4-wire 1149.1 serial bus residing in the backplane wiring. All boards receive the TCK and TMS control outputs from an SBM connected to the backplane. As shown in Figure 3, the TDO output of the SBM is input to the first board's TDI input, passes through the board's ICs (as shown in Figure 1) and is output onto the backplane via the board's TDO output. The TDO output of the first board is input to the second board's TDI input, passes through the board's ICs and is output onto the backplane via the board's TDO output, and so on. The TDO of the last board (N) is output onto the backplane via the board's TDO output, and is input to the SBM's TDI input. The TCK output from the SBM provides the clocking for data and command shift operations. The TMS output from the SBM provides the control to enable shift operations through all boards in the backplane ring configuration. The shift operation works only if all the boards are included in the ring and are operable to shift data from their TDI input to TDO output in response to TMS and TCK control input from the SBM. If one of the boards is removed from the backplane or if a board is unable to shift data due to a fault in one of its ICs or connections between one of its ICs, the SBM will be unable to shift data and command information through the boards in the backplane. The main problem in using the 1149.1 ring configuration as a backplane level serial bus as shown in Figure 3 is that the scan operations will only work as long as each board is electrically connected to the backplane serial bus and is operable to shift data from it's TDI input to it's TDO output in response to the backplane TCK clock and TMS control signals. In most applications, it is required that the SBM maintain serial access to boards in the backplane when one or more boards are removed for repair and/or replacement. Since the backplane ring configuration does not allow serial access to remaining boards when one or more of the boards are removed, it does not meet the needs of a backplane level serial bus. Although this description of the ring configuration has been in terms of ring connected boards in a backplane, the same problems occur for multiple circuits ring-connected in an IC, multiple ICs ring-connected on a common substrate, multiple boards ring-connected in a backplane, multiple subsystems ring-connected in a system, and multiple ring-connected systems. Figure 4 depicts a prior art backplane star configuration wherein up to N boards BOARD1, BOARD2, BOARDN are coupled to the 4-wire 1149.1 serial bus residing in the backplane wiring, and further coupled to serial bus master SBM . All boards receive the TCK and TDI bus signals from the SBM and output a TDO bus signal to the SBM. Also each board receives a unique TMS (1,2...n) signal from the SBM. In the star configuration only one board at a time can be enabled by the SBM to shift data from the SBM's TDO output into the board's TDI input, through the board level ICs (see Figure 1) and back to the SBM's TDI input via the board's TDO output. Because the boards all share a common TDO output wiring connection, only one board at a time can be enabled to drive serial data out on TDO to be received by the SBM. When one board is enabled for scan access, the TMS signal associated with that board is active while all the other TMS signals to the other boards are inactive. When scan access to the enabled board is complete another board may be enabled via its TMS signal to allow the SBM to scan data and command information to and from that selected board. The prior art star configuration disadvantageously requires each board have its own TMS signal and backplane wire connection. For example, in a backplane with 100 boards, the SBM would have to have 100 individually controllable TMS signals, to enable access to each of the 100 boards. In addition, the backplane would have to have wiring channels to support 100 TMS signals, one TMS signal wire for each board in the backplane. Due to a limited number of wiring channels in today's backplane bus standards, the star configuration cannot be used in most applications because it requires a TMS signal for each board in the backplane. Again, although this description relates to star-connected boards in a backplane, the same problem occurs for: multiple circuits star-connected in an IC, multiple ICs star-connected on a common substrate, multiple boards star-connected in a backplane, and multiple subsystems star-connected in a system. Serial backplane busses exist or are in development that overcome some or all of the problems that have been described in using the 1149.1 serial bus for a backplane applications. For example, a military backplane bus, referred to as a test and maintenance bus (TMBus), exists and can be used to access a board containing 1149.1 compatible ICs. Further, two IEEE serial bus backplane standards (P1149.5 and P1394) are in development that can also be used to access a board containing 1149.1 compatible ICs. However, all known backplane serial buses operate differently from the 1149.1 serial bus and therefore are not directly compatible, and all require translation hardware and software which comprehends at least two different bus standards. In order to interface one of the mentioned proposed backplane serial buses to a standard board level 1149.1 serial bus, special interface circuits must be developed to translate between each of the different backplane serial bus protocols and the 1149.1 board level serial bus protocol. These serial bus interface circuits are unique for each backplane serial bus since each backplane serial bus operates according to a different protocol. Thus multiple interfaces must be developed, one for each backplane serial bus protocol type. Also each interface disadvantageously requires a complex IC to be placed on the board to translate between one of the backplane serial bus and the 1149.1 board level serial bus. In addition, the introduction of an interface circuit between a backplane and 1149.1 board level serial bus significantly reduces the bandwidth of the serial data to and from an 1149.1 board environment. Further, the aforementioned backplane serial bus types are complex, compared to the 1149.1 serial bus, and require expert engineering skills to develop the sophisticated and expensive interfaces and software. While certain military and high-end commercial applications may be able to adopt this sophisticated and expensive approach, these solutions are inappropriate and unworkable for most commercial applications and systems. Section I Addressable Shadow Port and Protocols A first embodiment of a board example using the invention is shown in Figure 5. Board 11 is comprised of multiple ICs IC1, IC2, ICN and an Addressable Shadow Port ASP, coupled to a system backplane bus using the 1149.1 standard bus and further coupled to serial bus master SBM . The ICs operate, when coupled to the 1149.1 serial bus via the ASP, exactly as described in the board of Figure 1. The ASP has a backplane interface for connection to the backplane level 1149.1 serial bus signals, a board interface for connection to the board level 1149.1 serial bus signals, and an address input . The backplane 1149.1 serial bus signals are referred to as; primary TDI (PTDI), primary TDO (PTDO, primary TCK (PTCK), and primary TMS (PTMS). The board 1149.1 serial bus signals are referred to as; secondary TDI (STDI), secondary TDO (STDO), secondary TCK (STCK), and secondary TMS (STMS). The address input to the ASP is used to identify the board on which the ASP mounted. The invention defines a serial bus protocol and circuitry that provides an addressable method of coupling the SBM up to one of many boards in a backplane, via the 1149.1 serial bus network. The circuit and related protocol is referred to herein as an Addressable Shadow Port (ASP). The term "shadow" indicates the nature of the protocol and circuitry, since it exists in the background of the serial bus it is associated with. While the 1149.1 serial bus is in operation, the ASP is inactive and does not interfere with the operation of the bus. The ASP can be enabled when the 1149.1 backplane serial bus is in either the IDLE or RESET states (FIGURE 2). The ASP is enabled when it is required to connect the SBM up to one of the boards in the backplane. After the ASP has been used to connect a board to the SBM, it is disabled and is transparent to the normal operation of the 1149.1 serial bus or whatever bus it is associated with. Since the invention operates via its own unique protocol that is not part of the 1149.1 protocol, it provides a solution to the extension of the 1149.1 standard to the backplane environment without modification of the 1149.1 standard or the need for additional hardware translation circuitry. The ASP protocol can select or deselect boards while the 1149.1 backplane serial bus is in either the IDLE or RESET states. This is a critical advantage over other suggested or existing approaches, because by allowing the 1149.1 bus to remain in the IDLE state when selecting a new board the invention supports the simultaneous execution of self test or other high level functions on each board. If it were necessary to transition back through the RESET state of the 1149.1 standard to select the next board, the ASP protocol would not support these higher level test functions running simultaneously on multiple boards. Desirable tests also could not be executed between boards, because when the board's IC's see the RESET state on the bus, the test mode is aborted and the IC's on the board enter the functional mode. This situation could arise if one wanted to test board to board operations, for example. Although in Figure 5 the board address is shown to be externally input to the ASP, it could be hard-coded or electrically programmable inside the ASP circuit as well. The protocol of the invention provides the ability to select a particular board by having the SBM output the address of the board to be selected using a unique serial protocol that does not affect the existing standard protocol developed for the 1149.1 serial bus. In Figure 6, multiple boards BOARD1, BOARD2, BOARDN, each similar to the one in Figure 5, are shown being interfaced to the SBM via ASPs. In operation, when one of the boards needs to be accessed, the SBM transmits a select protocol that addresses and enables the ASP of the selected board. Embedded in the ASP select protocol is an address that is used to match against the address associated with each ASP. All ASPs receive the select protocol from the SBM, but only the one with the matching address is selected. In response to the SBM select protocol, the selected ASP transmits an acknowledge protocol, containing its address, back to the SBM to verify the connection. After transmitting the acknowledge protocol, the selected ASP makes a connection between the backplane and board 1149.1 signals, such that the PTDI backplane signal couples to the STDO board signal, likewise PTMS couples to STMS, PTCK couples to STCK, and PTDO couples to STDI. In response to the ASP acknowledge protocol, the SBM communicates further commands and data to the selected board, via the now transparent ASP, using the standard 1149.1 serial bus protocol. After the SBM has completed its 1149.1 serial access to the currently selected board, it can select another board by transmitting a new select protocol that addresses and enables another board's ASP. The new selection protocol can be transmitted by the SBM while the serial bus is in either the IDLE or RESET state, (or any other 1149.1 state where the TDO and TDI signals are disabled). In response to the new select protocol the newly selected ASP transmits an acknowledge protocol back to the SBM then makes a connection between the backplane and board level 1149.1 buses. When a new ASP is selected, the previously selected ASP disconnects from the backplane 1149.1 backplane bus. The disconnecting ASP remains in the state the backplane bus was in when the disconnect occurred, i.e. IDLE or RESET. In response to the new ASP acknowledge protocol, the SBM can output the standard 1149.1 protocol to transmit serial data into and out of the ICs of the newly selected board. This process is repeated each time a new board is selected. The acknowledge protocol part of the ASP protocol scheme additionally allows the SBM to verify that it has successfully selected a board. For example, if the SBM outputs a select protocol to address a board in the backplane, and that board address does not exist or the addressed board is disabled or has been removed from the backplane, the SBM will not receive the acknowledge protocol. If the SBM does not receive the acknowledge protocol it will not attempt to communicate to the board using the 1149.1 serial bus protocol. Also the SBM can identify the problem and output an error indication that connection to that particular backplane board address failed. A key feature of the invention is its capability to electronically connect the backplane level serial bus to a board level serial bus in response to a uniquely designed protocol. The ASP protocol has two parts; a select protocol transmitted from the SBM to the ASP of each board in the backplane, and an acknowledge protocol transmitted from the selected board's ASP to the SBM. This protocol is transmitted between the SBM and the ASP of each board in the backplane using the existing 4-wire serial bus signals defined by the 1149.1 serial bus. No additional backplane signals are required to use the invention. In addition, the protocol is transmitted so that it does not infringe upon the existing 1149.1 serial bus protocol. This result is achieved by making use of the dead-time of the 1149.1 serial bus to transmit the ASP select and acknowledge protocols. In the 1149.1 serial bus configuration of Figure 6, the SBM's TDO and TDI signals are only active to transfer serial data between the SBM and the selected board when the 1149.1 serial bus is active in its DSS or CSS states of Figure 2. When the 1149.1 serial bus is in its RESET or IDLE states, the TDO and TDI signals of the 1149.1 serial bus are disabled. While the 1149.1 serial bus is in the RESET or IDLE state, the SBM can therefore output the invention's select protocol from the SBM's TDO output to the PTDI inputs of the ASPs, and receive the invention's acknowledge protocol from the selected ASP's PTDO output on the SBM's TDI input. Since the 1149.1 serial bus does not require use of the TDO and TDI signals while they are being used to transmit the invention's select and acknowledge protocols, these transactions do not interfere with or impinge upon the operation of the 1149.1 serial bus. The ASP and the protocol expand the functionality of the SBM's 1149.1 TDO output and TDI input signals so that when not being used by the 1149.1 serial bus, they can be used to transmit the invention's protocol to address and select one of the boards connected to the backplane serial bus via the ASP circuit. Comparing the prior art star configuration of Figure 4 against the ASP configuration of Figure 6, the advantages of the ASP circuit and protocol are realized from the fact that the ASP approach eliminates the need for the additional TMS signals required in the 1149.1 star configuration. The ASP provides a method of overcoming the problems associated with the 1149.1 star configuration shown in Figure 4, and creates an effective use of the 1149.1 serial bus at the backplane level to serially access boards. Also when comparing the use of different backplane buses to interface into 1149.1 board environments versus using the ASP to achieve the same result, the invention advantageously does not require use of sophisticated, expensive, and inefficient translation circuitry, and the protocol of the invention advantageously allows the SBM to select, access and deselect multiple boards without the necessity of resetting the serial bus and its interfaces. A block diagram of the ASP circuit is shown in Figure 7. The Addressable Shadow Port circuit consists of a primary port for interfacing to the backplane level 1149.1 serial bus signals (PTDI,PTMS,PTCK,PTDO), a secondary port for interfacing to the board level 1149.1 serial bus signals (STDO,STMS,STCK,STDI), and a control logic section. The control logic section provides the interface between the primary and secondary ports and also receives a board address input. During a select protocol, the control logic receives a PTDI input sequence from the SBM. If the address received during the select protocol transmission matches the board address input to the control logic, the control logic makes a connection between the primary and secondary ports and transmits an acknowledge protocol, containing the board address, back to the SBM via the PTDO output. In response to receiving the acknowledge protocol, the SBM outputs the 1149.1 serial bus protocol onto the backplane to serially input data to and output data from the selected board, via the connection made between the primary and secondary ports of the ASP by the control logic. If the address received during the select protocol transmission does not match the board address input, the control logic does not make a connection between the primary and secondary ports, and does not transmit an acknowledge protocol to the SBM. In response to not receiving the acknowledge protocol, the SBM detects that the board address does not exist or is unable to respond and does not attempt to transfer serial data to the board using the 1149.1 serial bus protocol. Recalling Figure 1, the 1149.1 serial bus has four bus signals, two signals for data transfer (TDI & TDO), one signal providing a clock (TCK), and one signal controlling the operation of the bus (TMS). The TMS signal controls the state of the bus as shown in the diagram of Figure 2. The TMS signal determines whether the serial bus shifts data on the TDO and TDI signal paths or is placed in an IDLE or RESET state. Thus the 1149.1 serial bus uses separate signal paths for controlling the operation of the bus (TMS) and transferring serial data on the bus (TDO & TDI). Since the objective of the invention is not to intrude on the normal operation of the bus it is used with, the invention cannot reuse the TMS signal for controlling its select and acknowledge protocols. In order for the SBM and ASP to communicate the invention's select and acknowledge protocols without using the 1149.1's TMS control signal, an encoding scheme was developed to allow control and data information to be transmitted together on a single wiring channel. In Figure 6, the encoding scheme allows the SBM to transmit the select protocol from its TDO output to the ASP's PTDI inputs. Likewise, the encoding scheme allows the selected ASP to transmit the acknowledge protocol from its PTDO output to the SBM's TDI input. In both transactions, the protocols are transmitted over a single backplane wiring channel. The select protocol passes through the wiring channel between the SBM's TDO output and the ASPs PTDI inputs. The acknowledge protocol passes through the wiring channel between the selected ASP's PTDO output and the SBM's TDI input. While this description illustrates the select and acknowledge protocols as being transmitted on separate single wiring channels, they could be transmitted on a common single wiring channel as well, since the protocols are never transmitted simultaneously. The reason the preferred embodiment presented here uses separate single wiring channels for the select and acknowledge protocols is to maintain compatibility with the 1149.1 serial bus standard, which uses two separate wiring channels so that serial data input and output transmissions can occur simultaneously. Both the select and acknowledge protocols of the invention require a method of transmitting control to indicate; (1) an idle condition, (2) a start data transfer condition, and (3) a stop data transfer condition. In addition, both protocols require a method of transmitting data during the interval between the start and stop data transfer conditions. To achieve the transmission of both control and data on a single wire, a unique bit-pair encoding scheme is used. The encoded bit-pairs are transferred between the SBM and ASP during select and acknowledge protocols synchronous to the backplane TCK signal. Two TCKs are required to transmit each encoded bit-pair. Figures 8-11 depict the inventions bit-pair encodings for: (8) an Idle bit-pair, (9) a Select bit-pair, (10) a logic 1 bit-pair, and (11) a logic 0 bit-pair respectively. In Figure 8, an encoded control signal, called Idle (I), is identified by the transfer of two successive logic one bits from a transmitter to a receiver. During the select protocol, the SBM (transmitter) outputs the Idle bit-pair on its TDO output to the ASP's (receivers) PTDI inputs. During the acknowledge protocol, the selected ASP (transmitter) outputs the Idle bit-pair on its PTDO output to the SBM's (receiver) TDI input. In the timing diagram of Figure 8, it is seen that Idle bit-pairs are output from the transmitter on the falling edge of the TCK, and are input to the receiver on the rising edge of the TCK. In Figure 9, an encoded control signal, called Select (S), is identified by the transfer of two successive logic zero bits from a transmitter to a receiver. During the select protocol, the SBM (transmitter) outputs the Select bit-pair on its TDO output to the ASP's (receivers) PTDI inputs. During the acknowledge protocol, the selected ASP (transmitter) outputs the Select bit-pair on its PTDO output to the SBM's (receiver) TDI input. In the timing diagram of Figure 9, it is seen that Select bit-pairs are output from the transmitter on the falling edge of the TCK, and are input to the receiver on the rising edge of the TCK. In Figure 10, an encoded logic one signal, called Data (D), is identified by the transfer of a logic zero bit followed by a logic one bit from a transmitter to a receiver. During the select protocol, the SBM (transmitter) outputs the logic one Data bit-pair on its TDO output to the ASP's (receivers) PTDI inputs. During the acknowledge protocol, the selected ASP (transmitter) outputs the logic one Data bit-pair on its PTDO output to the SBM's (receiver) TDI input. In the timing diagram of Figure 10, logic one Data bit-pairs are shown output from the transmitter on the falling edge of the TCK, and are input to the receiver on the rising edge of the TCK. In Figure 11, an encoded logic zero signal, called Data (D), is identified by the transfer of a logic one bit followed by a logic zero bit from a transmitter to a receiver. During the select protocol, the SBM (transmitter) outputs the logic zero Data bit-pair on its TDO output to the ASP's (receivers) PTDI inputs. During the acknowledge protocol, the selected ASP (transmitter) outputs the logic zero Data bit-pair on its PTDO output to the SBM's (receiver) TDI input. In the timing diagram of Figure 11, logic zero Data bit-pairs are shown as output from the transmitter on the falling edge of the TCK, and are input to the receiver on the rising edge of the TCK. Note that the definitions of a logic one DATA bit-pair represented by a 0 and 1 bit sequence and a logic zero DATA bit-pair represented by a 1 and 0 bit sequence could be reversed without departing from the nature of the invention. Also note that the rising edge and falling edge timing nature of the bit-pairs may be redefined as required in an application without departing from the nature of the invention. The definitions of the Idle bit-pair represented by two successive 1's and the Select bit-pair represented by two successive 0's could be switched without departing from the scope of the invention. However, in the 1149.1 serial bus application of the invention, the definitions of the Idle and Select bit-pairs as shown in Figures 1 and 2 are very important. When the 1149.1 serial bus is in its RESET or IDLE state, the TDO output from the SBM and slave devices is disabled to a high logic level. While the 1149.1 serial bus is in the RESET or IDLE states, the inventions protocol can be output on the bus. Since both the select and acknowledge protocols start and stop by outputting IDLE bit-pairs, it makes sense that the Idle bit-pairs be of the same logic level as the disabled TDO outputs are in, i.e. a high logic level. Thus the definition shown for the Idle bit-pair, two success logic ones, enables a clean transition between the 1149.1's protocol and the inventions protocol. Unintentional entry into the ASP protocol of the invention is also avoided by the use of this definition of the Idle bit-pair. In the diagram of Figure 12 an example of the ASP select and acknowledge protocols are shown. In the diagram the sequence framed between the first and second Idle (I) bit-pair signals following the "TDO to PTDI" indication is the select protocol output from the SBM's TDO output to the ASP's PTDI inputs. The sequence framed between the first and second Idle bit-pair signals (I) following the "PTDO to TDI" indication is the acknowledge protocol output from the selected ASP's PTDO output to the SBM's TDI input. The select protocol always precedes the acknowledge protocol, as shown in the diagram. Inside the select and acknowledge protocols, first and second Select bit-pair signals (S) frame a sequence of Data (D) bit-pair symbols. The sequence of "2's" following the TCK indication represents the number of test clocks required for each bit-pair signals transferred during each protocol. For clarification, a time line reference is shown to indicate the order in time in which the bit-pair signals are transferred. As shown in Figure 12, the ASP protocol can be executed during times when the 1149.1 serial bus is idle in its RESET or IDLE states, to select a board for serial access. The "T" signals in the protocol sequences in Figure 12 indicate tri-state conditions on the TDO output from the SBM and the PTDO output from the ASP. The tri-state conditions are placed on the TDO and PTDO outputs whenever the 1149.1 serial bus is idle in the RESET or IDLE state. When a T signal is shown in the protocol sequence, the logic level on the wiring channel will be a logic one due to pull-up resistance on the TDI and PTDI inputs connected to the PTDO and TDO outputs. The ASP protocol of the invention takes advantage of this 1149.1 pull-up requirement by defining the Idle bit-pair to be two logic ones, so that when the invention's protocol is idle, i.e. when no select or acknowledge protocols are being transmitted, the logic level it drives onto the bus is indistinguishable from the T signal logic level. Thus the Idle bit-pair encoding is necessary to making the invention transparent to the normal operation of the 1149.1 serial bus. In an alternative serial bus, where the inactive state of the bus drives the data wiring channels to a low logic level, it would be necessary to encode the Idle bit-pair as two logic zeros and the Select bit-pairs as two logic ones to enable the invention to operate transparently with that serial bus protocol. The I signals in the protocol sequences indicate the transfer of an Idle bit-pair (two logic ones). The I signals are transferred at the beginning and ending of both the select and acknowledge protocols, to frame the protocols. The I signal transfer at the beginning of the select and acknowledge protocols is indistinguishable from the existing logic state of the wiring channel, since the T signals indicate that the wiring channel is pulled up to a logic one level. However, the I signal transfer at the end of the select and acknowledge protocol is distinguishable from the other preceding Select and Data bit-pairs (S & D) since the I signal is the only bit-pair defined by a two bit sequence of logic ones. The S signals in the protocol sequences indicate the transfer of a Select bit-pair (two logic zeros). The S signals are transferred at the beginning and ending of a sequence of Data bit-pair (D) transfers, to frame the data transfer operation. Framing of the Data bit-pair transfer is possible since the S signals at the beginning and ending of the data transfer are distinguishable from the I and D signals, since the S signals are the only bit-pair defined by a two bit sequence of logic zeros. The D signals in the protocol sequences indicate the transfer of a Data bit-pair. A logic zero Data bit-pair is a logic one bit followed by a logic zero bit. A logic one Data bit-pair is a logic zero bit followed by a logic one bit. The D signals are transferred after the first S signal is transferred and continue until the second S signal is transferred. The logic zero D signal is distinguishable from the I, S, and logic one D signals. The logic one D signal is distinguishable from the I, S, and logic zero D signal. A series of D signal transfers between the first and second S signals in the select and acknowledge protocols is referred to hereinafter as an address or an "A" signal. The number of D signals transferred within an address frame can be selected to be either a fixed or variable number. If fixed address framing is selected, all addresses framed between first and second S signals will be contain the same number of D signals. If variable address framing is selected, the number of D signals transferred within an address is determined by the occurrence of the first and second S signals. The advantage of fixed address framing over variable address framing is that address lengths are predictable during fixed framing, thus short or long addresses can be detected as failures, improving the fault tolerance of the invention's select and acknowledge protocols. Figure 13 depicts an example of select and acknowledge protocol signals (I,S,A) as transferred between an SBM and board resident ASP to enable scan access of board ICs Bd1 via the 1149.1 serial bus. In Figure 13, the SBM is shown to be connected to only one board, however multiple boards are actually connected to the SBM as shown in Figure 6. The SBM has a transmitter circuit XMT to output the select protocol to the ASP from TDO to PTDI, a receiver circuit RCR to receive the acknowledge protocol from the ASP from PTDO to TDI, and a master control circuit MCC to regulate the operation of the transmitter and receiver circuits. When the SBM's transmitter circuit is not being used to output the select protocol, it can be used to output serial data to the selected board via the ASP during 1149.1 scan operations. Likewise, when the SBM's receiver circuit is not being used to receive the acknowledge protocol, it can be used to receive serial data from the selected board via the ASP during 1149.1 scan operations. The SBM's transmitter and receiver circuits are controlled by the master control circuit to either transmit and receive the 1149.1 serial bus protocol or the inventions protocol. The ASP has a receiver circuit RCR to receive the select protocol from the SBM, a transmitter circuit XMT to output the acknowledge protocol to the SBM, and a slave control circuit SCC to regulate the operation of the transmitter and receiver circuits. The receiver, transmitter, and slave control circuits are part of the control logic section of the ASP block diagram of Figure 7. If the ASP's receiver and transmitter circuits are not being used to communicate the select and acknowledge protocols, and if the ASP is selected, the receiver and transmitter circuits allow serial data to flow through the ASP from PTDI to STDO and from STDI to PTDO during 1149.1 scan operations. Also when the ASP is selected the TCK and TMS outputs from the SBM pass through the ASP via the PTCK to STCK and PTMS to STMS signal paths to control the board ICs during 1149.1 scan operations. When scan access of board BD1 is required, the SBM's master control circuit causes the transmitter to output the select protocol signal sequence of ISASI to the ASP's receiver while the 1149.1 bus is idle. The "A" signal framed between the first and second S signals is a series of D signals equal to the address of board 1. At the end of the select protocol transmission from the SBM, the slave control circuit of the ASP checks the address input to the receiver circuit to see if it matches the boards address. If a match occurs the ASP's slave control circuit enables the ASP's transmitter circuit to output the acknowledge protocol signal sequence of ISASI to the SBM's receiver and then electronically connects the backplane and board level serial bus signals together. At the end of the acknowledge protocol transmission from the ASP, the master control circuit of the SBM checks the address input to the receiver circuit to see if the expected board address has been returned. If the expected address is returned, the master control circuit of the SBM enables the transmitter and receiver circuits to perform 1149.1 scan operations to serially access the ICs of board 1. During the scan operation the SBM outputs serial data and control to the board, via the ASP, from its TDO and TMS outputs and receives serial data from the board, via the ASP, on its TDI input. The SBM's TCK output free-runs, so it always provides a clock input to the ASP and board. A state diagram of the operation of the SBM's and ASP's transmitter circuits is shown in Figure 14. The SBM's transmitter circuit is a master transmitter and the ASP's transmitter is a slave transmitter. The SBM uses its transmitter circuit to send the select protocol sequence and the ASP uses its transmitter circuit to send the acknowledge protocol sequence. The SBM outputs on its transmitter whenever it is necessary to send a select protocol, but the ASP can only output the acknowledge protocol on its transmitter in response to a select protocol transmission from the SBM. Since the select and acknowledge protocol sequences are identical, a common transmitter circuit design can be used in both SBM and ASP devices, simplifying the implementation of the invention circuitry. In the state diagram, the transmitter circuit is forced into the Transmitter Disabled state while the 1149.1 bus is active. This state insures that the transmitter cannot be inadvertently enabled, while the 1149.1 bus is in operation, to output select or acknowledge protocols. When the 1149.1 bus is idle, the transmitter circuit enters into the Transmitter Idle state. If it is not necessary to output a select or acknowledge protocol, the transmitter circuit remains in the Transmitter Idle state until the 1149.1 bus becomes active again, in which case the transmitter circuit returns to the Transmitter Disabled state. If it is necessary to output a select or acknowledge protocol, while in the Transmitter Idle state, the transmitter circuit enters the Send Idle Signal state to output the first I signal, then enters the Send Select Signal state to output the first S signal, then enters the Send Address state to output a series of D signals indicating the address, then enters the Send Select Signal state to output the second S signal, then enters the Send Idle Signal state to output the second I signal, and then returns to the Transmitter Idle state. After the protocol has been sent, the transmitter returns to the Transmitter Disabled state whenever the 1149.1 bus becomes active. A state diagram of the operation SBM's and ASP's receiver circuits is shown in Figure 15. The ASP uses its receiver circuit to receive the select protocol sequence and the SBM uses its receiver circuit to receive the acknowledge protocol sequence. Since the received select and acknowledge protocol sequences are identical, a common receiver circuit design can be used in both SBM and ASP devices, simplifying the implementation of the invention. In the state diagram, the receiver circuit is forced into the Receiver Disabled state while the 1149.1 bus is active. This state insures that the receiver cannot be inadvertently enabled, while the 1149.1 bus is in operation, to receive a false input condition. When the 1149.1 bus is idle, the receiver circuit enters into the Receiver Idle state. If the 1149.1 bus becomes active again, the receiver circuit returns to the Receiver Disabled state. While in the Receiver Idle state, the receiver circuit polls for the occurrence of an I or S signal. In response to an I signal, the receiver remains in the Receiver Idle state. In response to an S signal, the receiver signals the occurrence of a first S signal to the associated master or slave control circuits MCC or SCC and transitions into the Start Address Input state to start the address input operation. When a transition into the Start Address Input state occurs, the receiver circuit polls for the occurrence of an I, S, or D signal. In response to an I or S signal input, the receiver circuit will transition from the Start Address Input state back into the Receiver Idle state and signal the master or slave control circuit that a false first S signal had been received. This transition path provides; (1) a method of returning receiver circuit to the Receiver Idle state in the event that the receiver transitioned into the Start Address input state in response to an error input, and (2) a method of signaling the associated master or slave control circuit that a select or acknowledge protocol had not actually been started and to reset and begin looking for the next occurrence of a first S signal indication. In response to a D signal input, the receiver circuit transitions from the Start Address input state into the Input Address state and starts receiving the transmitted address. The receiver remains in the Input Address state and continues receiving the address while D signals are being input. In response to an S signal, the receiver circuit stops inputting the address, signals the occurrence of the second S signal to the associated master or slave control circuit, and transitions from the Input Address state into the Stop Address Input state. When the ASP's receiver enters the Stop Address Input state, the slave control circuit matches the address input to the ASP against the board's address to see if the board has been selected. The ASP's receiver transitions from the Stop Address Input state to the Receiver Idle state in response to an I signal input from the SBM. If the address input matches the board address, the ASP's slave control circuit instructs the ASP's transmitter circuit to send an acknowledge protocol to the SBM's receiver and then connects the backplane serial bus to the boards serial bus. When the SBM's receiver enters the Stop Address Input state, the master control circuit matches the address input to the SBM against the expected board address to see if the correct board has been selected. The SBM's receiver transitions from the Stop Address Input state to the Receiver Idle state in response to an I signal input from the ASP. If the address input matches the expected board address, the SBM's master control circuit can serially access the board using the 1149.1 serial bus protocol. If the address input does not match the expected board address, the SBM's master control circuit will not attempt to serially access the board and will report the failure. A state diagram of the operation of the SBM's master control circuit is shown in Figure 16. The master control circuit regulates the operation of the SBM's transmitter and receiver circuits. The master control circuit can enable the SBM's transmitter and receiver circuits to communicate to the ASPs using either the 1149.1 serial bus protocol or the inventions select and acknowledge protocols. Initially, the master control circuit will communicate to the ASPs using the inventions select and acknowledge protocols to select a board for serial access. After a board has been selected the master control circuit serially accesses the board using the 1149.1 serial bus protocol. The state diagram of Figure 16 shows that when no board is being accessed, the master control circuit is in the Master Control Circuit Idle state. If access is required to a board whose ASP has previously been selected, the master control circuit can transition from the Master Control Circuit Idle state to the Scan Board state and serially access the board using the 1149.1 protocol. However, if the boards ASP has not been previously selected or if a new board is to be accessed, the master control circuit must select the board's ASP before entering the Scan Board state. To select a board's ASP, the master control circuit transitions from the Master Control Circuit Idle state into the Transmit Select Protocol state. In the Transmit Select Protocol state, the master control circuit loads the SBM's transmitter circuit with the address of the board to be selected, and then enables the transmitter circuit to transmit a select protocol sequence to select the board's ASP. After enabling the transmitter circuit to send the select protocol, the master control circuit transitions from the Transmit Select Protocol state to the Receive Acknowledge Protocol state. In the Receive Acknowledge Protocol state, the master control circuit enables the SBM's receiver circuit to receive the acknowledge protocol from the selected ASP. After the acknowledge protocol is received, the master control circuit transitions from the Receive Acknowledge Protocol state into the Expected Address Received? state to verify that the address of the selected ASP was received. If an incorrect address was received, the master control circuit aborts the board select operation and transitions from the Expected Address Received? state into the Report Address Error state. In the Report Address Error state, the master control circuit reports the address failure and places the SBM's transmitter and receiver circuits into their idle state. If the correct address is received, the master control circuit may either transition from the Expected Address Received? state into the Master Control Circuit Idle state and access the selected board at a later time, or transition into the Scan Board state to immediately access the board using the 1149.1 serial bus protocol. In either case, when the master control circuit does enter the Scan Board state, it configures the SBM's transmitter and receiver circuits to where they can be used to communicate with the board using the 1149.1 serial bus protocol. After the board has been serially accessed in the Scan Board state, the master control circuit transitions from the Scan Board state into the Master Control Circuit Idle state, where it disables the SBM's transmitter and receive circuits and remains until it is required to serially access the same or another board. A state diagram of the operation of the ASP's slave control circuit is shown in Figure 17. The slave control circuit regulates the operation of the ASP's transmitter and receiver circuits. The slave control circuit enables the ASP's transmitter and receiver circuits to communicate to the SBM using the inventions select and acknowledge protocols. After the ASP has been selected by the SBM, the slave control circuit enables the transmitter and receiver circuits to pass the serial data input and output through the ASP during 1149.1 scan operations. In the state diagram, it is seen that when no select protocols are being sent from the SBM to the ASP, the slave control circuit will be in the Slave Control Circuit Idle state. When the start of a select protocol is received by the ASPs receiver circuit the slave control circuit will transition from the Slave Control Circuit Idle state into the Receive Select Protocol state. After the select protocol is received, the slave control circuit transitions from the Receive Select Protocol state into the Address Match? state. In the Address Match? state the slave control circuit reads the address received by the ASP's receiver circuit and compares the address against the board address. If the address does not match the ASP's board address, the slave control circuit transitions from the Address Match? state into the Disconnect Buses state to disconnect any previously connected board to backplane bus signals inside the ASP. From the Disconnect Buses state the slave control circuit transitions into the Slave Control Circuit Idle state and waits for the start of another select protocol sequence. If the address matches the ASP's board address, the slave control circuit transitions from the Address Match? state into the Transmit Acknowledge Protocol state. In the Transmit Select Protocol state, the slave control circuit loads the board address into the ASP's transmitter circuit and then enables the ASP's transmitter circuit to transmit an acknowledge protocol sequence to the SBM's receiver circuit to verify the ASP is selected and the board to backplane connections are made. After the acknowledge protocol is sent the slave control circuit disables the ASP's transmitter and transitions from the Transmit Acknowledge Protocol state into the Connect Buses state. In the Connect Buses state the slave control circuit outputs control to connect the board and backplane bus signals inside the ASP, enabling the SBM to serially access the board ICs using the 1149.1 serial bus protocol. After the buses are connected the slave control circuit transitions from the Connect Buses state into the Slave Control Circuit Idle state to wait for the start of another select protocol input from the SBM. Figure 18 depicts one possible circuit implementation of the Addressable Shadow Port hardware. The receiver circuit RCR consists of a controller for regulating the protocol input from the SBM, and a serial input/parallel output SIPO register for receiving the serial address from the SBM and outputting the address in parallel to the slave control circuit. The PTDI signal is input to the SIPO register to supply the serial address during select protocols, and is input to the controller for regulating the operation of the receiver during select protocols. The parallel address output from the SIPO register is input to the slave control circuit via the address input to the slave controller circuit to indicate when a select protocol has started, when the address is ready to read, and when the select protocol has completed. The receiver's RCR controller determines when a first "I then S then D" signal sequence occurs on PTDI, indicating the start of the select protocol and the start of the address input. In response to this input the controller enables the SIPO to receive the serial address input on PTDI. The RCR controller next determines when a first "D then S then I" sequence occurs on the PTDI signal, indicating the end of the address input and select protocol. In response to this input sequence, the RCR controller sends status to the slave control circuit to enable the address in the SIPO register to be parallel input to the slave control circuit via the AI bus, and terminates the select protocol input operation. The transmitter circuit XMT consists of a controller for regulating the acknowledge protocol output from the ASP, and a parallel input/serial output or PISO register for receiving the parallel ASP address from the slave control circuit and outputting the address serially to the PSBM. The PISO register receives parallel data from the slave control circuit via the address output bus AO, and outputs the address serially to multiplexer MX1 via the acknowledge protocol output signal APO. The XMT controller receives control input from the slave control circuit via the control bus, and outputs status to the slave control circuit via the status bus. Control input on the XMT control bus regulates the parallel to serial conversion process that takes place during the acknowledge protocol. The status output from the transmitter XMT informs the slave control circuit of the transmitters status during the acknowledge protocol, i.e. whether the acknowledge protocol is in progress or is completed. At the beginning of an acknowledge protocol, the slave control circuit enables multiplexer MX1 and the tri-state buffer 3SB to pass the APO signal from the transmitter to the PTDO output. The slave control circuit then inputs the ASP address to transmitter XMT via the AO bus, which is then to be shifted out on PTDO. In response to the address input, the transmitter XMT outputs a I and S signal on output PTDO to start the acknowledge protocol, then serially transmits the address on PTDO. After the address is shifted out, the transmitter circuit XMT outputs an S and I signal sequence to stop the acknowledge protocol. The slave control circuit is a controller that regulates the operation of the ASP transmitter circuit, receiver circuit RCR, and multiplexers MX1 and MX2 in response to matching address input during a select protocol. The slave control circuit receives the PTMS and PTCK signals from the primary port of the ASP, the address input AI and status buses from the receiver RCR, the status bus from transmitter XMT, the external ASP board address signals, a reset signal from the power up reset circuit PRST, and reset address signals from the reset address circuit RSTA. The slave control circuit outputs control to the receiver circuit RCR, transmitter circuit XMT, tri-state buffers 3SBs, and multiplexers MX1 and MX2. The slave control circuit is clocked by the PTCK input from the primary port. The PTMS input from the primary port indicates to the slave control circuit when the 1149.1 bus is busy, idle or reset. The status inputs from the receiver and transmitter circuits inform the slave control circuit of the receiver and transmitter circuit status. The AI bus from the receiver is used to input the address received during a select protocol to the slave control circuit. The reset input from the PRST circuit resets the slave control circuit at powerup. The reset address input from the RSTA circuit allow resetting the slave control circuit via a reset address input from a select protocol operation. The control output from the slave control circuit controls the operation of the receiver, transmitter, and MX1 and MX2. The AO bus output from the slave control circuit is used to input the ASPs parallel address to the transmitter during acknowledge protocols. During select protocols, the slave control circuit receives parallel address input from the receiver RCR via the AI bus. The status bus input from the receiver RCR informs the slave control circuit when a select protocol has started, when the address input is ready, and when the select protocol is complete. From the address input AI, the slave control circuit determines whether a match occurred and it has been selected. If the received address matches the board address the ASP responds by outputting an acknowledge protocol, then connects the ASP primary and secondary ports together. During acknowledge protocols, the slave control circuit outputs control to the transmitter XMT to start an acknowledge protocol, and also to input the ASP address to the transmitter XMT via the AO bus for output during the acknowledge protocol. The status bus input from the transmitter XMT informs the slave control circuit when the acknowledge protocol starts and completes. After the acknowledge protocol completes, the slave control circuit outputs control to enable the STDO and PTDO tri-state buffers 3SBs, and connects PTMS to STMS via multiplexer MX2, and STDI to PTDO via mux MX1. Multiplexer MX1 receives selection control input from the slave control circuit and the APO signal from the transmitter XMT and the STDI signal from the secondary port of the ASP. MX1 outputs the selected input (STDI or APO) to the PTDO output signal via 3-state output buffer 3SB. The output buffer 3SB is enabled or disabled (tri-stated) by a control input from the slave control circuit. Multiplexer MX2 also receives selection control from the slave control circuit, the PTMS signal from the primary port, and a logic 0 and 1 input. In response to the control input MX2 outputs the selected data input PTMS, logic 0, or logic 1 to the STMS output signal. When power is first applied to the ASP hardware, the slave control circuit is reset by an input from the power-up reset circuit PRST, which deselects the ASP from the backplane. When reset, the slave control circuit outputs control to: reset the transmitter and receiver circuits to their idle states, disable the STDO and PTDO outputs to a logic 1 via their tri-state buffers 3SB, cause the STMS signal to output a logic 1 from multiplexer MX2, and cause the STCK signal to output the PTCK clock. The logic 1 output on the STMS signal and the free running clock on STCK insure that the board level serial bus is disabled and the TAPs of the ICs on the board are transitioned into their RESET state as shown in Figure 2. While an internal power-up reset PRST circuit is illustrated, the reset could also be achieved by other means, such as inputting a reset signal to the slave control circuit using an external reset input signal. The ASP can also be reset by inputting a select protocol with an address that matches the reset address RSTA as shown in Figure 18. The reset address is a fixed address that is input to the slave control circuit and matched against the address input from the receiver circuit after a select protocol has been received. If the address input matches the reset address, the ASP is reset to the same state as described in the power-up reset. The fixed reset address is the same for all ASPs so that a global reset of all ASPs can be achieved by the transmission of a single select protocol containing the reset address. Since the reset address is used to reset the ASP, it must be unique and not reused as a board address. A preferred value for the ASP reset address is zero, since board address numbering will usually start with an address of 1 and go up through address N as shown in Figure 6. When the SBM of Figure 6 inputs a select protocol containing the reset address zero , the ASPs respond by resetting and deselecting themselves from the backplane serial bus. Also there is no acknowledge protocol transmitted from the ASPs to the SBM whenever a reset address is input via a select protocol. Elimination of the acknowledge protocol is required to avoid contention.of logic states that would occur between the PTDO outputs of multiple ASPs during an acknowledge protocol transmission. When the SBM places the 1149.1 backplane serial bus in the RESET state (as shown in Figure 2), the PTMS signal will be at a logic 1 state, the PTCK signal will be active, and the PTDI and PTDO signals will be disabled to a high logic state (T condition of Figure 12). If, during the RESET state, the SBM inputs a select protocol to the ASP and the address matches the ASP's board address, the ASP will be selected and respond back to the SBM with an acknowledge protocol. During the acknowledge protocol, the slave control circuit enables the PTDO tri-state buffer 3SB and selects the acknowledge protocol output APO as data output by multiplexer MX1 so that the transmitter circuit XMT can output the acknowledge protocol. After transmitting the acknowledge protocol, the slave control circuit connects the board and backplane serial buses together. During the connection process, the STDO tri-state buffer 3SB is enabled to output the PTDI backplane signal, mux MX1 is switched from outputting the APO input on PTDO to outputting the STDI board signal input on PTDO, the PTDO tri-state buffer 3SB remains enabled, and mux MX2 is switched from outputting either the logic 1 or 0 input on STMS to outputting the PTMS backplane signal input. The following three scenarios describe what happens on the STMS output when an ASP that has previously been: (1) reset, (2) deselected and left in the RESET state, or (3) deselected and left in the IDLE state, is selected while the backplane 1149.1 bus is the RESET state. (1) If the ASP is selected (while the backplane bus is in the RESET state) after being reset, multiplexer MX2 switches from outputting the logic 1 input on STMS to outputting the present PTMS backplane signal on STMS. Since the PTMS signal is a logic 1 when the backplane bus is in the RESET state, the STMS output signal remains at a logic 1 during the connection process. (2) If the ASP is selected (while the backplane bus is in the RESET state) after having been previously deselected while the backplane bus was in the RESET state (PTMS is a logic 1 level in the RESET state), mux MX2 switches from outputting the previous PTMS state (logic 1 input) on STMS to outputting the present PTMS backplane signal on STMS. Since signal PTMS is a logic 1 when the backplane bus is in the RESET state, the signal STMS output remains at a logic 1 during the connection process. (3) If the ASP is selected (while the backplane bus is in the RESET state) after having been previously deselected while the backplane bus was in the IDLE state (PTMS is a logic 0 level in the IDLE state), mux MX2 switches from outputting the previous PTMS state (logic 0 input) on STMS to outputting the present PTMS backplane signal on STMS. Since the PTMS is a logic 1 when the backplane is in the RESET state, the STMS output changes from outputting a logic 0 to outputting a logic 1 during the connection process. When the SBM places the 1149.1 backplane serial bus in the RESET state (Figure 2), the PTMS signal will be at a logic 1 state, the PTCK signal will be active, and the PTDI and PTDO signals will be disabled to a high logic state (T condition of Figure 12). If, during the RESET state, the SBM inputs a select protocol to select a new ASP, the presently selected ASP becomes deselected and disconnected from the backplane bus by control output from the ASP's slave control circuit. During the disconnection process, the STDO and PTDO outputs are disabled to a logic 1 state via their tri-state buffers 3SB, mux MX1 continues to select and output the STDI signal to the input of the PTDO 3SB, and mux MX2 is switched from outputting the high logic level from the PTMS backplane signal (PTMS is high when backplane bus is in the RESET state) on STMS to outputting the logic 1 input on STMS. By forcing MX2 to select and output the logic 1 input on the STMS output, the board level 1149.1 serial bus remains in the RESET state after the ASP is deselected. The invention thus allows the ASP to keep the board level 1149.1 serial bus in the RESET state after it has been deselected. When the SBM places the 1149.1 backplane serial bus in the IDLE state (Figure 2), the PTMS signal will be at a logic 0 state, the PTCK signal will be active, and the PTDI and PTDO signals will be disabled to a high logic state (T condition of Figure 12). If, during the IDLE state, the SBM inputs a select protocol to the ASP and the address matches the ASP's board address, the ASP will be selected and respond back to the SBM with an acknowledge protocol. During the acknowledge protocol, the slave control circuit enables the PTDO tri-state buffer 3SB and selects the acknowledge protocol output signal APO to mux MX1 so that the transmitter circuit can output the acknowledge protocol. After transmitting the acknowledge protocol, the slave control circuit connects the board and backplane serial buses together. During the connection process, the STDO tri-state buffer 3SB is enabled to output the PTDI backplane signal, mux MX1 is switched from outputting the APO input on PTDO to outputting the STDI board signal input on PTDO, the PTDO tri-state buffer 3SB remains enabled, and mux MX2 is switched from outputting either the logic 1 or 0 input on the STMS signal to outputting the PTMS backplane signal input on the STMS signal. The following three scenarios describe what happens on the STMS output when an ASP that has previously been; (1) reset, (2) deselected and left in the RESET state, or (3) deselected and left in the IDLE state, is selected while the backplane 1149.1 bus is the IDLE state. (1) If the ASP is selected (while the backplane bus is in the IDLE state) after having been previously reset, MX2 switches from outputting the logic 1 input on STMS to outputting the present PTMS backplane signal on STMS. Since PTMS is a logic 0 when the backplane bus is in the IDLE state, the STMS output changes from outputting a logic 1 to outputting a logic 0 during the connection process. (2) If the ASP is selected (while the backplane bus is in the IDLE state) after having been previously deselected while the backplane bus was in the RESET state (PTMS is a logic 1 level in the RESET state), mux MX2 switches from outputting the previous PTMS state (logic 1 input) on STMS to outputting the present PTMS backplane signal on STMS. Since PTMS is a logic 0 when the backplane bus is in the IDLE state, the STMS output changes from outputting a logic 1 to outputting a logic 0 during the connection process. (3) If the ASP is selected (while the backplane bus is in the IDLE state) after having been previously deselected while the backplane bus was in the IDLE state (PTMS is a logic 0 level in the IDLE state), MX2 switches from outputting the previous PTMS state (logic 0 input) on STMS to outputting the present PTMS backplane signal on STMS. Since the PTMS is a logic 0 when the backplane is in the IDLE state, the STMS output remains at a logic 0 during the connection process. When the SBM places the 1149.1 backplane serial bus in the IDLE state (Figure 2), the PTMS signal will be at a logic 0 state, the PTCK signal will be active, and the PTDI and PTDO signals will be disabled to a high logic state (T condition of Figure 12). If, during the IDLE state, the SBM inputs a select protocol to select a new ASP, the presently selected ASP becomes deselected and disconnected from the backplane bus by control output from the ASP's slave control circuit. During the disconnection process, the STDO and PTDO outputs are disabled to a logic 1 state via their tri-state buffers 3SB, multiplexer MX1 continues to select and output the STDI signal to the input of the PTDO 3SB, and mux MX2 is switched from outputting the low logic level from the PTMS backplane signal (PTMS is low when backplane bus is in the IDLE state) on STMS to outputting the logic 0 input on STMS. By forcing multiplexer MX2 to select and output the logic 0 input on the STMS output, the board level 1149.1 serial bus remains in the IDLE state after the ASP is deselected. The invention thus allows the ASP to keep the board level 1149.1 serial bus in the IDLE state after it has been deselected. Although this application has discussed the ASP protocol in terms of the standard 1149.1 serial bus, the ASP protocol herein described may be used with any other serial bus and protocol, as will be recognized by those skilled in the art. The invention can be used with other pre-existing or newly defined serial buses to provide a method of serially connecting a slave device (IC, board, etc) up to an SBM. For example, a typical serial bus is comprised of the following signal types. A control signal (like TMS) that regulates the normal operation of the serial bus. A clock signal (like TCK) that times the flow of serial data through devices on the serial bus. A serial data input signal (like TDI) for inputting data to a slave device. A serial data output signal (like TDO) for outputting data from a slave device. Since the normal operation of the serial bus is regulated by a control signal (like TMS), the protocol developed for the ASP avoids using this signal to select or deselect slave devices. By designing the ASP's protocol to be independent of a particular serial bus's control signal, the inclusion of invention into existing serial buses does not require modifying the serial bus's normal mode of operation. The ASP circuit can exist as a packaged IC for assembly on a printed circuit board, an unpackaged die for assembly on a multi-chip module substrate, a subcircuit within an integrated circuit, or an embedded circuit in a multi-chip module semiconductor substrate. Other alternative implementations are possible and are considered within the scope of this application and its claims. While the description of the invention herein illustrates the ASP circuit as being a board mounted device operable to selectively interface 1149.1 serial bus signals at the backplane level into 1149.1 serial bus signals at the board level, the ASP circuit can be used at any level of electronic assembly to provide a serially addressable interface between an SBM and slave devices on a serial bus. For example, in Figure 6 the ASP circuit could be viewed as a circuit providing interface between the SBM and: (1) multiple subcircuits (1-n) connected to a common serial bus inside an IC, (2) multiple ICs (1-n) connected to a common serial bus on a multi-chip module, (3) multiple ICs (1-n) connected to a common serial bus on a board, (4) multiple boards (1-n) coupled to a common serial bus on a backplane, (5) multiple backplanes connected to a common serial bus in a subsystem, (6) multiple subsystems (1-n) connected to a common serial bus in a system, or (7) multiple systems (1-n) connected to a common serial bus network. These and other applications are also considered within the scope of this application. Figure 19 depicts an alternative preferred embodiment of the invention in a circuit 13 having three separate secondary ports, each coupled to the primary ports by means of separately addressable ASP circuits ASP-1, ASP-2 and ASP-3. In some board designs, the 1149.1 serial bus may be partitioned into separate scan paths. To individually select and access each scan path from the backplane 1149.1 bus, via the primary port, separate ASPs are required. However, to reduce the number of ASP circuits on a board, multiple ASP circuits may be packaged in one IC as shown in Figure 19. Each ASP circuit ASP-1, ASP-2, ASP-3 has its own unique address (01, 10, 11) and a common connection to the primary port so that it and only it can be selected and enabled to allow the backplane 1149.1 bus to access the desired boards level scan path via the respective ASPs secondary port (SP1-SP3 in the figure.) To reduce the IC package size, the individual ASP addresses may be hardwired inside the IC or programmed using fuse, RAM, ROM or other programmable logic inside the device, thus eliminating the need for IC package pins for the ASP addresses. Figure 20 depicts an application specific IC or ASIC 35 which has a built in ASP, an address input, and an internal serial test bus coupled to various large application logic blocks 37, each of which has a separate TAP test port 39. This figure demonstrates that for highly dense VLSI IC's or multiple chip modules the ASP invention may be used to efficiently provide access to these internal scan paths as well.

Claims: A system comprising a master device (SBM) and a plurality of slave devices (11) connected by a communication bus (TDI, TDO, TMS, TCK); each slave device (11) comprising an addressable port circuit (ASP) operable to connect the communication bus to or disconnect the communication bus from a bus of the slave device that uses the same bus protocol as the said communication bus; each addressable port circuit (ASP) comprising: a primary port (PTDI, PTDO, PTMS, PTCK) to which the communication bus is connected; a secondary port (STDI, STDO, STMS, STCK) to which the bus of the slave device is connected; connection means (MX1, MX2, 3SB) connected to said primary and secondary ports and operable to connect the communication bus to or disconnect the communication bus from the said bus of the slave device in response to a control signal; and control circuitry to generate said control signal in response to a selection sequence issued by the master device; wherein when said communication bus is not used for normal communication according to the bus protocol (IDLE, RESET) the master device (SBM) can send out a selection sequence on the said communication bus using a protocol different from the normal communication protocol to specify the logical address of a slave device (11) to be selected next; and the control circuitry in each slave device (11) is arranged to check whether or not an address issued by the master device (SBM) corresponds to the logical address of that slave device; if that address does not correspond the control circuitry is arranged to send a message to the connection means to disconnect the bus of that slave device from the communication bus; and if that address does correspond the control circuitry is arranged to send a message to the connection means to connect the bus of that slave device to the communication bus, in such a way that they are perceived by the system as a single communication bus. A system according to claim 1, wherein said communication bus is a serial communication bus. A system according to claim 2, wherein said communication bus is a test bus on a system backplane. A method of operating a system comprising a master device (SBM) and a plurality of slave devices (11) connected by a communication bus (TDI, TDO, TMS, TCK) each slave device (11) comprising an addressable port circuit (ASP) operable to connect the communication bus to and disconnect the communication bus from a respective slave bus of each slave device that uses the same bus protocol as the communication bus; each addressable port circuit (ASP) comprising: a primary port (PTDI, PTDO, PTMS, PTCK) to which the communication bus is connected; a secondary port (STDI, STDO, STMS, STCK) to which the bus of the slave device is connected; connection means (MX1, MX2, 3SB) connected to said primary and secondary ports and operable to connect the communication bus to or disconnect the communication bus from the said bus of the slave device in response to a control signal; and control circuitry to generate said control signal in response to a selection sequence issued by the master device; comprising the steps of: while said communication bus is not being used for normal communication according to the bus protocol (IDLE, RESET) sending out from the master device (SBM) on the said communication bus using a protocol different from the normal communication protocol a selection sequence specifying the logical address of a slave device (11) to be selected next; and the control circuitry in each slave device (11), checking whether or not the address specified by the master device (SBM) corresponds to the logical address of that slave device; in any slave device the address of which does not correspond to the address specified, the control device sends a message to disconnect the bus of that slave device from the communication bus; and in any slave device the address of which does correspond to the address specified, the control device sends a message to connect the bus of that slave device to the communication bus, in such a way that they are perceived by the system as a single communication bus. A method according to claim 4, wherein said communication bus is a serial communication bus. A method according to claim 5, wherein said communication bus is a test bus on a system backplane.

Inventors: WHETSEL LEE D, WHETSEL, LEE D.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1993
Main classification: G06F13
IPC codes: G06F13, H04L29, G01R31, G06F11