Digital signal processing apparatus employed in electronic musical instruments

Abstract: A designating mechanism generates filtering designation data, which designate the contents of filtering, reverberating designation data, which designate the contents of reverberation, and characteristics data, which express the combined contents of filtering and reverberation. A parameters generating mechanism generates filtering parameters expressing filtering characteristics, and generates reverberating parameters expressing reverberation characteristics. A readout device reads out a first operating algorithm, which designates filtering designation data, and a second operating algorithm, which designates reverberating designation data, from a memory mechanism wherein a plurality of operating algorithms are stored. A computing mechanism creates a digital filter having characteristics corresponding to filtering parameters, based on the first operating algorithm, creates an operating unit having reverberation characteristics corresponding to reverberating parameters, based on the second operating algorithm, operates this digital filter and this operating unit in a time shared manner, and processes filtering and reverberation in parallel.

Description: Field of the Invention The present invention relates to a digital signal processing apparatus which simultaneously applies various effects such as reverberation and chorus and the like with respect to a digital musical tone signal generated in an electronic musical instrument. Background Art Conventional examples of this type of digital signal processing apparatus include, for example, the effector disclosed in Japanese Patent Publication No. Hei 1-19593. This effector comprises a plurality of operators such as multipliers and adders. This apparatus applies reverberation and modulation effects such as chorus, flanger, and the like, with respect to a digital musical tone signal which is generated. In this type of apparatus, during, for example, one sampling period, after modulation effects have been applied, reverberation is applied. That is to say, in this type of apparatus, in the case in which a plurality of effects are applied to a digital musical tone signal, the processing for applying the various "effects" is conducted in order and consecutively. Accordingly, in such a conventional effector, while processing for the application of a given "effect" is being conducted, it is not possible to conduct processing for the application of a second "effect". As a result, the waiting period of the operators becomes large, and the effective efficiency of use of the operators worsens. In addition, as processes for the application of effects are executed in series, high speed processing is not possible. US-A-4,472,993 discloses a sound effect imparting device for an electronic musical instrument. The digital signal processor of this sound effect imparting device executes a modulation effect process and a reverberation effect process in one sampling period. By control data and parameter data which are respectively read out from a control unit and a parameter memory by means of a read out unit, switching of the operation mode of the digital arithmetic operation unit is controlled in a time-sharing manner, whereby a plurality of sound effects are imparted to a musical tone through digital arithmetic operations. However, in this sound effect imparting device of the prior art a modulation effect is first added within one sampling period of the digital musical tone signal and then a reverberation effect is sequentially added on a time-sharing basis in addition to the modulation effect. This means the processing for applying the modulation effect and the reverberation effect is conducted in order and consecutively. While processing for the application of a first effect is being conducted it is not possible to conduct processing for the application of the second effect simultaneously. As a result, the waiting period of the operators becomes large and the efficiencies of use of the operators worsens. High speed processing is not possible. EP-A-0 248 527 discloses a digital signal processing using waveguide networks. The digital waveguide networks have signal scattering junctions. A junction connects two waveguide sections together or terminates a waveguide. The junctions are constructed from conventional digital components such as multipliers, adders, and delay elements. The signal processor is typically used for digital reverberation and for synthesis of reed, string or other instruments. Summary of the Invention It is accordingly an object of the present invention to provide a digital signal processing apparatus capable of increasing the efficiency of use of the operators, and capable of conducting high speed processing even in cases in which a plurality of effects are to be applied. The invention is defined by the appended claim 1, with advantageous embodiments being defined by the appended dependent claims 2-9. In accordance with the type of composition as given by the present invention, the designating mechanism generates the filtering designation data, the reverberating designation data, and the characteristics data, which are a combination of the filtering and the reverberation. The parameters generating mechanism generates filtering parameters indicating filtering characteristics, and reverberating parameters indicating reverberation characteristics. The readout mechanism reads the first operating algorithm, which designates filtering designation data, and the second operating algorithm, which designates reverberating designation data, out of the memory mechanism, in which a plurality of operating algorithms are stored. The computing mechanism forms a digital filter having characteristics in accordance with the filtering parameters, based on the first operating algorithm, and further forms an operating unit having reverberation characteristics in accordance with the reverberating parameters, based on the second operating algorithm, and conducts time shared operating of this digital filter and operating unit, and conducts parallel processing of filtering and reverberation. Accordingly, as the digital filter which conducts the filtering of a musical tone signal, and the operating unit which applies reverberation to the musical tone signal, are operated in parallel, the efficiency of use of the operators can be increased, and processing can be accomplished rapidly, even in the case in which a plurality of effects are to be applied. Brief Description of the Drawings Fig. 1 is a block diagram showing the composition of a digital musical instrument in accordance with a preferred embodiment of the present invention. Fig. 2 is a block diagram showing the composition of operating signal generator 10 in the same preferred embodiment. Fig. 3 is a block diagram showing the composition of computing part 5 in the same preferred embodiment. Fig. 4 is a block diagram showing the composition of the digital filter, which is operated in a time shared manner, in computing part 5. Fig. 5 is a block diagram showing the composition of a reverberation effecting circuit, which is operated in a time shared manner in computing part 5. Fig. 6 is a block diagram showing the composition of the reverberation effecting circuit shown in Fig. 5, when this is divided into operating units. Fig. 7 is a block diagram showing the composition of the operating unit shown in Fig. 6. Fig. 8 is a diagram showing a timetable of the filtering and reverberation effecting process which is executed for each tone generation channel 0ch-31ch within a sampling period T. Fig. 9 is a timetable showing the contents of the filtering which is conducted in tone generation channel 0ch. Fig. 10 A,B is a timetable showing the control contents of operating unit A. Fig. 11 and 12 is a timetable showing the control contents of operating unit B. Detailed Description of the Preferred Embodiments (First Preferred Embodiment) Hereinbelow, preferred embodiments of the present invention will be explained with reference to the drawings. The digital signal processing apparatus explained in the present preferred embodiment is used in a digital musical instrument as an effector for conducting a filtering process and a reverberation effecting process which will be explained hereinbelow. (1) Overall Composition Fig. 1 is a block diagram showing the composition of an electronic musical instrument utilizing a digital signal processing apparatus in accordance with the present invention. In the figure, reference numeral 1 indicates a keyboard circuit. This keyboard circuit 1 generates key-on signals KON, key codes KC, and key-off signals KOFF, and the like, in accordance with the operation of the keyboard by a performer. Reference numeral 2 indicates a tone generation assignment circuit, which assigns the musical tone signal generated in correspondence with the depression of a key to any of a plurality of tone generation channels. The digital musical instrument in accordance with the present invention possesses 32 tone generating channels. Reference numeral 3 indicates a tone color parameters supplier, which supplies tone color parameters related to musical tones to be generated. This tone color parameters supplier 3 generates, for example, tone color codes NTC indicating tone color (a piano tone, organ tone, violin tone, or the like) from tone color information A, which is described hereinbelow, and generates tone color parameters indicating information relating to tone colors other than those expressed by tone color codes NTC. Reference numeral 4 indicates a tone generator. Tone generator 4 is provided with 32 tone generation channels 0-31ch, and generates digital musical tone signals with respect to each tone generation channel by means of time shared operating. Reference numeral 5 indicates a computing part; this conducts filtering with respect to musical tone signals supplied by tone generator 4, and conducts reverberation with respect to the output signals of a panning circuit 13, to be explained hereinbelow, in parallel and in a time-shared manner. This computing part 5 will be explained in detail hereinbelow. Reference numeral 6 indicates an operation panel comprising a plurality of operating members; it generates setting information in accordance with setting operations applied to these operating members, and supplies this setting information to setting part 7. In operation panel 6, various switches with are not indicated in the diagram are provided; for example, tone color selecting switches, and various switches for setting filtering characteristics or reverberation effecting. Setting part 7 transforms the setting information by means of the tone color information A indicating tone color numbers, and outputs this. Furthermore, setting part 7 creates characteristics data in accordance with the combined contents of the filtering characteristics and the reverberation, and supplies these data to operating signal generator 10. Filter selector 8 creates address signals which are necessary for the readout of the control program which executes filtering, based on tone color information A from setting part 7, and supplies these address signals to operating signal generator 10. Reverberation selector 9 creates address signals which are necessary for the readout of the control program which executes reverberation effecting, based on tone color information A from setting part 7, and supplies these address signals to operating signal generator 10. Operating signal generator 10 designates the operations of the above described computing part 5; the composition thereof will be explained hereinbelow. Next, the musical tone signals of the 32 channels, the filtering of each of which is conducted in computing part 5, are severally supplied to envelope generator 11. Envelope generator 11 generates an envelope waveform, multiplies this by an inputted musical tone signal, and outputs the result. The musical tone signals having envelope waveforms applied thereto in this manner are then supplied to accumulator 12, and accumulated. Reference numeral 13 indicates a panning circuit; it splits an inputted signal into a stereo left signal and right signal, and supplies these to computing part 5. Reverberation effects are applied to the left signal and the right signal in computing part 5, and these signals are converted to analog signals in digital/analog converter 14. Then, these analog signals are generated as musical tones as the output of the digital musical instrument through the medium of two differing speakers 15. (2) Composition of Operating Generator 10 Next, with reference to Fig. 2, the composition of operating generator 10 will be explained. The address signals generated by filter selector 8 are supplied to filtering parameters supplier 20 1 and readout control circuit 21 1 . Filtering parameters supplier 20 1 generates the parameters FLT-Q, FLT-fc, and address FLT-ad, which are used in filtering, from tone color information A and the address signals; it then modifies these parameters and address so as to be synchronous with key-on signal KON and supplies these to computing part 5 (see Fig. 1). Parameter FLT-Q indicates the resonance value of the filter, parameter FLT-fc indicates the cut-off frequency of the filter, and furthermore, address FLT-ad indicates the address signal necessary in the filtering operation. Reference numeral 22 1 indicates a filtering control signal memory. This memory 22 1 stores a plurality of control programs P1 1 , P1 2 , ..., which execute filtering. Control programs P1 1 , P1 2 , ..., conduct the time sharing control of the selection of various selectors and the readout and writing of various registers in computing part 5. Readout control circuit 21 1 reads, in order, control programs corresponding to address signals out of filter selector 8. The address signals generated by reverberation selector 9 are supplied to reverberating parameters supplier 20 2 and readout control circuit 21 2 . The reverberating parameters supplier 20 2 generates the reverberation parameters REV-COEF and REV-VOL, as well as the address REV-ad, from the address signals, characteristics data, and tone color information A, and supplies these parameters and address to computing part 5. Parameter REV-COEF expresses a reverberating operation coefficient, while parameter REV-VOL expresses the size of the reverberating output. Address REV-ad indicates an address signal necessary in the reverberating operation. Reference numeral 22 2 indicates a reverberating control signal memory. This memory 22 2 stores a plurality of control programs P2 1 , P2 2 , ..., which execute reverberation. The control programs P2 1 , P2 2 , ..., conduct the time shared control of the selection of the various selectors and the readout and writing of various registers in computing part 5. Readout control circuit 21 2 reads out, in order, control programs corresponding to address signals supplied by reverberation selector 9. Accordingly, computing part 5 operates based on the control programs read out by means of the above readout control circuits 21 1 and 21 2 . (3) Composition of Computing Part 5 Next, with reference to Fig. 3, the composition of computing part 5 will be explained. Computing part 5 executes filtering with respect to musical tone signals which are supplied to input terminal FILT-IN, and applies reverberation effects with respect to musical tone signals which are supplied to input terminal REV-IN. Computing part 5 is comprising selectors 51-54, filtering register 55, reverberating register 56, full adder 57, and multiplier 58. As stated above, the selecting control of selectors 51-54 and the readout/write control of filtering register 55 and reverberating register 56 is conducted by means of operating signal generator 10. The addresses used at the time of readout and writing in filtering register 55 and reverberating register 56 are designated by means of address FLT-ad supplied from reverberating parameter supplier 20 1 , and by address REV-ad supplied from reverberating parameters supplier 20 2 . References D 1 -D 9 indicate delay elements which delay input of signals for a period corresponding to 1 sampling clock and then output these signals; reference 3D indicates a delay element having a delay period corresponding to 3 sampling clocks. What is meant by "1 sampling clock" here is a period corresponding to 1/256 of the sampling period T of the digital musical instrument (this will be explained in detail hereinbelow). The musical tone signal supplied to input terminal FILT-IN is supplied to input terminal B of selector 52. The output of selector 52 is inputted to input terminal A of full adder 57 through the medium of delay element D 1 . The output of full adder 57 is supplied to envelope generator 11 (see Fig. 1) from output terminal FILT-OUT thorough the medium of delay element D 2 , and is supplied to digital/analog converter 14 (see Fig. 1) through the medium of output terminal REV-OUT. Furthermore, the output of full adder 57 is supplied to the input terminal A of selector 51, is supplied to the input terminal C of selector 52, is supplied to the input terminal D of selector 52 through the medium of delay element D 3 , is supplied to input terminal B of selector 53, is supplied to the data input terminal of filtering register 55 through the medium of delay element D 4 and is supplied to the data input terminal of reverberating register 56 through the medium of delay element D 5 . The above-described parameters FLT-Q, FLT-fc, REV-COEF, and REV-VOL are inputted into the input terminals A, B, C, and D, respectively, of selector 54. The output of selector 54 is supplied to multiplier 58 through the medium of delay element D 6 as a multiplication coefficient. The output of selector 53 is inputted into multiplier 58, and the output of selector 54, that is to say, the above-described multiplication coefficient, is multiplied thereby. The output of multiplier 58 is delayed by 3 sampling clocks in delay element 3D, and is then supplied to input terminal B of selector 51, and is supplied to input terminal C of the same selector after being amplified by 6 dB in amplifier OP. The output of selector 51 is supplied to one input terminal of exclusive-OR gate 59. Furthermore, an adder-subtractor control signal SUB having a value of 0 or 1 is supplied to the other input terminal of exclusive-OR gate 59 from operating signal generator 10. This adder-subtractor control signal SUB includes the control signals outputted from the above described readout control circuits 21 1 and 21 2 . Exclusive-OR gate 59 outputs the exclusive-or value of the output of selector 51 and adder-subtractor control signal SUB. The output of this exclusive-OR gate 59 is supplied to input terminal B of full adder 57 through the medium of delay element D 6 . A 1-bit signal within adder-subtractor control signal SUB is inputted into full adder 57 though the medium of delay element D 7 as a carry signal (carrying-over signal). By means of this, full adder 57 adds the signals supplied to input terminal A and input terminal B and outputs this value when each bit of adder-subtractor control signal SUB has a value of 0. On the other hand, when each bit of adder-subtractor control signal SUB has a value of 1, the signal supplied to input terminal B is subtracted from the signal supplied to input terminal A, and the result is outputted. The above-described left signal and right signal are supplied to input terminal A of selector 53 through the medium of input terminal REV-IN. Next, the data read out of filtering register 55 are supplied to input terminal A of selector 52 and input terminal C of selector 53 through the medium of delay element D 8 . The data read out of reverberating register 56 are supplied to input terminal D of selector 53 through the medium of delay element D 9 . The addresses FLT-ad and REV-ad, which indicate addresses used at the time of readout/writing, are supplied to filtering register 55 and reverberating register 56 from filtering parameters supplier 20 1 and reverberating parameters supplier 20 2 , which are shown in Fig. 2. The computing part 5 having the above composition functions as a "digital filter" and a "reverberation effecting circuit" in a time-shared manner. That is to say, the computing part 5 executes filtering with respect to the musical tone signals of the 32 channels supplied by tone generator 4, and simultaneously, applies predetermined reverberation with respect to the output signals of panning circuit 13. (4) Composition of the Digital Filter Next, the composition of the "digital filter", which is formed in a time-shared manner in computing part 5, will be explained with reference to Fig. 4. In Fig. 4, references S 1 -S 4 indicate adders, and references M 1 -M 3 indicate multipliers having multiplication coefficients K 1 -K 3 . Furthermore, references R 1 and R 2 indicate delays, which have delay periods corresponding to the sampling period T of the digital musical instrument. These delays R 1 and R 2 are realized by means of addressing to filtering register 55 in computing part 5 (this will be explained in detail hereinbelow). First, the input signal x(t) (t indicates a number 0, 1, 2, ..., corresponding to each sampling period) of the digital filter is added to the multiplication result L 1 of multiplier M 3 in adder S 1 , and furthermore, the addition result L 2 thereof is added to the delay result of delay R 1 in adder S 2 . In addition, the addition result L 3 of adder S 2 is multiplied by coefficient K 1 in multiplier M 1 , and the multiplication result L 4 thereof is supplied to the subtraction input terminal (-) in adder S 3 . The addition result L 5 of adder S 3 is multiplied by coefficient K 2 in multiplier M 2 , and the multiplication result L 6 thereof is supplied to one input terminal of adder S 4 , and is supplied to the addition input terminal (+) of adder S 3 and to the input terminal of multiplier M 3 through the medium of delay R 1 . In addition, the addition result L 7 of adder S 4 is outputted as output signal X(t), to which filtering has been applied by means of the digital filter, and is returned to the other input terminal of adder S 4 and to the other input terminal of adder S 2 through the medium of delay R 2 . In the digital filter having this composition, if the addition result of adder S 3 is y(t), the delay results of delays R 1 and R 2 can be expressed as y(t-1) and X(t-1), and furthermore, it is possible to express the various output data in the following manner. (1) Multiplication result L 1 of multiplier M 3 = K 3 · y(t-1) (2) Addition result L 2 of adder S 1 = L 1 + X(t) (3) Addition result L 3 of adder S 2 = L 2 + X(t-1) (4) Multiplication result L 4 of multiplier M 1 = K 1 • L 3 (5) Addition result L 5 of adder S 3 = y(t) = y(t-1) - L 4 (6) Multiplication result L 6 of multiplier M 2 = K 2 · y(t) = K 2 • L 5 (7) Addition result L 7 of adder S 4 = X(t) = L 6 + X(t-1) (5) Composition of the Reverberation Effecting Circuit Next, the composition of the reverberation effecting circuit which is formed in a time-shared manner in computing part 5 will be explained with reference to Fig. 5. In the drawing, the reverberation effecting circuit is comprising generally initial reflecting tone generator 60 and reverberating tone generator 61. This initial reflecting tone generator 60 forms an initial reflecting tone which indicates the first half portion of the reverberation characteristics which are to be simulated. In contrast, reverberating tone generator 61 forms a final reverberating tone which indicates the second half portion of the reverberation characteristics, which continue after the initial reflecting tone, which are to be simulated. In Fig. 5, references KC 1 -KC 24 indicate multipliers which multiply inputted signals by coefficients C 1 -C 24 , respectively, and output these values. References T 1 -T 7 indicate adders which output addition results TC 1 -T 7 , respectively. Furthermore, references DM 1 -DM 3 indicate delays which delay inputted signals by a predetermined delay time before outputting these signals. Delays DM 1 -DM 3 are comprising a single type of shift register, respectively, and shift the written data in order in each sampling period T. Accordingly, in delay DM 1 , addition result TC 7 is written into address A 1 , and after a predetermined delay period has elapsed, this is read in addresses A 2 -A 10 , and thereby delay data DC 2 -DC 10 having a predetermined delay time with respect to addition result TC 7 can be generated. In the same way, in delays DM 2 and DM 3 , the addition results TC 5 and TC 6 are written into addresses A 1 and A 2 respectively, and after a predetermined delay period has elapsed, these are read in addresses A 12 -A 14 and addresses A 16 -A 18 , and thereby, it is possible to generate delay data DC 12 -DC 14 and delay data DC 16 -DC 18 , which have a predetermined delay period with respect to addition results TC 5 and TC 6 . A detailed description thereof will be given hereinbelow. The reverberation effecting circuit shown in Fig. 5 can be divided into the operating units 70-76 shown in Fig. 6. The operations of these operating units 70-76 are executed within a sampling period T, and thereby, it is possible to conduct reverberation effecting. The addition results TC 1 -TC 4 in operating units 72-76 are temporarily stored in reverberating register 56 (see Fig. 5); and addition results TC 5 -TC 7 are stored in the same register in order to generate delay data. Furthermore, in operating units 70-72, when the input consists of "X", this indicates that nothing is inputted; however, a multiplication coefficient "0" is supplied so that the output of the corresponding multiplier becomes "0". These operating units 70-76 can be further divided into either operating units A or operating units B, which will be described next. Fig. 7 is a block diagram showing the composition of an operating unit A; this corresponds to operating units 70-74 in Fig. 6. In the same manner, Fig. 8 is a block diagram showing the composition of an operating unit B; this corresponds to operating units 75 and 76 in Fig. 6. By operating these operating units A and B in order, the reverberating effecting circuit shown in Fig. 5 can be equivalently formed. Next, the composition of the operating unit A which corresponds to operating units 70-74 will be explained. As shown in Fig. 7, input data E 1 is multiplied by multiplication coefficient K 4 by means of multiplier M 4 and the multiplication result L 11 thereof is supplied to one input terminal of adder S 5 . Furthermore, input data E 2 is multiplied by coefficient K 5 in multiplier M 5 and the multiplication result L 12 thereof is supplied to the other input terminal of adder S 5 . Furthermore, in adder S 5 , multiplication results L 11 and L 12 are added, and the addition result L 13 thereof is supplied to one input terminal of adder S 6 . Input data E 3 is multiplied by coefficient K 6 in multiplier M 6 , and the multiplication result L 14 is supplied to the other input terminal of adder S 6 . In adder S 6 , addition result L 13 and multiplication result L 14 are added, and the addition result L 15 thereof is supplied to one input terminal of adder S 7 . Input data E 4 are multiplied by coefficient K 7 in multiplier M 7 , and the multiplication result L 16 thereof is supplied to the other input terminal of adder S 7 . In addition, in adder S 7 , addition result L 15 and multiplication result L 16 are added, and the addition result L 17 thereof is outputted as output data F 1 . That is to say, input data E 1 -E 4 are multiplied by coefficients K 4 -K 7 , respectively, in multipliers M 4 -M 7 , and the sum of the multiplication results thereof is outputted as output data F 1 . The various data of the operating unit A shown in Fig. 7 correspond to differing data in the operating units 70-74 shown in Fig. 6. For example, the various data in operating unit A correspond in the following manner in operating unit 70. That is to say, input data E 1 correspond to the left signal, input data E 2 and E 3 correspond to addition results TC 1 and TC 3 , and furthermore, input data E 4 correspond to "X" (as explained above, nothing is inputted). Addition results TC 1 and TC 3 are temporarily stored in reverberating register 56, so that readout is conducted at the necessary timing. In addition, output data F 1 correspond to the left output, which is outputted to the digital/analog converter 14 as the left signal, to which reverberation has been applied. In the same manner, the various data in operational unit A correspond in the following manner in operational unit 71. That is to say, input data E 1 correspond to the right signal, input data E 2 and E 3 correspond to the addition results TC 2 and TC 4 , and furthermore, input data E 4 correspond to "X". In addition, output data F 1 correspond to the right output, and are supplied to the digital/analog converter (see Fig. 1). Furthermore, the various data in operating unit A correspond in the following manner in operating units 72-74. That is to say, the input data E 1 in operating unit A correspond to the left signal and to the delay data DC 2 and DC 3 , respectively, in operating units 72-74, input data E 2 correspond to the right signal and to delay data DC 4 and DC 5 , respectively, input data E 3 correspond to "X", and to delay data DC 6 and DC 7 , respectively, and furthermore, input data E 4 correspond to "X", and to delay data DC 8 and DC 9 , respectively. Delay data DC 2 -DC 9 are read out and supplied by means of the designation of predetermined addresses from reverberating register 56 (see Fig. 3). Furthermore, the output data F 1 in operating unit A correspond to addition results TC 7 , TC 1 , and TC 2 , respectively, in operating units 72-74, and these are written into predetermined addresses in reverberating register 56. Next, the composition of operating unit B, which corresponds to the operating units 75 and 76, will be explained. As shown in Fig. 8, input data E 5 is multiplied by coefficient K 8 in multiplier M 8 , and the multiplication result L 18 thereof is supplied to one input terminal of adder S 8 . Furthermore, input data E 6 are multiplied by coefficient K 9 in multiplier M 9 , and the result thereof is supplied to the other input terminal of adder S 8 . Then, in adder S 8 , the multiplication results L 18 and L 19 are added, and the addition result L 20 thereof is outputted as output data F 2 . Input data E 7 and E 8 are multiplied by coefficients K 10 and K 11 in multipliers M 10 and M 11 , respectively, and furthermore, multiplication results L 21 and L 22 are added in adder S 9 , and the addition result L 23 thereof is outputted as output data F 3 . The input data E 5 -E 8 in operating unit B correspond to delay data DC 10 , DC 14 , DC 10 , and DC 18 , respectively, in operating unit 75, which is shown in Fig. 6. In operating unit 76, these input data correspond to delay data DC 12 , DC 16 , DC 13 , and DC 17 , respectively. These delay data are read out of predetermined addresses in reverberating register 56. Furthermore, the output data F 2 and F 3 in operating unit B correspond to addition results TC 5 and TC 6 , respectively, in operating unit 75. Furthermore, in operating unit 76, these output data correspond to addition results TC 3 and TC 4 , respectively, and these addition results TC 3 - TC 6 are written into predetermined registers in reverberating register 56. Next, operations at the time of readout/writing of reverberating register 56, and the generating principle of the various delay data DC 2 -DC 10 , DC 12 -DC 14 , and DC 16 -DC 18 by means of delays DM 1 , DM 2 , and DM 3 , will be explained. The addition result TC 7 shown in Fig. 5 is written into address A 1 of delay DM 1 . This indicates that the contents of the address REV-ad which was designated in reverberating register 56 in Fig. 3, has a value of "A 1 ". That is to say, the addition result TC 7 of operating unit 72 in Fig. 6 is written into address A 1 in reverberating register 56. In the same way, the addition results TC 5 and TC 6 of operating unit 75 are written into addresses A 11 and A 15 in reverberating register 56. Next, the addition result TC 7 which is written in address A 1 is read into addresses A 2 -A 10 in operating units 73-75 as delay data DC 2 -DC 10 . At this time, the relationship between address A 1 and addresses A 2 -A 10 can be expressed in the manner shown below. A 2 = A 1 + d 2 , A 3 = A 1 + d 3 , ..., A 10 = A 1 + d 10 . Reverberating register 56 is a shift register which shifts the data stored therein in the direction of increase of the addresses during each sampling period T. That is to say, the addition result TC 7 written in address A 1 is moved to address (A 1 +1) after one sampling period. Accordingly, the delay data DC 2 which were read out of address A 2 (= A 1 + d 2 ) are data which delay addition result TC 7 by a period of time equivalent to d 2 × (sampling period T). Furthermore, delay data DC 3 -DC 10 are data which delay the addition results TC 7 by a period equivalent to (d 3 , d 4 , ..., d 10 ) × (sampling period T), respectively. The delaying principle of delays DM 2 and DM 3 is identical to that of DM 1 . Reverberating register 56 may be a pseudo-shift register, formed by means of the addressing of normal RAM. In such a case, a counter is present which reduces the final address value of reverberating register 56 by "1" each sampling period, and the result of this count is added to the addresses A 1 -A 10 . By means of this, even if it appears that writing/readout is being conducted in the same address, the actual address is moved in each sampling period. On the other hand, the addition results TC 1 , TC 2 , TC 3 , and TC 4 of operating units 73, 74, and 76 (see Fig. 6) are written into reverberating register 56 for the purpose of temporary storage. Here, the address given to address REV-ad is, respectively, A 19 , A 20 , A 21 , and A 22 . After the addition results TC 1 -TC 4 have been written into addresses A 19 -A 22 , respectively, it is possible to read out the same addition results without delay if readout is conducted from the same addresses A 19 -A 22 in the same sampling period. However, this occurs in the case in which writing and readout is conducted in that order in the same sampling period. In the case in which readout is first conducted and then writing is conducted, the data which are read out are those data which are written in the immediately previous sampling period; however, this does not present an obstacle in the case of reverberation. Filtering register 55 comprises a shift register or a pseudo-shift register formed by means of RAM, and the operations at the time of readout/writing are identical to the operations of reverberating register 56. (6) Outline of Operations In a digital musical instrument having the composition described above, when a key on the keyboard is depressed by a performer, keyboard circuit 1 generates a key-on KON and a key code KC corresponding to the depressed key, and supplies this to tone generation assignment circuit 2. Next, tone generation assignment circuit 2 searches, in order, for empty channels in tone generator 4 which are capable of tone generation assignment, that is to say, channels which are in a tone generation stand-by status. At this time, tone generation assignment circuit 2 supplies key-on KON and key code KC with respect to an empty channel, when such a channel has been found, so that a musical tone signal will be generated. On the other hand, in the case in which no empty channel is present, the channel in which tone generation is most advanced is selected, a truncation process is conducted which forces this channel to become empty, and after a directive has been issued to this channel so that the present tone generation is caused to decay (damping process), key-on KON and key code KC are supplied. Here, key-on KON is provided to envelope generator 11. Furthermore, tone color parameters supplier 3 creates various tone color parameters corresponding to the tone colors set by means of tone color information A, and supplies these parameters to tone generator 4 and envelope generator 11. Then, the channel in tone generator 4 which was assigned by means of tone generation circuit 2 generates a musical tone signal having a tone color corresponding to the tone color parameters which were supplied and having a pitch corresponding to key code KC, from the initialization of key-on KON. In this manner, differing musical signals corresponding to 32 channels are generated in tone generator 4. Operating panel 6 supplies the setting information of the operating members thereof to setting part 7. Setting part 7 generates tone color information A showing a tone color number from this setting information, and supplies this to tone color parameter supplier 7, filter selector 8, reverberation selector 9, and operating signal generator 10. Furthermore, setting part 7 creates performance data based on the setting information from operating panel 6, and supplies this performance data to operating signal generator 10. Then, filter selector 8 and reverberation selector 9 create address signals of control programs which are to be read out, based on tone color information A. That is to say, filter selector 8 selects the control program which is to be read out from among the plurality of control programs for filters P 1 , P 2 , ..., by means of tone color information A, and furthermore, in accordance with the control sampling clock, the address of the control program is updated by a value of "1" each time. Here, if the size of one control program is 256 steps, the control sampling clock is supplied at periods corresponding to 1/256 of sampling period T. That is to say, the cycle of one control program is completed in one sampling period. In the same manner, in reverberation selector 9, the control program which is to be read out is selected from among the plurality of control programs for reverberation P2 1 , P2 2 , ..., by means of tone color information A, and in accordance with the control sampling clock, the control program address is updated by a value of "1". In Fig. 2, filtering parameters supplier 20 1 supplies filtering parameters FLT-Q and FLT-fc in order based on tone color information A and in correspondence with address signals. These filtering parameters FLT-Q and FLT-fc are synchronized with the selected control program for filtering and supplied, and are supplied so as to correspond to the coefficients K 1 -K 3 (see Fig. 4) for each channel. In the same manner, reverberating parameters supplier 20 2 supplies reverberating parameters REV-COEF and REV-VOL in order based on tone color information A and performance data, in correspondence with address signals. These reverberating parameters REV-COEF and REV-VOL are synchronized with the selected control program for reverberation and are supplied, and are supplied in such a manner as to correspond to coefficients K 4 -K 11 (see Fig. 7) for each channel. Filtering based on the corresponding filtering parameters described above is conducted in computing part 5 with respect to the musical signals of the 32 channels which were generated by tone generator 4, and subsequently, these are multiplied by an envelope waveform in envelope generator 11. The signals which have been multiplied in this manner are first accumulated in accumulator 12, and then, in panning circuit 13, these signals are separated into a left signal and a right signal for the purpose of producing stereo. Thereupon, reverberation is applied to this left signal and right signal in computing part 5, and then these signals are converted to analog signals in digital/analog converter 14, and tone generation is conducted through the medium of speakers 15. (7) Operation of Computing Part 5 In computing part 5, as explained above, filtering is conducted with respect to the musical tone signals of each tone generation channel generated by means of tone generator 4, and reverberation effecting is conducted with respect to the left and right signals divided by means of the panning circuit 13; these are conducted within one sampling period T and in a time shared manner and in parallel. Fig. 9 shows the execution timing of the filtering and the reverberation effecting executed in each tone generation channel within a sampling period T. As shown in the diagram, sampling period T is divided into 32 equal blocks. Numbers "0"-"31" corresponding to each tone generation channel are assigned to these blocks. The filtering which is executed with respect to each tone generation channel 0-31ch is conducted so as to be delayed by 1 block in a 3-block period. That is to say, the filtering conducted with respect to the musical tone signal in channel 0ch is conducted during the 0-2 block period, and the filtering conducted with respect to the musical tone signal in a channel n ch (n represents an integer within a range of 0-31) is conducted so as to be delayed by 1 block with respect to the processing of the channel (n-1) ch. The processing of each operating unit 70-76 which realizes reverberation effecting is conducted so as to be delayed by 1 block within a period of 3 blocks. That is to say, in reverberation effecting, first, the processing of the operating unit 70 using operating unit A is conducted in the 0-2 block period, and next, the processing of the operating unit 71 is conducted with a 1 block delay with respect to the processing of operating unit 70. Hereinafter, in the same manner, the processing of the operating unit 74 using operating unit A is conducted with a 1-block delay with respect to the operating unit 73. Next, the processing of the operating unit 75 using operating unit B is conducted with a 1-block delay with respect to the processing of the operating unit 74, and the processing of the operating unit 76 is conducted with a 1-block delay with respect to the operating unit 75. The actual processing number of the operating units conducting reverberation effecting in a sampling period T is 32. However, in the example shown in the diagram, for the purposes of simplification of the explanation, the actual execution was limited to the 7 operating units 70-76 which were described above. In conclusion, in a sampling period T, a control program comprising 32 consecutive blocks is executed. This control program is executed in such a manner that the filtering with respect to the musical tone signals of the channels 0-31 ch and the operations of operating units 70-76 are delayed by 1 block within a 3-block period, and are thus overlaid. (8) Operation of the Digital Filter Next, the operation of the digital filter which is formed in computing part 5 will be explained. In the explanation of this operation, the case in which filtering is executed with respect to the musical tone signal of the 0ch channel will be used as an example. Fig. 10 shows a control program, which executes filtering with respect to the musical tone signal of the 0ch shown in Fig. 9, as a timetable. Furthermore, to explain in greater detail, the selection of selectors 51-54 and the control of filtering register 55 in computing part 5 is expressed as a timetable. The adding timing of full adder 57 and the multiplication timing of multiplier 58 have no relationship to the operation of the control program; however, they are shown in the timetable in order to facilitate explanation. As shown in Fig. 10, this control program comprises 3 blocks "0"-"2". Each block comprises 8 steps. Each step is executed in a 1-block period. As a result, in a sampling period 1T, a control program having 256 (32 blocks X 8 sampling clocks) steps is executed. Accordingly, in a sampling period 1T, by supplying 256 sampling clocks, the control program is executed. In a sampling clock, the numbers "0"-"7" are applied in order to the blocks. Hereinbelow, in order to facilitate explanation, in the case in which, for example, the fifth sampling clock of the first block is indicated, this will be referred to as sampling clock 1-5. Computing part 5 executes each operation [1]-[7] described below in accordance with the timetable shown in Fig. 10, and finds the operational results L 1 -L 7 of the digital filter (see Fig. 4). [1] Calculation of Multiplication Result L 1 First, as shown in Fig. 10, in sampling clock 0-3, address FLT-ad is supplied from filters parameter supplier 20 1 (see Fig. 2) as a readout address, and y(t-1), which is the delay data of delay R 1 (see Fig. 4) is read out of filtering register 55. This data y(t-1) was written as delay R 1 one sampling period prior to the present time t. That is to say, delays R 1 and R 2 are realized using filtering register 55, and by means of reading out the written data after period 1T, the data are delayed by 1 sampling period T. The data y(t-1) are delayed by one sampling clock by means of delay element D 8 (see Fig. 3), so that these data are supplied to selector 53 during sampling clock 0-4. Next, in sampling clock 0-4 (see Fig. 9), selector 53 selects input terminal C. By means of this, data y(t-1) are supplied to multiplier 58. In sampling clock 0-3, selector 54 selects input terminal A. The data supplied to this input terminal A correspond to coefficient K 3 in Fig. 4, and in sampling clock 0-3, these data are parameter FLT-Q, which is supplied from filtering parameters supplier 20 1 . These data are supplied to multiplier 58 during sampling clock 0-4 through the medium of delay element D 6 . Accordingly, during sampling clock 0-4, data y(t-1) and coefficient K 3 are supplied to multiplier 58 so that the multiplication result L 1 shown in equation 1 is calculated. Multiplication result L 1 is supplied to input terminal C of selector 51 through the medium of delay element 3D and amplifiers 0P, in order. That is to say, multiplication result L 1 is amplified by +6 dB during sampling clock 0-7 and is supplied to input terminal C of selector 51. [2] Calculation of Addition Result L 2 In sampling clock 0-7, selector 51 selects input terminal C, and selector 52 selects input terminal B. By means of the selection of selector 51, multiplication result L 1 is supplied to input terminal B of full adder 57 through the medium of exclusive-OR gate 59 and delay element D 6 . Furthermore, the signal supplied to input terminal FILT-IN is digital filter input signal x(t), and by means of the selection of selector 52, this is supplied to input terminal A of full adder 57 through the medium of delay element D 1 . Here, multiplication result L 1 and input signal x(t) are supplied through the media of delay elements D 6 and D 1 , respectively, so that they are supplied during sampling clock 1-0 to full adder 57. Accordingly, the addition result L 2 shown in equation 2 is calculated. [3] Calculation of Addition Result L 3 Next, in sampling clock 1-1, selector 51 selects input terminal A. At this time, the addition result L 2 calculated by means of full adder 57 in sampling clock 1-0 is delayed by 1 sampling clock by means of delay element D 2 and is supplied to input terminal A of selector 51. By means of this, addition result L 2 is supplied to input terminal B of full adder 57 through the media of exclusive-OR gate 59 and delay element D 6 . In sampling clock 1-0, the data X(t-1) of delay R 2 which were written in the immediately previous sampling period are read out of filtering register 55. These data are delayed by 1 sampling clock by means of delay element D 8 , so that they are supplied in sampling clock 1-1 to input terminal A of selector 52. In sampling clock 1-1, selector 52 selects input terminal A, so that data X(t-1) are supplied to input terminal A of full adder 57 through the medium of delay element D 1 . That is to say, addition result L 2 and data X(t-1) are supplied through the medium of delay elements D 6 and D 1 , respectively, so that they are supplied in sampling clock 1-2 to full adder 57. By means of this, the addition result L 3 shown in Equation 3 is calculated. [4] Calculation of Multiplication Result L 4 Next, in sampling clock 1-3, selector 53 selects input terminal B. At this time, the addition result L 3 calculated by means of full adder 57 in sampling clock 1-2 is delayed by 1 sampling clock by means of delay element D 2 and is supplied to input terminal B of selector 53, so that this addition result is supplied to multiplier 58. In sampling clock 1-2, selector 54 selects input terminal B. The data supplied to this input terminal B correspond to coefficient K 1 in Fig. 4, and are parameter FLT-fc, which is supplied from filtering parameters supplier 20 1 in sampling clock 1-2. These data are supplied in sampling clock 1-3 to multiplier 58 through the medium of delay element D 6 . Accordingly, in sampling clock 1-3, addition result L 3 and coefficient K 1 are supplied to multiplier 58, so that the multiplication result L 4 shown in Equation 2 is calculated. This multiplication result L 4 is outputted through the medium of delay element 3D, so that it is supplied to selector 51 in sampling clock 1-6. [5] Calculation of Addition Result L 5 Next, in sampling clock 1-6, selector 51 selects input terminal B. As a result, multiplication result L 4 is supplied to input terminal B of full adder 57 through the medium of exclusive-OR gate 59 and delay element D 6 . At this time, each bit of adder-subtractor control signal SUB acquires a value of "1", so that the subtraction processing of input terminal (A-B) is conducted in full adder 57. Furthermore, multiplication result L 4 is supplied through the medium of delay element D 6 , so that it is delayed by 1 sampling clock from sampling clock 1-6 and is supplied to full adder 57 in sampling clock 1-7. In sampling clock 1-5, the data y(t-1) of delay R 1 are again read out from filtering register 55. In sampling clock 1-6, selector 52 selects input terminal A. The data y(t-1) are supplied through the medium of delay elements D 8 and D 1 in order, so that these data are delayed by 2 sampling clocks from sampling clock 1-5, that is to say, they are supplied to input terminal B of full adder 57 in sampling clock 1-7. Accordingly, in sampling clock 1-7, multiplication result L 4 and data y(t-1) are supplied to full adder 57, so that the addition result L 5 shown in equation 5 is calculated. This addition result L 5 is outputted through the medium of delay element D 2 , so that it is supplied to selector 53 in sampling clock 2-0. Furthermore, addition result L 5 is supplied through the medium of delay element D 4 so that it is supplied to the data input terminal of filtering register 55 in sampling clock 2-1. At this time, addition result L 5 is written into filtering register 55 as the data y(t) of delay R 1 at the present time T. Here, the data which were written as y(t) are read out in sampling clocks 0-3 and 1-5 as data y(t-1), which were delayed by 1 sampling period. Filtering register 55 operates as a shift register, so that the writing address and the readout address are identical. That is to say, in sampling clocks 0-3, 1-5 and 2-1, the address FLT-ad supplied by filtering parameters supplier 20 1 has the same contents. As explained above, this is caused by the fact that the order of writing and readout is reversed. [6] Calculation of Multiplication Result L 6 Next, in sampling clock 2-0, selector 3 selects input terminal B. At this time, the addition result L 5 is supplied to input terminal B of the same selector, so that the addition result is supplied to multiplier 58. In sampling clock 1-7, selector 54 selects input terminal B. By means of this, the parameter FLT-fc which was supplied from filtering parameters supplier 20 1 to the input terminal, is supplied to multiplier 58 through the medium of delay element D 6 in sampling clock 2-0. This parameter FLT-fc corresponds to the coefficient K 2 shown in Fig. 4. Accordingly, in sampling clock 2-0, addition result L 5 and coefficient K 2 are supplied to multiplier 58, so that the multiplication result L 6 shown in Equation 6 is calculated. This multiplication result L 6 is supplied through the medium of delay element 3D, so that it is supplied to selector 51 in sampling clock 2-3. [7] Calculation of Addition Result L 7 Next, in sampling clock 2-3, selector 51 selects input terminal B and selector 52 selects input terminal A. At this time, the multiplication result L 6 is supplied to selector 51, so that this multiplication result is supplied to input terminal B of full adder 57 through the media of exclusive-OR gate 59 and delay element D 6 . That is to say, multiplication result L 6 is supplied to input terminal B of full adder 57 in sampling clock 2-4. In sampling clock 2-2, data X(t-1) of register R 2 are read out again from filtering register 55. These data are supplied through the medium of delay element D 8 , so that they are supplied to input terminal A of selector 52 in sampling clock 2-3. At this time, selector 52 selects the input terminal stated above. As a result, data X(t-1) are supplied through the medium of delay element D 1 , so that they are supplied to input terminal A of full adder 57 in sampling clock 2-4. Accordingly, in sampling clock 2-4, multiplication result L 6 and data X(t-1) are supplied to full adder 57, so that the addition result L 7 shown in equation 7 is calculated. This addition result L 7 is supplied through the medium of delay element D 2 , so that this is outputted from output terminal FILT-OUT in sampling clock 2-5 through the medium of delay element D 4 . As a result, in sampling clock 2-6, this is supplied to the data input terminal of filtering register 55. At this time, addition result L 7 is written into filtering register 55 as data X(t) of a new delay R 2 . Here, the data written as X(t) are read out in sampling clock 1-0 and sampling clock 2-2 with a 1 sampling period delay as data x(t-1). However, in this case as well, the writing address and the readout address are identical for the same reasons as in the case of y(t) described above; that is to say, because the order of writing and readout is reversed. That is to say, in sampling clocks 1-0, 2-2, and 2-6, the address FLT-ad supplied from filtering parameters supplier 20 1 has identical contents. In this way, by means of the control program shown in Fig. 9, filtering is conducted with respect to the musical tone signal in channel 0ch in the period from sampling clock 0-0 to sampling clock 2-7. Next, the filtering with respect to the musical tone signal of tone generation channel 1ch is conducted in such a manner as to be delayed by 1 block with respect to the processing of the tone generation channel 0ch described above and as shown in Fig. 9. Hereinafter, in the same manner, the filtering with respect to the musical tone signal of a channel n ch is conducted in such a manner as to be delayed by 1 block with respect to channel (n-1) ch. As a result, for example, in the period of the block number 2 shown in Fig. 9, the filtering of the musical signals of channels 0-2ch proceeds simultaneously and without hindrance. The filtering algorithm of the 32 channels is identical for each tone generation channel. However, differing filtering parameters are supplied from filtering parameters supplier 20 1 for each tone generation channel, so that individual filtering can be executed with respect to the musical tone signals of the 32 channels. (9) Operation of the Reverberation Effecting Circuit The reverberating effecting circuit is realized by means of the time shared operation of the operating units A shown in Fig. 7 or the operating units B shown in Fig. 8. First, the operation of operating unit A will be explained with reference to Fig. 10. Here, in order to simplify the explanation, operating unit A is explained with reference to the case in which operating units 73 and 74 are operated. Fig. 10 shows the timetable of a control program for executing reverberation effecting. To explain in greater detail, the selection of selectors 51-54 and the control of reverberating register 56 in computing part 5 is displayed in terms of a timetable. The operating units which execute the reverberation effecting circuit are comprising, as in the case of the filtering described above, 3 blocks "0"-"2". Each block comprises 8 steps (sampling clocks). Computing part 5 executes the operations [1]-[7] described hereinbelow, and obtains the various operational results L 11 -L 17 of operating unit A (see Fig. 7). [1] Calculation of Multiplication Result L 11 First, as shown in Fig. 10, in sampling clock 0-2, selector 53 selects input terminal D. At this time, input data E 1 , which were read out of reverberating register 56 in sampling clock 0-1, are supplied to input terminal D of selector 53 through the medium of delay element D 9 . As a result, these input data are supplied to multiplier 58. In sampling clock 0-1, selector 54 selects input terminal C. At this time, the parameter REV-COEF from reverberating parameters suppliers 20 2 is supplied to input terminal C as coefficient K 4 of operating unit A, and is supplied in sampling clock 0-2 to multiplier 58 through the medium of delay element D 6 (see Fig. 3). Accordingly, in sampling clock 0-2, coefficient K 4 and input data E 1 are supplied to multiplier 58, and a multiplication result L 11 , wherein L 11 = K 4 · E 1 , is calculated. This multiplication result L 11 is supplied through the medium of delaying element 3D, so that it is supplied to selector 51 in sampling clock 0-5. At this time, selector 51 selects input terminal B, and furthermore, multiplication result L 11 is supplied through the medium of delay element D 6 , so that this multiplication result is supplied to input terminal B of full adder 57 in sampling clock 0-6. In sampling clock 0-5, selector 52 does not select an input terminal, so that nothing is inputted into input terminal A of full adder 57 in sampling clock 0-6. Accordingly, in sampling clock 0-6, full adder 57 adds nothing to multiplication result L 11 , and output it. That is to say, multiplication result L 11 is outputted in an unchanged manner. In this case, in sampling clock 0-5 it is also acceptable for selector 52 to select "0". [2] Calculation of Multiplication Result L 12 In sampling clock 0-5, selector 53 selects input terminal D. In sampling clock 0-4, input data E 2 are read out of reverberating register 56. By means of this, these input data are supplied to multiplier 58 in sampling clock 0-5. Furthermore, in sampling clock 0-4, selector 54 selects input terminal C. At this time, the parameter REV-COEF which is supplied to input terminal C is coefficient K 5 of operating unit A shown in Fig. 7 (1). By means of this, coefficient K 5 is supplied to multiplier 58 in sampling clock 0-5. Accordingly, in sampling clock 0-5, coefficient K 5 and input data E 2 are supplied to multiplier 58, and a multiplication result L 12 , wherein L 12 = K 5 • E 2 , is calculated. This multiplication result L 12 is supplied through the medium of delay element 3D, so that this multiplication result is supplied to input terminal B of selector 51 in sampling clock 1-0. [3] Calculation of Addition Result L 13 In sampling clock 1-0, selector 51 selects input terminal B. At this time, multiplication result L 12 is supplied to input terminal B of this selector, and delay element D 6 is connected to the output of this selector. As a result, in sampling clock 1-1, multiplication result L 12 is supplied to input terminal B of full adder 57. In sampling clock 1-0, selector 52 selects input terminal D. At this time, multiplication result L 11 is supplied to the input terminal D of selector 52. This is because the multiplication result L 11 outputted from full adder 57 and sampling clock 0-6 is delayed by 2 sampling clocks through the medium of delay elements D 2 and D 3 . By means of this, multiplication result L 11 is supplied from selector 52 though the medium of delay element D 1 , and is supplied to input terminal A of full adder 57 in sampling clock 1-1. Accordingly, in sampling clock 1-1, multiplication results L 11 and L 12 are supplied to full adder 57, and addition result L 13 , wherein L 13 = L 11 + L 12 , is calculated. [4] Calculation of Multiplication Result L 14 In the same manner as in the case of the calculation of the multiplication results L 11 and L 12 described above, in sampling clock 0-7, selector 53 selects input terminal D, and input data E 3 are read out from reverberating register 56 in sampling clock 0-6. By means of this, input data E 3 are supplied to multiplier 58 in sampling clock 0-7. Furthermore, in sampling clock 0-6, selector 54 selects input terminal C. At this time, the parameter REV-COEF supplied to input terminal C is coefficient K 6 of operating unit A (see Fig. 7). By means of this, coefficient K 6 is supplied to multiplier 58 in sampling clock 0-7. Accordingly, in sampling clock 0-7, coefficient K 6 and the data of register E 3 are supplied to multiplier 58, and a multiplication result L 14 , wherein L 14 = K 6 • E 3 , is calculated. This multiplication result L 14 is supplied through the medium of delay element 3D, so that it is delayed by 3 sampling clocks, and is supplied to input terminal B of selector 51 in sampling clock 1-2. [5] Calculation of Addition Result L 15 In sampling clock 1-2, selector 51 selects input terminal B. At this time, multiplication result L 14 is supplied to input terminal B of this selector 51. Furthermore, delay element D 6 is connected to the output of this selector 51, so that multiplication result L 14 is supplied to the input terminal B of full adder 57 in sampling clock 1-3. In sampling clock 1-2, selector 52 selects input terminal C. At this time, addition result L 13 is supplied to input terminal C of the same selector 52. This is because the addition result L 13 which was outputted by full adder 57 in sampling clock 1-1 is delayed by 1 sampling clock through the medium of delay element D 2 . By means of this, addition result L 13 is supplied from selector 52 through the medium of delay element D 1 , and is supplied to the input terminal A of full adder 57 in sampling clock 1-3. Accordingly, in sampling clock 1-3, addition result L 13 and multiplication result L 14 are supplied to full adder 57, and an additional result L 15 , wherein L 15 = L 13 + L 14, is calculated. [6] Calculation of Multiplication Result L 16 In the same manner as in the case of the multiplication results L 11 , L 12 , and L 14 , in sampling clock 1-1, selector 53 selects input terminal D, and in sampling clock 1-0, input data E 4 are read out from reverberating register 56. By means of this, in sampling clock 1-1, input data E 4 are supplied to multiplier 58. Furthermore, in sampling clock 1-0, selector 54 selects input terminal C. At this time, the parameter REV-COEF which is supplied to input terminal C is coefficient K 7 of operating unit A (see Fig. 7). As a result, in sampling clock 1-1, coefficient K 7 is supplied to multiplier 58. Accordingly, in sampling clock 1-1, coefficient K 7 and input data E4 are supplied to multiplier 58, and a multiplication result L16, wherein L 16 = K 7 · E 4 , is calculated. This multiplication result L16 is supplied through the medium of delay element 3D, so that it is supplied to the input terminal B of selector 51 with a 3-sampling clock delay, in sampling clock 1-4. [7] Calculation of Addition Result L 17 In sampling clock 1-4, selector 51 selects input terminal B. At this time, multiplication result L 16 is supplied to input terminal B of selector 51. Furthermore, delay element D 6 is connected to the output of selector 51, so that the multiplication result is supplied to input terminal B of full adder 57 in sampling clock 1-5. In sampling clock 1-4, selector 52 selects input terminal C. At this time, addition result L 15 is supplied to input terminal C of selector 52. This is because addition result L 15 , which was outputted from full adder 57 in sampling clock 1-3, is delayed by 1 sampling clock through the medium of delay element D 2 . By means of this, the addition result is supplied from selector 52 through the medium of delay element D 1 , and is supplied to input terminal A of full adder 57 in sampling clock 1-5. Accordingly, in sampling clock 1-5, addition result L 15 and multiplication result L 16 are supplied to full adder 57, and an addition result L 17 , wherein L 17 = L 15 + L 16 , is calculated. This addition result L 17 is delayed by 2 sampling clocks through the medium of delay elements D 2 and D 5 , and is written into reverberating register 56 as output data F 1 . The operating unit A, which obtains each of these operation results L 11 - L 17 in this manner, corresponds to the operating units 70-74 which are shown in Fig. 6, and as shown in Fig. 9, these are operated in 3-block periods. For example, when the processing of an operating unit 73 using an operating unit A is conducted, at the readout timings of the input data E 1 -E 4 in operating unit A, the respectively corresponding delay data DC 2 , DC 4 , DC 6 , and DC 8 are read out from reverberating register 56. This is conducted by means of designating addresses A 2 , A 4 , A 6 , and A 8 as address REV-ad. Furthermore, the coefficients K 4 -K 7 of parameter REV-COEF are supplied as coefficients C 5 , C 7 , C 9 , and C 11 in operating unit 73, at each supply timing. Furthermore, the output data F 1 of operating unit A are temporarily stored in reverberating register 56 as addition result TC 1 of operating unit 73. In the same manner, when the processing of operating unit 74 which uses operating unit A is conducted, at the readout timings of input data E 1 -E 4 in operating unit A, the respectively corresponding delay data DC 3 , DC 5 , DC 7 , and DC 9 are read out from reverberating register 56. This is conducted by means of designating the addresses A 3 , A 5 , A 7 , and A 9 as address REV-ad. Furthermore, the coefficients K 4 -K 7 , which are parameter REV-COEF, are supplied at each supply timing as coefficients C 6 , C 8 , C 10 , and C 12 in operating unit 74. Then, the output data F 1 of operating unit A are temporarily stored in reverberating register 56 as addition result TC 2 of operating unit 74. Next, the operations at the time of the conducting of the processing of operating units 70-72 (see Fig. 6) by means of operating unit A will be explained. In this case, the differences with the above-described operating units 73 and 74 lie in the fact that input data E 1 in operating unit A comprise a left signal in operating unit 70 and 72, and comprise a right signal in operating unit 71. In the timetable shown in Fig. 10, in sampling clock 0-2, selector 53 selects input terminal D. However, in accordance with the points of difference mentioned above, when the processing of operating units 70-72 is conducted, the selector 53 selects input terminal A. At this time, panning circuit 13 (see Fig. 1) generates a left signal when operating unit 70 or 72 is executed, and generates a right signal when operating unit 71 is executed, and supplies these through the medium of input terminal REV-IN. When the processing of operating unit 72 is conducted, the input data E 2 in operating unit A comprise a right signal, and in sampling clock 0-5, selector 53 selects input terminal A. In operating units 70-72, the input data E 4 and the multiplication coefficient which is multiplied by the input data E 4 in operating unit A have values of "X" and "0", respectively. In the case in which a representation is to be made of the processing of operating units 70-74 by means of operating unit A, in sampling clock 1-1, a selection signal is not supplied to selector 53. In this case, the selection of an input terminal in selector 53 is indeterminate. However, in the present preferred embodiment, in sampling clock 1-0, the value of the coefficient K 7 which is supplied as parameter REV-COEF to input terminal C of selector 54 is set to a value of "0" in accordance with the multiplication coefficient in operating unit 70. As a result, because coefficient K 7 is supplied through the medium of delay element D 6 , this coefficient is supplied to multiplier 58 in sampling clock 1-1. By means of this, the multiplication result of the multiplier 58 becomes "0", and this is the multiplication result L 15 in operating unit A. In the same manner, the input data E 3 of the operating unit A corresponding to operating unit 72 and the multiplication coefficient multiplied by this input data E 3 have values of "X" and "0", respectively. In this case, in sampling clock 0-7, a selection signal is not supplied to selector 53, and in sampling clock 0-6, the coefficient K 6 which is supplied as parameter REV-COEF to input terminal C of selector 54 has a value of "0", in accordance with the multiplication coefficient in operating unit 70. As a result, this coefficient is supplied through the medium of delay element D 6 , so that the coefficient is supplied to multiplier 58 in sampling clock 0-7, and the multiplication result of multiplier 58 becomes "0". This is the multiplication result L 14 in operating unit A. In this manner, in the present preferred embodiment, the coefficients K 6 and K 7 which are supplied as parameter REV-COEF, are given values of "0" at supply timings thereof, and thereby, the processing of the input data "X" and the multiplication coefficient "0" in operating units 70-72 is accomplished. Furthermore, the multiplication coefficients C 23 and C 24 in operating units 70 and 71 are supplied to the multipliers TC 23 and TC 24 , which determine the size of the left and right outputs, as can be seen from the reverberation effecting circuit shown in Fig. 5. That is to say, in the processing of operating units 70 and 71 by means of operating unit A, multiplication coefficients C 23 and C 24 are supplied not as parameter REV-COEF, but rather as coefficient K 6 of parameter REV-VOL. Accordingly, in representing the processing of operating unit 70 by means of operating unit A, the situation is different from that shown in Figure 11 in that selector 54 selects input terminal D in sampling clock 0-6, and in sampling clock 0-5, multiplication coefficient C 23 is supplied to input terminal D of selector 54 as coefficient K 6 of parameter REV-VOL. In the same way, when the processing of operating unit 71 is conducted by means of operating unit A, selector 54 selects input terminal D in sampling clock 0-6, and multiplication coefficient C 24 is supplied to input terminal D of selector 54 as coefficient K 6 of parameter REV-VOL in sampling clock 0-5. In this manner, when processing is conducted using operating unit A, as a result of the differences of operating units 70 - 74, the selection of the selectors 51 - 54 and the writing/readout control of reverberating register 56 are conducted fundamentally in accordance with the timetable shown in Fig. 11, and the operations of operating unit A are conducted repeatedly in correspondence with the individual operating units 70 - 74. Furthermore, computing part 5 determines operation results L 18 - L 23 of operating unit B (see Fig. 8) in accordance with the timetable shown in Fig. 12. The points of difference between this timetable and the timetables shown in Fig. 10 are given hereinbelow. a) In sampling clock 1-3, addition result L 20 is written into reverberating register 56 as output data F 2 . b) In sampling clock 1-2, multiplication result L 21 has nothing added thereto, so that selector 52 selects nothing. Other than this, computing part 5 proceeds in accordance with the timetable in Fig. 12, in a manner identical to that of operating unit A, and the operations of operating unit B are repeatedly conducted in correspondence with the individual operating units 75 and 76. As shown in Fig. 9, computing part 5 executes the operations of operating units 70-76 in order in correspondence with operating units A and B. That is to say, computing part 5 executes operating unit 70 in the period of blocks 0-2, executes operating unit 71 with a 1-block (8 clock) delay, and in the same manner, executes all operating units up through operating unit 76. Accordingly, computing part 5 executes operating units 70-76 in 1 sampling period T, so that reverberating effecting is conducted with respect to the left and right signals of panning circuit 13 (see Fig. 1). As explained above, computing part 5 conducts filtering, and, by means of operating units 70-76, reverberation effecting with respect to musical tone signals in channels 0-31ch in a time-shared manner and in 1 sampling period T. At this time, as is clear from Figs. 10-12, there is no overlap among the selection control of selectors 51-54, the read out/writing control of filtering register 55, and the read out/writing control of reverberating register 56, in computing part 5. For example, in the second block of the sampling period shown in Fig. 9, the filtering of the musical tone signals of channels 0-2ch and the processing of operating units 70-72 proceed simultaneously. However, the operating timing of full adder 57 and multiplier 58 does not overlap at the sampling clock level. This is achieved by providing delay elements between each selector 51-54, full adder 57, and multiplier 58 in computing part 5. Furthermore, the filtering is divided into channels, and the reverberation effecting is divided into operating units, as a unit of the operational algorithm, and these operational algorithms are executed in such a manner that they are delayed by a fixed period. As a result, it is possible to process a plurality of inputted data in a time-shared manner so that there is no mutual hindrance, and to output these data. Furthermore, filtering and reverberation effecting are conducted in the same computing part 5, so that the circuit composition is simplified. (Second Preferred Embodiment) In the above-described preferred embodiment, after filtering was applied to the musical tone signals, reverberation was applied. However, in the composition of the present preferred embodiment, if the content of the control program is rewritten, it is possible to apply effects such as chorus, flanger, distortion, exciter, or the like. Furthermore, these effects may be applied not merely to the same musical tone signal, but a plurality of different effects may be applied to a plurality of differing musical tone signals. In addition, it is possible to apply differing effects in a parallel manner to a single musical tone signal.

Claims: A digital signal processor which repeatedly executes waveform processing based on operation clocks during each sampling period of musical tones, the digital signal processor comprising: musical-tone-signal supplying means for supplying a group of musical tone signals including one or more musical tone signals; parameter generation means (20-1, 20-2) for generating filter parameters, controlling a characteristic of a digital filter, and effecter parameters controlling a characteristic of an effecter; control means (21-1, 21-2) for generating a first control signal controlling a first operating algorithm of the digital filter as well as a second control signal controlling a second operating algorithm of the effecter; and computing means (5), which provides operation elements such as multipliers, adders and subtracters, for effecting in several steps corresponding to units of said operation clocks a digital filter process, having a characteristic which corresponds to the filter parameters, on at least one musical tone signal of said group of musical tone signals in accordance with the first control signal, the computing means also effecting in several steps corresponding to units of said operation clocks an effecter process, which corresponds to the effecter parameters, on at least one musical tone signal of said group of musical tone signals in accordance with the second control signal, characterized in that the first control signal, and the second control signal are fed to said computing means (5) alternatingly for each operation clock whereby for any of said steps some of said operation elements of said computing means (5) are required for said digital filter process whereas others of said operation elements are not required simultaneously for said digital filter process, and those of said operation elements not required for said digital filter process are used at least partially for said effecter process in the respective steps, thereby conducting virtual parallel processing of said digital filter process and said effecter process. A digital signal processor according to claim 1 wherein one musical tone signal of said group of musical tone signals corresponds to a plurality of channels which operate in a time division manner; and the digital filter process is executed with respect to musical tone signals of each channel independently, using different filter coefficient for each channel. A digital signal processor according to claim 1 wherein the processes, which are executed based on the first and second control signals respectively, are executed in a parallel manner distributed over a sampling period. A digital signal processor according to claim 1 wherein each sampling period is divided into a plurality of blocks, so that the first and second control signals are subjected to parallelization in each block of the sampling period. A digital signal processor according to claim 4 wherein one digital signal process is executed in accordance with the first control signal in each block of the sampling period, so that a plurality of digital signal processes are executed in one sampling period. A digital signal processor according to claim 5 further comprising filter designating means for generating filter designating data (8), wherein the control means (22 1 ) generates a variety of first control signals, so that the computing means executes digital filter processes of different algorithms in accordance with the variety of the first control signals. A digital signal processor according to claim 4 wherein one operation unit is executed in accordance with the second control signal by each block of the sampling period, so that a plurality of operation units are executed in one sampling period. A digital signal processor according to claim 7 wherein execution of the effecter process is realized by connecting the plurality of operation units, which are executed in one sampling period, in accordance with the second control signal. A digital signal processor according to claim 8 further comprising effecter designating means (9) for generating effecter designating data, wherein the control means (222) generates a variety of second control signals, so that the computing means (5) changes the manner of connection of the plurality of operation units in response to the variety of second control signals so as to execute effecter processes of different algorithms.

Inventors: ICHIKI TETSUJI, ICHIKI, TETSUJI, Ichiki, Tetsuji, c/o YAMAHA CORPORATION
Applicants: YAMAHA CORP, YAMAHA CORPORATION
Application year: 1993
Main classification: G10H1
IPC codes: G10K15, H04S1, G10H1