Control bus for multi-component consumer electronics system

Abstract: A consumer electronics system has plural apparatuses interconnected by a multiple channel for control and data signalization including a control channel. The control channel is a qualifier bus that in each apparatus is interfaced to a control element that in an initiator apparatus transmits a message selectively specifying a proprietary signalization interface. A follower apparatus acknowledges the message if the user signalization interfaces match. Thereupon, the system coactivates the matched interfaces in initiator and follower apparatuses. In an extended form, the apparatuses as a prerequisite try to consent about a standard protocol on a further control channel external to said multiple channel.

Description: The invention relates to a consumer electronics system comprising a plurality of apparatuses that are interconnected by a multiple parallel channel for the exchange of control and data signals, the parallel channel including a particular single control channel. A consumer electronics system may in particular comprise audio and/or video as classes of user signals, although other types of services that a user may require are not excluded. An example of such a system of interconnected apparatuses is described in European Patent Application EP-A-0 437 882. In that system, a video signal generating device is coupled via a signal bus to one or more signal receiving devices. In operation, the described system acts to determine which of a number of possible video signal formats (for example CVBS, Y/C, MAC) are supported by both the signal generator and signal receiver apparatuses. In the event that two or more formats are common to both generator and receiver, means are provided for selecting one of the common formats, usually on the basis of the highest quality available. A particular example of multi-contact connector is the standardized SCART connector that is used in combination with associated multi-wire cables for interconnecting audio/video apparatuses in the home, and for other applications. There is a proliferation of signal quality types available in modem audio/video systems, depending in particular on the program source. While many of these different signal types can be carried via multiwire cables, either in parallel or as alternatives, consumers will generally need some automated system for selecting and routing of signals to thereby assure the realization of the best quality that is available for watching or recording a given program, or optimising the use of other facilities. One solution is to use a proprietary (i.e dedicated and brand-specific) control system for making and breaking paths, using pin 10 of the SCART connector system. The problem with such proprietary systems is that they are often only valid for fixed combinations of products. They thereby exclude combining with products of other manufacturers, upgrading to a next product generation and often even combining with other contemporary products from the same manufacturer. Such proprietary solutions therefore need to be redeveloped from generation to generation. One solution is to use a standard bus system such as the Domestic Digital Bus (D2B), as standardised by the International Electrotechnical Commission (IEC), Geneva, Switzerland, and published by them as Standard IEC 1030. A system of apparatuses supporting the D2B standard requires a dedicated interconnection for each apparatus, but provides many additional control functions for the user. On the other hand, for the problem of signal quality matching, a simpler control system can be implemented using a spare conductor in the conventional multi-wire cable. Such a control system may be specific to one manufacturer, or may be standardized. A problem arises in that when two or more control systems (or protocols) are available in a given apparatus, conflicts will arise as to which system actually has control. Also, it is not desirable that a consumer who chooses at one point to use a simple control system is then prevented from gaining the benefits of a more functional control system at a later date, and forced to scrap the existing apparatus. In the long term, the consumer will benefit from compatibility of all his or her apparatuses, be they old or new. Accordingly amongst other things, it is an object of the invention to provide, in such consumer systems, an intermediate sage in the development of a standard solution, of which a particularly useful example is the above-mentioned D2B system. With current products getting more and more features, present proprietary solutions need upgrades, that may straightforwardly be implemented with the more powerful D2B system when all apparatuses on the system support the D2B protocols. A so-called system supported indication is proposed to find out whether the proprietary system implemented in a first product or initiator apparatus does match or does not match the proprietary system implemented in a second product or follower apparatus (which match is rather unlikely in the case of products from different manufacturers), or whether they both support the standard solution, such as for example the D2B standard. In other words, it is an object of the invention to allow an apparatus to use a control system integrated in a multi-wire cable, while maintaining the option to use alternative, more advanced, and in particular, standardized control systems if and when these are supported by the other apparatuses of the system. In accordance with a first aspect of the present invention there is provided a consumer electronics system as set forth in the opening paragraph, in which the said particular single control channel, referred to hereinafter as a qualifier bus, is interfaced within each such apparatus to a respective control element, characterised in that said control element in at least a first, initiator, apparatus is arranged for transmitting a first message selectively specifying one of a plurality of control system interfaces applicable to the initiator apparatus, and said control element in at least a second, follower, apparatus is arranged for acknowledging said first message upon matching of a control system interface applicable to that follower apparatus and the control system interface specified in said first message, the system being arranged for thereupon coactivating such matched control system interfaces in both the initiator apparatus and in the follower apparatus. In this way, the pairing of matched interfaces becomes extremely straightforward. The initiator apparatus may have only a single (perhaps proprietary) control system interface, it may have more than one thereof, or it may have only one such interface that may however operate in an environment that allows more than only a single such interface. Advantageously, in the said first initiator apparatus said control element is arranged to transmit, prior to the said first message, a second message specifying a standard control protocol defined on a further control channel external to the multiple parallel channel with the control element in at least the said second, follower, apparatus being arranged for acknowledging such a second message conditionally to matching therein of such standard control protocol applicable to the follower apparatus and that defined on the further control channel, the system being arranged for thereupon coactivating such standard control protocol in both the initiator apparatus and in the follower apparatus. Accordingly, the hierarchy of a full-fledged realization according to the invention is organized as follows among the standard control protocol and the various control system interfaces. First, if both apparatuses concerned are found to support the D2B or other standard protocol, this will subsequently be used. Next, if one or both apparatuses do not support D2B, but both have the same proprietary solution implemented, the latter will be used. Only if no corresponding solution has been implemented, no control features can be communicated between the two apparatuses concerned. In situations concerning more than two apparatuses at a time, similar considerations apply between each respective pair of apparatuses. Advantageously, said first and second messages are bitwise temporally hierarchized within a single message format, which is to say the first control element is suitably operable to generate and send on the qualifier bus the single message format having a fixed portion thereof within which is transmitted one or other of the first and second messages. The fusing of first and second messages to a single format that is transmitted only once, speeds up the selection. Advantageously, the first control element in the initiator apparatus is arranged to present an escape signal in the message, of which a dominant value indicates that a subsequent bit train in the message will signal particular initiator apparatus supported and standardized signal quality parameters, whereas a recessive value indicates that a subsequent bit train in the message will signal particular initiator apparatus supported and proprietary defined signal quality parameters. In this way, an initiator apparatus that does not have the specific signal quality indication protocol according to the present invention gets its way by default, whilst the signalling of particular signal quality indications is particularly fast. Mirroring this feature, the follower apparatus is suitably arranged to present an escape acknowledging signal in the message, of which a dominant value signals forthcoming bitwise acknowledging of the standardized signal quality parameters as being supported by the follower apparatus, whereas a recessive value signals forthcoming bitwise acknowledging of the proprietary defined signal quality parameters as being supported by the follower apparatus. The same advantages are now attained with respect to a follower apparatus. Advantageously, the system is arranged to include in the message a directional signalization with respect to a relative positioning of a source apparatus and a destination apparatus, respectively, with respect to a data stream between the initiator and follower apparatuses. The invention also relates to an initiator apparatus and to a follower apparatus, for use in such system, and as defined in the attached claims to which reference should now be made. These and other aspects and advantages of the invention will be better appreciated with regard to the description of preferred embodiments hereinafter, and in particular with reference to the appended Figures that show in particular: Figure 1 shows a system of audio/video apparatuses interconnected for the communication of AV signals and control signals; Figure 2 shows the signal allocations for two connectors and a multi-wire cable used in the system; Figure 3 shows the frame format of control signals transmitted via a control wire in the multi-wire cable; and Figure 4 shows representative bit waveforms for the control signals. Figure 1 shows a system of domestic audio/video (AV) apparatuses 110, 112, 114 etc. The first apparatus 110 is a display unit (television receiver or video monitor), while the remaining units are various AV apparatuses (VCR, satellite tuner, video disc player etc.) capable of acting as sources and/or destinations of AV signals. Each apparatus has one or two special multi-wire sockets, physically similar to the well-known SCART or Peritel sockets (standard IEC 933-1). The apparatuses are connected in a chain-like manner via multi-wire cables 116, 118, 120 etc., starting from the display unit 110. AV signals can pass through these cables in both directions, and are respectively designated "up-stream" or "down-stream", according to whether their source apparatus or destination apparatus, respectively, is nearer in the chain to the display unit 110. Referring also now to Figure 2, the special sockets are designated "I", if they are for connection to an apparatus which is down-stream in the chain, and "II", if they are for connection to an apparatus which is up-stream in the chain. In accordance with its position always at the head of the chain, the display unit apparatus 110 has only a type "I" socket. Figure 2 shows the assignment of signals among numbered contacts 1-21 of the special SCART-like sockets: type "II" on the left and type "I" on the right. The corresponding conductors in the multi-wire cable are also shown, in the central column of the Figure. In each apparatus, the corresponding contacts of sockets "I" and "II" are connected through to each other, either directly or via switches, so that the apparatus can send and receive AV signals to other apparatuses via the up-stream or downstream signal paths. The user interface of each apparatus allows the user to distinguish between the up- and down-stream signal paths. For example, a VCR forming apparatus 112 (Figure 1) may be given a RECORD UP command to record signals from a source apparatus (such as 114) further down the chain, and a RECORD DOWN command to record a signal coming from a signal source (TV tuner) in the display unit apparatus 110. Broadly speaking, the up-stream path will be used for playing functions to the user, and the down-stream path for recording. While any multi-wire interconnection system may be used, the particular allocation of contacts 1-21 shown in Figure 2 provides a good degree of compatibility with the existing standard, allowing for the presence in the system of older apparatuses with conventional SCART connectors. Signal names, levels and impedances are accordingly made compatible with the existing conventions, unless stated otherwise. Note that in each cable connection, there are two audio signal channels, A and B. Depending on the source of signals, channels A and B may be a stereo pair, or may carry monaural sound in two alternative languages. For video signals, similarly, the same program can be carried in various forms, referred to herein as signal qualities. There are up- and down-stream paths for composite video signals (CVBS), for signals with separate luminance and chrominance (Y and C), and there is an up-stream path only for primary colour signals RED, GREEN and BLUE (RGB). Of these video signal qualities, RGB is preferred over Y/C, which is in turn preferred over CVBS. However, each source and destination apparatus may be limited in the signal qualities it can generate or accept at a given particular time, or at all times. Furthermore, the limited number of contacts and wires means that not all qualities can be carried in both directions at the same time. Note that signals CVBS up and C up share the same conductor as do signals CVBS down and C down, signals RED up and C up, and signals BLUE up and C down. An additional aspect of signal quality today is the aspect ratio of a video picture: whether it is of normal or wide screen format. Some control mechanism is clearly required, at least to determine which signal qualities should be used at any point in a signal path, be it up-stream or downstream, and this is provided by reserving one signal path for the carriage of interface establishment messages. This path, referred to hereinafter as the qualifier bus, is connected to each compatible apparatus via contact 10. Each apparatus 110, 112 and 114 has a first control interface module CTRL1 within it to transmit and receive message frames via contact number 10. Contact 10 (and its return contact 21) are connected directly through each apparatus from socket 'I' to socket 'II'. Figure 3 shows two types of message frame which can be sent by a module CTRL1 via the qualifier bus (control wire - contact 10). A message frame will generally be sent when an apparatus changes state, typically as a result of a user command, or for example upon the triggering of a VCR timed recording. The apparatuses do not have individual addresses. Rather, for each frame, one apparatus acts as "initiator" of the message, while the others, referred to as "followers", are obliged to 'listen' to the frame. However, it will be seen that a follower is allowed to modify certain bits in each frame. Figure 4 shows representative bit waveforms at the outputs of an initiator and a follower. The signal level actually present on the qualifier bus is shown at the foot of Figure 4, and takes either a low or a high level, labelled L and H respectively. The output of each apparatus has a low impedance (dominant) state, labelled D in the figure, and a high impedance (recessive) state, labelled R. Since the outputs of all modules CTRL1 are connected together via the qualifier bus, the level on the wire is a logical combination (wired-AND) of the outputs of all modules CTRL1 connected in the chain. Any output in the dominant state D will force the qualifier bus low (L). The qualifier bus will only be high (H) when all outputs are in the recessive (R) state. Figure 4 illustrates three representative bit periods, numbered n, n+1 and n+2, during which the control element of the initiator CTRL1 module outputs logical values '1', '1' and '0' in sequence. Each bit begins with a transition to the dominant state, at a time labelled BIT SYNC. All followers synchronize their bit timing to this event. At a predetermined time BIT SAMPLE following each BIT SYNC transition, the state D or R of the initiator output indicates, respectively, whether a '0' or '1' bit is being transmitted. On the other hand, the actual level L or H on the qualifier bus at time BIT SAMPLE determines whether a logic '0' or logic '1' value is received for that bit by each module CTRL1. As can be seen in Figure 4, the bits n and n+2 will be received as logic '1' and '0' respectively, namely the values transmitted by the initiator. The bit n + 1, however, is modified by the dominant output of the follower, so that a '0' will be detected instead of the '1' transmitted by the initiator. The initiator also samples the actual level on contact 10, so that it too knows the modified bit value. In Figure 3, two alternative frame formats are shown. Having established that no other module is transmitting on the qualifier bus, the initiator generates a START signal for the frame, by making its output dominant for a predetermined period. The frame continues with a header comprising five bits labelled ESC, DIR, PAS, NAS and DES, then a further sixteen data bits. When ESC=0, the sixteen bits are designated Quality bits QTY 1- 16 as shown in Figure 3a. When ESC=1, the sixteen data bits are designated Control System Supported bits CSS 1-16, as shown in Figure 3b. In a frame with ESC=0 the header and Quality bits provide a system for management of the signal path switching and video signal qualities, to provide the user with best quality signal paths from source to destination in up- and down-stream directions. This is achieved by the exchange of header and data bits. Some of the header and data bits must only be set by the initiator, and will be referred to as flag bits. Others of the data bits may be modified by a follower, and are known as Arbitration bits. The detailed meaning of these bits will be described later. For the avoidance of doubt, a frame sent by the initiator corresponds to the first interface establishment message referred to hereinbefore and the frame as modified or not (as the case may be) by the follower corresponds to the first acknowledgement message. The above-mentioned second interface establishment message corresponds to the frame sent by the initiator when it supports D2B or another proprietary control system, that is to say a frame where the escape bit ESC=1. Returning to Figure 1, this shows how other control modules of type CTRL2 and CTRL3 may be provided in a consumer apparatus. A module CTRL2 provides for control of and by the apparatus via a standard control bus, namely the D2B bus and related protocols as described in Standard IEC 1030 mentioned previously. D2B distributes system control intelligence over all apparatuses, while providing for cooperation between apparatuses of different brands in a standardised manner. Compared with the CTRL1 system described so far, D2B requires dedicated cabling between apparatuses, but has the advantages of a full range of control features, more flexible signal routing, a higher data rate, full device-subdevice addressing and message security (parity checking). Due to crosstalk within the multi-wire cables, for example, the data rate of the qualifier bus (SCART contact 10) must be kept very low. An example of D2B in application can be found in GB 2 223 114 A (PHN 12678), which describes the automatic establishment of signal paths between source and destination devices. Like module type CTRL1, module type CTRL3 uses contact 10 and the qualifier bus to provide a control function which is proprietary to one supplier. Various suppliers already produce or plan to produce apparatuses using contact 10 for their own purposes, and it is desirable that the system proposed by the present invention should be able to function as an alternative to D2B or such a proprietary system within the same apparatus. Otherwise the purchaser of a CTRL1 type apparatus would be 'locked out' of the market for enhanced facilities offered by D2B or proprietary solutions. The Control System Supported bits CSS 1-16 of the second message frame format (ESC = 1) provide a system of arbitration which selects the control module CTRL1,2 or 3 to be used from among those available in the relevant apparatuses. In the following embodiment, it is assumed that each participating apparatus supports signal path and quality control via a module CTRL1, optionally via D2B (CTRL2), and optionally via one proprietary control protocol (CTRL3) only. Alternative embodiments can readily be conceived if necessary, for example to allow more than one proprietary control system, and other standard systems using the multi-wire cables or dedicated wiring, optical fibres etc. The behaviour of the initiator and followers during a frame are defined below, with examples in a form of pseudo-code. The code will be largely self explanatory to the person skilled in the art, when keeping in mind the frame format as outlined in Figure 3 and the bit waveforms of Figure 4. It should be remembered in particular that a logic '1' in any bit position is recessive, so that a logic '0' output by another apparatus will predominate. As an example, the notation "Output QTY1 = 1" indicates the value '1' for a bit output by the relevant apparatus during bit period QTY1, while "Sample QTY1 = 0" indicates that the actual bit value detected on the control wire (contact 10) during the same bit period is logic '0'. Explanatory comments appearing within the pseudo-code segments are placed between curly brackets (braces) thus: {...} Following the START bit, each bit of the frame is processed simultaneously by the initiator and the followers. The first Header Bit is the Escape Bit ESC. As mentioned above, the setting of the Escape Bit depends on whether the initiating apparatus wishes to perform signal quality optimisation (ESC=0) or to select the control system (ESC=1). The second Header Bit, DIR, is the Direction Bit. The setting of this determines whether this control frame concerns AV signals travelling up-stream (DIR=1) or down-stream (DIR=0). This is of course relevant for switch settings and signal-called capabilities within each apparatus. The third Header Bit, PAS, is used to determine whether any apparatus is Presently an Active Source of AV signals for an established signal path in the specified direction. If the initiator determines that an active source of AV signals already exists (by setting its output PAS=1 and detecting PAS=0) it may terminate the attempt to establish communications. The fourth Header Bit, NAS is used to determine whether any apparatus is a New Active Source of AV signals. An apparatus is a new active source when it is activated by a user to supply AV signals and no signal path has been established yet. The fifth Header Bit, DES, complements the presently active source PAS bit. An apparatus responds with the DES bit dominant (that is to say it outputs DES=0) when it is active as a destination for AV signals in the specified direction. Turning to the data bits, for a frame with Sample ESC =0, the data bits are signal quality bits QTY 1-16. Initiator and Follower need not be distinguished for the following examples, provided that the reader notes the distinction between 'flag' type bits and 'arbitration' type bits defined above. In a frame where Sample ESC = 1 the data bits are Control System Supported bits CSS1 ... CSS 16, the functions of which are defined in the following example: From the above, it will be apparent to the skilled person how the best signal quality which is supported throughout the signal path can be identified and used to implement the user's wishes using the best possible quality. For example, if any apparatus in the chain does not support RGB quality signals, the bit QTY5 will be forced low by that apparatus, telling the source apparatus that Y/C or CVBS must be used. Similarly, a priority is established between the various control systems and protocols that may be available within the system. If the D2B standard is supported by all apparatuses in the signal path, then bit CSS1 will be '1'. Then all apparatuses will respond to control via their D2B interface (modules CTRL2) only. This is desirable in view of the greater range of control features provided, inter-brand compatibility, better error handling and so forth. On the other hand, if not all apparatuses can be controlled via D2B, but they can communicate via the qualifier bus (contact 10), then it is desirable that they do so. If all apparatuses are provided with control modules CTRL3 which support a common proprietary control system, then this may be preferred over the use of the CTRL1 system.

Claims: A consumer electronics system comprising a plurality of apparatuses (110,112,114) that are interconnected by a multiple parallel channel (116,118) for the communication of control signals and system data, the multiple parallel channel including a particular single control channel, the said particular single control channel, referred to hereinafter as a qualifier bus, being interfaced within each such apparatus to a respective control element (CTRL1), characterised in that said control element in at least a first, initiator, apparatus is arranged for transmitting a first message selectively specifying one of a plurality of control system interfaces applicable to the initiator apparatus, and said control element in at least a second, follower, apparatus is arranged for acknowledging said first message upon matching of a control system interface applicable to that follower apparatus and the control system interface specified in said first message, the system being arranged for thereupon coactivating such matched control system interfaces in both the initiator apparatus and in the follower apparatus. A system as claimed in Claim 1, wherein in the said first initiator apparatus said control element (CTRL1) is arranged to transmit, prior to said first message, a second message specifying a standard control protocol defined on a further control channel (D2B) external to the multiple parallel channel (116,118) with said control element in at least the second, follower, apparatus being arranged for acknowledging such second message conditionally to matching therein of such standard control protocol applicable to that follower apparatus and that defined on said further control channel, said system being arranged for thereupon coactivating such standard control protocol in both the initiator apparatus and in the follower apparatus. A system as claimed in Claim 2, wherein the first control element is operable to generate and send on the qualifier bus a single message format having a fixed portion thereof within which is transmitted one or other of the said first and second messages. A system as claimed in Claim 2 or 3, wherein said further control channel is a serial data bus and communications thereon conform to D2B communications protocols. A system as claimed in any of Claims 1 to 4, wherein at least said initiator apparatus comprises at least two different such interfaces (CTRL1, CTRL2), and said system is arranged for executing a search for finding a matching pair of such interfaces in the initiator apparatus and the follower apparatus. A system as claimed in any of Claims 1 to 5, wherein the first control element in said initiator apparatus is arranged to present an escape signal in the message, of which a dominant value indicates that a subsequent bit train in the message will signal particular initiator apparatus supported and standardized signal quality parameters, whereas a recessive value indicates that a subsequent bit train in the message will signal particular initiator apparatus supported and proprietary defined signal quality parameters. A system as claimed in Claim 6, wherein the follower apparatus is arranged to present an escape acknowledging signal in the message, of which a dominant value signals forthcoming bitwise acknowledging of the standardized signal quality parameters as being supported by the follower apparatus, whereas a recessive value signals forthcoming bitwise acknowledging of the proprietary defined signal quality parameters as being supported by the follower apparatus. A system as claimed in any of Claims 1 to 7, wherein the initiator apparatus is arranged to include in the said message a directional signal with respect to a relative positioning of said initiator and follower apparatus, respectively. A system as claimed in any of Claims 1 to 8, and being arranged to present an initialization signal in the message with respect to an initiator apparatus, and acknowledging the said initialization signalization with respect to a follower apparatus, respectively. An initiator apparatus for use in a consumer electronics system comprised of the initiator apparatus and one or more follower apparatuses connected for communication of system data and control signals therebetween by a multiple parallel-path channel (116), one part of which, referred to hereinafter as the qualifier bus, is reserved for the carriage of control system interfacing messages; said initiator apparatus comprising: multiple parallel path connector means (I,II) connectable to respective ones of the multiple parallel paths, including the qualifier bus, with said initiator apparatus being operable to transmit and/or receive system data and control signals on paths of the multiple parallel path channel (116) via the multiple parallel-path connector means, characterised in that the initiator apparatus supports a plurality of control system interfaces governing the transmission and/or reception of system data and control signals, with a selected one of the said plurality of interfaces being active at any instant; and a control element (CTRL1) operable to generate a control system interface message based on information identifying the said selected one of the control system interfaces and send this first control system interface message, via the multiple parallel path connector means, on the qualifier bus; wherein the control element (CTRL1) is further operable to detect, via the multiple parallel path connector means, signals on the qualifier bus and, on detection of a predetermined acknowledgement message in response to the control system interface message, to initiate the transmission and/or reception of the said system data and control signals in accordance with the said selected one of the control system interfaces. A follower apparatus for use in a consumer electronics system comprised of an initiator apparatus and one or more of the follower apparatuses connected for communication of system data and control signals therebetween by a multiple parallel-path channel (116), one path of which, referred to hereinafter as the qualifier bus, is reserved for the carriage of control system interface messages; the follower apparatus comprising: multiple parallel-path connector means (I,II) connectable to respective ones of the said multiple parallel paths (116), including the qualifier bus, with the follower apparatus being operable to transmit and/or receive the said system data and control signals via the multiple parallel-path connector means on paths of the multiple parallel-path channel, the follower apparatus supporting at least one control system interface governing the transmission and/or reception of the system data and control signals; and characterised by a control element (CTRL1) operable to detect, via the multiple parallel-path connector means, signals on the qualifier bus including a control system interface message identifying a control system interface supported by the initiator apparatus, to compare this initiator-supported interface with the said follower-supported interface and, where a match occurs, to generate and send on the qualifier bus an acknowledgement message; wherein, on generation of the acknowledgement message in response to the first control system interface message, the control element (CTRL1) is operable to initiate transmission and/or reception of the system data and control signals in accordance with the said matched control system interface.

Inventors: VAN STEENBRUGGE BERNARD, VAN STEENBRUGGE, BERNARD
Applicants: D2B SYSTEMS CO LTD, D2B SYSTEMS CO. LTD.
Application year: 1993
Main classification: H04L12
IPC codes: H04N9, H04B1, H04N7