Improved semiconductor memory device including memory cells connected to a ground line

Abstract: A memory cell array in a static random access memory (SRAM) includes an improved circuit. Memory cells (M51 - M58) in one row are connected to a ground line (GL1). The memory cells (M61 - M68) in another row are connected to the ground line (GL2). Word lines (WL2, WL3) each are connected alternately to the memory cells of two rows column by column. In a read operation, when one of the word lines (WL2) is activated, a current flows from the memory cell to the two ground lines. Since a total of currents flowing through one ground line is reduced, the rise of potentials of the ground lines is prevented, so that destruction of data can be prevented.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device including memory cells connected to a ground line. The present invention has particular applicability to a static random access memory (SRAM). Description of the Background Art In recent years, static random access memories (hereinafter referred to as "SRAMs") using thin film transistors (hereinafter referred to as "TFTs") have been developed and marketed to meet the requirements for higher degree of integration and low power consumption of semiconductor memory devices. An example of the SRAM using TFTs is disclosed in a paper entitled "A POLYSILICON TRANSISTOR TECHNOLOGY FOR LARGE CAPACITY SRAMs" (1990, International Electron Devices Meeting (IEDM), pp 469-472). Although the invention can be generally applied to the semiconductor memories including memory cells connected to a ground line, an example in which the present invention is applied to the SRAM will be described hereinafter. Fig. 8 is a block diagram of a conventional SRAM. Referring to Fig. 8, an SRAM 100 includes a memory cell array 1, an X decoder 2, a Y decoder 3, a sense amplifier 5, an output buffer 6, an input buffer 7 and a write circuit 8. Memory cell array 1 includes a large number of memory cells MC disposed in rows and columns. In Fig. 8, each of memory cell groups 1r, 1r, ..., arranged in a lateral direction is a row, and each of memory cell groups 1c, 1c, ..., arranged in a vertical direction is a column. X decoder 2 selects a row in memory cell array 1. Y decoder 3 selects a column in memory cell array 1. Sense amplifier 5 amplifies a data signal read out from the memory cell MC. Output buffer 6 provides the amplified data signal as output data DO. Input buffer 7 receives externally applied input data DI. Write circuit 8 amplifies an input data signal to write the resultant signal in a desired memory cell MC. In Fig. 8, a line 100 also indicates a semiconductor substrate. In reading operation, the X-decoder 2 activates one of word lines WL in response to an externally applied X-address signal XA. A data signal, which is stored in the memory cell MC connected to the activated word line WL, appears on bit lines BLa and BLb. The Y-decoder 3 selects one bit line pair in response to an externally supplied Y-address signal YA. More specifically, one of switch circuits in a Y-gate circuit 4 is rendered conductive in response to an output signal supplied from the Y-decoder 3, and therefore the data signal on one bit line pair is applied to the sense amplifier 5. The applied data signal is amplified by the sense amplifier 5, and then is supplied as the output data DA through the output buffer 6. In writing operation, input data DI is applied through the input buffer 7 to a write circuit 8. The applied data signal is amplified by the write circuit 8, and then is applied to the gate circuit 4. The Y-decoder 3 sets one of the switch circuits in the gate circuit 4 conductive in response to the Y-address signal YA, and therefore the amplified data signal is applied to the corresponding bit line pair. The X-decoder activates one of the word lines WL in response to the X-address signal XA, and therefore the input data DI is stored in the designated memory cell. Fig. 9 is a circuit diagram using TFTs. Referring to Fig. 9, the memory cell MC includes PMOS transistors 105 and 106 and MMOS transistors 101 and 102, which form a data storing circuit, as well as NMOS transistors 103 and 104 serving as access gate transistors. The transistors 105 and 106 are formed of the TFTs described before. A source of the driver transistor 101 is connected to a ground line GL through a direct contact resistance R1, which will be described later. Likewise, a source of the driver transistor 102 is connected to a ground line GL through a direct contact resistance R2. The transistors 103 and 104 are connected at their gates to the word line WL. In writing operation, the bit line (e.g., BLa) attains a high level and the bit line BLb attains a low level and thereafter the word line WL is activated. Since the transistors 103 and 104 are turned on, nodes N1 and N2 of the data storing circuit change to the high and low levels, respectively. In this data stored state, the transistors 102 and 105 are turned on, and the transistors 101 and 106 are turned off. In reading operation, when the word line WL is activated, a current I flows from a power supply potential Vcc to a ground potential, as shown in Fig. 9. More specifically, the current I flows to the ground line GL through a bit line load transistor 111, access gate transistor 104 and driver transistor 102. In this current path I, there exists the direct contact resistance R2 and an interconnection resistance r, so that a potential of a ground node N4 of the memory cell MC is raised. Thus, during the activation of the word line WL, the current I flows through the memory cell MC toward the ground line GL, whereby the potential of ground node N4 rises. This current I is referred to as a "column current". Since the column current I is a thousand to a million times as large as the currents flowing through the TFTs 105 and 106, the rise of the potentials of ground nodes N3 and N4 is a remarkable problem particularly in the SRAM. Fig. 10 is a schematic block diagram of a memory cell array including the memory cells shown in Fig. 9. Referring to Fig. 10, the memory cell array includes memory cells M41' - M78' disposed in rows and columns. Word lines WL1 - WL4 are connected to the memory cells in first to fourth rows. The memory cells M41' - M48' and M51' - M58' in the first and second rows are connected to a ground line GL1 through direct contact resistances R. Likewise, the memory cells M61' - M68' and M71' - M78' in the third and fourth rows are connected to the ground line GL2. Each of the ground lines GL1 and GL2 includes the interconnection resistance r. The ground lines GL1 and GL2 are connected to common ground lines GNDLa and GNDLb. The word lines WL1 - WL4 and ground lines GL1 and GL2 extending in a lateral direction in Fig. 10 are formed of polysilicon layers or polycide layers on the semiconductor substrate. Meanwhile, the ground lines GNDLa and GNDLb extending in a longitudinal direction in Fig. 10 are formed of aluminium interconnections. In general, the aluminium has a resistance lower than that of polysilicon and polycide. Therefore, the longitudinal ground lines GNDLa and GNDLb in Fig. 10 are made of aluminium for reducing the resistances of ground lines. Although not shown in Fig. 10, the bit lines are formed of longitudinal aluminium interconnections in Fig. 10. Fig. 11 shows a layout of the memory cells M62' and M63' of Fig. 10 formed on the semiconductor substrate. In this layout, the transistors 101, 102, 103 and 104 shown in Fig. 9 among the transistors forming the memory cell M62' are depicted. The PMOS transistors 105 and 106 formed of TFTs do not appear in the layout diagram of Fig. 11. Referring to Fig. 11, the memory cell M62' includes first polysilicon layers 214 and 215, which form the transistors 101 and 102, respectively, as well as first polysilicon layers 212' forming the transistors 103 and 104, respectively. Regions AR surrounded by dashed lines are active regions formed in the semiconductor substrate. A source of the transistor 101 is connected through a direct contact DC2 to the ground line (GL2) formed of a third polysilicon layer 230. Likewise, a source of the transistor 102 is connected through a direct contact DC1 to the third polysilicon layer 230. Other memory cells M52', M53' and M63' have layouts similar to those of the memory cell M62'. Fig. 12 is a cross section of a structure including the direct contact DC2 shown in Fig. 11. Referring to Fig. 12, a P-type well 251 is formed on an N-type semiconductor substrate 250. Insulating layers 241 and 242 are formed on the P-type well 251. First polysilicon layers 215 and 216 are formed on the insulating layers 241 and 242, respectively. The first polysilicon layers 215 and 216 are insulated by an insulator 240. A third polysilicon layer (i.e., ground line GL2) 230 insulated by the insulator 240 is directly connected to an active region AR1 formed in the P-type well 251. At a contact portion between the third polysilicon layer 230 and active region AR1, there exists a resistance, which is referred to as a "direct contact resistance". The direct contact resistances R1 and R2 shown in Fig. 9 and the direct contact resistance R shown in Fig. 15 are caused in this manner, because the ground line is formed of polysilicon. Fig. 13 is a circuit diagram showing the currents flowing through the ground line GNDLa in the memory cell array in Figure 15. Referring to Fig. 13, upon activation of the word line WL1, column currents I1 - I5 flow from the memory cells M41' - M45' to the ground line GL1, respectively. Each of the currents I1 - I5 flows through the corresponding direct contact resistance R and interconnection resistance r to the ground lines GNDLa and GNDLb (= volt). As can be seen from Fig. 13, nearer to the end of the ground line GL1, in other words, nearer to the ground line GNDLa, the current flowing through the ground line GL1 increases. Since the ground line GL1 includes the interconnection resistance r, the potentials at respective positions on the ground line GL1 change dependent on the existence of the currents I1 - I5. Thus, as indicated by curve C2 in Fig. 14, the potential VGL1 changes the position by position on the ground line GL1. In particular, as the current flowing through the ground line GL1 increases, the potentials at respective positions on the ground line GL1 rise. The rise of potentials of the ground line GL1 destroys the data stored in the memory cells. In particular, as can be seen from curve C2 in Fig. 14, the maximum rise of potential is caused at a central portion of the ground line GL1, so that data stored in the memory cells M44' and M45' at the central positions among the memory cells M41' - M48' is particularly liable to be destroyed. In addition, there is another problem. Referring to Fig. 13 again, the column current supplied, e.g., from the memory cell M42' flows as a current I2 from the right side in the figure in some cases, and also flows as a current I2' from the left side in other cases. When the column current I2 flows from the memory cell M42', a potential VN14 of a common connection node N14 of the memory cells M41' and M42' is expressed by the following expression. VN14 = (I1 + I2 + I3 + I4)•2r + I1•R When the column current I2' flows from the memory cell M42', a potential VN14' of the node N14 is expressed by the following expression. VN14' = (I1 + I2 + I3 + I4)•2r + (I1 + I2')•R For example, it is assumed that each of the column currents I1 - I4 is 20µA, the direct contact resistance R is 500Ω, and the interconnection resistance r is 20Ω. The potentials VN14 and VN14' in the respective cases are expressed by the following expressions. VN14 = 1.6 x 10 -2 + 1.0 x 10 -1 = 0.116V VN14' = 1.6 x 10 -2 + 2.0 x 10 -1 = 0.216V As can be seen from the foregoing expressions (1) - (4), when the word line WL1 is activated, the potential of the connection node N14 changes, depending on a state of storage of data in the memory cell M42', which may also destroy data as described before. The changes of potentials VN14 and VN14' are represented by curves C3 and C4 in Fig. 15. In Fig. 15, the ordinate represents the potential, and the abscissa represents positions of nodes N13 and N14. US 4 733 374 discloses a DRAM device including a first memory cell, comprising a semiconductor substrate, a first conductive layer formed on the substrate, a first and second access transistor, each having a gate formed from the first conductive layer, an insulating layer formed on the first and second access transistor gates, the insulating layer having a first contact hole therein to expose the first access transistor gate, a second conductive layer formed on the insulating layer, a first word line formed from the second conductive layer, the first word line being connected to the first access transistor gate through the first contact hole, a second memory cell adjacent to the first memory cell, the insulating layer further having a second contact hole therein to expose the second access transistor gate, and a second word line formed from the second conductive layer, the second word line being connected to the second access transistor gate through the second contact hole. Patent Abstracts of Japan as to JP 62-188263 (A) discloses a SRAM device, wherein, for the purpose of reducing the potential difference of the earthing point and an earthing wire of the memory cell, the word lines of two adjacent rows are interchanged by a connection in a crossing form in the center point or its vicinity. Patent Abstracts of Japan as to JP 4-186671 (A) discloses a SRAM device, wherein the word lines of two adjacent rows are interchanged by crossing after each column such that every second memory cell of the same row is connected to the same word line. EP 0 501 884 A2 discloses a semiconductor memory device including access and driver transistors having gates, word lines and a ground line, the word lines having a so-called split word line arrangement. The gates and the word lines are made from a first of five polysilicon layers, whereas the ground line is made from the fifth of the five layers. An object of the invention is to provide an improved semiconductor memory device including memory cells connected to a ground line, which is capable of preventing destruction of data stored in the memory cells and allows smaller memory cells. This object is achieved by a semiconductor memory device according to claim 1. Further developments of the invention are given in the dependent claims. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, of which Fig. 1 is a schematic block diagram of a memory cell array of an embodiment of the invention; Fig. 2 is a schematic diagram for showing currents flowing through ground lines in a memory cell array shown in Fig. 1; Fig. 3 is a graph showing change of a potential of a ground node N4 shown in Fig. 2; Fig. 4 is a layout of memory cells shown in Fig. 1 on a semiconductor substrate; Fig. 5 is a schematic block diagram of a memory cell array of another embodiment of the invention; Fig. 6 is a schematic block diagram of a memory cell array of yet another embodiment of the invention; Fig. 7 is a layout of oblique word lines shown in Fig. 9 on a semiconductor substrate; Fig. 8 is a block diagram of an SRAM in the prior art; Fig. 9 is a schematic diagram of a memory cell using TFTs; Fig. 10 is a schematic block diagram of a memory cell array including memory cells shown in Fig. 9; Fig. 11 is a layout of memory cells shown in Fig. 10 on a semiconductor substrate; Fig. 12 is a cross section of a structure including a direct contact DC2 shown in Fig. 11; Fig. 13 is a schematic diagram showing currents flowing through a ground line in a memory cell array shown in Fig. 10; Fig. 14 is a graph showing change of a potential on a ground line shown in Fig. 13; and Fig. 15 is a graph showing change of a potential of a ground node N14 shown in Fig. 13. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 1, a memory cell array includes memory cells M41 - M78 disposed in rows and columns. The memory cells M41 - M48 in one row and the memory cells M51 - M58 in another row are connected to a ground line GL1 through a direct contact resistance R. Likewise, the memory cells M61 - M68 and M71 - M78 are connected to a ground line GL2. The ground lines GL1 and GL2 are formed of a polysilicon layer or a polycide layer on a semiconductor substrate. These ground lines are connected to common ground lines GNDLa and GNDLb made of aluminium. In comparison with the memory cell array in Fig. 10, word lines WL0 - WL5 are connected to the memory cells in a fashion different from that in Fig. 10. As shown in Fig. 1, the word lines WL0 - WL5 form pairs two by two, and the paired word lines are twisted. For example, the word line WL2 is connected to the memory cells M51, M62, M53,···. In a manner complementary to this, the word line WL3 is connected to the memory cells M61, M52, M63,···. In other words, the word line WL2 is alternately connected to the memory cells M51 - M58 and M61 - M68 of the second and third rows. In a fashion complementary to the word line L2, the word line WL3 is connected alternately to the memory cells M51 - M68. More specifically, a plurality of pairs M51 and M62, M53 and M64, ..., M57 and M68 in successive memory cells M51, M62, M53, ..., M68 connected to the word line WL2 are positioned alternately in neighboring rows. Similarly, a plurality of pairs M61 and M52, M63 and M54, ..., M67 and M58 in successive memory cells M61, M52, M63, ..., M58 connected to the word line WL3 are positioned alternately in neighboring rows. The word lines WL0 - WL5 are also formed of the polysilicon layer or polycide layer. In Fig. 1, paired word lines of the word lines WL0 to WL5 have end portions on the side of the ground line GNDLa not twisted, and end portions on the side of the ground line GNDLb twisted. The present invention is not limited to such an example of Fig. 1. The end portions on the sides of the ground lines GNDLa and GNDLb of the paired word lines may be twisted or not twisted. Fig. 2 is a circuit diagram for showing currents flowing through the ground lines GL1 and GL2 in the memory cell array shown in Fig. 1. In Fig. 2, there are shown the memory cells M51 - M55 and M61 - M65 in the second and third lines among those in the memory cell array shown in Fig. 1. For example, when the word line WL2 is activated, the memory cells M51, M62, M53, M64, M55,··· are accessed. Therefore, column currents I1 - I5 flow from the accessed memory cells to the ground lines GL1 and GL2. The currents I1 and I3 among the currents I1 - I5 flow through the ground line GL1 to the ground line GNDLa. The currents I2 and I4 flows through the ground line GL2 to the ground line GNDLa. The current I5 flows through the ground line GL1 to the ground line GNDLb (not shown). As can be seen from Fig. 2, when one of the word lines WL2 is activated, the current flows from the selected memory cell through the two ground lines GL1 and GL2. Therefore, the total of currents flowing through each of the ground lines GL1 and GL2 is smaller than the sum of the current flowing through one ground line GL1 shown in Fig. 13. Therefore, the rise of potentials of the ground lines GL1 and GL2 is half the rise of the potential of the ground line GL1 shown in Fig. 13. Referring to Fig. 14 again, curve C1 shows the change of potential on the ground line GL1 shown in Fig. 2. As can be seen from the comparison with curve C2 showing the change of potential on the ground line GL1 in Fig. 13, the rise of potential on the ground line GL1 in Fig. 2 is half the rise of potential of the ground line in Fig. 13. In a memory cell array shown in Fig. 1, when the word line WL2 is activated for the read operation, the potential of the ground line GL1 rises to an extent smaller than that in the memory cell array in Fig. 10, so that destruction of data which may be caused by the rise of potential of the ground line is prevented. Further, the potential of ground node N4 of the memory cell M62 changes dependent on whether the current (i.e., current I2) flows from the right side of the memory cell M62, or the current (i.e., current I2') flows from the left side of the memory cell M62, in a manner as described below. When the current I2 shown in Fig. 2 flows from the memory cell M62, the potential VN4 of ground node N4 is expressed by the following expression. VN4 = (I2 + I4)•3r + I2•R In the case where the current I2' shown in Fig. 2 flows from the memory cell M62, the potential VN4' of ground node N4 is expressed by the following expression. VN4' = I2'•2r + I4•3r Similarly to the example shown in Fig. 13, assuming that each of the column currents I1 - I4 is 200µA, the direct contact resistance R is 500Ω, and the interconnection resistance r is 20Ω, then VN4 = 0.124 volt and VN4' = 0.02 volt are obtained from the expressions (5) and (6). As can be seen from the comparison of these values with the values expressed by the expressions (3) and (4), the rise of potential of the ground node N4 in the memory cell M62 can be reduced. The change of potential at the ground node N4 is shown in Fig. 3. As described above, when the word lines are connected alternately to memory cells in neighboring rows, a circuit of a configuration in which the word lines are connected alternately to memory cells column by column can prevent the most effectively the rise of potential of ground nodes caused by a current flowing from the neighboring memory cells to ground nodes therebetween. Fig. 4 is a diagram showing a layout of the memory cells M63 and M64 shown in Fig. 1 on the semiconductor substrate. In order to connect the word lines WL2 and WL3 alternately to the memory cells column by column, the word lines WL2 and WL3 are formed as shown in Fig. 4 on the semiconductor substrate. Referring to Fig. 4, the word line WL2 includes a first polycide layer 211, a second polysilicon layer (or second polycide layer) 222 and a first polycide layer 213 which are formed on the semiconductor substrate. The first polycide layer 211 is connected to the second polysilicon layer 222 through a contact hole CH1. The second polysilicon layer 222 is connected to the first polycide layer 213 through a contact hole CH2. The word line WL3 includes a second polysilicon layer 221, a first polycide layer 212 and a second polysilicon layer 223 which are formed on the semiconductor substrate. The second polysilicon layer 221 is connected to the first polycide layer 212 through a contact hole CH3. The first polycide layer 212 is connected to the second polycide layer 223 through a contact hole CH4. In the layout of Fig. 4, there are shown four transistors 101, 102, 103 and 104 forming one memory cell (e.g., M63). The PMOS transistors 105 and 106 formed of TFTs are not shown on Fig. 4. The driver transistor 101 is formed of a first polycide layer 215. The driver transistor 102 is formed of a first polycide layer 214. The access gate transistors 103 and 104 are formed of the first polycide layer 212. Regions AR represent active regions formed in the semiconductor substrate. A ground line GL2 is formed of a third polysilicon layer (or third polycide layer) 230. The third polysilicon 230 is connected to the active regions through the direct contacts DC1, DC2 and DC3. Each of the direct contacts DC1 - DC3 has the aforementioned direct contact resistance R. Fig. 5 is a schematic block diagram showing another embodiment of the present invention. In the memory cell array shown in Fig. 1, there are provided the word lines each of which is connected alternately to the memory cells of two rows column by column. Meanwhile, in the memory cell array shown in Fig. 5, there are provided word lines WL10 - WL15 each having portions connected alternately to the memory cells in two rows, two columns by two columns. More specifically, a plurality of pairs of successive memory cells connected to the word lines WL10 to WL15, respectively, are positioned alternately in neighboring rows. In a specific configuration, the word lines WL10 to WL15 are connected alternately, two columns by two columns, to memory cells excluding memory cells on both ends of each row. The word lines WL10 to WL15 are connected alternately to respective memory cells of one ends of respective rows and respective memory cells neighboring thereto, and alternately connected to respective memory cells on the other ends of respective rows and respective memory cells neighboring thereto. In the embodiment shown in Fig. 5, when one of the word lines is activated, the total of currents flowing from the memory cells to the ground lines is reduced by half, compared with the circuit shown in Fig. 10, so that the rise of potentials of the ground lines can be prevented. Therefore, the destruction of data stored in the memory cells can be prevented also in this embodiment. In this embodiment, in memory cells in neighboring rows, word lines are connected alternately to memory cells two columns by two columns. Therefore, the effects of suppressing the rise of potential of ground nodes caused by a current flowing from neighboring memory cells to ground nodes therebetween are a little smaller than those of the circuit shown in Fig. 1. However, the effects of suppressing the rise of potential of the ground nodes are larger than the case where word lines are connected alternately to memory cells for every two or more columns. In addition, the following peculiar effect can be obtained in this embodiment. The effects of suppressing the rise of potential of the ground node as described above can be obtained at ground nodes between memory cells of portions to which word lines are connected alternately in each row. Referring to Fig. 14, memory cells (for example, M41, M48) at respective ends of the ground lines GL1, GL2 have the greatest potential difference between ground nodes on both sides of the memory cell. Therefore, by decreasing the potential difference between ground nodes of memory cells at respective ends of the ground lines GL1, G12, it is possible to effectively suppress the rise of potential of the ground lines GL1, GL2, compared to the case where the potential difference between the ground nodes of other memory cells is decreased. Focusing on memory cells at respective ends of the ground lines GL1, GL2, the word lines WL10 to WL15 are connected alternately to memory cells at respective ends of the ground line GL1, GL2 and memory cells neighboring thereto. Therefore, the circuit of Fig. 5 can suppress effectively the rise of potential of respective ground lines GL1, GL2, compared to the case where the word lines WL10 to WL15 are not connected alternately to memory cells at respective ends of the ground lines GL1, GL2 and memory cells neighboring thereto. Fig. 6 is a schematic block diagram of a memory cell array of yet another embodiment of the invention. Referring to Fig. 6, the memory cell array includes memory cells M81 - M114 disposed in rows and columns. Each of the ground lines GL1 - GL4 is connected to the memory cells in the corresponding row, respectively. In all the embodiments already described, the word lines extend in a lateral direction. In the embodiment in Fig. 6, however, word lines extend substantially obliquely on the semiconductor substrate. Each oblique word line is connected to the memory cells which are aligned in a diagonal direction in the memory cell array. For example, the oblique word line WL20 is formed by connecting local word lines WL21 - WL24 to second polysilicon interconnections (or second polycide interconnections) 226 - 228. The local word lines WL21 - WL24 are connected to the corresponding memory cells M81, M92, M103 and M114, respectively. Other oblique word lines in the memory cell array shown in Fig. 6 are formed in the oblique direction on the semiconductor substrate in a fashion similar to the oblique word lines WL20. When the oblique word line WL20 is activated, the currents flow from the memory cells M81, M92, M103 and M114 to the corresponding ground lines GL1, GL2, GL3 and GL4, respectively. Also in this embodiment, the current flowing through one ground line upon activation of one word line (oblique word line) is reduced, so that the rise of potential of the ground line is prevented, and thus the destruction of data stored in the memory cells is prevented. In this embodiment, in a plurality of memory cells provided in the row direction and connected to one ground line, it is configured that one memory cell is connected to one word line. Therefore, a current flowing through one ground line is decreased as compared to the circuit shown in the other embodiments, and the rise of potential of one ground line is suppressed as compared to the circuit shown in the other embodiments. Fig. 7 is a layout showing the oblique word line WL20 on the semiconductor substrate shown in Fig. 6. Referring to Fig. 7, each of the local word lines WL21, WL22 and WL23 forming the oblique word line WL20 is formed of the first polycide layer on the semiconductor substrate. The local word line WL21 is connected to the local word line WL22 through the second polysilicon layer (or second polycide layer) 226. The local word line WL22 is connected through the second polysilicon layer 227 to the local word lines WL23. In the embodiments shown in Figs. 1 and 5 , as described hereinabove, the current flows from the memory cell to two ground lines upon activation of one word line. Therefore, the current flowing through one ground line is reduced by half, compared with the circuit shown in Fig. 10, so that the rise of potential of the ground line can be reduced. As a result, the destruction of data, which may be caused by the rise of potential of the ground line, can be prevented. Further, in the embodiment shown in Fig. 6, when one oblique word line is activated, the current flows from the memory cell to multiple ground lines. Therefore, the rise of potentials of the ground lines is prevented, and the destruction of data can be prevented. Although there have been described the examples in which the invention is applied to the SRAM, it should be noted that the present invention can be generally applied to various semiconductor memories including memory cells connected to ground lines. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.

Claims: A semiconductor memory device including a first memory cell (M63) and a second memory cell (M64) adjacent to said first memory cell, comprising: a semiconductor substrate; a first conductive layer (211, 212, 213, 214, 215, 216, 217) formed on said substrate; a first and a second access transistor (103, 104) in the first and second memory cell, respectively, each having a gate (211; 212; 213) formed from said first conductive layer; a first and a second driver transistor (101, 102) in the first and second memory cell, respectively, each having an active region (AR) formed in said substrate; an insulating layer formed on said first and second access transistor gates and on said first and second driver transistor active regions; said insulating layer having a first contact hole (CH3) and a second contact hole (CH2) therein to expose said first and second access transistor gates (212; 213), respectively, and a third contact hole (DC2) therein to expose said first driver transistor active region; a second conductive layer (221) formed on said insulating layer; a first word line (WL3)formed from said second conductive layer (221), said first word line (WL3)being connected to said first access transistor gate (212; 213) through said first contact hole (CH3); a second word line (WL2) formed from said second conductive layer (222) and said second word line (WL2; 222) being connected to said second access transistor gate through said second contact hole (CH2); and a ground line (GL2) said ground line being connected to said first driver transistor active region (AR) through said third contact hole (DC2). The semiconductor memory device according to claim 1, further comprising driver transistor gates (214 to 217), wherein said driver transistor gates (214, 215; 216, 217) in one memory cell (M63; M64) are formed such that their gate width extend perpendicular to the gate widths of said first or second access transistor gates (212, 213), respectively, in the same memory cell. The semiconductor memory device according to claim 1 or 2, wherein said first and second access transistor gates (212, 213) are formed from polycide.

Inventors: KOHNO YOSHIO, KURIYAMA HIROTADA, KOHNO, YOSHIO, KURIYAMA, HIROTADA
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1993
Main classification: H01L27
IPC codes: G11C5, G11C11