METHOD FOR FABRICATING MONOLITHIC CHIP CONTAINING INTEGRATED CIRCUITRY AND SELF-SUPPORTING MICROSTRUCTURE

Abstract: The invention comprises a method for fabricating a monolithic chip containing integrated circuitry as well as a suspended polysilicon microstructure. The inventive method comprises 67 processes which are further broken down into approximately 330 steps. The processes and their arrangement allow for compatible fabrication of transistor circuitry and the suspended polysilicon microstructure on the same chip.

Description: ? c J r °?„ SS n K5? ICATING M0N0 IT HIC CHIP CONTAINING INTEGRATED CIRCUITRY AN SELF-SUPPORTING MICROSTRUCTURE. Field of the Invention The invention pertains to techniques for fabricating microεtructures . More particularly, the invention pertains to a technique for fabricating sensors, and particularly accelerometers, in which a microstructure and resolving circuitry are embodied on the same chip. Background of the Invention The construction of microεensors on microchips is of great interest in many industries because of its potential to reduce size and cost of devices which require the sensing of environmental or other conditions. An accelerometer is just one example of a type of sensor which has wide application possibilities. Acceleration sensors are known for measuring force or mass or to operate control systems responsive to acceieraticr.. For instance, acceleration sensors may be used in automotive vehicles to deploy air bags responsive to a particular threshold deceleration rate of a vehicle. Acceleration sensors may also be used m the automotive industry as part of active suspension systems in which microcontrollers adjust suspension components responsive to the vertical acceieraticr. of tne wheels . An accelerometer comprises an acceleration- sensing element, or transducer, which is commonlv interfaced to resolving circuitry for prcducmσ a useful output signal from the output of the transducer. Though the term "accelerometer" is sometimes used to refer to the sensor (or transducer) itself, the term is used herein to denote a complete system including a transducer as well aε the resolving circuitry. Many commercially available accelerometers employ transducers comprising a mechanical or electromechanical element (e.g., piezoelectric, piezoresiεtive or strain gauge) . Acceleration sensing microstructures embodied on εiiicon chips have been suggested in the prior art. For instance, U.S. Patent No. 4,711,128 iεsued to Boura discloses an acceleration sensor formed by micromachining a fine monocryεtal wafer. The sensor comprises a flat mobile mass suεpended above the rest of the structure by means of two thin parallel strips situated on each side of tne mass Tne mass comprises at least one mobile capacitive plate wnich is disposed between two other capacitive plates which are net part of the suspended microstructure but are fixed en the structure. Tne mobile plates are charged to a voltage relative to the stationary- plates. When the sensor is subjected to an acceleration, the mobile plates move relative to the fixed plates causing a change in capacitance between the mobile plates and each of tne fixed plates The change in capacitance is observed oy observing the voitaσe between the mobile t>Iate and the fixed plates and iε a direct indication of the distance of movement of the fixed plate which, in turn, iε a meaεurement of the acceleration. U.S. Patent No. 4,705,659 iεsued to Bernstein et al . teaches a technique of fabricating a free¬ standing thin or thick structure such as an acceleration sensor, including the steps of providing a substrate, forming a layer of carbon on the subεtrate and depoεiting a film of polycryεtalline material over the layer of carbon. The sandwich structure iε heated in an oxidizing ambient to cause the oxidation of the carbon layer, leaving the polysilicon material as a free-standing film. The prior art, however, doeε not teach a monolithic accelerometer in which the acceleration εenεcr aε well as the resolving circuitry for producing a useful output are embodied on a single chip or a technique for making such a monolithic accelerometer. Thus, prior art accelerometers require a separate chip or other means containing circuitry for resolving the output of the sensor into a usable signal. Accordingly, it is an object cf the present •invention to provide a technique for fabricating a monolithic sensor. It iε a further object cf the present invention to provide a technique for fabricating a microchip embodying circuitry and a polysilicon micrcstr cture on a sinσle chit. It iε another object of the present invention to provide a technique for fabricating a microchip embodying BIMOS tranεiεtors and a suspended polysilicon sensor on a single chip. It iε one more object of the present invention to provide a technique for fabricating a monolithic accelerometer . Summary of the Invention The method disclosed herein for fabricating a monolithic sensor comprises over 300 individual steps... Some of the steps are esεentially standard εtepε well known in the art for fabricating BIMOS circuitry. Interleaved amongst these BIMOS steps are a large number of steps relating to the fabrication of the microstructure tranεducer . The fabrication method can be considered to comprise 67 proceεεes, each of which comprises one cr more cf the over 300 steps. The starting material is a p-doped substrate •having a thin layer of p-epi (epitaxial) thereover. The 67 processes are listed and briefly deεcribed below, with the "name" of each proceεs shown in upper case before the process description. 1. OXIDΞ 1-fcrm a blanket thermal oxide layer en the surface of the p-epi. 2. N-WΞ11 MASK - etch the oxide layer to define the desired σeoσraphv cf the n-weliε. 3. N-WELL IMPLANT - ion implant phoεphoruε into the p-epi to form n-wellε. 4. N-WELL DRIVE - diffuse the phosphorus into the p-epi layer to the desired depth. 5. OXIDE STRIP - remove the oxide layer in a buffered oxide etch bath. 6. PAD OXIDE - form a streεε relief thermal oxide blanket on the chip. 7. LPCVD NITRIDE DEPOSIT - depoεit a blanket nitride layer over the oxide layer by low preεεure chemical vapor depoεition. 8. THICK OXIDE MASK - etch through the nitride and oxide layerε to form a pattern for formation of a thick oxide layer . 9. P-FIELD MASK - form photoresist mask for upcoming implant of boron in selected areas. 10. P-FIELD IMPLANT - ion implant boron in the selected areaε. 11. N-FIELD MASK - form photoreεist mask for upcoming implant of arεenic in εelected areaε. 12. N-FIELD IMPLANT - ion implant arsenic in the εelected areas . 13. THICK OXIDE - form thermal oxide layer or. the bare silicon areaε between n-weiiε: this layer will act as a field threshold ad j ust to isolate transistors from each other. 14. NITRIDE STRIP - remove the nitride layer in a wet-etch process . 15. SACRIFICIAL OXIDE - form another thermal oxide layer. 16. BASE MASK - form photoresist pattern for upcoming implantation of boron to form transiεtor bases. 17. BASE IMPLANT - ion implant boron to form transiεtor baseε. 18. PLATE MASK - form photoresist pattern for implantation of field threshold adjust to follow in next step. 1 . PLATE IMPLANT - ion implant boron aε a field threshold adjust over the area in which the sensor transducer will be formed which will improve electrical isolation between portions of the senεor . 20. BASE DRIVE - diffuse boron implanted in steps 17 and 19 into the p-epi to desired depth. 21. EMIT MASK - create photoresist mask pattern for upcoming formation of transiεtor emitterε and n+ interconnect runners from the sensor to the circuitry. 22. EMIT IMPLANT - implant arεenic for transistor emitterε and n-÷- interconnect runners from the εenεor to the circuitry. 23. EMIT DRIVE - diffuse arsenic implanted in εtep 22 to deεired depth. 24. PVT IMPLANT - ion implant a blanket of boron to adjuεt field thresholds of MOS transistors. 25. SACRIFICIAL OXIDE STRIP - remove sacrificial oxide layer formed in step 15 in a buffered oxide etch bath. - 1 - 26. GATE OXIDE - form a blanket thermal oxide layer on the chip for forming MOS transistor dielectric. 27. GATE POLY DEPOSIT - deposit blanket layer of polysilicon by low pressure chemical vapor deposition for forming transiεtor gateε. 28. POCi 3 POLY DOPING - dope the polysilicon with P0C1- to make it conductive. 29. POLY MASK - etch polysilicon in dry plasma etch to form desired gate regions for transistors. 30. PSD MASK - form photoresiεt mask for forming P-type source and drain regions for MOS tranεistorε. 31. PSD IMPLANT - ion implant boron to form source and drain regionε for MOS tranεiεtorε. 32. LPCVD NITRIDE DEPOSIT - depoεit nitride blanket layer by low preεsure chemical vapor deposition: the nitride layer will act as a barrier to prevent BPSG (which will oe deposited in process 33) from diffusing into the underlying layerε. 33. BPSG DEPOSIT - depoεit boron phosphorus silicate glass (BSPG) in a plasma enhanced chemical vapor deposition process: the BPSG layer is a pianarization layer which, after it is reflowed, will reduce the severity cf the topography cf the surface cf the chip so that metal contacts can be formed en the surface at a later time. 34. SOURCE AND DRAIN DRIVE - diffuεe boron implanted in εtep 31 to desired depth, and εimultaneouεly reflow BPSG layer in a thermal proceεε. 35. LPCVD NITRIDE DEPOSIT - depoεit blanket layer of nitride by low pressure chemical vapor depoεition proceεε: this nitride layer will act as an etch stop at a later time when dielectrics are etched from the circuit area. 36. MOAT MASK - in sensor transducer area (hereinafter referred to as moat area) , etch away the nitride layer formed in step 35, the BPSG layer formed in step 33, the nitride layer formed in step 32, and the polysilicon layer formed in step 27, thus exposing the gate oxide in the moat area. 37. MOAT IMPLANT - ion implant more boron in the moat area to further increaεe field threεhold. 38. LTO DEPOSIT - depoεit low temperature oxide (LTO) layer for εurface passivation. 39. DENSIFICATION - densify LTO layer in a thermal process to slow down its etching. 40. LPCVD NITRIDE DEPOSIT - deposit a blanket layer of nitride by a low pressure chemical vapor deposition proceεε aε an etch εtop when removing LTO layer to be formed in step 41, and to accommodate future nitride-to-nitride sealing. 41. SPACER LTO DEPOSIT - chemical vapcr deposit a low temperature oxide spacer layer which will support the microstructure sensor until it is released into suεpenεion. 42. DENSIFICATION - densify LTO layer deposited in step 40 so as to slow down the etching process. 43. BUMPS MASK - etch small divots into upper surface of spacer LTO: divots will allow small bumps to form in bottom surface of microstructure sensor which will serve to reduce surface contact of microstructure with substrate during upcoming microstructure release etch. 44. ANCHOR MASK - selectively etch through spacer oxide, nitride and gate oxide layers down to the underlying n+ runners so as to form openings for anchors (or poεtε) from which polyεilicon microstructure sensor will be suspended. 45. ANCHOR IMPLANT - ion implant phosphorus so as to provide good ohmic contact of microsenεor anchorε to the underlying n+ runnerε. 46. SENSOR POLYSILICON DEPOSIT - low preεεure chemical vapor depoεit a blanket of polyεilicon from whicn εensor will be formed. 47. SENSOR POLYSILICON IMPLANT - ion implant phosphorous into polyεilicon layer to increase its conductivity. 48. SENSOR POLYSILICON RAMPED ANNEAL - anneal amorphous polysilicon tc form, by recryεtallizaticn, polyεilicon of deεired tensile stress. 49. BEAMS MASK - dry etch polysilicon into desired microstructure snape. 50. M03Ξ MASK - remove spacer oxide from all of tne chip except the moat area. 51. LTO DEPOSIT - chemical vapor deposit another blanket of low temperature oxide to protect microstructure sensor from upcoming platinum deposition. 52. MOSIN MASK - remove low temperature oxide layer formed in procesε 51, LPCVD formed in εtep 40, and low temperature oxide formed in step 38 from all cf the chip except the moat area. 53. CONTACT MASK - etch through nitride layer formed in step 35, BPSG layer formed in step 33, nitride layer formed in step 32, and gate oxide layer formed in step 26 so as to selectively expose openings on top surface of transiεtorε for contact with conductorε to be formed subsequently. 54. PLATINUM DEPOSIT - high vacuum sputter coat the chip with platinum so aε to allow for good ohmic contact between aluminum leads to be formed in subsequent step and contact surface. 55. PLATINUM SINTER - expose chip to high temperature to sinter platinum and allow it to react with silicon to form platinum suicide in contact areaε. 56. PLATINUM STRIP - remove all platinum which waε not converted to platinum εilicide (all platinum not in the contact areas) in a nitric hydrochloric acid bath. 57. SILICON CHROMIU!. SPUTTER - form blanket layer of silicon chromium for forming trimmable resistors. 58. METAL SPUTTER - form blanket layer of titanium tungsten (TiW) followed by a blanket of aluminum/copper (AlCu) out of which will be formed metal leads. 59. METAL MASK - etch AlCu and TiW layerε (two separate etches) to form metal leads in desired pattern. 60. THIN FILM MASK - etch silicon chromium to form desired resistors. 61. ALLOY - expose chip to high temperature such that TiW and AlCu react with the platinum suicide to form ohmic contact in the contact openings. 62. PLASMA OXIDE DEPOSIT - plasma enhanced chemical vapor depoεit a blanket of oxide which will serve to protect circuitry and εenεor from upcoming nitride etch, and will further be part of the final circuit area passivation. 63. PASSIVATION MASK - wet etch the plasma oxide to open a narrow channel around the perimeter of the senεor in preparation for upcoming formation of nitride-to- nitride εeal and also to expose bond pads in circuit area. 6 . PLASMA NITRIDE DEPOSIT - plasma enhanced chemical vapor deposit a nitride layer to set up a nitride-to-nitride εeal as an etch barrier around the sensor, and to act as part of the final circuit area passivation. 65. BACK ETCH - etch away all dielectrics from the back side cf the chit. 66. NTPAS MASK - etch away the nitride layer from the bond padε and the polyεilicon εensor area. 67. BEAM RELEASE MASK - etch low temperature oxide formed in step 51 and step 62 to open the sensor area and etch spacer oxide formed in step 41 to releaεe the εensor into its final suεpended condition. Brief Deεcription of the Drawing FIG. IA iε a top view of the εuεpended portion of an exemplary microεtructure which can be fabricated by the proceεε of the preεent invention. FIG. IB iε a εide view of the exemplary suspended microstructure portion of FIG. IA which can be fabricated by the method of the present invention. FIG. 2A is a top view of an exemplary εenεor which can be fabricated according to the present invention. FIG. 2B is a circuit diagram of exemplary resolving circuitry for an accelerometer fabricated according to the present invention. FIG. 3 is a cross-sectional view of the circuit region of an exemplary chip during a first stage of the fabrication method of the present invention. FIG. 4 is a croεε-εectiona view of the εenεor region of the εenεcr region of an exemplary chip during a second stage cf the fabrication method of the present invention. FIG. 5 iε a croεs-sectional view of the circuit region of an exemplary chip during a third εtage of the fabrication method of the present invention. FIG. 6 is a crosε-sectional view of the sensor region of the senεor region of an exemplary chip during a fourth stage of the fabrication method of the present invention. FIG. 7 iε a croεε-sectional view of the senεor region of the sensor region of an exemplary chip during a fifth stage of the fabrication method of the present invention. FIG. 8 is a croεε-εectional view of the sensor region of the sensor region of an exemplary chip during a sixth stage of the fabrication method of the present invention. FIG. 9 is a crosε-εectional view of the εenεor region of the εensor region of an exemplary chip during a seventh stage cf the fabrication method of the present invention. FIG. 10 is a crosε-εectional view of the sensor region of the εensor region of an exemplary chip during an eighth stage cf the fabrication method of the present invention. FIG. 11 is a crosε-sectional view of the εenεor •region of the sensor region cf an exemplary chip during a ninth stage cf the fabrication method of the present invention. FIG. 12 iε a cross-sectional view of the εenεcr region of the senεcr region of an exemplary chip during a tenth εtage of the fabrication method of the present invention. FIG. 13 is a crosε-εectional view of the εenεor region of the sensor region of an exemplary chip during an eleventh stage of the fabrication method of the present invention. FIG. 14 is a cross-sectional view of the senεor region of the εenεor region of an exemplary chip during a twelfth εtage of the fabrication method cf the present invention. FIG. 15 is a croεε-sectional view of the sensor region ^ of the sensor region of an exemplary chip during a thirteenth stage of the fabrication method of the present invention. FIG. 16 iε a croεε-εectional view of the sensor region of the senεor region of an exemplary chip during a fourteenth εtage of the fabrication method of the preεent invention. FIG. 17 iε a croεε-εectional view of the sensor- region of the sensor region of an exemplary chip during a fifteenth stage of the fabrication method of the present invention. FIG. 18 is a crosε-εectional view of the circuit region of an exemplary chip during a εixteenth εtage of the fabrication method cf the present invention. FIG. 19 is a cross-sectional view of the sensor region of the sensor region of an exemplary chip during a seventeenth εtage cf the fabrication method of the present invention. FIG. 20 is a crosε-εectional view of the sensor region of the sensor region of an exemplary chip during an eighteenth stage of the fabrication method of the present invention. FIG. 21 is a croεε-εectional view of the εenεor region of the εenεor region of an exemplary chip during a nineteenth stage of the fabrication method of the present invention. FIG. 22 is a crosε-εectional view of the εensor region of the sensor region of an exemplary chip during a twentieth εtage of the fabrication method of the present invention. FIG. 23 is a croεε-εectional view of the εensor region of the sensor region of an exemplary chip during a twenty-first εtage of the fabrication method of the present invention. Detailed Description of a Preferred Embodiment of the Invention U.S. Patent No. 07/569,080 filed August 17, 1990 and entitled MONOLITHIC ACCELEROMETER is assigned tc the same aεsignee aε thiε application and the diεcloεure cf that application is incorporated herein by reference. That patent application discloses a monolithic accelerometer which can be fabricated by the method disclosed herein. Further, U.S. Patent Application No. 07/872,037 entitled METHOD FOR FABRICATING MICROSTRUCTURES filed on April 22, 1992 and aεεigned to the same aεεignee aε the present application discloses an improvement on the method disclosed herein relating to a method for preventing the suspended microstructure from becoming damaged or stuck to the εubstrate during the fabrication processes. The disclosure of that patent application is also incorporated herein by reference. FIGS. IA and IB are top and side views, respectively, of the εuεpended portion 10 of an exemplary microεtructure which may be fabricated by the method of the present invention. Aε εhown in the drawings, the suspended central beam 12 has a plurality of suspended arms 14 extending tranεversely therefrom. The beam 12 is supported at opposite ends from support beams 16 and 18. Support beams 16 and 18 are suεpended above the silicon substrate by anchors 20, 22, 24 and 26. FIGS. IA and 13 show only the suεpended portion of the microεtructure. However, in an actual commercially usable device, the microεtructure would alεo compriεe fixed components. FIG. 2A, for inεtance, εhowε a top view of the εenεor portion cf an exemplary accelerometer. Aε can be seen, the arms 14 of the microεtructure are poεitioned adjacent and parallel tc fixed arms 28 and 29. Each of arms 28 and 29 is also suspended above the substrate from anchors at one end thereof . Nevertheless, they are generally considered to be fixed because they will not move significantly under accelerative force since the suspended portions of arms 28 and 29 are relatively short. The suspended portion, including arms 14, electrically comprise a firεt node. Fixed armε 28 are electrically coupled together to a second node and fixed arms 29 are electrically coupled together to a third node. Fixed armε 28 form the first electrode of a first capacitor and fixed arms 29 form the first electrode of a second capacitor. Mobile arms 14 form the second electrodes of both the firεt and second capacitors. When the device is subjected to an acceleration, support arms 16 and 18 flex under the accelerative force causing mobile arms 14 to move relative to fixed arms 28 and 29. Accordingly, under accelerative forceε, the distance between the mobile arms and the adjacent fixed arms changes, resulting in a change in capacitance between each mobile arm and the adjacent fixed armε. The change in capacitance is a direct indication of the accelerative force. The senεor is electrically connected to resolving circuitry which receives the voltage differential between the mobile arms and the fixed armε. FIG. 2B iε a circuit diagram of exemplary resolving circuitry for force balancing the sensor cf FIG. 2A and using the force-balancing feedback signal on line 31 as a measurement of the acceleration. A more detailed description of the circuitry and the sensor can be found in the aforementioned U.S. patent application No. 07/569,080. Using the fabrication method of the present invention, the sensor of FIG. 2A and the circuitry of FIG. 2B can be embodied in a single chip, thus reducing the size and cost of the accelerometer. The fabrication method of the preεent invention combines processeε for fabricating BIMOS circuitry and for fabricating suspended microstructures in a mutually compatible manner. The overall method comprises approximately 330 individual stepε . Many of the approximately 330 individual stepε are parts of processes which are well known in the art. For instance, the procesε of forming a photoreεiεt maεk by meanε of photolithography iε well known in the prior art and compriεeε εix individual εtepε . The individual steps of the present invention can be considered to comprise 67 processes. Some of the 67 procesεeε are εtandard proceεεeε which are known in the art . The present invention lies in a novel combination of processes so aε to fabricate a monolithic εenεor aε well aε in the fact that some of the processes are novel in and cf themselves. On an even broader level, the overall method can be considered to comprise 20 taε s, each task compriεinσ one cr more cf the processes. The detailed diεcuεεion of the invention herein iε divided into 20 taεk headings. The section under each taεk heading is further divided into one or more processes. Where necesεary, the individual steps of a process are discusεed. However, aε previouεly noted, many of the individual εtepε are well known in the prior art and thuε are not deεcribed in great detail. Further, not all steps or procesεeε are illustrated in distinct FIGS, in- order to avoid obfuscation of the invention. STARTING MATERIAL The εtarting material for the method of the present invention iε a p-doped εilicon subεtrate having a thin p-doped epitaxial layer thereover of approximately 30 micronε in thickneεε. TASK 1 : N-WELL IMPLAN . This taεk involveε implanting into the εubεtrate the n-wellε within which the tranεistors will be formed. It compriseε proceεεes 1-5. PROCESS 1 : OXIDE 1 A thermal oxide is formed on the surface cf the chip by conventional thermal meanε. In particular, the chip is heated to approximately 1000°C in an oxygen ambient environment, causing the silicon on . the surface cf the chip to oxidize, forming a' thermal oxide, SiC . layer. The depth cf oxidation is controlled by the temperature and exposure time. This layer iε formed to a depth of approximately 3600 angstroms. PROCESS 2: N-WELL MASK This procesε involves patterning the oxide layer formed in εtep 1 into the deεired pattern of n-wellε on the subεtrate. Thiε proceεε comprises standard photolithography stepε followed by etching of the oxide layer in a buffered oxide etch (hydrofluoric acid) bath. In particular, photolithography compriεeε the steps of (1) coating the chip with a blanket layer of organic photoresist, (2) placing a mask in the form of the desired n-well pattern over, but not in contact with, the photoresist, (3) accurately aligning the mask over the chip, preferably in a stepper, so that all layerε are formed in proper position relative to all other layerε, (4) εhining a light of εpecified wavelength through the maεk onto the photoresist, causing the portions of the photoresiεt expoεed under the maεk to be developed while the portions occluded by the mask are not developed, (5) removing the mask, and (6) spraying the chip with a chemical wash which washes away the ' developed portion of the oxide layer. After the six photolithography steps, the underlying oxide layer is exposed beneath the developed away portion of the photoresist. The chip is then dipped in a buffered oxide etch bath of hydrofluoric acid which etches through the exposed portion of the oxide layer but doeε not affect the portion of the oxide layer which iε still covered by photoresist. Commonly, the photoresiεt layer would be removed immediately after the etching of the underlying layer. In the present proceεε, however, the photoreεiεt iε not yet removed for reaεonε which will be explained shortly. PROCESS 3: N-WELL IMPLANT In this procesε, phoεphoruε iε blanket depoεited on the chip to a concentration of 5.0E12/cm 2 . The phosphorus iε implanted into the substrate only in the areas defined by the thermal oxide mask. The phosphorus is depoεited in a εtandard ion implantation proceεε in which the chip iε bombarded with a high energy beam of phosphorus particles (n-type particles). In the preferred embodiment, the particles are accelerated to approximately 100 kiloelectron volts (KeV) cf energy. The photoresiεt maεk which waε formed in proceεε 1, but not yet removed, serves as an additional protective mask in thiε n-weli implant proceεε. After the phoεphoruε iε deposited, the photoresiεt can be εtripped away. This can be done by either dipping the chip in a sulfuric acid etch bath or by dry plasma stripping. In the preferred embodiment of the invention, it iε done in an acid etch. PROCESS 4: N-WELL DRIVE At the completion of proceεε 3, the phoεphoruε implanted in proceεε 3 is diffused into the substrate only to a very shallow depth. The phosphorus now must be diffused (or driven) into the substrate to the desired depth. The phosphorous can be diffused deeper into the subεtrate in a thermal process. In the preferred embodiment of the invention, the chip is exposed to approximately 1250°C for approximately 7 hours in an ambient environment including a small amount of oxygen (to allow for some oxidation) as well aε a gaε . The depth of diffuεion can be controlled by both the duration and temperature of the proceεε. PROCESS 5: OXIDE STRIP The n-wellε having been implanted and driven to the desired depth, the protective oxide layer formed in process 1 can now be removed. The chip is dipped into a buffered oxide etch bath. Since the photoresist mask has been removed, ail remaining oxide is etched away leaving the bare εilicon with n-wellε. TASK 2: THICK OXIDE This taεk relates to field threshold adjust in order to improve surface isolation between the components which will be formed in the chip. It comprises processes 6-14. Thick oxide will be formed around essentially all individual transistors to increase εurface isolation. However, the dopant level must be increaεed beneath the thick oxide regionε to reduce surface leakage. Accordingly, arsenic will be implanted in the regions of the n-wells which will be covered by thick oxide (hereinafter n-field regions) to increase n-doping. In the other areas of the chip, boron will be implanted under the regions where the thick oxide will be formed (hereinafter p-field regions) in order to increase p-doping in thoεe areaε . PROCESS 6: PAD OXIDE In thiε proceεε, a thin layer of thermal oxide (approximately 500 angstroms) iε formed by oxidizing the surface of the chip as previously deεcribed with respect to procesε 1. This layer of oxide iε formed in order to protect the silicon from the nitride which will be deposited in process 7. Nitride will damage bare silicon. PROCESS 7: LPCVD NITRIDE DEPOSIT In this proceεε, a layer of approximately 1200 angεtromε of εilicon nitride is deposited in a standard low presεure chemical vapor depoεition proceεε. In low preεεure chemical vapor deposition, the chip is placed in a low temperature furnace containing an ambient gas. In the caεe of a nitride deposition step, the ambient would include NH_ and SiH_Cl 2 . The vaporized particles deposit themselves onto any available surface such aε the substrate surface. PROCESS 8: THICK OXIDE MASK In thiε proceεε, a photoresist maεk iε formed using conventional photolithography as previously deεcribed with reεpect to proceεε 2. The maεk is patterned to define the field inactive regions (i.e., n-field and p-field regionε) of the chip where a thick layer of oxide is to be grown in an upcoming proceεε for increasing surface iεolation. Once the photoreεiεt maεk iε formed, the nitride layer iε etched by a conventional plaεma etch. The photoreεist maεk iε removed and the pad oxide is then etched in a conventional buffered oxide etch. Only the portions exposed through the nitride laver are etched awav. PROCESS 9: P-FIELD MASK Since p-fields and n-fieldε uεt be doped with different i puritieε, a conventional photoresist maεk iε formed defining only thoεe areas exposed through the thick oxide mask in which p-field regions are to be formed. PROCESS 10: P-FIELD IMPLANT In this procesε, boron particleε (p-type particles) are implanted in the p-field regionε exposed under the mask of photoresist to a concentration of 5.5E13/cm 2 at 50 KeV by conventional ion implantation such as waε described with respect to procesε 3. After the boron is implanted, the photoresiεt mask is εtripped away. PROCESS 11: N-FIELD MASK Thiε proceεε iε similar to procesε 9 except the maεk defines the n-field regions rather than the p-field regionε of the field area. PROCESS 12: N-FIELD IMPLANT In this process, arεenic is deposited to a concentration of 4.0Ell/cm by an ion implantation process to form the desired n-field region ' s in the n-weliε.' In at leaεt one preferred embodiment, the particles are accelerated to 100 KeV. The photoresist iε then εtripped away. FIG. 3 illustrates the state of the circuit region of the chip after the completion of the n-field implant of proceεε 12, but before the photoresiεt maεk iε removed. The p-doped εubεtrate aε well aε the p-epi layer are εhown collectively aε 30. An exemplary n-well formed in TASK 1 iε εhown at 40. The pad oxide layer (formed in proceεε 6 and patterned in proceεs 8) and the nitride layer (formed in process 7 and patterned in proceεs 8) are shown collectively at 13. The n-field photoreεiεt mask formed in process 11 is shown at 11 wherein openings 11a define the n-field regions. The actual p-fields and n-fieldε, however, are not repreεented in thiε FIG. εince they have not been fully formed yet. In particular, they have not been diffused to the desired depth yet. PROCESS 13 : THICK OXIDE In this process, a blanket thick oxide layer of approximately 14,900 angstroms is formed by thermal oxidation such as was described with respect to proceεs 1. The oxide formed in thiε proceεs will only form where the bare εilicon iε exposed under the etched nitride layer formed in procesεes 7 and patterned in ε. Since the nitride formed in process 7 and patterned in proceεε 8 exposed the inactive regions of the substrate, the thick oxide forms only in those regions. The thick oxide improves the electrical isolation of the transistorε which will be formed on the chip from each other and from the aluminum leads which will be formed. The thick oxide layer is a field threεhold adjuεt layer. Thiε thermal process also serves to diffuse the boron and arsenic implanted in processes 10 and 12, respectively, thus completing the formation of the p-field and n-field regions. PROCESS 14: NITRIDE STRIP In thiε proceεε, the chip iε dipped in a phosphoric acid bath to remove all remaining nitride deposited in process 7. The chip is then dipped in a buffered oxide etch bath to remove the remaining oxide which was formed in procesε 6. The buffer oxide εtrip, of course, will also εtrip away εome of the thick oxide layer formed in proceεε 13. However, that layer is so thick that the vast majority of that layer remains after the oxide strip. TASK 3: FORM BASES OF BIPOLAR TRANSISTORS AND PARTIALLY FORM SOURCES AND DRAINS OF PMOS TRANSISTORS This task comprises processes 15-20. In this task, the bases cf the bipolar transistors are formed. Since the sources and drains of the PMOS transistorε have similar doping requirements, they are also partially formed in this task. The more shallow source and drain diffusions necessary to completely form the source and drains of the PMOS tranεistors are formed later during TASK 7. PROCESS 15: SACRIFICIAL OXIDE In thiε proceεε, a 850 angεtrom thick layer of sacrificial oxide is grown on the chip by thermal oxidation. This εacrificial layer will serve to prevent channelling in the device aε well as prevent damage from occurring in the upcoming base implant. PROCESS 16: BASE MASK In thiε proceεs, a mask of photoresiεt iε formed on top of the sacrificial oxide layer to define the desired bipolar transiεtor baεeε and PMOS εources and drains by standard photolithography εtepε as previously described. The sacrificial oxide layer is then etched into the tranεiεtor base pattern in a buffered oxide etch bath also aε previouεly deεcribed. PROCESS 17: BASE IMPLANT In this process, p-type particles (boron particleε) are ion implanted into the substrate in the pattern dictated by the mask formed in procesε 16. After the implantation, the photoresiεt iε stripped away. PROCESS 18: PLATE MASK In thiε process, another photoresist mask is formed by standard photolithography. The mask is formed so as to protect the circuitry area but expose the moat area of the chip. PROCESS 19: PLATE IMPLANT In thiε proceεε, boron iε ion implanted in the εenεor area through the maεk formed in procesε 18. Thiε implantation createε a more heavily p-doped area (or plate) in the moat region. The plate serves as a field threshold adjust to improve isolation between the arms of the sensor . The photoresiεt iε εtripped away after the plate implantation. PROCESS 20: BASE DRIVE In this proceεε, the boron implanted in proceεs 17 to form the baεeε cf the bipolar transistors and to partially form the sources and drains of the PMOS transistors is diffused into the n-wells to the deεired depth in a high-temperature diffusion procesε such as previously described with respect to process 4. The boron implanted in step 19 is also diffused at this time. FIG. 4 illuεtrateε the εtate of the chip and particularly the moat region, after the completion of process 20. As before, the p-doped subεtrate aε well aε the p-epi layer are shown collectively aε 30. The plate layer formed in process 19 is shown at 32. Dotted vertical line 34 is the dividing line between the sensor area (or moat area) and the circuit area of the chip. As can be seen in that figure, the plate appears only in the moat area. The sacrificial oxide layer formed in process 15 iε shown at 36 and covers both the circuit area and the εenεor area. An exemplary thick oxide region formed in taεk 2 (processes 7-14) is εhown at 38. Thick oxide region 38 in FIG. 4 is part of a ring of thick oxide (formed in task 2) which completely surrounds the moat area. Of course, thick oxide has been deposited in other regions as well. An exemplary n-well region in the circuit region iε illuεtrated at 40. A p-field formed in εtep 10 beneath thick oxide region 38 is shown at 42. TASK 4: FORM CONDUCTORS FROM MOAT AREA TO CIRCUIT AREA AND BIPOLAR TRANSISTOR EMITTERS This task comprises processes 21-23. In this task, the emitters for the bipolar transistors are implanted. Further, n+ runners between components of the senεor and the circuitry are also formed. These conductors are essentially long emitter regions and, thus, can be formed during the same processes as the transistor emitters. PROCESS 21: EMIT MASK A layer of photoresist is deposited and patterned to define the bipolar transistor emitterε as well aε the n-t- runnerε (conductors) from the sensor area to the circuit area. These runnerε will electrically connect the polyεilicon εenεor to the BIMOS circuitry. PROCESS 22: EMIT IMPLANT In this procesε, arsenic is ion implanted to a conceennttrraattiioonn ooff 66..1188EE1155//ccmm' at 150 KeV to form the emitters and n+ runnerε PROCESS 23: EMIT DRIVE In this process, the arsenic is diffused in to the desired depth and concentration in a high temperature diffusion procesε. FIG. 5 shows the circuit region of the chip at the completion of procesε 23. Reference numeral 17 denotes the base regionε of the bipolar tranεistors and partially formed source and drain regions of the PMOS transistors formed in processes 16, 17 and 20. Reference numeral 19 denotes the emitter regionε formed -**» in processes 21, 22 and 23. Reference numeral 38 denotes the thick oxide layer formed in proceεses 8 and 13. Reference numeral 23 denotes an exemplary n-field formed in processes 11, 12 and 13. Finally, reference numeral 42 denotes an exemplary p-field formed in procesεeε 9, 10 and 13. TASK 5 : FORM GATE OXIDE REGIONS Thiε task comprises processeε 24-26. In thiε task, the dielectric of the MOS tranεiεtorε is formed. PROCESS 24: PVT IMPLANT In thiε proceεε, boron iε implanted to a concentration of 4.5Ell/cm 2 at 50 KeV. Thiε blanket layer of boron is a threshold adjust for the PMOS transistors. In the embodiment of the invention for manufacturing the monolithic accelerometer shown in FIGS. IA, IB, 2A and 2B and disclosed in U.S. Patent application No. 07/560,080, the circuitry comprises no NMOS transistors. Accordingly, the boron can be deposited in this step without benefit of a maεk. Although the boron is blanket depoεited on the chip, it only significantly affects the channel regions since the other regions of the chip are already so heavily doped that this relatively small addition of boron will not significantly affect the other regions. The additional steps necessary to adapt this process to a device also having NMOS transistors, however, would be obvious to a person of ordinary skill in the relevant art. PROCESS 25: SACRIFICIAL OXIDE STRIP In this procesε, the sacrificial oxide layer which was formed in process 15 is now stripped away in a buffered oxide etch bath. PROCESS 26: GATE OXIDE In this process, a thermal oxide is grown on the chip to a depth of 725 angεtromε . Thiε layer will comprise the capacitive oxide beneath the gates of the MOS tr ' ansiεtorε . FIG. 6 illustrates the moat area of the chip after the completion of process 26. As shown in FIG. 6, at this point, the moat area has three layers above substrate 30. They are plate layer 32, n+ conductors 44 and gate oxide blanket layer 46. TASK 6: FORM BIMOS GATES This taεk comprises processes 27-29. In this task, the polysilicon gateε of the BIMOS tranεiεtors are formed. PROCESS 27: GATE POLYSILICON DEPOSIT In this process, a blanket layer of polysilicon is deposited on the chip. Polysilicon deposition techniques are well known in the art. For instance, the polyεilicon may be deposited in a chemical vapor depoεition technique involving exposing the chip in a high temperature furnace with an ambient containing vaporized silicon hydride (SiH.). The silicon hydride decomposes in the high temperature and deposits onto all available surfaceε, i.e., the chip. In the preferred embodiment of the preεent invention, the polyεilicon iε deposited to a depth of 5500 angstroms. This blanket of polyεilicon will be formed into the gateε of the MOS tranεiεtors in upcoming processes . PROCESS 28: OCl 3 POLYSILICON DOPING In this process, the polysilicon deposited in process 27 is highly doped (20 ohms/εq) with POC1--. in order to increase its conductivity. In the preferred embodiment of the invention, the polysilicon is doped in a depoεition cycle of a diffusion process in which the chip is placed in a high temperature furnace with ambient POCl_ . Although similar to a chemical vapor deposition technique, this process is not considered a chemical vapor deposition because, instead of depositing a new layer of material, this procesε dopeε the prior existing layer with an impurity. PROCESS 29: POLYSILICON MASK In this proceεs, a photoresiεt layer iε formed over the polysilicon and patterned into the desired gate pattern. The polyεilicon is then etched in a dry plasma etch to form the gate regions. FIG. 7 illustrates the sensor area of the chip after completion of process 29. In addition to forming the gate regionε, an island of gate polysilicon 48 is also formed over the moat area. This polysilicon iεland will act as an etch stop when removing BPSG in a subsequent procesε . Near the end cf the fabrication method, a process will remove all- gate polysilicon from the sensor region except for a narrow ring. TASK 7: FORM SHALLOW P-TYPE SOURCE AND DRAIN REGIONS FOR BIMOS TRANSISTORS Thiε task comprises processeε 30 and 31, in which the source and drain regions of the PMOS transiεtorε are formed. PROCESS 30: P-TYPE SOURCE AND DRAIN MASK In this procesε, a photoresist maεk is formed by standard photolithography steps to define the source and drain regionε of the PMOS transistors. PROCESS 31: PSD IMPLANT In this procesε, boron (p-type) is ion implanted to a concentration of 1.5E13/cm 2 at 40 KeV. The photoresiεt is stripped subsequent to the boron implantation. TASK 8: BPSG PLANARIZATION At this εtage in the fabrication of the device, the εurface topography of the chip is relatively severe (i.e., rough). In subsequent processes, it will be necessary to form metal leads on the surface of the chip. It is preferable that the metal be deposited on a relatively smooth surface. Accordingly, in proceεses 32-35, a bor.ophosphosilicate glasε (BPSG) , which eεsentially comprises SiO, with small amounts of boron and phosphorus, is deposited and reflowed to provide a smoother surface for the metallization process. Otherwise, the severe topography of the surface of the chip would make it difficult to depoεit metal leads without cracking. PROCESS 32: LPCVD NITRIDE DEPOSITION In this process, a 200 angstrom thick layer of nitride is deposited on the surface of the chip by low-pressure chemical vapor deposition. This nitride layer protects the underlying gate oxide from the BPSG layer which will be deposited in process 33. The nitride prevents the BPSG from diffusing into and beyond the gate oxide layer. PROCESS 33: BPSG DEPOSITION In this proceεs, a 5500 angstrom thick layer of borophosphosilicate glasε is plasma enhanced chemical vapor depoεited. The BPSG layer will be reflowed to provide a planarization layer for reducing the severity of the topography such that metal interconnectε and contacts can be depoεited subsequently with reduced risk of cracking. The BPSG will be reflowed to planarize the chip εurface in proceεs 3 . PROCESS 34: SOURCE AND DRAIN DRIVE In this process, the boron deposited as source and drain regions is diffused to the desired depth and concentration. In at least one preferred embodiment, the chip is exposed to 1000°C for approximately 2 hours. This process is actually part of both task 8 (planarization) and task 7 (formation of the source and drain regions). This process is performed subsequent to the BPSG deposition to accomplish source/drain drive as well as BPSG reflow (i.e., melt and resolidify the BPSG so it forms a smooth planar surface upon which the metal interconnects can be formed) . PROCESS 35: LPCVD NITRIDE DEPOSITION In this process, another 200 angstroms of nitride are deposited over the BPSG layer. This nitride layer will act as an etch stop in the circuit area when it becomes necessary to wet etch through dielectrics deposited for the purposes of constructing the sensor. Dielectrics are commonly laid down as a blanket and thus the sensor dielectrics will also be formed in the circuit area at some point. Accordingly, they must be removed from the circuit area. This nitride layer will act as an etch stop when it becomes necessary to remove those dielectrics. FIG. 8 illustrates the condition of the sensor area of the chip after the completion of process 35. The nitride layer deposited in process 32 is shown at 50, the BPSG layer formed in process 33 is shown at 52, and the nitride layer formed in process 35 is shown at 54. TASK 9: CLEAR MOAT AREA As can be seen from FIG. 8, at this stage in the fabrication method of the present invention the moat region is covered with a number of layers of dielectric which were deposited for BIMOS circuitry formation. In processes 36 through 40, the unnecessary dielectrics will be removed from the moat area and the surface concentration of the p-regions will be increased to reduce the probability of surface leakage between the n+ runnerε. Further, after the moat area is cleared of all BIMOS dielectrics and its dopant concentration has been increased, several dielectric layers for the moat are formed. PROCESS 36: MOAT MASK In thiε process, a photoresist layer is deposited and patterned to expose only the moat region. Then, the nitride layer deposited in process 35 is removed in a dry etch process, the BPSG planarization layer deposited in procesε 33 is removed in a wet etch process, the nitride layer formed in process 32 is removed in another dry etch process and, finally, the polysilicon layer deposited in procesε 27 iε removed in a dry etch procesε. At this point, the gate oxide iε now exposed in the moat region. PROCESS 37: MOAT IMPLANT In this process, more boron is ion implanted in the moat area (the remainder of the chip is still protected by the photoresist) . The boron is implanted to a concentration of 5E12/cm 2 at 50 KeV. This boron implantation procedure serves the same function as the plate implant procedure of procesε 19, i.e., as a field threshold adjust to increase componentry electrical isolation. The process is split into two separate implantations because, at this point, the initial plate implant has been substantially depleted from the surface due to exposure to several thermal operations and the segregation nature of boron. FIG. 9 shows the chip after the completion process 37. As can be seen, the moat area is exposed down to the gate oxide 48. PROCESS 38: LTO DEPOSITION In this process, a 2,000 angstrom thick layer of low temperature oxide iε deposited over the chip. This increases the total oxide thickneεε from about 600 angεtromε to about 2600 angεtroms in the field regions and ensures adequate εurface paεεivation. In thiε proceεε, the oxide iε not formed by a thermal process as previously deεcribed wherein the exposed εilicon surfaces oxidize. Instead, in this process, the oxide is deposited in a chemical vapor deposition type procesε. Essentially, the chip is placed in a low temperature furnace with a εilicon compound and oxygen ambient. The ambient oxide precipitateε onto the εurface of the εilicon. Thiε proceεε does not uεe up any εilicon on the εubεtrate. PROCESS 39: DENSIFICATION The low temperature oxide deposited in process 38 iε now denεified to slow down its etching. Esεentially, the chip iε placed in a high temperature furnace for a εpecified period to denεify the oxide. PROCESS 40: LPCVD NITRIDE DEPOSITION A 1200 angstrom thick layer of nitride is deposited over the denεified low temperature oxide.' This layer will act as an etch stop with respect to the etching of another low temperature oxide layer which will be deposited over thiε nitride layer in proceεε 41. Thiε nitride layer will alεo permit the nitride-to-nitride εealing diεcuεεed in Taεk 19. FIG. 10 shows the chip after the completion of procesε 40. Aε shown therein, a layer of low temperature oxide 56 has been depoεited followed by a layer of nitride 58. TASK 10: FORM SPACER OXIDE The microstructure should be able to withεtand normal operating conditions after the complete chip has been fabricated and packaged. For instance, the monolithic accelerometer which is contemplated for fabrication by the method of the present invention is expected to withstand accelerative forces on the order of lOOg. Nevertheless, during fabrication, the microstructure undergoes proceεεeε and iε expoεed to environmental conditions which are εignificantly more harεh than it iε likely to encounter during operation. Thus, precautionary meaεureε muεt be built into the microεtructure aε well as the method for fabricating the microstructure in order tc reduce the possibility of damaging the microstructure during fabrication. The εpacer oxide εerves two functions. Firεt, the poivεilicon microεtructure will be depoεited and formed over the spacer oxide and then the spacer oxide will be etched away from underneath the microstructure leaving it suεpended. The εpacer oxide is not removed until eεεentially the very end of the method. Accordingly, a εecond function of the spacer oxide is to rigidly εupport the εuεpended microstructure which otherwiεe might be damaged when exposed to the conditions and proceεεeε of fabrication. The formation of the spacer oxide comprises process 41-43. PROCESS 41: SPACER OXIDE DEPOSITION. In this procesε, the εpacer low temperature oxide (LTO) which will support the microstructure is deposited by chemical vapor depoεition. Thiε layer iε grown to approximately 16,000 angstroms. PROCESS 42: DENSIFICATION In this proceεε, the chip iε expoεed to a high temperature for an extended period of time in order to densify the spacer LTO layer to slow down itε etching. Thiε will allow for much more accurate etching of the εpacer oxide. PROCESS 43 : BUMPS MASK In this proceεε, a photoresist layer is deposited over the spacer LTO and patterned to form small openings interspersed in the sensor area. The spacer oxide iε then etched in a buffer oxide etch bath. The chip iε only expoεed to the buffer oxide etch for a limited period of time εo that only εmall divotε will be taken out of the top surface cf the spacer LTO rather than etching completely through the spacer LTO down to the underlying nitride layer. Thus, when the microεtructure iε formed over the εpacer LTO, there will be εmall bumpε in itε bottom εurface adjacent to the poεition of the divotε in the εpacer oxide. Theεe bumpε, will serve to minimize surface area contact of the microεtructure to the chip during and after removal cf the εpacer oxide. During and after the etch for removing the εpacer oxide to leave the microεtructure εuspended, the relatively delicate microstructure can be bent such that it comeε in contact with the underlying subεtrate. Thiε ' iε undeεirable since the microεtructure haε a tendency to εtick to the εubεtrate. By placing small bumpε in the bottom εurface of the microεtructure, if and when the bottom εurface cf the microstructure comes in contact with the subεtrate, only the bumps will contact the εurface thereby minimizing the contact surface area and the likelihood of stickinσ. FIG. 11 shows the chip after the completion of process 43. Aε shown therein, a thick layer of spacer oxide 60 haε been depoεited over the entire chip and small divots such as divot 61 have been formed in itε upper surface. TASK 11: ANCHOR FORMATION In the exemplary accelerometer illustrated in FIGS. IA, IB and 2A, the microstructure iε suspended from four anchors, and the fixed arms are individually anchored to the substrate in the same manner. Processes 44 and 45 relate to the preparation for forming the anchors of the microεtructure. PROCESS 44: ANCHOR MASK In this process, a photoresiεt maεk is formed defining the anchorε from which the polysilicon microstructure will be suεpended. The spacer oxide, nitride, and additional underlying oxides are dry etched, thus exposing the n+ runnerε beneath, such as runner 44 (see FIG. 12). PROCESS 45: ANCHOR IMPLANT In this procesε, phosphorous is implanted to a concentration of 4.0Ξ15/cm 2 in an ion implantation proceεε at 30 KeV. The phoεphorouε is implanted so as to allow the polysilicon anchors, when formed, to make good ohmic contact to the underlying n+ runner, e.g., 44. The phosphorouε implantation increaεeε the phoεphorous concentration at the polysilicon/silicon interface, encouraging uniform recrystallization at the anchor point and reducing anchor resistance. FIG. 12 shows the chip after the completion of step 45, including exemplary anchor opening 59. TASK 12: POLYSILICON MICROSTRUCTURE FORMATION Procesεes 46 - 49 relate to the formation of the suspended microstructure. However, as noted earlier, the microεtructure will not be suεpended, but will be supported by the spacer LTO, until esεentially the end of the fabrication method. PROCESS 46: SENSOR POLYSILICON DEPOSITION In thiε proceεε, a 20,000 angεtrom thick layer of polyεilicon iε depoεited over the εpacer oxide in a low preεεure chemical vapor deposition procesε. Thiε iε the polyεilicor-. layer from which the microεtructure will be formed. A low deposition temperature is used tc produce a partially amorphous film. PROCESS 47: SENSOR POLYSILICON IMPLANT In thiε procesε, the microεtructure polyεilicon iε made more conductive by ion implanting phosphorous. PROCESS 48: POLYSILICON RAMPED ANNEAL When the polyεilicon iε depoεited, it is subεtantially amorphouε. In order to form the polyεilicon to the desired tensile streεε, it iε annealed. The chip is heated for an extended period in a nitrogen ambient (N ) . The annealing step also drives the phosphorouε dopant into the polyεilicon aε in a standard implant drive proceεε. In the preferred embodiment, the polysilicon is annealed to reεult in a tenεile εtreεε of approximately 6E8dyneε/cm in order to maintain a relatively εtable εpring conεtant for the finished microstructure. The resulting polyεilicon εheet resistance is approximately 90 to 160 ohmε/εq. FIG. 13 εhowε the chip after completion of step 48. Aε εhown therein, a 20,000 angstrom thick layer cf polyεilicon 62 has been depoεited over the chip. A.s shown in FIG. 13, an anchor 64 iε formed in anchor well 59. PROCESS 49: MICROSTRUCTURE MASK In thiε proceεε, a photoresist maεk iε formed to remove all polyεilicon from the circuit area and to form the desired microstructure εhape in the moat area. The polyεilicon iε then dry etched. FIG. 14 illuεtrates the chip after the completion of proceεs 49. TASK 13: REMOVE SPACER OXIDE FROM CIRCUIT AREA Thiε taεk comprises only process 50. PROCESS 50: MOBE MASK In this procesε, a photoresiεt layer is deposited and masked for etching the εpacer oxide layer 60. The term "MOBE" iε an arbitrary deεignation for this particular mask. The term "MOBE" is a contraction of "moat and beam" and was selected becauεe this mask is formed so aε to cover the microεtructure (or beam) but to allow the εpacer oxide 60 to be removed from the circuit area. The maεk, different than the moat maεk uεed in proceεs 36. After the photoresist is patterned, the chip iε depoεited in the buffer oxi e etch bath in which the εpacer oxide iε selectively etched away down to underlying nitride layer 58. The LPCVD nitride layer 58 acts as an etch stop for the etching cf the oxide. FIG. 15 illuεtrateε the chip subsequent to the completion of step 50. TASK 14 : DEPOSIT OXIDE LAYER TO PROTECT MICROSTRUCTURE This task compriεeε only a single proceεs. PROCESS 51: LOW TEMPERATURE OXIDE DEPOSITION In this proceεε, a 2,000 angεtrom thick layer of low temperature oxide is deposited by chemical vapor deposition. This oxide layer will εerve to protect the microεtructure from an upcoming deposition of platinum for forming the electrical contacts in the circuit area as well as between the sensor and the circuitry. Without the thin layer of LTO, the platinum would react with the polyεilicon during platinum εilicidation and alter the polyεilicon' ε mechanical and electrical propertieε. FIG. 16 εhowε the 2,000 angεtrom low temperature oxide layer at 66. TASK 15: REMOVE SENSOR DIELECTRICS FROM CIRCUIT AREA Thiε taεk compriεes only a single procesε. PROCESS 52: MOSIN MASK A patterned photoreεist layer iε formed using standard- photclithcσraohv εtepε to define a larσe iεland in the moat area where all εenεor dielectrics will be preserved while the remainder of the photoresiεt iε developed away so as to allow the etching away of all senεor dielectricε from the circuit area of the chip. Two maεkε are uεed here, a MOSIN maεk and the MOBE maεk, to provide extra photoresiεt protection on the sharp vertical stepε of the polyεilicon εensor. The term "MOSIN" waε choεen to diεtinguiεh thiε maεk from the MOAT maεk and the MOBE maεk. The term "MOSIN" iε a contraction of "moat and εilicon nitride" εince the maεk will be uεed to etch all the way down to nitride layer 54. In thiε proceεε, the MOBE maεk iε uεed firεt followed by the MOSIN maεk. The MOBE maεk iε slightly smaller than the MOSIN maεk such that two photoresiεt patterns are visible. The senεor dielectricε which are etched away from the circuit area in thiε proceεs compriεe the low temperature oxide layer depoεited in proceεs 51, the nitride layer depoεited in proceεε 40 and the low temperature oxide layer depoεited in proceεε 38. The two oxide layerε are removed by separate wet etch procesεeε (buffer oxide etch) . The nitride layer is removed in a dry plasma etch procesε. The nitride layer 54 underlying the three layers which are etched in this process that was depoεited during process 35 remains. This layer, 54, serveε aε an etch εtop for the etching cf oxide layer 56. The three layers etched away in thiε proceεs are removed in order to enable laser trimming in the circuit area. The photoresiεt iε then removed after the three layerε are etched. FIG. 17 shows the chip after the completion of procesε 52. Aε shown therein, layers 66, 58 and 56 have been removed from the circuit area, thus expoεing nitride layer 54. TASK 16: CONTACT MASK Thiε task comprises only process 53. PROCESS 53: CONTACT MASK Like MOSIN mask in proceεε 52, contact mask utilizes two separate photoresist layers (contact and MOBE) to provide sufficient photoresiεt coverage on the εharp vertical stepε in the senεor area. Firεt MOBE maεk iε applied to cover the moat area and leave the circuitry regionε expoεed. Then, contact maεk iε applied. The contact maεk iε developed to define openingε to the tranεiεtorε for metal contactε and openingε to the n-t- runners in the moat area for metal contacts and also to provide additional photoresiεt coverage for the microstructure in the moat area. After the photoresist maskε have been formed, four layerε muεt be etched through. They are nitride layer 54, BPSG layer 52, nitride layer 50 and gate oxide layer 46. All four layerε are etched in a εingle long plasma etch which exposeε the εubεtrate in the defined contact areaε εuch aε the bare n+ runner in opening 67 in FIG. 19. FIG. 18 illuεtrateε the circuit region of the chip after the completion of process 53. Reference numeral 48 indicates the gate polysilicon. Reference numeral 46 indicates the gate oxide. The shallow source and drain diffusion regions of the PMOS transiεtorε are shown at 33. The BPSG layer iε shown at 52. The remaining numerals refer to regionε previouεly diεcuεsed with respect to at leaεt FIG. 5 and have been defined in the diεcuεεion of FIG. 5. TASK 17: FORM PLATINUM SILICIDE IN CONTACT AREAS Thiε task comprises procesεeε 54-56. The purpoεe of thiε taεk iε to form a platinum εilicide layer in the metal contact openingε, e.g., opening 67 in FIG. 19, εo aε to provide good ohmic contact with the electrical leadε which will be formed in subsequent proceεεeε . PROCESS 54: PLATINUM DEPOSIT In thiε proceεε, platinum is deposited on the chip by a standard high-vacuum sputtering proceεs. The platinum iε depoεited to a depth of 400 angεtromε. PROCESS 55: PLATINUM SINTER The platinum formed in process 54 is sintered in this process so as to cause the platinum to react with the silicon on the surface of the substrate to form platinum silicide. The process essentially comprises exposing the chip to a high temperature. The platinum silicidizeε only where it contactε the bare subεtrate, e.g., in the contact openings. PROCESS 56: PLATINUM STRIP In this procesε, the platinum which haε not been silicidized is removed. Specifically, the chip is placed in a nitric-HCL acid bath which strips away unsilicidized platinum leaving platinum silicide in the contact openings. FIG. 19 shows the chip after the completion of process 56 illustrating silicidized contact opening 67. TASK 18: METALLIZATION The metallization task compriseε proceεses 57-61. In this taεk, the metal leads are formed to connect the various contact openings to each other so as to couple the transistors together in the desired circuit pattern. The thin film trimmable resistors also are formed. PROCESS 57: SiCr SPUTTER In this proceεε, a blanket of SiCr iε formed by a standard sputter deposition procesε. The SiCr will be used to form laser trimmable resistors. The SiCr is deposited to a εheet reεiεtance of 1,000-1,200 ohms/sq. PROCESS 58: METAL SPUTTER In this process, titanium tungsten (TiW) and aluminum/copper (AlCu) are deposited in two separate sputtering processeε. The two metals will be formed into the electric leads in the following process. PROCESS 59: METAL MASK In this process, a photoresiεt maεk iε formed defining the deεired metal leads. Two consecutive exposureε are required with two different maεkε to insure complete removal of the photoresiεt (and ultimately the metal) from the two micrometer deep sensor gaps. The firεt mask expoεed iε a εtandard metal maεk to connect the BIMOS circuitry on the chip. Then, a moat maεk iε expoεed in the εame reεiεt to facilitate removal of all reεiεt from the sensor area during development. Only the sensor area is opened by moat mask so only the senεor area gets over exposed. The AlCu is then etched by a wet etch procesε in a bath of phosphoric acetic nitric (PAN) acid. This is followed by a wet etch of the TiW in hydrogen peroxide leaving the deεired electrical leadε. The photoresist iε then εtripped away. PROCESS 60: THIN FILM MASK Photoreεiεt is deposited and patterned to define the desired resistors. The SiCr layer is dry etched in accordance with the photoresist mask to form the reεiεtorε. The Photoreεiεt is then stripped away. Thin film mask, like the metal mask in procesε 59, uses a second exposure with moat mask to facilitate clearing the senεor area of photoreεist and, therefore, thin film material also. PROCESS 61: ALLOY In this process, the chip is expoεed in a high temperature furnace to cauεe the TiW and AlCu tc react with the platinum εilicide in the contact openings so as to form good ohmic contact between the εubεtrate and the electrical leadε. FIG. 20 illustrates the circuit after * the completion cf proceεε 61. Aε shown therein, metal leads, such aε lead 68, have beer, formed in contact openingε εuch aε opening 67. The leadε extend over nitride layer 54 to connect the contact openingε, thus coupling the transiεtorε into the deεired circuit. TASK 19: PASSIVATION This task comprises processes 62-66. The pasεivation used in the method of this invention iε depoεited in two εeparate εtepε to allow a nitride-to-nitride seal to be formed around the εensor to protect the circuitry from the very long etching proceεs which will follow to completely undercut the spacer LTO and releaεe the εenεor. The passivation layers will serve to protect the metal from scratching and also to protect the circuitry from moisture, ionic contamination, etc. The passivation, however, cannot exist in the bond pad openings becauεe metal must be bonded to the bond padε . The paεεivation alεo muεt be removed from the microεtructure εo aε not to affect itε free movement under accelerative forceε. PROCESS 62: PLASMA OXIDE DEPOSIT In thiε proceεε, plaεma oxide iε depoεited to a thickneεε of 5,000 angstroms by plasma ' enhanced chemical vapor deposition. A small amount of phosphorous is contained in the oxygen plasma so aε to form part of the oxide layer. PROCESS 63: PASSIVATION MASK In this procesε, the oxide layer formed in proceεε 62 is patterned to set up the nitride-to- nitride seal around the perimeter of the sensor and also to open up the circuit area bond pads. Accordingly, a photoresist maεk is formed and patterned to define (1) a channel around the perimeter of the sensor and (2) the bond pads. The oxide layer is etched in a buffer oxide etch bath and the photoresiεt iε then stripped away. FIG. 21 illustrates the chip subsequent to the completion of procesε 63. As shown therein, a plasma oxide layer 70 has been formed over the chip and layer 70 haε been etched to define openingε εuch aε sensor perimeter opening 72 and bond pad opening 74. PROCESS 64: PLASMA NITRIDE DEPOSIT At this point, another layer of nitride 76 iε depoεited to a thickneεε of approximately 5,000 angεtromε by plaεma enhanced chemical vapor deposition. Thiε setε up a nitride-to-nitride εeal around the εensor area. The nitride-to-nitride seal protects the circuit area from the final long wet etch used to remove the spacer LTO from under the polysilicon sensor. The seal is formed between this nitride layer 76 (see FIG. 22) and the LPCVD nitride layer 58 that was depoεited in proceεε 40. PROCESS 65: BACK ETCH Thiε is a standard proceεε and iε not actually related to the nitride-to-nitride seal task 19. However, it is performed at this point, i.e., before the nitride layer depoεited in proceεε 64 is removed, because the nitride layer adds extra protection during the back etch. In any event, the back etch involves blanket coating the front of the chip with photoresist and etching all dielectrics from the back of the chip in a long serieε of wet and dry etcheε. PROCESS 66: NTPAS MASK It is now necessary to remove the nitride deposited in procesε 64 from the εensor area aε well aε from the bond padε, e.g., bond pad 74. A photoresist maεk is formed to open the bond pads and the εenεor. The nitride layer 76 iε etched in a dry etching proceεε. Aε noted above, thiε etching proceεε iε performed after the back etch becauεe the nitride layer provideε added protection during the back etch. FIG. 22 illustrates the chip after the completion of process 66. As shown therein, a nitride layer 76 has been formed over the chip and has been etched to open up the metal leads in the bond pad regionε such as lead 68 and to open up the sensor . TASK 20: RELEASE MICROSTRUCTURE This final task comprises only process 67 in which the spacer oxide layer is removed, thus releasing the microstructure into its final εuspended condition as illuεtrated in FIGS. IA, IB and 2A. PROCESS 67: MICROSTRUCTURE RELEASE MASK In this procesε, a photoresiεt maεk is formed to entirely cover the circuitry area and most of the moat area with a few holes in the moat area adjacent to sections where the spacer oxide is exposed, i.e., sectionε where the polyεilicon has been removed to form the microstructure εhape. The holeε in the photoreεiεt are placed εuch that they are directly adjacent to the edgeε of the overlying microεtructure. The chip iε then placed in a buffered etch oxide bath εuch that the oxide layer iε etched where it is expoεed under the photoresiεt maεk. The chip iε left in the bath for an extended period such that the oxide iε etched εlightly beyond the dimensions of the hole in the photoresist and extend a few micronε beneath the edges of the microstructure. The photoresist is then removed and another layer of photoresist is depoεited on the chip. Thiε layer of photoreεiεt fills in the holes now formed in the oxide layer as well aε fills in the voids between portions of the etched polysilicon microεtructure. The photoreεiεt iε then exposed without a mask to develop away most of the photoresist. However, the portions of the photoresist which have filled in the edges of the holeε and which extend under the edges of the microstructure are not developed away becauεe these edgeε are occluded by the polyεilicon microstructure. If desired, a mask can be used so as also to leave some photoresist bridges in polysilicon layer 62 in the gaps between non-contacting portions of the polysilicon microstructure, e.g., between mobile armε 14. The remaining spacer oxide 60 is then removed in a buffer oxide etch. This bath also removeε oxide layers 66 and 70 which were earlier left in the moat area coating the microstructure. The buffered oxide bath does not affect the polyεilicon or the photoresist. Accordingly, the photoresiεt- bridges in the gaps between non-contacting portions of the microεtructure aε well aε the photoresist pedestals formed underneath the microstructure still remain after the spacer oxide is removed. The photoresiεt pedestals which formed at the edges of the holes beneath the microstructure vertically support the microstructure preventing it from bending and contacting the underlying substrate. The photoresist bridges left in the gaps between non-contacting portions of the microεtructure provide lateral support preventing such portions from laterally bending and contacting each other. Without the photoresiεt pedestals and bridgeε, portions of the microstructure would be extremely prone to bending and contacting the substrate and/or other portions of the microstructure during the drying procedure after the buffer oxide wet etch due to liquid surface tension effects. The photoresist pedestals and bridges significantly reduce the possibility of portions of the microεtructure contacting the substrate or other portions of the microstructure. Further, even if contact occurs, the bumps formed on the bottom surface of the microεtructure during process 43 significantly reduce surface area contact thuε significantly reducing the possibility of sticking. Accordingly, the photoresiεt pedestalε and bridges as well aε the bumpε significantly increase the device yield of the method of the present invention. The photoresiεt pedeεtalε and bridgeε are removed in a long oxygen plaεma εtripping proceεε which does not present any liquid εurface tenεion problemε . Process 67 of the present invention is more fully discussed in U.S. Patent Application No. 07/872,037 referenced above. Accordingly, it will only be briefly discussed here. For a more complete understanding of this procesε and itε many steps, reference should be made to the aforementioned patent application. At this point, the microstructure is now suspended in its final form aε illustrated in FIG. 20. It should be understood that the method of the present invention can be readily adapted for circuitry having NMOS transiεtorε in addition to the PMOS and bipolar transistors discussed in the preferred embodiment disclosed herein. It should further be understood that the method of the present invention can be used to fabricate many kinds of chips embodying a microεtructure aε well aε circuitry and iε not limited to the accelerometer diεcussed herein. Having thuε deεcribed a few particular embodimentε of the invention, variouε alterationε, modificationε and improvements will readily occur to thoεe skilled in the art. Such alterationε, modificationε and improvementε aε are made obvious by this diεcloεure are intended to be part of thiε description though not expresεly εtated herein, and are intended to be within the εpirit and εcope of the invention. Accordingly, the foregoing deεcription is by way of example only, and not limiting. The invention is limited only aε defined in the following claims and equivalents thereto. What iε claimed is:

Claims: CLAIMS 1. A method of fabricating a microchip which includes a suspended microstructure and circuitry, said method comprising the steps of; (1) forming transistors in a first region of a surface of a substrate, (2) forming a layer of material on said surface which will act as an etch stop for the etching of oxide, (3) removing dielectrics formed on said substrate during said formation of said transistors from a second region of said substrate, except for a layer of oxide on said surface, said second region defining where said microstructure will be formed, (4) passivating said surface in said second region, (5) depositing a layer of spacer oxide over said etch εtop layer to act aε a spacer for the formation of said εuspended microεtructure, (6) etching anchor openings in said spacer oxide layer defining anchors from which said suspended microstructure will be supported, (7) depositing a layer of polysilicon over εaid spacer oxide from which said suspended microstructure will be formed, (8) etching said polyεilicon to form said polysilicon into said microstructure. (9) removing said spacer oxide from said firεt region of said surface, (10) forming a protective layer of oxide over said polysilicon in said second region, (11) forming conductive paths on said microchip for electrically interconnecting said transistors to form a circuit and for electrically interconnecting said microstructure to said circuit, (12) passivating said first region of said microchip, and (13) etching said spacer oxide layer to remove all of said oxide and release said microstructure into a suspended state. 2. A method as set forth in Claim l wherein step (1) comprises the step of; (1.1) implanting dopant into said substrate in said second region so as to improve isolation between different portions of said microstructure. 3. A method as set forth in Claim 1 further comprising the step of; (3.1) implanting more dopant into said subεtrate in said second region to increase the dopant level so as to improve isolation between portions of εaid microstructure. 4. A method as εet forth in Claim 1 wherein said layer of material formed in step (2) compriεeε nitride and further wherein step (13) comprises forming a nitride-to-nitride seal around said first region. 5. A method as set forth in Claim 4 wherein step (12) comprises the steps of; (12.1) depositing a layer of oxide over said nitride layer formed in step (2), (12.2) selectively etching said oxide deposited in step (12.1) so as to form a channel around said first region, and (12.3) depositing a second layer of nitride over said microchip so as to form a nitride-to-nitride seal around said first region. 6. A method as set forth in Claim 5 wherein step (12) further compriseε the step of; (12.4) removing said nitride layer formed in step (12.3) from said second region. 7. A method as set forth in Claim 1 wherein step (11) further includes forming resiεtors and comprises the steps of; (11.1) depositing a layer of SiCr on εaid microchip from which said resiεtorε will be formed, (11.2) depoεiting metal on εaid microchip from which said conductive paths will be formed, (11.3) selectively etching εaid metal εo aε to form said conductive pathε, and (11.4) selectively etching said SiCr so as to form said resistors in a specified pattern. 8. A method as set forth in Claim 7 wherein step (11.2) further comprises the step of; (11.2.1) sputter coating said microchip with TiW, and (11.2.2) sputter coating said microchip with AlCu. 9. A method as set forth in Claim 8 wherein step (11) further comprises the step of; (11.5) heating said microchip for a specified interval such that said TiW and said AlCu chemically interact to form an alloy. 10. A method as set forth in Claim 1 wherein step (1) comprises the steps of; (1.2) forming emitters of said transistorε while simultaneously forming n+ runners for electrically connecting said microstructure to said circuitry. 11. A method as set forth in Claim 1 wherein step (9) comprises selectively etching said spacer oxide and wherein said method further comprises the step of; (4.5) depositing a layer of nitride over said microchip, said layer to act as an etch stop for the etching of said εpacer oxide in εtep (9). 12. A method aε set forth in Claim 1 wherein step (6) comprises the steps of; (6.1) increasing dopant levels in said anchor openings. 13. A method as set forth in Claim 1 wherein εtep (4) compriseε the εteps of; (4.1) depositing a layer of oxide over said microchip, and (4.2) densifying said oxide. 14. A method as set forth in Claim 1 wherein step (5) comprises the steps of; (5.1) depositing said spacer oxide by chemical vapor depoεition, and (5.2) densifying said spacer oxide by expoεing it to high temperature. 15. A method aε set forth in Claim 14 wherein step (5) further comprises the step of; (5.3) selectively etching divots into a top surface of said spacer layer, whereby, when said microεtructure iε formed over said spacer layer, bumps are formed on a bottom surface of said microstructure. 16. A method as εet forth in Claim 1 wherein step (5) further compriseε the step of; (5.3) selectively etching divots into a top surface of said spacer layer, whereby, when said microstructure is formed over said spacer layer, bumps are formed on a bottom surface of said microstructure. 17. A method as set forth in Claim 1 wherein step (7) comprises the steps of; (7.1) depositing said polysilicon over said spacer oxide by low pressure chemical vapor deposition, (7.2) implanting a dopant into said polysilicon in order to make said polysilicon electrically conductive, and (7.3) annealing said polysilicon to form said polysilicon to a specified tensile stress. 18. A method as set forth in Claim 1 wherein step (10) comprises etching εaid spacer oxide from said firεt region. 19. A method as set forth in Claim l further comprising the step of; (10.5) removing from said firεt region all dielectrics formed in said first region in steps (4) through (10) . 20. A method as set forth in Claim 11 wherein said method further comprises the step of; (4.3) depositing a layer of nitride over said microchip, to act as an etch stop for the etching of said spacer oxide in step (9). 21. A monolithic sensor comprising: a substrate, a suspended microstructure dispoεed above and suspended from said substrate for sensing a condition, and circuitry for resolving a signal based on said sensed condition. 22. A monolithic sensor as set forth in claim 21 wherein said microstructure senses acceleration.

Inventors: BROKAW A PAUL, CORE THERESA A, SHERMAN STEVEN J, TSANG ROBERT W K, BROKAW, A., PAUL, CORE, THERESA, A., SHERMAN, STEVEN, J., TSANG, ROBERT, W., K.
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INC.
Application year: 1993
Main classification: G01P15
IPC codes: B81B3, G01P15, H01L29