Display controlling apparatus

Abstract: An image is displayed excellently by partially rewriting the image on the display. A display controlling apparatus for displaying an image on the display having a memory function is characterized by comprising input means for image signal, storage means for storing an image signal input by said input means, differential calculating means for calculating the differential value between image signal input by said input means and image signal before unit time at the same location stored in said storage means, and partial rewrite controlling means for creating a partial rewrite signal of the display from the differential value.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a display controlling apparatus for controlling halftone display, and particularly to a display controlling apparatus suitable for controlling a display having memory function for displaying an image at a lower frequency than the frame frequency of an input image signal, for example, a ferroelectric liquid crystal display (hereinafter abbreviated to as FLCD). Related Background Art First, FLCD will be described briefly. FLCD is a display using a liquid crystal, characterized in that each pixel itself of the display has a memory, whereby each pixel cell can hold its display state without application of electric field, the display state of pixel being changed by applying electric field. FLCD is expected as a display in the next generation because it is easily manufactured into large screen. Recently, several binarization methods have been developed, including an error diffusion method and an average density preservation method, whereby a high quality binary image can be obtained even though the image may contain characters, line figures and natural images mixed with each other. FLCD can not operate at the display speeds of high definition, for example, 60Hz non-interlace for the image size of 1280 x 1024, due to its characteristics. In particular, for computer display outputs from the work station which has recently advanced for higher definition, FLCD can not follow the cursor movement of mouse requiring the interactiveness, with a frame frequency of about 1/4, so that the operator may feel unpleasantly, with the operation efficiency decreased. Thus, a method has been devised, with improved apparent frequency, in which the display state is altered for only the changed portion between frames by making effective use of the memory function of FLCD. Fig. 2 shows the relation between a computer and a display. 10 is a computer main unit, comprised of a CPU and peripheral units such as a memory and a disk. From the computer main unit, an image signal 11 for display is output. Normally, the image signal 11 is a digital signal, or an analog signal, such as an NTSC composite signal, a component RGB signal and a non-interlace signal. 30 is an FLCD. 20 is an image process unit, according to the present invention, for inputting an RGB analog signal 11 from the computer main unit 10 for the conversion into digital signal 12, one bit for each RGB, which is then output to the FLCD 30. The FLCD 30 inputs the digital RGB signal 12 for the display from the image process unit 20. However, in the configuration as shown in Fig. 2, the output from the computer 10 is an analog signal of 60Hz non-interlace with the image signal 11 corresponding to the size of 1280 x 1024, for example, wherein information regarding the shape of cursor or the movement from (X0, Y0) to (X1, Y1) is not specifically given, even though the cursor is moved as shown in Fig. 6. That is, no information regarding the area to change the display state to effect the fast display is supplied from the computer. Hence, such information must be extracted out of the input image data. In particular, when the image data is displayed through quantization, it is a problem how to extract the area to change the display state. On the other hand, a technique for switching between the intraframe coding and the interframe coding depending on whether or not the display state is changed has been described in Japanese Patent Application Nos. 4-149470 and 4-292214. However, the above-cited technique needed no information as to which area of the screen was changed. Therefore, it could not detect such changed area which is of concern in the present invention. SUMMARY OF THE INVENTION In the light of the aforementioned affairs, an object of the present invention is to display an excellent image by partially rewriting a display image. To achieve such object, according to the present invention, there is disclosed a display controlling apparatus comprising, input means for inputting image data; quantisation means to quantise the image data by using a pseudo-halftone processing method; detection means for detecting changes between image data representing first and second successive image frames; generation means responsive to said detection means, to generate a control signal to control rewriting of a partial area of a display; and output means co-operative with said quantisation means, and said generation means, to output quantised image data selected under the control of said control signal; wherein said detection means is arranged between said input means and said quantisation means to receive and operate on image data prior to it being quantised by said quantisation means. It is acknowledged that it is known to detect changes between image data representing first and second successive image frames and to control partial rewriting of a display to rewrite those lines which correspond to the detected changed image data - see for example European Patent Applications EP-A-0435701 and EP-A-0368117. Other advantages and preferred embodiments of the present invention will be apparent from the following description with reference to the drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of a display controlling apparatus according to a first embodiment; Fig. 2 is an overall diagram of an image display system to which the present invention is applied; Fig. 3 is a block diagram showing the configuration of a display controlling apparatus according to a second embodiment; Fig. 4 is a block diagram showing the configuration of a display controlling apparatus according to a third embodiment; Fig. 5 is a diagram showing a low pass filter useful for the smoothing according to a third embodiment; Fig. 6 is a diagram showing the movement of a cursor; Fig. 7 is a block diagram showing the configuration of a display controlling apparatus according to a fourth embodiment; Fig. 8 is a block diagram showing the configuration of a display controlling apparatus according to a fifth embodiment; Fig. 9 is a block diagram showing the configuration of a display controlling apparatus according to a sixth embodiment; Fig. 10 is a block diagram showing the configuration of a display controlling apparatus according to a seventh embodiment; Fig. 11 is a diagram showing a low pass filter useful for smoothing in the seventh embodiment; and Fig. 12 is a block diagram showing the configuration of a display controlling apparatus according to an eighth embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments 1 to 3 of the present invention as set forth below each comprise storage means for storing image data before unit time when displaying image on a display having memory function, differential calculation means for calculating the differential between input image signal and stored image signal at the same location, binarization means for binarizing a result of said differential calculation means at a threshold, whereby the precision of determining the partial rewrite area is enhanced by determining the partial rewrite area of the display which is to be rewritten from binarized data obtained by said binarization means. Also, signal conversion means for converting input image signal is provided to improve the detection precision of a pointing mark such as a cursor, as represented mainly in black and white. Further, means for smoothing input image is provided to reduce influence with noise. Specific embodiments will be now described. (First embodiment) Fig. 1 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In this embodiment, input signal is supposed to be a non-interlace 60Hz signal of component RGB. In Fig. 1, 100 is an input terminal for RGB analog output signal 11 from a computer 10, and 110 is an A/D conversion unit for A/D converting an RGB analog signal as input to create multi-value digital RGB signal. RGB analog signal is a 60Hz non-interlace signal. 120 is an image binarization unit for converting multi-value RGB digital signal into signal, one bit for each RGB. Binarization technique for the image used herein is an error diffusion method suitable for representing the half tone. 130 is a delay buffer composed of an FIFO memory to effect synchronization. 140 is a switch which is turned on or off by a predetermined control signal. 150 is a frame memory for storing data, one bit for each RGB, of each pixel, and which is comprised of, for example, two-port RAM. 160 is an RGB/Y conversion unit for generating multi-value Y signal which is a luminance signal from multi-value digital RGB signal. 170, 180 are frame memories for storing Y signal, and 190 is an absolute value differential unit for calculating the absolute value differential between input Y signal and Y signal before one frame stored in a frame memory 170 or 180. 200 is a binarization unit for binarizing multi-value absolute differential value. Binarization technique used herein is a simple binarization for effecting binarization by making a comparison with a prefixed threshold. 210 is a line flag memory for enabling a flag to be turned on or off for each scan line. 220 is a partial write detection unit for detecting whether or not the partial write is performed from the content of line flag memory 190 as well as controlling the location of partial write. 230 is an FLCD interface for reading the control of video frame memory 150 for the output to the FLCD 30 via a terminal 240. RGB analog signal of 60Hz non-interlace from the computer 10 is input into the A/D conversion unit 110 via the terminal 100. Input multi-value RGB analog signal is A/D converted into multi-value RGB digital signal in the A/D conversion unit 110 for the input to image binarization unit 120 and RGB/Y conversion unit 160. The image binarization unit 120 binarizes input multi-value RGB signal for each color in succession by using the error diffusion method. Its result is stored in the delay buffer 130. On the other hand, multi-value RGB digital signal input into the RGB/Y conversion unit 160 is converted into Y signal for each pixel in succession. The conversion from RGB signal into Y signal is performed based on an expression: Y = 0.299 x R + 0.587 x G + 0.114 x B The Y signal is input into the absolute value differential unit 190, and at the same time written into the frame memory 170 or 180. The frame memories 170 and 180 are subjected to alternating operation of writing and reading in the unit of frame, that is, while one of them is written, the other is read. The absolute value differential unit 190 calculates the absolute value of the differential between the Y signal input from the RGB/Y conversion unit 160 and the Y signal before one frame at the same location written into the frame memory 170 or 180. The absolute value of the differential of Y signal input into the binarization unit 200 is compared with a prefixed threshold TH for the binarization. If the absolute value of the differential is greater than the threshold TH, 1 is output, or otherwise, 0 is output. It suffices that the threshold TH is a greater value than the analog noise of input RGB signal. There are various methods for determining the threshold TH. For example, an analog signal of single luminance (herein, 128 is supposed) output beforehand is input to the terminal 100, converted into digital data in the A/D conversion unit 110, input into the RGB/Y conversion unit 160 for the conversion into the Y signal, and written into the frame memory 170. The absolute value differential unit 190 calculates the absolute value differential from the fixed value (herein, 128 is supposed), but not the input from the RGB/Y conversion unit 160, with its maximum value determined as the threshold TH. If the binarized Y signal is 1, it is extracted as the change point. Before starting the process of scan lines, corresponding flags in the line flag memory 210 are reset. The presence of change point is detected in the unit of line, and if at least one change point is extracted in a line of interest, the flag of the line flag memory 210 corresponding to the scan line of interest is set. If no change point exists within one scan line, the flag set in the line flag memory 210, if any, is reset. The partial write detection unit 220 monitors the flag status in the line flag memory 210, and if any flag is set, the partial write for the corresponding scan line is performed. In performing the partial write, the switch 140 is turned on, and location information concerning the scan line for the partial write is transmitted to the video frame memory 150 and the FLCD interface unit 230. As a result, binarized RGB signal of scan line corresponding to the scan line at which change point is detected is read from the delay buffer 130, and written into the video frame memory 150. Further, the FLCD interface 230 reads RGB binarization signals of corresponding scan lines in the video frame memory 150 to change the display states of the corresponding scan lines of the FLCD 30 based on the scan line data of the FLCD 30. If no flag is set in the line flag memory 210, the partial write detection unit 220 turns off the switch 140, wherein no partial write for RGB binarization signal of the corresponding scan line is performed. In this way, the display state for only the portion that has been changed is altered. (Second embodiment) Fig. 3 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In Fig. 3, like numerals refer to the parts having the same functions as in Fig. 1 of the embodiment 1. 300 to 350 are frame memories. 360, 370, 380 are absolute value differential units for calculating the absolute value of the differential between frames by making a comparison between input multi-value signal and multi-value signal before one frame stored in the frame memory. 390, 400, 410 are binarization units for the image, and 480 is an OR circuit. RGB analog signal of 60Hz non-interlace from the computer 10 is input into the A/D conversion unit 110 via the terminal 100. Input multi-value RGB analog signal is A/D converted into multi-value RGB digital signal in the A/D conversion unit 110 for the input to image binarization unit 120, R multi-value signal being input into a frame memory 320 or 330, G multi-value signal into a frame memory 300 or 310, and B multi-value signal into a frame memory 340 or 350. The frame memories 300 and 310, the frame memories 320 to 330, and the frame memories 340 and 350, are subjected to alternating operation of writing and reading in the unit of frame, that is, while one of them is written, the other is read. The image binarization unit 120 binarizes input multi-value RGB signal for each color in succession by using the error diffusion method. Its result is stored in the delay buffer 130. The absolute value differential unit 360 calculates the absolute value of the differential between the R signal input from the A/D conversion unit 110 and the R signal before one frame at the same location written into the frame memory 170 or 180. The absolute value of the differential between R signals input into the binarization unit 360 is compared with a fixed threshold TH R for the binarization. If the absolute value of the differential is greater than the threshold TH R , 1 is output, or otherwise, 0 is output. It suffices that the threshold TH R is a greater value than the analog noise. In the same way, change points for B signal and G signal are also detected. The outputs from the R signal binarization unit 390, G signal binarization unit 400 and B signal binarization unit 410 are input into an OR circuit 480. The OR circuit 480 calculates a logical sum of these inputs for the output to the line flag memory 210. Before starting the process of scan lines, corresponding flags in the line flag memory 210 are reset. If the output of the OR circuit 480 is 1, the flag in the line flag memory 210 corresponding to the scan line of interest is set. The partial write detection unit 220 monitors the flag status in the line flag memory 210, and if any flag is set, the partial write for the corresponding scan line is performed. In performing the partial write, the switch 140 is turned on, and location information concerning the scan line for the partial write is transmitted to the video frame memory 150 and the FLCD interface unit 230. As a result, binarized RGB signal of scan line corresponding to the scan line at which change point is detected is read from the delay buffer 130, and written into the video frame memory 150. Further, the FLCD interface 230 reads RGB binarization signals of corresponding scan lines in the video frame memory 150 to change the display states of the corresponding scan lines of the FLCD 30 based on the scan line data of the FLCD 30. If no flag is set in the line flag memory 210, the partial write detection unit 220 turns off the switch 140, wherein no partial write for RGB binarization signal of the corresponding scan line is performed. In this way, the display state for only the portion that has been changed is altered. (Third embodiment) Fig. 4 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In Fig. 4, like numerals refer to the parts having the same functions as in Fig. 1 of the embodiment 1. 600 is an analog RGB/Y conversion unit for generating analog Y signal which is a luminance signal from analog RGB signal. 610 is an A/D conversion unit for A/D converting analog Y signal to create multi-value digital Y signal. 620 is a low pass filter unit for effecting low pass filter process as shown in Fig. 5 to subsample scan lines odd-numbered. 630, 640 are frame memories having one-half the image size of display in vertical and horizontal directions. 650 is an absolute value differential unit for calculating the absolute value differential between input Y signal and Y signal before one frame stored in the frame memory 630 or 640. 660 is a binarization unit for binarizing the multi-value absolute value differential. Binarization technique used herein is a simple binarization by the comparison with a fixed threshold. 670 is a line flag memory the flags of which can be turned on or off for each scan line odd-numbered. 680 is a partial write detection unit for detecting whether or not the partial write is performed from the content of the line flag memory 670 to control the partial write such as the location of partial write. 690 is a delay buffer. RGB analog signal of 60Hz non-interlace from the computer 10 is input into the A/D conversion unit 110 and the RGB/Y conversion unit 600 via the terminal 100. Input multi-value RGB analog signal is A/D converted into multi-value RGB digital signal in the A/D conversion unit 110 for the input to image binarization unit 120. The image binarization unit 120 binarizes input multi-value RGB signal for each color in succession by using the error diffusion method. Its result is stored in the delay buffer 690. On the other hand, the RGB/Y conversion unit 600 converts input RGB analog signal into analog Y signal for the output to the A/D conversion unit 610. The A/D conversion unit 610 A/D converts analog Y signal to create multi-value digital Y signal for the input into the low pass filter unit 620. The low pass filter unit 620 performs the low pass filter process to subsample the scan lines odd-numbered at half the frequency. The Y signal subjected to low pass filtering is written into the frame memory 630 or 640. The frame memory 630 and 640 are subjected to alternating operation of writing and reading in the unit of frame, that is, while one of them is written, the other is read. The absolute value differential unit 650 calculates the absolute value of the differential between the R signal input from the RGB/Y conversion unit 610 and the Y signal before one frame at the same location written into the frame memory 630 or 640. The absolute value of the differential between Y signals input into the binarization unit 660 is compared with a fixed threshold TH for the binarization. If the absolute value of the differential is greater than the threshold TH, 1 is output, or otherwise, 0 is output. If binarized Y signal is 1, it is extracted as the change point. Before starting the process of scan lines, corresponding flags in the line flag memory 210 are reset. If change point is extracted, the flag in the line flag memory 210 corresponding to the scan line of interest is set. If no change point exists within one scan line, the flag set in the line flag memory 210, if any, is reset. The partial write detection unit 220 monitors the flag status in the line flag memory 210, and if any flag is set, the partial write for corresponding scan lines is performed. In performing the partial write, the switch 140 is turned on, and location information concerning the scan line for the partial write is transmitted to the video frame memory 150 and the FLCD interface unit 230. If no partial write is performed at the previous scan line odd-numbered in the line flag memory 670, the partial write detection unit 680 reads data for the scan line of interest odd-numbered and data for the scan lines even-numbered located before and after the scan line of interest from the delay buffer 690. The location of the scan line of interest odd-numbered and the locations of the scan lines even-numbered before and after that scan line of interest are transmitted to the video frame memory 150 as the location information, and also transmitted to the FLCD interface 230 at the same time when data is written. RGB binarization signal of the scan line of interest in the video frame memory 150 is read to change the display state of the scan line of interest in the FLCD 30, with the scan line data of the FLCD 30. If no flag is set in the line flag memory 670, the partial write detection unit 680 turns off the switch 140, wherein no partial write for RGB binarization signal of the corresponding scan line is performed. In this way, the display state for only the portion that has been changed is altered. Input signal is not limited to the RGB analog signal, but may be a multi-value digital signal, or further an image signal for any of color components other than R, G, B. Also, it is not limited to the color. The signal for detection of change point is not limited to a luminance signal, but may include a chromaticity signal, or is not limited to luminance and chromaticity. The binarization technique for image is not limited thereto, but may be a pseudo-half tone process such as a dither method, or an average density preserve method as described in U.S. Patent No. 5,130,819, or other binarization techniques. The unit of the partial write is not limited to a scan line unit, but may be a block or pixel unit. The configuration of the frame memory is not limited thereto, but may be of a plurality of line buffers or other configuration. The subsampling technique for detection of change point is not limited thereto, but may be a subsampling or filter process performed before the A/D conversion. The display is not limited to the FLCD, but may be a display having memory function as well. As above described, with the provision of binarization means for the display and binarization means for the detection of interframe change, it is possible to provide the display with high definition as well as improving the precision for the detection of interframe change. Also, by converting the input signal into image signal such as luminance, it is possible to facilitate the extraction of a cursor, mainly composed of black and white, and reduce the memory capacity for detecting the interframe change, thereby attaining the lower costs of the device. Also, owing to subsampling the image signal, it is also possible to attain the lower costs of the device, reduce the memory capacity for the detection of change point because of sampling less than the image size of display, eliminate the noise contained in the analog signal by the use of a low pass filter, resulting in the improvement in detection precision of interframe change. As above-described, according to the above-described embodiments of the present invention, it is possible to display an excellent image by partially rewriting the display image. The following embodiments 4 to 6 of the present invention provides a first quantization means for quantizing image information for the display, when displaying an image on the display having memory function, and a second quantization means for quantizing image information for the detection of interframe change point to determine the partial rewrite area, wherein the precision of partial rewrite area is improved by determining the area from the image obtained by said second quantization means. Also, signal conversion means for converting image signal input to the second quantization means is provided to effect conversion of image signal, thereby improving the detection precision of a pointing mark such as a cursor as represented mainly by black and white. Further, means is provided for sampling image signal input to the second quantization means in less than the number of pixels for the input image, thereby preventing any false detection of interframe change point due to noise. (Fourth embodiment) Fig. 7 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In this embodiment, input signal is supposed to be a non-interlace 60Hz signal of component RGB. The quantization is performed by binarization. Fig. 7 shows the details of the image process unit 20 as shown in Fig. 2. 100 is an input terminal of RGB analog output signal 11 from the computer 10, and 110 is an A/D conversion unit for A/D converting an RGB analog signal as input to create multi-value (e.g., eight bits for each RGB) digital RGB signal. RGB analog signal is a 60Hz non-interlace signal. 120 is an image binarization unit for converting multi-value RGB digital signal into signal, one bit for each RGB. Herein, binarization technique for the image used herein is an error diffusion method suitable for the representation of half tone. 130 is a delay buffer composed of an FIFO memory to effect synchronization. 140 is a switch which is turned on or off by partial write control signal. 150 is a frame memory for storing data, one bit for each RGB, of each pixel, and which is comprised of, for example, two-port RAM. 160 is an RGB/Y conversion unit for generating multi-value Y signal which is a luminance signal from multi-value digital RGB signal. 2100 is a binarization unit for binarizing multi-value Y signal. The binarization technique used herein is a simple binarization by comparison with a fixed threshold. 2170, 2180 are frame memories for storing binarized Y signal, and 2200 is a change point extraction unit for detecting the change point between frames by comparison between binarized Y signal input and the binarized Y signal before one frame stored in the frame memory 2170 or 2180. 210 is a line flag memory for enabling a flag to be turned on or off for each scan line. 220 is a partial write detection unit for detecting whether or not the partial write is performed from the content of line flag memory 210 as well as controlling the partial write regarding the location of partial write. 230 is an FLCD interface for reading the content of video frame memory 150 for the output to the FLCD 30 via a terminal 240. RGB analog signal of 60Hz non-interlace from the computer 10 is input into the A/D conversion unit 110 via the terminal 100. Input multi-value RGB analog signal is A/D converted into multi-value RGB digital signal for the input to image binarization unit 120 and RGB/Y conversion unit 160. The image binarization unit 120 binarizes input multi-value RGB signal for each color in succession by using the error diffusion method. Its result is stored in the delay buffer 130. On the other hand, multi-value RGB digital signal input into the RGB/Y conversion unit 160 is converted into Y signal for each pixel in succession for the output to the binarization unit 2100. The conversion from the RGB signal into the Y signal is performed based on an expression: Y = 0.299 x R + 0.587 x G + 0.114 x B The Y signal input into the binarization unit 2100 is compared with a fixed threshold value for the binarization. Binarized Y signal is written into the frame memory 2170 or 2180. The frame memories 2170 and 2180 are subjected to alternating operation of writing and reading in the unit of frame, that is, while one of them is written, the other is read. Binarized Y signal is input into a change point extraction unit 2200. The change point extraction unit 2200 has a line buffer to create a 5 x 5 window for each pixel, compare it with binarized Y signal before one frame for each pixel, count the number of changed pixels, and compare it with the threshold, wherein if the number of changed pixels is greater than the threshold, that point is extracted as a change point. Before starting the process of scan lines, corresponding flags in the line flag memory 210 are reset. If any change point is extracted, the flag of the line flag memory 210 corresponding to the scan line of interest is set. If no change point exists within one scan line, the flag set in the line flag memory 210, if any, is reset. The partial write detection unit 220 monitors the flag status in the line flag memory 210, and if any flag is set, the partial write for the corresponding scan line is performed. In performing the partial write, the switch 140 is turned on, and location information concerning the scan line for the partial write is transmitted to the video frame memory 150 and the FLCD interface unit 230. As a result, binarized RGB signal of scan line corresponding to the scan line at which change point is detected is read from the delay buffer 130, and written into the video frame memory 150. Further, the FLCD interface 230 reads RGB binarization signals of corresponding scan lines in the video frame memory 150 to change the display states of the corresponding scan lines of the FLCD 30 based on the scan line data of the FLCD 30. If no flag is set in the line flag memory 210, the partial write detection unit 220 turns off the switch 140, wherein no partial write for RGB binarization signal of the corresponding scan line is performed. In this way, the display state for only the portion that has been changed is altered. (Fifth embodiment) Fig. 8 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In Fig. 8, like numerals refer to the parts having the same functions as in Fig. 7 of the embodiment 4. 2300, 2310 and 2320 are binarization units for the image, and 2330, 2335, 2340, 2345, 2350 and 2355 are frame memories. 2360, 2370 and 2380 are change point extraction units for detecting the change point between frames by making a comparison between input binarized signal and binarized signal before one frame stored in the frame memory. 480 is an OR circuit. RGB analog signal of 60Hz non-interlace from the computer 10 is input into the A/D conversion unit 110 via the terminal 100. Input binarized RGB analog signal is A/D converted into multi-value RGB digital signal for the input to image binarization unit 120, R multi-value signal being input into a binarization unit 2300, G multi-value signal into a binarization unit 2310, and B multi-value signal into a binarization unit 2320. The image binarization unit 120 binarizes input multi-value RGB signal for each color by using the error diffusion method. Its result is stored in the delay buffer 130. Input R signal into the binarization unit 2300 is compared with a fixed threshold value for the binarization. Binarized R signal is written into a frame memory 2330 or 2335. The frame memories 2330 and 2335 are subjected to alternating operation of writing and reading in the unit of frame, that is, while one of them is written, the other is read. Binarized R signal is input into a change point extraction unit 2360. The change point extraction unit 2360 has a line buffer to create a 5 x 5 window for each pixel, compare it with binarized R signal before one frame for each pixel, count the number of changed pixels, and compare it with the threshold, wherein if the number of changed pixels is greater than the threshold, that point is extracted as a change point, and 1 is sent out. If no change point exists within one scan line, 0 is sent out. Likewise, the change point is detected for B binarized signal and G binarized signal. The outputs from the change point extraction unit 2360 of R binarized signal, the change point extraction unit 2370 of G binarized signal and the change point extraction unit 2380 of B binarized signal are input into the OR circuit 480. The OR circuit 480 calculates the logical sum of these inputs for the output to the line flag memory 420. Before starting the process of scan lines, corresponding flags in the line flag memory 420 are reset. If the output of OR circuit 480 is 1, the flag of the line flag memory 420 corresponding to the scan line of interest is set. The partial write detection unit 220 monitors the flag status in the line flag memory 420, and if any flag is set, the partial write for the corresponding scan line is performed. In performing the partial write, the switch 140 is turned on, and location information concerning the scan line for the partial write is transmitted to the video frame memory 150 and the FLCD interface unit 230. As a result, binarized RGB signal of scan line corresponding to the scan line at which change point is detected is read from the delay buffer 130, and written into the video frame memory 150. Further, the FLCD interface 230 reads RGB binarized signals of corresponding scan lines in the video frame memory 150 to change the display states of the corresponding scan lines of the FLCD 30 based on the scan line data of the FLCD 30. If no flag is set in the line flag memory 420, the partial write detection unit 220 turns off the switch 140, wherein no partial write for RGB binarized signal of the corresponding scan line is performed. In this way, the display state for only the portion that has been change is altered. (Sixth embodiment) Fig. 9 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In Fig. 9, like numerals refer to the parts having the same functions as in Fig. 7 of the embodiment 4. 2500 is a low pass filter unit. 600 is an analog RGB/Y conversion unit for generating analog Y signal which is a luminance signal from analog RGB signal. 610 is an A/D conversion unit for A/D converting analog Y signal by subsampling the scan lines odd-numbered at half the frequency to create multi-value digital Y signal. 2530 is a binarization unit for the image. 2540, 2545 are frame memories having one-half the image size of display in vertical and horizongal directions. 2550 is a change point extraction unit for detecting the change point between frames by comparison between input binarized signal and binarized signal before one frame stored in the frame memory. 670 is a line flag memory the flags of which can be turned on or off for each scan line odd-numbered. 680 is a partial write detection unit for detecting whether or not the partial write is performed from the content of the line flag memory 670 to control the partial write regarding the location of partial write. 690 is a delay buffer. RGB analog signal of 60Hz non-interlace from the computer 10 is input into the A/D conversion unit 110 and the low pass filter unit 2500 via the terminal 100. Input multi-value RGB analog signal is A/D converted into multi-value RGB digital signal in the A/D conversion unit 110 for the input to image binarization unit 120. The image binarization unit 120 binarizes input multi-value RGB signal for each color in succession by using the error diffusion method. Its result is stored in the delay buffer 690. On the other hand, the low pass filter 2500 causes each RGB signal to pass through the low pass filter to get the signal having half the frequency. The RGB signal having the frequency halved is input into analog RGB/Y conversion unit 600 for the conversion into analog Y signal, and then output to the A/D conversion unit 610. The A/D conversion unit 610 A/D converts analog Y signal by subsampling the scan lines odd-numbered at half the frequency to create multi-value digital Y signal for the input into the binarization unit 2530. Input Y signal into the binarization unit 2530 is compared with a fixed threshold value for the binarization. Binarized Y signal is written into a frame memory 2540 or 2545. The frame memories 2540 and 2545 are subjected to alternating operation of writing and reading in the unit of frame, that is, while one of them is written, the other is read. Binarized Y signal is input into a change point extraction unit 2550. The change point extraction unit 2550 has a line buffer to create a 3 x 3 window for each pixel, compare it with binarized Y signal before one frame for each pixel, add changed pixels by weighting as shown in Fig. 5, compare its sum with a threshold, wherein if the sum is greater than the threshold, that point is extracted as a change point, and the flag in the line flag memory 560 corresponding to the scan line of interest is set. Before starting the process of scan lines, corresponding flags in the line flag memory 560 are reset. If no change point exists within one scan line, the flag in the line flag memory 560 for the scan line of interest remains reset. The partial write detection unit 680 monitors the flag status in the line flag memory 670, and if any flag is set, the partial write for the corresponding scan line is performed. In performing the partial write, the switch 140 is turned on, and location information concerning the scan line for the partial write is transmitted to the video frame memory 150 and the FLCD interface unit 220. If the partial write is not performed at the previous scan line odd-numbered, the partial write detection unit 680 reads data of the scan line of interest odd-numbered and data of the scan lines even-numbered before and after that scan line of interest from the delay buffer 690. The location information, including the location of the scan line of interest odd-numbered and the locations of the scan lines even-numbered before and after that scan line of interest, is transmitted to and written into the video frame memory 150. At the same time, location information is also transmitted to the FLCD interface 230, which reads RGB binarized signals of corresponding scan lines in the video frame memory 150 to change the display states of the corresponding scan lines of the FLCD 30 based on the scan line data of the FLCD 30. If no flag is set in the line flag memory 560, the partial write detection unit 570 turns off the switch 130, wherein no partial write for RGB binarized signal of the corresponding scan line is performed. In this way, the display state for only the portion that has been changed is altered. Input signal is not limited to the RGB analog signal, but may be a multi-value digital signal, or further an image signal for any of color components other than R, G, B. Also, it is not limited to the color. The signal for detection of change point is not limited thereto, but may include a chromaticity signal, and is not also limited to luminance and chromaticity. The binarization technique for image is not limited thereto, but may be other binarization methods such as a dither method or an average density preserve method. Binarization technique of image for the detection of interframe change is not limited thereto, but may be other binarization techniques such as a dither method. The extraction method of change point is not limited thereto, but it is conceived that the image may be divided into blocks, or the change in a unit of pixel may be utilized. The unit of the partial write is not limited to a scan line unit, but may be a block or pixel unit. The configuration of the frame memory is not limited thereto, but may be of a plurality of line buffers or other configuration. The subsampling technique for the detection of change point is not limited thereto, but may be a subsampling or filter process such as projection performed before the A/D conversion. The technique for the display is not limited to the FLCD, but may be a display having memory function. Quantization has been described in binarization, but it is conceived that greater degree of quantization, for example, ternary based on two thresholds, may be used. As above described, with the provision of binarization means for the display and binarization means for the detection of interframe change, it is possible to provide the display with high definition as well as improving the precision for the detection of interframe change. Also, by converting the input signal into image signal such as luminance, it is possible to facilitate the extraction of a cursor, mainly composed of black and white, and reduce the memory capacity for the detection of interframe change, thereby attaining the lower costs of the device. Also, owing to subsampling the image signal, it is possible to attain the lower costs of the device, reduce the memory capacity for the detection of change point because of sampling less than the image size for display, eliminate the noise contained in the analog signal by the use of a low pass filter, resulting in the improvement in detection precision of interframe change. As above described, according to the above embodiments 4 to 6 of the present invention, it is possible to display an excellent image by partially rewriting the display image. (Seventh embodiment) A preferred embodiment will be described below. Fig. 10 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In this embodiment, the signal is a component RGB non-interlace 60Hz signal. Fig. 10 shows the details of the image process unit 20 as shown in Fig. 2. 100 is an input terminal of RGB analog output signal from the computer 10, and 110 is an A/D conversion unit for A/D converting input RGB analog signal to create multi-value digital RGB signal. RGB analog signal is a 60Hz non-interlace signal. 120 is an image binarization unit for converting multi-value RGB digital signal into signal, one bit for each RGB. Herein, the binarization technique for the image is a pseudo-half tone process suitable for representing the half tone, including, for example, an error diffusion method. 130 is a delay buffer composed of an FIFO memory to effect synchronization. 140 is a switch which is turned on or off by a control signal. 150 is a frame memory for storing data, one bit for each RGB, of each pixel, and which is comprised of, for example, two-port RAM. 4160 is an RGB/YCbCr conversion unit for converting multi-value digital signal RGB into a luminance Y signal and chrominance Cb, Cr signals. 4500 to 4540 are low pass/subsampling units for performing the the low filter process as well as the subsampling of picking up the image signal. 4550, 4560, 4570 are buffers for temporarily storing Y, Cb, Cr signals after the low pass/subsampling process for each frame, respectively. 4360, 4370, 4380 are absolute value differential units for calculating the absolute value differential in pixel value at the same location between stored image signal before one frame and the next image signal. 4390, 4400, 4410 are binarization units for binarizing the absolute value differential obtained by 4550, 4560, 4570 at threshold TH1, TH2, TH3, respectively, wherein if the pixel is 1, the pixel is determined to have been changed. These binarized signals are ORed in OR circuit 4480, wherein if the line with "1" exists, the flag is set in the line flag memory 4420. 4420 is a line flag memory for enabling a flag to be turned on or off for each scan line. 220 is a partial write detection unit for detecting whether or not the partial write is performed from the content of line flag memory 420 as well as controlling the partial write regarding the location of partial write. 230 is an FLCD interface for reading the content of video frame memory 150 for the output to the FLCD 30 via terminal 240. RGB analog signal of 60Hz non-interlace from the computer 10 is input into the A/D conversion unit 110 via the terminal 100. Input multi-value RGB analog signal is A/D converted into multi-value RGB digital signal for the input to image binarization unit 120 and RGB/Y conversion unit 4160. The image binarization unit 120 binarizes input multi-value RGB signal in succession for each color by using the error diffusion method. Its result is stored in the delay buffer 130. On the other hand, multi-value RGB digital signal input into the RGB/Y conversion unit 4160 is converted into Y, Cb, Cr signals in succession for each pixel. The conversion from RGB signal to YCbCr signals is performed by the following expressions: Y = 0.299 x R + 0.587 x G + 0.114 x B Cb = (B-Y) x 0.564 + 128 Cr = (R-Y) x 0.713 + 128 Y signal is passed through the low pass filter process in the low pass/subsampling unit, and subsampled for the pixel values odd-numbered at half frequency. Fig. 11 shows an example of the low pass filter. For all the pixels, convolution operation is performed by weighting pixel of concern with 2 and left and right pixels with 1. Thereafter, odd-numbered pixels are subsampled. Buffer 4550 stores Y data having one-half the number of pixels in each line for one screen. For Cb, Cr signals, the same process is performed, except that this low pass/subsampling process is repeated twice at 4510, 4520 and 4530, 4540. That is, for the Cb, Cr signals, data having one-quarter the number of pixels for each line is stored in the buffers 4560, 4570 for one screen, respectively. The detection of changed pixels is performed separately for each of Y, Cb, Cr signals in the absolute value differential unit 4360, 4370, 4380 and the binarization unit 4390, 4400, 4410, but the sampling interval is different between Y and CbCr. That is, since it is believed that Y signal contains the most important information in the respects of variation and movement among the color image components, it has a two times greater detection precision in terms of variation than CbCr. To increase the detection precision, it is desirable not to perform subsampling if possible, but because the buffer capacity is increased by taking differential from the previous frame, 1/2 subsampling for Y and twice 1/2 or 1/4 subsampling for CbCr are made in this embodiment. For the CbCr signals, the portion having less variation in luminance with the color changed is mainly detected. For the Y signal, pixel values subsampled with the previous frame stored in the buffer 4550 are stored by one frame. The absolute value of the differential in pixel value between the current frame and the previous frame is calculated sequentially in the absolute value differential unit 4360, and compared with a fixed threshold TH1 for the binarization in the binarization unit 4390. If the absolute value of the differential is greater than the threshold TH1, "1" is output, or otherwise, "0" is output. For Cb, Cr signals, the same process is performed, wherein binarization is performed using the thresholds TH2, TH3 in the binarization units 4400, 4410. It suffices that the thresholds TH1 to TH3 are greater than the analog noise. There are various ways for determining the thresholds TH1 to TH3. For example, an analog signal having a single luminance (herein, 128 is supposed), output beforehand, is input via the terminal 100, converted into digital data in the A/D conversion unit 110, input to the RGB/YCbCr conversion unit 4160 for the conversion into the YCbCr signal, and written into the buffers 4550, 4560, 4570. It is also possible that the absolute value differential units 4360, 4370, 4380 calculate the absolute value differential from the fixed value (herein, 128), but not the input from the RGB/YCbCr conversion unit 4160, with its maximum value defined as the threshold TH. If binarized absolute value differential signal is equal to 1, that signal is extracted as a change point. The logical sum for the change point of YCbCr is taken in the OR circuit 4480, and if there is any change, the flat "1" is set in the line flag memory 4420. The line flag memory 4420 resets the flag, before starting the process of scan lines for each frame. If any one change point is extracted, the flag for that line is set to "1". If no change point exists within one scan line, the corresponding flag in the line flag memory is set to "0". The partial write detection unit 220 monitors the flag status in the line flag memory 4420, and if any flag is set, the partial write for the corresponding scan line is performed. In performing the partial write, the switch 140 is turned on, and location information concerning the scan line for the partial write is transmitted to the video frame memory 150 and the FLCD interface unit 230. As a result, binarized RGB signal of scan line corresponding to the scan line at which change point is detected is read from the delay buffer 130, and written into the video frame memory 150. Further, the FLCD interface 230 reads RGB binarized signals of corresponding scan lines in the video frame memory 150 to change the display states of the corresponding scan lines of the FLCD 30 based on the scan line data of the FLCD 30. If no flag is set in the line flag memory 4420, the partial write detection unit 220 turns off the switch 140, wherein no partial write for RGB binarization signal of the corresponding scan line is performed. In this way, the display state for only the portion that has been changed is altered. While in the seventh embodiment the detection of change point was performed for the luminance and chrominance signals Y, Cb, Cr with the luminance signal Y weighted, it will be appreciated that it can be performed using the luminance and chrominance signals of LUV, L*a*b*, YIQ in the same way. (Eighth embodiment) Fig. 12 is a diagram showing the configuration of an image process unit in an image display system according to this embodiment. In Fig. 12, like numerals refer to the parts having the same functions as in Fig. 10 of the seventh embodiment. Fig. 12 is an embodiment wherein the signal for the detection of change point is an RGB signal itself. The RGB signal digitized by the A/D conversion unit 110 is directly input into the low pass subsampling units 4510, 4500, 4530. Herein, since it is believed that the G signal contains the most important component for detecting the variation and movement, the subsampling rate is 1/2 for R and 1/4 for B. By doing so, it is possible to reduce the buffer memory, like Y, CbCr, as well as detecting the change point in high precision. While the subsampling was 1/2 for each scan line, it will be appreciated that the sampling may be 2:1 in horizontal and vertical directions for two-dimensional low pass filter, as shown in Fig. 5. As above described, according to the above embodiments of the present invention, with the provision of binarization means for the display and differential means for the detection of interframe change, it is possible to rapidly update the change portion in the display. In particular, by detecting the change between frames by differently weighting the components of signals RGB and YCbCr constituting the color for the detection of interframe change, it is possible to facilitate the extraction of a cursor with a luminance difference with respect to the surroundings, reduce the memory capacity for the detection of interframe change as well as the costs of the apparatus. Also, owing to subsampling the image signal, it is possible to attain the lower costs of the device, reduce the memory capacity for the detection of change point because of less sampling than the image size of display, and eliminate the noise contained in the analog signal by the use of a low pass filter, resulting in the improvement in detection precision of interframe change. As above described, it is possible to detect a changed portion, for example a moving portion, of the input image efficiently. FLCD 30 (Fig. 2) used in the above embodiments is as described in U.S. Patent No. 4,964,699, and composed of a ferroelectric liquid crystal having a memory function. This FLCD can rewrite a partial area of a frame in accordance with the output signal. It will be understood that the present invention is not limited to the above embodiments, but various variations and modifications can be made within the scope of claims.

Claims: A display control apparatus, for controlling halftone display, comprising: input means (100) for inputting image data; quantisation means (10) to quantise the image data by using a pseudo-halftone processing method; detection means (160-190;300-380;600-650; 160,2100-2200;2300-2380; 600,610,2530-2550;4160,4500-4380) for detecting changes between image data representing first and second successive image frames; generation means (200-220; 390-420, 220; 660-680; 210,220; 480,420,220; 670,680; 4390-4420, 4480,220) responsive to said detection means, to generate a control signal to control rewriting of a partial area of a display; and output means (150,230-240) co-operative with said quantisation means, and said generation means, to output quantised image data selected under the control of said control signal; wherein said detection means is arranged between said input means and said quantisation means to receive and operate on image data prior to it being quantised by said quantisation means. A display control apparatus according to claim 1 wherein said detection means comprises: conversion means (160) to convert the image data to luminance data; first and second frame memories (170,180) arranged for alternate reading and writing of the luminance data of successive image frames, and difference means (190), co-operative with said conversion means and said first and second frame memories, to obtain the absolute value difference between each of the luminance data of the current and immediately preceding frames; and said generation means comprises: binarising means (206) for binarising the difference data obtained by said difference means, line flag memory means (210), responsive to said binarising means, for providing a flag for each scan line of the display which flag is on or off depending on the binarisation results for that line of data; and signalling means (220), responsive to said flags, to generate said control signal. A display control apparatus according to claim 2 including a first analogue-to-digital conversion means (110) arranged between said input means (100) and said quantisation means (120), and wherein said conversion means is arranged to access image data preceding said first analogue-to-digital conversion means, a second analogue-to-digital conversion means (610) arranged following said conversion means, and low pass filter means (620) arranged with its input connected to said second analogue-to-digital conversion means and its output connected to said first and second memories and said difference means. A display control apparatus according to claim 1 wherein said detection means comprises:- respective first and second frame memories (300,310, 320 & 330, 340 & 350) for each of three colour channels for alternate reading and writing of colour component image data of successive image frames; respective difference means (360,370,380), in each colour channel co-operative alternately with respective first and second memories to obtain the absolute value difference between colour component image data received from said input means for a current frame and colour component image data stored in one of the respective first and second memories for the immediately preceding frame; and said generation means comprises: respective binarising means (390,400,410), in each channel, for binarising the difference data obtained by said respective difference means; an OR gate (480) for combining the binarisation results of each of said respective binarisation means; followed by line flag memory means (420) responsive to said OR gate, for providing a flag for each scan line of the display which flag is on or off depending on the binarisation results for that line of data; and signalling means (220), responsive to said flags, to generate said control signal. A display control apparatus according to claim 1 wherein said detection means comprises: conversion means (160) to convert access image data to luminance data; binarisation means (2100) to binarise said luminance data; first and second frame memories (2170,2180) arranged for alternate reading and writing of the binarised luminance data of successive frames; and difference means (2200) co-operative with said binarisation means and said first and second memories to obtain the difference between each of the binarised luminance data of the current and immediately preceding frames; and said generator means comprises: line flag memory means (210), responsive to said difference means, for providing a flag for each scan line of the display, which flag is on or off depending on the difference results for that line of data; and signalling means (220) responsive to said flags, to generate said control signal. A display control apparatus according to claim 5 including a first analogue-to-digital conversion means (110) arranged between said input means (100) and said quantisation means (120), and wherein said conversion means (600) is arranged to receive image data preceding said first analogue-to-digital conversion means via a low pass filter means (2500); and a second analogue-to-digital conversion means (2530) interposed between said conversion means (160) and said binarisation means (2530). A display control apparatus according to claim 1 wherein said detection means comprises: respective binarisation means (2300,2310,2320) for each of three colour channels to binarise respective colour component data of the accessed image data; respective first and second frame memories (2330 & 2335, 2340 & 2345, 2350 & 2355) for alternate reading and writing of the colour component data of successive frames; and respective difference means (2360, 2370, 2380) co-operative with said respective binarisation means and said respective first and second frame memories, to obtain the difference between each of the colour component data of the current and immediately preceding frames; and said generation means comprises: an OR-gate (480) to combine the difference results; line flag memory means (420) for providing a flag for each scan line of the display, which flag is on or off depending on the difference results for that line of data; and signalling means (220) responsive to said flags, to generate said control signal. A display control apparatus according to any preceding claim for controlling a liquid crystal display. A display control apparatus according to claim 8 for controlling a liquid crystal display having a memory function. A display control apparatus according to claim 9 for controlling a ferroelectric liquid crystal display. A display control apparatus according to any preceding claim combined with a display unit including said display. A method of processing image data and of controlling an image display to partially rewrite an image, comprising steps of: inputting image data, quantising the image data by pseudo-halftone processing, detecting changes between image data representing first and second successive image frames; generating a control signal to control partial rewriting of an image on the image display in response to the detection of the changes aforesaid; and selecting and outputting quantised image data under the control of the control signal; wherein said step of detecting changes between image data is performed on input image data prior to quantising the input image data by pseudo-halftone processing.

Inventors: MAEDA MITSURU, YOSHIDA TADASHI, MAEDA, MITSURU, YOSHIDA, TADASHI, Maeda, Mitsuru, c/o Canon Kabushiki Kaisha, YOSHIDA, TADASHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: G09G3
IPC codes: G09G3