POWER DRIVER CIRCUIT

Abstract: A power driver circuit for turning a semiconductor switching device on and off in response to receipt of a control signal includes a trigger circuit (Q2) that turns on a latching switch (SCR1) at a speed that is independent of the rate of change of the control signal. The trigger circuit (Q2) is responsive to the control signal to apply a current from the semiconductor switching device to the latching switch (SCR1). A high speed SCR may be used as the latching switch and may be triggered by a small trigger current from the gate of the semiconductor switching device fed to both the anode and cathode gates of the SCR. High speed diodes may also be used to increase the speed of the circuit. The power driver circuit improves the efficiency of the semiconductor switching device by decreasing the time the switching device spends in transition between its two steady states.

Description: POWER DRIVER CIRCUIT BACKGROUND OF THE INVENTION The present invention relates to power driver circuits for controlling the operation of a semiconductor switching device in response to control signal inputs from a control circuit. In one aspect, the present invention relates to a method and device for turning on a latching switch in the power driver circuit at a speed that is independent of the rate of change of the control signal input voltage. In another aspect, the present invention is responsive to the control signal to control the operation of the latching switch by the semiconductor switching device. It is to be understood that the terms used to describe elements of various embodiments of the present invention are not intended to limit the invention to those particular named elements where a functional equivalent exists. For example, even though the term "MOSFET" is used in the following description to describe the semiconductor switching device, the present invention also relates to other semiconductor switching devices such as FETs, IGBTs, MOS controlled thyristors (MCTs) , BJTs, triacs, SCRs, GTO thyristors, and SITs. The gate of the MOSFET has equivalent structures in these devices and reference to a gate herein includes the equivalent structure in these devices. Further, by way of example, the term "SCR" as used in the following description also refers to other latching switches as are known in the art. Semiconductor switching devices typically are used to regulate power that is to be switched on and off at a frequency determined by a control circuit. A power driver circuit typically acts as a buffer between the control circuit and the switching device and translates control signals from the control circuit into signals that can turn the switching device on and off at the requisite frequency. For example, a switchmode power supply (a semiconductor switching device) may be operated by a pulse transformer (a control circuit) at 300 kHz through a power driver circuit. As is known, semiconductor switching devices consume more power during the period of transition between its two on and off steady states than during either the on or off periods. Therefore, one way to improve the efficiency of a switching device operating at a particular frequency is to decrease the length of the periods in which the switching device is in transition. The background of the present invention may be further understood with reference to Figure i"j in which a power driver circuit of the prior art may be seen. A FET 10 may be driven by a control circuit 12 through a power driver circuit 14. To turn the FET 10 on, current is provided to the gate 16 of the FET thereby allowing the FET to conduct a current between its source 18 and drain 20. To turn the FET off and stop current flow between its source and drain, current is pulled from the gate 16. The control signal is applied through Dl to charge Cl in one cycle and the FET is turned on when a control signal from control circuit 12 in a second cycle is routed through D2 and D3 to the base of BJT Ql, turning Ql on. When Ql is on, current from Cl is applied to the gate 16 to turn on the FET. The FET is turned off when the current at gate 16 is drained through a latching switch 22 (the latching switch in Figure 1 is formed by the combination of BJTs Q2 and Q3) . The current from the FET gate 16 is drained when latching switch 22 is turned on with latching switch 22 being turned on when the voltage across R2 is Ql V BE below the gate voltage of the FET. In other words, R2 provides a trigger current for turning on the latching switch 22. The rate at which the FET turns off, and thus the length of the period of transition, is controlled by the speed at which the charge on the gate 16 is drained. The speed at which the charge is drained from the gate 16 is, in turn, controlled by the speed at which latching switch 22 turns on. Typically, a latching switch, such as an SCR, must build up a charge before turning on. The trigger of the prior art (R2) which controls conduction of the latching switch derives current from the control signal, and thus the speed at which the latching switch conducts is a function of the character in the control signal. In contrast, the latching switch of the present invention is independent of the character of the control signal. More specifically, the latching switch that controls the turn off rate of the FET is turned on immediately following a change in polarity of the control signal by drawing a small portion of the current from the FET as a trigger current to both the anode gate and the cathode gate of the latching switch. In contrast to the known prior art which provides a triggering signal to only one side of the latching switch, triggering signals are provided to both sides of the latching switch to speed its conditioning for conduction. This distinction may be more clearly seen with reference to Figures 2 and 3 where the present invention (Figure 2) uses a trigger signal from the FET gate to turn on latching switch 2 in contrast to the prior art (Figure 3) , where the switch 2 is turned on by the control signal. With reference to Figure 3, power from the control circuit (possibly by way of capacitor Cl of Figure 1) is applied through Switch 1 to the gate of the FET. Conduction (or turn on) of the FET is thus achieved by the application of a control signal from the control circuit to the control terminal of Switch 1, and the application of a control signal to the trigger switch which insures non-conduction of the Switch 2 which permits the accumulation of charge on the FET gate. The turn off of the FET is achieved by reversal of the conduction states of Switch 1 and Switch 2 under the control of the control circuit, Switch 1 opening to remove power to the FET gate and Switch 2 closing to drain the charge from the FET gate. However, the trigger switch is not immediately responsive to the reversal of the polarity of the control signal and depends on its amplitude. Thus the initiation of FET turn off is a function of the character of the control signal and lags the polarity reversal. As shown in Figure 2, the turn on of the FET is achieved in the same manner as described above in connection with Figure 3. However, turn off is accelerated because the trigger switch in Figure 2 is immediately responsive to the polarity reversal of the control circuit without regard to its amplitude to apply a trigger signal from the gate of the FET to Switch 2, thereby immediately initiating conduction of Switch 2. Turn off of the FET is thus independent of the character of the control signal. Accordingly, it is an object of the present invention to provide a novel method and device for"improving the efficiency of semiconductor switching devices. It is a further object of the present invention to provide a novel method and device for providing triggering a latching switch in a power driver circuit. It is yet a further object of the present invention to provide a novel method and device in which current from the semiconductor switching device gate is used to initiate operation of a latching switch in a power driver circuit. It is still a further object of the present invention to provide a novel method and device for decreasing the length of the periods of transition between the two steady states of a semiconductor switching device. It is another object of the present invention to provide a novel power driver circuit in which a high speed diode and a high speed SCR contribute to decreasing the length of the period of transition between the two steady states of a semiconductor switching device. These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings and the following detailed description of preferred embodiments. DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic circuit diagram of a power driver circuit of the prior art. Figure 2 is functional block diagram of the operation of the power driver circuit of the present invention. Figure 3 is functional block diagram of the operation of the power driver circuit of the prior art as illustrated in Figure 1. Figure 4 is a schematic circuit diagram of one embodiment of the power driver circuit of the present invention. Figures 5A-C schematically illustrate the sequence of operation of the circuit of the present invention. Figure 6 is a schematic circuit diagram of an embodiment of the present invention with a pulse'"transformer as the control circuit. Figure 7 is a circuit diagram of an embodiment of the present invention with a unipolar transformer as the control circuit. Figure 8 is a circuit diagram of an embodiment of the present invention with a PWM current booster as the control circuit. Figure 9 is a schematic circuit diagram of a latching switch of the prior art that may be used in the circuit of the present invention. Figure 10 is a plan view of a diode structure that may be used in the circuit of the present invention. Figure 11 is circuit diagram of the diode illustrated in Figure 10. Figure 12 is a graph depicting current and voltage of diodes that may be used in the present invention. Figure 13 is plan view of a diode structure of the prior art. Figure 14 is further embodiment of the diode illustrated in Figure 10 that may be used in the circuit of the present invention. Figure 15 is a graph depicting the rise times versus load capacitance for the circuit of the present invention and for circuits of the prior art. Figure 16 is a graph depicting the fall times versus load capacitance for the circuit of the present invention and for circuits of the prior art. DESCRIPTION OF PREFERRED EMBODIMENTS With reference now to the figures in which various embodiments of the power driver circuit of the present invention are illustrated, the various pin numbers depicted therein refer to connection pins that are found in a chip embodying the present invention and it is to be understood that the invention is not limited to this pin arrangement. With reference now to Figure 4, the circuit of the present invention may include supply pin PI and ground pins P4 and P5, which are considered the reference terminals. A power input on pin P7 is connected to the supply pin PI and the ground pin P4 by diodes Dl and D5 respectively. A control input pin P2 is connected to the control terminal of an output switch, which is illustrated as transistor Ql, by diodes D2 and D3. The collector-emitter current path of Ql is connected between the supply pin PI and a source output pin P8 and is desirably capable of sourcing at least 6 amperes of current. The second output switch is illustrated as SCRl having its anode connected to a sink output pin P3 and its cathode connected to the ground pin P5. Resistor Rl connects the cathode to the cathode gate CG of SCRl and resistor R2 connects the anode to the anode gate AG of SCRl. A trigger circuit, which includes PNP transistor Q2, is connected across the anode gate AG and cathode gate CG. A diode D6 connects the emitter of Q2 to the anode gate AG. A diode D4 connects the base of Q2 to the control pin P2. A resistor R4 connects the base of Ql to sink output pin P3 via resistor R2. The power driver circuit of Figure 4 provides separate outputs pin P8 and pin P3 for sourcing and sinking current respectively. The SCRl is used to sink large currents, desirably at least 10 amperes. When the input goes low on pin P2, resistor R3 provides base drive for Q2. Transistor Q2 triggers SCRl at both the anode and cathode gates. This triggering sequence begins as soon as D4 becomes reverse biased. Thus, the triggering delay time is independent of the input fall time. Resistor R4 provides a base discharge path for Ql. Diode D6 increases the input hysteresis to reduce the chances that ringing at the input or output will trigger the SCR. Resistors Rl and R2 remove excess stored charge from the SCR and also helps prevent false triggering. Diode D5 clamps the input low voltage. A high input turns on Ql. Diodes D2 and D3, along with Dl, prevent Ql from saturating. Diode Dl also provides a means of passing charge from the input pin P7 to the supply pin PI. The operation of the present invention may be more clearly seen with reference to Figures 5A-C in which the sequence of operation is illustrated. As seen in' Figure 5A, the FET is turned on when current is provided through transistor Ql to the FET gate. Transistor Ql is on when the control signal is positive. Transistor Q2 and SCRl are not on. As seen now in Figure 5B, when the control signal first goes negative, a small amount of trigger current is provided to both the anode gate and cathode gate of SCRl from the FET gate to begin turning SCRl on (i.e. , by building up the charge in the SCR) . Trigger current flow is through resistor R2, diode D6 and emitter- collector path of transistor Q2 which has been turned on by the change of polarity of the control signal. Finally, as seen in Figure 5C, SCRl is turned on and drains the charge from the FET gate. One of the applications for the power driver circuit of Figure 4 driver is with a push-pull driven pulse transformer. The circuit of the present invention may be seen connected to 1 such a transformer in Figure 6. The pulse transformer Tl provides the control signal at pin P2 and the charge for the MOSFET gate at pin P7. The transformer primary is driven bidirectionally to provide core reset. Many pulse width modulation (PWM) circuits provide complimentary outputs so each end of the primary winding is alternately connected to the PWM chip supply or ground. This generates a bidirectional signal in the transformer. Capacitor C IN provides volt-second balancing for the transformer secondary by charging to the .average output voltage. A similar capacitor is usually required in series with the transformer primary. These capacitors are usually sized such that their voltage changes a fraction of a volt over a cycle. They transfer charge equal to the MOSFET gate charge plus the product of the circuit input current times "on" time. When the transformer output goes positive, the MOSFET gate is pulled up. Capacitor C s acts as the power supply providing the gate charge. It is sized to hold at least ten times the MOSFET gate charge so its voltage change over a cycle is a fraction of a volt. Resistor R^ tailors the impedance matching between the transformer and the MOSFET. Its value is multiplied by the NPN current gain of Ql, typically 200, at the control input pin P2. Therefore, during the low-to-high transition, the transformer is lightly loaded minimizing signal timing delays due to leakage inductance. The resistor o ^. also damps oscillations that could inadvertently trigger the off SCRl. After the MOSFET gate is brought high, charge is transferred from the transformer to the storage capacitors C s through the diode Dl connected between the power input pin P7 and the supply pin PI. This charge storage permits the MOSFET driver to source peak currents much larger than the maximum current rating of the PWM circuit driving the transformer primary. When the transformer polarity reverses, the SCRl is triggered on which rapidly discharges the MOSFET gate. The diode D5 r connected to the power input pin P7, clamps the input P2 about 1 volt below the MOSFET source and provides a path for transformer core and C m reset currents. Operation for the first few cycles of start up is a little different. Since the MOSFET gate supply is initially discharged, the pulse transformer supplies current for the MOSFET gate and supply capacitor C s at the same time. This means that for the first cycle the MOSFET is not turned on as hard or as quickly as normal, but this is not usually problematic. However, as long as the gate is above 3V, the turn off function works the same. The MOSFET driver circuit draws no quiescent supply current so any charge on C s remains until the next low-to-high transition. One significant advantage of this approach is that none of the MOSFET driver circuitry requires any precharging or quiescent supply current to begin operating. If precharging or start-up current was required, it would most likely have to be supplied from a high voltage DC supply. This would degrade the overall power supply efficiency or require some extra circuit and cost to disable the precharge supply once the main power supply began operation. It is possible to set up a latch state that discharges the storage capacitor C s If a positive going control signal turning on Ql occurs before the SCRl has recovered, then both Ql and SCRl can be on. The resulting * cross conducting current will discharge the storage capacitor C s . Resistor R ouτ limits the peak current to a safe value and the circuit will unlatch when either the capacitor is discharged or the control input is taken low. This latch will not occur if the low-to-high transition is approximately 1 μS after the previous high-to-low transition. This SCR recovery time limits the maximum frequency of operation. Figure 6 is but one example of the use of the power driver circuit of Figure 4. Other variations may include smaller diodes connected in parallel with diodes Dl and D5 external to the integrated circuit of the driver. These diodes reduce the recovery time for input currents above 100 mA, for example. Similarly, circuit variations may include elimination of the input capacitor C IN and the storage capacitors C s and their replacement by appropriate resistors. R oατ would also be eliminated, albeit with decreased turn-on time of the MOSFET. In high wattage power supply, several MOSFETs may be connected in parallel requiring the use of a unipolar transformer pulse driver for the total gate currents. As illustrated in Figure 7, the unipolar transformer T2 is controlled by FET 2 and includes diodes D10 and Dll and resistor RIO in parallel with primary of the transformer T2. Zener diode Dll clamps the back swing of the primary which also limits the back swing in the secondary. The resister RIO continues to pass the core of demagnetizing current after he reverse voltage drops below the zener conduction voltage. Because of the clamping operation of the zener diode Dll, the clamping diodes Dl and D5 of the driver are not needed and pin P7 may be left open. The external diode D2 which connects the secondary of the transformer T2 to pin PI, charges the storage capacitor C s _ The controller input P2 is also connected to the secondary transformer T2 and the diodes D2, D3, Dll must be capable of sustaining the back swings voltage of the transformer. As an alternative, the diode D12 may connect the output of the secondary transformer T2 to both the power input pin P7 and the control input pin P2. Thus, diode D12 prevents the driver circuit from clamping the reverse voltage at one diode drop. The driver of Figure 4 will interface to most PWM chips providing greater gate drive capacity than the PWM chip alone. As illustrated in Figure 8, the driver circuit supply V s is the same as that for the PWM circuit. The resister R f provides a low impedance gate discharge path once the SCRl has turned off. The resistor R Sf along with capacitor C s provides filtering to reduce switching spikes on the supply line. It also prevents the driver circuit from collapsing the PWM supply should it be set into a latch state. The capacitor C s should hold about 10 times the charge as the MOSFET gate of FET1. The power driver circuit of the present invention has been implemented in an integrated circuit in a minimal amount of space. The integrated circuit was built in a high frequency complimentary bipolar process having dielectric isolation. A circuit has been built when the diodes have a maximum of 5,000 mils 2 . The output transistor Ql was designed to be capable of at least 2 amps without saturation and with its interconnect required about 1900 mils 2 ' An SCR which may find application in the present invention and is capable of fast turn on and fast turn off is illustrated in Figure 9. The SCR has a 25 volt blocking voltage, can handle over 10 amps, can turn on in under 10 nanoseconds and takes up approximately 300 mils 2 - The SCR includes high speed, high gain vertical PNP transistor Ql and NPN transistor Q12 connected in SCR arrangement with their bases and collectors connected together, with the emitter of Qll being the anode and emitter of Q12 being the cathode. Connected in parallel between their emitters, collectors and bases respectively of vertical transistors Qll and Q12 are slower, low gain lateral PNP transistor Q13 and NPN transistor Q14. A trigger current first turns on the vertical devices Qll and Q12 which drives the lateral devices Q13 and Q14. The forward voltages at turn- on creates an electric field that aids moving excess charge into the device interior. Thus, the SCR turns on quickly. To turn off the SCR, ' two more lateral transistors, namely NPN transistor Q15 and PNP transistor Q16, operate to short out the anode gate-anode junction and the cathode gate-cathode junction when the SCR is on. The coϊlector-emitter path of Q15 connects the anode and anode gate and its base and is controlled with the cathode gate or collector of Qll. The collector-emitter path of Q16 connects the cathode and cathode gate and its base and is controlled by the anode gate or collector of Q12. Transistor Q15 conducts a large fraction of the electrons injected by Q12 and Q14 to the anode terminal reducing the base drive to Qll and Q13. This limits the charge stored in the bases of Qll and Q13. Transistor Q6 similarly shunts the hole current to the cathode. The SCR structure including transistors Qll, Q12, Q13, Q14 and described in detail U.S. Patent 4,979,011 which is incorporated herein by reference. The fast recovery SCR including transistors Qll, Q12, Q15 and Q16 by themselves and in combination with the fast turn on portions Q13 and Q14 are described in U.S. Patent 5,086,242 also incorporated herein by reference. The diodes Dl through D5 of the circuit of Figure 4 may limit the speed of the circuit. An improved diode of sufficient speed and breakdown capacity is illustrated in Figure 10. The anode region AP is formed by a P-type region and a cathode region CN is formed by a N-type region, both in an illustrated N-substrate. The anode contact includes a P+ portion AP+, and an N+ portion AN+. Similarly the cathode contact includes a P+ portion CP+, and an N+ portion CN+. The contact regions have common boundaries. The diode of Figure 10 has less charge storage for a given current because the addition of the opposite type diffusion in the anode and cathode contacts. The N+ contact diffusion AN+ in the P anode AP increases the electron diffusion current density in the AP material for a given concentration in the N region. The diode behaves like it has very shallow contact diffusions except that the diode breakdown voltage is not reduced. The diode forward voltage is higher because of the reduction in carrier concentration in the N-region. But since both holes and electrons contribute to the terminal current, the voltage drop does not increase proportionally to the decrease in carrier concentration. Also, the effective junction barrier potential is reduced by the presence of the "opposite" type diffusion in the contacts which reduces the forward voltage at low current densities and partially compensates at high currents. A circuit model diode of Figure 10 is a parallel combination of a diode connected PNP with a diode connected NPN as illustrated in Figure 11. The resistor shown arise from the reduced contact diffusion area since approximately half of the contact is opposite doping type. The resistance may be minimized by a high level interdigitation of the N-type and P- type material for the contact. Figure 12 shows the voltage and current characteristics of the a typical prior art diode that has not been gold doped (as depicted in Figure 13) , a diode of Figures 10 and 11 and a gold doped diode (an 1Ν914 diode) . A pulse generator through series diode applied a forward bias followed by a reverse bias. The diode recovery times are illustrated in the graph of Figure 12. Stored charge is the integral of the reverse current over time. The time the current remains negative is the diode recovery time. The diode of Figures 10 and 11, although not as fast as the gold doped diode 1N914 (and not as expensive) , has a substantially faster recovery time than that of the prior art diode of Figure 13, and thus has much less reverse charge. With further reference to Figures 10 and 11, the N- substrate region may be the substrate or collector region of a vertical bipolar transistor in the same integrated circuit. The P anode AP and the N cathode CN are the base regions of vertical bipolar transistors and the anode and cathode contact regions AP+, NP+, CP+ and CN+ are the emitter regions of bipolar transistors. The diodes may also be formed using lateral bipolar transistor regions as illustrated in Figure 14. The P anode AP is a collector of a lateral bipolar transistor. The cathode CN-is the N-substrate. The anode contacts are interdigitized AN+ and AP+ regions. The cathode contacts are interdigitized CN+ and CP+. Although Figures 10 and 11 show a single pair of contacts for the anode and cathode, the interdigitized structure of Figure 14 * 'can also be used in the diode of Figures 10 and 11. For the larger capacity diodes, for examples diodes Dl and D5 of Figure 4, a plurality of cathode regions may be connected in parallel and interdigitized with a plurality of parallel connected anode regions. To measure the characteristics of the power driver circuit of the present invention, tests were performed to compare it to industry standard power driver circuits that include combined CMOS and bipolar transistors. A 50 ohm pulse generator was connected to the input and a capacitor was fixed to the output. The propagation delay from the input to the output was measured at 10 nanoseconds for the driver of Figure 4. The output rise and fall times for a range of load capacitances are shown in Figures 15 and 16, respectively. These figures show data for the 10% to 90% transition times when the capacitors are charged to 15 volts. The 80 nanoseconds fall time for a 100 nF load indicates that the peak SCR current is in excess of 15 amperes. The use of the power driver circuit of the present invention in the foregoing are but examples of its many uses, with other implementations being apparent to those skilled in the art. For example, the driver circuit of Figure 4 could be used to drive IGBT's, power NPN's and GTO-SCR's in applications similar to those shown since a "low" applied to their gates (bases) does not result in a DC current through the SCR. The NPN may be used as a buffer or switch element. Loads could be connected to either the collector or emitter as long as the current, voltage and power dissipation limits are observed. Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by way of limitation. The spirit and scope of the present invention are to be limited only by the terms of the appended claims.

Claims: I Claim : 1. A power driver circuit adapted to be connected to a control circuit for a semiconductor switching device for providing a control signal to a gate of the semiconductor switching device, said power driver circuit comprising; an SCR in the discharge path of the gate of the semiconductor switching device, said SCR having at least one gate; and trigger means operatively connected to said SCR for providing a trigger signal to the gate of said SCR in response to the control signal, said trigger means being responsive to a change in polarity of the control signal independently of the control signal's amplitude or wave shape. 2. The power driver circuit of Claim 1 wherein said SCR has an anode gate and a cathode gate; and wherein said trigger signal is applied to both of said anode and cathode gates to increase the speed at which the SCR conducts. 3. The power driver circuit of Claim 1 wherein said trigger signal is derived from a conduction-inducing charge on the gate of the semiconductor switching device. 4. A power driver circuit for a semiconductor switching device comprising: an SCR that discharges a gate of the semiconductor switching device, the SCR having anode and cathode gates; and trigger means operatively connected to said SCR for providing a trigger current to both said anode and cathode gates, thereby increasing the speed at which the SCR turns on. 5. The circuit of Claim 4 wherein said trigger means comprises means for drawing said trigger current from the gate of the semiconductor switching device. 6. The circuit of Claim 4 further comprising transistor means for providing the trigger current to said anode and cathode gates when the polarity of a control signal for controlling the switching device becomes negative. 7. The circuit of Claim 6 wherein said transistor means is an PNP transistor. 8. A power driver circuit for a semiconductor switching device comprising: an SCR that discharges a gate of the semiconductor switching device; and trigger means operatively connected to said SCR and the semiconductor switching device for drawing a relatively small trigger current from a gate of a semiconductor switching device and providing said trigger current to said SCR to increase the speed at which the SCR turns on. 9. The circuit of Claim 8 further comprising transistor means for providing the trigger current to said SCR when the polarity of a control signal for controlling the switching device becomes negative. 10. The circuit of Claim 9 wherein said transistor means is an PNP transistor. 11. A power driver circuit that is responsive to a transformer that reduces the power required to operate a semiconductor switching device at a specific frequency by decreasing the time required to transition the semiconductor switching device from on to off, the semiconductor switching device having a gate operated by the power driver circuit, the circuit comprising: an SCR having an anode gate and a cathode gate, the SCR being adapted to discharge a relatively large current at a gate of a semiconductor switching device to turn the semiconductor switching device off when the SCR is turned on; means for drawing a relatively small trigger current from the gate of the semiconductor switching device when transformer voltage becomes negative; and means for providing the trigger current to both of the anode and cathode gates to initiate conduction in the SCR, thereby increasing the speed at which the SCR turns on and decreasing the time the semiconductor switching device transitions from on to off. 12. The circuit of Claim 11 wherein said SCR comprises: a vertical PNP transistor connected in parallel to a lateral PNP transistor by their collectors, bases and emitters; a vertical NPN transistor connected in parallel to a lateral NPN transistor by their collectors, bases and emitters; said vertical PNP transistor having its collector and base connected respectively to said base and said collector of said lateral NPN transistor; said lateral PNP transistor having its collector and base connected respectively to said base and said collector of said vertical NPN transistor; and said lateral PNP transistor's base being said anode gate and said lateral NPN transistor's base being said cathode gate. 13. The circuit of Claim 12 wherein said SCR further comprises first shunt means for limiting a charge stored in the bases of said lateral PNP transistor and said vertical PNP transistor, and second shunt means for limiting a charge stored in the bases of said lateral NPN transistor and said vertical NPN transistor. 14. The circuit of Claim 13 wherein said first shunt means comprises a second lateral NPN transistor, and said second shunt means comprises a second lateral PNP transistor. 15. The circuit of Claim 11 wherein said means for drawing a trigger current comprising a diode for preventing inadvertent turn on of said SCR. 16. The circuit of Claim 15 wherein said diode comprises a PNP transistor and an NPN transistor where the base of each said transistor is connected to the emitter of the other said transistor, and the emitter of each said transistor is connected to the collector of the other said transistor, and wherein resistance means is provided in each of the emitter- collector connections. 17. In a semiconductor switching device dependent upon the conduction of a latching switch to remove the charge from the gate of the semiconductor switching device which controls its conduction, a method of improving the efficiency of the semiconductor switching device by decreasing the transition thereof between its two steady state conditions comprising the step of utilizing a portion of the charge on the gate of the semiconductor switching device to initiate conduction of the latching switch. 18. The method of Claim 17 wherein the semiconductor switching device is a FET and wherein the latching switch is a SCR. 19. The method of Claim 18 wherein the efficiency of the FET is further enhanced by applying a portion of the FET charge to plural control terminals of the SCR. 20. In a semiconductor switching device dependent upon the conduction of a latching switch to remove the charge from the gate of the semiconductor switching device which controls its conduction, a method of improving the efficiency of the semiconductor switching device by decreasing the time of transition thereof between its two steady state conditions comprising the step of initiating conduction of the latching switch at plural locations. 21. The method of Claim 20 wherein the semiconductor switching device is a FET; wherein the latching switch is an SCR with an anode gate and a cathode gate; and wherein the plural locations are said anode gate and said cathode gate. 22. The method of Claim 21 wherein said conduction of said SCR is initiated by drawing a relatively small trigger current from the gate of the FET and providing the trigger current to said anode and cathode gates. 23. The method of Claim 22 wherein the trigger current is provided to said anode and cathode gates when the polarity of a control signal for controlling the switching device becomes negative. 24. The method of Claim 23 wherein the negative polarity turns on a PNP transistor operatively connected said anode and cathode gates that enables the trigger current to be provided to said anode and cathode gates. 25. In a power driver circuit operative in response to a polarity reversing control signal to selectively supply to and drain from the gate of a semiconductor switching device a conduction controlling charge, the method of decreasing the time necessary to effect turn off of the semiconductor switching device comprising the step of initiating semiconductor switching device turn off immediately upon and in response to the detection of a change in the polarity of the control signal independently of the control signal's amplitude or wave shape. 26. A method of turning off a semiconductor switching device comprising the steps of: a) providing a semiconductor switching device turned off by the drain of a conduction-inducing charge therefrom through a latching switch; b) detecting a change in the polarity of a control signal independently of its amplitude or wave shape; and c) initiating the conduction of the latching switch in response to the detection of a polarity change. 27. The method of Claim 26 including the further step of applying a plurality of conduction-inducing trigger signals to the latching switch in response to the detection of the change in polarity of the control signal. 28. The method of Claim 26 including the further step of applying a portion of the conduction-inducing charge on the semiconductor device to initiate the conduction of the latching switch in response to the detection of the change in polarity of the control signal. 29. A method of reducing the power required to operate a semiconductor switching device at a specific frequency by decreasing the time required to transition the semiconductor switching device from on to off comprising the steps of: a) providing a power driver circuit responsive to a control signal for controlling the drain of the conduction- inducing charge on the gate of the semiconductor device; b) initiating the drain of the charge on the gate of the semiconductor device in response to a change in the polarity of the control signal independently of the amplitude and wave shape of the control signal. 30. The method of Claim 29 wherein the charge drain is initiated by developing an initial trigger signal from the charge on the semiconductor device. 31. The method of Claim 29 wherein the charge drain is initiated by developing a plurality of trigger signals. 32. In any one of the preceding claims where the semiconductor switching device is one of a MOSFET, IGBT, MCT, BJT, triac, SCR, GTO thyristor, and SIT.

Inventors: PRENTICE JOHN S, PRENTICE, JOHN, S.
Applicants: HARRIS CORP, HARRIS CORPORATION
Application year: 1993
Main classification: H03K17
IPC codes: H03K17