Auto-reset circuit with improved testability

Abstract: A first active element (41) has its first terminal coupled to a first power-supply terminal (31), its second terminal coupled through a resistor (51) to a second power-supply terminal (32), and its third terminal coupled to the second power-supply terminal( 32), or to a control signal input terminal that is normally at the same potential as the second power-supply terminal (32). A second active element (42) has its first terminal coupled to the second power-supply terminal (32), its second terminal coupled through a resistor (52) to the first power-supply terminal (31), and its third terminal coupled to the second terminal of the first active element (41). A reset signal is taken from the second terminal of the second active element (42). The control signal can be used to prevent current flow during static current measurements.

Description: BACKGROUND OF THE INVENTION This invention relates to an auto-reset circuit used to initialize an electronic circuit when the electronic circuit is powered up, or when its power supply is momentarily interrupted. When a complex electronic device such as a large-scale-integrated (LSI) circuit is powered up, it must generally be reset by placing its internal circuits in certain initial states. The device must also be reset if its power supply is interrupted during operation, as sometimes happens due to temporary conditions. For these purposes, LSI and other devices often have an auto-reset circuit that detects the rise of the power supply and generates an internal reset signal. Many types of auto-reset circuits can be found in the prior art. One of the simplest comprises a resistor and capacitor coupled in series between the two power-supply terminals, which are commonly referred to as power and ground, or V DD and V SS . The reset signal is taken from a point between the resistor and capacitor. At power-up the reset signal starts with the value of one of the two power-supply potentials, then changes to the value of the other as the capacitor charges. The reset signal can be used directly, or it can be used to drive an output stage such as an inverter or Schmitt trigger. A disadvantage of this simple auto-reset circuit is that it fails to produce a reset signal if the supply voltage rises slowly in comparison to the resistor-capacitor time constant, or if power is interrupted for an interval that is brief in relation to that time constant. To overcome the disadvantages of this simple circuit, many auto-reset circuits incorporating active elements have been developed. The one that comes closest to the present invention has a p-channel metal-oxide-semiconductor field-effect transistor (referred to below as a P-MOSFET) and a resistor coupled in series between the power-supply terminals, the source of the P-MOSFET being coupled to V DD and its drain to the resistor. An n-channel metal-oxide-semiconductor field-effect transistor (referred to below as an N-MOSFET) and another resistor are also coupled in series between the power-supply terminals, the source of the N-MOSFET transistor being coupled to V SS and its drain to the resistor. The gates of both the P-MOSFET and N-MOSFET are coupled to the drain of the P-MOSFET. The reset signal is output from the drain of the N-MOSFET. This circuit produces a reset signal that is initially high, but goes low when the supply voltage reaches a value equal to the sum of the threshold voltages of the two MOSFETs. With the traditional five-volt power supply, the reset signal is typically output while the supply voltage rises from zero to about 1.4 V, then released as the supply voltage rises from 1.4 V to a steady-state 5 V. The recent trend toward three-volt operation has created a problem for this auto-reset circuit, however. The problem arises, for example, during device tests carried out prior to shipment to the customer. Consider a device specified to operate reliably on a 3.0-V ±10% power supply over a temperature range of -40 o C to +85 o C. The nominal transistor threshold voltage is 0.7 V, but there is a variability of about ±0.25 V inherent in the fabrication process, and further variability results from the temperature dependence of the threshold voltage, so within the above temperature range the threshold voltage may be as high as 1.2 V. If both the P-MOSFET and N-MOSFET have this threshold voltage, then the reset signal will not be released until the supply voltage reaches at least 2.4 V. This would not necessarily be a problem if tests were carried out with supply voltages between 2.7 V and 3.3 V, but to prevent degradation of circuit elements, tests may be performed at a reduced supply voltage such as 2.4 V. When the device is powered up to this voltage, the auto-reset circuit may fail to release the reset signal, causing the device to be rejected as defective. To allow a reasonable margin in such tests, the auto-reset circuit needs to release the reset signal at about 1.9 V. The problem becomes even more serious at lower supply voltages, such as the 1.8 V supply voltage employed in devices driven by two nickel-cadmium cells. For such devices the auto-reset circuit described above is completely unsatisfactory. Another problem that occurs in device testing is that current flow through the above auto-reset circuit cannot be reduced to zero. One of the tests performed to detect photolithography defects and other defects is a measurement of static current consumption (I DD ). The presence of current flow through the auto-reset circuit impairs the precision of this measurement, because the exact amount of current flowing through the auto-reset circuit is unknown. Also, it becomes impossible to characterize the device down to extremely small current values. Thus the test fails to screen out devices having minor defects that may lead to failure in the field. Yet another problem of the above auto-reset circuit is that in some cases it may generate a reset signal with an inadequate pulse width, or fail to output a reset signal at all. This problem occurs not only at power-up, but also when the supply voltage drops momentarily during operation, then recovers. It occurs particularly when the supply voltage rises rapidly (in a few hundred nanoseconds, for example), and the reset signal must drive a significant capacitive load. In many devices the internal reset signal does drive a significant capacitive load, because there are many internal circuits to be reset. If the reset signal is routed to those circuits directly, the capacitance of the signal-line wiring is large. If buffers are used, the reset signal must drive the input capacitance of the buffers. A capacitive load on the order of half a picofarad is typical. If the resistor through which the reset signal is output has sufficient resistance to hold current flow through the auto-reset circuit to about ten microamperes during the steady state, and the power supply rises to five volts in a few hundred nanoseconds, then the reset signal will be released while the capacitive load is still charging and the reset signal is still inactive. This problem could be alleviated by reducing the resistance value of the resistor, but then more current would flow through the circuit during steady-state operation. If the current flow is too high, problems such as excessive power consumption and battery drain arise. SUMMARY OF THE INVENTION It is accordingly an object of the present invention to ensure release of the reset signal, even in devices with a low supply voltage. Another object of the invention is to ensure that an adequate reset signal is generated even if the power-supply potential rises rapidly. Yet another object of the invention is to ensure that a reset signal is output when the power supply is interrupted, even if the interruption is momentary. Still another object of the invention is to avoid needlessly high current drain during operation. A further object of the invention is to enable current drain through the auto-reset circuit be reduced to zero for testing purposes. Patent Abstracts of Japan, vol. 13, No. 220 (E-762) [3568], May 23, 1989 & JP-A-1,032,716 discloses an auto clearing circuit. There is disclosed an auto clearing circuit to prevent a current from flowing in a backup condition and to stabilize action by executing the on-off control of second switching element with a voltage inputted to an input terminal and, when a first switching element is in an off condition, tuming off the second switching element too. DE-A-2,539,869 discloses a circuit for generating pulses which are used for setting logical circuits, in particular MOS circuits, when switching on the power supply. Therein it is disclosed to add a RC device at the gate of a transistor which acts as a threshold switch. Patent Abstracts of Japan, vol. 7, No. 27 (E-156) [1172], February 3, 1983 & JP-A-57,183,125 discloses an initializing circuit directed to generate an initial clearing signal even by a low power voltage by connecting a N-MOS whose drain and gate are connected and a resistance to a power source and then connecting the gate of a p-MOS to a connection point between the n-MOS and the resistance. When a power voltage drops below a threshold level of a N-MOS, the N-MOS tums on. Consequently, a voltage V 1 generated by dividing the power voltage through a resistance and a N-MOS is applied to the gate of a P-MOS and when a voltage being the difference between the power voltage and V 1 exceeds the threshold level of the P-MOS, the P-MOS turns on. During a period from the conduction from the N-MOS to that of the P-MOS, the output of an inverter is at a high level and is used as an initial clearing signal. An auto-reset circuit according the present invention is defined in independent claim 1. Dependent claims 2 and 3 define particular embodiments of the invention. The invented circuit can be fabricated as a complimentary metal-oxide-semiconductor (CMOS) circuit in which the first and second transistor are MOSFETs and their first, second, and third terminals are their source, drain, and gate, respectively. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a first embodiment of an auto-reset circuit. Fig. 2 is a voltage waveform diagram illustrating the operation of Fig. 1. Fig. 3 is a circuit diagram of a second embodiment of an auto-reset circuit. Fig. 4 is a voltage waveform diagram illustrating the operation of Fig. 3. Fig. 5 is a circuit diagram of a third embodiment of an auto-reset circuit. Fig. 6 is a voltage waveform diagram illustrating the operation of Fig. 5. Fig. 7 is a circuit diagram of a fourth embodiment of an auto-reset circuit. Fig. 8 is a voltage waveform diagram illustrating the operation of Fig. 7. Fig. 9 is a circuit diagram of a fifth embodiment of an auto-reset circuit illustrating a first embodiment of the invention. Fig. 10 is a voltage waveform diagram illustrating the operation of Fig. 9. Fig. 11 is another voltage waveform diagram illustrating the operation of Fig. 9. Fig. 12 is a circuit diagram of a sixth embodiment of an auto-reset circuit illustrating a second embodiment of the invention. Fig. 13 is a voltage waveform diagram illustrating the operation of Fig. 12. Fig. 14 is another voltage waveform diagram illustrating the operation of Fig. 12. Fig. 15 is a circuit diagram of a seventh embodiment of an auto-reset circuit illustrating a third embodiment of the invention. Fig. 16 is a voltage waveform diagram illustrating the operation of Fig. 15. Fig. 17 is another voltage waveform diagram illustrating the operation of Fig. 15. Fig. 18 is a circuit diagram of an eighth embodiment of an auto-reset circuit illustrating a fourth embodiment of the invention. Fig. 19 is a voltage waveform diagram illustrating the operation of Fig. 18. Fig. 20 is another voltage waveform diagram illustrating the operation of Fig. 18. Fig. 21 is a circuit diagram of a ninth embodiment of an auto-reset circuit illustrating a fifth embodiment of the invention. Fig. 22 is a voltage waveform diagram illustrating the operation of Fig. 21. Fig. 23 is another voltage waveform diagram illustrating the operation of Fig. 21. Fig. 24 is a circuit diagram of a tenth embodiment of an auto-reset circuit illustrating a sixth embodiment of the invention. Fig. 25 is a voltage waveform diagram illustrating the operation of Fig. 24. Fig. 26 is another voltage waveform diagram illustrating the operation of Fig. 24. Fig. 27 is a circuit diagram of an eleventh embodiment of an auto-reset circuit illustrating a seventh embodiment of the invention. Fig. 28 is a voltage waveform diagram illustrating the operation of Fig. 27. Fig. 29 is another voltage waveform diagram illustrating the operation of Fig. 27. Fig. 30 is a circuit diagram of a twelfth embodiment of an auto-reset circuit illustrating an eighth embodiment of the invention. Fig. 31 is a voltage waveform diagram illustrating the operation of Fig. 30. Fig. 32 is another voltage waveform diagram illustrating the operation of Fig. 30. DETAILED DESCRIPTION OF THE INVENTION Various embodiments of auto-reset circuits will be described with reference to the attached drawings. It has to be noted that the following description referring to Figures 1 to 8 is for explanatory purposes only, the embodiments shown therein do not form a part of the invention. Embodiments of the invention are shown in and explained with reference to Figures 9 to 32. It will be assumed that the auto-reset circuits described below are incorporated in an LSI or other device powered by two potentials, the higher of which is denoted V DD and the lower V SS . The terms "high" and "low" will also be used to refer to these potentials. The term "supply voltage" will refer to the difference V DD - V SS . The symbols V TN and V TP will be used to denote N-MOSFET and P-MOSFET threshold voltages, respectively, the threshold voltage of a MOSFET being the absolute gate-source voltage at which the MOSFET turns on. Typically, V TN and V TP are about 0.7 V. It will be assumed that during normal, steady-state operation the supply voltage V DD - V SS exceeds the threshold voltages V TN and V TP sufficiently to enable the MOSFETs to turn on "hard;" that is, with negligible on-resistance. 1st Embodiment Fig. 1 is a circuit diagram of a first embodiment of an auto-reset circuit. This auto-reset circuit has a first power-supply input terminal 31 to which V DD is applied, a second power-supply input terminal 32 to which V SS is applied, and an output terminal 33, the potential at which is denoted V O . The reset signal RS is output at the output terminal 33. The circuit comprises a first three-terminal active element 41, a second three-terminal active element 42, and two resistors 51 and 52. The first active element 41 is a P-MOSFET. The second active element 42 is an N-MOSFET. The circuit is thus a CMOS circuit. P-MOSFET 41 and resistor 51 are coupled in series between the two power-supply terminals: the source of P-MOSFET 41 is coupled to the first power-supply terminal 31, the drain of P-MOSFET 41 is coupled to one terminal of resistor 51, and the other terminal of resistor 51 is coupled to the second power-supply terminal 32. The gate of P-MOSFET 41 is also coupled to the second power-supply terminal 32; this is a novel feature of the present invention. V DD is applied not only to the source of P-MOSFET 41 but also to the substrate or well in which P-MOSFET 41 is formed, as indicated by the conventional symbol in the drawing; that is, P-MOSFET 41 has no back-gate bias. N-MOSFET 42 and resistor 42 are likewise coupled in series between the two power-supply terminals: one terminal of resistor 52 is coupled to the first power-supply terminal 31, the other terminal of resistor 52 is coupled to the drain of N-MOSFET 42, and the source of N-MOST 42 is coupled to the second power-supply terminal 32. The output terminal 33 is coupled to the drain of N-MOSFET 42. The gate of N-MOSFET 42 is coupled to the drain of P-MOSFET 41. The gate potential of N-MOSFET 42 is denoted by the symbol V G . N-MOSFET 42 also has no back-gate bias; its source is at the same potential (V SS ) as the well or substrate in which it is formed. The operation of this embodiment will be explained with reference to Fig. 2. In this drawing the threshold voltages V TP of P-MOSFET 41 and V TN of N-MOSFET 41 are shown as slightly unequal: for example, V TP is 0.7 V and V TN 0.8 V. This is not a necessary condition; the invention is also applicable to circuits with equal threshold voltages. In interval A before power-up, V DD , V G , and V O are all at the same potential as V SS . In interval B power is turned on and the supply voltage begins to rise at a rate determined by a time constant of the power supply. V DD is shown rising in relation to V SS . The supply voltage V DD - V SS is initially less than the threshold voltage V TP of P-MOSFET 41, so P-MOSFET 41 is off. N-MOSFET 42 is also off, because its gate is pulled down through resistor 51 to V SS . The output terminal 33 is therefore pulled up through resistor 52 to V DD , and the output voltage V O rises together with V DD . In interval C, the supply voltage V DD - V SS exceeds V TP so P-MOSFET 41 turns on. P-MOSFET 41 and resistor 51 now act as a voltage divider between V DD and V SS , and the gate potential V G of N-MOSFET 42 begins to rise. V G - V SS is still less than the threshold voltage V TN , however, so N-MOSFET 42 remains off and the output voltage V O continues to match V DD . In interval D, V G - V SS passes V TN and N-MOSFET 42 turns on. N-MOSFET 42 and resistor 42 now act as a voltage divider between V DD and V SS , but as the gate potential V G of N-MOSFET 42 continues to rise, the on-resistance of N-MOSFET 42 quickly decreases in comparison with the resistance of resistor 52, and the drain potential of N-MOSFET 42 approaches V SS . The output voltage V O at output terminal 33 accordingly falls back toward V SS . In the drawing, for clarity, V O is shown as falling to V SS instantaneously, but the fall actually takes place over a certain span of time within interval D. In interval E, power-up is completed and V DD holds to its steady state. In this state the gate-source voltage of P-MOSFET 41 is V DD - V SS , so P-MOSFET 41 is turned on hard, the on-resistance of P-MOSFET 41 is negligible in comparison with the resistance of resistor 51, and V G is substantially equal to V DD . The gate-source voltage V G - V SS of N-MOSFET 42 is therefore substantially equal to V DD - V SS , N-MOSFET 42 is also turned on hard, the on-resistance of N-MOSFET 42 is negligible in comparison with the resistance of resistor 52, and the output voltage V O is substantially equal to V SS . The reset signal RS thus goes high (V O = V DD ) during intervals B and C, then goes low (V O = V SS ) in interval D and remains low in the steady state in interval E. RS is an active-high reset signal that can be used to initialize the internal circuits of an LSI or other device at power-up. In both the circuit of Fig. 1 and the above-mentioned prior art, the reset signal RS is released when the supply voltage V DD - V SS equals the threshold voltage V TN of N-MOSFET 42 plus the voltage drop across P-MOSFET 41. In the prior art circuit in which the drain and gate of P-MOSFET 41 were interconnected, this voltage drop was V TP . In Fig. 1 the voltage drop can be made arbitrarily small by increasing the resistance value of resistor 51. If the resistance of resistor 51 is high enough that the voltage drop across P-MOSFET 41 is substantially nil, then the reset signal RS will release when the supply voltage V DD - V SS equals the larger of V TP and V TN . If V TP = 0.7 V and V TN = 0.8 V, the reset signal will release when V DD - V SS = 0.8 V, for example. This assures that even a device powered at 3.0 V will come out of reset at power-up, and will do so even during tests performed at extreme temperatures with a reduced supply voltage. 2nd Embodiment Fig. 3 is a circuit diagram of a second embodiment of an auto-reset circuit. Elements identical to elements of the first embodiment shown in Fig. 1 have the same reference numerals. In this embodiment V SS is applied to the first power-supply terminal 31 and V DD is applied to the second power-supply terminal 32. The first active element is therefore an N-MOSFET 61 instead of the P-MOSFET 41 in Fig. 1, and the second active element is a P-MOSFET 62 instead of the N-MOSFET 42 in Fig. 1. Apart from these replacements, the active elements and resistors are interconnected in the same manner as in Fig. 1. Fig. 4 is a voltage waveform diagram illustrating the operation of the second embodiment. In this drawing, when power is turned on V DD is shown as remaining constant while V SS decreases. This may appear different from Fig. 2, but in fact the two drawings show the same power-up event. V DD and V SS do not have independent absolute values; only the difference between them is meaningful. V G now denotes the gate potential of P-MOSFET 62. V G and V O are shown in relation to V DD . The operation of the second embodiment as illustrated in Fig. 4 is the same as the operation of the first embodiment illustrated in Fig. 2, except that the roles of V DD and V SS are reversed. In interval A, V SS , V G . and V O are all equal to V DD . As V SS decreases in intervals B and C the gate-source voltage |V G - V DD | remains less than the threshold voltage V TP of P-MOSFET 62, so P-MOSFET 62 stays off, and the output voltage V O decreases together with V SS . In interval D, |V G - V DD | exceeds V TP and P-MOSFET 62 turns on, causing the output voltage V O to return to the V DD level. In interval E the supply voltage V DD - V SS is in its steady state and the output voltage V O remains at V DD . The reset signal in this second embodiment is active low: it normally stays at the high level (V DD ), but goes low (V SS ) for an interval during power-up. The choice between the first and second embodiments depends on whether an active-high or an active-low reset signal is more convenient. 3rd Embodiment Fig. 5 is a circuit diagram of a third embodiment of an auto-reset circuit. Elements identical to elements of the first embodiment shown in Fig. 1 have the same reference numerals. The difference between this third embodiment and the first is that an additional resistor 53 has been inserted in series between resistor 51 and the drain of P-MOSFET 41. The gate of N-MOSFET 42 is coupled to a point between resistors 51 and 53. Referring to Fig. 6. this embodiment operates like the first embodiment except that the gate potential V G of N-MOSFET 42 is now divided by the resistance ratio of resistors 51 and 53, so V G rises at a more moderate rate than V DD . Since it takes V G longer to reach the threshold voltage V TN of N-MOSFET 42, interval C is longer than in Fig. 2, and when V G does reach V TN , the V DD potential is higher than in Fig. 2. The potential V O of the reset signal RS therefore follows V DD to a higher level before dropping back to V SS . The supply-voltage value at which N-MOSFET 42 turns on and reset signal RS is released can be adjusted by altering the resistance ratio of resistors 51 and 53. If resistors 51 and 53 have substantially equal resistance values (both 500 kilohms, for example) and the on-resistance of P-MOSFET 41 is negligible in comparison, then RS will release at about 1.6 V instead of the 0.8 V mentioned in the first embodiment. The release voltage can be increased by increasing the value of resistor 53 in relation to resistor 51, or decreased by decreasing the value of resistor 53 in relation to resistor 51, as required by the application. 4th Embodiment Fig. 7 is a circuit diagram of a fourth embodiment of an auto-reset circuit. Elements identical to elements of the second embodiment shown in Fig. 3 have the same reference numerals. This fourth embodiment is related to the second embodiment in the same way that the third embodiment was related to the first. Specifically, an additional resistor 53 is inserted in series between resistor 51 and the drain of N-MOSFET 61, and the gate of P-MOSFET 62 is coupled to a point between resistors 51 and 53. Referring to Fig. 8, this embodiment operates like the second embodiment except that the gate potential V G of P-MOSFET 62, being divided by resistors 51 and 53, falls at a more moderate rate. As a result, interval C is longer than in Fig. 4, and the reset signal RS follows V SS down to a lower level before returning to the V DD level. As in the third embodiment, the supply-voltage value at which the reset signal RS is released can be adjusted by altering the resistance ratio of resistors 51 and 53. Increasing the resistance of resistor 53 in relation to resistor 51 makes RS release at a higher supply voltage value (a lower V SS level in Fig. 8). Decreasing the resistance of resistor 53 in relation to resistor 51 makes RS release at a lower supply voltage value (a higher V SS level in Fig. 8). The first four embodiments solve the problem of failure of the reset signal to release, and the third and fourth embodiments enable the release point to be set at any desired level between the higher of the two transistor' threshold voltages V TP and V TN and the steady-state supply voltage. These embodiments do not, however, solve the other problems referred to in the prior art. If the power supply rises quickly (in a matter of microseconds or less, for example) the reset signal RS may have inadequate duration, or may not be output at all. Modifications of the above embodiments to solve this problem will be described in the next four embodiments. 5th Embodiment (First embodiment of the invention) Fig. 9 is a circuit diagram of a fifth embodiment of an auto-reset circuit illustrating a first embodiment of the invention. Elements identical to elements of the first embodiment shown in Fig. 1 have the same reference numerals. In this auto-reset circuit a third resistor 54 is inserted in series between the gate of N-MOSFET 42 (the second active element) and the drain of P-MOSFET 41 (the first active element). The gate of N-MOSFET 42 is furthermore coupled through a capacitor 71 to the second power-supply terminal 32. The capacitor 71 is connected to a point between the gate of N-MOSFET 42 and resistor 54. V G is now not only the gate potential of N-MOSFET 42 but also the potential to which capacitor 71 is charged in relation to V SS . The operation of this auto-reset circuit will be explained with reference to Figs. 10 and 11. Fig. 10 is a voltage waveform diagram illustrating the case in which V DD rises slowly in comparison to the time constant of resistor 54 and capacitor 71. As it rises in interval C, V DD charges capacitor 71 through resistor 54; that is, V DD is integrated by resistor 54 and capacitor 71 to produce the gate potential V G . Since V DD rises slowly, however, integration is able to keep pace, and V G has substantially the same waveform as in Fig. 2. The reset signal RS also has substantially the same waveform (V O ) as in Fig. 2. Fig. 11 is a voltage waveform diagram illustrating the case in which V DD rises quickly in comparison to the time constant of resistor 54 and capacitor 71. Fig. 11 would apply, for example, if resistor 54 has a resistance of 500 kilohms, capacitor 71 has a capacitance of about 12 picofarads (making the time constant 6 microseconds), and V DD rises in about 1 microsecond. In interval A in Fig. 11, before power-up V DD , V G , and V O are all at the same potential as V SS . When power is turned on, there is a very brief interval B during which V DD is less than the threshold voltage V TP of P-MOSFET 41, and both P-MOSFET 41 and N-MOSFET 42 are off. In interval B the reset output voltage V O begins to rise together with V DD , as in Fig. 10. In interval F V DD rises all the way to the steady state, quickly passing both transistor threshold levels V TP and V TN . P-MOSFET therefore 41 turns on and V DD begins to charge capacitor 71 through resistor 54. The gate potential V G has the waveform of V DD integrated by resistor 54 and capacitor 72. Because of the time constant of resistor 54 and capacitor 72, the rise of V G takes place at a comparatively moderate rate over intervals F, G, and H. In intervals F and G in Fig. 11, V G - V SS remains less than the threshold voltage V TN , so N-MOSFET 42 remains off and the output voltage V O continues to follow V DD . In interval H, when V G - V SS passes V TN , N-MOSFET 42 turns on and the output voltage V O falls back to the V SS level. Interval I shows the steady state, in which V G is at substantially the same potential as V DD , N-MOSFET 42 is turned on hard, and V O is held reliably at the V SS level. Calculations made under the assumptions that V TN is 0.7 V, V DD rises from 0 V to 5 V in 1 microsecond, and the reset signal RS must drive a certain capacitive load show that, without resistor 54 and capacitor 71 to slow the rise of the gate potential V G , the reset signal RS would have a pulse width of only about 17 nanoseconds. With resistor 54 and capacitor 71, assuming the above-mentioned values of 500 kllohms for resistor 54 and 12 picofarads for capacitor 71, the pulse width becomes approximately 1.1 microseconds, making the reset much more dependable. If this pulse width is still inadequate it can be increased by increasing the resistance of resistor 54 or the capacitance of capacitor 71, or both. Accordingly, the first embodiment of the invention enables a reliable power-up reset to be carried out even with a fast-rising power supply. 6th Embodiment (second embodiment of the invention) Fig. 12 is a circuit diagram of a sixth embodiment of an auto-reset circuit illustrating a second embodiment of the invention. Elements identical to elements of the fifth embodiment shown in Fig. 9 have the same reference numerals. The second embodiment of the invention has the same circuit topology as the first embodiment, but V SS is applied to the first power-supply terminal 31, V DD is applied to the second power-supply terminal 32, the first active element is an N-MOSFET 61, and the second active element is a P-MOSFET 62. The operation of this embodiment will be explained briefly with reference to Figs. 13 and 14. Fig. 13 is a voltage waveform diagram illustrating the case in which the fall of V SS (that is, the rise of V DD ) is slow in relation to the time constant of resistor 54 and capacitor 71. Since capacitor 71 has adequate time to charge during the fall of V SS , the waveforms in Fig. 13 are substantially the same as those of the embodiment in Fig. 4. Fig. 14 is a voltage waveform diagram illustrating the case in which the fall of V SS is quick in relation to the time constant of resistor 54 and capacitor 71. The waveforms in Fig. 14 are identical to those in Fig. 11 with the roles of V DD and V SS and the positive and negative senses of the waveforms reversed. Due to the presence of resistor 54 and capacitor 71, an active-low reset pulse with an adequate pulse width is obtained despite the rapid transition of the supply voltage from zero volts to its steady state. The second embodiment of the invention provides the same effects as the first embodiment, except that the reset signal RS is active low. 7th Embodiment (Third embodiment of the invention) Fig. 15 is a circuit diagram of a seventh embodiment of an auto-reset circuit illustrating a third embodiment of the invention. Elements identical to elements of the first embodiment shown in Fig. 9 have the same reference numerals. The difference between this embodiment and that of Fig. 9 is the presence of another resistor 53 inserted in series between resistor 51 and the drain of P-MOSFET 41, as in the embodiment of Fig. 5. Resistor 54 is coupled to a point between resistors 51 and 53. The operation of this embodiment will be explained briefly with reference to Figs. 16 and 17. Fig. 16 is a voltage waveform diagram illustrating the operation of this embodiment when the rise of V DD is slow in relation to the time constant of resistors 53 and 54 and capacitor 71. Since capacitor 71 has ample time to charge during the rise of V DD , the waveforms are substantially the same as in Fig. 6. V G rises somewhat more slowly, however, because the gate capacitance of N-MOSFET 42 must be charged through both resistor 53 and resistor 54. Consequently, the reset signal RS attains a higher potential V O than in Fig. 6. Fig. 17 is a voltage waveform diagram illustrating the operation of this embodiment when V DD rises quickly in relation to the time constant of resistors 53 and 54 and capacitor 71. The waveforms are similar to those of the embodiment in Fig. 11, except that V G rises even more slowly, since capacitor 71 must be charged through both resistors 53 and 54 instead of just resistor 54. The pulse width of the reset signal is therefore even greater than in Fig. 11. The third embodiment of the invention combines the advantages of the embodiments of Figures 5 and 9: V DD rises slowly, the V DD level at which the reset signal RS is released can be adjusted by adjusting the resistance ratio of resistors 51 and 53; and when V DD rises fast, an adequate reset pulse width can be obtained by suitable selection of the values of resistors 51 and 53 and capacitor 71. 8th Embodiment (Fourth embodiment of the invention) Fig. 18 is a circuit diagram of an eight embodiment of auto-reset circuit illustrating a fourth embodiment of the invention. Elements identical to elements of the embodiment shown in Fig. 12 have the same reference numerals. This embodiment is related to the one of Fig. 12 in the same way that the one of Fig. 15 was related to the one of Fig. 9, by the addition of a resistor 53 coupled in series between resistor 51 and the first active element, which in the embodiments of Figs. 12 and 18 is the N-MOSFET 61. The operation of this embodiment will be explained briefly with reference to Figs. 19 and 20. Fig. 19 is a voltage waveform diagram illustrating the case in which the fall of V SS (that is, the rise of V DD ) is slow in relation to the time constant of resistors 53 and 54 and capacitor 71. Fig. 20 is a voltage waveform diagram illustrating the case in which V SS falls quickly in relation to this time constant. These two diagrams are identical to Figs. 16 and 17 with the roles of V DD and V SS and the positive and negative senses of the waveforms reversed. This embodiment provides the same effects as the previous one, except that the reset signal RS is active low. The first through fourth embodiments of the invention solve the reset problem presented by a fast-rising power supply at power-up. They do not, however, solve the problem of a momentary power interruption followed by a quick recovery. Indeed, if the interruption is sufficiently short and the recovery sufficiently quick, no reset signal will be output at all, because capacitor 71 will not have time to discharge and the second active element (N-MOSFET 42 or P-MOSFET 62) will remain on. Circuits that can output a reset signal RS even after momentary power interruptions (lasting only a few microseconds, for example) will be described below. 9th Embodiment (Fifth embodiment of the invention) Fig. 21 is a circuit diagram of a ninth embodiment of an auto-reset circuit illustrating a fifth embodiment of the invention. Elements identical to elements of the embodiment shown in Fig. 9 have the same reference numerals. This embodiment has been obtained from the embodiment of Fig. 9 by coupling the gate of N-MOSFET 42 (the second active element) to the first power-supply terminal 31 through a diode 72. The anode of diode 72 is connected to a point between the gate of N-MOSFET 42 and resistor 54. The cathode of diode 72 is connected to a point between resistor 52 and the first power-supply terminal 31. V G is now not only the gate potential of N-MOSFET 42 and the potential of the charge in capacitor 72, but also the anode potential of diode 72. The operation of this embodiment will be explained with reference to Figs. 22 and 23. Fig. 22 is a voltage waveform diagram illustrating the operation when V DD rises slowly at power-up, later drops due to a momentary power interruption, then rises slowly again, "slowly" meaning slowly in relation to the time constant of resistor 54 and capacitor 71. During power-up and in the steady state, the cathode potential (V DD ) of diode 72 is equal to or higher than the anode potential (V G ), so diode 72 does not conduct. During intervals A to E, the operation depicted in Fig. 22 is substantially identical to the operation of the embodiment depicted in Fig. 10, as if diode 72 were not present. When the power supply is interrupted and V DD begins to drop in interval J, the drain potential of P-MOSFET 41 also begins to drop, permitting capacitor 71 to discharge through resistor 54. The discharge is slow, however, because the discharge current equals the small potential difference between V G and the drain potential of P-MOSFET 41 divided by the resistance of resistor 54. Although V G decreases slightly due to this discharge, the decrease is not noticeable in the drawing. In interval K, however, V DD has fallen far enough that the difference between V G and V DD equals or exceeds the forward voltage (0.7 V, for example) necessary to make diode 72 conduct. Diode 72 now offers little resistance, and capacitor 71 begins to discharge rapidly through diode 72 to the first power supply terminal 31. V G begins to drop sharply, paralleling the drop of V DD . In interval L, V DD falls below the threshold voltage V TP of P-MOSFET 41, which turns off, but capacitor 71 continues discharging through diode 72. In interval M, V G - V SS falls below the threshold voltage V TN of N-MOSFET 42 and N-MOSFET 42 turns off. The reset output voltage V O therefore rises to V DD , but since V DD is by now approaching V SS , the resulting reset pulse is small and of brief duration. At the end of interval M V DD has fallen all the way to V SS , so V O also returns to V SS . In interval N, V DD remains at V SS and V G falls below the threshold voltage of diode 72. The forward voltage across diode 72 is now insufficient for substantial conduction to take place. Capacitor 71 continues to discharge, at a slower rate, through resistors 54 and 51 to the second power supply terminal 32. If resistors 51 and 54 have resistances of 500 kilohms and capacitor 71 has a capacitance of 3 picofarads, then in about 3.8 microseconds during this interval V G decreases from 0.7 V to 0.2 V, at which level N-MOSFET 42 is turned off hard. In interval 0, the power supply starts to recover and V DD rises again, at the same rate as at power-up. MOSFETS 41 and 42 and diode 72 stay turned off in this interval, so the output voltage V O rises together with V DD , while capacitor 71 continues to discharge through resistors 54 and 51. As V DD rises and V G falls, diode 72 becomes reverse-biased again. In interval P, V DD exceeds the threshold voltage V TP of P-MOSFET 41, so P-MOSFET 41 turns on, capacitor 71 begins to charge again, and V G now rises. V G - V SS is still less than the threshold voltage V TN of N-MOSFET 42, so N-MOSFET 42 remains off and the output voltage V O continues to rise together with V DD . In interval Q, V G - V SS exceeds V TN , so N-MOSFET 42 turns on and the reset output voltage V O drops back to the V SS level. In interval R the steady state is restored, N-MOSFET 42 is is turned on hard, and V O is held at the V SS level. By permitting capacitor 71 to discharge quickly in intervals K, L, and M, diode 72 allows N-MOSFET 42 to turn off even during a relatively brief power interruption, so that a reset signal can be output when power is recovered. The voltage waveform (V O ) of the reset signal during recovery from the power interruption in intervals O and P is substantially the same as the waveform in intervals B and C at power-up. Fig. 23 shows the case in which the supply voltage rises quickly in relation to the time constant of resistor 54 and capacitor 71, both at power-up and in recovering from a momentary power interruption. The waveforms in intervals A, B, F, G, H, and I at power-up are the same as the waveforms of the embodiment, illustrated in Fig. 11. The waveforms in intervals J, K, L, M, and N, during which V DD drops momentarily to V SS , are the same as in Fig. 22. The waveforms during recovery from the power interruption in intervals 0, P, Q, S, and T are generally similar to the waveforms in intervals B, F, G, H, and I at power-up. The main difference is that, since V G starts rising from a value slightly higher than V SS , it reaches the threshold voltage V TN of N-MOSFET 42 at the beginning of interval Q instead of the end, so the reset pulse is shorter by the width of interval Q than at power-up. The reduction in pulse width is comparatively slight, however. As in the embodiment of Fig. 11, resistor 54 and capacitor 71 permit an adequate reset pulse to be output even when the power supply rises quickly, and as in Fig. 22, by discharging capacitor 71 and turning off N-MOSFET 42 quickly, diode 72 enables a reset signal to be output after even a momentary power interruption. With the circuit constants cited above, a dependable reset is obtained when interval N in Fig. 23 is as short as 3.8 microseconds. 10th Embodiment (sixth embodiment of the invention) Fig. 24 is a circuit diagram of a tenth embodiment of an auto-reset circuit illustrating a sixth embodiment of the invention. Elements identical to elements of the embodiment shown in Fig. 21 have the same reference numerals. This embodiment has the same circuit topology as the one of Fig. 21, but the first active element is an N-MOSFET 61, the second active element is a P-MOSFET 41, V SS is applied to the first power-supply terminal 31, and V DD is applied to the second power-supply terminal 32. Diode 72 is accordingly connected in the reverse direction: its anode is coupled to the first power-supply terminal 31, and its cathode to the gate of P-MOSFET 62. The operation of the embodiment is illustrated in Fig. 25 for the case of a slow-rising power supply, and in Fig. 26 for the case of a fast-rising power supply, the rise of the power supply being depicted in both cases as a fall of V SS . The waveforms are the same as in Figs. 22 and 23, with positive and negative reversed. A detailed description will be omitted, since the operation of the embodiment is exactly analogous to the operation of the previous one. The embodiment provides the same effects for an active-low reset signal as the previous embodiment provides for an active-high reset signal. 11th Embodiment (seventh embodiment of the invention) Fig. 27 is a circuit diagram of an eleventh embodiment of an auto-reset circuit illustrating a seventh embodiment of the invention. Elements identical to elements of the embodiment shown in Fig. 21 have the same reference numerals. In this embodiment, a resistor 53 is coupled between the drain of P-MOSFET 41 and the point of interconnection of resistors 51 and 54, as in the embodiment of Fig. 15, and a diode 72 is coupled between the gate of N-MOSFET 42 and the first power-supply terminal 31, as in the embodiment of Fig. 21. Fig. 28 is a voltage waveform diagram illustrating the operation of the embodiment when V DD rises rapidly in relation to the time constant of resistors 53 and 54 and capacitor 71. The waveforms in intervals A through E at power-up are substantially the same as the corresponding waveforms of the embodiment illustrated in Fig. 16. The waveforms during the momentary power interruption and its recovery in intervals J through R are generally similar to the corresponding waveforms of the embodiment illustrated in Fig. 22, but since V G has a lower steady-state value, interval J, during which diode 72 is non-conducting, is longer and interval K, during which diode 72 conducts and MOSFETS 41 and 42 are both still on, is shorter. Although capacitor 71 has less time to discharge through diode 72 during intervals K, L, and M than in Fig. 22, the discharge starts from a lower steady-state V G potential, so V G arrives at approximately the same value at the end of interval M in both Figs. 28 and 22, and falls to about the same value in intervals N and 0. This value is low enough to turn off N-MOSFET 42 and create a reset signal in intervals O and P that is substantially the same as the one in intervals B and C at power-up. Fig. 29 illustrates the operation of the embodiment when V DD rises quickly in relation the time constant of resistors 53 and 54 and capacitor 71. The waveforms are similar to those of the embodiment in Fig. 23, except that the steady-state V G potential is lower, as in the embodiment of Fig. 15. During the recovery from the momentary power interruption, V DD rises from the V SS level to the steady state during intervals O and U, and V G rises from a value slightly higher than V SS to the threshold value V TN of N-MOSFET 42 in interval U. A reset signal is therefore output during intervals O and U. The present embodiment combines the effects of the embodiments of Figs. 15 and 23: release level of the reset signal can be altered by changing the resistance ratio of resistors 51 and 53; owing to resistor 54 and capacitor 71, a reset signal is output even if the power supply rises quickly; and due to diode 72, capacitor 71 can discharge quickly during a momentary power interruption, so that a reset signal can be output again when power is recovered. 12th Embodiment (eigth embodiment of the invention) Fig. 30 is a circuit diagram of a twelfth embodiment of an auto-reset circuit illustrating an eigth embodiment of the invention. Elements identical to elements of the embodiments shown in Figs. 24 and 27 have the same reference numerals. This embodiment has the same circuit topology as the previous one, but the first active element is an N-MOSFET 61, the second active element is a P-MOSFET 41, V SS is applied to the first power-supply terminal 31, and V DD is applied to the second power-supply terminal 32. Diode 72 is connected so that its anode is coupled to the first power-supply terminal 31 and its cathode to the gate of P-MOSFET 62. The operation of the embodiment is illustrated in Fig. 31 for the case of a slow-rising power supply and in Fig. 32 for the case of a fast-rising power supply, the rise of the power supply being depicted as a fall of V SS . The waveforms are the same as in Figs. 28 and 29 but with positive and negative reversed. A detailed description will be omitted, the operation of the present embodiment being analogous to the operation of the previous one. The present embodiment provides the same effects for an active-low reset signal as are provided for an active-high reset signal by the previous embodiment. The preceding embodiments have addressed the problems of assuring reset signal output even when the steady-state supply voltage is low, even when the supply voltage rises quickly, and even after power is interrupted for a brief interval. As will be apparent to those skilled in the art, the preceding embodiments can be modified in further ways, invention. For example, the three-terminal active elements need not be MOSFETs; other active elements in which conduction between a first terminal and a second terminal is controlled by the input at a third terminal can be employed instead.

Claims: An auto-reset circuit for generating a power-up reset signal, comprising: a first power-supply terminal (31) for receiving a first potential; a second power-supply terminal (32) for receiving a second potential different from said first potential; an output terminal (33) for outputting the power-up reset signal; a first transistor (41 or 61) having a first terminal, a second terminal, and a third terminal for controlling electrical conduction between the first terminal and second terminal thereof, first terminal of which is coupled to said first power-supply terminal (31), and the third terminal of which is coupled to said second power-supply terminal (32); a first resistor (51); a second resistor (52) coupled between said first power-supply terminal (31) and said output terminal (33); a second transistor (42 or 62) having a first terminal, a second terminal, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal of which is coupled to said second power-supply terminal (32), and the second terminal of which is coupled to said output terminal (33); characterized in that said first resistor (51) is coupled between the second terminal and the third terminal of the first transistor (41 or 61), and in that said auto-reset circuit further comprises: a third resistor (54) coupled between the second terminal of the first transistor (41 or 61) and the third terminal of the second transistor (42 or 62); and a capacitor (71) coupled between the terminal and the third terminal of the second transistor (42 or 62). The circuit of claim 1, further comprising a diode (72) via which the third terminal of said second transistor (42 or 62) is coupled to said first power-supply terminal (31). The circuit of claims 1 or 2, further comprising a fourth resistor (53) coupled in series between the second terminal of the first transistor (41 or 61) and said first resistor (51), said fourth resistor (53) also being coupled in series between the second terminal of said first transistor (41 or 61) and said third resistor (54).

Inventors: FUJISAWA YOSHIMITU, SHIN YASUHIRO, FUJISAWA, YOSHIMITU, SHIN, YASUHIRO, Fujisawa, Yoshimitu, c/o Oki LSI, Shin, Yasuhiro, c/o Oki Electric Industry Co. Ltd.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1993
Main classification: H03K17
IPC codes: H03K17