Frame synchronization circuit for digital communication system

Abstract: A frame synchronization circuit which detects a frame synchronization bit allotted in a particular position within a receiving data string includes a shift register (1), a synchronization pattern detection circuit (2) and a control circuit (3). The shift register receives and stores the receiving data string and outputs a parallel data string. The synchronization pattern detection circuit receives the parallel data string outputted from the shift register in synchronization with a clock signal and makes decisions simultaneously on the matching/non-matching of a parallel data string of totally r bits disposed in an n bit cycle within the receiving data string with r kinds of predetermined synchronization patterns of r bits. The control circuit (3) receives an output (Z) of the synchronization pattern detection circuit (2), and outputs either a signal indicative of the in-synchronization state through a terminal (53) or a signal indicative of the out-of-synchronization state through a terminal (54). This enhances the synchronization reset characteristics and reduces the worst average synchronization reset time.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit which is utilized for detecting a frame synchronization bit disposed at a particular position within a frame in performing a digital communication. (2) Description of the Related Art A digital communication requires a frame synchronization technique for recognizing a location of a given frame. As an example of a frame structure in the digital communication, an ISDN (Integrated Services Digital Network) primary rate interface is shown in Fig. 6. In the ISDN primary rate interface, one frame consists of 193 bits and the first bit is called "F-bit". Those bits from a second bit to a 193rd bit are data bits and there are 24 time slots each consisting of 8 bits. One frame is transmitted/received in a cycle of 125 µ s and 24 frames as a unit constitutes a multi-frame. Within 24 F-bits of the multi-frame, the respective F-bits (6 bits) of 4th, 8th, 12th, 16th, 20th and 24th frames are regulated as a frame synchronization pattern of "001011". The respective F-bits (6 bits) of 2nd, 6th, 10th, 14th, 18th and 22nd frames are CRC (Cyclic Redundancy Check) bits for monitoring code errors of the interface and protecting against frame synchronization errors, and the respective F-bits (12 bits) of odd number frames are maintenance and operation data bits which are called "m-bits". Thus, in the ISDN primary rate interface in which, within the 4632 bits (= 193 × 24), the synchronization bits pattern of "001011" are inserted in every 772 (= 193 × 4) bits, it is important that the frame synchronization is performed by the detection of this synchronization bits pattern. An example of a conventional circuit which takes into account the frame structure of the ISDN primary rate interface and the operation thereof are explained hereunder. As conventional frame synchronization systems, those known include a one-bit shift system or a multi-point supervising system in which such one-bit shift system is applied. As an example of the conventional frame synchronization systems, Fig. 1 shows in block diagram an arrangement in which a system of multi-point supervising type is utilized. The conventional frame synchronization circuit shown in Fig. 1 is formed by a shift register 23, an AND circuit 24, a counter 25, a synchronization pattern generation circuit 26, a comparator circuit 27 and a control circuit 28. The shift register 23 of 3860 (= 772 × 5) bits receives an input data from a data input terminal 62 and a clock signal from a clock input terminal 63. The AND circuit 24 performs a logical AND operation on the clock signal from the clock input terminal 63 and an output Y issued from the control circuit 28. The counter 25 divides the clock signal outputted from the AND circuit 24 into 1/772. The synchronization pattern generation circuit 26 outputs a synchronization pattern in synchronization with the output from the counter 25. The comparator circuit 27 receives and compares the output of the shift register 23 and the output of the synchronization pattern generation circuit 26. The control circuit 28 receives an output X of the comparator circuit 27 and decides whether it is "in-synchronization" or "out-of-synchronization". The signal indicative of the in-synchronization state is outputted from one terminal 64 while that indicative of the out-of-synchronization state is outputted from the other terminal 65. Fig. 2 shows in block diagram an internal structure of the shift register 23, in which there are an input terminal 66, six output terminals 67 - 72 and five 772-bits shift registers 29 - 33 respectively corresponding to the output terminals 68 - 72. Fig. 3 shows in block diagram an internal structure of the synchronization pattern generation circuit 26, in which there is a 6-bits shift register 34 connected to pre-set terminals 73 - 78 and output terminals 79 - 84. In the arrangement shown in Fig. 1, the data inputted from the data input terminal 62 is inputted to and stored at the shift register 23, and is outputted from the output terminals 67 - 72 in every 772 bits as a parallel signal of a unit of 6 bits. This parallel signal of 6 bits outputted from the shift register 23 is then inputted to the comparator circuit 27 and compared with the frame synchronization pattern outputted from the synchronization pattern generation circuit 26. In Fig. 3, assuming that, as an initial state, the synchronization pattern generation circuit 26 is set to the synchronization pattern of "001011" through the pre-set terminals 73 - 78, this pattern is phase-shifted one bit at a time in synchronization with a clock signal, in such a way as "100101", "110010", "011001", "101100" and "010110". Such patterns are respectively outputted from the output terminals 79 - 84. At the comparator circuit 27, if the frame synchronization pattern outputted from the synchronization pattern generation circuit 26 does not match the frame pattern of the data received, then the comparison is made between the next data received and the synchronization pattern. Here, the output Y of the control circuit 28 is OFF and, thus, the clock signal which is supplied to the AND circuit 24 from the clock input terminal 63 is not supplied to the counter 25 through this AND circuit 24. Therefore, the output terminal 64 takes an OFF state indicative of the in-synchronization state while the output terminal 65 takes an ON state indicative of the out-of-synchronization state. This state continues until the matching between the input data pattern and the synchronization pattern takes place. When the comparison results in the matching of the synchronization pattern, the output Y of the control circuit 28 becomes ON and, with the gate of the AND circuit 24 being opened, the clock signal received from the clock input terminal 63 is supplied to the counter 25. In this way, at the control circuit 28, the output terminal 64 turns to ON state indicative of the in-synchronization state and the output terminal 65 turns to an OFF state indicative of the out-of-synchronization state. The counter 25 supplies one clock to the synchronization pattern generation circuit 26 when it counted the received clocks up to 772 clocks. In response to this one clock, the synchronization pattern generation circuit 26 produces the next synchronization pattern and forwards the same to the comparator 27. The comparator circuit 27 compares the present data, that is, the receiving data after 772 bits from the receiving data having been compared and decided the last time, with the synchronization pattern mentioned above and the result of this comparison is inputted to the control circuit 28. If this second comparison results in the matching of the receiving data and the synchronization pattern, the same operation is repeated. The most important among the characteristics of such frame synchronization circuit is a synchronization reset characteristic. As a parameter for this synchronization reset characteristic, the worst average synchronization reset time is available, which may be expressed by the following equation: T S = [1 + {P(N - 1)/R(1 - P)}] T F wherein T S is the worst average synchronization reset time, P is a probability of the synchronization pattern matching with the bit string to be compared, N is the total number of bits within the frame, R is a length of the frame synchronization pattern, and T F is a frame cycle. When this equation is applied to the conventional example, P = (1/2) n , N = 4632, R = 6, T F = 3 ms and the calculated worst average synchronization reset time T S is T S = 39.75 ms. The foregoing has explained the operation of the conventional frame synchronization circuit. In a frame synchronization circuit generally used, it is important for the circuit to have a good holding characteristic, that is, there should be no likelihood for the out-of-synchronization to occur due to disturbances such as transmission code errors. In order to ensure this, it is important for the circuit to have front and back protection functions. In the back protection function, even when the receiving data and the frame synchronization pattern match each other, this is not immediately recognized as being the in-synchronization state but is so recognized only after the number of times of the matching exceeds a certain value (protection stage number). Similarly, in the front protection function, even when the non-matching is detected under the synchronization state, this is not immediately recognized as being the out-of-synchronization state but is recognized only after the number of times of the non-matching exceeds a certain value (protection stage number). In the conventional example shown in Fig. 1, counters corresponding to the number of protection stages are provided in the control circuit 28 and this makes it possible for the frame synchronization circuit to have the front and back protection functions. In the conventional frame synchronization circuit explained above, the synchronization reset characteristic which is critical to the frame synchronization circuit is bad. For example, in the case of the ISDN primary rate interface, whereas it is regulated that the worst average synchronization reset time should not exceed 15 ms, the conventional frame synchronization circuit has been unable to satisfy such regulation and the worst average synchronization reset time which is the parameter for indicating the synchronization reset characteristic has been prolonged and this has been a problem in the conventional frame synchronization circuit. EP-A-0,405,761 discloses a system for synchronizing data frames in a serial bit stream. A synchronizer in a receiver for a serial data stream includes a shift register for temporarily storing the most recently received data. Taps at a plurality of locations on such shift register provide bit signals at regularly spaced locations. These bit signals are checked for the occurrence of frame bit candidates. A candidate shift register indicates which bit positions currently remain as candidates for the frame bit position, and is shifted synchronously with the incoming data. The candidate shift register is N bits in length, and a modulo-N counter is connected to the serial output thereof. Each time a bit position shifted out of the candidate register contains a valid candidate, the modulo-N counter is reset. When the counter counts for a full cycle, the true frame bit position has been identified. CA-A-1,219, 977 discloses a framing circuit for detecting framing bits in a t.d.m. bit stream. A framing circuit is also disclosed in "IEEE Transactions on Communications, vol. 33, No. 5, May 1, 1985, New York, US, pages 465-469, David E. Dodds: Robust Frame Synchronization for Noisy PCM Systems". SUMMARY OF THE INVENTION It is, therefore, an object of the invention to overcome the problem existing in the conventional frame synchronization circuit and to provide an improved frame synchronization circuit in which the worst average synchronization reset time is effectively shortened. A frame synchronization circuit according to the present invention is defined in independent claim 1. The dependent claims define particular embodiments of the invention. According to one embodiment of the invention, there is provided a frame synchronization circuit which detects frame synchronization bits allotted in particular positions within a receiving data string, the frame synchronization circuit comprising: a shift register which receives and stores the receiving data string; and a synchronization pattern detection circuit which receives the receiving data string outputted in a parallel form from the shift register in synchronization with a clock signal and makes decisions simultaneously on matching/non-matching between a parallel data string of totally r (r being an integer larger than 0) bits disposed in an n (n being an integer larger than 0) bit cycle within the receiving data string and r kinds of predetermined synchronization patterns of r bits. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention explained with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional frame synchronization circuit; Fig. 2 is a block diagram of a shift register shown in Fig. 1; Fig. 3 is a block diagram of a synchronization pattern generation circuit shown in Fig. 1; Fig. 4 is a block diagram of a frame synchronization circuit according to the present invention; Fig. 5 is a circuit diagram of a synchronization pattern generation circuit shown in Fig. 4; and Fig. 6 is a diagram showing a frame structure of an ISDN primary rate interface. DESCRIPTION OF THE PREFERRED EMBODIMENT Now, the present invention is explained with reference to the accompanying drawings. Fig. 4 is a block diagram showing an embodiment of the present invention. As shown in Fig. 4, the frame synchronization circuit of this embodiment comprises a shift register 1 which stores a data string inputted to a data input terminal 51 in synchronization with a clock signal inputted to a clock input terminal 52; a synchronization pattern detection circuit 2 which receives an output of the shift register 1; and a control circuit 3 which receives an output Z of the synchronization pattern detection circuit 2, decides whether the received output Z is in-synchronization or out-of-synchronization, and outputs either a signal indicative of the in-synchronization state through a terminal 53 or a signal indicative of the out-of-synchronization state through a terminal 54. The shift register 1 is the same as the shift register 1 in the conventional circuit shown in Fig. 1, and the detail thereof is shown in Fig. 2. Fig. 5 is a detailed circuit diagram showing an internal structure of the synchronization pattern detection circuit 2. The synchronization pattern detection circuit 2 exemplified in Fig. 5 comprises, correspondingly with six input terminals 55 - 60 and one output terminal 61, six inverters 4 - 9, six NAND circuits 10 - 15, three Exclusive NOR circuits 16 - 18, three NOR circuits 19 - 21, and one OR circuit 22. In Fig. 5, assuming that the receiving data corresponding to the synchronization pattern of "001011" is inputted to the input terminals 55 - 60, the outputs of the inverters 4 and 5 both become "1" and, thus, the output of the NAND circuit 10 becomes "0". Also, the NAND circuit 11 outputs "1" and the Exclusive NOR circuit 16 outputs "1". The output of the inverter 6 becomes "0", the output of the inverter 7 becomes "1" and, thus, the output of the AND circuit 12 becomes "1". Also, the NAND circuit 13 outputs "1" and the Exclusive NOR circuit 17 outputs "0". The outputs of the inverters 8 and 9 both become "0" and, thus, the output of the NAND circuit 14 becomes "1". Also, the NAND circuit 15 outputs "0" and the Exclusive NOR circuit 18 outputs "1". Then, as the output "0" of the NAND circuit 10, the output "0" of the Exclusive NOR circuit 17 and the output "0" of the NAND circuit 15 are inputted to the NOR circuit 19, this NOR circuit 19 outputs "1". The NOR circuits 20 and 21 both output "0". As a result, the OR circuit 22 outputs "1" to the output terminal 61 as a signal indicative of the matching of the receiving data with respect to the synchronization pattern. Even when any of "100101", "110010", "011001", "101100" and "010110" is inputted to the input terminals 55 - 60 as the receiving data, the output to the output terminal 61 is in all cases "1" as a signal indicative of the matching between the receiving data and the synchronization pattern. On the other hand, when a receiving data other than the above six kinds of synchronization patterns is inputted, the output to the output terminal 61 is "0" indicative of the non-matching of the receiving data with respect to the synchronization pattern. In Fig. 4, the data inputted from the data input terminal 51 and outputted as the receiving data of 6 bits from the shift register 1 with intervals of 772 bits are parallelly inputted to the input terminal 55 - 60 of the synchronization pattern detection circuit 2. Here, the six output terminals 67 - 72 (in Fig. 2) of the shift register 1 correspond respectively to the input terminals 55 - 60 of the synchronization pattern detection circuit 2. When the receiving data of 6 bits outputted from the shift register 1 matches the synchronization pattern of "001011" or any of the synchronization patterns "100101", "110010", "011001", "101100" and "010110" in which one bit each is sequentially shifted, the output from the output terminal 61 (in Fig. 5) is "1" as an output signal Z for indicating the matching and is inputted to the control circuit 3. In this case, in the control circuit 3, the output terminal 53 takes the ON state which indicates the in-synchronization state and the output terminal 54 takes the OFF state which indicates the out-of-synchronization state. Under the states of non-matching with any of the above mentioned six synchronization patterns, the output from the output terminal 61 of the synchronization pattern detection circuit 2 is "0" and the signal Z of "0" is inputted to the control circuit 3. In this case, the output terminal 53 takes the OFF state which indicates the in-synchronization state and the output terminal 54 takes the ON state which indicates the out-of-synchronization state. In the conventional frame synchronization circuit, even in the worst case, where the matching/non-matching decisions have been made 4631 times, the matching with the synchronization pattern must take place in the next turn. Therefore, the worst average synchronization reset time is an expected value of the time required for making 4631 times of the matching/non-matching decisions and the value of this time is 39.75 ms from the equation (1) given earlier. However, in the frame synchronization circuit according to the invention, even in the worst case, where the matching/non-matching decisions have been made 771 times, the matching with one of the six synchronization patterns must take place in the next turn. Therefore, the worst average synchronization reset time is an expected value of the time required for making 771 times of the matching/non-matching decisions and the value of this time is 1/6 of 39.75 ms, which is about 6.6 ms accordingly. Thus, the value of the worst average synchronization reset time has been remarkably reduced. In other examples or applications, the synchronization pattern detection circuit 2 may be constituted by a PLA (Programmable Logic Array) or may be realized by using other means such as a ROM (Read Only Memory). As explained above, according to the invention, the frame synchronization circuit comprises a shift register which stores the receiving data string, and a synchronization pattern detection circuit which makes decisions simultaneously on the matching/non-matching of a data string of totally r bits disposed in an n bits cycle within the receiving data string stored in the shift register with r kinds of predetermined synchronization patterns of r bits. This enhances the synchronization reset characteristics and reduces the worst average synchronization reset time effectively.

Claims: A frame synchronization circuit for use in an ISDN (Integrated Services Digital Network) primary rate interface, for detecting frame synchronization bits allotted in particular positions within a receiving data string, said frame synchronization circuit comprising: a shift register (1) which is adapted to receive and store said receiving data string, and then to output a parallel data string of 6 bits disposed in a 772 bit cycle within the receiving data string; and a synchronization pattern detection circuit (2) which is adapted to receive said parallel data string output from said shift register (1) in synchronization with a clock signal and to make decisions simultaneously or at one time on matching/non-matching between said parallel data string of 6 bits and any one of 6 kinds of predetermined synchronization patterns of 6 bits, said 6 kinds of predetermined synchronization patterns having been established in advance in said synchronization pattern detection circuit (2); said synchronization pattern detection circuit (2) characterized by comprising: a first to a sixth inverter (4-9) respectively coupled to receive one bit of said parallel data string of 6 bits; a first to a sixth NAND gates (10-15), said first NAND gate (10) having a first input coupled to an output of said first inverter (4) and a second input coupled to an output of said second inverter (5), said second NAND gate (11) having a first input coupled to receive a first one bit of said parallel data string of 6 bits and a second input coupled to receive a second one bit of said parallel data string of 6 bits, said third NAND gate (12) having a first input coupled to an output of said third inverter (6) and a second input coupled to an output of said fourth inverter (7), said fourth NAND gate (13) having a first input coupled to receive a third one bit of said parallel data string of 6 bits and a second input coupled to receive a fourth one bit of said parallel data string of 6 bits, said fifth NAND gate (14) having a first input coupled to an output of said fifth inverter (8) and a second input coupled to an output of said sixth inverter (9), and said sixth NAND gate (15) having a first input coupled to receive a fifth one bit of said parallel data string of 6 bits and a second input coupled to receive a sixth one bit of said parallel data string of 6 bits; a first to a third Exclusive NOR gate (16-18), said first Exclusive NOR gate (16) having a first input coupled to receive the first one bit of said parallel data string of 6 bits and a second input coupled to receive the second one bit of said parallel data string of 6 bits, said second Exclusive NOR gate (17) having a first input coupled to receive the third one bit of said parallel data string of 6 bits and a second input coupled to receive the fourth one bit of said parallel data string of 6 bits, and said third Exclusive NOR gate (18) having a first input coupled to receive the fifth one bit of said parallel data string of 6 bits and a second input coupled to receive the sixth one bit of said parallel data string of 6 bits; a first to a third NOR gate (19-20), said first NOR gate (19) having a first input coupled to an output of said first NAND gate (10), a second input coupled to an output of said second Exclusive NOR gate (17) and a third input coupled to an output of said sixth NAND gate (15), said second NOR gate (20) having a first input coupled to an output of said second NAND gate (11), a second input coupled to an output of said third NAND gate (12) and a third input coupled to an output of said third Exclusive NOR gate (18), and said third NOR gate (21) having a first input coupled to an output of said first Exclusive NOR gate (16), a second input coupled to an output of said fourth NAND gate (13) and a third input coupled to an output of said fifth NAND gate (14); and an OR gate (22) having a plurality of inputs adapted to receive outputs of said first to third NOR gates (19-21), and having an output for outputting an output indicating matching or non-matching between said parallel data string of 6 bits and said any one of six kind of predetermined synchronization pattern of 6 bits. A frame synchronization circuit according to claim 1, further comprising a control circuit (3) which has a first and a second terminal (53, 54) and which is adapted to receive an output (z) of the synchronization pattern detection circuit (2), and to detect whether the received output (Z) is in-synchronization or out-of-synchronization, and to output either a signal indicative of an in-synchronization state through said first terminal (53) or a signal indicative of an out-of-synchronization state through said second terminal (54). A frame synchronization circuit according to claim 1, in which said shift register (1) is formed by five 772-bit shift registers connected in series.

Inventors: OHGANE SHOJI, OHGANE, SHOJI, Ohgane, Shoji, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H04J3
IPC codes: H04L7, H04Q11, H04J3