Input/output stage adapted to operate with low and high voltages

Abstract: A stage of both input and output configurable for operation with low and high voltages, comprises: first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means; at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); and an input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal of the stage (1).

Description: This invention relates to input and output devices, in particular a stage of both input and output which may be configured to operate with low and high voltages. Circuits of this type are known from JP-A-62 035 958 and EP-A-0 096 637. It is well recognized that standard input and output stages have some limitations to their operation which are mainly due to the technologies employed in their making. Specifically, said input and output stages are implemented in technologies which forbid implementation on the same chip of circuit portions which operate with low voltages and circuit portions which operate with high voltages. The technical problem underlining the present invention is that of realizing a mixed technology stage of both input and output which may be configured to operate with low and high voltages. In fact, by using a mixed technology, both low and high voltage circuit portions can be implemented on one chip. The above technical problem is solved by a stage of both input and output as defined in Claim 1. The features and advantages of a stage of both input and output according to the invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawing. The single Figure of the drawing shows a circuit diagram for a stage of both input and output according to the invention. The circuit layout of a stage (1) of both input and output, implemented in a mixed technology and shown in the enclosed drawing, comprises a first transistor (M1) of the P-channel MOS type, and second (M2) and third (M3) transistors of the N-channel DMOS type which can be operated with a high voltage, each of the aforesaid three transistors having a source terminal, a drain terminal, and a gate terminal. Specifically, the source, drain, and gate terminals of the first transistor (M1) are connected respectively to a first terminal of a voltage supply, to the source terminal of the second transistor (M2), and to drive means which are not shown in the drawing. The drain and gate terminals of the second transistor (M2) are connected respectively to a circuit node (A) forming an input/output terminal for the stage (1), and to switching circuit means (2). The source, drain, and gate terminals of the third transistor (M3) are respectively connected to a second terminal of the voltage supply, which is at a lower potential than the first terminal, to the circuit node (A), and to the drive means. The switching circuit means (2) are adapted to alternately connect the gate terminal of the second transistor (M2) to first (Vrefl) and second (Vref2) reference potentials, with (Vrefl) which is at a higher potential than (Vref2), to enable respectively low and high voltage operation of the stage (1). A diode (D2) is connected between the source terminal and the drain terminal of the second transistor (M2). This diode (D2) is intrinsic to the integrated structure of the second transistor (M2) and may be operated even with a high voltage. The circuit layout of the stage (1) further comprises an input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal of the stage (1). The input circuit (3) is a circuit arrangement of the differential type comprising first (T1) and second (T2) bipolar transistors of the PNP type. The operation of the stage (1) of both input and output, according to the invention, will now be discussed. When the stage (1) is used as an output stage, it may be either operated in a push-pull configuration of the CMOS type or in an open-drain configuration. Operation of the stage (1) in the push-pull configuration of the CMOS type is obtained by turning on the second transistor (M2) through the connection of its gate terminal to the first reference potential (Vrefl), via the switching circuit means (2). In this way, the diode (D2) will be shorted by the transistor (M2), and the first and third transistors (M1) and (M3) can operate in the push-pull configuration of the CMOS type if driven in phase opposition through the drive circuit means. In the push-pull configuration of the CMOS type, the stage (1) will operate with low output voltages. Operation of the stage (1) in the open-drain configuration is obtained by turning on the first transistor (M1) through the drive circuit means, and connecting the gate terminal of the second transistor (M2) to the second reference potential (Vref2) through the switching circuit means (2). Thus, the second transistor (M2) is turned off, and the diode (D2) disconnects said transistor from the node (A) when the node (A), functioning as the output terminal of the stage (1), is connected to a load which is supplied a higher voltage than that present at the drain terminal of the first transistor (M1). The third transistor (M3) can then operate in the open-drain configuration even with high output voltages. In order, to utilize the stage (1) as an input stage, the first, second and third transistors (M1), (M2) and (M3) are turned off through the drive means and the switching circuit means (2), and the differential circuit arrangement (3) is used as input circuit. As an input stage, the stage (1) may be operated with either low or high voltages.

Claims: An input/output stage of with the output is configurable for operation with low and high voltages, characterized in that it comprises: first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and the control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, to the first terminal of the second transistor (M2), and to drive circuit means, the second terminal and the control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to switching circuit means (2), adapted to alternately connect the control terminal of said second transistor (M2) to first (Vrefl) and second (Vref2) reference potentials, to enable respectively low and high voltage operation of the stage (1), the first and second terminals and the control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, to the circuit node (A), and to the drive circuit means; at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); and an input circuit (3) having a first input terminal connected to the circuit node (A), a second input terminal connected to a reference voltage (Vref3), and at least one output terminal forming an output terminal. An input/output stage according to Claim 1, characterized in that the input circuit (3) of the stage (1) is a circuit arrangement of the differential type. An input/output stage according to Claim 2, characterized in that the differential arrangement comprises bipolar transistors of the PNP type. An input/output stage according to Claim 1, characterized in that it is implemented in a mixed technology, and that the first transistor (M1) is a P-channel MOS transistor and the second (M2) and third (M3) transistors are N-channel DMOS transistors. An input/output stage according to Claim 4, characterized in that the first and second terminals and the control terminal of the first (M1), second (M2) and third (M3) transistors are source, drain and gate terminals, respectively. An input/output stage according to Claim 1, characterized in that the diode (D2) is an intrinsic diode to the integrated structure of the second transistor (M2).

Inventors: CORDINI PAOLO, PEDRAZZINI GIORGIO, ROSSI DOMENICO, CORDINI, PAOLO, PEDRAZZINI, GIORGIO, ROSSI, DOMENICO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H03K19
IPC codes: H03K19