A driving circuit for a display apparatus

Abstract: In the driving circuit for a display apparatus a charging circuit applies a voltage equal to or higher than the highest positive gradation (V₃) to each data line for a predetermined period of time before the start of a period for applying a positive gradation voltage (+V₀, +V₁ +V₂ +V₃), After that, a positive gradation voltage in accordance with data is applied to each data line. Then, a period for the applying a negative gradation voltage (-V₀, -V₁, -V₂, -V₃) is started, when a negative gradation voltage in accordance with data is applied to each data line, Accordingly, after being charged with a voltage applied by the charging circuit at the beginning of each cycle of the AC driving, each data line is applied with an equal or lower gradation voltage. Alternatively, a discharging circuit first applies a voltage equal to or lower than the lowest negative gradation voltage to each data line for a predetermined period of time before the start of a period for applying a negative gradation voltage. After that, a negative gradation voltage in accordance with data is applied to each data line. Then, a period for applying a positive gradation voltage is started, when a positive gradation voltage in accordance with data is applied to each data line. Accordingly, after being discharged with a voltage applied by the discharging circuit at the beginning of each cycle of the AC driving, each data line is applied with an equal or higher gradation voltage.

Description: The present invention relates to a driving circuit for a display apparatus which can display an image with plural gradations by the application of voltages in accordance with digital data. Figure 8 shows part of a conventional driving circuit for an active matrix type liquid crystal display apparatus utilizing a TFT (thin film transistor). In the following description, the display apparatus is presumed to display an image with four gradations by using two bits of data for simplification. Figure 8 shows only a portion of the driving circuit contributing to the supply of an output O n to a data line (the nth data line). Data D 0 has one bit and Data D 1 has one bit, which are serially sent to the driving circuit, are latched in a sampling circuit 1 by a sampling signal T SMPn for each data line. The data latched in the sampling circuit 1 are then latched at a time in a holding circuit 2 by a holding signal LP. A decoder 3 decodes the data latched in the holding circuit 2, thereby turning on one of four analog switches 4. As a result, one of four gradation voltages V 0 to V 3 corresponding to the data is supplied to the data line as an output O n . In a liquid crystal display, it is necessary to avoid the application of DC components for preventing the degradation of the liquid crystal as a display medium. Therefore, the driving circuit adopts AC driving. In AC driving, applied voltages are classified into several voltage levels, each having a positive or negative voltage value with a base voltage V M in the middle, as shown in Figure 9. A positive voltage and a negative voltage are alternately inverted to each other, for example, every horizontal scanning period. The data line receiving the output O n from the driving circuit has an equivalent circuit as shown in Figure 10. It is necessary for the driving circuit to charge or discharge a capacitance C through a resistance R of the data line in order to apply one of the four gradation voltages V 0 to V 3 to the data line. In Figure 10, resistance components and capacitance components, which are inherently present in a data line as distributed constants, are equivalently indicated as the resistance R and the capacitance C as lumped elements. Although the data line is further connected to a pixel capacitance C LC via a TFT as shown in Figure 10, the pixel capacitance C LC can be ignored because it has a smaller capacitance by equal to or more than three orders of magnitude than the capacitance C. When the driving circuit supplies, for example, a gradation voltage V 0 to the data line, as shown in Figure 11, a voltage of +V 0 is applied to the data line in a scanning period T 1 to charge the capacitance C, and a voltage of -V 0 is applied to the data line in a scanning period T 2 to discharge the capacitance C. In this manner, charge and discharge of the capacitance C are alternately repeated in each horizontal scanning period. When the gradation voltage is switched from V 0 to V 3 , a voltage of +V 0 is applied to the data line in the period T 1 , and then a voltage of -V 3 is applied to the data line in the period T 2 as shown in Figure 12. When the gradation voltage is switched from V 3 to V 0 , a voltage of +V 3 is applied to the data line in the period T 1 , and then a voltage of -V 0 is applied to the data line in the period T 2 as shown in Figure 13. In this manner, it is necessary to charge or discharge the capacitance C in accordance with the data supplied to the driving circuit. In such a driving circuit, the difference between the highest voltage +V 0 of the positive gradation voltages and the lowest voltage -V 0 of the negative gradation voltages is taken as, for example, 10 V, and the resistance of one data line is taken as, for example, 50 kΩ. Under such conditions, the driving circuit of Figure 8 supplies a charging/discharging current of 0.2 mA (10 V/50 kΩ) at most. For example, in an RGB display panel having 640 pixels in the horizontal direction, however, the number of the data lines are actually 1920 (640 x 3), and therefore, a driving circuit in such a display panel supplies a maximum charging/discharging current of 384 mA (0.2 mA x 1920) as a whole. Therefore, in a conventional driving circuit, it is necessary for the power supply circuits for the gradation voltages V 0 to V 3 to supply a large charging/discharging current by using, as output means of a negative feedback circuit of an operational amplifier 11, a SEPP (single ended push-pull) circuit comprising a complementary symmetry npn transistor 12 and pnp transistor 13, as shown in Figure 14. Moreover, the analogue switches 4 should be bi-directional. Because of the above, the structures of the power supply circuits and the like are complicated in the conventional driving circuit. As a result, the production cost is raised and a larger electric power is required. According to one aspect of the present invention, there is provided a driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line, the driving circuit comprising charging means for applying a voltage equal to or higher than a highest positive gradation voltage to each data line for a predetermined period of time at the beginning of a period for applying a positive gradation voltage. This aspect of the invention also provides a driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line, the driving circuit comprising discharging means for applying a voltage equal to or lower than a lowest negative gradation voltage to each data line for a predetermined period of time at the beginning of a period for applying a negative gradation voltage. According to another aspect of the present invention there is provided a driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line for each alternate frame, the driving circuit comprising charging means for applying a voltage equal to or higher than a highest positive gradation voltage to each data line for a predetermined period of time at the beginning of a horizontal scanning period. This aspect of the invention also provides a driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line for each alternate frame, the driving circuit comprising discharging means for applying a voltage equal to or lower than a lowest negative gradation voltage to each data line for a predetermined period of time at the beginning of a horizontal scanning period. Preferred features of the invention are set out in dependent claims 2, 4, 6, 7, 9 and 10. In the driving circuit for a display apparatus according to the present invention, charging means applies a voltage equal to or higher than the highest positive gradation voltage to each data line for a predetermined period of time before the start of a period for applying a positive gradation voltage. After that, a positive gradation voltage in accordance with data is applied to each data line. Then, a period for applying a negative gradation voltage is started, when a negative gradation voltage in accordance with data is applied to each data line. Accordingly, after being charged with a voltage applied by the charging means at the beginning of each cycle of the AC driving, each data line is applied with an equal or lower gradation voltage. In other words, the data line is discharged alone to follow the applied voltage. As a result, the power supply circuit for the charging means or the discharging means of the present invention can be an unidirectional circuit for either charging or discharging alone. The power supply circuits for the gradation voltages can also be unidirectional circuits for either discharging or charging alone, reversely to that for the charging or discharging means. Moreover, the power supply circuit for the highest positive gradation voltage can work also as the power supply circuit for the charging means. The power supply circuit for the lowest negative gradation voltage can work also as the power supply circuit for the discharging means. Thus, the invention described herein makes possible the advantages of providing an inexpensive driving circuit for a display apparatus which requires a small amount of electric power. These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. Figure 1 is a block diagram of a driving circuit for a display apparatus according to an example of the present invention. Figure 2 is a time chart for an operation of the driving circuit of Figure 1. Figure 3 is a time chart for another operation of the driving circuit of Figure 1. Figure 4 is a block diagram of a power supply circuit according to an example of the present invention. Figure 5 is a block diagram of a driving circuit for a display apparatus according to another example of the present invention. Figure 6 is a block diagram of a driving circuit for a display apparatus according to still another example of the present invention. Figure 7 is a time chart for the driving circuit of Figure 6. Figure 8 is a block diagram of a conventional driving circuit for a display apparatus. Figure 9 is a time chart for a typical operation of the driving circuit of Figure 8. Figure 10 is an equivalent circuit for a data line. Figure 11 is a time chart for an operation of the conventional driving circuit of Figure 8 outputting a gradation voltage V 0 . Figure 12 is a time chart for another operation of the conventional driving circuit of Figure 8 switching the gradation voltage from V 0 to V 3 . Figure 13 is a time chart for another operation of the conventional driving circuit of Figure 8 switching the gradation voltage from V 3 to V 0 . Figure 14 is a block diagram of a conventional power supply circuit. The present invention will now be described by way of examples referring to the accompanying drawings. (Example 1) In this example, a driving circuit for an active matrix type liquid crystal display apparatus utilizing a TFT will be described. In the following description, the display apparatus is presumed to display an image with four gradations by using two bits of data for simplification. Figure 1 is a block diagram of the driving circuit for a display apparatus of this example. Figure 1 shows only a portion of the driving circuit distributing the supply of an output O n to a data line (the nth data line). Like reference numerals will be used throughout to refer to like elements in the conventional circuits shown in Figures 8 and 14. The driving circuit comprises a sampling circuit 1, a holding circuit 2, AND circuits 5, a decoder 3 and analog switches 4. The sampling circuit 1 is a flip-flop circuit for latching two bits of data D 0 and D 1 by a sampling signal T SMPn . The holding circuit 2 is a flip-flop circuit for latching the two bits of data D 0 and D 1 latched in the sampling circuit 1 by a holding signal LP. The AND circuit 5 is a gate circuit for transferring the data D 0 or D 1 latched in the holding circuit 2 to the decoder 3 only when a charging/discharging signal DIS is deactivated (at a high level). Therefore, when the charging/discharging signal DIS is activated (at a low level), signals input through the terminals A and B of the decoder 3 are both at a low level regardless of the value of the data D 0 and D 1 . The decoder 3 receives two bits of signals to activate one of the four output lines Y 0 to Y 3 in accordance with the values of the received signals. The four output lines Y 0 to Y 3 are connected to the control input terminals of the four analog switches 4, respectively. The analog switch 4 is a contactless switching circuit connected between one of the gradation voltages V 0 to V 3 and the output O n of the driving circuit. Only one of the analog switches 4 is selected by the decoder 3 to be turned on, thereby connecting one of the gradation voltages V 0 to V 3 to the output O n . In other words, when the terminals A and B of the decoder 3 are both supplied with signals at a low level, the gradation voltage V 0 is output. When the terminals A and B of the decoder 3 are both supplied with signals at a high level, the gradation voltage V 3 is output. The output O n of the driving circuit is supplied to the corresponding one of the data lines of the display apparatus. The operation of the driving circuit having the above-mentioned structure will be described referring to the time charts shown in Figures 2 and 3. In this example, a common electrode of the display apparatus, which faces a plurality of pixel electrodes connected to the data lines with a liquid crystal layer as a display medium interposed therebetween, adopts DC driving at a base voltage V M . A holding signal LP has a pulse in each horizontal scanning period as shown in Figure 2. The data D 0 and D 1 are latched in the holding circuit 2 at the timing of the pulse. Since the driving circuit adopts AC driving, the gradation voltages V 0 to V 3 are inverted between a negative voltage level and a positive voltage level in each horizontal scanning period. Therefore, when the data D 0 and D 1 corresponding to the gradation voltage V 3 are input as shown in Figure 2, gradation voltages of +V 3 and -V 3 are alternately output in each horizontal scanning period. The sampling signal T SMPn (not shown) has a pulse at an appropriate timing in each horizontal scanning period, thereby latching, in the sampling circuit 1, only the corresponding data among all the two bits of data serially transferred to the driving circuit. A charging/discharging signal DIS is activated for a predetermined period of time after the start of the output of the gradation voltage +V 3 . Therefore, the driving circuit once outputs a voltage of +V 0 , i.e., the highest voltage, at the beginning of the application of the positive gradation voltage, then outputs a voltage of +V 3 in accordance with the data D 0 and D 1 , and finally outputs a voltage of -V 3 when a negative gradation voltage is being applied. This cycle is repeated every two horizontal scanning periods, i.e., every cycle of AC driving. As a result, in the driving circuit of this example, the data line is always discharged regardless of the data D 0 and D 1 after being charged up to the highest voltage of +V 0 at the beginning of one cycle of AC driving. Therefore, when the power supply circuit for the gradation voltage V 0 alone is bidirectional, the power supply circuits for the other gradation voltages V 1 to V 3 can be unidirectional circuits used for only discharging. When the charging/discharging signal DIS is activated for a predetermined period of time after the start of the output of the gradation voltage -V 3 , the data line is always charged regardless of the data D 0 and D 1 after being discharged down to the lowest voltage of -V 0 at the beginning of one cycle of the AC driving. Therefore, when the power supply circuit for the gradation voltage V 0 alone is bidirectional, the power supply circuits for the other gradation voltages V 1 to V 3 can be unidirectional circuits used for only charging. Figure 4 is a block diagram of a unidirectional power supply circuit, for example, for charging alone. The power supply circuit has such a simple structure that the output means for a negative feedback circuit of an operational amplifier 11 comprises an npn transistor 12 alone as shown in Figure 4. The AND circuits 5 can be replaced with OR circuits 5' to form a gate circuit as shown in Figure 5. Moreover, in this example, a power supply circuit for the highest positive gradation voltage +V 0 also works as a power supply circuit for charging. A power supply circuit for the lowest negative gradation voltage -V 0 also works as a power supply circuit for discharging. Since one power supply circuit is used for double purposes, the whole driving device can be made more compact. The power supply circuits for charging and discharging, however, can be provided separately from those for the gradation voltages. (Example 2) Figure 6 is a block diagram of a driving circuit for a display apparatus according to this example. Explanation for like elements in Example 1 will be partially omitted in the following description. The driving circuit comprises, as shown in Figure 6, a sampling circuit 1, a holding circuit 2, a decoder 3, AND circuits 6, a NOT circuit 7, analog switches 4 and another analog switch 8. The four output lines Y 0 to Y 3 of the decoder 3 are connected to the control input terminals of the four analog switches 4 via the four AND circuits 6, respectively. The AND circuit 6 is a gate circuit which makes the output lines Y 0 to Y 3 of the decoder 3 effective only when the charging/discharging signal DIS is deactivated (at a high level). The analog switch 8 is connected between a power supply circuit for a voltage V DIS and the output O n of the driving circuit, and receives the charging/discharging signal DIS through its control terminal via the NOT circuit 7. The voltage V DIS is adjusted to have a lower voltage level than that of the lowest negative gradation voltage -V 0 . Figure 7 is a time chart for an operation of the driving circuit of this example. As shown in Figure 7, when the charging/discharging signal DIS is activated for a predetermined period of time after the start of the output of the negative gradation voltage, the data line is always charged regardless of the data D 0 and D 1 after being discharged down to the lowest voltage -V DIS at the beginning of one cycle of the AC driving. Therefore, the power supply circuit for the voltage V DIS can be a unidirectional circuit for discharging alone, while the power supply circuits for all the gradation voltages V 0 to V 3 can be unidirectional circuits for discharging alone. As described above, in the examples of the present invention, all the power supply circuits for the gradation voltages can be unidirectional circuits to simplify the circuit configuration, resulting in a lower production cost of the driving circuit. Moreover, since the power supply circuit is unidirectional, the number of the output transistors therein can be halved, thereby decreasing the electric power consumed in the driving circuit. In addition, the analog switch 4 can be unidirectional to further simplify the driving circuit, resulting in a more compact LSI. Although the display with four gradations by two bits of data is described in the above-mentioned examples, the driving circuit of the present invention can be applied in a case where a display with eight or more gradations by three or more bits of data is desired. In such a case, since the number of the power supply circuits for each gradation is further increased, the power supply circuits are further effectively simplified. The present invention is not limited to the cases where a common electrode adopts DC driving, but can be applied in a case where a common electrode adopts AC driving. In such a case, AC driving for a driving circuit means that a positive and negative voltage of a data line with respect to a voltage level of a common electrode are alternately inverted to each other. There is another driving method for a display apparatus. In the driving method, the gradation voltages are inverted between a negative voltage level and a positive voltage level for each alternate frame. In such a case, the polarity of the gradation voltages to be applied to a display medium is not inverted during each frame, but the voltage level of the gradation voltage to be applied to the display medium is varied for each horizontal scanning period. Thus, in the conventional driving circuit, it is necessary for the power supply circuits for the gradation voltages to supply a charging/discharging current. In one application of the present invention for such a case, either a voltage equal to or higher than the highest positive gradation voltage, or a voltage equal to or lower than the lowest negative gradation voltage is applied to the display medium through each data line for a predetermined period of time at the beginning of each horizontal scanning period. Thus, the power supply circuits for the gradation voltages can be unidirectional circuits for either discharging or charging alone. Preferably, in view of consumption of electric power, when the power supply circuits for the gradation voltages are for discharging alone, a voltage equal to or higher than the highest positive gradation voltage is used for charging in a positive frame, and a voltage equal to or higher than the highest negative gradation voltage is used for charging in a negative frame; and when the power supply circuits for the gradation voltages are for charging alone, a voltage equal to or lower than the lowest positive gradation voltage is used for discharging in a positive frame, and a voltage equal to or lower than the lowest negative gradation voltage is used for discharging in a negative frame. Here, the highest negative gradation voltage and the lowest negative gradation voltage each indicate a voltage at which the difference between the voltage level of a common electrode and that of a pixel electrode is minimum. The present invention is not limited to a driving circuit for an active matrix LCD using a TFT as described in the above examples, but can be applied in driving circuits for other display apparatuses which conduct a gradation display by the application of voltages in accordance with digital data, such as an EL (electroluminescence) display apparatus and a plasma display.

Claims: A driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line, the driving circuit comprising charging means for applying a voltage equal to or higher than a highest positive gradation voltage to each data line for a predetermined period of time at the beginning of a period for applying a positive gradation voltage. A driving circuit according to claim 1, wherein a power supply circuit for the highest positive gradation voltage works also as a power supply circuit for the charging means. A driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line, the driving circuit comprising discharging means for applying a voltage equal to or lower than a lowest negative gradation voltage to each data line for a predetermined period of time at the beginning of a period for applying a negative gradation voltage. A driving circuit according to claim 3, wherein a power supply circuit for the lowest negative gradation voltage works also as a power supply circuit for the discharging means. A driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line for each alternate frame, the driving circuit comprising charging means for applying a voltage equal to or higher than a highest positive gradation voltage to each data line for a predetermined period of time at the beginning of a horizontal scanning period. A driving circuit according to claim 5, wherein a voltage equal to or higher than the highest positive gradation voltage is applied to each data line for the predetermined period in a positive frame, and a voltage equal to or higher than a highest negative gradation voltage is applied to each data line for the predetermined period in a negative frame. A driving circuit according to claim 5, wherein a power supply circuit for the highest positive gradation voltage works also as a power supply circuit for the charging means. A driving circuit for a display apparatus in which a positive voltage and a negative voltage selected from a plurality of gradation voltages in accordance with data are alternately applied to a display medium through each data line for each alternate frame, the driving circuit comprising discharging means for applying a voltage equal to or lower than a lowest negative gradation voltage to each data line for a predetermined period of time at the beginning of a horizontal scanning period. A driving circuit according to claim 8, wherein a voltage equal to or lower than a lowest positive gradation voltage is applied to each data line for the predetermined period in a positive frame, and a voltage equal to or lower than the lowest negative gradation voltage is applied to each data line for the predetermined period in a negative frame. A driving circuit according to claim 8, wherein a power supply circuit for the lowest negative gradation voltage works also as a power supply circuit for the discharging means.

Inventors: OKADA HISAO, TAKARADA TAKESHI, TANAKA MASARU, OKADA, HISAO, TAKARADA, TAKESHI, TANAKA, MASARU
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1993
Main classification: G09G3
IPC codes: G09G3, G02F1