Method and apparatus for performing discrete cosine transform and its inverse

Abstract: A discrete cosine transform (DCT) apparatus, capable of generating one-dimensional and two-dimensional DCT and inverse DCT results, uses six-stage DCT/IDCT fast algorithms to process a sequence of input data (Din) of an 8 x 8 data block. Each of the different stages of the DCT/IDCT fast algorithms involves a number of butterfly operations, which can be performed by a butterfly operation unit (2) of the DCT apparatus, or a number of intrinsic multiplications, a number of post-addition multiplication operations, or a number of post-multiplication subtraction operations, all of which can be performed by a multiplication operation unit (3). A control unit (6) of the DCT apparatus permits the use of a single butterfly operation unit (2) and a single multiplication operation unit (3) to perform the different stages of the DCT/IDCT fast algorithms. The results of each stage of the DCT/IDCT fast algorithms are stored in a data register unit (4) of the DCT apparatus to serve as inputs for the succeeding stages of the DCT/IDCT fast algorithms.

Description: The invention relates to a method and apparatus for performing discrete cosine transform and its inverse, more particularly to a DCT/IDCT apparatus which is capable of real-time processing and which has a relatively simple and small hardware construction. Forward and inverse discrete cosine transforms (DCT/IDCT) are performed during the compression and decompression of digital image data. In a conventional digital image compression operation, an original image signal is usually divided into a number of 8 x 8 pixel blocks, each of which undergo a DCT operation so as to generate DCT transform data. In a conventional digital image decompression operation, IDCT is performed with the DCT transform data which result from the DCT of one pixel block in order to retrieve the original image signal. If a two-dimensional DCT/IDCT operation is to be executed, each row (or column) of a data block undergoes a first one-dimensional DCT/IDCT. Each column (or row) of the resulting DCT/IDCT transform data then undergoes a second one-dimensional DCT/IDCT, thus completing the two-dimensional DCT/IDCT operation. The one-dimensional DCT of an 8 x 8 pixel block can be obtained from the following equation: F(k) = ½ C(k) Σ S(m) Cos[(2m+1)kπ/16], k=0,1,...7 m=0 wherein: C(k) is equal 2 -½ when k=0 and is equal to 1 when k=1, 2,... 7; S(m) is the pixel data in spatial domain; and F(k) is the resulting DCT transform data. A DCT fast algorithm which can be derived from the above equation involves thirteen multiplication operations and twenty-nine addition/subtraction operations. Figure 1 is a flow graph illustrating the DCT fast algorithm. The DCT fast algorithm uses three kinds of arithmetic operations: butterfly, multiplication, and addition followed by multiplication, as shown in Figures 2A to 2C. Referring to Figure 2D, a fourth kind of arithmetic operation, the multiplication followed by subtraction, is used in a corresponding IDCT fast algorithm. Referring once more to Figure 1, the DCT fast algorithm uses twelve butterfly operations, five addition followed by multiplication operations and eight intrinsic multiplication operations. An apparatus to perform the DCT flow graph of Figure 1 can be divided into six operating units: a first unit capable of performing four butterfly operations; a second unit capable of performing two addition followed by multiplication operations; a third unit capable of performing four more butterfly operations; a fourth unit capable of performing three addition followed by multiplication operations; a fifth unit capable of performing another four butterfly operations; and a sixth unit capable of performing eight intrinsic multiplication operations. The IDCT fast algorithm can be obtained by performing the DCT fast algorithm in a reverse sequence. Figure 3 illustrates the flow graph of the IDCT fast algorithm. Note that an apparatus to perform the IDCT flow graph can also be divided into six operating units: a first unit capable of performing eight multiplication operations; a second unit capable of performing four butterfly operations; a third unit capable of performing three multiplication followed by subtraction operations; a fourth unit capable of performing four more butterfly operations; a fifth unit capable of performing two more multiplication followed by subtraction operations; and a sixth unit capable of performing another four butterfly operations. If it is desired to process an 8 x 8 data block with the use of two-dimensional DCT/IDCT, a first apparatus to perform the above described DCT/IDCT fast algorithms is provided so as to execute a first one-dimensional DCT/IDCT operation. The transform data resulting from the first apparatus are then provided to a second apparatus which is similar to the first apparatus in order to perform a second one-dimensional DCT/IDCT operation. Conventional DCT/IDCT apparatus are relatively expensive since they involve the use of large and relatively complicated hardwired logic circuits which are designed in order to achieve pipeline processing at a very high processing speed. However, in actual practice, most applications do not require data processing at a very high processing speed in order to achieve real time transformation. Proceedings of the 1990 International Symposium on Circuits and Systems. Vo. 1/4, 1 May 1990, New Orleans USA, pages 77-80, P.Duhamel et al: "A DCT chip based on a new structured and computationally efficient algorithm" discloses a DCT apparatus with a recursive core that comprises a data-path and a scratch-pad memory. Intermediate data generated in a previous stage can be fed back as input data for a next stage. FR-A-2,581,463 relates to an apparatus for performing DCT and IDCT operations. The DCT/IDCT flow is partitioned into two types of elementary operations, namely A-type and PM-type. A plurality of A-type and PM-type computing devices, arranged in series, are employed to perform the different elementary operations. It is desirable to provide a DCT/IDCT apparatus which has a relatively simple and small construction and which is relatively inexpensive. It is also desirable to provide a DCT/IDCT apparatus which is capable of processing data in real time. The present invention provides a discrete cosine transform method as set out in claim 1. The invention also provides a one-dimensional discrete cosine transform apparatus as set out in claim 3. The invention further provides an inverse discrete cosine transform method as set out in claim 7, and an inverse discrete cosine transform apparatus as set out in claim 9. Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments, with reference to the accompanying drawings, of which: Figure 1 is a flow graph of a DCT fast algorithm that is to be performed by the DCT/IDCT apparatus; Figure 2A illustrates a butterfly operation used in the flow graph shown in Figure 1; Figure 2B illustrates an multiplication operation used in the flow graph shown in Figure 1; Figure 2C illustrates an addition followed by multiplication operation used in the flow graph shown in Figure 1; Figure 2D illustrates a multiplication followed by subtraction operation that is used in an IDCT fast algorithm; Figure 3 is a flow graph of an IDCT fast algorithm that is to be performed by the DCT/IDCT apparatus; Figure 4 is a schematic circuit block diagram of the first preferred embodiment of a DCT/IDCT apparatus according to the present invention; Figure 5 is a timing diagram illustrating the operation of the first preferred embodiment during a DCT operation; Figure 6 is a timing diagram illustrating the operation of the first preferred embodiment during an IDCT operation; Figure 7 is a schematic circuit block diagram of the second preferred embodiment of a DCT/IDCT apparatus according to the present invention; and Figure 8 is a timing diagram illustrating the operation of the second preferred embodiment. Referring to Figure 4, the first preferred embodiment of a DCT/IDCT apparatus according to the present invention is shown to comprise an input unit 1, a butterfly operation unit 2, an addition and multiplication operation unit 3, a data register unit 4, an output unit 5 and a control unit 6. The input unit 1 is a demultiplexer which receives a sequence of serial input data (Din) of an 8 x 8 data block from an external device (not shown) and that sends the input data (Din) to the butterfly operation unit 2 or to the multiplication operation unit 3 in accordance with the intended transform operation. The butterfly operation unit 2 includes a multiplexer 21 and a butterfly circuit 22. The butterfly circuit 22 generates the sum and difference of two input data thereto. The multiplexer 21 has a select input which is connected to the control unit 6 and data inputs which are connected to the input unit 1 and the data register unit 4. The control unit 6 controls the multiplexer 21 to select the input data (Din) from the input unit 1 or data from the data register unit 4, and provides the selected data to the butterfly circuit 22 to enable the latter to perform a butterfly operation. The output of the butterfly circuit 22 is stored in the data register unit 4 or is sent to the output unit 5. The addition and multiplication operation unit 3 includes an input select multiplexer 31, an addition/subtraction circuit 32, a multiplier circuit 33, a coefficient read-only memory (ROM) 34, and an output select multiplexer 35. The coefficient ROM 34 contains a plurality of weighting coefficients that serve as one of the operand inputs to the multiplier circuit 33. The multiplication operation unit 3 is capable of performing multiplication, addition followed by multiplication and multiplication followed by subtraction. Input data (Din) from the input unit 1 or data from the data register unit 4 is sent to the addition/subtraction circuit 32 or to the input select multiplexer 31 in order to enable the addition and multiplication operation unit 3 to perform the intended arithmetic operation. The outputs of the addition/subtraction circuit 32 and the multiplier circuit 33 are sent to the output select multiplexer 35 so as to be stored in the data register unit 4. The output of the multiplier circuit 33 can also be sent directly to the output unit 5. When the addition and multiplication operation unit 3 executes an multiplication multiplication operation, the selected data from the input select multiplexer 31 is sent to the multiplier circuit 33. At the same time, the coefficient ROM 34 is controlled by the control unit 6 so as to provide a predetermined one of the weighting coefficients to the multiplier circuit 33, thereby enabling the latter to perform a multiplication operation. When the multiplication operation unit 3 executes a addition followed by multiplication operation, the addition/subtraction circuit 32 receives two successive input data from the data register unit 4. The sum of the input data is then sent to the multiplier circuit 33. At the same time, the coefficient ROM 34 is controlled by the control unit 6 so as to provide a predetermined one of the weighting coefficients to the multiplier circuit 33, thus enabling the latter to complete the addition followed by multiplication operation. When the addition and multiplication operation unit 3 executes a multiplication followed by subtraction operation, two successive data from the data register unit 4 are respectively received by the addition/subtraction circuit 32 and the multiplier circuit 33. At the same time, the coefficient ROM 34 is controlled by the control unit 6 so as to provide a predetermined one of the weighting coefficients to the multiplier circuit 33. The product output of the multiplier circuit 33 serves as the other input to the addition/subtraction circuit 32. The addition/subtraction circuit 32 subtracts the data from the data register unit 4 from the product output of the multiplier circuit 33, thus completing the multiplication addition and subtraction operation. The data register unit 4 is a four-port register file, such as a random access memory (RAM) with two write ports (WP1, WP2) and two read ports (RP1, RP2). The first set of read and write ports (RP1, WP1) of the data register unit 4 are connected to the butterfly operation unit 2, while the second set of read and write ports (RP2, WP2) of the same are connected to the addition and multiplication operation unit 3. The data register unit 4 serves to store data from the butterfly operation unit 2 and the addition and multiplication operation unit 3, and serves to provide data thereto. The output unit 5 is a multiplexer which selects the output of the butterfly circuit 22 or the multiplier circuit 33, depending on whether DCT or IDCT is being performed. Finally, the control unit 6 is responsible for controlling the read/write operations of the coefficient ROM 34 and the data register unit 4, and is also responsible for controlling the various multiplexers 21, 31, 35. The control unit 6 is further responsible for controlling the timing of the operations of the remaining components of the DCT/IDCT apparatus. Figures 5 and 6 are timing diagrams which illustrate the operation of the first preferred embodiment. For a data block (N) undergoing two-dimensional DCT/IDCT, a first transform data block is obtained after a first one-dimensional (1-D) DCT/IDCT operation. The first transform data block then undergoes a second 1-D DCT/IDCT in order to accomplish two-dimensional DCT/IDCT. Each 1-D DCT/IDCT operation can be accomplished in six operating stages which involve the use of the butterfly operation unit 2 or the addition and multiplication operation unit 3. Referring to Figure 5, the first, third and fifth stages of the DCT fast algorithm shown in Figure 1 require the use of the butterfly operation unit 2, while the second, fourth and sixth stages of the DCT fast algorithm require the use of the multiplication operation unit 3. The second and fourth stages of the DCT fast algorithm involve addition followed by multiplication operations, while the sixth stage of the DCT fast algorithm involves multiplication operations. Referring to Figure 6, the first, third and fifth stages of the IDCT fast algorithm shown in Figure 3 require the use of the addition and multiplication operation unit 3, while the second, fourth and sixth stages of the IDCT fast algorithm require the use of the butterfly operation unit 2. The first stage of the IDCT fast algorithm involves intrinsic multiplication operations, while the third and fifth stages of the IDCT fast algorithm involves multiplication followed by subtraction operations. In the present invention, the first stage of the first 1-D DCT/IDCT is performed immediately upon reception of the input data block (N). The results of the two-dimensional DCT/IDCT can be obtained from the output of the sixth stage of the second 1-D DCT/IDCT. Note that the results of the first to fifth stages of a 1-D DCT/IDCT operation are stored in the data register unit 4 so that the data inputs to the second to sixth stages of the 1-D DCT/IDCT operation can be obtained from the latter. When the first preferred embodiment is used to perform a two-dimensional DCT/IDCT operation, the results of the sixth stage of the first 1-D DCT/IDCT operation of a data block (N) are stored in the data register unit 4. This is necessary since the transform data block obtained from the first 1-D DCT/IDCT operation has to be processed in columns if the original data block was input in rows. The transform data block that is generated during the first 1-D DCT/IDCT operation overwrites the transform data block obtained from the second 1-D DCT/IDCT operation of a preceding data block. Note that the construction of the data register unit 4 permits the butterfly operation unit 2 and the addition and multiplication operation unit 3 to read and write data therein at the same time, thus enabling the latter two to achieve parallel pipeline processing. The data register unit 4 further permits each of the butterfly operation unit 2 and the multiplication operation unit 3 to perform three DCT/IDCT fast algorithm operating stages in succession when processing data. The following is a detailed description of the operation of the first preferred embodiment. Referring again to Figures 4 and 5, when the first preferred embodiment is employed so as to perform 1-D DCT, the sixty-four pixel data of an 8 x 8 pixel block are sequentially provided to the input unit 1 in rows (or columns). The control unit 6 controls the input unit 1 to send the input pixel data (Din) to the butterfly operation unit 2 in order to enable the latter to perform the first stage of the DCT fast algorithm which involves four butterfly operations for each row (or column). The control unit 6 then controls the data register unit 4 so that the first-stage output data from the butterfly operation unit 2 are stored therein via the write port (WP1). When predetermined ones of the first-stage output data have been stored in the data register unit 4, the control unit 6 controls the data register unit 4 to provide the predetermined ones of the first-stage output data to the addition and multiplication operation unit 3 via the read port (RP2) in order to enable the latter to perform the second stage of the DCT fast algorithm which involves two addition followed by multiplication operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the second-stage output data from the addition and multiplication operation unit 3 therein via the write port (WP2). After the butterfly operation unit 2 has finished performing the first stage of the DCT fast algorithm, the control unit 6 controls the data register unit 4 to provide the first- and second-stage output data in a predetermined sequence to the butterfly operation unit 2 via the read port (RP1) in order to enable the latter to perform the third stage of the DCT fast algorithm which involves four more butterfly operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the third-stage output data from the butterfly operation unit 2 therein via the write port (WP1). When predetermined ones of the third-stage output data have been stored in the data register unit 4, the control unit 6 controls the data register unit 4 to provide the predetermined ones of the third-stage output data to the addition and multiplication operation unit 3 via the read port (RP2) in order to enable the latter to perform the fourth stage of the DCT fast algorithm which involves three addition followed by multiplication operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the fourth-stage output data from the addition and multiplication operation unit 3 therein via the write port (WP2). After the butterfly operation unit 2 has finished performing the third stage of the DCT fast algorithm, the control unit 6 controls the data register unit 4 to provide the third- and fourth-stage output data in a predetermined sequence to the butterfly operation unit 2 via the read port (RP1) in order to enable the latter to perform the fifth stage of the DCT fast algorithm which involves another four butterfly operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the fifth-stage output data from the butterfly operation unit 2 therein via the write port (WP1). The control unit 6 then controls the data register unit 4 to provide the fifth-stage output data to the addition and multiplication operation unit 3 via the read port (RP2) in order to enable the latter to perform the sixth stage of the DCT fast algorithm which involves eight multiplication operations for each row (or column). Note that the control unit 6 may control the output unit 5 so as to receive the sixth-stage output data from the addition and multiplication operation unit 3 if 1-D DCT is performed. Otherwise, the control unit 6 controls the data register unit 4 so as to store the sixth-stage output data therein. If two-dimensional DCT is performed, the control unit 6 controls the data register unit 4 to output sequentially the sixth-stage output data of the first 1-D DCT to the butterfly operation unit 2 in columns (or rows) via the read port (RP1) of the same, thereby starting the second 1-D DCT operation. The operation of the second 1-D DCT operation is substantially similar to the first 1-D DCT operation, the main difference residing in that, instead of writing the sixth-stage output data into the data register unit 4, the sixth-stage output data of the second 1-D DCT operation is received by the output unit 5 from the multiplier circuit 33. The sixth-stage output data serve as the final transformed data and are provided by the output unit 5 to an external device. Referring again to Figures 4 and 6, when the first preferred embodiment is employed so as to perform 1-D IDCT, the sixty-four transform data of an 8 x 8 transform data block are sequentially provided to the input unit 1 in rows (or columns). The control unit 6 controls the input unit 1 to send the input transform data (Din) to the addition and multiplication operation unit 3 in order to enable the latter to perform the first stage of the IDCT fast algorithm which involves eight multiplication operations for each row (or column). The control unit 6 then controls the data register unit 4 so that the first-stage output data from the addition and multiplication operation unit 3 are stored in the data register unit 4 via the write port (WP2) of the same. As the first-stage output data are stored in the data register unit 4, the control unit 6 controls the data register unit 4 to provide the available first-stage output data to the butterfly operation unit 2 via the read port (RP1) in order to enable the latter to perform the second stage of the IDCT fast algorithm which involves four butterfly operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the second-stage output data from the butterfly operation unit 2 therein via the write port (WP1) of the same. When predetermined ones of the second-stage output data have been stored in the data register unit 4, the control unit 6 controls the data register unit 4 to provide the predetermined ones of the second-stage output data to the addition and multiplication operation unit 3 via the read port (RP2) in order to enable the latter to perform the third stage of the IDCT fast algorithm which involves three multiplicationfollowed by subtraction operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the third-stage output data from the addition and multiplication operation unit 3 therein via the write port (WP2) of the same. After the butterfly operation unit 2 has finished performing the second stage of the IDCT fast algorithm, the control unit 6 controls the data register unit 4 to provide the second- and third-stage output data in a predetermined sequence to the butterfly operation unit 2 via the read port (RP1) in order to enable the latter to perform the fourth stage of the IDCT fast algorithm which involves four more butterfly operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the fourth-stage output data from the butterfly operation unit 2 therein via the write port (WP1) of the same. When predetermined ones of the fourth-stage output data have been stored in the data register unit 4, the control unit 6 controls the data register unit 4 to provide the predetermined ones of the fourth-stage output data to the addition and multiplication operation unit 3 via the read port (RP2) in order to enable the latter to perform the fifth stage of the IDCT fast algorithm which involves two multiplication followed by subtraction operations for each row (or column). The control unit 6 again controls the data register unit 4 to store the fifth-stage output data from the addition and multiplication operation unit 3 therein via the write port (WP2). After the butterfly operation unit 2 has finished performing the fourth stage of the IDCT fast algorithm, the control unit 6 controls the data register unit 4 to provide the fourth- and fifth-stage output data in a predetermined sequence to the butterfly operation unit 2 via the read port (RP1) in order to enable the latter to perform the sixth stage of the IDCT fast algorithm which involves another four butterfly operations for each row (or column). The control unit 6 may control the output unit 5 so as to receive the sixth-stage output data from the butterfly operation unit 2 if 1-D IDCT is performed. Otherwise, the control unit 6 controls the data register unit 4 to store the sixth-stage output data therein. If two-dimensional IDCT is performed, the control unit 6 controls the data register unit 4 to output sequentially the sixth-stage output data of the first 1-D IDCT to the addition and multiplication operation unit 3 in columns (or rows) via the read port (RP2) of the same, thereby starting the second 1-D IDCT operation. The operation of the second 1-D IDCT operation is substantially similar to the first 1-D IDCT operation, the main difference residing in that, instead of writing the sixth-stage output data into the data register unit 4, the sixth-stage output data of the second 1-D IDCT operation is received by the output unit 5 from the butterfly circuit 22. The sixth-stage output data are the retrieved pixel data and are provided by the output unit 5 to an external device. Referring to Figure 7, the second preferred embodiment of a DCT/IDCT apparatus according to the present invention is capable of performing two-dimensional DCT/IDCT pipeline processing of an 8 x 8 data block and is shown to comprise two 1-D DCT/IDCT apparatus 7, 8 and a control unit 9. Each of the 1-D DCT/IDCT apparatus 7, 8 is capable of performing the six-stage DCT and IDCT fast algorithms shown in Figures 1 and 3. The first 1-D DCT/IDCT apparatus 7 comprises: an input unit 71, such as a demultiplexer; a butterfly operation unit 72 including a multiplexer 721 and a butterfly circuit 722; a addition and multiplication operation unit 73 including an input select multiplexer 731, an addition/subtraction circuit 732, a multiplier circuit 733, a coefficient ROM 734, and an output select multiplexer 735; and a first data register unit 74 for storing the results of the six stages of the first 1-D DCT/IDCT operation and which also serves as a transpose memory for providing input data to the second 1-D DCT/IDCT apparatus 8. The second 1-D DCT/IDCT apparatus 8 comprises: a butterfly operation unit 81 including a multiplexer 811 and a butterfly circuit 812; a addition and multiplication operation unit 82 including an input select multiplexer 821, an addition/subtraction circuit 822, a multiplier circuit 823, and an output select multiplexer 824; a second data register unit 83; and an output unit 84, such as a multiplexer. The multiplier circuits 733, 823 share a common coefficient ROM 734. The control unit 9 is for controlling the read/write operations of the coefficient ROM 734 and the data register units 74, 83, and is also for controlling the various multiplexers 721, 731, 735, 811, 821, 824. The control unit 9 is further for controlling the timing of the operations of the remaining components of the first and second 1-D DCT/IDCT apparatus 7, 8. Referring to Figures 7 and 8, during the operation of the second preferred embodiment, when the first 1-D DCT/IDCT apparatus 7 receives rows of input data (Din) corresponding to a data block (N), the second 1-D DCT/IDCT apparatus 8 receives columns of DCT/IDCT transform data corresponding to a previous data block (N-1) from the read port (RP1A) of the data register unit 74 if a two-dimensional DCT operation is being performed, or from the read port (RP2A) of the latter if a two-dimensional IDCT operation is being performed. As both 1-D DCT/IDCT apparatus 7, 8 perform the sixth stage of the DCT/IDCT fast algorithm, the final transform data corresponding to the data block (N-1) are received by the output unit 84 for transmission to an external device. Meanwhile, the DCT/IDCT transform data corresponding to the data block (N) are stored in the data register unit 74 in order to enable the second 1-D DCT/IDCT apparatus 8 to perform the same operation in columns. The second preferred embodiment has a processing speed which is two times that of the first preferred embodiment, thus permitting a higher output bit rate.

Claims: A method of calculating a discrete cosine transform (DCT) in six-stages by processing a sequence of input data (Din) of an 8 x 8 data block so as to generate a sequence of transform data, wherein first, third and fifth stages of said method involve a plurality of butterfly operations, second and fourth stages of said method involve a plurality of addition followed by multiplication operations, and a sixth stage of said method involve a plurality of multiplication operations, said method comprising the steps of: (a) providing said sequence of input data (Din) to an input unit (1); (b) said input unit (1) providing said input data (Din) to a butterfly operation unit (2) in order to perform butterfly operations of said first stage; (c) storing in a data register unit (4) first-stage output data from said butterfly operation unit (2); (d) providing predetermined ones of said first-stage output data stored in said data register unit (4) to an addition and multiplication operation unit (3) in order to perform said addition followed by multiplication operations of said second stage and wherein said addition and multiplication unit begins to perform said addition followed by multiplication operations of said second stage when said predetermined ones of said first-stage output data have been stored in said data register unit (4), while said butterfly operation unit continues to perform butterfly operations of said first stage; (e) storing in said data register unit (4) second-stage output data from said addition and multiplication operation unit (3); (f) outputting from said data register unit (4) said first- and second-stage output data in a predetermined sequence to said butterfly operation unit (2) wherein said butterfly operation unit (2) performs butterfly operations of said third stage after said butterfly operation unit (2) has finished performing butterfly operations of said first stage; (g) storing in said data register unit (4) third-stage output data from said butterfly operation unit (2) ; (h) said data register unit (4) providing predetermined ones of said third-stage output data to said addition and multiplication operation unit (3) in order to perform said addition followed by multiplication operations of said fourth stage, wherein said addition and multiplication unit begins to perform said addition followed by multiplication operations of said fourth stage when said predetermined ones of said third-stage output data have been stored in said data register unit (4), while said butterfly operation unit continues to perform said third stage; (i) storing in said data register unit (4) fourth-stage output data from said addition and multiplication operation unit (3); (j) said data register unit (4) providing said third- and fourth-stage output data in a predetermined sequence to said butterfly operation unit (2) and wherein said butterfly operation unit (2) performs said butterfly operations of said fifth stage after said butterfly operation unit (2) has finished performing said butterfly operations of said third stage; (k) storing in said data register unit (4) fifth-stage output data from said butterfly operation unit (2); (l) said data register unit (4) providing said fifth-stage output data to said addition and multiplication operation unit (3) and wherein said addition and multiplication operation unit (3) performs multiplication operations of said sixth stage; and (m) sending to an output unit (5) said sixth-stage output data from said addition and multiplication operation unit (3). The method as claimed in claim 1, further comprising the steps of, between steps (1) and (m): storing in said data register unit (4) said sixth-stage output data; said data register unit (4) providing said sixth-stage output data to said butterfly operation unit (2) and wherein said butterfly operation unit (2) performs said first stage; and repeating steps (c) to (l). Apparatus to calculate a one-dimensional discrete cosine transform (DCT) in six-stages by processing a sequence of input data (Din) of an 8 x 8 data block so as to generate a sequence of transform data, wherein first, third and fifth stages involve a plurality of butterfly operations, second and fourth stages involve a plurality of addition followed by multiplication operations, and a sixth stage involves a plurality of multiplication operations, said DCT apparatus comprising: an input unit (1) adapted to receive said input data (Din); a butterfly operation unit (2) adapted to perform said first, third and fifth stages and comprising means adapted to generate respectively first-, third- and fifth-stage output data; an addition and multiplication operation unit (3) adapted to perform said second, fourth and sixth stages and comprising means adapted to generate respectively second-, fourth- and sixth-stage output data; a data register unit (4) connected to said butterfly operation (2) and said addition and multiplication operation unit (3) and comprising means adapted to store said first-, second-, third-, fourth- and fifth-stage output data therein; a control unit (6) connected to said input unit (1), said butterfly operation unit (2), said data register unit (4) and said multiplication operation unit (3) and to an output unit wherein said control unit comprises means adapted to control said butterfly operation unit, said data register unit, said addition and multiplication unit, said input unit and said output unit; said input unit (1) comprising means adapted to provide said input data (Din) to said butterfly operation unit (2); said data register unit (4) comprising means adapted to store said first-stage output data from said butterfly operation unit (2); said data register unit (4) further comprising means adapted to provide predetermined ones of said first-stage output data to said addition and multiplication operation unit wherein said addition and multiplication unit comprises means adapted to begin performing and to perform said second stage of said DCT fast algorithm when said predetermined ones of said first-stage output data have been stored in said data register unit (4), and while said butterfly operation unit continues to perform said first-stage of said DCT fast algorithm; said data register unit (4) further comprising means adapted to store said second-stage output data from said addition and multiplication operation unit (3); said data register unit (4) further comprising means adapted to provide said first- and second-stage output data in a predetermined sequence to said butterfly operation unit (2) said butterfly operation unit comprising means adapted to perform said third stage after said butterfly operation unit (2) has finished performing said first stage; said data register unit (4) further comprising means adapted to store said third-stage output data from said butterfly operation unit (2); said data register unit (4) further comprising means adapted to provide predetermined ones of said third-stage output data to said addition and multiplication operation unit (3) and wherein said addition and multiplication unit comprising means adapted to begin performing and to perform said fourth stage when said predetermined ones of said third-stage output data have been stored in said data register unit (4) and while said butterfly operation unit continues to perform said third-stage of said DCT fast algorithm; said data register unit (4) further comprising means adapted to store said fourth-stage output data from said addition and multiplication operation unit (3); said data register unit (4) further comprising means adapted to provide said third- and fourth-stage output data in a predetermined sequence to said butterfly operation unit (2) and wherein said butterfly unit comprises means adapted to perform said fifth stage of said DCT fast algorithm after said butterfly operation unit (2) has finished performing said third stage of said DCT fast algorithm; said data register unit (4) further comprising means adapted to store said fifth-stage output data from said butterfly operation unit (2); said data register unit (4) further comprising means adapted to provide said fifth-stage output data to said addition and multiplication operation unit (3) and wherein said addition and multiplication operation unit (3) comprises means adapted to perform said sixth stage of said DCT fast algorithm; and an output unit (5) connected to said multiplication operation unit (3) and said control unit (6) adapted to receive said sixth-stage output data from said addition and multiplication operation unit (3). The apparatus as claimed in claim 3, wherein said butterfly operation unit (2) comprises: a multiplexer (21) having a select input connected to said control unit (6) and data inputs connected to said input unit (1) and said data register unit (4), and wherein said control unit comprises means to control said multiplexer unit (21), said multiplexer (21) comprising means adapted to generate output data corresponding to a selected one of said input unit (1) and said data register unit (4); and a butterfly means (22) connected to said multiplexer (21) comprising means adapted to receive said output data thereof. The apparatus as claimed in claim 3, wherein said addition and multiplication operation unit (3) comprises: an addition/subtraction circuit (32) which is connected to said control unit (6) and said data register unit (4) and comprising means adapted to receive said predetermined ones of said first-stage and said third-stage output data from said data register unit (4) and means adapted to generate sums therefrom; a multiplier circuit (33) which is connected to said control unit (6), said data register unit (4) and said addition/subtraction unit (32); and a coefficient ROM (34) which is connected to said multiplier circuit (33) and said control unit (6) and which contains a plurality of weighting coefficients therein; means adapted to output predetermined ones of said weighting coefficients from said coefficient ROM (34); said multiplier circuit (33) comprising means adapted to receive said sums from said addition/subtraction circuit (32) and said predetermined ones of said weighting coefficients and means adapted to generate products thereof which serve as said second- and fourth-stage output data when said addition and multiplication operation unit (3) performs said second and fourth stages; said multiplier circuit (33) comprising means adapted to receive said fifth-stage output data from said data register unit (4) and said predetermined ones of said weighting coefficients and means adapted to generate products thereof which serve as said sixth-stage output data when said addition and multiplication operation unit (3) performs said sixth stage and wherein said control unit comprises means to control said addition/subtraction unit, said multiplier circuit, said coefficient ROM, said means to output predetermined ones of said weighting coefficients for said coefficient ROM. The apparatus as claimed in claim 3, wherein said data register unit (4) is a four-port random access memory with a first set of read and write ports (RP1, WP1) connected to said butterfly operation unit (2) and a second set of read and write ports (RP2, WP2) connected to said addition and multiplication operation unit (3). Method of computing an inverse discrete cosine transform (IDCT) in six-stages by processing a sequence of input data (Din) of an 8 x 8 data block so as to generate a sequence of transform data, the first stage of said method involving a plurality of multiplication operations, second, fourth and sixth stages of said method involving a plurality of butterfly operations, and third and fifth stages of said method involving a plurality of multiplication followed by subtraction operations, said method comprising the steps of: (a) providing said sequence of input data (Din) to an input unit (1); (b) said input unit (1) providing said input data (Din) to an addition and multiplication operation unit (3) wherein said addition and multiplication operation unit (3) performs said first stage; (c) a data register unit (4) storing first-stage output data from said addition and multiplication operation unit (3); (d) said data register unit (4) providing said first-stage output data to a butterfly operation unit (2) and said butterfly operation unit (2) performing said second stage; (e) said data register unit (4) storing second-stage output data from said butterfly operation unit (2) ; (f) said data register unit (4) providing predetermined ones of said second-stage output data to said addition and multiplication operation unit (3), said addition and multiplication operation unit (3) beginning to perform and performing said third stage of said IDCT fast algorithm when said predetermined ones of said second-stage output data have been stored in said data register unit (4), while said butterfly operation unit continues to perform said second stage; (g) said data register unit (4) storing third-stage output data from said addition and multiplication operation unit (3); (h) said data register unit (4) providing said second- and third-stage output data in a predetermined sequence to said butterfly operation unit (2) and said butterfly operation unit (2) performing said fourth stage after said butterfly operation unit (2) has finished performing said second stage; (i) said data register unit (4) storing fourth-stage output data from said butterfly operation unit (2); (j) said data register unit (4) providing predetermined ones of said fourth-stage output data to said addition and multiplication operation unit (3), said addition and multiplication operation unit (3) beginning to perform and performing said fifth stage when said predetermined ones of said fourth-stage output data have been stored in said data register unit (4), while said butterfly operation unit continues to perform said fourth stage; (k) said data register unit (4) storing fifth-stage output data from said addition and multiplication operation unit (3); (l) said data register unit (4) providing said fourth- and fifth-stage output data in a predetermined sequence to said butterfly operation unit, (2) said butterfly operation unit (2) performing said sixth stage after said butterfly operation unit (2) has finished performing said fourth stage; and (m) sending to an output unit (5) said sixth-stage output data from said butterfly operation unit (2). The method as claimed in claim 7, further comprising the steps of, between steps (1) and (m): said data register unit (4) storing said sixth-stage output data; said data register unit (4) providing said sixth-stage output data to said addition and multiplication operation unit (3), said addition and multiplication operation unit (3) performing said first stage; and repeating steps (c) to (l). Apparatus to calculate a one-dimensional inverse discrete cosine transform (IDCT) in six-stages by processing a sequence of input data (Din) of an 8 x 8 data block so as to generate a sequence of transform data, wherein a first stage involves a plurality of multiplication operations, second, fourth and sixth stages involve a plurality of butterfly operations, and third and fifth stages, involve a plurality of multiplication followed by subtraction operations, said apparatus comprising: an input unit (1) adapted to receive said input data (Din); an addition and multiplication operation unit (3) adapted to perform said first, third and fifth stages and comprising means adapted to generate respectively first-, third- and fifth-stage output data; a butterfly operation unit (2) adapted to perform said second, fourth and sixth stages and comprising means adapted to generate respectively second-, fourth- and sixth-stage output data when performing said second, fourth and sixth stages; a data register unit (4) connected to said butterfly operation unit (2) and said addition and multiplication operation unit (3) adapted to store said first-, second-, third-, fourth- and fifth-stage output data; a control unit (6) connected to said input unit (1), said butterfly operation unit (2), said data register unit (4) and said addition and multiplication operation unit (3) wherein said control unit comprising means to control said input unit, said butterfly operation unit, said data register unit, said addition and multiplication unit and an output unit; said input unit (1) comprising means adapted to provide said input data (Din) to said addition and multiplication operation unit (3), said addition and multiplication operation unit (3) comprising means adapted to perform said first stage; said data register unit (4) comprising means adapted to store said first-stage output data from said addition and multiplication operation unit (3); said data register unit (4) further comprising means adapted to provide said first-stage output data to said butterfly operation unit (2), said butterfly operation unit (2) comprising means adapted to perform said second stage; said data register unit (4) further comprising means adapted to store said second-stage output data from said butterfly operation unit (2); said data register unit (4) further comprising means adapted to provide predetermined ones of said second-stage output data to said addition and multiplication operation unit (3), said addition and multiplication operation unit (3) comprising means adapted to begin performing and to perform said third stage when said predetermined ones of said second-stage output data have been stored in said data register unit (4), while said butterfly operation unit continues to perform said second stage of said IDCT fast algorithm; said data register unit (4) further comprising means adapted to store said third-stage output data from said addition and multiplication operation unit (3) therein; said data register unit (4) further comprising means adapted to provide said second- and third-stage output data in a predetermined sequence to said butterfly operation unit (2), said butterfly operation unit (2) comprising means adapted to perform said fourth stage after said butterfly operation unit (2) has finished performing said second stage; said data register unit (4) further comprising means adapted to store said fourth-stage output data from said butterfly operation unit (2); said data register unit (4) further comprising means adapted to provide predetermined ones of said fourth-stage output data to said addition and multiplication operation unit (3), said multiplication operation unit (3) comprising means adapted to begin performing and to perform said fifth stage when said predetermined ones of said fourth-stage output data have been stored in said data register unit (4), while said butterfly operation unit continues to perform said fourth stage of said IDCT fast algorithm; said data register unit (4) further comprising means adapted to store said fifth-stage output data from said addition and multiplication operation unit (3); said data register unit (4) further comprising means adapted to provide said fourth- and fifth-stage output data in a predetermined sequence to said butterfly operation unit (2), said butterfly operation unit (2) comprising means adapted to perform said sixth stage after said butterfly operation unit (2) has finished performing said fourth stage; and said output unit (5) connected to said butterfly operation unit (2) and said control unit (6) and comprising means adapted to receive said sixth-stage output data from said butterfly operation unit (2). The one-dimensional apparatus as claimed in claim 9, wherein said addition and multiplication operation unit (3) comprises: a first multiplexer (31) having a select input connected to said control unit (6) and data inputs connected to said input unit (1) and said data register unit (4), said first multiplexer (31) comprising means adapted to generate output data corresponding to a selected one of said input unit (1) and said data register unit (4); a coefficient ROM (34) which is connected to said control unit (6) and which contains a plurality of weighting coefficients therein; output means to output predetermined ones of said weighting coefficients from said coefficient ROM; a multiplier circuit (33) connected to said control unit (6), said first multiplexer (31) and said coefficient ROM (34), said multiplier circuit (33) comprising means adapted to receive said input data (Din) from said input unit (1) via said first multiplexer (31) and said predetermined ones of said weighting coefficients and comprising means adapted to generate products thereof which serve as said first-stage output data when said addition and multiplication operation unit (3) performs said first stage of said IDCT fast algorithm, said multiplier circuit (33) further comprising means adapted to receive said output data from said first multiplexer (31) and said predetermined ones of said weighting coefficients and adapted to generate products thereof when said multiplication operation unit (3) performs said third- and fifth-stages; an addition/subtraction circuit (32) connected to said control unit (6), said data register unit (4) and said multiplier circuit (33), said addition/subtraction circuit (32) comprising means adapted to receive said products from said multiplier circuit (33) and said predetermined ones of said second- and fourth-stage output data from said data register unit (4) and adapted to generate differences therefrom when said multiplication operation unit (3) performs said third- and fifth-stages, said differences serving as said third- and fifth stage output data; and a second multiplexer (35) having a select input connected to said control unit (6), data inputs connected to said multiplier circuit (33) and said addition/subtraction circuit (32), and an output connected to said data register unit (4), said second multiplexer (35) comprising means adapted to generate output data corresponding to a selected one of said multiplier circuit (33) and said addition/subtraction circuit (32) and wherein said control unit (6) comprising means to control said first multiplexer, said coefficient ROM, said output means, said multiplier circuit, said addition/subtraction circuit, said second multiplexer. The one-dimensional apparatus as claimed in claim 9, wherein said data register unit (4) is a four-port random access memory with a first set of read and write ports (RP1, WP1) connected to said butterfly operation unit (2) and a second set of read and write ports (RP2, WP2) connected to said addition and multiplication operation unit (3).

Inventors: SHYU RONG-FUH, SHYU, RONG-FUH
Applicants: WINBOND ELECTRONICS CORP, WINBOND ELECTRONICS CORPORATION
Application year: 1993
Main classification: G06F17
IPC codes: G06F17