METHOD FOR CASCADING SIGMA-DELTA MODULATORS AND A SIGMA-DELTA MODULATOR SYSTEM

Abstract: The invention relates to a method for cascading two or more feedforward-type sigma-delta modulators, and a modulator system comprising at least two cascaded modulators (1, 2). According to the invention, each subsequent modulator (2) in the cascade quantizes the integrated signal estimate error (e) of the preceding modulator (1), the quantized error (e') is differentiated (3) and subtracted (6) from the quantized output signal (D") of the preceding modulator (1).

Description: Method for cascading sigma-delta modulators and a sigma-delta modulator system Field of the Invention The invention relates to a method for cascading at least two sigma-delta modulators, wherein an error of one modulator in the cascade is quantized by the next modulator in the cascade; the quantized error is differentiated; and the differentiated error is sub- tracted from the quantized output signal of said one modulator. Background of the Invention In sigma-delta modulators (also known as delta- sigma modulators), the signal is quantized by using only a small number of quantization levels (2 - 256, which corresponds to an A/D converter with a resolution of 1 to 8 bits) at a high rate, usually 32 - 512 times the signal frequency. The ratio between the Nyquist sampling frequency (two times the useful signal band) and the used high sampling frequency is also called oversampling ratio (M). A quantizer is a combination of an A/D and a D/A converter, in which an analog signal is converted by the A/D converter to a discrete digital value which is then immediately converted back to an analog voltage (value) by the D/A converter. A quantizing error (e k ) is the dif¬ ference voltage (value) between the analog input voltage and the analog output voltage, and the quantizing noise is the spectrum (Q e ) of the quantizing error; in the case of the sigma-delta modulator, the quantizing noise can be regarded as white noise. The effective value (E) of the white noise in a one-bit quantizer is (q/2) 2 with a one-bit, where q is the spacing between the quantization levels. A sigma-delta modulator configuration is such that the quantizer error transfer function (NTF) to the output of the modulator is different from the signal transfer function (STF) from the input to the output of the modulator. The object is to provide a quantizing error transfer function NTF with the highest possible attenuation within a desired pass¬ band while the signal transfer function STF is as uniform as possible over the whole passband. The STF and NTF are interdependent in a manner determined by the used modulator structure. The order of the mod¬ ulator is the order of the NTF function, or the number of integrators in the modulator. By increasing the order of the modulator the amount of quantizing noise in the passband can be decreased. Another way of decreasing the amount of quantizing noise in the passband is to increase the oversampling ratio; how¬ ever, an increase in the oversampling ratio increases the sampling frequency which in turn is limited by the components used in the implementation. Therefore the only way to improve the ratio (S/N q ) between the signal (S) and the quantizing noise (N q ) in the pass¬ band is to increase the order of the modulator or to improve the NTF so that the attenuation in the pass- band is increased while the order of the modulator and the oversampling ratio remain unchanged. A conventional sigma-delta modulator with directly series-connected integrators is, however, difficult to implement due to the oscillation caused by the feedback loop. Therefore higher-order sigma- delta modulators have been formed by cascading two or more stable lower-order sigma-delta modulators. The quantizing error of the first modulator in the cas¬ cade connection (the difference between the input and output signals of the quantizer) is applied to the second modulator in the cascade, and the amount of quantizing noise over the signal band can be de¬ creased by suitably interconnecting the outputs of the blocks. A 16-bit Oversampling R-to-O Conversion Using Triple- Integration Noise Shaping, IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6, December 1987, p. 921 to 929, describes the cascading of first-order sigma-delta modulators by the so-called MASH technique. FI Patent 80548 describes the cascade connections of second-order multiple-feedback modulators. Summary of the Invention The object of the present invention is to cas- cade two sigma-delta modulator blocks to achieve a better SNRQ than what was possible in the prior art modulator system of the same order and with the same oversampling ratio. This is achieved by a method described in the introductory chapter, which according to the invention is characterized in that the error is the error of the integrated signal estimate of said one modulator. According to the invention, at least two nth- order sigma-delta modulator blocks realized by a 1- bit quantizer are cascaded so that each subsequent modulator block quantizes the signal estimate error voltage formed in the preceding modulator block, scaled by a scalar 1/C to the operating range of the subsequent modulator. The 1-bit data of the sub¬ sequent modulator block is filtered by a digital filter having a transfer function which is the in¬ verse of the transfer function of the integrators of the first modulator block, and scaled by a scalar C, and then subtracted from the 1-bit data of the first block, which data has been delayed in an amount cor¬ responding to the delay caused by the subsequent mod¬ ulator block. In this way the signal estimate error of the first block, quantized by the subsequent mod- ulator block, can be subtracted from the output of the first block, and the accuracy of the signal estimate is improved and the amount of quantizing noise on the signal band is reduced. The obtained digital output is the output of a 2*nth-order sigma- delta modulator. As distinct from the prior art cas¬ cading based on the re-quantization of the quantizing error, the cascading according to the invention based on the signal estimate error ensures that the signal transfer function of the entire modulator system will always be 1 irrespective of the coefficients (STF) of the used modulator block. The prior art re-quantiza¬ tion of the quantizing error and the substraction of the error from the output of the first block linear¬ izes the attenuation across the quantizer to a constant value (1), so that the signal transfer function is determined by the STF of the first mod¬ ulator block. The modulator blocks used in the invention are of the FF-type. According to the invention the blocks are at least of the second order. The STF of the two blocks must be equal. As the first feedforward-type modulator has a single feedback for the quantized value (from the output to the inpu ), the signal estimate error is the voltage difference between the feedbacked quantized signal (voltage) and the analog input voltage. However, the signal estimate error is integrated n times (n is the number of the integration stages) before it is applied to the sub¬ sequent (next) modulator. In addition, it is possible to subtract an appropriately weighted signal estimate (a 1-bit quantized voltage) from the signal estimate error. In addition to the advantages of the higher- order modulator system and the associated reduction in the amount of quantizing noise, the cascade con¬ nection can improve the signal-to-noise ratio (S/N+N q ) in practical applications, because the re¬ quired voltage scaling in the input of the first mod¬ ulator block is smaller than in the prior art cas- caded modulators. The sensitivity of the modulator to the noise (N) of the circuit elements is at highest in the input stage, and so the performance of nearly all modulators (with an accuracy higher than 16 bits) is limited by the noise of the circuit elements of the first integrator. With less voltage scaling the physical noise (N) of the circuit elements is relatively smaller. The invention also relates to a sigma-delta modulator system comprising a first sigma-delta modulator having at least two integration stages and a quantizing means for quantizing a primary signal; a means for providing an error signal representing the quantizing noise of the first modulator; a second sigma-delta modulator means having at least two integration stages and a quantizing means, for quantizing said error signal; a differentiation means having a transfer function substantially equal to the inverse function of the common transfer function of the integration stages of the first modulator means, for differentiating the output signal of the second modulator means; a means for delaying a quantized primary signal in an amount corresponding to the delay of the second modulator means; and a means for subtracting the differentiated error signal from the delayed quantized primary signal. Brief Description of the Drawings In the following the invention will be de¬ scribed in greater detail by means of illustrating embodiments with reference to the attached drawing, in which Figure 1 is a block diagram illustrating an nth-order sigma-delta modulator system according to the invention; Figure 2 is a block diagram illustrating an nth-order feedforward modulator based on the connect¬ ing of an integrated signal estimate error and suit¬ able for use as a modulator block SD1 in Figure 1; and Figure 3 is a block diagram illustrating an nth-order feedforward modulator suitable for use as a modulator block SD2 in Figure 1. Detailed Description of the Invention The present invention has a special range of applications in oversampled A/D converters. Over¬ sampling generally means that the sampling frequency Fs is substantially higher than the lowest sampling frequency determined by the Nyquist criterion, which is two times the highest frequency of the signal. The sampling frequency usually applied in oversampling is an integer multiple of the Nyquist frequency, e.g. 32 or 64 (oversampling ratio). However, the invention is applicable in any applications utilizing a higher-order sigma-delta modulator. Figure 1 illustrates generally the cascading of two nth-order modulators SD1 and SD 2 according to the invention, but it is equally possible in the invention to cascade several modulators in the same way. An input signal Din to be quantized is applied to a first modulator block SDl, which produces a quantized 1-bit output signal D', which is delayed in a delay block 5 by a delay z "k , and the delayed quantized signal D" is applied to one input in a subtractor means 6. An integrated signal estimate error e of the modulator block SDl is first scaled by a coefficient 1/C and then applied to the second modulator block SD2, which produces a quantized error signal e'. The signal e' is differentiated by a digital filter block 3 forming a differentiator, the transfer function (1-z- "1 )" of the filter block 3 being substantially equal to the inverse function of the common transfer function of the integration stages of the modulator block SDl. The differentiated and quantized error signal e" is scaled by a coefficient C (the reciprocal of 1/C), and the scaled error signal e q is applied to another input in the subtractor means 6. As a result, the quantized error signal e q is subtracted from the delayed quantized primary signal D", so that only the 2*nth-order quantizing noise of the modulator block SD2, dif¬ ferentiated n times, is retained in the output signal D' of the system. In practice, it is preferable that the modulator blocks SDl and SD2 are of the same order and have the same coefficient values. If the modul¬ ator blocks SDl and SD2 are not of the same order or have not the same number of delays, the digital filter block 3 is difficult to implement as not only the FIR differentiator but also the IIR part has to be realized by it. Therefore the cascading of modul¬ ator blocks SDl and SD2 of unequal order is a less interesting application. Accordingly, in the pre¬ ferred embodiments of the invention, the order n of the differentiator realized by the block 3 is equal to the order of the modulator blocks SDl and SD2, and it eliminates the effect of the common transfer function of the integrations of the modulator block SDl on the quantized error signal e' . The delay k of the delay block 5 has to be equal to the delay of the modulator block SD2, that is, the combined delay of its integrators. In the practical implementation the delay k consists of a number of clock periods equal to the order n of the modulator block SDl, that is, n = k. The error signal is scaled by a coefficient 1/C, and so the voltage of the error signal will fall within the linear operating range of the block SD2. Thereafter the digital output of the block SD2 is scaled by the coefficient C so that the original signal level will be restored. The minimum value of the coefficient C is the ratio between the modulator coefficients b n /b 1 . The system, however, is operative even at higher scaling coefficients C, although the SNRQ deteriorates with the increasing coefficient. Nth-order feedforward modulator structures will be described below as illustrating embodiments, which can be used as the blocks SDl and SD2 in the modulator system according to the invention. Figure 2 shows a feedforward modulator struc- ture suitable for use as SDl, comprising a series connection of a subtractor 26 and n integration stages 21-1 ... 21-n in this order. The output volt¬ age D- L -D- jj of each integration stage 21-1 ... 21-n is connected through a respective scaling means 24-1 ... 24-n (each voltage being scaled by a respective coupling coefficient bl-bn) to a summing means 25, which combines the scaled voltages D^D.. and applies the sum voltage Ds to a quantizer 23. The quantizer 23 is a combination of an A/D and a D/A converter, in which the analog voltage Ds is converted by the A/D converter 23A to a discrete digital value D' , which is the output signal of the modulator SDl and which is immediately thereafter converted back to an analog voltage Df (value) by the D/A converter 23B so as to establish a negative feedback from the output of the quantizer 23 to the input of the modulator SDl. For this purpose the quantized output signal D', that is, the signal estimate, is converted by the D/A con¬ verter 23B into an analog voltage Df and then applied to one input in the subtractor 26 to be subtracted from the input voltage Din applied to the integration stage 21-1. The difference voltage DO between the voltages Din and Df is the signal estimate error. The output voltage of the last integration stage 21-n, that is, the integrated signal estimate error Dn may be the error voltage e applied to the next modulator stage SD2 when scaled by the coeffi¬ cient 1/C in a scaling means 28. In such a case the modulator does not comprise a subtractor 27 and a scaling means 29. Alternatively, it is possible to use a subtractor 27 to one input of which the output volt¬ age of the integration stage 21-n is applied. The output signal D' of the quantizer 23 is weighted (after having been converted into an analog voltage by the A/D converter 23B) by a scaling coefficient x (where 0 < x < 4*bl/b2) in the scaling means 29 and further applied to another input in the subtractor 27 (as shown by the broken lines) so as to be subtracted from the voltage Dn, that is, from the integrated signal estimate error to obtain their difference voltage e, which is preferably scaled in a scaling means 28 by a scaling coefficient 1/C smaller than one (at least h,/^) to decrease the signal level to the operating range of the next modulator block SD2. Figure 3 shows a feedforward-type sigma-delta modulator structure suitable for use as the modulator block SD2. In Figure 3 the modulator comprises a series connection of a subtractor 36 and n integration stages 31-1 ... 31-n in this order. The output voltage e^e.. of each integration stage 31-1 ... 31-n is connected through a respective scaling means 34-1 ... 34-n (each voltage being scaled by a respective coupling coefficient bl-bn) to a summing means 35. The output voltage of the last integration stage 31-n is connected to the summing means 35 through a delay block 37 connected in series with the scaling means 34-n. The delay z ~(1-d2) of the delay block 37 is zero when the delay d2 of the integration stage 31-n is one, and z "1 when the delay of the integration stage 31-n is unequal to 1 (d2 = 0). The summing means 35 combines the scaled voltages & j _-e n and applies the sum voltage es to a quantizer 33. The quantizer 33 is a combination of an A/D and a D/A converter, in which the analog voltage es is con¬ verted by the A/D converter 33A into a discrete digital value e', which is the output signal of the modulator SD2 and which is immediately thereafter converted back to an analog voltage ef (value) by the D/A converter 33B so as to establish a negative feed¬ back from the output of the quantizer 33 to the input of the modulator SD2. For this purpose the quantized output signal e' , that is, the signal estimate is converted into an analog voltage ef by the D/A con- verter 33B and applied to one input in the subtractor 36 to be subtracted from the input voltage e of the integration stage 31-1. The output of the quantizer 33 gives a quantized error signal e' which is applied to the differentiator block 3 shown in Figure 1. If the transmission zeros of the noise function of the modulator are to be transferred from the zero frequency, the output voltage e n of the integration stage 31-n is feedbacked through a scaling means 39 having a feedback coefficient "a" to a subtractor 38 in the input of the preceding integration stage 31- (n-1) to be subtracted from the input voltage of the integration stage. The subtractor 38 is, of course, omitted if the feedback is not provided. The transfer of the transmission zeros from the zero frequency imposes a few additional requirements on the blocks SDl and SD2. The integrators of the modulator blocks SDl and SD2 have to be delayed (generally a delay of at least two clock periods in the outermost modulator feedback loop of the quantized value, including the integrator delays; and a delay of one or two clock periods for the feedback "a", including the integrator delays) in order that the block SD2 could produce a transmission zero in the noise function. If the feedback loop "a" comprises one delay, the trans- mission zero will be positioned accurately on the unit circle of the z domain, and infinite attenuation will be obtained at this point. On the contrary, if the feedback loop "a" comprises two delays, the transmission zero will be positioned on a line which is tangent to the unit circle at a point (1, 0) so that an absolutely accurate transmission zero is obtained at this point only; the zeros, however, are positioned so close to the circumference of the unit circle at oversampling ratios greater than 64 that there is no significant difference in the amount of quantizing noise on the signal band as compared wxxh the accurate zero. If the order n of the modulator blocks SDl and SD2 is higher than or equal to 3, the modulator block SD2 has to comprise at least two delayed integration stages to achieve the trans- mission zero. The figures and the description related to them are only intended to illustrate the present inven¬ tion. In its details, the modulator system according to the invention may vary within the scope and spirit of the attached claims.

Claims: Claims : 1. Method for cascading at least two feed¬ forward-type sigma-delta modulators, wherein an error of one modulator in the cascade is quantized by the next modulator in the cascade, the quantized error is differentiated, and the differentiated error is subtracted from the quantized output signal of said one modulator, c h a r a c t e r i z e d in that the error is the error of the integrated signal estimate of said one modulator. 2. Method according to claim 1, c h a r a c ¬ t e r i z e d in that said error signal is the out- put voltage of the last integration stage of said one modulator. 3. Method according to claim 1, c h a r a c ¬ t e r i z e d in that said error signal is obtained by scaling the quantized output signal of said one modulator by a predetermined scaling coefficient and by subtracting the scaled quantized output signal from the output voltage of the last integration stage of said one modulator stage. 4. Sigma-delta modulator system comprising a first sigma-delta modulator (SDl) having at least two integration stages (21) and a quantizing means (23), for quantizing a primary signal (Din); a means for providing an error signal (e) representing the quantizing noise of the first modulator (SDl); a second sigma-delta modulator means (SD2) having at least two integration stages (31) and a quantizing means (33), for quantizing said error signal (e); a differentiation means (3) having a transfer function substantially equal to the inverse function of the common transfer function of the integration stages of the first modulator means, for differen¬ tiating the output signal (e' ) of the second modul- ator means; a means (5) for delaying a quantized primary signal (D' ) in an amount corresponding to the delay of the second modulator means (SD2); and a means (6) for subtracting the differentiated error signal (e", e q ) from the delayed quantized primary signal (D"), c h a r a c t e r i z e d in that said error signal (e) is the integrated error of the signal estimate of the first modulator (SDl). 5. System according to claim 4, c h a r a c - t e r i z e d in that the first modulator (SDl) com¬ prises a summing means (25) for summing the scaled output voltages (Dl-Dn) of the integration stages (21) and for applying the sum voltage (D) to the quantizing means (23), and a feedback means (26) for effecting a negative feedback from the output of the quantizer (23) to the input of the first integration stage (21-1). 6. System according to claim 4 or 5, c h a r ¬ a c t e r i z e d in that said error signal (e) is the output voltage (Dn) of the last integration stage (21-n) of the first modulator (SDl). 7. System according to claim 4, 5 or 6, c h a r a c t e r i z e d in that the first modulator (SDl) comprises a second scaling means (29) for scaling the output signal (D' ) of the quantizer (23), and a subtractor means (27) for subtracting the output signal of said second scaling means (29) from the output voltage (Dn) of the last integration stage (21-n) of the first modulator means so as to provide said error signal (e). 8. System according to any of claims 4 to 7, c h a r a c t e r i z e d in that the second modulator (SD2) comprises a negative feedback from the output of at least one integration stage (31-n) to the input of the preceding integration stage, and that at least the feedbacked integration stage or the integration stage preceding it is delayed. 9. System according to any of claims 4 to 8, c h a r a c t e r i z e d in that it comprises a third scaling means (28, 38) for scaling the error signal (e) by a first scaling coefficient smaller than one before the second modulator means (SD2), and a fourth scaling means (4) for scaling the quantized error signal (e', e" ) by a second scaling coefficient substantially equal to the reciprocal of the first coefficient before the error signal is subtracted from the quantized primary signal (D").

Inventors: KAREMA TEPPO, RITONIEMI TAPANI, TENHUNEN HANNU, KAREMA, TEPPO, RITONIEMI, TAPANI, TENHUNEN, HANNU
Applicants: RITONIEMI TAPANI, RITONIEMI, TAPANI
Application year: 1993
Main classification: H03M3
IPC codes: H03M3