Driving circuit for a field effect transistor in final semibridge stage

Abstract: A drive circuit for a field-effect transistor (MFET1) which has a drain terminal connected to the positive pole (+Vcc) of the power supply and a source terminal connected to a load (OUT). The circuit has circuit means for turning off the field-effect transistor (MFET1) which comprises a first transistor (M1) connected between the gate terminal of the field-effect transistor (MFET1) and the negative pole (GND) of the power supply. Said first transistor (MFET1) is driven by an operational amplifier (M3,M4,MR1,MR2,MR3) which has inverting and non-inverting terminals connected to the gate and source terminals of the field-effect transistor (MFET1) respectively.

Description: The present invention relates to drive circuits for driving field-effect transistors, in particular field-effect power transistors used either in the upper output stage of bridge or half-bridge circuit structures, or as the final stage of a structure commonly referred to as "High Side Driver" in said stages being provided a single output transistor connected to the positive supply pole. As is known to the skilled man, the above-outlined structures are used extensively to drive motors and inductive loads in general, using transistors either of the bipolar or the field-effect type. The half-bridge structure is specifically employed to drive brushless and stepper motors, and to transmit high-voltage logic signals, mainly using field-effect transistors. In fact, wherever the implementing technology so allows, VDMOS (Vertical Double Diffused MOS) components are used as field-effect transistors on account of the many advantages that they afford over the bipolar components. The two field-effect transistors which form a half-bridge are connected in series with each other between the two terminals of a voltage supply generator, in other words between the "power supply" and the ground potential, and are alternately driven into conduction by control circuit means coupled to their gate terminals. The voltage amplitude of the output signal from the linking node between the two transistors is both dependent on the output current and the saturation resistance of the conducting transistor. To minimize the voltage drop between the power supply and the output, it's necessary to impose to the upper transistor, during the conduction phase, a gate voltage higher than the source voltage (usually about 10 V), to optimize the saturation resistance. Such circuitry is known from PATENTS ABSTRACTS OF JAPAN, vol. 14, no. 22, (E-874), 17 January 1990 & JP-A-12 64 311. By methods well known to those skilled in the art, e.g. through the use of a voltage multiplier, a predetermined optimum voltage amount is established, which is higher than the supply voltage, and this higher voltage is applied, during the conduction phase, to the gate terminal of the upper transistor to provide optimum gate/source voltage independently of the supply voltage. It is common practice to protect the upper transistor against unavoidable voltage peaks -- which are even higher than this optimum voltage anddue to the on/off transistors -- by means of two Zener diodes connected between the source and the drain, reversed one from the other. On the contrary, the problem does not exist with the lower transistor, which would be automatically protected being driven by internally generated voltages. In addition, the source terminal of the lower transistor is always maintained at a reference potential, whereas the source terminal potential of the upper transistor may vary between the two potential levels of the voltage supply generator, that is to say between the "power supply" and the ground potential. A conventional method of turning off the upper field-effect transistor is the one which provides the gate terminal of such transistor to be led to ground via a depletion current generator connected in series with a switch to be closed during the off phase. The current generator may be connected to a reference voltage, and the switch may be another field-effect transistor driven to switch over. An improvement on this arrangement has been provided in practice by connecting the gate terminal of the upper field-effect transistor to a depletion current generator, again via a switch, not directly but with the interposition of a PNP type of bipolar transistor, the emitter and collector terminals of said bipolar transistor being directly connected to the gate and source terminals respectively of the field-effect transistor and its base terminal being coupled to the ground depletion current generator via the switch. The advantages of the last-mentioned arrangement for turning off a field-effect transistor in an upper final stage are that the transistor own gate capacitance discharge current can be dissipated directly to the load, and that upon turning back on, the gate terminal will already be at the same potential as the source terminal, which doesn't need to be the ground potential. Furthermore, the current from the depletion current generator is lowered by a factor equal to the PNP transistor gain. Disadvantages inherent to the presence of a bipolar transistor are, however, frequency limitations and increased integration area requirements. Moreover, if a higher voltage than the drop voltage on the base/collector junction of the PNP transistor is imposed at the output, a pull from the output occurs through said junction. Specifically in the instance of a half-bridge structure -- but obviously not in that of the High Side Driver -- with the circuit configurations above described, in the case where the device is used as a line driver, or for driving loads connected to the positive supply pole, a further problem is posed. When the upper transistor is turned off through the depletion current generator and the lower transistor turned back on, it may happen that the potentials at the source and gate terminals of the upper stage transistor may be enough to turn this transistor back on, thereby an uncontrolled current would be produced, commonly referred in the art to as "cross-current". From document US-A-4 672 246 a MOSFET transistor switch control circuit is known wherein the voltage present at the source of the MOSFET is mirrored to the gate terminal thereof. The turn-off circuit thus establishes a floating gate-to-source voltage differential of zero volts, independent of the voltage actually appearing at the source, without requiring any direct current conduction path between gate and source terminals of the MOSFET. The underlying technical problem of this invention is to provide a drive circuit for a field-effect transistor which is suitable to be used in the upper stage of a half-bridge structure, which can operate at high switching rates with no cross-current appearing during the switching phases irrespective of the load, and which can provide, in the event of the transistors being turned off simultaneously, a very high output impedance with no current draw. This problem is solved by a drive circuit for field-effect transistors as defined in the characterizing portion of Claim 1. The features and advantages of a drive circuit according to the invention will become apparent from the following description of an embodiment thereof, given by way of example with reference to the accompanying drawing. The drawing single Figure is a circuit diagram showing a field-effect transistor for the upper stage of a half-bridge structure and a drive circuit according to this invention, which can be integrated monolithically using MOS-type or combination technologies. The diagram shown in the drawing includes a field-effect transistor MFET1, which may be a VDMOS type and has its source and drain terminals connected to an output terminal OUT and to a positive pole of a voltage supply generator +Vcc respectively. The gate terminal of the transistor MFET1 is connected, via a switch S1, to a reference voltage Vcp, having a higher potential than the pole +Vcc. The drive circuit for said transistor comprises a first transistor M1, which is connected in series with a second switch S2 between the gate terminal of transistor MFET1 and a negative pole of the voltage supply generator, i.e. ground potential, GND. The gate terminal of transistor M1, and that of a second transistor M2, are connected to the pole +Vcc through a constant current generator G1. The second transistor M2 is connected, in series with a third switch S3, between a differential structure, comprising third M3 and fourth M4 transistors, and the ground potential GND. The gate terminals of transistors M3 and M4 are connected to the gate terminal of transistor MFET1 and the output terminal OUT respectively. A Zener diode DZ1 is connected between the switch S3 and the gate terminal of transistor MFET1. The transistors M3 and M4 are connected to the input legs of first MR1 and second MR2 current mirror circuits respectively. The output leg of circuit MR1 is connected to the gate terminal of transistor M1. The output leg of circuit MR2 is connected, via a third current mirror circuit MR3, to the gate terminal of transistor M2. The gate terminals of transistors M3 and M4 constitute the non-inverting and inverting input terminals of an operational amplifier which comprises the transistors M3, M4 and circuits MR1, MR3, and has its output connected to the gate terminal of transistor M1. Control circuit means, not shown in the drawing, drives the switches; the switches S2 and S3 are in the turned off state only when the switch S1 is turned on, and vice versa. Closing the switch S2 results in the transistor MFET1 being turned off through the charge depletion transistor M1. Closing the switch S3, on the other hand, enables the operational amplifier to thereby set to operation the differential structure and the current mirror circuits through the transistor M2 which has current generator functions. The input stage of the operational amplifier is preferably implemented with field-effect devices, to avoid current pulling through the inputs whereby the source and gate voltages of the transistor MFET1 are measured. With this arrangement no current will thus be pulled from the output in the instance of both transistors being off in the half-bridge structure. The principle on which the illustrated circuit operates is the following. With the switches S2 and S3 in the on state, the transistor MFET1 can be turned on by closing the switch S1 which brings the gate of MFET1 to the voltage Vcp. In the off state, the switch S1 opens the contact between the gate and the reference voltage Vcp, while the switch S3 enables the operational amplifier. At this point, the gate of MFET1 is discharged from the transistor M1 driven by the operational amplifier so long as a potential difference exists across the operational amplifier inputs. Of course, the switch S2 should also be closed. Thus, at the end of the transient period, by virtue of the negative feedback, the gate of transistor MFET1 will attain a balance voltage, which is tied both to the source voltage, i.e. the voltage at the output OUT, and the voltage established by means of the Zener diode DZ1, which is essential to the definition of a balance voltage. During the on phase of transistor MFET1, the switch S1 will be closed, and the switches S2 and S3 open. Accordingly, the differential stage consisting of the transistors M3 and M4 will be disabled because it becomes disconnected from the transistor M2, and the gate of transistor MFET1 will be at the same voltage as Vcp because it becomes disconnected from the transistor M1 and connected to the reference voltage Vcp. For turning off the transistor MFET1, the switch S1 is opened and both switches S2 and S3 closed. The differential stage comprising the transistors M3 and M4 will be enabled by the current pull by the transistor M2, presently in the on state, and the transistor M3, whose gate is at a higher potential than the gate potential of transistor M4 will go into conduction. Simultaneously therewith, the gate of transistor MFET1 is discharged by transistor M1, and after a time period, will attain the same voltage level as the source of MFET1, whereupon the transistor M4 begins to conduct and transistor M3 turns to the off state. As soon as the transistor M4 begins to conduct, the current mirror circuits will also conduct, to generate a current which tends to turn off the transistors M1 and M2. The gate of transistor MFET1 continues to be discharged until a balanced condition is reached wherein the transistor M3 is off, transistor M4 is on, Zener diode DZ1 is directly biased, and transistors M1 and M2 absorb the current that keeps flowing. In conclusion, the advantages of a circuit according to the invention can be summarized as follows: No current pull from the output, irrespective of the voltage value applied thereto; in the instance of a half-bridge structure, and irrespective of the load, no cross-currents occurs during the switching phases, since the source and gate of the upper transistor MFET1 are measured any time; and high-frequency switching can take place without problems. While an exemplary embodiment of the invention has been described and illustrated in the foregoing, changes and modifications may be made thereunto within the scope of the inventive concept. As an example, the transistors M1, M2 and those comprising the current mirror circuits could be replaced with suitably biased bipolar transistors, and the constant current generator could be connected to a different voltage reference.

Claims: A drive circuit for driving at least one field-effect transistor (MFET1) which has a first terminal for the connection to a positive pole of a voltage supply generator (+VCC), a second terminal for the connection to a load, and a control terminal for the connection to a reference voltage (VCP) having a higher potential than the positive pole (+VCC) of the voltage supply generator, comprising control circuit means driving a first switch (S1) connected between the voltage reference (VCP) and the control terminal of the field-effect transistor (MFET1), and circuit means for turning off the field-effect transistor, which comprise an operational amplifier (M3,M4,MR1,MR2,MR3) having a non-inverting input terminal connected to the control terminal of the field-effect transistor (MFET1), a terminal with an inverting input connected to the second terminal of the field-effect transistor, an output terminal and at least one enable terminal coupled to the control circuit means, characterized in that the circuit means for turning off the field-effect transistor comprise also a first transistor (M1) having a first terminal connected to the control terminal of the field-effect transistor (MFET1) through a second switch (S2) driven by the control circuit means, a second terminal connected to a negative pole (GND) of the voltage supply generator, and a control terminal connected to the output terminal of the operational amplifier, and in that the operational amplifier (M3,M4,MR1,MR2,MR3) is enabled by the control circuit means when the first switch (S1) is open and the second switch (S2) is closed. A drive circuit according to Claim 1, characterized in that the operational amplifier comprises an input stage (M3,M4) with field-effect devices connected directly to the input terminals. A drive circuit according to Claim 1, characterized in that the enable terminal of the operational amplifier is connected to a current generator circuit means (M2) through a third switch (S3) driven by the control circuit means. A drive circuit according to Claim 3, characterized in that the current generator circuit means is a second transistor (M2) connected between the third switch (S3) and the negative pole (GND) of the voltage supply generator, and has a control terminal connected to the output terminal of the operational amplifier and also connected to the positive pole (+VCC) of the voltage supply generator via a constant current generator (G1). A drive circuit according to Claim 4, characterized in that the operational amplifier has a differential input stage comprising third (M3) and fourth (M4) transistors, each having first and second terminals and a control terminal, the control terminals of the third and fourth transistors being the non-inverting terminal and the inverting terminal of the operational amplifier respectively, and the second terminal of each of said transistors being connected to the enable terminal of the operational amplifier. A drive circuit according to Claim 5, characterized in that the operational amplifier comprises first (MR1), second (MR2), and third (MR3) current mirror circuits, each having an input leg and an output leg, the input and output legs of the first current mirror circuit (MR1) being connected to the first terminal of the third transistor (M3) and to the control terminal of the first transistor respectively (M1), the input and output legs of the second current mirror circuit (MR2) being connected to the first terminal of the fourth transistor and to the input leg of the third current mirror circuit (MR3) respectively, the output leg of the third current mirror circuit being the output terminal of the amplifier. A drive circuit according to Claim 5, characterized in that the operational amplifier comprises a Zener diode (DZ1) connected between the second terminal and the control terminal of the third transistor (M3). A drive circuit according to any of the preceding claims, characterized in that each transistor is a field-effect transistor, and that the first and second terminals and the control terminal of each transistor are drain, source, and gate terminals respectively.

Inventors: GARIBOLDI ROBERTO, PULVIRENTI FRANCESCO, GARIBOLDI, ROBERTO, PULVIRENTI, FRANCESCO
Applicants: CONS RIC MICROELETTRONICA, SGS THOMSON MICROELECTRONICS, CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1993
Main classification: H03K17
IPC codes: H03K17