Pulse-width modulator for class D amplifier

Abstract: A hysteresis-type pulse width modulator for a class D audio amplifier converts an input voltage into a pulse width modulated waveform. The width of the pulses is related to the input voltage amplitude. The modulator comprises a window comparator, a supply voltage source having a pair of terminals across which a supply voltage is provided, and a hysteresis voltage source having a pair of terminals across which a hysteresis voltage is provided. The hysteresis voltage source comprises a multiplier, a comparator for adding the supply voltage and input voltage to generate a sum voltage, and a comparator for subtracting the input voltage from the supply voltage to generate a difference voltage. The audio amplifier output stage comprises first and second solid state devices, each having a controlled current conducting path comprising first and second terminals and a controlling current conducting path comprising at least a third terminal. The output stage also includes an uncontrolled current conducting path in antiparallel relation with each of the devices' controlled current conducting paths. A saturable reactor is positioned in series with the uncontrolled current conducting path to limit current flow therethrough during the switching of current flow from the controlled current conducting path of one of the devices to the uncontrolled current conducting path occasioned by operation of the amplifier.

Description: This invention relates to improved class D amplifiers. It is disclosed in the context of a class D audio amplifier, but is believed to have applicability to class D amplifiers for other applications as well. In class D audio amplifier design, hysteresis pulse width modulators have the inherent advantages of low distortion, high power supply rejection, and automatic compensation for any switching waveform anomalies caused by non-ideal components. However, the operating frequency of circuits employing class D technology varies dramatically with input signal voltage. The operating frequency for the prior art circuit of Fig. 1 can be shown to be: 2π f pwm = (V s -V i ) (V s +V i) 2 C R V s V h Where ± V s = supply voltage; V i = input signal voltage; V h = hysteresis voltage; C = capacitance, in farads, of the integrating capacitor; and, R = resistance, in ohms, of the feedback and input resistors. For purposes of this discussion, the resistances of the input and feedback resistors are considered equal (unity gain). However, relevant principles hold with any designed gain. In the operation of the Fig. 1 circuit, all terms on the right hand side of equation (1) are constants with the exception of V i , the audio input signal voltage. As the input signal voltage instantaneously approaches either supply voltage (± V s ), one or the other of the terms in the numerator of equation (1) approaches zero. The operating frequency drops accordingly. This drop in frequency can permit the pulse width modulator's own lowered switching frequency to appear as an audible artifact in the output signal. This problem is discussed e.g. in Elektronik 23, Nov. 1988, pages 112-116, by H. Sax in the article : "Schalten statt Heizen". According to the invention, a hysteresis-type pulse width modulator converts an input voltage into a pulse width modulated waveform, the width of the pulses of which is related to the input voltage amplitude. The modulator comprises a window comparator, a supply voltage source having a pair of terminals across which a supply voltage is provided, and a hysteresis voltage source having a pair of terminals across which a hysteresis voltage is provided. The hysteresis voltage source comprises a multiplier, a comparator for adding the supply voltage and input voltage to generate a sum voltage, and a comparator for subtracting the input voltage from the supply voltage to generate a difference voltage. The input voltage is provided to the sum voltage generating comparator and difference voltage generating comparator. The supply voltage source is coupled to the sum voltage generating comparator and difference voltage generating comparator. The sum voltage generating comparator and difference voltage generating comparator are coupled to the multiplier. The multiplier is coupled to the window comparator. According to an illustrative embodiment of the invention, the hysteresis-type pulse width modulator comprises an integrator, the window comparator, the hysteresis voltage source, and a flip-flop. The input voltage is coupled to the integrator, the integrator to the window comparator, the window comparator to the flip-flop, and the hysteresis voltage source to the window comparator. Further illustratively according to the invention, the window comparator comprises first and second comparators, each having non-inverting and inverting terminals. The integrator is coupled to the window comparator by coupling an output terminal of the integrator to a non-inverting input terminal of the first comparator and to an inverting input terminal of the second comparator. The hysteresis voltage source is coupled to the window comparator by coupling a first of the pair of terminals of the hysteresis voltage source to the inverting input terminal of the first comparator and a second of the pair of terminals of the hysteresis voltage source to the non-inverting input terminal of the second comparator. The invention may best be understood by referring to the following descriptions and accompanying drawings which illustrate the invention. In the drawings: Fig. 1 illustrates a partly block and partly schematic diagram of a prior art hysteresis pulse width modulator equipped class D amplifier; Fig. 2 illustrates a partly block and partly schematic diagram of a hysteresis pulse width modulator equipped class D amplifier according to an aspect of the invention; Fig. 3 illustrates a partly block and partly schematic diagram of a class D amplifier driver and output stage according to an aspect of the invention; Fig. 4 illustrates a more detailed block and schematic diagram of part of an embodiment of the invention; and, Fig. 5 illustrates a more detailed block and schematic diagram of part of an embodiment of the invention. In Fig. 1, a difference amplifier 10, which illustratively is one-half of a National Semiconductor LM833, is coupled in integrator amplifier configuration to receive at its inverting (-) input terminal the input voltage signal V i through an input resistor 12. The non-inverting input terminal (+) of difference amplifier 10 is coupled to ground. An integrating capacitor 14 is coupled across the output terminal and - input terminal of amplifier 10. The output terminal of amplifier 10 is coupled to the + input terminal and - input terminal, respectively, of two difference amplifiers 16 and 18. The - input terminal of amplifier 16 is coupled to one terminal of a hysteresis voltage source 20 (illustrated as a battery) which provides a constant output voltage V h . The other terminal of source 20 is coupled to the + input terminal of amplifier 18, and to ground. Difference amplifiers 16, 18 illustratively are each one-half of a National Semiconductor LM319. The coupling of difference amplifiers 16, 18 in this configuration constitutes a window comparator 22, the output terminals 24, 26 of which provide positive-going pulses at the S and R input terminals, respectively, of an SR flip-flop 28, depending upon whether the output signal from amplifier 10 is above V h or below ground, respectively. The Q output terminal of flip-flop 28 provides the modulated width pulses of the pulse width modulator 30 of Fig. 1. Flip-flop 28 illustratively is half of an RCA CD4011 quad NAND gate. In a class D audio amplifier these signals are then supplied to a basic, or power, amplifier 32, the output of which is supplied through a low pass filter including an inductor 34 in series and a capacitor 36 in parallel with a primarily resistive load 38, which illustratively is the voice coil of a moving coil loudspeaker. Feedback customarily is provided from an output terminal of power amplifier 32 to the - input terminal of amplifier 10 through a feedback resistor 39. The deficiency of this circuit is an previously discussed. The pulse width modulator 30's own reduced operating frequency f pwm can pass though the low pass filter 34, 36 and appear in the audio output of transducer 38. In the circuit of Fig. 2, the hysteresis voltage, V h , is made to vary in a compensatory manner with V i so that the pulse width modulator 30's operating frequency f pwm remains constant throughout the range of input voltage V i . As Fig. 2 illustrates, an analog multiplier is used to provide a varying hysteresis voltage, V h ', according to the following relationship: V h ' = K 2 (V s -V i ) (V s +V i ) where K is a constant. Inputs to the multiplier are K(V s -V i ) and K(V s +V i ) which are readily available. Substituting V h ' in equation (1) gives the operating frequency f pwm of the circuit in Fig. 2 as follows: 2π f pwm = (V s -V i ) (V s +V i ) 2 C R V s K 2 (V s -V i ) (V s +V i ) = 1 2 C R V s K 2 It will be appreciated that all terms in the final form of equation (3) are constants. Thus, f pwm is a constant, independent of V i . In the improved class D audio amplifier of Fig. 2, those components which perform the same or similar functions to components illustrated in Fig. 1 are identified by the same reference numbers. A hysteresis voltage (V h ') supply 42 includes first 44 and second 46 difference amplifiers and a multiplier 48. The input voltage V i is coupled to the + input terminal of the first difference amplifier 44 and to the - input terminal of the second difference amplifier 46. The - input terminal of first difference amplifier 44 is coupled the -V, terminal. The + input terminal of second difference amplifier 46 is coupled to the +V s terminal. The signals at the output terminals of difference amplifiers 44, 46 are thus K(V s + V i ) and K(V s - V i ), respectively, where K is a constant, the gain of amplifiers 44, 46. These signals are coupled to two input terminals of multiplier 48 to provide the K 2 (V s - V i ) (V s + V i ) or V h ' hysteresis voltage signal required by equation (3) to the window comparator 22. In the embodiment illustrated in Fig. 2, the operating frequency f pwm of the pulse width modulator 40 has thus been rendered a constant, insensitive to the input voltage V i . Amplifiers 44, 46 and multiplier 48 illustratively are collectively realized by a ROHM BA6110 operational transconductance amplifier. Turning now to Fig. 3, a basic amplifier 32 receives appropriately preamplified and otherwise processed signals from a logic drive source 50 which includes SR flip-flop 28 of Figs. 1-2. The driver stage of amplifier 32 includes a final driver inverting amplifier 52 and a pair of output MOSFET switches 54, 56. Switches 54, 56 illustratively are Motorola MTP 50N06E MOSFETs. Switches 54, 56 are coupled in push pull configuration, with the inverting amplifier 52 inverting the signal which is coupled to the gate of switch 54 and providing this inverted drive signal to the gate of switch 56. Each switch 54, 56 is provided with a body diode 58, 60, respectively. Diodes 58, 60 are formed on the material from which switches 54, 56 are fabricated at the time of fabrication of the switches 54, 56 so that devices 54, 58 are in the same package and devices 56, 60 are in the same package and there are no external leads between devices 54, 58 or between devices 56, 60. The drain lead of MOSFET 54 and cathode of diode 58 are coupled by a suitable conductor 62 to the +V s supply terminal. The source lead of MOSFET 54 and anode of diode 58 are coupled through the series inductor 34 to the parallel combination of capacitor 36 and load 38. The source lead of MOSFET 54 and anode of diode 58 are also coupled to the drain lead of MOSFET 56 and cathode of diode 60 by a suitable conductor 64. The source lead of MOSFET 56 and anode of diode 60 are coupled to the -V s supply terminal. A high magnetic permeability bead 66 is placed on each of conductors 62, 64. During switching of MOSFETs 54, 56, as the polarities of the voltages across diodes 58, 60 reverse and the carriers begin to be swept out of the diodes 58, 60 as a result of this reversal, the tendency of the currents in diodes 58, 60 to surge uncontrolled in conductors 62, 64 is buffered by the saturable reactors 66. Since the reactors 66 saturate at relatively low current flows, the only times they affect the currents in conductors 62, 64 is during this reversal of the direction of current flow in conductors 62, 64. The rest of the time, that is, during periods of high current flow or no current flow in conductors 62, 64, saturable reactors 66 are invisible to the circuit of Fig. 3. Turning now to the more detailed schematic diagram of Fig. 4, the various illustrated pin numbers on the illustrated integrated circuits and devices refer to the specific integrated circuits and devices which have already been identified or will be identified herein. However, that does not constitute a representation, nor should any such representation be inferred, that there are no integrated circuits or devices other than those identified herein that will perform the functions performed by the identified integrated circuits and devices. Common mode noise rejection in the input signal V i is achieved by an input difference amplifier 80 which illustratively is one half of a National Semiconductor LM833. V i is coupled across the + and - input terminals of difference amplifier 80. Identical 10 K input resistors 12' are provided in series between the V i terminals and the respective + and - input terminals of amplifier 80. A feedback network including a parallel 22.1K resistor and a 47pF capacitor is coupled between the output terminal of amplifier 80 and its - input terminal. An identical parallel RC network is coupled between the + input terminal of amplifier 80 and the signal common. The output terminal of amplifier 80 and the signal common are coupled through identical 3.65K resistors to the - and + input terminals, respectively, of integrating difference amplifier 10. As previously noted, amplifier 10 illustratively is also half of an LM833 and illustratively is the other half of the same LM833 of which amplifier 80 is half. Consequently, +V s is illustrated connected to pin 8 of amplifier 80 and -V s , which in the illustrated embodiment is the chassis voltage of the circuit, is illustrated connected to pin 4 of amplifier 10. The remaining power supply connections to these amplifiers are made on the integrated circuit chip on which they are realized. A .0033µF integrating capacitor 14 is coupled between the output terminal of amplifier 10 and its - input terminal. The + input terminal of amplifier 10 is coupled through a .0015µF capacitor to the - input terminal of difference amplifier 16, and through a .0015µF capacitor to the circuit common. The output terminal of amplifier 10 is coupled to the + input terminal of difference amplifier 16 and to the - input terminal of difference amplifier 18. The + input terminal of amplifier 18 is coupled to the circuit common. Again, difference amplifiers 16, 18 are configured as a window comparator 22, and are realized on a National Semiconductor LM319 integrated circuit whose power supply terminals, pins 11 on the one hand and 3, 6 and 8 on the other, are coupled across the +V s and -V s (chassis) supply terminals. The output terminals 24 and 26, respectively, of amplifiers 16, 18 are coupled to the S and R input terminals, respectively, of SR flip flop 28. Flip flop 28 is realized by two, 84, 86, of the two-input NAND gates of an RCA CD4011B quad, two-input NAND gate integrated circuit. 3K pull up resistors couple the S and R input terminals, pins 6 and 1, respectively, of flip flop 28 to switched +V s . Pin 14 of flip flop 28 is also coupled to switched +V s . Pin 7 of flip flop 28 is coupled to -V s (chassis). The output terminal of NAND gate 84 is coupled to the remaining input terminal of NAND gate 86 and the output terminal of NAND gate 86 is coupled to the remaining input terminal of NAND gate 84. Both input terminals of each of the two remaining NAND gates on the CD4011B are coupled to -V s and their output terminals are left open. The drive for the output FETs is provided by two identical output driver circuits 88, 90, only one of which will be described in further detail here. The Q output, pin 4, of flip flop 28 is coupled to the gate electrode of an FET 92, which illustratively is a type 2N7000 FET. The source of FET 92 is coupled to -V, and its drain is coupled through a 1K resistor to +3V s which is generated as will be described hereinafter. The drain of FET 92 is also coupled through an 82 Ω resistor to the joined bases of complementary NPN and PNP transistors 94, 96 which illustratively are types 2N4401 and 2N4403 transistors, respectively. The collector of transistor 94 is coupled to +3V s . The collector of transistor 96 is coupled to -V s . Their emitters are joined and form the output terminal 98 of driver circuit 88. The corresponding output terminal of driver circuit 90 is identified by the reference number 100. Each output transistor 54, 56 and its associated flyback diode 58,60, respectively, in the embodiment of Fig. 3 are realized in the embodiment of Fig. 4 by a pair of FETs 54-1, 54-2; 56-1, 56-2, respectively. As previously noted, the flyback diodes are incorporated into the FETs during the manufacture of the FETs. FETs 54-1 and 54-2 serve to provide a pathway for the charging of a .01µF capacitor 102 in a first sense (source of FET 54-1 going more positive with respect to drain of FET 54-2) between the +V s and -V s terminals. FETs 56-1 and 56-2 serve to provide a pathway for discharging capacitor 102 in the first sense or charging it in a second, opposite sense (source of FET 56-2 going more positive with respect to drain of FET 56-1) between the +V s and -V s terminals. The drains of FETs 54-1 and 56-2 are coupled to +V s . The sources of FETs 54-2 and 56-1 are coupled to -V s . The source and drain, respectively, of FETs 54-1 and 56-1 are coupled through capacitor 102 and a series 1Ω ring damping resistor 104 to the drain and source, respectively, of FETs 54-2 and 56-2, respectively. The gates of FETs 54-1 and 54-2 are coupled to terminal 100. The gates of FETs 56-1 and 56-2 are coupled to terminal 98. FETs 54-1, 54-2, 56-1 and 56-2 thus drive the voltage across capacitor 102 up and down between the +V s and -V s supply terminals based upon the switching voltages at the Q and Q terminals, pins 4 and 3, respectively, of flip flop 28. Feedback is provided from the source of FET 54-1 and the drain of FET 54-2 through 10K feedback resistors 39', 39' to the + and - input terminals, respectively, of amplifier 10. The speaker 38 and its associated circuitry 106 are coupled in parallel with the series RC combination 102, 104. The associated circuitry 106 includes a single turn saturable reactor 66 in series with the drain of each of FETs 54-2, 56-2. Reactors 66 are oriented in opposite senses so that, upon any change in current flow in circuit 106, the fields in reactors 66 cancel each other. A nine-turn inductor 34-1, 34-2 is in series between each reactor 66 and a respective terminal of speaker 38. A pair of .39µF capacitors 36-1 and 36-2 in series are coupled across the speaker 38 terminals. A 2.2µF capacitor 36-3 is coupled in parallel with series capacitors 36-1 and 36-2. The junction of capacitors 36-1 and 36-2 is coupled to the -V s terminal. Switching pulses appear across the RC series combination 102, 104 during operation, owing to the recovery of energy stored in the magnetic fields of inductors 34-1 and 34-2. These pulses are coupled through 18µF, 35 VDC capacitors 114, 116 to a full wave diode bridge rectifier 117 which is coupled through a 20Ω resistor to the switched +V s terminal. Rectifier 117 rectifies these pulses to provide a +3V s source. They are filtered and stored by a 120µF, 35 VDC capacitor 118 from which +3V s is supplied to driver circuits 88, 90. Turning to the K 2 (V s + V i )(V s - V i ) generator 42, it includes the operational transconductance amplifier 120 of, for example, a ROHM BA6110 integrated circuit 122. The I abc terminal, pin 4, of integrated circuit 122 is coupled through a 10K series resistor to the output terminal of amplifier 80 to receive the V i signal. V i is also coupled from the output terminal of amplifier 80 through a 10K series resistor to the + input terminal, pin 1, of integrated circuit 122. + V s is coupled through a 10K series resistor to the I d terminal, pin 3, of integrated circuit 122 and through the series combination of two forward biased diodes, illustratively type 1SS133 diodes, and a 10K series resistor to the - input terminal, pin 2, of integrated circuit 122. +V s is also coupled to pins 7 and 9 of integrated circuit 122. -V s is coupled to pin 5 of integrated circuit 122. Pin 6, the output terminal of operational transconductance amplifier 120, is coupled through a 15K resistor to the circuit common, through a 220pF capacitor to -V s (chassis), through a 300K resistor to +V s , and to the + input terminal of a difference amplifier 124 which is configured as a unity gain buffer amplifier. That is, the output terminal of amplifier 124 is coupled to its - input terminal. The output signal from amplifier 124 is coupled to the - input terminal of amplifier 16. Amplifier 124 illustratively is one fourth of a Motorola type MC34074 quad integrated circuit operational amplifier. Muting transistors are provided at appropriate locations throughout the circuit of Fig. 4. These include transistor 126, the collector and emitter of which are coupled across capacitor 14, and the base of which is coupled through a 10K resistor to a suitable source of muting signal. The presence of muting signal on the base of transistor 126 shorts the voltage across capacitor 14. The collector of a muting transistor 128 is coupled to the I abc terminal of operational transconductance amplifier 120. The base of transistor 128 is coupled through a 100K resistor to the muting signal source and through a .047µF capacitor to -V s . The emitter of transistor 128 is also coupled to -V s . A muting signal on the base of transistor 128 shorts the I abc signal on pin 4 of the operational transconductance amplifier 120 to -V s . Transistors 126, 128 illustratively are type 2N3904 transistors. The collector of an additional muting transistor 130 is coupled through a suitable diode, illustratively a type 1SS133, to the drain terminal of FET 92 in each of driver circuits 88, 90. The emitter of transistor 130 is coupled to -V s . The base of transistor 130 is coupled through a 10K resistor to the muting signal source. The muting signal shorts the drive signal for transistors 94, 96 in each of circuits 88, 90 to -V s . Transistor 130 illustratively is a type 2N4401 transistor. A suitable power supply for the amplifier of Fig. 4 is illustrated in Fig. 5. A multiple section LC filter 132 is coupled across a 2V s source, such as a 12VDC vehicle battery. The more negative terminal of the source is denominated -V s . Filter 132 includes a .047µF capacitor 134 across the source, a series 100µH inductor 136 and 1500µF, 16VDC capacitor 138 across capacitor 134, and a series 10µH inductor 140 and 3000µF, 16VDC capacitor 142 across capacitor 134. The voltage which appears at the common terminal of inductor 140 and capacitor 142 is denominated +V s . Overvoltage protection is provided by the series combination of a 1K resistor 144 and a zener diode 146 (illustratively a type 1N5246B) across the common terminal of inductor 140 and capacitor 142 and -V s . The junction of resistor 144 and zener diode 146 is coupled through a 1K resistor to the base of a PNP transistor 148. Transistor 148 illustratively is a type 2N3906. The emitter of transistor 148 is coupled to +V s and its collector is coupled to the base of a PNP transistor 150, illustratively a Motorola type MPS-A56. The emitter of transistor 150 is coupled to +V s . The base of transistor 150 is also coupled to +V s through a 2K resistor, and to the collector of an NPN transistor 152 through a 2K resistor. The emitter of transistor 152 is coupled to -V s . The base of transistor 152 is coupled through a 10K resistor to an on/off signal source. Transistor 152 illustratively is a Motorola type MPS-A06. The collector of transistor 150 forms the switched +V s supply. The collector of transistor 150 is coupled through series 33.2K and 68.1K resistors 156, 158, respectively, to -V s , the amplifier chassis. The common terminal of resistors 156, 158 is coupled to the - input terminal of a difference amplifier 160, the output terminal of which is coupled through a 680pF capacitor to its - input terminal to provide feedback thereto. Series 1K and 5.1K resistors 162, 164, respectively, couple the collector of transistor 150 to the output terminal of amplifier 160. The emitter of a transistor 166 (illustratively a type 2N4403) is coupled to the collector of transistor 150. The base of transistor 166 is coupled to the common terminal of resistors 162, 164. The collector of transistor 166 is coupled through a series voltage divider including a 120K resistor 165 and a 2.7K resistor 167 to -V s . The junction of resistors 165, 167 is coupled to the base of transistor 152. The collector of transistor 166 is also coupled through four series forward-biased diodes 168 (illustratively, type lSS133s) and a 5.1K resistor 170 to -V s . The common terminal of diodes 168 and resistor 170 is coupled to the + input terminal of amplifier 160. The collector of transistor 166 forms the regulated +V s terminal of the supply of Fig. 5. Identical parallel RC networks 171, each including a 10K resistor 172 and a .047µF capacitor 174, are coupled in series across the regulated +V s and-V s terminals. The common terminal of these two RC networks 171 is coupled to the + input terminal of a difference amplifier 176. Networks 171 divide in half the +V s to -V s voltage. This voltage is buffered by amplifier 176, which is configured as a unity gain amplifier, to provide at the output terminal of amplifier 176 the signal common for the circuits of Figs. 4-5. The muting signals for transistors 126, 128 and 130 of Fig. 4 are developed from the regulated +V s supply through a series RC time constant circuit including 4.7M resistor 180 and a .33µF capacitor 182. This series circuit is coupled across the regulated +V s and -V s terminals, and the common terminal of resistor 180 and capacitor 182 is coupled to the + input terminal of a difference amplifier 184. Signal common is coupled to the - input terminal of amplifier 184. The output terminal of amplifier 184 is coupled through a series resistive voltage divider including a 10K resistor 186 and a 1K resistor 188 to -V s . The common terminal of resistors 186, 188 is coupled to the base of an NPN transistor 190, which illustratively is a type 2N3904. The emitter of transistor 190 is coupled to -V s . The muting signal is formed on the collector of transistor 190, which is coupled to the +3V s supply (Fig. 4) through a 5.1K resistor. Amplifiers 160, 176 and 184 illustratively are three fourths of the Motorola type MC34074 quad operational amplifier integrated circuit from which buffer amplifier 124 (Fig. 4) was realized.

Claims: A hysteresis-type pulse width modulator for converting an input voltage (V i ) into a pulse width modulated waveform , the width of the pulses of which is related to the input voltage (V i ) amplitude, the modulator comprising a window comparator (22), a supply voltage source having a pair of terminals (+V s , -V s ) across which a supply voltage is provided, and a hysteresis voltage source (42) having a pair of terminals across which a hysteresis voltage is provided, characterized in that the hysteresis voltage source comprises a multiplier (48), means (44) for adding the supply voltage (V s ) and input voltage (V i ) to generate a sum voltage (V s + V i ), means (46) for subtracting the input voltage (V i ) from the supply voltage (V s ) to generate a difference voltage (V s -V i ), means for coupling the input voltage (V i ) to the sum voltage generating means (44) and difference voltage generating means (46), means for coupling the supply voltage source (+V s , -V s ) to the sum voltage generating means (44) and difference voltage generating means (46), means for coupling the sum voltage generating means (44) and difference voltage generating means (46) to the multiplier (48), and means for coupling the multiplier (48) to the window comparator (22). The apparatus of claim 1 further characterized in that the hysteresis-type pulse width modulator comprises an integrator (10, 14), the window comparator (22), the hysteresis voltage source (42), a flip-flop (28), means for coupling the input voltage (V i ) to the integrator (10, 14), means for coupling the integrator (10, 14) to the window comparator (22), means for coupling the window comparator (22) to the flip-flop (28), and means for coupling the hysteresis voltage source (42) to the window comparator (22). The apparatus of claim 2 further characterized in that the window comparator (22) comprises first (16) and second (18) comparators, each having non-inverting (+) and inverting (-) terminals, the means for coupling the integrator (10, 14) to the window comparator (22) comprising means for coupling an output terminal of the integrator to a non-inverting (+) input terminal of the first comparator (16) and to an inverting (-) input terminal of the second comparator (18), the means for coupling the hysteresis voltage source (42) to the window comparator (22) comprises means for coupling a first of the pair of terminals of the hysteresis voltage source (42) to the inverting input terminal (-) of the first comparator (16) and a second of the pair of terminals of the hysteresis voltage source (42) to the non-inverting input terminal (+) of the second comparator (18).

Inventors: MCCORKLE DAVID P, MCCORKLE, DAVID P.
Applicants: HARMAN INT IND, HARMAN INTERNATIONAL INDUSTRIES INCORPORATED
Application year: 1993
Main classification: H03F3
IPC codes: H03F3, H03K7, H03F1