Switched capacitor circuit

Abstract: A switched capacitor circuit includes a first capacitor (102) connected between first and second nodes (101, 103), a second capacitor (C₁) connected between the first node and an intermediate node (M), and a third capacitor (C₂) connected between the third node (M) and ground. A group of m parallel circuits are connected between the intermediate node and the second node. Each of the m parallel circuits has a fourth capacitor (C v ) and a switch (D v ) for coupling it to ground or to the second node (103) depending on a corresponding one of m bits of an N-bit gain control signal. (N - m) parallel circuits are connected between the first and second nodes, each including a fifth capacitor and a switch for charging it depending on one of (N - m) bits of the N-bit gain control signal. A first sampling switch (S₁) couples an input voltage to the first node (101) in response to the first phase of a two-phase clock signal and coupling the first node to ground in response to the second phase. A second sampling switch provides charging of a sixth capacitor (104), connected to the second node, in response to the first phase and discharges energy from it to an output terminal of the switched capacitor circuit in response to the second phase.

Description: The present invention relates generally to a switched capacitor circuit, and more particularly to a switched capacitor circuit which operates in response to a two-phase high frequency clock signal to synthesize an equivalent resistor. A prior art switched capacitor circuit as shown in Fig. 1 comprises a first sampling switch S1 of single-pole-double-throw (SPDT) type connected to an input terminal 100 for coupling it to a circuit node 101 in response to a first phase 1 of a two-phase high frequency clock signal and coupling the node 101 to ground in response to the second phase 2 of the clock signal. A second sampling switch S2 of the SPDT type is connected to a circuit node 103 for coupling it to ground in response to phase 1 and coupling it, in response to phase 2, to the inverting input of an operational amplifier 106 , which functions as the energy supply source for the switched capacitor circuit. Between the circuit nodes 101 and 103 is provided a variable sampling capacitor circuit SC1 comprising a capacitor 102 with value C s which is in shunt with a plurality of gain control switches D i and sampling capacitors C i respectively connected to switches D i , where i = 1, 2,..... 8. The least to most significant bits of an eight-bit binary signal are applied respectively to the gain control switches D 1 to D 8 for coupling the associated capacitors in shunt with the fixed capacitor 102 in response to a bit "1". The capacitance of each of the switched capacitors C i is equal 2 (i-1) x C o where C o is the capacitance unit. The circuit node 103 is further connected through a transfer capacitor 104 to a third sampling switch S3 of the SPDT type. Third sampling switch S3 is responsive to phase 1 for coupling the transfer capacitor 104 to ground for discharging it and responsive to phase 2 for coupling it to the output terminal 107 to which the output of operational amplifier 106 is connected. A feedback capacitor 105 is connected between the inverting input of operational amplifier 106 and output terminal 107 to stabilize the operational amplifier when the inverting input is disconnected from circuit node 103 . Since the gain (V out /V in ) of the switched capacitor circuit is given by the ratio of the total capacitance of the variable sampling capacitor circuit SC1 to the capacitance C t of transfer capacitor 104 , it can be adjusted to one of 256 capacitance ratios (i.e., C s /C t , (C s +C o )/C t , (C s +2C o )/C t , (C s +3C o )/C t , ........., (C s +255C o )/C t ) in response to an 8-bit gain control signal, using 255 capacitance units. From the power savings standpoint of the operational amplifier 106 it is desirable to reduce the total number of capacitance units as well as to reduce the value of the capacitance unit itself. However, the precision of the capacitance ratio tends to decrease as the value of the capacitance unit C o decreases due to the process limitations imposed by the integrated circuit technique. Since the capacitance unit value C o cannot be reduced below what is obtainable by the integrated circuit technology, it is important to reduce the total number of capacitance units. To reduce the total number of capacitance units C o to 131 units, as well as the total of the capacitances of sampling capacitors and transfer capacitor to 1/64 of Fig. 1, a variable sampling capacitor circuit SC2 of what is known as the ladder or T-type structure is shown in Fig. 2. According to this prior art, each of the switched capacitor circuits formed by gain control switches D k (where k = 1, 2, 3, ..... 6) includes a series of capacitors C k1 and C k3 and a capacitor C k2 connected across the node between capacitors C k1 and C k3 and ground. All capacitors C k1 and C k3 except for C 63 have unit capacitance value C o , while capacitor C 63 has twice the unit capacitance value, and all capacitors C k2 except for capacitor C 62 have a capacitance equal to (2 (7-k) - 2)C o and the capacitor C 62 is of the unit value C o . The values of capacitors 102 and 104 are reduced to C s /64 and C t /64, respectively. After charging the capacitors C k1 , C k2 and C k3 , the charge stored on capacitor C k3 is transferred to the transfer capacitor 104 . Since the amount of energies discharged by the gain control sampling capacitors is given by V in x C k1 x C k3 /(C k1 + C k2 + C k3 ), each of the capacitor networks connected to switches D 1 to D 6 has an equivalent capacitance C k1 x C k3 /(C k1 + C k2 + C k3 ) ranging from C o /64 to C o /2. A further prior art sampling capacitor circuit SC3 which is known as the π structure reduces the total number of capacitance units C o to 65 units as shown in Fig. 3. According to this π-structure each of the capacitor networks associated with switches D j (where j = 1 and 2) is formed by a series of unit-value capacitors C j1 , C j3 , C j5 and grounded capacitors C j2 and C j4 respectively coupled to the node between capacitors C j1 and C j3 and the node between C j3 and C j5 . The values of the grounded capacitors C 12 and C 14 are 3C o and 11C o , respectively, and those of the grounded capacitors C 22 and C 24 are C o and 9C o , respectively. The quantity of the charges transferred from the gain control sampling capacitors is given by V in x C j1 x C j3 x C j5 /{(C j1 + C j2 )(C j3 + C j4 + C j5 ) + C j3 (C j4 + C j5 )}. The equivalent capacitances of the capacitor networks with switches D 1 and D 2 are equal to C o /64 and C o /32, respectively. However, there is still a need to decrease the number of capacitance units for each of the T- and π-type of sampling capacitor networks. The document WO-A-8 902 192 discloses a switched capacitor filter of a prior art using a π configuration. It is therefore an aim of the present invention to provide a switched capacitor circuit having a smaller number of capacitance units. According to a first aspect of the present invention, there is provided a switched capacitor circuit which comprises a first capacitor connected between first and second nodes, a second capacitor connected between the first node and a third node; a third capacitor connected between the third node and a reference potential; a plurality of first parallel circuits, each of the first circuits including a respective fourth capacitor and a respective first switch means arranged to connect the respective fourth capacitor selectably (a) between the third node and the reference potential and (b) between the third node and the second node in dependence upon a respective bit of a plural-bit gain control signal; a plurality of second parallel circuits, each of the second circuits including a respective fifth capacitor and a respective second switch means arranged selectably (a) to connect and (b) to disconnect the respective fifth capacitor between the first and second nodes in dependence upon a respective further bit of the gain control signal; a third switch means arranged to connect the first node selectably (a) to an input signal of the switched capacitor circuit in response to a first phase of a two-phase high-frequency clock signal and (b) to the reference potential in response to the second phase of the clock signal; a sixth capacitor; and a fourth switch means arranged selectably (a) to connect the second node to the reference potential and to discharge the sixth capacitor in response to the first phase of the clock signal and (b) to connect the sixth capacitor between the second node and an output terminal of the switched capacitor circuit in response to the second phase of the clock signal. According to a second aspect of the present invention, there is provided a switched capacitor circuit comprising: a first capacitor connected between a first node and a second node; second and third capacitors connected in series between the first node and a third node; a fourth capacitor connected between a reference potential and a node between the second and third capacitors; a fifth capacitor connected between a reference potential and the third node; a plurality of first parallel circuits, each of the first circuits including a respective sixth capacitor and a respective first switch means arranged to connect the respective sixth capacitor selectably (a) between the third node and the reference potential and (b) between the third node and the second node in dependence upon a respective bit of a plural-bit gain control signal; a plurality of second parallel circuits, each of the second circuits including a respective seventh capacitor and a respective second switch means arranged selectably (a) to connect and (b) to disconnect the respective seventh capacitor between the first and second nodes in dependence upon means arranged to connect the first node selectably (a) to an input signal of the switched capacitor circuit in response to a first phase of a two-phase high-frequency clock signal and (b) to the reference potential in response to the second phase of the clock signal; an eighth capacitor; and a fourth switch means arranged selectably (a) to connect the second node to the reference potential and to discharge the eighth capacitor in response to the first phase of the clock signal and (b) to connect the eighth capacitor between the second node and an output terminal of the switched capacitor circuit in response to the second phase of the clock signal. Further features of the invention are characterised in the dependent claims. The present invention will be described in further detail. by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a first prior art switched capacitor circuit; Fig. 2 is a circuit diagram of a second prior art switched capacitor circuit of T-type structure; Fig. 3 is a circuit diagram of a third prior art switched capacitor circuit of π-type structure; Fig. 4 is a circuit diagram of a switched capacitor circuit according to a first embodiment of the present invention; and Fig. 5 is a circuit diagram of a switched capacitor circuit according to a second embodiment of the present invention. In order to reduce the number of unit capacitances C o of the T-type sampling capacitor circuit, a first embodiment of the present invention is shown in Fig. 4. The sampling capacitor circuit SC4 of this embodiment comprises a unit-value capacitor C 1 connected between the node 101 and a node M and a capacitor C 2 with a value of 32C o connected between node M and ground, which serves a reference potential. Between the circuit nodes M and 103 is connected a plurality of parallel circuits each including a capacitor C Vm connected in series with a single-pole-double-throw (SPDT) switch D Vm , where m = 1, 2,.... 5, and the value of each capacitor C Vm is equal to 2 (m-1) C o . The least significant bit to the fifth significant bit of an 8 bit gain control signal are applied respectively to -SPDT switches D V1 to D V5 . Each of the SPDT switches D Vm is responsive to a bit "1" for coupling the associated capacitor C Vm to the node 103 and responsive to a "0" for coupling that capacitor to ground. When switches S 1 , S 2 and S 3 are changed to position "a" in response to the phase 1 of a two-phase high frequency clock, a charging current is supplied from terminal 100 and all capacitors C Vm are charged regardless of the positions of their associated switches D Vm to develop a voltage V M at node M . More specifically, those of capacitors C Vm which are coupled to ground by the corresponding switches D Vm (to which a bit "0" is applied) allow the charging currents to find their paths to ground through such bit-0-applied switches, and the other capacitors which are coupled to node 103 by the associated switches D Vm (to which a bit "1" is applied) allow the charging currents to find their paths through switch S 2 . Therefore, the node voltage V M , which is given below, is precisely proportional to the voltage V in at input terminal 100 , regardless of the operating states of switches D V1 to D V5 : When switches S 1 , S 2 and S 3 are changed to position "b" in response to the phase 2 of the two-phase clock, those of the sampling capacitors which are coupled to node 103 are brought into a series connection by switch S 3 to the transfer capacitor 104 . The amount of energies discharged by the gain control sampling capacitors C V1 ∼ C V5 is given by: where M is the total number of capacitors C Vm which are connected to node 103 . Therefore, the equivalent capacitance ratio R is expressed by: It is seen that if each one of the capacitors C V1 ∼ C V5 is coupled exclusively to node 103 , a capacitance value C o /64, 2C o /64, 4C o /64, 8C o /64 or 16C o /64 is brought into shunt with the fixed sampling capacitor 102 . Therefore, a capacitance value ranging from a minimum of C o /64 to a maximum of 31 C o /64 with an increment of C o /64 can be provided by a combination of the least significant bit to the fifth significant bit of the 8-bit gain control signal. The sampling capacitor circuit SC4 of this invention includes the switches D 6 to D 8 and their associated capacitors in the same manner as shown in Figs. 2 and 3. Since the switches D 6 to D 8 are respectively responsive to the sixth to the most significant bits of the 8-bit gain control signal, the application of a bit "1" to switch D 6 brings a capacitance C o /2 (= 32C o /64) in shunt with the fixed sampling capacitor 102 as the next value to the maximum value of 31C o /64 which is provided if all capacitors C V1 to C V5 are coupled to node 103 . In like manner, the operation of switches D 7 and D 8 brings equivalent capacitances C o and 2C o in shunt with the fixed sampling capacitor 102 . It follows that a maximum of 256 capacitance ratios can be provided by a combination of any of switches D V1 ∼ D V5 , D 6 to D 8 using 71 unit-value capacitors, representing a reduction of 60 capacitance units in comparison with the prior art T-type sampling capacitor circuit of Fig. 2. A second embodiment of the present invention is shown in Fig. 5. This embodiment is an improvement over the prior art π-type sampling capacitor circuit of Fig. 3. The sampling capacitor circuit SC5 of this embodiment includes the same capacitor networks formed by the gain control switches D 4 to D 8 and their associated capacitors C 41 ∼ C 43 , C 51 ∼ C 53 , C 61 ∼ C 63 , C 7 and C 8 as used in the prior art of Fig. 3. The fourth significant bit to the most significant bit of an 8 bit gain control signal are applied respectively to SPDT switches D 4 to D 8 . The sampling capacitor circuit SC5 includes a series of unit-value (C o ) capacitors C 1 and C 3 between circuit nodes 101 and M ', a capacitor C 2 with value 3C o connected across the node between capacitors C 1 and C 3 and ground, and a capacitor C 4 with value 5C o connected between the node M ' and ground. Between the circuit nodes M ' and 103 is connected a plurality of parallel circuits each including a capacitor C Vm connected in series with a single-pole-double-throw (SPDT) switch D Vm , where m = 1, 2 and 3, and the value of each capacitor C Vm is equal to 2 (m-1) C o . The least significant bit to the third significant bit of the 8 bit gain control signal are applied respectively to SPDT switches D V1 to D V3 . Similar to the first embodiment, each of the SPDT switches D Vm is responsive to a bit "1" for coupling the associated capacitor C Vm to the node 103 and responsive to a "0" for coupling that capacitor to ground. When switches S 1 , S 2 and S 3 are changed to position "a" in response to the phase 1 of a two-phase high frequency clock, a charging current is supplied from terminal 100 and capacitors C V1 to C V3 are charged regardless of the positions of their associated switches to develop a voltage V' M at node M ' which is given by: When switches S 1 , S 2 and S 3 are changed to position "b" in response to phase 2, those of the sampling capacitors which are coupled to node 103 are brought into a series connection by switch S 3 to the transfer capacitor 104 . The amount of charges transferred from the gain control sampling capacitors C V1 ∼ C V3 is given by: Therefore, the equivalent capacitance ratio R is expressed by: If each one of the capacitors C V1 ∼ C V3 is coupled exclusively to node 103 , an equivalent capacitance value C o /64, 2C o /64, or 4C o /64 is brought into shunt with the fixed sampling capacitor 102 . Therefore, a capacitance value ranging from a minimum of C o /64 to a maximum of 7C o /64 can be provided by a combination of the least significant bit to the third significant bit of the 8-bit gain control signal. The capacitors associated with the switches D 4 to D 8 add an equivalent capacitance ranging from C o /8 to 2C o to the range of values provided by capacitors C V1 to C V3 . The total number of capacitance units is reduced to 36, representing a reduction of 29 units in comparison with the prior art π-type sampling capacitor circuit of Fig. 3. In summary, a preferred embodiment of switched capacitor circuit includes a first capacitor (102) connected between first and second nodes (101, 103), a second capacitor (C 1 ) connected between the first node and an intermediate node (M), and a third capacitor (C 2 ) connected between the third node (M) and ground. A group of m parallel circuits are connected between the intermediate node and the second node. Each of the m parallel circuits has a fourth capacitor (C V ) and a switch (D V ) for coupling it to ground or to the second node (103) depending on a corresponding one of m bits of an N-bit gain control signal. (N - m) parallel circuits are connected between the first and second nodes, each including a fifth capacitor and a switch for charging it depending on one of (N - m) bits of the N-bit gain control signal. A first sampling switch (S 1 ) couples an input voltage to the first node (101) in response to the first phase of a two-phase clock signal and coupling the first node to ground in response to the second phase. A second sampling switch provides charging of a sixth capacitor (104), connected to the second node, in response to the first phase and discharges energy from it to an output terminal of the switched capacitor circuit in response to the second phase. It will be understood that the present invention has been described above purely by way of example, and modifications of detail can be made within the scope of the invention as it is defined in the appended claims.

Claims: A switched capacitor circuit comprising: a first capacitor (102) connected between a first node (101) and a second node (103); a second capacitor (C 1 ) connected between the first node (101) and a third node (M); a third capacitor (C 2 ) connected between the third node (M) and a reference potential; a plurality of first parallel circuits, each of the first circuits including a respective fourth capacitor (C V1 ...C V5 ) and a respective first switch means (D V1 ...D V5 ) arranged to connect the respective fourth capacitor selectably (a) between the third node (M) and the reference potential and (b) between the third node (M) and the second node (103) in dependence upon a respective bit of a plural-bit gain control signal; a plurality of second parallel circuits, each of the second circuits including a respective fifth capacitor (C 61 ...C 63 ,C 7 ,C 8 ) and a respective second switch means (D 6 ...D 8 ) arranged selectably (a) to connect and (b) to disconnect the respective fifth capacitor between the first and second nodes (101,103) in dependence upon a respective further bit of the gain control signal; a third switch means (S 1 ) arranged to connect the first node (101) selectably (a) to an input signal of the switched capacitor circuit in response to a first phase of a two-phase high-frequency clock signal and (b) to the reference potential in response to the second phase of the clock signal; a sixth capacitor (104); and a fourth switch means (S 2 ,S 3 ) arranged selectably (a) to connect the second node (103) to the reference potential and to discharge the sixth capacitor in response to the first phase of the clock signal and (b) to connect the sixth capacitor between the second node (103) and an output terminal of the switched capacitor circuit in response to the second phase of the clock signal. A switched capacitor circuit as claimed in claim 1, wherein: the fourth capacitor of each of the first circuits has a capacitance of 2 (j-1) × C 0 , where C 0 is a unit value and j ranges from one to the total number of the first circuits; and the fifth capacitor of each of the second circuits has an equivalent capacitance value of C 0 /2 (k-2) , where k ranges from one to the total number of the second circuits. A switched capacitor circuit as claimed in claim 1 or 2, wherein the second and third capacitors have capacitances of C 0 and 2 m × C 0 , respectively, where m is the total number of the first circuits. A switched capacitor circuit comprising: a first capacitor (102) connected between a first node (101) and a second node (103); second and third capacitors (C 1 ,C 3 ) connected in series between the first node (101) and a third node (M'); a fourth capacitor (C 2 ) connected between a reference potential and a node between the second and third capacitors; a fifth capacitor (C 4 ) connected between a reference potential and the third node (M'); a plurality of first parallel circuits, each of the first circuits including a respective sixth capacitor (C V1 ...C V3 ) and a respective first switch means (D V1 ...D V3 ) arranged to connect the respective sixth capacitor selectably (a) between the third node (M') and the reference potential and (b) between the third node (M) and the second node (103) in dependence upon a respective bit of a plural-bit gain control signal; a plurality of second parallel circuits, each of the second circuits including a respective seventh capacitor (C 41 ...C 63 ,C 7 ,C 8 ) and a respective second switch means (D 4 ...D 8 ) arranged selectably (a) to connect and (b) to disconnect the respective seventh capacitor between the first and second nodes (101,103) in dependence upon a respective further bit of the gain control signal; a third switch means arranged to connect the first node (101) selectably (a) to an input signal of the switched capacitor circuit in response to a first phase of a two-phase high-frequency clock signal and (b) to the reference potential in response to the second phase of the clock signal; an eighth capacitor (104); and a fourth switch means arranged selectably (a) to connect the second node (103) to the reference potential and to discharge the eighth capacitor in response to the first phase of the clock signal and (b) to connect the eighth capacitor between the second node (103) and an output terminal of the switched capacitor circuit in response to the second phase of the clock signal. A switched capacitor circuit as claimed in claim 4, wherein: the sixth capacitor of each of the first circuits has a capacitance of 2 (j-1) × C 0 , where C 0 is a unit value and j ranges from one to the total number of the first circuits; and the seventh capacitor of each of the second circuits has an equivalent capacitance value of C 0 /2 (k-2) , where k ranges from one to the total number of the second circuits. A switched capacitor circuit as claimed in claim 4 or 5, wherein the second, third, fourth and fifth capacitors have capacitances of C 0 , C 0 , 3 × C 0 and 5 × C 0 , respectively.

Inventors: TATSUMI SATOSHI, TATSUMI, SATOSHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1993
Main classification: H03H19
IPC codes: H03H19