Voltage booster circuit for generating both positive and negative boosted voltages

Abstract: A circuit for generating positive and negative boosted voltages, comprising first (El-pos) and second (El-neg) voltage booster circuits, respectively for positive and negative voltages, which have output terminals interconnected at a common node (N). It comprises two tristate logic gate circuits for coupling said voltage booster circuits to a positive supply voltage generator (Vdd,GND) and additional tristate logic gate circuits for driving the phases of charge pump circuits incorporated to the booster circuits. This voltage generating circuit may be integrated in single-well CMOS technology.

Description: This invention relates to monolithically integratable voltage booster circuits, and particularly to a circuit effective to generate both positive and negative boosted voltages for driving circuit nodes in circuits adapted for monolithic integration in CMOS technology. A specific application of the invention is related to devices which include non-volatile storage cells. With conventional non-volatile memories, a known cell write technique is that of applying, to the cell drain terminal, a voltage having a moderately high value (e.g., 6.5 Volts), while a higher voltage value (e.g., 10.5 Volts) is applied to its gate. To erase a cell, on the other hand, a high voltage (e.g., 10.5 Volts) is applied to the source terminal of the cell, while its gate terminal is held at ground potential. Such erasing is usually carried out simultaneously on all the cells of a device or all the cells in a memory block ("erasing by sectors"). All the high-voltage references needed for proper operation of a memory are conveniently generated, moreover, within the device from the standard external supply voltage (5 Volts). It should not be overlooked, however, that during the erasing phase, a current is flowed between the cell sources and the substrate; while this is quite small (equal to 1 µA) for an individual cell, the overall current would be fairly high in the instance of a large storage capacity device, making it difficult to provide a voltage booster within the integrated circuit which can drive the source electrodes during that operation phase. Furthermore, the application of a high reverse bias between the cell sources and the substrate may introduce reliability problems in that voltages close to the junction breakdown voltage may be reached and hot holes generated which become trapped within the gate oxide. It is for the above-outlined reasons that an alternative memory erasing technique has been developed whereby the source electrodes of the cells are held at a relatively low positive voltage (e.g., 5 Volts), while the gate electrodes are applied a negative voltage of adequate value (approximately -10.5 Volts). The circuit which generates this voltage is not required to supply a large current, so that it can be provided internally of the integrated storage circuit. Thus, in more recently developed storage cell devices --such as "flash" devices -- implemented with field-effect transistors, the gate terminal of each storage cell is applied a high positive or negative voltage at the programming stage, depending respectively on whether the involved phase is a write or a erase one, relative to a reference potential. In circuit solutions currently in use to implement that technique, the positive or negative boosted voltages for driving the storage cells during the write and erase phases are applied to the gate terminals through suitable selection transistors with switch functions. However, driving the storage cells through their gate terminals poses a major problem from the wide variation in value of the voltages and their polarities. A variation of 21 Volts would, at the above-mentioned voltage values, make the use of "high-voltage" transistors and a number of circuit arrangements, effective to prevent the undesired triggering of parasitic diodes in the integrated circuit, unavoidable. Also, selection transistors cannot be used where a single-well integration process in CMOS technology is employed, due to problems from charge injection. A circuit for generating boosted voltages of different polarities as indicated in the preamble of claim 1 is disclosed in the US Patent No. 5,237,209. The underlying technical problem of this invention is to provide a circuit which can generate both positive and negative boosted voltages to drive storage cells through their gate terminals, and affords a broader choice of integration techniques for a device incorporating it as well as improved reliability. This problem is solved by a positive and negative boosted voltage circuit as indicated hereinabove and defined in the characterizing parts of the appended claim 1 to this specification. The features and advantages of a negative and positive boosted voltage generating circuit according to the invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a block diagram of a positive and negative boosted voltage generating circuit according to the invention; and Figure 2 shows a circuit diagram for a negative voltage booster circuit of the charge pump type, which can be incorporated to a voltage generating circuit according to the invention. The block diagram for a positive and negative boosted voltage generating circuit according to the invention, shown in Figure 1, comprises first Tr1, second Tr2, third Tr3, fourth Tr4, fifth Tr5 and sixth Tr6 switching circuits, each having an input terminal IN, an output terminal OUT, and an enable terminal EN for connecting the input to the output when enabled. In a preferred embodiment of a voltage generating circuit according to the invention, such switching circuits are implemented as tristate logic gate circuits, in forms well known from the pertinent technical literature. The block diagram of Figure 1 further includes first and second voltage booster circuits, El-pos and El-neg, respectively for positive and negative voltages, each having first and second command terminals 1 and 2, a supply terminal, respectively Vdd and GND, for said first and second voltage booster circuits, and an output terminal OUT. The voltage booster circuits mentioned above are preferably embodied by charge pump circuits easily implemented in CMOS technology, and the two command terminals allow the charge phases to be controlled. According to the invention, the output terminals of the two voltage booster circuits are directly connected together at a circuit node which is driven thereby through positive and negative voltages having higher absolute values than the positive supply voltage. In the power supply, which is exclusive with non-volatile storage cell CMOS technology devices, the gate terminals of the storage cells are coupled to that circuit node N. The values of the generated voltages are typically +10.5 Volts and -10.5 Volts, for a supply voltage of +5 Volts. In the preferred embodiment of a circuit for generating positive and negative voltages, according to the invention, the circuit includes a third voltage booster circuit, identified by a block Bod-sw in Figure 1, which allows the "body" substrate of the transistors used for the charge pump of the negative voltage booster circuit El-neg to be suitably biased. The voltage booster circuit Bod-sw also has first and second command terminals, Φ1 and Φ2, for the phases of the charge pump circuit therein, and an output terminal OUT connected to a BODY terminal for biasing the bodies of the transistors in the charge pump circuit of the negative voltage booster circuit El-neg. A preferred practical example of this negative voltage booster circuit is depicted in Figure 2. The voltage booster circuit Bod-sw generates positive voltages which are controlled at predetermined levels by means of a control terminal CRLT. The positive voltage booster circuit also has a charge reset command terminal which is preferably coupled to the control terminal CRLT in parallel therewith. The input terminals of the switching circuits Tr1 and Tr4 are respectively connected to a ground GND and a supply ground Vdd. It should be noted that for the two switching circuits, the inverting tristate circuit embodiment form has been adopted in this case, it being understood that this form may also be used for the others. The input terminals of the switching circuits Tr2 and Tr6 are connected together at a first common input node IN1, to which the first command terminal of the booster circuit Bod-sw is also connected. The input terminals of the switching circuits Tr3 and Tr5 are connected together at a second common input node IN2, to which the second command terminal of the circuit Bod-sw is also connected. The enable terminals of the switching circuits Tr1, Tr2 and Tr5 are connected together at a first common enable node EN1. The enable terminals of the switching circuits Tr3, Tr4 and Tr6, the control terminal of the voltage booster circuit Bod-sw, and the charge reset command terminal of the positive voltage booster circuit El-pos are connected together at a second enable circuit node EN2. The common node links specified hereinabove are useful for signal synchronizations but no strict requirement, and the several terminals of the blocks could be disconnected from one another, or be coupled together by other circuit arrangements, in accordance with design techniques well known to the skilled persons in the art. The output terminals of the switching circuits Tr1, Tr2 and Tr5 are respectively connected to the supply terminal and the first and second command terminals of the positive voltage booster circuit E1-pos. The output terminals of the switching circuits Tr6, Tr3 and Tr4 are respectively connected, on the other hand, to the first and the second command terminals, and the supply terminal, of the negative voltage booster circuit El-neg. As previously mentioned, at the programming stage, the gate terminal of each storage cell should either be applied a positive voltage or a negative voltage, depending on the programming, writing or erasing requirements. Each voltage booster circuit should then bring its output to the target voltage value or allow it to attain the voltage value impressed by other driver circuits, such as the other booster to which it is connected. In figure 1 the memory celles load is represented by a capacitor. The voltage booster circuit El-pos, for example, should impress on its output a voltage of 10.5 Volts when requested, and allow the output to attain -10.5 Volts when the circuit node N is to be controlled by the voltage booster circuit El-neg. In accordance with this invention, a novel circuit topology is proposed which can provide this driver function. The fundamental aspect of this topology is that the outputs of both voltage booster circuits, i.e. both the positive voltage generating circuit and the negative voltage generating circuit, are held at all times connected to the load, which load is represented by the gate capacitance of the cells to be driven. Whenever a booster circuit is required to output no boosted voltage, it is disabled internally such that its output is allowed to float, thereby leaving the other booster circuit free to take over in the common output node control. In the specific instance of voltage booster circuits which are operated in the charge pump mode, as one voltage booster circuit is deactuated, its charge pump is disconnected from the supply (Vdd for El-pos, GND for El-neg) and the charge pump phase generator (1,2). In this way, the output of the deactuated booster will be allowed to float, so that it can follow the voltage impressed by the actuated drive circuitry (specifically, the other voltage booster circuit) without disturbing its normal operation. Of course, the actuation of one circuit causes its charge pump to be both connected to its respective supply and the charge driving phase generator. The topology proposed herein requires appropriate arrangements for it to be effective. The following considerations apply to booster circuits as integrated in CMOS technology with a p-doped substrate. It will be appreciated that the same considerations would also apply, with appropriate adaptations, to boosters integrated in CMOS technology with an n-doped substrate. The booster circuits are connected to or disconnected from a suitable supply and the driving phases through tristate circuits. These may be embodied conventionally, and each of the tristate circuits functions as an inverter when enabled (EN=1), and exhibits a high output impedance when deactuated (EN=0). The voltage booster circuit El-pos includes, according to the invention, a p-channel output transistor whose gate is connected to ground. This transistor would be turned automatically on, with the booster circuit El-pos operative and the booster circuit El-neg disabled (in fact, the voltages at both the source and drain terminals are positive), and off with El-neg enabled and El-pos disabled (the voltage at the source terminal is null and that at the drain terminal is negative). By providing this transistor, the positive voltage generated by the booster circuit can be transferred to the output N (which is then coupled to the gate terminals of the storage cells) upon El-pos being enabled, and the negative voltage impressed on the node N by El-neg can be passed to the booster circuit El-pos upon the latter being disabled. The last-mentioned aspect is vital to preventing the source electrodes of the n-channel transistors connected to the output of the booster El-pos from being forward biased with respect to the substrate, which is p-doped and connected to ground; otherwise, the charge from the booster El-neg would be drained to the substrate, so that the node N cannot be pulled to the negative voltage required and problems from carrier injection into the substrate may be experienced. The fact that the booster circuit El-pos is disabled whilst the booster circuit El-neg is enabled (the supply and the drive inputs of the charge pumps are disconnected) prevents a voltage in excess of 20 Volts from being applied between the drain and the source of the output transistor such as would cause reliability problems, and avoids power waste. As for the negative voltage booster El-neg, of which Figure 2 shows an embodiment form, it should be emphasized that the source areas of the p-channel transistors comprising it are forward biased with respect to the body regions of the transistors upon the booster circuit being disabled and the voltage at the node N brought to positive values. (This would, in a similar manner to that described above for the booster circuit El-pos, cause the charge supplied by the booster circuit El-pos to be drained off.) To this aim, the topology proposed herein provides under these conditions for the body electrode of the p-channel transistors of the booster El-pos to be connected to a voltage which is the equal of or higher than the voltage generated by the booster El-pos. This voltage may be obtained at the device through an appropriate booster circuit Bod-sw, as shown in Figure 1. It is obviously convenient that upon actuation of the booster circuit El-neg, the body electrode of the p-channel transistors be not connected to an excessively high voltage, so that an excessive body effect on the threshold of the transistors can be avoided and the effectiveness of the charge pump circuits maintained; this measure has the added advantage that the application of an excessively high voltage across the junction between the source and the body of transistors M7 and M14 of the negative booster can be prevented. The booster Bod-sw can generate a voltage having an adequate value to drive said body electrodes to either states (booster circuit El-neg enabled and disabled). The booster circuit Bod-sw will generate a voltage of about 14.5 Volts with the booster circuit El-pos enabled, and generate a voltage of about 4.5 Volts with the latter disabled and the booster circuit El-neg enabled. This can be accomplished by means of conventional circuit arrangements. With the booster circuit El-pos enabled and El-neg deactuated, both the drain of the first charge pump transistor of the negative booster circuit (M1, M8; thereby denying an escape path to the charge from the positive booster) and the electrodes of the phase charge pump (thereby avoiding unnecessary increase of the capacitive load as seen from the positive booster circuit) are allowed to float. The net result of all this is that the booster circuit El-pos supplies 10.5 Volts, the booster circuit El-neg is deactuated through the tristate circuits such that its output will float, and the bodies of its transistors are brought to 14.5 Volts; on the other hand, when the negative booster supplies -10.5 Volts, the bodies of its transistors are brought to 4.5 Volts and the positive booster is deactuated (through the tristate blocks) such that its output will be floating. The circuit solutions proposed herein relate to the instance of booster circuits which operate on the charge pump principle. However, the proposed topology (continued connection of both the output of the positive voltage booster circuit and the output of the negative voltage booster circuit to the load to be driven, with "internal" deactuation of either booster, such that its output will be floating while the other booster is operative) is also applicable to boosters which are operated on different techniques. It is understood that many modifications, adaptations, integrations and substitutions of elements may be made unto the embodiment described hereinabove by way of illustration and not of limitation without departing from the scope of the appended claims.

Claims: A circuit for generating a first and a second voltage with a first and a second polarity relative to a reference potential, which first and second voltages are boosted in absolute value over said reference potential, first (El-pos) and second (El-neg) voltage booster circuits respectively for generating said first and second voltages, each having command terminals (Φ1,Φ2), at least a first supply terminal (Vdd,GND) and at least a first output terminal (OUT), said first voltage booster circuit being actuated to supply the first voltage to its output when the second voltage booster circuit is deactuated, and said second voltage booster circuit being actuated to supply the second voltage to its output when the first voltage booster circuit is deactuated characterized in that said first output terminals of the first (El-pos) and the second (El-neg) voltage booster circuits are connected together at a common output node (N), and in further comprising first (Tr1), second (Tr2), third (Tr3) and fourth (Tr4) switching circuits, each having an input terminal (IN), an output terminal (OUT) and an enable terminal (EN) for connecting the input to the output when enabled; the input terminals of the first (Tr1) and the fourth (Tr4) switching circuits being respectively connected to a first terminal (GND) and a second terminal (Vdd) of a supply voltage generator, the output terminals (OUT) of the first (Tr1) and the second (Tr2) switching circuits being respectively connected to the first supply terminal (Vdd) and a first command terminal (Φ1) of the first voltage booster circuit (El-pos), the output terminals (OUT) of the third (Tr3) and the fourth (Tr4) switching circuits being respectively connected to a first command terminal (Φ2) and the first supply terminal (GND) of the second voltage booster circuits (El-neg), the enable terminals of said first and second switching circuits being connected to a first common enable node (EN1), the enable terminals of said third and fourth switching circuits being connected to a second common enable node (EN2), said input terminals of said second and third switching circuits being connected to different first and second input nodes (IN1, IN2). A voltage generating circuit according to Claim 1, characterized in that it further comprises fifth (Tr5) and sixth (Tr6) switching circuits, each having at least an input terminal (IN), output terminal (OUT) and enable terminal (EN), the output terminals (OUT) of said fifth and sixth switching circuits being respectively connected to a second command terminal (Φ2) of the first voltage booster circuit (El-pos) and to a second command terminal (Φ1) of the second voltage booster circuit (El-neg), each of said first and second voltage booster circuits comprising a charge pump circuit driven through said first and second command terminals (Φ1, Φ2) of the same voltage booster circuit. A voltage generating circuit according to Claims 1 and 2, characterized in that at least one of the switching circuits is a tristate logic gate circuit. A voltage generating circuit according to any of Claims 1, 2 and 3, characterized in that the first voltage booster circuit (El-pos) has an electric charge reset command terminal (Vcr1). A voltage generating circuit according to any of Claims 1, 2, 3 and 4, characterized in that it comprises a third voltage booster circuit (Bod-sw), for voltages of the first polarity type which can be set at predetermined levels, being provided with at least a first command terminal (Φ1), at least a first control terminal (CTRL), and at least a first output terminal (OUT), said first output terminal being connected to at least a first bias terminal (BODY) of the second voltage booster circuit (El-neg). A voltage generating circuit according to Claim 5, characterized in that the input terminals of the second and the sixth switching circuits (Tr2,Tr6) are connected together at said first input node (IN1) to which the first command terminal (Φ1) of the third voltage booster circuit (Bod-sw) is also connected. A voltage generating circuit according to any of Claims 5 and 6, characterized in that the input terminals of the third and the fifth switching circuits (Tr3,Tr5) are connected together at said second input node (IN2). A voltage generating circuit according to Claim 7, characterized in that the third voltage booster circuit (Bod-sw) has a second command terminal (Φ2) connected to the second input node (IN2) and comprises a charge pump circuit driven through the first (Φ1) and the second (Φ2) command terminals of the respective booster circuit. A voltage generating circuit according to any of Claims 5, 6, 7 and 8, characterized in that the enable terminals (EN) of the first (Tr1), the second (Tr2) and the fifth (Tr5) switching circuits are connected together at said first common enable node (EN1). A voltage generating circuit according to any of Claims 5, 6, 7, 8 and 9, characterized in that the enable terminals (EN) of the third (Tr3), the fourth (Tr4) and sixth (Tr6) switching circuits, the first control terminal (CRTL) of the third voltage booster circuit (Bod-sw) and the charge reset command terminal (Vclr) of the first voltage booster circuit (El-pos) are all connected together at said second common enable node (EN2). A voltage generating circuit according to any of the preceding claims, when monolithically integrated, characterized in that the first voltage booster (El-pos) comprises a field-effect final transistor having an output terminal connected to the common output node (N) and a gate terminal connected to the first terminal of the supply voltage generator (GND). A voltage generating circuit according to any of the preceding claims, when monolithically integrated in CMOS technology, characterized in that the second voltage booster circuit (El-neg) comprises field-effect transistors having body bias terminals connected to the output terminal (OUT) of the third voltage booster circuit (Bod-sw).

Inventors: CALLIGARO CRISTIANO, GASTALDI ROBERTO, MALCOVATI PIERO, TORELLI GUIDO, CALLIGARO, CRISTIANO, GASTALDI, ROBERTO, MALCOVATI, PIERO, TORELLI, GUIDO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11C5
IPC codes: H01L27, G11C17, G11C16, H02M3, G11C5, H01L21, H03K19