Image processing apparatus

Abstract: This application is to improve the data processing efficiency in a system including plural image processing apparatus and a network connecting these apparatus. Reduced image data in the disk 11 of the work station WS4 are transferred through the LAN 6 to the work station WS1. The work station WS1 edits the transferred reduced image data and transfers the content of editing alone through the LAN 6 to the work station WS4, which regenerates the original image from the transferred content of editing, the reduced image data and the encoded data, and prints the original image in edited state. The application involves the compression of image data with the JBIG standard.

Description: The present invention relates to an image processing system including at least an image processing apparatus in which JBIG (joint bi-level image group) method is applicable. In a system in which plural image processing apparatus, including the above-mentioned one, are mutually connected through a network, the original image data or the edited data are transmitted through said network. However, in such system in which plural image processing apparatus are mutually connected through a network, by the transmission of the original image data of an extremely large amount of information through said network, the total data processing amount in the entire system becomes extremely large, thereby deteriorating the processing efficiency of each image processing apparatus, also increasing the memory capacity required therefor, and increasing the traffic within the network. Journal of Electronic Imaging, vol. 1, no. 1, January 1992, pages 5-21 S.J. Urban "Review of Standards for Electronic Imaging for Facsimile Systems", discusses a number of coding methods for encoding image data to be transmitted by facsimile. In particular, this document has a discussion of the JBIG encoding method. This bi-level coding technique consists of repeatedly reducing the resolution of a bi-level image, thereby creating a series of images having one half the resolution of the previous image. The lowest resolution image is transmitted without distortion by binary arithmetic coding. The next level image is then transmitted using the picture elements of the previous image and previously transmitted casual picture elements of the later image as predictors in an attempt to predict the next picture element to be transmitted. If prediction is possible, the predicted picture element is not transmitted. This progressive build up is repeated until the highest level image has been transmitted. Other coding methods are also discussed in Signal Processing of HDTV, II, Proceedings of the third international workshop on HDTV 1 September 1989, Turin, Italy pages 431-442 H.YASUDA "Progress in Multimedia Coding Standard". A method and apparatus for editing images is disclosed in EP-A-0392753. A number of original images are hierarchically encoded by an encoder and stored on a database. When two images are to be synthesised lower resolution encoded data of the images are read and decoded by a decoder. These images are displayed on a display unit. An operator can then edit the displayed images with the editing procedure being stored in a memory. When the editing process has been completed the original images are read from the database and edited in accordance with the stored editing procedure. The edited results are then hierarchically encoded and stored in the database. In consideration of the foregoing, the present invention aims to provide an image processing system which alleviates the above-mentioned drawbacks. In accordance with one aspect of the present invention there is provided an image processing apparatus for connection to a network said apparatus comprising: data storage means for storing image data received from an external apparatus via the network; editing means for effecting an editing operation on said image data and for generating information in the form of edited image contents or process content information representing said image data editing operation; and storage means for storing said information representing the image data editing operation; characterised by: transfer means for transferring only said information representing the image data editing operation stored in said storage means to the external apparatus via said network. A second aspect of the invention provides an image processing apparatus for connection to a network, the apparatus comprising: storage means for storing image data in coded form; transfer means for transferring a part of the coded image data to an external apparatus via the network; storage means for storing data representing an image data editing operation received on said part of the coded image data effected by said external apparatus and received from said external apparatus via the network said data being in the form of edited image contents or process content information; means for decoding the stored coded image data to provide decoded image data; and means for applying the data relating to the image data editing operation to the decoded image data to provide edited image data. In accordance with a further aspect of the present invention there is provided an image processing system comprising a plurality of such image processing apparatus each connected to a network, wherein transfer means is arranged for transferring the information representing an image data editing operation stored in said storage means to other information processing apparatus of said plurality of information processing apparatus via said network. In accordance with yet another aspect of the present invention there is provided an image processing method to be performed on an information image apparatus connected to an external apparatus via a network, comprising the steps of: storing image data received from the external apparatus via the network; effecting an editing operation on said image data; generating information representing said image data editing operation in the form of edited image contents or process content information; storing said information representing the image data editing operation; and transferring said stored information to said external apparatus via said network. Fig. 1 is a block diagram of an embodiment 1 of the present invention; Fig. 2 is a view showing areas of a main memory 2 shown in Fig. 1; Fig. 3 is a chart showing the principle of the compression or expansion of the JBIG method; Fig. 4 is a flow chart showing an example of the control program to be stored in a program area PMEM shown in Fig. 2; Fig. 5 is a view showing an example of the original image; Fig. 6 is a view showing an example of the prepared icon; Fig. 7 is a flow chart showing the sequence for displaying image data generated in the course of the JBIG method; Fig. 8 is a view showing low resolution data and differential code data, generated by the hierarchical encoding of the JBIG process; Fig. 9 is a flow chart showing the sequence of displaying image data generated in the course of the JBIG process. Fig. 10 is a flow chart showing a conventional example corresponding to Fig. 9; Fig. 11 is a view of the structure of a main memory; Fig. 12 is a flow chart for control sequence for a scrolling display; Fig. 13 is a flow chart of the sequence for extending an icon on the clipboard and pasting it on another display area; Figs. 14 to 16 are views showing specific examples of the sequence shown in Fig. 13; Fig. 17 is a flow chart showing a conventional example corresponding to Fig. 13; Fig. 18 is a view showing a state in which display data of 100 dpi are stored in the main memory; Fig. 19 is a view showing a state in which display data of 25 dpi are stored in the main memory; Fig. 20 is a block diagram showing the principal circuit configuration of an embodiment 5 of the present invention; Fig. 21 is a schematic plan view of the image display state in high-speed page advancing in the embodiment 5 of the present invention; Fig. 22 is a plan view showing the image display state in an ordinary display mode for displaying an expanded image; Fig. 23 is a flow chart showing the control sequence of the embodiment 5 of the present invention; Fig. 24 is a view showing the concept of an example of the interpolation in the embodiment 5 of the present invention; Fig. 25 is a view showing the concept of another example of the interpolation in the embodiment 5 of the present invention; Fig. 26 is a flow chart showing the control sequence of an embodiment 6 of the present invention; Figs. 27 and 28 are plan views showing examples of display at the start of clipping area instruction for the image data in the embodiment 6 of the present invention; Fig. 29 is a plan view showing an example of display in the course of clipping process for image data in the embodiment 6 of the present invention; Fig. 30 is a plan view showing an example of display at the end stage of clipping process for image data in the embodiment 6 of the present invention; Fig. 31 is a plan view showing an example of display after the clipping process for image data in the embodiment 6 of the present invention; Fig. 32 is a flow chart showing the control sequence of a modification of the embodiment 6 of the present invention; Fig. 33 is a memory map chart showing an example of the display image buffer to be employed in an embodiment 7 of the present invention; Fig. 34 is a flow chart showing the control sequence of an embodiment 7 of the present invention; Fig. 35 is a schematic view showing an example of the size of reduced image data processed in the embodiment 7 of the present invention; Fig. 36 is a schematic view of a striped structure of image processed in a variation of the embodiment 7 of the present invention; Fig. 37 is a flow chart of the control sequence of a variation of the embodiment 7 of the present invention; Fig. 38 is a block diagram of another example of the compression/expansion circuit; Fig. 39 is a flow chart of an operation for regulating the number of compressions; Fig. 40 is another flow chart of the operation for regulating the number of compressions; Fig. 41 is a view showing the mode of compression for individual stripe; Fig. 42 is a flow chart for a clipping operation; Fig. 43 is a view showing the encoding mode of a stripe alone required for the clipping; Fig. 44 is a view showing stored data relating to the clipped image data in the clipboard; Fig. 45 is a flow chart of the pasting of the clipped image data; and Fig. 46 is a block diagram of an image processing system. DESCRIPTION OF THE PREFERRED EMBODIMENTS Now the present invention will be clarified in detail by preferred embodiments thereof shown in the attached drawings. Embodiment 1 Fig. 1 illustrates an embodiment 1 of the present invention, wherein following units are connected to a system bus 19. A central processing unit (CPU) 1 controls the functions of the entire apparatus, and also effects image editing operation according to a system program stored in a memory 2. A main memory 2 stores the system program to be executed by the CPU 1, and also contains an image memory for storing image data to be subjected to the image editing, and a work memory for storing various data related to the image processing. An input/output interface (I/O) 3 effects data transfer with external equipment. A video random access memory (RAM) 4 stores image data of an image frame to be displayed on a CRT (display unit) 5. The image data stored in the video RAM 4 are read by the CRT 5 and visually displayed. The image data stored in the video RAM 4 have a resolution of 100 dpi (dot/inch). A LAN (local area network) interface 7 effects data transfer with other image processing apparatus connected to the LAN. A compression/expansion circuit 8 stepwise compresses the image data of 400 dpi, under the instruction of the CPU, thus generating compressed encoded image data of 12.5 dpi. It also expands the compressed image data of 12.5 dpi, under the instruction of the CPU 1, to image data of 400 dpi. Said compression/expansion circuit 8 effects the compression or expansion in the JBIG method. A direct memory access controller (DMAC) 15 is connected to a disk interface 9 and a scanner/printer interface 12 and effects reading/writing of the image data of input/output units (scanner 14, printer 13) and memory media (floppy disk 10, rigid disk 11) from or to a memory area, instructed by the CPU 1, in the main memory 2. A key interface 16 transfers, to the CPU 1, the information entered from a keyboard 17 or a coordinate input device 18 called mouse. Fig. 2 illustrates areas of the main memory 2 shown in Fig. 1. There are provided an image area IMEM for storing image data from the scanner 14; a program area PMEM for storing a program to be executed; and a work area WMEM for storing work data. In the following explained is the compression/expansion process of the JBIG method, to be executed by the compression/expansion circuit 8 shown in Fig. 1. The details of said JBIG method are described in the Journal of Image Electron Academy, Vol. 20, No. 1 (1990), pp. 41 - 49. This method will be briefly explained in the following. In case of compressing image data of 4 x 4 pixels as shown in Fig. 3, the pixel data A1 - A16 of 4 x 4 pixels for example of 400 dpi are compressed to pixel data B1 - B4 of 200 dpi, and the differences of the compressed pixel data B1 - B4 and the original pixel data A1 - A16 are encoded. The compressed pixel data are considered as new pixel data A1 - A16 for compression and are subjected to compression and encoding. The compression is conducted in this manner to the image data of minimum resolution of about 12.5 dpi, which are used for communication or storage, together with the encoded data. In the data expansion, the image data of minimum resolution (12.5 dpi) and the corresponding encoded data are utilized for preparing the image data of an upper rank (25 dpi). Subsequently image data of higher resolutions are prepared in succession, up to the original image data of 400 dpi. In the JBIG method, compressed data of a pixel, for example B4 in Fig. 3, is determined by entering the high resolution pixel data of A6 - A8, A10 - A12 and A14 - A16 surrounded by a thick line and the already compressed pixel data B1 - B3 into a weighting equation. Also the data employed for encoding are taken from the data of the reference pixels, but the positions and number of said reference pixels are made variable according to the contents of such reference around the target pixel to be encoded. Fig. 4 is a flow chart showing an example of the control program stored in the program area PMEM shown in Fig. 2. In a step S1, an image, for example of a ship, is read by the scanner 14 of 400 dpi, and the obtained image information of 400 dpi is stored in the image area IMEM of the main memory 2. Said image information is converted to a lower resolution, by the compression/expansion circuit 8 according to the JBIG method, and the obtained image information of 100 dpi is stored in a buffer memory of the image area IMEM. Then a step S2 releases the image information of 100 dpi from the buffer memory to the system bus, and a step S3 stores said information in the VRAM 4. As shown in Fig. 5, in a window 20 of the image frame 21 of the CRT 5, a ship image 22 of 100 dpi is displayed. Then, in a step S3-1, an image clipping is instructed from the keyboard 17. It is assumed that the clipping of the entire read image of ship is instructed. A step S3-2 copies the image data (400 dpi), instructed for clipping, on the image area IMEM of the main memory 2. Then a step S4 compresses the clipped image data, prepared in the buffer of the image memory IMEM, by the compression/expansion circuit 8 according to the JBIG method, thereby obtaining a low resolution image of 12.5 dpi. Then a step S5 stores the image data of 12.5 dpi and the encoded data in the rigid disk 11, and stores the image data of 12.5 dpi in another buffer of the main memory 2. A step S6 registers the image data stored in the buffer as an icon, then stores said image data in the VRAM 4 through the system bus, and displays a ship image of 12.5 dpi, reduced to a size of (1/16) x (1/16) of the original image, on a clipboard window on the image frame 21. Fig. 6 illustrates the icon displayed on the clipboard window. Embodiment 2 Fig. 7 is a flow chart of an embodiment 2 of the present invention, indicating the process for image display with a resolution of 100 dpi on the CRT 6. A step S101 reads the image data of 400 dpi by the scanner 14, and stores the read image data of 400 dpi in the image memory IMEM of the main memory 2 (cf. Fig. 11). Then for hierarchical encoding by the JBIG method, a step S102 effects compressions of two steps in the JBIG method, thereby obtaining data C + C1 + C2, wherein C indicates the data of lower resolution (100 dpi) obtained by stepwise reduction of resolution in the JBIG method as shown in Fig. 8, and C1 and C2 indicate the encoded difference data. A next step S103 transfers said data C (100 dpi), stored in IMEM of the main memory, to the VRAM 4, and displays said data on the CRT. A next step S104 discriminates whether the hierarchical encoded data obtained in the JBIG method are to be registered as a file, and, if affirmative, a step S105 effects compressions of three steps to prepare data C3 + C4 + C5 + F (cf. Fig. 8). Then a step S106 stores the data C1 + C2 + C3 + C4 + C5 + F in the disk, and a step S107 effects the window display of data F as an icon as in the foregoing embodiment (in practice there is executed a process for pasting said icon on the clipboard). As explained in the foregoing, the present embodiment can transfer the image of 100 dpi, obtained in the stepwise encoding, to the VRAM for visual display. Fig. 9 shows a variation of this embodiment, in which the image data stored in the rigid disk 11 or the floppy disk 10 (namely low resolution data F of 12.5 dpi and encoded data C1 - C5: cf. Fig. 8) are read to the main memory 2 and are displayed on the CRT 5. At first a step S110 selects the data to be displayed. More specifically, one of the displayed icons is selected by the mouse. Then a step S111 displays an image processing sheet window on the CRT. Then a step S112 discriminates whether an undisplayed image is present, and, if affirmative, a step S113 acquires a display image buffer area on the image memory IMEM of the main memory 2. A next step S114 converts the data, read from the rigid disk or the floppy disk, to 100 dpi by the expansion circuit, and writes the expanded data in the display image buffer. A next step S115 transfers the image data of 100 dpi from the display image buffer to the VRAM, thereby displaying an image on the image processing sheet window. If the step S112 identifies that the undisplayed image is absent, the sequence proceeds to a step S116 for displaying other text data or vector data on the image processing sheet window. As explained above, the present embodiment can directly store the data of 100 dpi in the display image buffer, utilizing the feature of the JBIG method of increasing the resolution in succession from the image data of lowest resolution (12.5 dpi), without the conventional procedure of once storing the image data of 400 dpi in the main memory 2 and converting said data to 100 dpi. Fig. 10 shows, as reference, the conventional technology corresponding to the embodiment shown in Fig. 9, and the comparison of Figs. 10 and 9 will clarify the feature of the present embodiment. The sequence shown in Fig. 10 is as follows. At first a step S120 selects the data to be displayed, and a next step S121 displays an image processing sheet window on the CRT. If a step S122 identifies the presence of an undisplayed image, a step S123 discriminates whether a real image buffer (for 400 dpi) has been acquired on the main memory. If such buffer area has been acquired, a step S124 erases said real image buffer. Then a next step S125 acquires a real image buffer and a display image buffer area on the image memory IMEM of the main memory. Then a step S126 writes the image data (400 dpi) from the rigid disk or floppy disk, into the real image buffer. A step S127 prepares a display image (100 dpi) in the display image buffer, based on the image data (400 dpi) stored in the real image buffer. A next step S128 transfers the image data (100 dpi) from the display image buffer to the VRAM, thereby displaying an image in the image processing sheet window. On the other hand, if the step S122 identifies the absence of the undisplayed image, a step S129 displays other text data or vector data on the image processing sheet window. In contrast to the conventional technology shown in Fig. 10, the present embodiment utilizes the image data of 100 dpi, obtained in the course of expansion by the JBIG method, for display. Consequently, also in case of scroll display, there can be dispensed with the process of converting the data of 400 dpi to 100 dpi, according to a procedure shown in Fig. 12. Referring to Fig. 12, a step S130 instructs the scrolling display. A next step S131 discriminates whether the scrolling area contains an image, and, if affirmative, a step S132 transfers the display image (100 dpi), expanded by the JBIG method, to the VRAM. Then a step S133 displays other text data or vector data in the scrolling area. Embodiment 3 An embodiment 3, to be explained in the following, provides a procedure for expanded display of an identification mark displayed in a part of the CRT (namely an icon pasted on the clipboard). Fig. 13 is a flow chart showing the control sequence of said embodiment 3, and Figs. 14 to 16 show the examples of display in a process of selecting an icon on the clipboard (said icon being displayed in reduced size with 12.5 dpi, as explained before) and fitting said icon on a desired edited position. The flow chart shown in Fig. 13 will be explained in the following, with reference to Figs. 14 to 16. At first a step S135 selects image data to be pasted. For example, a ship image (12.5 dpi) is selected from plural icons on the clipboard, as shown in Fig. 14. Then a step S136 designates the position of pasting on the image processing sheet window (cf. Fig. 15). A next step S137 acquires a pasting image buffer area in the image memory IMEM of the main memory 2. A next step S138 increases the resolution to 100 dpi by the compression/expansion circuit 8, based on the data (data of lowest resolution and encoded difference data) stored in the rigid disk, and writes said image data of 100 dpi in the pasted display image buffer. A last step S139 transfer the image data of 100 dpi from said buffer to the VRAM, for displaying a pasted image on the image processing sheet window (cf. Fig. 16). As explained in the foregoing, the present embodiment can directly display the data of 100 dpi obtained in the course of expansion of the icon of 12.5 dpi on the clipboard, and can therefore dispense with the process of converting the data of 400 dpi into data of 100 dpi for display. This feature will be more clearly understood from the comparison with a conventional technology shown in Fig. 17. In the conventional technology shown in Fig. 17, at first a step S145 selects the image data to be pasted, then a step S146 designates the location of pasting on the image processing sheet window, and a step S147 acquires a real pasted image buffer area and a displayed image buffer area in the image memory IMEM of the main memory. Then a step S148 transfer the image data to be pasted, from the rigid disk, to said real pasted image buffer area. A next step S149 prepares, from the image data transferred to said real pasted image buffer, a display image in the display image buffer area. A last step S150 transfers the image data from said display image buffer to the VRAM, thereby displaying a pasted image on the image processing sheet window. Embodiment 4 An embodiment 4 of the present invention attains effective utilization of the image memory area IMEM of the main memory 2, thereby enabling to store a larger number of display images. Fig. 18 shows a general occupied state of the image buffer in the main memory. The image memory area IMEM is storing display images for displaying two images A, B on the CRT. Such state of the IMEM is obtained in the following manner. At first a first image A, read by the scanner 14, is stored in the IMEM as a real image of 400 dpi, then said image is converted to a display image (100 dpi) for display on the CRT, and the converted data is stored in the IMEM, as the display image (100 dpi) for the image A. Then a second image B is read by the scanner 14, and the real image data of 400 dpi is overlaid in the area which stores the real image (400 dpi) of the image A, whereby the real image (400 dpi) of the image B is stored in the IMEM. Then a display image, obtained by conversion to 100 dpi, is stored for the image B. However, the memory area may become deficient if a larger number of display image data (100 dpi) is to be stored. Consequently, in the present embodiment, images of lower resolution (for example 25 dpi) are stored for display, instead of the resolution of 100 dpi for display. Thus the present embodiment enables to store all the necessary image data in the IMEM, utilizing the formation of images of lower resolution by the hierarchical encoding of the JBIG method. Fig. 19 shows a state in which the image memory area IMEM of the main memory 2 stores the display image data (25 dpi) of three images A, B and C. Said display image data may be of a resolution of 50 dpi, or even of 12.5 dpi. In displaying these images on the CRT, there may be arbitrarily selected, according to the equipped window system whether to display an image of 100 dpi by expansion, or to display plural reduced images of 25 dpi at the same time. The foregoing description is based on a principle of storing display image data prepared from the real image data read by the scanner, but it is also possible to expand the low resolution image data of 12.5 dpi and the encoded difference data, already stored in the disk, and to use thus expanded data for display. The procedure of forming display image data of 25 dpi and storing said data in the area IMEM will be obvious from other embodiments, so that the corresponding flow chart is omitted. Embodiment 5 In the following an embodiment 5 of the present invention will be explained, with reference to Figs. 20 to 25. Said embodiment 5 enables image display in the high-speed page flipping, which is difficult to achieve in the conventional technology, thereby facilitating the work. Fig. 20 shows a principal circuit structure for realizing the present embodiment; Fig. 21 shows the display state of the present embodiment, in the high-speed page flipping mode; Fig. 22 shows the image display state of the expanded image; Fig. 23 shows the operation means of the present embodiment; and Figs. 24 and 25 show specific examples of interpolation of the present embodiment. In Fig. 20, an image interpolation circuit 224 for expanding the size of reduced image serves to interpolate the reduced image data of 25 dpi as shown in Fig. 24 or 25, thereby expanding the size of the image, and to send the interpolated data to the CRT 5 through the VRAM 4. It is assumed that image data of plural images, obtained for example from the scanner 14, are already converted into reduced image data of 25 dpi and encoded data, by the image compression of the JBIG method shown in Fig. 8, and are already stored in the rigid disk 11 or the floppy disk 10. The function of the present embodiment will be explained in detail, with reference to a flow chart shown in Fig. 23. When high-speed image display (high-speed page flipping) is instructed for example from the keyboard 17 shown in Fig. 1 (step S201), the data to be displayed is selected (step S202), and an image processing sheet window 220 is displayed, as shown in Fig. 21, on the display image frame 221 of the CRT 5 (step S203). Then a display image buffer area of 25 dpi is acquired in the image memory area IMEM of the main memory 2 (step S205), and the image data to be displayed are transferred from the rigid disk 11 or the floppy disk 10 to said display image buffer (step S206). Thus the above-mentioned reduced image data of 25 dpi, separate from the encoded data, are stored in said display image buffer in the image memory area IMEM. Then the reduced image data are transferred, from said display image buffer, through the image interpolation circuit 224 to the VRAM 4, for image display on the image processing sheet window 220 on the CRT 5 (step S207). In this operation, said image interpolation circuit 224 expands the reduced image data to the original image size, by a relatively simple interpolation such as zero value interpolation or same value interpolation as shown in Figs. 24 or 25, whereby images as shown in Fig. 21 are displayed in succession at a high speed, on the image processing sheet window 220. After the image data are all transferred from the display image buffer to the VRAM 4, the sequence returns to the step S204, and the above-mentioned steps S205 to S207 are repeated if an undisplayed image exists for example in the rigid disk 11. If such undisplayed image is absent, a step S208 effects necessary post-process and the sequence returns to the main program. If the high-speed image display is not instructed, there is executed normal image display by expanding the reduced image data of 12.5 dpi and the encoded data to the original image by the compression/expansion circuit 8 and displaying the expanded original image on the CRT 5 (step S209). In this case the displayed image is as clear as the original image, as shown in Fig. 22. This embodiment enables high-speed image display in simple and rapid manner, and with a limited image memory, since the image expansion process is not involved in the high-speed image display. However, the image quality is inferior, as schematically illustrated in Fig. 21, to the ordinary display obtained by the expansion process, as shown in Fig. 22, but such image quality is not a problem in practice, because, in the high-speed page flipping mode, the user only needs to identify the displayed image. In the foregoing description, the reduced image data are assumed to be of 25 dpi, but there may be employed those of 12.5 dpi. Embodiment 6 Figs. 26 to 32 show an embodiment 6, which, in the clipping of image data, displays the stepwise reduced image data in succession and finally erases the display, thereby clearly informing the user of the proceeding of the clipping process. Fig. 26 shows the control sequence of the present embodiment, while Figs. 27 to 31 show examples of display, and Fig. 32 shows the control sequence of a variation of the present embodiment. Now the function of the present embodiment will be explained in detail, with reference to a flow chart in Fig. 26. It is assumed that an image shown in Fig. 27 is displayed on the image processing sheet window 220 of the display frame 221 of the CRT 5. When image data clipping is instructed from the keyboard 17 in this state, a clipboard window 225 is displayed on the display frame 221 (step S211). Then the user designates the clipping area for example with a mouse, as indicated by a pointer P shown in Figs. 27 and 28, and, when the clipping area designation is completed as shown in Fig. 28 (step S213), the CPU 1 acquires a clipping image data buffer area in the image memory area IMEM of the main memory 2 (step S214). Then the image data of 400 dpi of thus designated clipping area are transferred, from the real image buffer in the image memory IMEM, to the clipping image data buffer (step S215). Subsequently the data in said clipping image data buffer are compressed and encoded by the compression/expansion circuit 8 according to the JBIG method shown in Fig. 8, thereby initially obtaining the reduced image data (200 dpi) and encoded data of a first stage (step S216). Said reduced image data are written by overlay into the clipping image data buffer, and are also transferred to the VRAM 4 for display on the CRT 5. Thus image data with a resolution of 1/2 are displayed on the image processing sheet window 220 (step S217). The above-explained steps S216 and S217 are repeated until the completion of the stepwise encoding. With such compression encoding, the image resolution varies in the steps of 400 dpi, 200 dpi, 100 dpi, 50 dpi, 25 dpi and 12.5 dpi, and the image size is also reduced to 1/4 with a reduction of 1/2 in the resolution. Consequently the image for clipping (a ship image in this case) displayed on the image processing sheet window 220 is reduced in size, as shown in Figs. 28, 29 and 30, corresponding to the process stage of the compression encoding, so that the user can clearly understand the progress of the clipping process. When the encoding is completed (step S218), the final reduced data are stored in the clipboard, then the image on the image processing sheet window 220 is erased as shown in Fig. 31, and the clipped reduced image of 12.5 dpi is pasted as an icon, on the clipboard window 225 through the VRAM 4 (step S219). Thereafter the control sequence returns to the main flow. Thus the user can immediately know the completion of the clipping procedure. In the conventional technology, the image to be clipped remains displayed in its original size for several seconds to about twenty seconds until the completion of the clipping procedure, and said image is suddenly erased upon said completion. Consequently the user is unable to comprehend the progress of the clipping procedure and finds difficulty in maintaining the work. On the other hand, the present embodiment displays the reduced images in succession in smaller sizes, and the above-mentioned inconvenience can therefore be resolved. Fig. 32 shows the control sequence of a variation of the embodiment 6, and the difference of said variation lies in a fact that, in a step S220 next to the step S216, an image of a resolution of 1/2 is displayed on the image processing sheet window 220 through the image interpolation circuit 224 as shown in Fig. 20. Consequently, in said variation, the displayed image, instead of being reduced in size as shown in Figs. 29 and 30, remains same in size as shown in Fig. 21 but becomes stepwise thinner and vanishes at the completion of encoding (step S219). It will be apparent that this variation provides the same effect as in the foregoing embodiment. Embodiment 7 Figs. 33 to 37 show an embodiment 7 of the present invention. In this embodiment, even when the capacity a of the residual memory area RM of the display image buffer acquired in the image memory IMEM of the main memory 2 becomes smaller than an image frame capacity T as shown in Fig. 33, the display of at least another image is rendered possible, thereby achieving effective utilization of the memory and improvement in the work efficiency. At first reference is made to a flow chart shown in Fig. 34, for explaining an example of the function of the present embodiment. When an instruction for the image data display is given from the keyboard 17 (step S221), there is discriminated whether the display image buffer of an image frame can be acquired in the display image buffer area of the image memory IMEM (step S222), by comparing the capacity a of the above-mentioned residual memory area RM with a capacity T required for an image frame. If a ≧ T, indicating that said display image buffer can be acquired (step S223), there is executed the ordinary image display process of storing the display image data of a new image frame of 100 dpi in said display image buffer and displaying said data on the CRT 5 through the VRAM 4 (step S229), and then the sequence returns to the main routine. In case of a < T, indicating that the display image buffer for an image frame cannot be acquired, the sequence proceeds to a step S224 for obtaining an image with a resolution of 1/2. More specifically, the reduced image data of 12.5 dpi and the encoded data of the JBIG method are supplied from the rigid disk 11 or the floppy disk 10 to the compression/expansion circuit 8 and are subjected to the JBIG expansion to obtain reduced image data of 50 dpi (step S224). Then there is discriminated whether a display image buffer for an image frame with a resolution of 1/2 can be acquired. More specifically, as shown in Fig. 35, the capacity b required for the reduced image data of 50 dpi is compared with the capacity a of the residual area RM, and said acquisition is identified possible or impossible respectively if b ≦ a or b > a. If said acquisition is identified impossible (step S226), the above-mentioned steps S224 and S225 are repeated until said acquisition becomes possible. More specifically, in a second cycle, reduced image data of 25 dpi are prepared in the compression/expansion circuit 8, then the capacity c required for said reduced image data (cf. Fig. 35) is compared with the capacity a of the residual memory area RM, and said acquisition is identified possible or impossible respectively if c ≦ a or c > a. For example if c ≦ a, indicating that a display image buffer for an image frame of 25 dpi can be acquired in the image memory IMEM, the sequence proceeds from the step S226 to S227 for transferring, to said display image buffer, the image data of a resolution of 1/n, decoded to the resolution level of the buffer (for example reduced image data of 25 dpi). Subsequently said image data of resolution of 1/n are read from the display image buffer, enlarged to the original image size through the image interpolation circuit 224 shown in Fig. 20, and transferred to the VRAM 4, thereby displaying the image of the resolution of 1/n on the image processing sheet window 220 (cf. Fig. 22) on the CRT 5 (step S228). The interpolation in this state is executed as shown in Fig. 24 or 25, whereby the display is made with somewhat deteriorated image quality, as shown in Fig. 21. Subsequently the sequence returns to the main program. Such display is considered practically acceptable, since some deterioration in the image quality is not a problem for merely confirming the content of image. Particularly the present embodiment provides an advantage of constantly enabling to see the entire image. Figs. 36 and 37 show a variation of the embodiment 7. In order to facilitate the sequence process in consideration of the scanner 14 etc., the image data of an image frame are usually divided into m stripes at maximum, satisfying a condition d x m ≦ T, and the JBIG compression is executed for each stripe, and the reduced image data of 12.5 dpi and the encoded data are stored in the rigid disk 11 or the floppy disk 10. The present embodiment is to display image data of an image frame, utilizing the combination of m stripes at maximum according to the capacity a of the residual memory area RM, without reducing the resolution from 100 dpi. This embodiment will be explained in the following, with reference to a flow chart shown in Fig. 37. Steps S231 - S233 and S239 will not be explained as they are similar to the steps S221 - S223 and S229 in Fig. 34. At first, if a step S233 identifies that a display image buffer for an image frame cannot be acquired, a step S234 obtains image data of 100 dpi, which are less by one stripe than in the preceding cycle, by the compression/expansion circuit 8, based on the data from the rigid disk 11 etc. Then a step S235 discriminates whether a display image buffer, for said data reduced by one stripe, can be acquired on the image memory area IMEM. More specifically, for an i-th cycle, (m - i) x d is compared with the aforementioned capacity a of the residual memory area RM, and said acquisition is identified possible or impossible, respectively if (m - i) x d ≦ a or (m - i) x d > a, wherein i = 1, 2,..., (m - 1). If the acquisition is identified impossible (step S236), the above-mentioned steps S234 and S235 are repeated until said acquisition becomes possible. When the step S236 subsequently identifies that the acquisition is possible, the composite image data are stored in the display image buffer by an amount corresponding to the acquired stripes (step S237), and said image data in the display image buffer are displayed in the original stripe position, on the image processing sheet window 220 (cf. Fig. 22) on the CRT 5 (step S238). Subsequently the sequence returns to the main routine. The order of selection of stripes in the step S234 can be variously considered according to the nature of the image. For example, if important image information is concentrated in the upper part of the image frame (for example a control chart), the stripes may be discarded from the lower part of the image frame. In case the important image information is concentrated in the center of the image frame (for example a design chart), the stripes may be discarded alternately from the upper and lower parts so as to leave the central stripes to the last. Consequently the image displayed on the CRT 5 in the step S238 shows the important image portions by a combination of stripes. The present embodiment provides an advantage of displaying the image with a resolution of 100 dpi which is same as the resolution of the CRT 5, and the present embodiment does not require the image interpolation circuit 224. The above-explained embodiment repeats the steps S224 and S225 (or steps S234 and S235) until the display image buffer is acquired, but it is also possible to determine, in one operation, the resolution of 1/n (or number i of stripes) through the comparison of the capacity a of the residual memory area RM with a predetermined capacity e i for each resolution (or comparison of the capacity a with n x i). Also the step S228 in Fig. 34 displays the image through the image interpolation circuit 224, but it is also possible to automatically decide the display according to the resolution, for example to display the image data of 100 dpi expanded by the compression/expansion circuit 8 in case of a very low resolution, and to effect the display without image interpolation in case the resolution is relatively high. As explained in the foregoing, the present embodiment enables image display even in case of capacity deficiency of the display image buffer area, thereby improving the operating efficiency. Embodiment 8 In the hierarchical encoding of image data by the JBIG method, following process enables further efficient utilization of memory and further improvement in the process efficiency. The original image data (400 dpi) stored in the main memory 2 (Fig. 38) are divided into horizontally oblong plural stripes (areas) arranged in the vertical direction, and said original image data are hierarchically encoded by the compression/expansion circuit 8 for each stripe in the main memory 2. Based on the data in a stage in the course of said encoding, a comparator 301 effects a comparison: (1) original image data size/n ≧ compressed image size (compressed image data size of said stage + encoded data to said stage); or (2) (compressed data size/compressed data size in preceding stage) ≦ X, (for example n = 2 - 1000, X = 0.5 - 0.99), and the encoding process for the stripe is terminated at this stage when the above-mentioned condition is satisfied. This is based on a fact that the additional hierarchical encoding does not provide significant (effective) reduction of the compressed data and that there can be economized the memory capacity consumed in the additional encoding. Flow charts shown in Figs. 39 and 40 show the process in the compression/expansion circuit 8, respectively corresponding to the above-mentioned comparisons (1) and (2). A step S301 receives, from the CPU 1, an instruction for starting the encoding for the original image data of 400 dpi in the main memory 2. Then a step S302 reads the image data of a first stripe from the main memory 2, and a step S303 effects the encoding of a first stage on thus read image data. Then a step S304A (Fig. 39) or S304B (Fig. 40) discriminates the signal indicating the result of process (1) or (2) by the comparator 301, and, if NO (condition (1) or (2) being not satisfied), the sequence returns to the step S303 for effecting the encoding of a next stage on said stripe. In case of YES (condition (1) or (2) being satisfied), the encoding for said stripe is terminated. Then the sequence proceeds to a step S305 for discriminating whether the hierarchical encoding has been completed for all the stripes of the original image data in the main memory 2, and the steps S302 to S304A/B are repeated until such encoding is completed. Fig. 41 shows the different process stages for the stripes, attained through the above-explained procedure. The process is completed at the 4th stage for the stripe 1, 2nd stage for the stripe 2, and 3rd stage for the stripe 3. Embodiment 9 In the image clipping of the image displayed on the CRT 5, and in the pasting of a clipped image onto other suitable text data, the following process under the control of the CPU 1 enables further improved utilization of the memory. The image data (100 dpi), displayed on the CRT 5 and stored in the image memory IMEM of the main memory 2, are divided into plural stripes, as in the embodiment 8. Then, when a clipping procedure to the clipboard is initiated as shown in Fig. 42, a step S311 awaits the designation of the clipping area utilizing the image displayed on the CRT 5, and a step S312 identifies a stripe to which the image A of the designated clipping area belongs (stripe 2 in Fig. 43). Based on the result of said identification, a step S313 effects stepwise encoding on the image data (100 dpi) of the corresponding stripe in the image memory IMEM for example to a resolution of 12.5 dpi. Then a step S314 discriminates whether the encoding has been completed for all the stripes to which the image A belongs (in case of Fig. 43, the image A belongs only to the stripe 2, but it may belong to plural stripes), and the step S313 is repeated until the encoding is completed. Upon completion, a step S315 writes, with respect to all the encoded stripe data to which the image A belongs, a header (consisting of the position of the encoded stripe in the image data on the image memory IMEM, position (X, Y) of the image A in the stripe, and image data size (width W and height H), and the encoded data (containing image data of 12.5 dpi of corresponding stripe) in a predetermined area of the clipboard of the image memory IMEM in the main memory 2. Such operating mode reduces the write-in data capacity into the clipboard, thereby achieving efficient utilization of the memory. In the following there will be explained the pasting of thus clipped image data A onto the image frame currently displayed on the CRT 5. When the clipboard is displayed on the CRT 5, the previously clipped image A is displayed as an icon, which is designated as an image to be pasted. Then an image to which said image A is to be pasted is displayed on the CRT 5. Then a step S316 in Fig. 45 awaits the designation of the pasting position utilizing the image displayed on the CRT 5, and a step S317 acquires a pasting data buffer in the image memory IMEM of the main memory 2. Then a step S318 decodes (100 dpi) the data of all the stripes to which the image A belongs, stored in the predetermined area of the clipboard of the image memory IMEM in the main memory 2, and stores the decoded data in the image memory IMEM, then a step S319 extracts the actually pasted image A from the image data of 100 dpi of the decoded stripes in the image memory IMEM based on the header information in the predetermined area of said clipboard and stores said image A in the buffer acquired in the step S317, and a step S320 displays the image A, extracted from said buffer, in the pasting position on the CRT 5, according to the designating information in the step S316. This procedure utilizes only the data of the necessary stripes, thereby achieving efficient utilization of the memory. Embodiment 10 In an image processing system, which utilizes the apparatus as shown in Fig. 1 as a work station functioning as a server and in which plural work stations are connected by a network, the following operation enables efficient operation. A system shown in Fig. 46 includes a work station WS4 functioning as a server of the structure shown in Fig. 1; work stations WS1, WS3 lacking the printer and the rigid disk; and a work station WS2 provided with a rigid disk llA. Each of the work stations WS1 - WS3 is equipped with the CRT 5, VRAM 4, CPU 1, main memory 2, I/O 3, LAN interface 7, compression/expansion circuit 8, key interface 16, keyboard 17 and mouse 19. A number 6 indicates the local area network (LAN). In the above-explained configuration, it is assumed that the disk 11 of the work station WS4 stores the image data C + C1 + C2 (Fig. 8). In case of effecting an editing operation in the work station WS1 by displaying an image corresponding to A (cf. Fig. 8) on the CRT, it is only required to transfer the data C alone from the work station WS4 to the VRAM (or main memory) of the work station WS1 through the LAN 6. Through this operation, the work station WS1 can display the image C on the CRT, and can effect editing operation by the mouse or the keyboard. The edited content H is stored in the main memory of the work station WS1. For printing thus edited image C', the edited content H alone is transferred from the main memory of WS1 to that of WS4 through the LAN 6, then the image data A are decoded in the WS4 from the data C + C1 + C2 stored in the disk 11, then the edited data H are added thereto, and the edited image data A' are printed in the printer 13. Also in case of storing said image data A', said data A' are stepwise encoded to obtain C' + C1' (corresponding to C1) + C2' (corresponding to C2), which are then stored in the disk 11. As explained in the foregoing, it is thus rendered possible to minimize the total data processing amount in the entire system, and the memory capacity required in each work station can also be minimized. The processing can be made more efficient, and the traffic in the LAN can also be maintained low.

Claims: An image processing apparatus (WS1) for connection to a network (6) said apparatus comprising: data storage means (2, WMEM) for storing image data received from an external apparatus (WS4) via the network; editing means (1, 17, 18) for effecting an editing operation on said image data and for generating information in the form of edited image contents or process content information representing said image data editing operation; and storage means (2) for storing said information representing the image data editing operation; characterised by: transfer means (1, 7) for transferring only said information representing the image data editing operation stored in said storage means (2) to the external apparatus (WS2-4) via said network (6). An image processing apparatus (WS4) for connection to a network (6), the apparatus comprising: storage means (11) for storing image data (A) in coded form (C + C1 + C2); transfer means (1, 7) for transferring a part (C) of the coded image data (C + C1 + C2) to an external apparatus (WS1) via the network; storage means (2) for storing data (H) representing an image data editing operation on said part of the coded image data effected by said external apparatus and received from the external apparatus (WS1) via the network (6), said data being in the form of edited image contents or process content information means (8) for decoding the stored coded image data (C + C1 + C2) to provide decoded image data (A); and means (1) for applying the data (H) relating to the image data editing operation to the decoded image data (A) to provide edited image data (A'). An image processing apparatus (WS4) according to claim 2, further comprising means (13) for printing the edited image data (A'). An image processing apparatus according to claim 2 or 3, further comprising means (8) for encoding the edited image data (A') and means (11) for storing the encoded edited image data (C' + C1' + C2'). An image processing apparatus in accordance with claim 1 or 2, wherein said apparatus comprises a display means. An image processing system comprising a first image processing apparatus (WS1) according to claim 1 and a second image processing apparatus (WS4) according to claim 2 each connected to a network (6), wherein said transfer means (1, 7) of said first image processing apparatus (WS1) is arranged to transfer the information (H) representing an image data editing operation stored in its storage means (2) to the second image processing apparatus (WS4) via said network (6). An image processing method to be performed on an image processing apparatus (WS1) connected to an external apparatus (WS2-4) via a network (6), comprising the steps of: storing image data (C) received from the external apparatus (WS4) via the network; effecting an editing operation on said image data; generating information (H) representing said image data editing operation in the form of edited image contents or process content information; storing said information (H) representing the image data editing operation; and transferring said stored information (H) to said external apparatus (WS2-4) via said network (6). An image processing method in accordance with claim 7 further comprising the step of: storing image data (C) to be edited by an image data editing operation, and wherein said stored image data (C) is transferred with said stored information (H) representing said image data editing operation to said external apparatus (WS2-4). An image processing method in accordance with claim 7 or claim 8 further comprising the step of: using said external apparatus (WS2-4) to perform an image editing operation in accordance with said transferred information (H) representing the image data editing operation.

Inventors: ISHIZAWA YASUHISA, NONOSHITA HIROSHI, ISHIZAWA, YASUHISA, NONOSHITA, HIROSHI, Ishizawa, Yasuhisa, c/o Canon Kabushiki Kaisha, Nonoshita, Hiroshi, c/o Canon Kabushiki Kaisha
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1993
Main classification: H04N1
IPC codes: H04N1, G06T9