Abnormal packet processing system

Abstract: An abnormal packet processing system minimizes processing of an abnormal packet during communication between a plurality of processing units by a receiving processor. In a data processing system including a plurality of processing units (1-1, 1-2, ..., 1-n) connected through an interconnection (2), a transmitting processor (1-1) includes means (3) for detecting abnormality of a data packet during transmission to a receiving processor (1-2) and means (4, 7) for adding abnormality report data to the data packet being transmitted and sending it to the receiving processor (1-2), or for inhibiting transmission of the abnormal packet.

Description: This invention relates to an abnormal packet processing system. More particularly, it is applicable to an abnormal packet processing system in communications between processing units in a parallel computer system including I/O apparatuses and central processing units. When any abnormality occurs during packet communication between processing units of a data processing system employing an abnormal packet processing system according to the prior art, an instruction processing portion in a transmitting processor reports this abnormality to a receiving processor by allowing a packet, different from the packet under transmission, to contain control data and abnormality data and transmitting it to the receiving processor. According to the prior art in the system described above, the abnormal data packet has already been received at the point of time when the different packet containing the abnormality report data arrives at the receiving processor, so there is the possibility that processing has been done on the abnormal packet. In other words, unnecessary processing is carried out on the abnormal packet. WO-A-84 04862 discloses an abnormal packet processing system according to the preamble of claim 1, which can inhibit transfer of a data packet from the transmitting processor when an abnormality is detected. According to the invention, in a data processing system including a plurality of processing units connected through an interconnection, there is provided an abnormal packet processing system wherein a transmitting processor includes an abnormality detection means for detecting an abnormality when such abnormality occurs during the transmission of a data packet from a transmitting processor to a receiving processor, and characterised by an abnormality report data addition means for adding abnormality report data indicating the occurrence of such abnormality and the classification of such abnormality to the data packet, during transmission to the receiving processor. It will therefore be seen that the present invention can be implemented in such a way as to provide an abnormal packet processing system which eliminates the necessity for processing an abnormal packet by a receiving processor when an abnormality occurs in a packet during transmission. For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, wherein: Fig. 1 is a block diagram useful for explaining the principle of the present invention; Fig. 2 is a block diagram useful for explaining another principle useful for understanding the present invention; Fig. 3 is a block diagram showing the construction of a data processing system applied to either Fig. 1 or Fig. 2; Fig. 4 is a block diagram showing one construction of a processing unit; Fig. 5 is a block diagram showing the construction of a transfer processing unit of the unit of Fig. 4; Fig. 6 is a flowchart useful for explaining the operation of the transfer processing unit shown in Fig. 5; Fig. 7 is a diagram showing the construction of a packet according to an embodiment of the present invention; Fig. 8 is a diagram showing the content displayed on a display according to an embodiment of the present invention; Fig. 9 is a block diagram showing the construction of a transfer processing unit using the principle of Fig. 2, not in accordance with the present invention; and Fig. 10 is a flowchart useful for explaining the operation of the transfer processing unit shown in Fig. 9. Prior to a detailed description of a preferred embodiment of the present invention, this embodiment will be generally explained. Fig. 1 is a block diagram showing basic features of an embodiment of the present invention. Fig. 1 shows a data processor equipped with a plurality of processing units 1-1, 1-2, ..., 1-n, which are connected to one another through an interconnection 2. A transmitting processor 1-1 is equipped with an abnormality detection means 3, for detecting any abnormality when such abnormality occurs in a data packet which is being transmitted from the transmitting processor 1-1 to a receiving processor 1-2. The processor 1-1 also comprises an abnormality report data addition means 4, for adding abnormality report data to indicate the occurrence of this abnormality and its classification to the data packet during transmission and for transmitting the data packet to the receiving processor 1-2. The receiving processor 1-2 is equipped with an abnormality indication means 5 for holding the received abnormality report data. Fig. 2 is a block diagram showing basic features of another arrangement, useful for understanding the invention. A plurality of processing units 1-1, 1-2, ..., 1-n are shown connected through an interconnection 2 in Fig. 2 in the same way as in Fig. 1. According to this arrangement, the transmitting processor 1-1 is equipped with an abnormality detection means 3 for detecting any abnormality when such abnormality occurs in a data packet during transmission from the transmitting processor 1-1 to the receiving processor 1-2, and with a packet transmission inhibition means 6 for inhibiting the transmission of the data packet from the transmitting processor 1-1 when such abnormality is detected. The transmitting processor 1-1 is equipped with an indication means 7 for indicating that transmission of the data packet is inhibited when the transmission of the data packet is inhibited. According to the embodiment of the invention shown in Fig. 1, the abnormality report data is added to the data packet during transmission and then the data packet is transmitted to the receiving processor 1-2. The receiving processor 1-2 displays the abnormality report data thus received. Accordingly, the report of the abnormal data arrives earlier at the reception processing unit and hence, abnormality processing becomes easier. According to the arrangement shown in Fig. 2, the transmission of the data packet from the transmitting processor 1-1 is inhibited when any abnormality occurs in the data packet during transmission from the transmitting processor 1-1 to the receiving processor 1-2. Accordingly, the processing of abnormal data becomes unnecessary in the receiving processor. Fig. 3 is a block diagram showing a data processing system to which the abnormal packet processing system according to either principle of Fig. 1 or Fig. 2 is applied. In the drawing, a plurality of processing units 3-1 to 3-n are shown connected through a network 32. These processing units are, for example, vector operation circuits or scalar operations circuits of a parallel computer system, and constitute a multiprocessor. The network 32 may be either a switching network having a switching function, or a bus. A packet is transmitted from one of the processing units to others. When any abnormality occurs in this packet during transmission, this abnormality is reported to the processing unit on the receiving side, by the means of the embodiment of the present invention which will be described next. Fig. 4 is a block diagram showing one construction of the processing unit. In the drawing, the processing unit 3-1 includes a main storage 40 for storing instructions (that is, a program) and data, an instruction processing unit 41 for retrieving the instructions from the main storage 40 and executing them, a transfer processing unit 42 to transfer a packet between the main storage 40 and a network 32, and an abnormality detection circuit 43 for detecting the occurrence of any abnormality when such abnormality occurs in any of the main storage 40, the instruction processing unit 41 and the transfer processing unit 42 during transmission of the packet. Fig. 5 is a block diagram showing the construction of the transfer processing unit 42 of Figure 4. In the drawing, the transfer processing unit 42 includes a main storage access control unit 50 for controlling access to the main storage 40, a data buffer 51 for storing the data read out from the main storage 40 and accumulating the data to be stored in the main storage 40 under the control of the main storage access control unit 50, a network transfer control unit 52, a network interface 53 and an abnormality indication device 54 for indicating that an abnormality exists in the received packet. Fig. 6 is a flowchart useful for explaining the operation of the transfer processing unit 42 shown in Fig. 5 and in accordance with the embodiment. Fig. 7 is a diagram showing the construction of the packet according to the embodiment. As shown in the drawing, the packet comprises address data for designating a receiving processor, other control data and abnormality data which is added in accordance with this embodiment. The control data includes memory access attributes in the transmitting processor, data relating to designation of the processing in the receiving processor, and so forth. Fig. 8 shows the content of the abnormality data held by the indication device inside the processing unit on the receiving side or the transmitting side according to the embodiment. As shown in the drawing, the indication device indicates that the transmission data is designated incorrectly, indicates that a multiple-bit error occurred in the transmission data, or indicates that hardware errors occurred inside the transfer processing unit. The operation of this example of the embodiment will now be explained with reference to Figs. 3 to 6. The main storage access control unit 50 accesses the main storage 40 under instruction from the network transfer control unit 52, and controls the transfer of data between the main storage 40 and the data buffer 51. The data buffer 51 temporarily stores the data when data transfer is carried out between the main storage 40 and the network 32, and also temporarily stores the data when a data write request is made by the data transfer unit 42 and by the main storage access control unit 50 to the main storage 40. The network transfer control unit 52 inside the transfer processing unit 42 is activated by the control data in the transfer packet generated by the instruction processing unit 41, and issues a main storage access request to the main storage access control unit 50 so as to read out the control data from the transfer packet. The data is read out from the main storage 40 in response to this access request, and is stored in the buffer 51 (Step 61 in Fig. 6). The network transfer control unit 52 controls the network interface 53, and sends the control data from the data buffer 51 to the network 32 (Step 62 in Fig. 6). When any abnormality occurs in the main storage 40, the instruction processing unit 41 or the transfer processing unit 42 during the transfer of the control data from the transfer processing unit 42 (in the case of Y at Step 63 in Fig. 6), the abnormality detection circuit 43 detects this abnormality and reports it to the network transfer control unit 52. Upon receiving this report, the transmission abnormality data addition device 55 inside the network control unit 52 adds the abnormality data to the data packet during the transmission (Step 64 in Fig. 6). When no abnormality is detected, the data from the data buffer 51 is delivered to the network 32 (Step 65 in Fig. 6). Upon receiving the packet having the abnormality data added thereto, the processing unit on the receiving side allows the abnormality indication device 54 to hold details of the abnormality. The abnormality indication device 54 is a register to which reference can be made from the instruction processing unit. This abnormality can also be held in the abnormality indication device 54 on the transmitting side. Fig. 9 is a block diagram showing the construction 30 of a transfer processing unit using the principle of Fig. 2. The same reference numerals will be used in this drawing to represent the same circuit elements as in Fig. 5 and a suffix a will be added to the reference numeral to represent the circuit element which is analogous to the one shown in Fig. 5. In Fig. 9, delivery of the normal data packet is carried out in the same way as in Fig. 5. When any abnormality occurs in the main storage 40, the instruction processing unit 41 or the transfer processing unit 42a during the transfer of the data packet, the abnormality detection circuit 43 detects this abnormality and reports it to the network transfer control unit 52a. Upon receiving this report, the abnormality packet transfer inhibition device 55a inside the network transfer control unit 52a inhibits the transmission of the abnormal data packet. The abnormality indication device 54 inside the processing unit on the transmission side indicates the inhibition of the transmission of the packet as well as the content of this abnormality. Fig. 10 is a flowchart useful for explaining the operation of the transfer processing unit 42a shown in Fig. 9. In this drawing, the control data of the packet is first read out from the main storage 40 at Step 101 in the same way as in Fig. 6, and is stored in the data buffer 51. When the abnormality report from the abnormality detection circuit 43 arrives during the storage of this control data (in the case of Y at Step 102), the abnormality data is sent to the abnormality indication device 54 at Step 103, the control data in the data buffer 51 is made invalid at Step 104, and the packet transfer is inhibited at Step 105. When the abnormality report does not exist at Step 102, the control data is read out from the data buffer 51 at Step 106 and is sent to the network 32, and the data is then read out from the data buffer 51 at Step 107 and is sent to the network 32. After the data representing that no abnormality exists is added to the packet at Step 108, the packet transfer is completed. Examples of abnormality in Figs. 5 and 9 are multiple-bit errors in the main storage 40 and hardware errors inside the transfer processing unit. Although the foregoing embodiment illustrates the case where the transmission abnormality data addition device is constituted by the hardware, it may also be accomplished by software. As can be clearly understood from the explanation given above, the present invention adds the abnormality report data to the data packet when any abnormality exists on the transmission side during the data transfer between the processing units of the data processing system. For this reason, transfer of another packet for notifying this abnormality to the reception processing unit becomes unnecessary, and the abnormality report arrives in the receiving processing unit, so that the abnormality processing becomes more simple.

Claims: An abnormal packet processing system in a data processing system including a plurality of processing units (1-1, 1-2, ..., 1-n) connected through an interconnection (2), wherein a transmitting processor (1-1) comprises abnormality detection means (3), for detecting any abnormality when such abnormality occurs in a data packet which is under transmission from said transmitting processor (1-1) to a receiving processor (1-2); characterised by an abnormality report data addition means (4) for adding to said data packet abnormality report data containing the occurrence of said abnormality and the classification of said abnormality. An abnormal packet processing system according to claim 1, wherein said receiving processor (1-2) is equipped with abnormality indication means (5) for displaying said abnormality report data. An abnormal packet processing system according to claim 1 or 2, wherein each of said processing units (3-1) include a main storage (40) for storing instructions and data, an instruction processing unit (41) for retrieving said instructions from said main storage (40) and executing them, a transfer processing unit (42) to transfer said packet between said main storage (40) and a network (32), and an abnormality detection circuit (43) for detecting abnormality when any abnormality occurs in said main storage (40), said instruction processing unit (41) and said transfer processing unit (42) during transfer of said packet. An abnormal packet processing system according to claim 3, wherein said transfer processing unit (42) includes a main storage access control unit (50) for controlling an access to said main storage (40), a data buffer (51) for storing data read out from said main storage (40) and accumulating data to be stored in said main storage (40) under control of said main storage access control unit (50), a network transfer control unit (52), a network interface (53), and a receiving abnormality indication device (54) for displaying the occurrence of any abnormality in said received packet. An abnormal packet processing system according to claim 4, wherein said network transfer control unit (52) includes a transmitting abnormality data addition device (55) for adding abnormality data to said data packet being transmitted by the report from said abnormality detection circuit (43).

Inventors: DEWA MASAMI, IKEDA MASAYUKI, ISHIZAKA KENICHI, KOBAYAKAWA KAZUSHIGE, NAGASAWA SHIGERU, SHINJO NAOKI, UENO HARUHIKO, UTSUMI TERUO, DEWA, MASAMI, IKEDA, MASAYUKI, ISHIZAKA, KENICHI, KOBAYAKAWA, KAZUSHIGE, NAGASAWA, SHIGERU, SHINJO, NAOKI, UENO, HARUHIKO, UTSUMI, TERUO, DEWA, MASAMI, C/O FUJITSU LIMITED, IKEDA, MASAYUKI, C/O FUJITSU LIMITED, ISHIZAKA, KENICHI, C/O FUJITSU LIMITED, KOBAYAKAWA, KAZUSHIGE, C/O FUJITSU LIMITED, NAGASAWA, SHIGERU, C/O FUJITSU LIMITED, SHINJO, NAOKI, C/O FUJITSU LIMITED, UENO, HARUHIKO, C/O FUJITSU LIMITED, UTSUMI, TERUO, C/O FUJITSU LIMITED
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1993
Main classification: H04L12
IPC codes: H04L12, G06F15, G06F13