Charge-to-voltage converter

Abstract: In a floating diffusion output type or a floating gate output type charge-to-voltage converter, the floating diffusion or the floating gate (1) is coupled to one or more diffusion regions (6) by means of one or more switch elements (7, 8; Q₁, Q₂), and such elements are selectively turned on or off (PG1, PG2) in such a manner that the charge-to-voltage conversion factor is raised to obtain a great voltage amplitude when a small quantity signal charge is input, or the conversion factor is lowered to obtain a small voltage amplitude when a large quantity signal charge is input.

Description: FIELD OF THE INVENTION The present invention relates to a charge-to-voltage converter for converting signal charge packets transferred thereto from a charge transfer region into a signal voltage. In particular, it relates to a charge-to-voltage converter of a floating diffusion output type. BACKGROUND OF THE INVENTION In a horizontal charge transfer region of a CCD area sensor or in a charge transfer region of a CCD delay line, a charge-to-voltage converter of a floating diffusion output type is employed as an output circuit for detecting input signal charge packets obtained from a charge transfer region and converting such signal charge packets into a signal voltage. As shown in FIGURE 3, in a conventional charge-to-voltage converter of a floating diffusion output type, a positive pulse is applied to a precharge gate (PG) 7 to switch on the PG 7, so that a potential in an floating diffusion (FD) region 1 can be used as a precharge voltage Vpd applied to a precharge drain (PD) region 2. Subsequently,in a state where the precharge gate is switched off, the signal charge packets transferred from a CCD transfer region 3 are injected into the FD region 1 via an output gate (OG). A signal voltage is produced by detecting the signal potential variation caused in the FD region 1. However, in the conventional charge-to-voltage converter of a floating diffusion output type mentioned above, the capacitance of the converter is of a fixed value. It is, therefore, impossible to selectively change the charge-to-voltage conversion factor of the converter, and the convertion factor is determined merely as a single value as follows. With regard to the signal charge quantity Q, the signal amplitude V in the FD region 1 (in FIGURE 3) is expressed as V = Q/C = Ne-/C where N is the number of electrons; e- denotes an elemental charge (-1.6 × 10-19[C]); and C is the capacitance of the FD region 1 (in FIGURE 3). Therefore the conversion factor ηH, i.e., the signal amplitude obtained at the time of input of one electron to the FD region 1 (in FIGURE 3), is given by η H = V/N = e-/C As a result, if the conversion factor is once set to a great value in design, the amplitude of the converted voltage is rendered excessively high when a large quantity of signal charge packets is input. Consequently such amplitude exceeds the maximum allowable limit of the converter to eventually raise a problem that proper charge-to-voltage conversion fails to be executed, whereby a sufficient dynamic range of conversion is not achievable. To the contrary, if the conversion factor of the converter is set to a small value in design for the purpose of complying with a large quantity of input signal charge packets as well, the amplitude of the converted voltage is rendered excessively low when the input signal charge packets are small in quantity. Harmful influence of noise is prone to be induced by the excessively low voltage to eventually raise a problem in practical use. In this case also, therefore, a sufficient dynamic range of conversion is not achievable either. In the EP-A-0 321 953 a charge transfer device provided with an improved out-putstage is disclosed, which has a gate electrode for resetting and electrodes for changing the sensitivity. In this charge transfer device the floating region is always surrounded by at least three gate electrodes, vis., the output gate electrode, the reset gate electrode and one of the electrodes for changing the sensitivity. Therefore, the floating region has undesired paracitic capacitances and as a result the charge transfer device has a comparatively low charge-to-voltage conversion factor. A similar charge coupled device is disclosed in patent abstracts of Japan, vol. 8, 142 and the JP-A-59 52 877. Summary of the invention In view of the circumstances mentioned, it is an object of the present invention to provide an improved charge-to-voltage converter which is changeable of the charge-to-voltage conversion factor of the converter by changing the capacitance of the floating diffusion and which is capable of relizing a sufficiently wide dynamic range in the conversion to comply with any state where the input signal charge packets are extremely small or great in quantity. To solve this object the present invention provides a charge-to-voltage converter as specified in claim 1. A preferred embodiment of the invention is described in claim 2. Since the capacitance of the floating diffusion or floating gate is changeable, hence achieving advantageous effects that the dynamic range of conversion can be widened. Therefore, when the invention is applied to a CCD imager or the like, a remarkable compleance is attainable in any state where the quantity of input light is extremely small or great. Brief description of the drawings The invention will be more readily understood with reference to the accompanying drawings, wherein: FIGURE 1 shows the constitution of a first embodiment of the present invention applied to a floating diffusion output type, in which (a) is a pattern diagram seen from above, (b) is a sectional view thereof, and (c) is an equivalent circuit diagram thereof; FIGURE 2 shows the constitution of a second embodiment of the present invention applied to a floating diffusion output type, in which (a) is a pattern diagram seen from above, (b) is a sectional view thereof, and (c) is an equivalent circuit diagram thereof; and FIGURE 3 shows the constitution of a conventional example of a floating diffusion output type, in which (a) is a pattern diagram seen from above, (b) is a sectional view thereof, and (c) is an equivalent circuit diagram thereof. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described in detail by referring to FIGURES 1 and 2. In these drawings, the same reference numerals are utilized as shown in FIGURE 3 so far as the same portions are referred. FIGURE 1 shows the constitution of a first embodiment of the present invention applied to a floating diffusion output type. In this embodiment, a diffusion region 6 is formed adjacent to an FD region 1 through a channel region, and a precharge drain (PD) region 2 is formed adjacent to the diffusion region 6 through a channel region. Further two precharge gates 7, 8 are formed on the channel regions respectively between such diffusion regions 1 & 6 and 6 & 2 to thereby constitute two MOS transistors (switch elements) Q1 and Q2. The charge-to-voltage conversion factor of the converter can be selectively changed by controlling the switching (on/off) actions of the two MOS transistors Q1 and Q2 in accordance with gate pulses PG1 and PG2 respectively. (1) In raising the conversion factor: Q1 is turned on or off by gate pulses PG1 corresponding to the conventional gate pulses PG. Q2 is kept in its on-state. (2) In lowering the conversion factor: Q1 is kept in its on-state. Q2 is turned on or off by gate pulses PG2 corresponding to the conventional gate pulses PG. The conversion factor is changeable in the following manner by selectively setting the two MOS transistors Q1 and Q2 as mentioned above. (1) In raising the conversion factor: With regard to the signal charge quantity Q, the signal amplitude VH in the FD region 1 is expressed as VH = Q/C1 = Ne-/C1 where N is the number of electrons; e- denotes an elemental charge (-1.6 × 10-19[C]); and C1 is the capacitance of the FD region 1. Therefore the conversion factor η H, i.e., the signal amplitude obtained at the time of input of one electron to the FD region 1, is given by η H = VH/N = e-/C1 (2) In lowering the conversion factor: Under the same conditions as those in (3), the signal amplitude VL in the FD region 1 is expressed as VL = Q/(C1 + C2) = Ne-/(C1 + C2) where C2 is the capacitance of the diffusion region 6. The conversion factor η L is given by ηL = VL/N = e-/(C1 + C2) As apparent from the above, ηH > η L Consequently it becomes possible to select either of two conversion factors by controlling the switching (on/off) actions of the two MOS transistors Q1, Q2 under external control of the terminal voltages PG1, PG2 of the precharge gates 7, 8. FIGURE 2 shows the constitution of a second embodiment of the present invention applied to a floating diffusion output type. In the second embodiment, two diffusion regions 6, 9 are formed adjacent to an FD region 1 through channel regions respectively. A PD region 2 is formed adjacent to the outer diffusion region 9 through a channel region. Further three precharge gates 7, 8, 10 are formed on the channel regions respectively between such diffusion regions 1 & 6, 6 & 9 and 9 & 2 to thereby constitute three MOS transistors Q1, Q2, Q3. The charge voltage conversion factor of the converter can be selectively changed by controlling the switching (on/off) actions of the three MOS transistors Q1, Q2, Q3 in accordance with gate pulses PG1, PG2, PG3 respectively. (1) In raising the conversion factor to the maximum: Q1 is turned on or off by gate pulses PG1 corresponding to the conventional gate pulses PG. Q2 is kept in its on-state. Q3 is also kept in its on-state. (2) In setting the conversion factor to an intermediate value: Q1 is kept in its on-state. Q2 is turned on or off by gate pulses PG2 corresponding to the conventional gate pulses PG. Q3 is kept in its on-state. (3) In lowering the conversion factor to the minimum: Q1 is kept in its on-state. Q2 is also kept in its on-state. Q3 is turned on or off by gate pulses PG3 corresponding to the conventional gate pulses PG. The conversion factor is changeable in the following manner by selectively setting the three MOS transistors Q1, Q2, Q3 as mentioned above. (1) In raising the conversion factor to the maximum: VH = Ne-/C1 η H = e-/C1 (2) In setting the conversion factor to an intermediate value: VM = Ne-/(C1 + C2) η M = e-/(C1 + C2) (3) In lowering the conversion factor to the minimum: VL = Ne-/(C1 + C2 + C3) η L = e-/(C1 + C2 + C3) where C3 is the capacitance of the diffusion region 9. As apparent from the above, η H > η M > η L Consequently it also becomes possible to select any of three conversion factors by controlling the switching (on/off) actions of the three MOS transistors Q1, Q2, Q3 under external control of the terminal voltages PG1, PG2, PG3 of the precharge gates 7, 8, 10. In the embodiments mentioned above, one or two diffusion regions are formed in addition to the known structure in the prior art to thereby constitute an improvement with an increase of one or two MOS transistors. However, it is to be understood that the present invention is not limited to such embodiments alone. For example, three or more diffusion regions may be added to further increase the number of MOS transistors.

Claims: Charge-to-voltage converter of a floating diffusion output type for producing a signal voltage by injecting signal charge packets transferred from a charge transfer region (3) into a floating diffusion region (1) via an output gate (OG), said converter comprising: a precharge drain region (2), a diffusion region (6); a first channel region and a second channel region separating said floating diffusion region (1) from said diffusion region and said diffusion region from said precharge drain region (2), respectively; a first precharge gate electrode (7) formed over said first channel region; and a second precharge gate electrode (8) formed over said second channel region; wherein the charge-to-voltage conversion factor being selectively changed in response to gate voltages (PG1, PG2) selectively applied to said first and second precharge gate electrodes (7, 8), said precharge drain region (2) is supplied with a reset voltage, and characterized in that said floating diffusion region (1) is adjacent only to said output gate (OG) and said first precharge gate (7) and connected only to said first channel region, said charge transfer region (3) and an output terminal (Vsig). A charge-to-voltage converter according to claim 1, characterized by a plurality of diffusion regions (6, 9) formed between said floating diffusion region (1) and said precharge drain region (2).

Inventors: MAKI YASUHITO, NARABU TADAKUNI, SATO MAKI, MAKI, YASUHITO, NARABU, TADAKUNI, SATO, MAKI, MAKI, YASUHITO, C/O SONY CORPORATION, NARABU, TADAKUNI, C/O SONY CORPORATION, Sato, Maki, c/o Sony Corporation
Applicants: SONY CORP, SONY CORPORATION
Application year: 1993
Main classification: H01L27
IPC codes: H01L29, H04N5, H01L21, G11C19