Liquid crystal display panel

Abstract: A liquid crystal display panel which includes a plurality of signal lines Yj (6) ( j = 1-N : total signal line number N) and a plurality of scanning lines Xi (5) (i=1-M) arranged in a matrix pattern of NxM, and thin film transistors (2) for switching signal inputs between a display pixel electrode (3) C (i, j) and signal wiring Yj, disposed to correspond to respective intersections of the signal lines and the scanning lines, and auxiliary capacitance Cadd formed in electrically parallel relation with the display pixel electrode C (i, j) composed of liquid crystal. The auxiliary capacitance Cadd is formed between the scanning line Xi-1 controlling the display pixel electrode C(i-1, j) at a previous stage of the display pixel electrode C (i, j) and display pixel electrode C (i, j), and disposed in such a positional relation that the display pixel electrode C (i, j) completely covers the scanning line Xi-1 at the previous stage in a direction of its line width in terms of a cross sectional construction. By the above arrangement, variation of display pixel signal due to leaking electric field from the gate line may be reduced.

Description: The present invention relates to a liquid crystal display panel having a base substrate, a confronting substrate and liquid crystal filled between the base substrate and the confronting substrate; said base substrate comprising a plurality of elongated signal electrodes extending parallel to each other, a plurality of elongated scanning electrodes extending parallel to each other and orthogonal to said signal electrodes to define a plurality of rectangular pixel areas, each pixel area enclosed by neighboring first and second signal electrodes and neighboring first and second scanning electrodes, said elongated first scanning electrode having a side edge facing said elongated second scanning electrode, a pixel electrode made of a transparent layer provided in each pixel area having a side edge juxtaposed to said side edge of said first scanning electrode, and a switching transistor provided between said first signal electrode and said pixel electrode. Conventionally, as a transistor array for a liquid crystal display device used for the above purpose, there has been provided an arrangement as shown in Figs. 2(a) and 2(b), and disclosed, for example, in a paper SID 89 DIGEST p.114 "Rear-Projection TV using High-Resolution a-Si TFT-LCD". More specifically, the array substrate as referred to above includes gate electrodes 4 for scanning lines X1-XM, source electrodes 6 for signal lines Y1-YN, and further, thin film transistors (referred to as TFT hereinafter) 2 formed corresponding to respective intersections, with a drain electrode 7 of the respective TFT being connected to a pixel electrode 3. Liquid crystal material 13 is inserted between a substrate 1 constituting the TFT and a confronting substrate 14, and independent pixels are formed between the pixel electrodes 3 and a confronting ground electrode 16 provided on the confronting substrate 14, with the liquid crystal 13 functioning as a capacitance equivalently. There are many cases where an auxiliary capacitance 12 is added in electrically parallel relation thereof depending on necessity in order to improve holding of the signal voltage. For constituting such auxiliary capacitance 12, it has been a recent trend to form the auxiliary capacitance 12 between the scanning lines 5Xi-1 of a previous stage and said display pixel electrode 3 in order to reduce the number of masks. However, in the case where the liquid crystal display mode is driven by a normally white mode (referred to as N.W. mode hereinafter) in which the display is made black during applying of voltage and it is made white during non-applying of voltage, due to occurrence of non-uniformity in the electric field within the pixels, there has been such a problem that consequent non-uniformity takes place in the orientation of liquid crystal molecules within the image area, thus resulting in lowering of the display quality arising from visible irregularities of the display. Still referring to Figs. 2(a) and 2(b) showing the conventional TFT-LCD of the previous stage capacitance type, problems taking place in the planar and sectional constructions in the known arrangement will be described hereinafter. In the conventional arrangement formed with the previous stage auxiliary capacitance 12, the display pixel electrode 3C (i, j) of the auxiliary electrode do not perfectly cover the scanning electrode 5Xi-1 of the previous stage in the direction of the line width, and thus, an edge portion of the previous stage electrode 5Xi-1 located close to said display pixel electrode 3C (i, j) is exposed. The exposure of the scanning electrode 5Xi-1 in terms of plane through the insulative layer results in the local lowering of transmission factor due to non-uniformity of signal potential within the pixels arising from leakage of the signal potential of the gate into the pixels. More specifically, in the above known arrangement, on the assumption, for example, that the signal applied to the pixel 3C (i, j) is at 4V, potential of gate electrode 4Xi and 5Xi is at -9V as an off potential, and potential of a confronting substrate 14 is at 0V, the potential distribution in the liquid crystal 13 constituting the pixels 3C (i, j) will be represented as shown in Fig. 3, and thus, non-uniformity of electric field distribution within the pixels 3C (i, j) becomes larger, thereby forming distribution within one pixel face in a transmittance characteristic of light. Accordingly, it has been necessary to hide the display from the pixel edge as much as 8µm in total, i.e., about 4µm from the edge of the pixel electrode 3 as the non-uniformity portion of the signal potential, and also, about 4µm as a margin for combining a black matrix disposed at the confronting substrate 14 and the pixel electrode 3. Therefore, there has been such a problem that display aperture ratio of the pixel is lowered as the density becomes higher. From EP-A-288 011 a liquid crystal display device is known, in which a pixel electrode overlaps that gate line or scanning line that corresponds to the next pixel, so that in an overlap area an additional capacitance is formed. From EP-A-464 579 a thin film field effect transistor array for a liquid crystal display is known, in which a pixel electrode overlaps a gate line in an area, thus forming an auxiliary capacitance. The pixel electrode is connected via contact holes with a thin film field effect transistor positioned at the intersection of scanning and signal lines. It is an object of the present invention to provide a liquid crystal display panel which is so arranged that display potential thereof is not adversely affected by an electric field from the gate electrode of a thin film transistor (referred to as TFT hereinafter), thereby to improve display quality of a thin film transistor-liquid crystal display (referred to as TFT-LCD hereinafter). The liquid crystal display panel of the above described type should also be simple in construction and stable in functioning at high reliability, so that it can be readily manufactured on a large scale at low cost. In accomplishing this object of the invention, a liquid crystal display panel as defined in the preamble of claim 1 is characterized in that a separate auxiliary electrode layer is provided on an insulating layer formed on the scanning electrodes and beneath the pixel electrode, said auxiliary electrode layer being arranged above the scanning electrode layer so as to extend beyond the side edges of the adjacent scanning electrode and the adjacent side edge of the respective pixel electrode layer. Preferable embodiments are defined in the dependent claims. The invention will now be described in connection with preferred embodiments of the invention with reference to the accompanying drawings, in which Fig. 1(a) is a fragmentary top plane view of a TFT-LCD serving as comparative example for describing the present invention, Fig. 1(b) is a fragmentary side sectional view on an enlarged scale, of the TFT-LCD of Fig. 1, Fig. 2(a) is a fragmentary top plane view of a conventional TFT-LCD having a previous stage capacitance, Fig. 2(b) is a fragmentary side sectional view on an enlarged scale of the conventional TFT-LCD of Fig. 2(a), Fig. 3 is a schematic cross sectional diagram for explaining non-uniformity of potential distribution in the pixel within liquid crystal for the conventional arrangement, Fig. 4 is a schematic fragmentary cross section showing a first step for forming the TFT array according to the example shown in Fig. 1; Fig. 5 is a cross section similar to Fig. 4, which particularly shows a second step therefor, Fig. 6 is a cross section similar to Fig. 4, which particularly shows a third step therefor, Fig. 7 is a fragmentary cross sectional view showing a TFT array according to an embodiment of the present invention, Fig. 8 is also a fragmentary cross sectional view similar to Fig. 7, which particularly shows another embodiment of the present invention, Fig. 9(a) is a top plane view similar to Fig. 1, which particularly shows a planar positional relation of a black matrix formed on the TFT-LCD with respect to the pixel electrode, and Fig. 9(b) is a schematic fragmentary side sectional view taken along the line IX(b)-IX(b) in Fig. 9(a), showing a side sectional positional relation of the black matrix formed on the TFT-LCD with respect to the pixel electrode. Before the description of the present invention proceeds, it is to be noted that like parts are designated by like reference numerals throughout the accompanying drawings. Figs. 1(a) and 1(b) show the construction of an array for a TFT liquid crystal display device as a comparative example. By adopting a construction to completely cover the gate electrode 5Xi-1 at a previous stage with pixel electrode 3C (i, j), leakage of electric field from the gate electrode 5Xi-1 can be prevented by shielding, and thus, uniformity of potential within the pixel C (i, j) may be improved. In this case, the gate electrode 4 of the TFT 2 for driving the display electrode 3C (i, j) is connected to scanning line 4Xi, and the display pixel 3C (i, j) forms an auxiliary capacitance 12 with respect to the scanning line 5Xi-1 at a previous stage through the gate insulative layer 8. The planar and side sectional constructions as shown in Figs. 1(a) and 1(b) can be achieved by following processes as described hereinbelow. For a first step, a substrate including a transparent substrate 1, and gate electrode 4Xi (i = 1-M), 5Xi-1, a gate insulative layer 8 formed by P-CVD method, etc., which are formed on said substrate 1, and a semi-conductor layer 9 with a channel protective layer 10 and another semi-conductor layer 9' doped with impurities for ohmic contact further formed on said semi-conductor layer 9 with a channel protective layer 10 is prepared as shown in Fig. 4. In a second step, when a transparent layer which serves as the pixel electrode 3C (i, j) is formed, it is so arranged that the gate electrode 5Xi-1 at the previous stage is completely covered by the pixel electrode 3C, so as to form said pixel electrode 3C (i, j) and its auxiliary capacitance forming portion 12 Cadd as illustrated in Fig. 5 . Further, for a third step as shown in Fig. 6, source electrode 6 and drain electrode 7 are formed on the substrate, thereby to form the TFT array in a matrix pattern. Moreover, in order to improve the reliability of the TFT 2, SiNx18 deposited by P-CVD method or the like is formed on said substrate with the pixel portion opened thereon. As is seen from Figs. 1(a) and 1(b), in the positional relation in the cross section, between the pixel electrode 3 forming the auxiliary capacitance 12 and the scanning line 5Xi-1 at the previous stage, the pixel electrode 3 completely covers the scanning line 5Xi-1 in the direction of its line width. This arrangement is different from the conventional arrangement as described in connection with Figs. 2(a) and 2(b). In a TFT array according to an embodiment of the present invention as shown in Fig. 7, in the structure of the source electrode 6 and the drain electrode 7, the pixel electrode 3C (i, j) is positioned at the upper layer from the source electrode 6 and the drain electrode 7 through the insulative layer 18, with the gate electrode 5Xi-1 at the previous stage being completely covered by the auxiliary electrode 21. Moreover, the pixel electrode 3C (i, j) is connected with the auxiliary electrode 21 through contact holes 19 formed in the insulative layer 18 located at the lower layer of the pixel electrode 3C (i, j). In a TFT array according to a further embodiment of the present invention as shown in Fig. 8, in the positional relation in the cross section, of the pixel electrode 3C (i, j), the source electrode 6, and the drain electrode 7, said pixel electrode 3C (i, j) is located at a lower layer than said source electrode 6 and the drain electrode 7. The pixel electrode 3 and the auxiliary electrode 21 are connected through contact holes 19 formed in the insulative layer 8 provided on said pixel electrode. In this case, an edge portion of the gate electrode 5Xi-1 at the previous stage near the pixel electrode 3C (i,j) with respect to the direction of line width is covered by the auxiliary electrode 21 connected with the pixel electrode 3C (i, j) or the gate electrode 5Xi-1 is completely covered thereby in its line width direction. Moreover, in any of the foregoing embodiments, a black matrix 15 may be provided on the confronting substrate 14 holding the liquid crystal 13 with respect to the TFT array substrate, and part of the gate electrode 5Xi-1 covered by the auxiliary electrode 21. Referring now to Figures 9(a) and 9(b), by this arrangement, since the gate portion 20 not covered by the black matrix 15 on the confronting substrate 14 is covered by the pixel electrode 3C (i, j), it is a region not affected by the gate electric field. Thus, transmission light is shielded by the gate electrode to serve as the black matrix, and further, owing to the fact that the electric field within the pixels is not affected by the gate electric field, the electric field of the transmission pixel portion may be made uniform. As is clear from the foregoing description, according to the arrangement of the present invention, the non-uniformity of potential within the pixels and lowering of the aperture ratio which are the problems in the display quality for the TFT-LCD can be remarkably improved by covering the gate electrode with the pixel electrode. For example, when the black matrix width is held constant, in the case of 100µm square pitch pixel, the width of the black matrix at 28µm in the conventional arrangement may be reduced to 24µm according to the present invention, while in the aperture ratio at 52% can be improved to 58%. Moreover, in the case of 50µm square pitch, 19% in the conventional example may be improved to 27% according to the present invention. Therefore, the arrangement of the present invention displays more effect as the pixel density becomes higher. Furthermore, since the simple construction is adopted to form the auxiliary capacitance with respect to the scanning line, the TFT array may be constituted without increasing the number of masks, and thus, it becomes possible to improve the display quality not requiring particular cost increase.

Claims: A liquid crystal display panel having a base substrate (1), a confronting substrate (14) and liquid crystal (13) filled between the base substrate and the confronting substrate; said base substrate (1) comprising a plurality of elongated signal electrodes (6) extending parallel to each other, a plurality of elongated scanning electrodes (5, 4) extending parallel to each other and orthogonal to said signal electrodes to define a plurality of rectangular pixel areas, each pixel area enclosed by neighboring first and second signal electrodes (6) and neighboring first and second scanning electrodes (5, 4), said elongated first scanning electrode (5) having a side edge facing said elongated second scanning electrode (4), a pixel electrode (3C) made of a transparent layer provided in each pixel area having a side edge juxtaposed to said side edge of said first scanning electrode (5), and a switching transistor (2) provided between said first signal electrode (6) and said pixel electrode (3C); characterized in that a separate auxiliary electrode layer (21) is provided on an insulating layer (8) formed on the scanning electrodes (4, 5) and beneath the pixel electrode (3), said auxiliary electrode layer (21) being arranged above the scanning electrode layer so as to extend beyond the side edges of the first scanning electrode (5) and the adjacent side edge of the respective pixel electrode layer. A liquid crystal display panel as claimed in claim 1, characterized in that said auxiliary electrode layer (21) overlaps the entire width of said first scanning electrode (5). A liquid crystal display panel as claimed in claim 1, characterized in that said switching transistor (2) comprises: a gate electrode (4) which is in common with said second scanning electrode (4); a source electrode (6) which is in common with said first signal electrode (6); and a drain electrode (7) which is connected to said pixel electrode (3). A liquid crystal display panel as claimed in claim 1, characterized in that another insulation layer (18) is disposed between said pixel electrode (3) and said auxiliary electrode layer (21). A liquid crystal display panel as claimed in claim 1, characterized in that another insulation layer (18) is disposed above said pixel electrode (3). A liquid crystal display panel as claimed in claim 4 or 5, characterized by connecting means (19) extending through a through-hole formed in said another insulation layer (18). A liquid crystal display panel as claimed in claim 1, characterized in that said auxiliary electrode layer (21) is located below said pixel electrode (3). A liquid crystal display panel as claimed in claim 1, characterized in that said auxiliary electrode layer (21) is located above said pixel electrode (3). A liquid crystal display panel as claimed in claim 1, characterized in that a black matrix (15) provided on said confronting substrate (14) does not cover the said first scanning electrode (5).

Inventors: KOBAYASHI IKUNORI, TAKEDA MAMORU, KOBAYASHI, IKUNORI, TAKEDA, MAMORU
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1993
Main classification: G02F1
IPC codes: G02F1, G09F9