Voltage generation circuits and methods

Abstract: According to the present invention, a voltage generation circuit is provided including a differential amplifier having positive and negative single inputs and first and second outputs. A voltage divider circuit is provided included first and second transistors (46, 48) having source/drain paths coupled in series to establish a current path between a high voltage rail V DD and low voltage U SS rail, the first and second transistors (46, 48) matched to provide a mid-supply voltage at a node along the current path, the node coupled to the positive input of the differential amplifier. Third and fourth transistors (38, 42) are provided having source/drain paths coupled in series between the first and second outputs of the differential amplifier, of the sources of the third and fourth transistors (38, 42) coupled to the negative input of the differential amplifier. The gate of the third transistor (38) is coupled to the first output of the differential amplifier and the gate of the fourth transistor (42) is coupled to the second output of the amplifier. A pair of open loop output transistors (40, 44) having source/drain paths coupled in series between the voltage rails is provided. The sources of the output transistors (40, 44) are coupled together to provide a low impedance output for the voltage generator circuit. A first one of the output transistors (40, 44) includes a gate coupled to the first output of the differential amplifier, and is matched to the third transistor (38). A second one of the output transistors (40, 44) has a gate coupled to the second output and is matched to the fourth transistor (42).

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates in general to electronic circuits and in particular to voltage generation circuits and methods. BACKGROUND OF THE INVENTION Single-rail integrated circuit systems which include analog devices and which also employ only a single voltage power supply and ground return, typically require the generation of an on-chip mid-supply voltage for an analog ground (AGND) reference. One currently available method of generating the mid-rail voltage while maintaining a low AC impedance is to use large value polysilicon resistors as a voltage divider to set the half-supply voltage, and then using an operational amplifier configured as a voltage follower (i.e., having unity gain feedback) to buffer the AGND supply. With the unity gain buffer approach, however, significant trade-offs must be made between circuit stability, bandwidth and slew rate. At d.c., the closed-loop output impedance of an operational amplifier is equal to its d.c. open-loop output impedance (∼ 1KΩ for a CMOS device) divided by the loop gain, which is typically on the order of 1Ω. At the unity gain frequency and beyond, however, the operational amplifier output impedance approximates the a.c. open-loop impedance which typically can range between 1 - 10 KΩ for a CMOS device. The result is that the mid-rail voltage supply generator will be slow to respond to frequencies beyond its unity gain bandwidth, such that high speed clock coupling and high frequency noise become a problem. Since CMOS circuits are primarily capacitive in nature, the AGND (analog ground) output node of the operational amplifier will have a large amount of capacitance coupled to it, and therefore, for unity gain stability, the operational amplifier must be internally compensated which decreases its slewing capability. To increase slewing in turn requires more current, and thus more power dissipation. Finally, because the AGND voltage generator must drive a capacitive load, then for the bandwidth to remain relatively constant, the ratio of the transconductance g m of the operational amplifier input stage to the value of the compensation capacitor C c must remain constant, even as larger compensation capacitors are required. Therefore, the transconductance g m must also increase as larger values of the compensation capacitor are required. Each of these design modifications causes an increase in the physical size of the mid-supply generator and in the required supply current. Thus, the need has arisen for an improved mid-rail voltage supply generator having good stability, bandwidth and slew rate, while at the same time being relatively small in physical size and requiring minimum supply current. EP-A-0 195 525 and EP-A-0 321 226 propose circuits for providing a mid-rail voltage supply. SUMMARY OF THE INVENTION According to the invention, a voltage generation circuitry comprising a differential amplifier having a positive signal input, a negative signal input, and first and second outputs; a voltage divider circuit coupled between first and second voltage supplies and providing a preselected voltage to said positive input of said differential amplifier; first and second transistors each having a current path and a control terminal, said current paths of said first and second transistors coupled at a node and further coupled in series between said first and second outputs of said amplifier, said control terminal of said first transistor coupled to said first output of said amplifier and said control terminal of said second transistor coupled to said second output, said node coupled to said negative input of said differential amplifier; and third and fourth transistors having current paths coupled in series between said voltage supplies, a node coupling said current paths of said third and fourth transistors providing an output for said voltage generation circuitry, said third transistor having a control terminal coupled to said first output of said amplifier and matched as a current mirror with said first transistor, and said fourth transistor having a control terminal coupled to said second output of said amplifier and matched as a current mirror to said second transistor. The present invention provides an improved mid-rail voltage supply generator having good stability, band width, slew rate and low output impedance while at the same time being relatively small in physical size and requiring minimum supply of current. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the illustrated embodiments of the present invention, and the advantages thereof, reference is now made to the following descriptions, taken in conjunction with the accompanying drawings in which: FIGURE 1 is a electrical schematic diagram of a voltage generation circuit according to the present invention. DETAILED DESCRIPTION OF THE INVENTION Referring to FIGURE 1, a mid-rail (analog ground) voltage generation circuit is shown generally at 10. In the preferred embodiment, generator 10 is fabricated as part of an integrated circuit including analog devices requiring a ground reference. In the illustrated embodiment, circuit 10 operates between a high rail (V DD ) and a low rail (V SS ), which typically are +5 volts and ground. It is important to recognize, however, that circuit 10 can also be used between differing voltage rails such +10 volts and -0 volts, the operation being substantially the same. P-channel field effect transistor 12, a resistor 14 and n-channel field effect transistor 16 are current source for a differential amplifier made up of field effect transistors 18, 20, 22, 24, 26, 28, 30, 32, 34 and 36. Resistor 14 may be a high sheet resistance polysilicon layer or formed from a diffused region on the chip. Transistor 36 is the tail current device which mirrors the current flowing in transistor 12 into the differential pair formed by p-channel transistors 18 and 20. N-channel transistors 22 and 24 provide the load devices for the differential pair of transistors 18 and 20. N-channel transistors 26 and 28 are common source transistor amplifiers used to increase the voltage gain at the output of the differential pair formed by transistors 18 and 20. P-channel transistors 30 and 32 form a unity gain current mirror used to translate the voltage gain of transistor 26 to the gates of transistors 38 and 40. Transistor 28 directly drives the gates of p-channel transistors 42 and 44. N-channel transistor 34 is a cascode device used to increase the output resistance of transistor 26, thereby eliminating channel-length modulation effects. The positive input to the differential amplifier (the gate of transistor 20) is set to the mid-supply voltage by equally sized (matched) diode connected p-channel transistors 46 and 48. Since for the fabrication of a given integrated circuit factors, such as gate oxide thickness and gate capacitance per area are essentially the same for all transistors on the chip, the problem of matching primarily concerns itself with matching width/length ratios of the transistor channels. The negative input of the differential amplifier (the gate of transistor 18) is the common connection to the sources of transistors 38 and 42, both of which are also diode connected. The gates and drains of transistors 38 and 42 are driven by the outputs (the drains of transistors 28 and 32) of the differential amplifier, the negative feedback of the circuit connection to the gate of transistor 18 forcing the common sources of transistors 38 and 42 to the mid-supply voltage. The output is then forced to the mid-supply voltage by the matching of transistor 38 to transistor 40, and transistor 42 to transistor 44. The common sources of transistors 40 and 44 provide a low impedance output for circuitry 10. In the illustrated embodiment, transistors 38 and 42 are matched at a 1:10 ratio to transistors 40 and 44. In this embodiment transistor 40 mirrors the current flow through transistor 38 with a current gain of ten and transistor 44 mirrors the current flow through transistor 42 with a current gain of ten. In alternate embodiments, the current gains may be adjusted by changing the matching between the transistors 38 and 42 and transistors 40 and 44. To further improve matching, transistor 40 and 44 may be fabricated as a group of parallel transistors, each substantially equal in size (i.e., width to length channel ratios substantially equal) to transistors 38 and 42. For example, in the illustrated embodiment, transistor 38 has a width/length ratio of 100/1 and therefore preferably, transistor 40 is fabricated as ten 100/1 transistors to arrive at the equivalent of a 1000/1 transistor. The only variations (errors) in the mid-supply voltage available at the output come from any mismatch in the impedance of transistors 40 and 42 from differences in transconductance and output conductance. The offset at the circuit output compared to a voltage exactly one-half of the supply voltage is not a substantial problem if the offset remains on the order of tens of millivolts, since the output voltage will be used for the analog ground for any circuits referenced to it. If, however, the offset at the output of the circuit increases to the order of hundreds of millivolts or more, the dynamic range for low distortion at maximum signal levels may be reduced. Output transistors 40 and 44 are advantageously not included in any feedback loop such that they operate at their own transition frequency f T . Transistors 40 and 44 are designed to operate at a very high frequency and have good transient settling response. The small signal output impedance of generator 10 is the parallel combination of the source impedances of transistors 40 and 44: R s40 R s44 R s40 + R s44 where R S40 ∼ 1 / g m40 and R S44 ∼ 1 / g m44 . The output resistance R 0 is preferably designed to be on the order of tens of ohms and be constant to frequencies out very near to the f T of the devices. Further, since the output of generator 10 is open loop, a very large capacitor, such as capacitor 50 in FIGURE 1, can be connected to it without any stability problems. Capacitor 46, for example, may be an off-chip capacitor on the order of one microfarad, and can be used to lower the output impedance to approximately 1Ω at approximately 160 Khz and beyond. Since the integrated circuit upon which generator 10 is preferably employed may only have a capacitive load presented to the generator 10 itself, a large off-chip capacitor, such as capacitor 50, will act as a reservoir of charge to restore any glitch due to high frequency effects. Additionally, it should be recognized that if circuit 10 is used as part of an integrated circuit, and capacitor 46 is off-chip, a resistor (not shown) may be added in series with the circuit output to reduce the Q of an LC tank circuit resulting from capacitor 50 and the lead frame inductor. Mid-rail voltage generator 10 is powered down by signal PWDN through n-channel transistor 52. To save power, the output of circuitry 10 goes to a high impedance state and p-channel transistors 54 and 56 clamp the output near the mid-supply voltage by supplying leakage current to keep capacitor 50 charged up. It is important to recognize that the p-well CMOS n-channel and p-channel devices can be interchanged, as known in the art, without change to the inventive concepts of the present invention as illustrated herein.

Claims: A voltage generation circuitry comprising: a differential amplifier (18-36) having a positive signal input (20), a negative signal input (18), and first and second outputs (28,32); a voltage divider circuit (46,48) coupled between first and second voltage supplies (V DD , V SS ) and providing a preselected voltage to said positive input of said differential amplifier; first and second transistors (38,40) each having a current path and a control terminal, said current paths of said first and second transistors coupled at a node and further coupled in series between said first and second outputs (28,32) of said amplifier, said control terminal of said first transistor (38) coupled to said first output (32) of said amplifier and said control terminal of said second transistor (40) coupled to said second output (28), said mode being coupled to said negative input (18) of said differential amplifier; and third and fourth transistors (40,44) having current paths coupled in series between said voltage supplies (V DD ,V SS ), a node coupling said current paths of said third and fourth transistors providing an output for said voltage generation circuitry, said third transistor (40) having a control terminal coupled to said first output (32) of said amplifier and matched as a current mirror with said first transistor (38), and said fourth transistor (44) having a control terminal coupled to said second output (28) of said amplifier and matched as a current mirror to said second transistor (42). The voltage generation circuitry of claim 1, wherein said voltage divider circuit comprises fifth and sixth transistors (46,48) having current paths coupled in series between said voltage supplies (V DD ,V SS ), said fifth and sixth transistors matched to provide said preselected voltage at a node coupling said current paths. The voltage generation circuitry of claim 2, wherein said fifth and sixth transistors comprise first and second diode connected transistors (46,48) having substantially equal channel width to length ratios, said node coupling a drain of said fifth transistor (46) and a source of said sixth transistor (46). The voltage generation circuitry of any preceding claim, wherein said third transistor (40) has a channel width to length ratio of n times a channel width to length ratio of said first transistor (38) and said fourth transistor (44) has a channel width to length ratio of n times a channel width to length ratio of said second transistor (28), where n is a positive integer. The voltage generation circuitry of any of claims 1 to 3, wherein said third transistor (40) comprises n parallel transistors each having a channel width to length ratio substantially equal to said channel width to length ratio of said first transistor (38), and said fourth transistor (44) comprises n parallel transistors each having a channel width to length ratio substantially equal to said channel width to length ratio of said second transistor (28). The voltage generation circuitry of any preceding claim, wherein said differential amplifier comprises: a differential transistor pair comprising first and second differential transistors (18,20) having sources coupled together and to a current source, a gate of said first differential transistor (20) providing said positive input and a gate of said second differential transistor (18) providing said negative input; a first voltage amplifier transistor (28) having a gate coupled to a drain of said first differential transistor, a source coupled to said low voltage rail(V SS ) and a drain providing said second output of said differential amplifier; and a second voltage amplifier transistor (26) having a gate coupled to a drain of said second differential transistor (18), a source coupled to said low voltage rail (V SS ) and a drain; a first mirroring transistor (30) having a drain and a gate coupled to said drain of said second voltage amplifier transistor (26), and a source coupled to said high voltage supply rail V DD ; and a second mirroring transistor (32) having a gate coupled to said gate of said first mirroring transistor (30), a source coupled to said high voltage supply rail (V DD ) and a drain providing said first output of said differential amplifier. The voltage generation circuitry of claim 6, wherein said drain of said second voltage amplifier transistor (26) is coupled to said of said first mirroring transistor (30) through a cascode transistor (34), said cascode transistor having a source coupled to said drain of said second amplifier transistor (26), a drain coupled to said drain of said first mirroring transistor (30) and a gate coupled to said node. The voltage generation circuitry of any preceding claim, wherein said differential amplifier includes a current supply input (36) coupled to a current source comprising a pair of transistors having current paths coupled in series between said voltage rails. The voltage generation circuitry of claim 8, wherein said current paths of said pair of transistors (12,16) comprising said current supply input are coupled by a resistor (14). The voltage generation circuitry of claim 8 or claim 9, wherein said current source is coupled to said current supply input through a current mirroring transistor (36). The voltage generation circuitry of any of claims 8 to 10, and comprising: a power control device (52) selectively coupling said pair of transistors (12,16) included in said current source with one of said voltage rails (V SS ); a first clamping transistor (54) coupling said high voltage rail (V DD ); and a second clamping transistor (56) coupling said low voltage rail (V SS ) to said output of said circuitry, said first and second clamping transistors providing leakage current to said output. The voltage generation circuitry of any preceding claim, wherein said first, second, third and fourth transistors (38-44) comprise field effect transistors. A method for generating an analog ground voltage comprising the steps of: generating a mid-rail voltage using a voltage divider circuit (46,48) operating between first and second voltage rails (V DD , V SS ); applying the mid-rail voltage to a positive input (20) of a differential amplifier (18-36); establishing a current path between first and second outputs (32) of the differential amplifier with a pair of diode connected transistors (38,42), the gate and drain of a first one (38) of the pair driven by the first outputs (28,32) of the differential amplifier and the gate and drain of a second one (42) of the pair driven by the second output (28) of the differential amplifier, the sources of the said pair of transistors (38,42) coupled to a negative input of the differential amplifier; and establishing a current path between the voltage rails with a pair of common source output transistors (40,44), a first one (40) of the output transistors mirroring current flow in the first one (38) of the diode connected transistors and a second one (44) of the output transistor mirroring current flow in the second one (42) of the diode connected transistors, the current gain of each of the pair of output transistors selected to be substantially equal. The method of claim 13, wherein said step of generating a mid-rail voltage comprises the step of using a voltage divider comprising diode connected transistors (46, 48).

Inventors: HELLUMS JAMES R, YUNG HENRY TIN-HANG, HELLUMS, JAMES R., YUNG, HENRY TIN-HANG
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1993
Main classification: G05F3
IPC codes: G05F1, H03F3, G05F3