Programmable single/dual output data streams RLL/NRZ decoder

Abstract: A decoder of a coded serial stream of digital data in a stream of decoded NRZ data has re-timing (BB, AA) flip-flops and a 2x1 multiplexer (MUX OUT) selectably providing a single-bit NRZ output stream or a dual-bit (NRZ⊘ and NRZ1) output streams by exploiting the pre-decoded values (ND⊘ and ND1) produced by two decoding combinative logic networks (RC1 and RC2) that compose the decoder.

Description: The invention generally relates to a programmable decoder for serial data transfer channels, for example from peripherals to a Central Processing Units (CPU) and viceversa. The invention is particularly useful for read/write channels of mass memories, for example hard-disk systems. In mass data storage supports, as for example hard disks, floppy disks, CDs, tape streamers and alike, digital data are stored, in practice, by physically recording on the support only the logic "1" and by "spacing" them by "segments" of a recording track, the length of which is proportional to the number of logical "0" present between successive "1". Considerations on the dynamic character typical of rotating supports or generally of translating supports, impose a minimum value of the separation distance between adjacently recorded "1", because if two successive "1" were to be physically recorded one next to the other on the support, inevitable interferences between the two recordings (peaks) detected in reading the data off the support, could cause uncertainties and errors due to a practical limitation of the discriminating capabilities of the reading pick-ups. Another common peculiarity of these mass data storage systems is represented by the fact that the sampling clock signal, used in the write/read channels, cannot be derived from a fixed system's clock, but necessarily must be a clock signal that is derived or extracted directly from the incoming serial stream of data, the speed of which may often vary. For example, in the case of a hard-disk, data recorded on outer tracks may be written and read at a higher linear speeds than data written and read on inner concentric tracks. Generally, in this as in other applications, a variable frequency clock signal, synchronous with the serial stream of data (pulses), is generated by detecting transitions in the coded stream of pulses that represents the succession of digital data, for example by employing a common phase-locked, ring circuit (TLL), cooperating with a voltage controlled oscillator (VCO). Where the need exists for self-generating a synchronous, variable frequency, clock signal, there may be a limit to the maximum tolerable "distance" between any two successively recorded logic "1", because if successive transitions were to occur after an excessively long interval of time, synchronism of the frequency of the self-generated clock signal, "phase-locked" with the pulse stream, could be partially lost, thus introducing, also in this case, conditions of indiscrimination of the correct sampling instant and therefore of reading errors. These "dynamic" limits in the operation of these systems are commonly overcome by employing special coding systems for the data being transferred, which ensure a certain minimum number of "0" and a certain maximum number of "0" between any two successive "1" of a coded binary data stream. There are different coding protocols of this type, for example in the RLL(2,7) coding (an acronym for Run Length Limited) , the values 2 and 7 7 indicate the minimum (2) number and the maximum (7) number, respectively, of "0" between two successive "1". In the: RLL(1,7) system, the two values indicate the minimum number (1) and the maximum number (7) of "0", that can be present between any two successive "1" of a coded binary data. Of course, the use of a particular coding of the serial data stream, for example from and to a rotating mass storage support, or also from and to a different type of peripheral having dynamic characteristics of operation similar thereto, implies the use of special coding and decoding circuits of the serial stream of digital data. A peculiarity common to these as well as to other coding/decoding systems, wherein the "frequencies" of the input and output serial data streams are different from each other, is represented by the fact that to a certain X number of bits of a decoded data serial signal, commonly of the so-called NRZ type (an acronym of Non-Return-to-Zero), corresponds a greater Y number of bits (Y=X+z, where z≥1) of a coded data serial signal. For example, to three bits (pulses) of the coded signal may correspond two bits (pulses) of an NRZ stream of decoded data. This fact implies that, during a reading phase, a certain time base frequency (base clock) VCO, be extracted from the sequence of transitions of the input coded signal, for example by the use of a PLL circuit. The clock signal VCO, synchronous with the coded serial stream, is used as the control (sampling) clock signal of a shift register to which the coded serial signal is fed. If, for example, the ratio between the equivalent number of bits of the coded serial stream and of the decoded serial stream is equal to 3:2(1.5), the base clock signal VCO, derived from the transitions of the coded input signal, may be used for deriving a first fractionary frequency clock signal VCO/1.5 for sampling the decoded output signal and a second fractionary frequency clock signal VCO/3 which is employed in the timing and synthesizing functions that must be necessarily performed by the decoding logic circuitry of the decoder. Typically, a decoder of this type, employs two decodification combinative logic networks. In the case of a decoder designed for handling an n number of bits, a first logic network processes the n-bits present at the n taps of a shift register to which the coded input signal is fed under the control of the synchronous extracted clock signal VCO and produces a first decodification signal. The signal produced by the first logic network is timed, by employing for the purpose a flip-flop that is sampled at the fractionary frequency of a first fractionary clock signal, and the so re-timed signal is fed to an input of a second combinative logic network, which processes a fractionary number of the n number of bits, picked-up from the respective taps of the input shift register. The first decodification signal produced by the first combinative logic network and a second fractionary frequency clock signal are input to the second logic network in order to re-synthesize the re-timed signal, produced by the first network, and produce a second decodification signal at the output of the second combinative logic network which, sampled by a second output flip-flop at the frequency of the first fractionary frequency clock, produces a decoded NRZ output stream. A decoder of this type together with an improved decoder that incorporates timing, multiplexing, retiming means for the first decodification signal, which in cooperation with storing latches of the fractionary number of bits that are processed by the second logic network, permit to double the operating frequency of the decoder, for the same fabrication technology of the combinative logic networks, are described in the European patent application No. 93830387.2, filed on September 21, 1993, by the same applicant. The description contained in said prior patent application is herein incorporated by express reference. The circuits "downstream" of the decoder must convert the serial stream of NRZ data in binary words, for example of 8 bits, that may thereafter be transferred toward a central processing unit, through parallel interfaces. This conversion of the data stream is commonly assisted by a microprocessor that supervises the serial-to-parallel conversion and the routing of the decoded bytes toward a support memory. The solution of employing a decoder that instead of producing a single NRZ output stream, produces two output streams, that is a dual output stream, respectively a first NRZ⊘ data stream and a second NRZ1 data stream is known. For the same frequency of the coded data signal present at the input of the decoder, the use of a dual-bit NRZ decoder permits to employ circuits for converting the decoded NRZ serial signal into a binary parallel signal capable of operating at half the frequency of what would be necessary for handling a single-bit decoded NRZ output stream. Notwithstanding that the required duplication of the downstream conversion networks will not produce a substantial global energy saving, it is possible to employ "slower" integrated circuits for realizing the converting networks, that is devices fabricated with less sophisticated technologies and therefore less expensive. The saving increases with the frequency of the input serial data stream. In many cases, the possibility of employing devices that can be fabricated with different technologies, permits also to optimize performances of the respective subsystems. In general, the choice of a single-bit NRZ decoder or of a dual-bit MRZ decoder, depends from design choices of the user of the integrated devices, that is of the manufacturer of the hardware apparatus. There is the need or utility for a decoder, the operating mode of which may be programmable by the user, according to his needs and/or in function of mutating operating conditions of the whole hardware system. This objective is fully achieved by the decoder of the present invention, which is provided with means for selecting, by programming either a single-bit output stream of decoded (NRZ) data or a dual-bit (NRZ0 & NRZ1) output stream of decoded data. This permits a complete adaptability of the device to the different situation of use, thus providing the user with the possibility of selecting one or the other output mode for the decoded stream, depending on the design choices of the hardware system, the operating frequency and/or on particular operating conditions, for example from the aspect of heat dissipation capabilities. By the use of a pair of timing flip-flops, controlled by a second fractionary frequency clock signal, a first decodification signal generated by a first combinative logic network (NRZ0) and a second decodification signal generated by a second combinative logic network (NRZ1), are made available through respective outputs (terminals) of the decoder, without effecting a re-synthesizing of the first decodification signal produced by the first combinative logic network with the fractionary number of bits that are processed by the second combinative logic network. Such a re-synthesizing function is effected in the second combinative logic network, as in a normal prior art decoder, by employing said second fractionary frequency clock signal, which "modifies" the combinative logic function of the network so that its output alternately assumes a simply re-timed value, as substantially produced by the first combinative logic network, and the value that is produced by the second combinative logic network by processing the relative input bits. In practice, a multiplexing function is realized within the second combinative logic network, that is instrumental in making available, at the output of the decoder, alternately the decoded dual-bits of the NRZ signal. The circuit employs a pair of output sampling flip-flops that are controlled by the second fractionary frequency clock signal and a (2x1) multiplexer, provided with a selection input terminal, in order to selectively provide either a single-bit decoded NRZ serial stream, sampled at the fractionary frequency of said first fractionary clock signal, or dual-bit decoded streams, NRZ0 and NRZ1, respectively, both sampled at the fractionary frequency of said second fractionary clock signal. The different aspects and advantages of the invention will become more evident through the following description of several important embodiments, herein incorporated by express reference and by referring to the attached drawings, wherein: Figure 1 is a block diagram of a decoder made according to the present invention; Figure 2 is a timing diagram relative to the decoder of Fig. 1; Figure 3 is a block diagram of a decoder of the invention having a "pipelined" structure capable of doubling the operating frequency for the same fabrication technology; Figure 4 is a timing diagram of the decoder of Fig. 3. With reference to the Figures 1 and 3, the shift register SR that receives the serial stream of coded data, SYNDATA , is synchronized with an extracted, base clock signal VCO, may be provided with a number of flip-flop (FF n ) greater than the number of bits handled by the decoder, which for example, in the case shown, is of 7 bits. The flip-flops in excess, relative to the Q0 and Q1 taps of the shift register SR, may be employed for other accessory functions, as is well known to a skilled person. A first combinative logic block RC1 processes the Q outputs of the seven flip-flops Q<2:8>, that is the taps relative to the seven bits handled by the decoder, and produces a first value ND0 which is fed to a first timing flip-flop A, sampled at a first fractionary clock frequency VCO/1.5. A second combinative logic network RC2 processes the bits Q5, Q6, Q7 and produces a second value ND1 which is fed to a second timing flip-flop B, which is also sampled, as the first flip-flop A, at the fractionary clock frequency VCO/1.5. Differently from single-bit NRZ decoders, the ND0 value, re-timed by the flip-flop A, is not input to the second logic network RC2 together with the second fractionary clock signal VCO/3 to produce a re-synthesized signal, on the contrary, the output stream NQ0 of the flip-flop A is fed to the input of a third flip-flop AA, which is sampled at the frequency of the second fractionary clock signal VCO/3, to produce a first, decoded, dual-bit serial signal NRZ0, at an output of the decoder. Similarly, the output signal of the second flip-flop B is fed to an input of a fourth flip-flop BB, which is also sampled at the frequency of said second fractionary clock signal VCO/3 to produce a second, decoded, dual-bit, serial signal NRZ1, at a respective output of the decoder. The two additional flip-flops AA and BB that implement the mode, whereby a pair of dual decoded output signals, sampled at the frequency of the second fractionary clock signal VCO/3, are produced, are put in evidence in the block diagram of Fig. 1, by using heavier lines in tracing them. According to an aspect of the invention, depicted in Fig. 1, the output signal NQ0 of the first timing flip-flop A, as well as the second fractionary clock signal VCO/3 are input to the second logic network RC2 in order to generated at the output thereof a re-synthisized signal ND1, as normally effected also in single-bit NRZ decoders of the prior art. Simultaneously, the first re-timed signal NQ0 is fed to an input of the third flip-flop AA, sampled at the fractionary clock frequency VCO/3, and the output of which is connected also to a first input (0) of a (2x1) output multiplexer MUX OUT. The second re-timed output signal of the flip-flop B is fed at the other input (1) of the MUX OUT multiplexer, as well as to the input of the fourth flip-flop BB, which is also sampled as the flip-flop AA at the second fractionary clock frequency VCO/3. The output stream of the flip-flop BB represents one (NRZ1) of the dual-bit decoded signals, the other one of which is selectably provided at the respective output of the decoder, through the output multiplexer MUX OUT, by selecting its 0 input. Viceversa, by effecting a different selection between the two inputs of the output multiplexer and by selecting the 1 input thereof, a single-bit decoded NRZ stream is made available at the output of the decoder. The selection of one or the other of the two possible output modes of the decoder is effected through a control input terminal (SEL) of the output multiplexer MUX OUT. The elements that implement the selection of the two different output modes of the decoder are made evident in Fig. 1 by the portions traced with heavy lines. Fig. 2 shows the timing diagrams of the decoder of Fig. 1, evidencing the differences between a single-bit decoded output serial signal (single-bit stream) NRZ and a dual-bit output signal (dual-bit stream) that is constituted by the pair of serial signals NRZ0 and NRZ1, that may be selectably output through the SEL command of the output multiplexer. An embodiment similar to the one depicted in Fig. 1, but employing a different architecture of the decoder, is shown in Fig. 3. The architecture of the decoder of Fig. 3 is substantially the architecture described in the prior European patent application No. 93830387.2, filed on September 21, 1993, by the same applicant, the description of which is herein incorporated by express reference. Also in this case, the elements that characterize the device object of the present invention are put in evidence in the block diagram by tracing them with thick lines. In both embodiments of the decoder of the invention the end user is capable of implementing a selection between a single-bit NRZ output stream or a dual NRZ0 & NRZ1 output stream by applying an appropriate command (address signal) through a dedicated pin of the device or in any other appropriate manner.

Claims: A decoder of a coded serial stream of digital data ( SYNDATA ) in dual streams of decoded data (NRZ0, NRZ1) comprising means for generating a base clock signal (VCO), synchronous with transitions of said coded serial stream; means for deriving from said base clock signal (VCO) a first fractionary clock signal (VCO/1.5), having a frequency fractionary in respect to the frequency of said synchronous base clock signal (VCO) with a frequency ratio congruent with the ratio between the number of bits of said coded stream and the number of equivalent bits of a decoded stream, and at least a second fractionary clock signal (VCO/3) having a fractionary frequency with respect to said first fractionary frequency clock signal (VCO/1.5) ; a shift register (SR) composed of a plurality of flip-flops (FFQ0,...,FFQ8), receiving said input stream of coded data ( SYNDATA ), under control of said synchronous base clocks signal (VCO) ; a first combinative-logic, decoding network (RC1) for processing n bits stored in said shift register (SR) and producing a first pre-decoded value (ND0); a first synchronizing flip-flop (A), sampled by said first fractionary clock signal (VCO1.5), receiving said first pre-decoded value (ND0); a second combinative-logic, decoding network (RC2) for combining a fractionary number of said n bits, said first pre-decoded and synchronized value (ND⊘) and said second fractionary clock signal (VCO/3) and producing a second pre-decoded value (ND1) at an output thereof; a second output flip-flop (B) receiving said second pre-decoded value (ND1), sampled by said first fractionary clock signal (VCO/1.5), characterized by comprising further a third (AA) and a fourth (BB) output flip-flop, controlled by said second fractionary clock signal (VCO/3), receiving the output stream of said first flip-flop (A) and the output stream of said second flip-flop (B), respectively, and producing two respective output streams; an output multiplexer (MUX OUT), having a first input receiving the output stream of said third flip-flop (AA), and a second input receiving the output stream of said second flip-flop (B) ; through a selection terminal of said output multiplexer (MUX OUT) either a serial stream of decoded data (NRZ) corresponding to the output (NQ1) from said second flip-flop (B) or a first serial stream (NRZ0) corresponding to the output from said third flip-flop (AA) of a dual-bit decoded data stream being selectable, a second serial stream (NRZ1) of said dual-bit decoded data stream being available from the output of said fourth flip-flop (BB). A decoder as defined in claim 1, capable of handling an input serial stream of an RLL (1,7) type.

Inventors: ALINI ROBERTO, DEMICHELI MARCO, GADDUCCI PAOLO, MOLONEY DAVID, ALINI, ROBERTO, DEMICHELI, MARCO, GADDUCCI, PAOLO, MOLONEY, DAVID
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1993
Main classification: G11B20
IPC codes: G11B20, H03M5, G06F3