Rectifying transfer gate circuit

Abstract: A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

Description: Background of the Invention The present invention relates to a rectifying transfer gate circuit, and more particularly, to a rectifying transfer gate circuit which is employed in a logic circuit operated at high speed, and application circuits thereof. Generally speaking, a logic circuit is constituted by a plurality of switching elements such as transistors and diodes. Here, a current controlled logic circuit deals with the current as a signal and a voltage controlled logic circuit deals with the voltage as a signal. The current controlled logic circuit is used in specific fields only to a limited extent, because it increases power consumption and its circuit design is more difficult than the voltage controlled logic circuit. On the other hand, voltage controlled logic circuits are widely utilized. The main components of a voltage controlled logic circuit employ field effect transistors, especially CMOS transistors, which can attain operation stability and reduce power consumption. However, the logic circuit constituted by CMOS transistors requires an additional circuit for inverting the input signal, thereby increasing the stray capacitance and line length so as to increase the signal delay time and the manufacturing cost. In DE 3441306 a logic circuit for the inverted Exclusive -OR function is described. The circuit comprises two input nodes for receiving signal currents and one output node for digital signals. The first input node is connected to a gate electrode of a first transistor, the second input node is connected to a gate electrode of a second transistor. The gate electrons of each of the input nodes are connected via level shifting diodes to the source electrode of the other of the two input nodes. The drain terminals of the two input transistors are connected with a common load transistor via at least one other transistor to an output terminal. Summary of the Invention Accordingly, it would be beneficial to provide a rectifying transfer gate circuit which is simple and can be operated in a stable state. It would also be beneficial to provide a logic circuit which is constituted by associations of a rectifying transfer gate circuit. In accordance with the present invention there is provided a rectifying transfer gate circuit comprising: first and second input nodes for receiving first and second binary logic input voltage signals, respectively; an output node for providing a binary logical output voltage signal; a first field effect transistor having a source coupled to said first input node, a gate coupled to said second input node, and a drain; a second field effect transistor having a source coupled to said second input node, a gate coupled to said first input node, and a drain coupled to the drain of said first field effect transistor; and a diode, characterised in that said diode has one end coupled directly to the drains of said first and said second field effect transistors and the other end coupled to said output node. In one embodiment of the above rectifying transfer gate circuit, the first and second field effect transistors are constituted by first and second NMOS transistors, respectively, and the drains of the first and second NMOS transistors are coupled to the cathode of the diode, and the output node is coupled to the anode of the diode. In another embodiment, the first and second field effect transistors are constituted by first and second PMOS transistors, respectively, and the drains of the first and the second PMOS transistors are coupled to the anode of the diode, and the output node is coupled to the cathode of the diode. The rectifying transfer gate circuit preferably further comprises: a reference potential source for providing a reference potential; and a conductive load coupled between the drains of the first and second field effect transistors and the reference potential source. A logic circuit according to one aspect of the present invention, comprises, in addition to the rectifying transfer gate circuit of the present invention: a reference potential source for providing a reference potential; and a first conductive load coupled between the reference potential source and the output node. In one embodiment of the above logic circuit, the first and second field effect transistors included in the rectifying transfer gate are constituted by NMOS transistors each having a drain coupled to the cathode of the diode. In another embodiment, the first and second field effect transistors included in the rectifying transfer gate are constituted by PMOS transistors each having a drain coupled to the anode of the diode. The logic circuit preferably further comprises: a second conductive load coupled between the drains of the first and second field effect transistors and the reference potential source. first, second and third field effect transistors having sources coupled to the first, second and third diodes, respectively, and gates coupled to the second, third and first input nodes, respectively, and drains commonly coupled to the output node; a reference potential source for providing a reference potential; and a conductive load coupled between the output node and the reference potential source. Here, the first, second and third field effect transistors are NMOS transistors. A carry logic circuit according to another aspect of the present invention comprises: first, second and third input nodes; an output node for providing an output signal; a first diode having an anode coupled to the first input node; a second diode having an anode coupled to the third input node; a first field effect transistor having a source coupled to the cathode of the first diode, a gate coupled to the third input node, and a drain coupled to the output node; a second field effect transistor having a source coupled to the cathode of the first diode, a gate coupled to the second input node, and a drain coupled to the output node; a third field effect transistor having a source coupled to the cathode of the second diode, a gate coupled to the second input node, and a drain coupled to the output node; a reference potential source for providing a reference potential; and a conductive load coupled between the output node and the reference potential source. Here, the first, second and third field effect transistors are preferably PMOS transistors. An adding circuit according to the present invention comprises: first and second input nodes; a carry input node for receiving a carry input signal; a sum signal output node for producing a sum signal to be obtained as the adding result; a carry output node for producing a carry signal to be obtained as the adding result; first and second field effect transistors having sources coupled to the first and second input nodes, respectively, gates coupled to the second and first input nodes, respectively, and drains coupled to each other; third and fourth field effect transistors having sources coupled to the drains of the first and second field effect transistors and the carry input node, respectively, and gates coupled to the carry input node and the drain of the first and second field effect transistors, respectively, and drains commonly coupled to the sum signal output node; a first diode having an anode coupled to the carry input node; a second diode having an anode coupled to the first input node; a fifth field effect transistor having a source coupled to the cathode of the first diode, a gate coupled to the first input node, and a drain coupled to the sum signal output node; a sixth field effect transistor having a source coupled to the cathode of the first diode, a gate coupled to the second input node, and a drain coupled to the sum signal output node; and a seventh field effect transistor having a source coupled to the cathode of the second diode, a gate coupled to the second input node, and a drain coupled to the sum signal output node. Here, the first through fourth field effect transistors are all preferably NMOS transistors. Brief Description of the Drawings The above features and other advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: FIG.1 is a circuit diagram illustrating a rectifying transfer gate circuit according to a first example useful for understanding the present invention; FIG.2 is a circuit diagram illustrating a rectifying transfer gate circuit according to a second example useful for understanding the present invention; FIG.3 is a circuit diagram illustrating a first embodiment of a rectifying transfer gate circuit according to the present invention; FIG.4 is a circuit diagram illustrating a second embodiment of a rectifying transfer gate circuit according to the present invention; FIG.5 is a circuit diagram illustrating a rectifying transfer gate circuit according to a third embodiment of the present invention; FIG.6 is a circuit diagram illustrating a fourth embodiment of a rectifying transfer gate circuit according to the present invention; FIG.7 is a block diagram illustrating a first embodiment of a logic circuit according to the present invention; FIG.8 is a block diagram illustrating a second embodiment of a logic circuit according to the present invention; FIG.9 is a cross-sectional view illustrating a first embodiment of a semiconductor structure used in realising the present invention; and FIG.10 is a cross-sectional view illustrating a second embodiment of a semiconductor structure used in realising the present invention. Detailed Description of the Invention FIG.1 is a circuit diagram illustrating a first example of a rectifying transfer gate circuit, wherein the rectifying transfer gate circuit includes input nodes I1 and I2, an output node T1, an NMOS transistor M1, and a diode D1. In FIG.1, input node I1 is coupled to the source of NMOS transistor M1, and input node I2 is coupled to the gate of NMOS transistor M1. The drain of the NMOS transistor M1 is coupled to the cathode of diode D1, and the anode of diode D1 is coupled to output node T1. Input nodes I1 and I2 receive a first logic input signal and a second logic input signal, respectively. When the second logic input signal is in the logic "high" state, NMOS transistor M1 turns on so as to transfer the first input logic input signal to the drain, and when the second logic input signal is in the logic "low" state, NMOS transistor M1 turns off so that the drain is in a high impedance state. When the potential of the output node T1 is higher than that of the drain of NMOS transistor M1 by the diode threshold voltage (e.g., 0.7V) or more, diode D1 conducts, but is otherwise "OFF." FIG.2 is a circuit diagram illustrating a second example of a rectifying transfer gate circuit, wherein the rectifying transfer gate circuit includes input nodes I3 and I4, an output node T2, a PMOS transistor M2, and a diode D2. Referring to FIG.2, input node I3 is coupled to the source of PMOS transistor M2, and input node I4 is coupled to the gate of PMOS transistor M2. The drain of PMOS transistor M2 is coupled to the anode of diode D2, and the cathode of diode D2 is coupled to output node T2. Input nodes I3 and I4 receive a first logic input signal and a second logic input signal, respectively. When the second logic input signal is in the logic "low" state, PMOS transistor M2 turns on so as to transfer the first logic input signal to the drain, and otherwise turns off so that the drain of PMOS transistor M2 is in a high impedance state. Diode D2 conducts when the potential of the drain of PMOS transistor M2 is higher than the potential of output node T2 by the diode threshold voltage or more, and therwise turns "OFF." FIG.3 is a circuit diagram illustrating a first embodiment of the rectifying transfer gate circuit according to the present invention, wherein the rectifying transfer gate circuit includes input nodes I5 and I6, an output T3, NMOS transistors M3 and M4, and a diode D3. In FIG.3, the source of NMOS transistor M3 is coupled to input node I5, the gate of NMOS transistor M3 is coupled to input node I6, and the drain of NMOS transistor M3 is coupled to the cathode of diode D3. Correspondingly, the source of NMOS transistor M4 is coupled to input node I6, the gate of NMOS transistor M4 is coupled to input node I5, and the drains of NMOS transistors M3 and M4 are commonly coupled to the cathode of diode D3. Input nodes I5 and I6 receive a first logic input signal and a second logic input signal, respectively. When the second logic input signal is "high," NMOS transistor M3 turns on so as to transfer the first logic input signal to the drain of NMOS transistor M3, and when the first logic input signal is "high," NMOS transistor M4 turns on so as to transfer the second logic input signal to the drain of NMOS transistor M4. Here, the drain of NMOS transistor M3 and the drain of NMOS transistor M4 are tied together, and the logic states thereof will be summarized in the following Table 1, according to the first and second logic input signals. first logic input signal second logic input signal drain state "high" "high" "high" "high" "low" "low" "low" "high" "low" "low" "low" high impedance Diode D3 turns "ON" when the potential of the common drain is lower than the potential of output node T3 by the diode's threshold voltage or more, and otherwise turns "OFF." FIG.4 is a circuit diagram illustrating a second embodiment of the rectifying transfer gate circuit according to the present invention, wherein the rectifying transfer gate circuit includes input nodes I7 and I8, an output node T4, PMOS transistors M5 and M6, and a diode D4. In FIG.4, the source of PMOS transistor M5 is coupled to input node I7, the gate of PMOS transistor M5 is coupled to input node I8, and the drain of PMOS transistor M5 is coupled to the anode of diode D5. Correspondingly, the source of PMOS transistor M6 is coupled to input node 18, the gate of PMOS transistor M6 is coupled to input node I7, and the drains of PMOS transistors M5 and M6 are commonly coupled to the anode of diode D4. Input nodes I7 and I8 receive a first logic input signal and a second logic input signal, respectively. When the second logic input signal is "low," PMOS transistor M5 turns on so as to transfer the first logic input signal to the drain of PMOS transistor M5, and when the first logic input signal is "low," PMOS transistor M6 turns on so as to transfer the second logic input signal to the drain of PMOS transistor M6. Here, the drains of PMOS transistors M5 and M6 are tied together, and the logic states thereof will be summarized in the following Table 2, according to the first and the second logic input signals. first logic input signal second logic input signal drain state "high" "high" high impedance "high" "low" "high" "low" "high" "high" "low" "low" "low" Diode D4 turns "ON" when the potential of the common drain is higher than the potential of output node T4 by the diode's threshold voltage or more, and otherwise turns "OFF." FIG.5 is a circuit diagram illustrating a third embodiment of the rectifying transfer gate circuit according to the present invention, wherein the rectifying transfer gate circuit includes input nodes I9 and I10, an output node T5, NMOS transistors M7 and M8, a reference potential source V CC , a conductive load R1, and a diode D5. In FIG.5, the source of NMOS transistor M7 is coupled to input node I9, the gate of NMOS transistor M7 is coupled to input node I10, and the drain is coupled to the anode of diode D5. Correspondingly, the source of NMOS transistor M8 is coupled to input node I10, the gate of NMOS transistor M8 is coupled to input node I9, and the drains of NMOS transistors M7 and M8 are commonly coupled to the anode of diode D5. The cathode of diode D5 is coupled to output node T5. The conductive load R1 is coupled between the common drain of NMOS transistors M7 and M8 and the reference potential source V CC . Diode D5 turns "ON" when the potential of the common drain of NMOS transistors M7 and M8 is higher than the potential of output node T5 by the diode's threshold voltage or more, and otherwise turns "OFF." This rectifying transfer gate circuit further includes the conductive load R1 between the common drain of NMOS transistors M7 and M8 and the reference potential source V CC (typically, the logic "high" level), resulting in stabilizing the open state of NMOS transistors M7 and M8 so as to increase the speed of the response. Therefore, the capability of these circuit is varied in accordance with the electrical characteristics of the conductive load. As the conductive load, there are a resistor, a depletion field effect transistor and a constant current source. Here, the constant current source is preferably used. FIG.6 is a circuit diagram illustrating a fourth embodiment of the rectifying transfer gate circuit according to the present invention, wherein the rectifying transfer gate circuit includes input nodes I11 and I12, an output node T6, PMOS transistors M9 and M10, a reference potential source V SS , a conductive load R2, and a diode D6. In FIG.6, the source of PMOS transistor M9 is coupled to input node I11, the gate of PMOS transistor M9 is coupled to input node I12, and the drain of PMOS transistor M9 is coupled to the cathode of diode D6. Correspondingly, the source of PMOS transistor M10 is coupled to input node I12, the gate of PMOS transistor M10 is coupled to input node I11, and the drains of PMOS transistors M9 and M10 are commonly coupled to the cathode of diode D6. The conductive load R2 is coupled between the reference potential source V SS (typically, ground) and the common drain of PMOS transistors M9 and M10, and output node T6 is coupled to the anode of diode D6. Diode D6 turns "ON" when the potential of output node T6 is higher than the potential of the common drain of PMOS transistors M9 and M10 by the diode's threshold voltage or more, and otherwise turns "OFF." This rectifying transfer gate circuit further includes the conductive load R2 between the common drain of PMOS transistors M9 and M10 and the reference potential source V SS , resulting in stabilizing the open state of PMOS transistors M9 and M10 and increasing the speed of the response. FIG.7 is a block diagram illustrating a first embodiment of the logic circuit according to the present invention, which includes a reference potential source V CC for providing a potential typically corresponding to the logic "high" level, an output node T7, a conductive load R3 coupled between the reference potential source V CC and output node T7, and a plurality of two-input rectifying transfer gate circuits 501, 502 and 503. In FIG.7, the two-input rectifying transfer gate circuits 501, 502 and 503 each correspond to either the rectifying transfer gate circuit shown in FIG.3 or that shown in FIG.6. Here, if the circuits 501, 502 and 503 correspond to FIG.3, the output T7 is: (1) with any one pair of inputs to the two-input rectifying transfer gate circuits being different from each other, in other words, one bit is "high" and the other bit is "low," then, the output node is a logic "low," and otherwise (2), the output node is a logic "high." Meanwhile, if the circuits 501, 502 and 503 correspond to FIG.6, the output T7 is: (1) with any one pair of inputs of the two-input rectifying transfer gate circuits being both logic "low," then, the output node is a logic "low", and otherwise (2), the output node is a logic "high." FIG.8 is a block diagram illustrating a second embodiment of the logic circuit according to the present invention, which includes a reference potential source V SS typically corresponding to ground, an output node T8, a conductive load R4 coupled between the reference potential source V SS and output node T8, and a plurality of two-input rectifying transfer gate circuits 601, 602 and 603. Referring to FIG.8, the two-input rectifying transfer gate circuits 601, 602 and 603 each correspond to either the rectifying transfer gate circuit depicted in FIG.4 or that depicted in FIG.5. Here, if the circuits 601, 602 and 603 correspond to FIG.4, the output T8 is: (1) with any one pair of inputs of the two-input rectifying transfer gate circuits being different from each other, in other words, one bit is "high" and the other bit is "low," then, the output node is a logic "high," and otherwise (2), the output node is a logic "low." Meanwhile, if the circuits 601, 602 and 603 correspond to FIG.5, the output T8 is: (1) with any one pair of inputs of the two-input rectifying transfer gate circuits being both logic "high," then, the output node is a logic "high," and otherwise (2), the output node is a logic "low". The rectifying transfer gate circuit as described above, can be simply implemented by forming a field effect transistor and a diode in separate regions and connecting one with the other via a conductive line. However, this structure has a problem in that, as the size of the diode is increased, the required area is increased together with an increase in stray capacitance, so as to reduce operation speed. Therefore, to increase the integration density and simultaneously reduce the stray capacitance, it is desirable to implement a semiconductor device such as that shown in FIG.9 or FIG.10. FIG.10 is a cross-sectional view illustrating a first embodiment of a semiconductor structure used in realising the present invention. In FIG.9, to define an active region and an isolating region, a field insulating layer 302 is selectively formed on a semiconductor substrate 301. Doping regions 303, 304 and 307 are formed in the active region and apart from one another. Here, doping regions 303, 304 and 307 all have the same conductivity, a transistor channel 305 is formed between doping regions 303 and 307, and a transistor channel 306 is formed between doping regions 307 and 304. In doping region 307, a doping region 308 having the opposite conductivity to that of doping region 307 is formed. A gate electrode 311 is formed over the transistor channel 305, with a gate insulating film disposed therebetween, and a gate electrode 312 is formed over the transistor channel 306, with a gate insulating film disposed therebetween. An electrode layer 313 is formed on the surface of doping region 303, and an electrode layer 315 is formed on the surface of doping region 304. Over gate electrodes 311 and 312, an insulating layer 316 having openings for exposing electrode layers 313 and 315 and doping region 308 is formed. An electrode layer 314 is formed on doping region 308, where electrode layer 314 is electrically isolated from gate electrodes 311 and 312 by insulating layer 316. In this structure, one transistor included in the rectifying transfer gate circuit shown in FIG.3 and FIG.4 is constituted by doping region 303, transistor channel 305, doping region 307, gate insulating film 309 and gate electrode 311, and the other transistor is constituted by doping region 304, transistor channel 306, doping region 307, gate insulating film 310 and gate electrode 312. Here, doping region 307 serves as the common drain of two MOS transistors. In addition, doping regions 307 and 308 constitute the diode. The output node of the rectifying transfer gate circuit shown in both FIG.3 and FIG.4 is constituted by electrode layer 314, and two input nodes are constituted by electrode layers 313 and 315, respectively. As shown in the drawings, the diode included in the rectifying transfer gate circuit is constituted by the doping region serving as the common drain and the doping region adjacent thereto, so as not to require additional area for forming the diode. FIG.10 is a cross-sectional view illustrating a second embodiment of a semiconductor structure used in realising the present invention. Referring to FIG.10, a doping region 401 is formed on a semiconductor substrate 400 and a doping region having the opposite conductivity to that of doping region 401 is formed in the doping region 401. An interlayer insulating layer 403 having an opening for exposing the surface of doping region 402 is formed on the surfaces of doping regions 401 and 402 and semiconductor substrate 400. A semiconductor layer is formed on a conductive material layer 404, for forming circuit elements. In the semiconductor layer, doping region 407, transistor channel 405, doping region 405, transistor channel 406 and doping region 409 are sequentially and laterally arranged, whereby the doping region 408 is disposed on conductive material layer 404. Gate electrode 413 is formed over transistor channel 405 with a gate insulating film disposed therebetween and gate electrode 414 is formed over transistor channel 406 with a gate insulating film disposed therebetween. In addition, electrode layers 410, 411 and 412 are formed in doping regions 407, 408 and 409, respectively. In this structure, doping regions 401 and 402 constitute a diode, doping region 408 constitutes the common drain of two MOS transistors, and doping regions 407 and 409 respectively constitute the sources of two MOS transistors. Conductive material layer 404 serves as the conductive line for connecting the common drain of MOS transistors with the diode, and electrode layers 410, 411 and 412 constitute the two input nodes and the output node, respectively. The gate electrode in the semiconductor device shown in FIG.9 and FIG.10, can be implemented by comprising a silicide layer. Here, a silicide layer made from a metal such as Ti, Mo or W can be utilized for the NMOS transistor, while a silicide layer made from a metal such as Zr can be utilized for the PMOS transistor. As described above, the rectifying transfer gate circuit according to the present invention can be implemented for a small number of circuit elements and an undesired circulating current in its application circuit can be prevented. Therefore, the signal delay is decreased and the manufacturing cost is reduced. Moreover, in the application circuit of the rectifying transfer gate circuit, malfunctions due to the undesired circulating current is prevented. While the invention has been described in conjunction with a few specific embodiments, it is evident to those skilled in the art that many alternatives, modifications and variations will be apparent in light of the foregoing description. Moreover, the source and the drain of the MOS transistors can be exchanged and reach the equivalent circuit operation. Accordingly, the present invention is intended to embrace all such alternative modifications and variations as fall within the scope of the appended claims. Also, the drain and the source in the appended claims can be interpreted interchangeably.

Claims: A rectifying transfer gate circuit comprising: first and second input nodes (I5, I6; I7, I8; I9, I10; I11, I12) for receiving first and second binary logic input voltage signals, respectively; an output node (T3, T4, T5, T6) for providing a binary logical output voltage signal; a first field effect transistor (M3, M5, M7, M9) having a source coupled to said first input node, a gate coupled to said second input node, and a drain; a second field effect transistor (M4, M6, M8, M10) having a source coupled to said second input node, a gate coupled to said first input node, and a drain coupled to the drain of said first field effect transistor; and a diode (D3, D4, D5, D6), characterised in that said diode has one end coupled directly to the drains of said first and said second field effect transistors and the other end coupled to said output node. A rectifying transfer gate circuit according to claim 1, wherein said first and second field effect transistors are constituted by first and second NMOS transistors (M3, M4), respectively, and the drains of the first and second NMOS transistors (M3, M4) are coupled to the cathode of said diode (D3), and said output node (T3) is coupled to the anode of said diode (D3). A rectifying transfer gate circuit according to claim 1, wherein said first and second field effect transistors are constituted by first and second PMOS transistors (M5, M6), respectively, and the drains of the first and second PMOS transistors (M5, M6) are coupled to the anode of said diode (D4), and said output node (T4) is coupled to the cathode of said diode (D4). A rectifying transfer gate circuit according to claim 1, further comprising: a reference potential source (V cc , V ss ) for providing a reference potential; a conductive load (R1, R2) coupled between the drains of said first and second field effect transistors and said reference potential source. A rectifying transfer gate circuit according to claim 4, wherein said first and second field effect transistors are constituted by first and second NMOS transistors (M7, M8), respectively, the drains of the first and second NMOS transistors (M7, M8) are coupled to the anode of said diode (D5), and said output node (T5) is coupled to the cathode of said diode (D5). A rectifying transfer gate circuit according to claim 4, wherein said first and second field effect transistors are constituted by first and second PMOS transistors (M9, M10), respectively, the drains of the first and second PMOS transistors (M9, M10) are coupled to the cathode of said diode (D6), and said output node (T6) is coupled to the anode of said diode (D6). A logic circuit comprising a rectifying transfer gate circuit according to claim 1, further comprising: a reference potential source (V cc , V ss ) for providing a reference potential; and a first conductive load (R3, R4) coupled between said reference potential source and said output node. A logic circuit according to claim 7, wherein said first and second field effect transistors included in said rectifying transfer gate are constituted by NMOS transistors each having a drain coupled to the cathode of said diode. A logic circuit according to claim 7, wherein said first and second field effect transistors included in said rectifying transfer gate are constituted by PMOS transistors each having a drain coupled to the anode of said diode. A logic circuit according to claim 7, further comprising: a second conductive load coupled between the drains of said first and second field effect transistors and said reference potential source. A logic circuit according to claim 10, wherein said first and second field effect transistors included in said rectifying transfer gate are constituted by NMOS transistors each having a drain coupled to the anode of said diode. A logic circuit according to claim 10, wherein said first and second field effect transistors included in said rectifying transfer gate are constituted by PMOS transistors each having a drain coupled to the cathode of said diode.

Inventors: NAKASHIMA TAKASHI, NAKASHIMA, TAKASHI
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1993
Main classification: H03K19
IPC codes: H01L27, H03K19, H01L21, H03K17, G06F7