CONFIGURABLE LOGIC NETWORKS

Abstract: A programmable logic device (PLD) and configurable logic network in which one or more logic combination networks (LCN) each receives logic inputs from two or more PLDs (PLD1, PLD2) and generates logic outputs (O, P) which can then be used to provide inputs to programmable logic networks (POR, UCL,...) for implementing logic functions of various types and functionality. Each programmable logic device includes an AND logic array (FAND...) having inputs for receiving signals (Ax, Bx) and generating product term output signals and an OR logic array (OG...) having inputs for receiving signals and generating sum term output signals (OF...). One or both of the AND logic and OR logic arrays is programmable and the logic arrays are interconnected to apply output signals from one of them as input signals to the other one, the output from which provides PLD output signals. The logic combination networks may be fixed logic networks (LCN100) or programmable logic function generators (UBLFG20, UBFF2P) that produce outputs controlled by a set of programmable inputs (CNx, DNx) to the generator as a function of the logic inputs (O, P) received from the programmable logic devices.

Description: PROGRAMMABLE LOGIC DEVICES AND CONFIGURABLE LOGIC NETWORKS TECHNICAL FIELD This invention relates to programmable logic devices (PLD) and to configurable logic networks employing PLDs. BACKGROUND OF THE INVENTION U.S. Patent No. 4,872,137 includes disclosure of a folded programmable logic device employing a triangular geometry, using an AND-gate array in which reprogrammable control circuits (RCC) are used to select and control programmable inputs to the AND gates. The RCC design is based on a transmission gate controlled by the user programmable content of a 1-bit shift register. The triangular geometry permits more effective use of semiconductor chip area to implement folded programmable logic devices than use of rectangular arrays employing previously proposed folding techniques. However, while this PLD design is advantageous in terms of versatility of application, operating speed and optimization of AND- gate utilization, it would be desirable to achieve a PLD structured to enable even greater versatility in terms of ability to process more complex Boolean logic inputs. Also, it is desirable to facilitate implementation of user programmable complex logic functions. DISCLOSURE OF THE INVENTION A programmable logic device embodying the present invention includes a plurality of groups of AND logic function gates with the AND logic function gates in each group having respective outputs connected to inputs of an OR logic function gate for that AND logic function gate group. Each AND logic function gate group has one or more individual output AND logic function gates with inputs that are programmable by individually programmable logic function generators (PLFG) of a set of PLFGs operatively associated with that AND gate group. In a preferred embodiment, each PLFG has a plurality of logic input pairs, each PLFG in a set receiving the same logic input pairs. Logic signals are applied as inputs to an AND logic function output gate for that PLFG according to programmable inputs to the PLFG as functions of logic input pairs of that PLFG. For different ones of said AND logic function gate groups, there are different numbers of logic input pairs in the respective logic input pair sets. In this manner, a folded PLD structure may be provided that is user programmable by selection of the control inputs of the PLFGs as a function of the logic inputs to the PLFGs, to provide varied as well as complex logic functions. As integration of complex electronic systems at the single chip and single wafer level increases, embodiments of the invention permit incorporation of programmable logic functions typically required in such systems directly on the system chip or wafer. Alternatively, the programmable logic devices may be provided separately as a single chip or wafer. For each one of the logic input pairs for a PLFG, an individual programmable cell may be provided having a set of user programmable control inputs from which an output signal is generated as a function of the logic input pair to that programmable cell. The control inputs conveniently may be provided by values stored in a programmable cells which may be provided by one or more volatile or non-volatile memories. In this manner, it is possible to provide an output from a cell selected from any of up to sixteen different logic functions. However, programmable logic devices embodying the invention also may be structured based on sets of more than two logic inputs. The use of logic input pairs is preferred in that it permits a less complex programmable cell designed to be used. Advantageously, the number of logic input pairs in the respective pluralities of logic input pair sets differs, across a succession of AND-gate groups. In this manner, a programmable logic device may be structured having a layout approximating a right-triangle. The OR logic function gates and AND-gate groups may be disposed in columns along one side, either one of the right-angled sides or the hypotenuse, of said triangle. Alternatively, the OR logic function gates may be embodied within the PLFG array itself. Such generally triangular shaped PLD arrays may be grouped together to define geometries which enable layout of such groups on a semiconductor chip or wafer in a manner maximizing functional utilization of the available chip surface area and improving cost effective production of such arrays. For example generally rectangular, hexagonal or trapezoidal groupings may advantageously be utilized. Current CMOS fabrication processing may advantageously be used to implement PLDs embodying the invention. The invention also incudes a configurable logic network having a plurality of Programmable Logic Devices (PLD) with PLD output signals from different ones of said plurality of PLDs applied to logic combination means to generate at least one output logic signal from said configurable logic network. The PLDs may be constructed as described in the preceding paragraphs or may be conventional programmable logic arrays (PLAs) . Each programmable logic device comprises an AND logic array having inputs for receiving signals and generating product term output signals and an OR logic array having inputs for receiving signals and generating sum term output signals, at least one of said logic arrays being programmable. Output signals are fed from one of said AND and OR logic arrays as input signals to the other one of said AND and OR logic arrays, said other one of the AND and OR logic arrays providing PLD output signals. Thus, the PLD output may be in the form of sums of product terms, or products of sum terms. Either or both of the AND and OR logic arrays is programmable. Alternatively, the PLD output may be constructed as products of sums. The logic combination means may produce a plurality of output logic signals from said Configurable Logic Network (LCN) which advantageously further includes means for deriving logic function signals from a selected group or groups said of output logic signals under control of signals which may be programmable. Although in basic implementations of a configurable logic network embodying the the logic combination means may receive output signals from two PLDs, output signals from three or more PLDs could be utilized as inputs for the logic combination means. Sets of output signals from different groups of two or more PLDs may be used as inputs to different logic combination networks to produce multiple different output signals from the configurable logic network. The logic combination means may suitably include a plurality of logic function generators (PLFG) in which each PLFG has a group of logic gates connected to receive first inputs comprising PLD output signals from said plurality of PLDs, and second inputs comprising respective sets of user programmable signals. The group of logic gates is connected to apply inputs to an output gate of that PLFG determined according to said first and second inputs, whereby the output gates of said plurality of PLFGs provide respective output logic signals (0,P) from the configurable logic network. BRIEF DESCRIPTION OF THE DRAWINGS By way of example, embodiments of the invention will be described in greater detail with reference to the drawings, in which: FIGURE 1 illustrates the overall arrangement of an exemplary implementation of a PLD embodying the invention; FIGURE 2 shows part of FIGURE 1 in more detail; FIGURE 3 shows the logic design of a programmable cell utilized in the PLD of FIGURE 1; FIGURES 4-15 depict implementations of programmable logic function generators used in FIGURE 1; FIGURES 16 and 17 depict how triangular arrays as illustrated by Fig 1 can be utilized to form rectangular, hexagonal and part-hexagonal arrays; FIGURES 18-23 depict various logic networks using PLD outputs to control more complex logic functions; FIGURE 24 is a block diagram of a logic system integrated circuit incorporating folded PLDs embodying the invention; FIGURES 25-30 depict various interconnections between PLD outputs to provide more complex logic functions; FIGURE 31 depicts a combinatorial network which can implement counting, addition and shifting with ripple- style carry propagation, the execution of which is controlled by the PLD outputs; FIGURE 32 depicts a combinatorial circuitry to implement a carry lookahead style adder controlled by the outputs of the PLD; and FIGURE 33 is a block diagram of a configurable logic network suitable for implementing logic functions by use of interconnections as described with reference to Figures 25-30. BEST MODES FOR CARRYING OUT THE INVENTION In the following description, relevant features of a basic form of PLD design particularly suitable for use in implementing embodiments the invention will be provided together with various circuit arrangements for utilizing logic outputs from one or more PLDs to enable realization of a wide variety of complex logic operations in a configurable logic network. However, embodiments of the invention may also be realized using conventional programmable devices such as, for example, PLAs in which an array of AND gates produces selected product terms of logic input signals, the product terms fed as inputs to an OR gate array which produces sums of product terms as outputs from the PLA. Alternatively, PLAs may be used in which selected sum terms of logic input signals are fed from an OR gate array which produces products of sum terms as PLA outputs. Either or both of the AND and OR gate arrays may be programmable as known in the art. In addition, the AND or the OR gate arrays may employ folding techniques as known in the art. Products of sums is another technique wherein the role of AND and OR gates are reversed. The logic operations are diverse and may be controlled on the basis of programmable signal values stored in one or more programmable memories, which may be volatile or non-volatile memories, suitably of the ROM, PROM, EPROM, EEPROM or RAM variety. Depending on the memory type, mask programming at the factory may be employed or user programmation in the field which permits greater flexibility. While, for simplicity, the description will be made in terms of positive logic function implementations using AND and OR gates, other implementations are possible, in particular by NOR, NAND and INVERTER gates as when the PLD is fabricated using CMOS technology. Thus, references to "AND logic function" and "OR logic function" contemplate both positive logic and negative logic implementations. Referring to Figures 1-15, FIGURES 1 and 2 show in outline form a preferred folded PLD device employing a group of OR gates OG12..0G1 each of which receives logic product term inputs from respective subgroups of AND gates SGA12..SGA1. Each subgroup comprises four AND gates AG (FIGURE 2) . In each subgroup, all four AND gates receive user programmable inputs derived from up to twelve logic input pairs A0B0..A11B11. The programmable inputs for the AND-gate subgroups SGA12..SGA1 are provided by respective sets of programmable logic function generators (PLFG) FAND24, FAND22, FAND20, ... FAND4, FAND2, each set comprising four PLFGs providing respective inputs to the four AND gates AG in the associated subgroup SGA. Each PLFG FAND24 provides logic function inputs to an individual AND gate AG in the AND-gate subgroup SGA12, derived from all twelve logic input pairs A0B0..A11B11. The PLFG FAND22 provides logic function inputs to the AND-gate subgroup SGAll derived from eleven logic input pairs AlBl..AllBll. The PLFG FAND10 provides logic function inputs to the AND-gate subgroup SGA10 derived from ten logic input pairs A2B2..AllBll. The number of logic input pairs from which the logic function inputs for the remaining AND-gate subgroups are derived decreases in this manner in an ordered sequence so that the PLFGs FAND4 and FAND2 provide logic function input pairs to the AND-gate subgroups SGA2 and SGAl derived from two pairs A10B10..AllBll and one pair AllBll, respectively, of the logic inputs AOBO..AllBll. Thus, in sequence, the PLFGs FAND2 to FAND24 comprise AND gate function arrays having increasing numbers of inputs, or conceptionally, the inputs increase in width. In this context, for convenience of description, the PLFGs FAND will sometimes be referred to as having the same or different width, or as narrower or wider. As indicated in FIGURE 1, the resultant PLD array can be physically laid out on a semiconductor chip in the approximate form of a right-triangle, the OR gates OG1..0G12 may be located at one of the right-angled sides alongside the AND-gate subgroups SGA1..SGA12, and the area occupied by the PLFG arrays bounded by the other two sides of the triangle. Alternatively, the OR gates could be disposed at selected locations within the AND gate sub-groups. As will be discussed later, such a triangular arrangement facilitates PLD layouts in a manner that results in more efficient utilization of chip area. The use of four PLFGs in each set providing inputs for four AND gates AG in a subgroup SGA is not essential but rather a matter of design convenience. Also, each set of PLFGs need not have an identical number of PLFGs; some may have as few as one PLFGs while others may have two, three, four or more. In addition, disposition of the PLFG sets in a triangular array, although often advantageous, is not essential and folding may also be achieved by other arrangements and sequences. Furthermore, instead of individual sets of PLFGs, the sets, or at least some of them, could be arranged in groups, with the PLFGs sets in each group all receiving the same set of logic input pairs. FIGURES 4-15 illustrate examples of the structure and functionality of the PLFGs FAND24..FAND2 each of which comprises one or more programmable cells the design of which is shown in FIGURE 3. The programmable cell PC2 includes four AND gates CA0..CA3 the outputs of which are connected as inputs to an OR gate CO providing the logic function output F(A,B) from the cell. The cell also has four column lines CL0..CL3 respectively connected to one input of the AND gates CA0..CA3, and four row lines RL0..RL3 respectively connected to the other input of the AND gates CA0..CA3. An input generator IG receives logic signal input pairs A and B as inputs from which it generates the minterm logic signals A&B, A*&B, A*&B*, A&B*. These logic signals are applied to the column lines CL0..CL3 respectively, while input signals E00, E10, Ell, E01 are applied to the respective row lines RL0..RL3, advantageously by connecting the row lines to outputs from a user programmable volatile or non-volatile memory MEM storing the signals E00,..E10. Thus, the generated signal F(A,B) from the OR gate CO of the programmable cell derived from the signals E00,..E01 determines the response F(A,B) to the logic input combination A,B. This implements the sixteen logic functions of the two logic input variables A,B. For convenience of comprehension, this programmable cell will subsequently be identified by the reference PC2 denoting that its output is determined by a fully decoded pair of logic inputs. The combined programmable cell PC2 and input generator IG will be referred to as a Universal Boolean Function Generator or "UBFG." Conveniently, the memory MEM has sufficient storage capacity to store signals providing the inputs E00..E11 for the programmable cells in all the PLFGs of the PLD. MEM may comprise more than one collection of signals E00...E11, which may ' be selected by shared controls externally generated. FIGURES 4-15 depict PLFGs FAND2 .. FAND24 which employ various combinations of programmable cells PC2 for generating logic function outputs F2 .. F24, respectively derived by increasing numbers of logic input pairs from the sequence A0B0 .. AllBll (for convenience indicated as ABO .. ABU) applied to the PLFGs. Thus, while the PLFG FAND2 depicted in FIGURE 4 generates an output based on a single logic input pair ABll, the PLFG FAND24 generates a logic function output based on all twelve logic input pairs ABO-11. FIGURES 4-7 depict PLFGs FAND2..FAND8 having output AND gates LC which receive inputs from one, two, three and four programmable cells PC2, respectively and generate output logic functions F2,F4,F6 and F8. Each AND gate LC each has four inputs and any of those inputs not connected to a programmable cell PC2 is held at a logic 1 level. The programmable cells PC2 of the PLFGs FAND2 - FAND8 receive logic pair inputs from their associated input generators IG as indicated below: PLFG LOGIC INPUTS TO GATE LC FAND2 1 1 1 ABll FAND4 1 1 AB10 ABll FAND6 1 AB9 AB10 ABll FAND8 AB8 AB9 AB10 ABll It will be appreciated that to continue to connect individual programmable cell outputs directly to individual inputs of the output gates LC of the PLFGs would significantly increase the structural complexity of the gates LC as the number of logic input pairs associated with that PLFG increases. Thus, for example, the PLFG FAND24 would require an output AND gate having twelve inputs. In order to limit the number of inputs required for the output AND gates LC of the PLFGs FAND10 - FAND24, some or all of those inputs are derived from selected PLFGs structured according to FAND2-FAND8 with appropriate changes in logic input pairs. In this manner, it is possible to employ output AND gates LC having three inputs in each of the PLFGs FAND10 - FAND24 as shown in FIGURES 8-15. Thus, for example, the PLFG FAND20 depicted in FIGURE 13 is shown as employing two PLFGs having an FAND8 structure (FIGURE 7) and receiving logic input pair sets AB8-11 and AB4-7, respectively, together with a PLFG having a FAND4 structure (FIGURE 5) which receives a logic input pair set AB2-3. This is not necessary in terms of logic, but may facilitate implementation in certain semiconductor technologies including CMOS. The programmable logic device configuration illustrated above is exemplary only. The number of rows of PLFGs, as well as the number of logic input pairs, could be fewer or greater. Further, the number of PLFGs in each rows may be fewer or greater than the four sets illustrated. The particular selection of PLFGs FAND2- FAND8 used in implementation of the PLFGs FAND10-FAND24 is not unique and other combinations than those illustrated could be used. Also, the number of inputs for the output AND gates LC is a matter of design choice and implementation. Additionally, although the AND gates AG in each of the AND gate subgroups SGA12-SGA1 are shown as four-input gates for ease of illustration, fewer or greater numbers of inputs could be used according to particular design implementations. Also, rather than two input function generation, 1, 2, 3 or mroe input function generators could be employed instead of PC2's. The PLD thus far described is seen to offer considerable versatility in complexity of logic functions that may be implemented because the basic logic input pair functionalities that can be achieved by each and every one of the programmable cells PC2 can be individually and independently user programmed by the control inputs E00, E10, Ell, E01 of each programmable cell. As previously mentioned, these control inputs for the programmable cells of all the PLFGs may be stored in a common user programmable volatile or non-volatile memory. Storage can be controlled by a relatively small number of signals resulting in significantly lower semiconductor chip surface area overhead. Multiple collections of E's may be stored in each PC2. The selection of which collection controls PC2 woud be made by a small number of global signals. The use of two logic input programmable cells PC2 as described above to implement the programmable logic function generators in the programmable AND logic gate array is significantly advantageous compared with implementation of AND gate arrays in conventional programmable logic devices. For example, a conventional programmable logic device may support the following logic functions of two logic inputs A, B: 0, 1,A,B,A*,B*,A&B,A*&B,A&B*,A*&B*. However, by employment of a programmable cell PC2 in a PLD it has 1 -. been found possible to support, in addition, the following logic functions: A&B* or A*&B(XOR); A&B or A*&B* (XNOR) ; A or B; A or B*; A* or B; A* or B*. The resultant advantage may be appreciated by considering the comparison of two 3-bit logic values using PLD embodying the invention and employing PC2 cells as described above, and a conventional PLD. In a conventional device, eight different comparisons would need to be carried out to determine equality between the compared values, wherein using PC2 cells in an embodiment of the convention, equality could be determined using three PC2 cells in one PLFG: Eq = (A3 XNOR B3) & (A2 XNOR B2) & (Al XNOR Bl) In an alternative embodiment of the invention, programmable cells using logic input sets of more than two logic signals could be used, but with greater complexity of the cell structure. For example, for three inputs, eight gates CA and eight programmable inputs would be required whereas for four logic inputs, sixteen AND gates CA and sixteen programmable inputs would be required. Likewise, corresponding increases in gates in the IG array would be required. In general, for n logic inputs, 2 AND gates with corresponding logic input signals and programmable inputs would be necessary. The invention thus enables a PLD to be constructed using fewer AND gates in the AND gate array than in a conventional programmable logic device, for implementing a particular level of functional complexity thereby permitting faster operation. The triangular configuration of the PLD array previously referred to enables a multiplicity of array blocks to be laid out and integrated on a semiconductor chip in a manner enhancing chip area utilization and enabling a more cost effective single chip solution for applications requiring multiple conventional PLDs. For example, as shown in Figure 16, pairs of triangular arrays PLDA and PLDB can be aligned to define rectangular blocks. Alternatively, as shown in Figure 16, a rectangular array may be constructed using three PLDs, PLDA, PLDB and PLDC having interleaved sets of PLFGs. In addition, hexagonal and trapezoidal (half-hexagonal) blocks can be achieved by layouts of triangular arrays as indicated in Figure 17. Figure 17 also depicts other ways in which PLDs embodying the invention may be shaped and arranged to form overall rectangular arrays. In this manner, wafer scale integration of many folded PLD arrays embodying the invention may be achieved, with signals for the user programmable inputs E00..E11 of the PLFGs for all of the PLDs conveniently stored in a common, volatile or non-volatile memory integrated on the same semiconductor chip, if so desired. Thus, not only is system level chip integration facilitated but in addition, minor or major modifications in the logic functions implemented by some or all of the PLDs can readily be implemented in the field by user programmation of the PFLG control inputs. Such user programmation is particularly facilitated by storage of the control input values in on-chip programmable memory. Additional versatility can be obtained and also still more complex user programmable configurations, by using the outputs from the OR gates OG of a PLD from which are derived logic inputs to additional programmable Boolean function generators. Examples of such arrangements will be described with reference to FIGURES 18 - 24. In each of those figures, four OR gates OGk, OG1, OGm and OGn, providing ORed outputs from corresponding width FAND arrays of a PLD are depicted by way of example. However, the OR gates could be selected from any two or more FAND arrays of a PLD as required. Also, different sets of OR gates OG could be used to for derivation of logic inputs to different Boolean function generators. The arrangements to be described with reference to FIGURES 18- 24 may be employed with the PLD as described with reference to FIGURES 1-15 as well as individual PLDs in arrangements as shown in Figures 16 and 17. FIGURE 18 depicts several different user programmable control logic circuits UCLl, UCL2, UCL3, and UCL4 to which, by way of example, the logic outputs from OR gates OGk, OG1, OGm and OGn are connected to generate more complex logic outputs. The circuits UCLl - UCL4 are all shown connected to the outputs of the same OR gates OG for convenience of description. In practice, different groups of OR gates from one or more PLD could serve as the inputs to differing UCL circuits. The control logic circuit UCLl comprises a programmable input OR gate circuit POR having four AND gates GAl connected to receive the respective inputs OFk, OF1, OFm and OFn, together with an OR gate GOl the inputs of which are supplied by the AND gates GAl. The AND gates GAl also receive respective selected control input signals OC1..0C4 which may be generated by volatile or nonvolatile memory. The OR gate GOl produces an output signal U = UFk&OCl OR OF1&OC2 OR OFm&OC3 OR OFn&OC4. The control logic circuits UCL2, UCL3 and UCL4 each contains two or more programmable input OR gate circuits POR which have the same configuration as in the control logic circuit UCLl, except that the control inputs OC1..0C4 can be individually selected for each circuit POR. The control logic circuit UCL2 comprises two programmable input OR circuits the outputs UI and U2 from which provide a logic input pair for a Universal Boolean Function Generator (UBFG2/1) which may be implemented by a programmable cell PC2 and input generator IG as described with reference to FIGURE 3. The input pair Ul,U2 corresponds to the logic input pair A,B in FIGURE 3. The UBFG2 receives programmable input signals corresponding to E00..E01 in FIGURE 3 on inputs CN0...CN3 the programmation of which determines the output signal VI = F CN0 _. CN03 (Ul,U2) where UI and U2 have the same form as the output U from the control logic circuit UCLl. In the control logic circuit UCL3, the output U0 from a control circuit UCLl and the output VI from the UBFG2/2 of a control logic circuit UCL2 provide inputs to an AND gate GA2 to produce an output WI = U0&V1. In the control circuit UCL4, the outputs V2 and V3 from UBFG2/3 and UBFG/4 of two control logic circuits UCL2 are applied as inputs to respective AND gates GA3 and GA4. An EXCLUSIVE-OR gate GX receives an input U0 from a control logic circuit UCLl and an input logic signal Rl (which may be an external programmable control signal) and has an output connected to inputs of each of the AND gates GA3 and GA4. The control logic circuit UCL4 thus produces outputs W2 = V0&V1A and W3 = V0&V1B, where VO = Rl XOR UO. Rl and UO can be used to force a particular output value for W2 and W3. Rl=l effectively implements the inversion of UO which is particularly useful. Such an implementation Could be achieved using an inverter instead of the EXCLUSIVE-OR gate GX. The inputs CN0...CN15 for UBFG2/1..UBFG2/4 may be individually programmed or generated in a programmable fashion and, if desired, may be derived from signals stored in either volatile or nonvolatile memory. The memory may be either field or factory programmable. FIGURE 19 depicts additional ways in which outputs OFk, OF1, OFm, OFn from a PLD may be utilized in conjunction with logic control circuits UCL as described with reference to FIG 18. The logic output VI from the UBFG2/1 of a control logic circuit UCL2 is connected as an input to a temporary register as store, shown as a D flip flop DFF1. The flip flop input is transferred to the Q output at the next clock pulse on the clock line CLOCK. Two control logic circuits UCL3A and UCL3B have AND gates which receive respective outputs VIA and V1B from UBFG2/2 and UBFGR/3 of control logic circuits UCL3A and UCL3B as well as inputs U3 from a common UCLl-type programmable OR gate circuit. The logic outputs WlA and WlB from the control logic circuits UCL3A and UCL3B provide respective inputs to D flip-flops DFF2 and DFF3, also clocked by the clock line CLOCK. The Q outputs Ql, Q2 and Q3 from the flip-flops DFF1, DFF2 and DFF3 may be used as external logic signals. Those Q outputs also may be transferred from the flip flops DFF1, DFF2 and DFF3 to programmably controlled logic generation cells KC0..KC3 KC4..KC7 and KC8..KC11 which generate signals K0..K3, K4..K7 and K8..K11 for the inputs CNO..CN3 of the UBFG2/1—UBFG2/3, respectively . An example of a suitable programmably controlled logic function cell K for the cells KC0..KC3 is illustrated in FIGURE 20 and comprises an EXCLUSIVE OR gate having a first input connected to receive the logic signal value Ml from a programmable memory cell. A NAND gate has two inputs, one connected to receive the logic signal value MO from a programmable memory cell and a second input connected to receive the Q output from the flip flop DFF1. The output K0 from the cell K is thus As thus far described, the control inputs K0..KC3 for UBFG2/1 from the cells KC0..KC3 could thereby each be selected from: K0..K3 e {0,1,Q1,Q1'} using logic signal values MO and Ml stored in programmable memory cells as selection signals applied to each one of the cells KC0..KC3. In addition, external logic signals may also be supplied from a port Pi (for example a terminal pin on a semiconductor chip on which the PLD(s) and control logic circuitry are integrated) and used to enter values as input signals to the programmably controlled logic cells KC0..KC3 for providing the control inputs K0..K3 to UBFG2/1. The control inputs K0..K3 for UBFG2/1 of the control logic circuit UCL2 then could be selected from: K0..K3 e {0, 1,Q1,Q ,PI} , using as selection signals, values MO, Ml and M2 stored in volatile or nonvolatile memory cells. These programmably controlled logic signal generator cells could be designed using conventional design procedures and would implement the following truth table: UBFG2/2 and UBFG2/3 of the control logic circuits UCL3A and UCL3B also receive at their inputs CN0..CN3 signals K4..K7 and K8..K11 from programmably controlled logic generation cells KC4..KC7 and KC8..KC11, respectively. Cells KC6, KC7, KC10 and KC11 are designed and controlled in a similar manner to the cells KC0..KC3 as described above, with cells KC6, KC7 receiving inputs Q2 from the flip flop DFF2 and from the external pin P2 while the cells KC10 and KC11 receive inputs Q3 from the flip flop DFF3 and from the external pin P3. The logic generator cells KC4 and KC8 also receive Ql from the flip flop DFF1 and Q2 from the flip flop DFF2, respectively, as SHIFT inputs. Ql also is applied as a COUNTER propagation input to the function cell KC5 while the ANDED signal Q1&Q2 is applied as a COUNTER propagation input to the cell KC9. The inputs K4 and K8 generated by the logic signal generator cells KC4 and KC8 for UBFG2/2 and UBFG2/3 of the control logic circuits UCL3A and UCL3B then could be __πw selected from: K4 e{0,1,Q2,Q2 * ,SHIFT,P2} , and K8 e {0, 1,Q3,Q3 * ,SHIFT,P3}, using as selection signals, values MO, Ml and M2 stored in volatile or nonvolatile memory cells. The programmably controlled logic generation cells KC4 and KC8 could be designed using conventional design procedures to implement the following truth table: MO Ml M2 K0 Shifting operations performed using KC4/KC8 type logic generation cells in the manner described above enable the temporary stores DFFl, DFF2 and DFF3 to be loaded from one pin Px by a succession of clocked operations. This allows the implementation of Parallel- In-Serial-Out and Serial-In-Parallel-Out shift registers to be functionally integrated into one circuit. This circuit can then be used to process these signals for functions such as Boolean polynomial calculations, which are extensively used in implementing Error Detection and Correction Coding schemes. Similarly, the inputs K5 and K9 generated by the cells KC5 and KC9 for UBFG2/2 and UBFG2/3 of the control logic circuits UCL3A and UCL3B could be selected from: K5 € { 0, 1 , Q2 , Q2 ~ , COUNT XOR Q2,P2}, and K9 e {0,1,Q3,Q3\COUNT XOR Q3,P3}, using as selection signals, values M0, Ml and M2 stored in volatile or nonvolatile memory cells. The programmably controlled logic generation cells KC5 and KC9 could be designed using conventional design procedures to implement the following truth table: Thus, counter functionality can be obtained by connecting additional UCL3-type stages and their associated D flip flops and function cells corresponding to KC8..KC11, with the KC9 type programmable function cells receiving inputs derived from the D flip flop of that stage and from the D flip flop of the preceding stage in the manner shown in Figure 19 for an Up Counter function. Down Counter and Up/Down Counter functions can be obtained by appropriate changes in the connections between the Q and Q* outputs from the D flip flops to the KC9 type programmable logic generation cells of neighboring stages. The counter functions are described according to the following relations: Assume an n-bit counter with bits Ql,...Qn; Count Up: Qi(next) = Qi(now) XOR CountUpi CountUpi = 1 if i=l = Ql & Q2 & ... Qi-1 if i>l Count Down: Qi(next) = Ql(now) XOR CountDowni CountDowni = 1 if i=l = Ql* & Q2* & ... Qi-1* if i>l Count Up/Down (UpDown Controlled) : Ql(next) = Qi(now) XOR CountUpDowni CountUpDowni = CountUpi & UpDown OR CountDowni & UpDown* Additional versatility of the configurable network as thus far described with reference to Figure 19 can be obtained in the following manner: The Q outputs from any or all of the flip flops DFF1, DFF2 and DFF3 and the outputs from programmable OR gates POR may be used to provide external logic signals. As shown in Figure 19, the DFF1 flip flop output Ql and the logic signal UO from an additional control circuit UCL1A are applied as inputs to a 2-to-l multiplexer MUXA. Alternatively, the Q output from a flip flop and the output from a programmable OR gate of a UCL3-type control circuit could be applied as inputs to a multiplexer. This is illustrated in Figure 19 by the connection of the Q3 output from the flip flop DFF3 and of the U2 output from a programmable OR gate of the control circuit UCL3B to a 2-to-l multiplexer MUXC. For greater flexibility, a flip flop Q output and a logic signal output from a programmable OR gate together with their inverted values could be applied as inputs to a 4- to-1 multiplexer to provide for output signal polarity selection. Thus, in Figure 19, the multiplexer MUXB receives the Q2 and Q2* outputs from the flip flop DFF2 while a logic signal UO from an additional programmable OR gate UCL1B is applied directly and via an inverter INV as inouts to the multiplexer MUXB. Figure 19 also includes circuitry permitting a multiplicity of enable inputs to be used to select connection of the output from a multiplexer to an external pin. Thus, the output from the multiplexer MUXB is connected via a switched inverter INVS to the external pin P2. An enable input for the inverter INVS is provided by a Universal Boolean Function Generator UBFG2/X implemented as described with reference to Figure 3. Output enable signals 0E1 and OE2 provide the logic input signals to UBFG2/X (equivalent to logic signals A and B in Figure 3) and the signals to inputs CN0..CN3 may be provided by values which may be stored in a volatile or nonvolatile memory, in the same manner as the stored values E00..E01 in Figure 3. In this manner, any of the sixteen logical functions of inputs OE1 and OE2 are available for selecting connection of the output from the multiplexer MUXB to the external pin P2. Similar output enable selection circuitry could also be used in conjunction with other output selection multiplexers such as MUXA and MUXC. Depending on the logic signals Ul and U2 input to the UBFG2/1, the logic signals K0, Kl, K2 and K3 are selectively transferred from input to the output of the UBFG2/1. The output signal VI of UBFG2/1 serves as the data input signal to the D flip flop DFFl. The signal generators KC0..KC3 of K0, Kl, K2 and K3 each possess a selector which is controlled by the state of the associated three bits of memory MO, Ml and M2 (not illustrated) . When DFFl is clocked, the state of the D flip flop is set to whichever one of these signals is present at the output of UBFG2/1. When the new state of the D flip flop has become stable and propagated to the Q output of the D flip flop, it is transmitted to the programmable signal generators KCO, KCl, KC2 and KC3. Changes in this Q signal then propagate through the circuitry of these signal generators KCO and KC3 and when the affected internal signals are selected for output, thus affect the output signals generated by KCO to KC3. Likewise, changes in the state of the logic signal present on the pin Pi can propagate through the signal generators KCO to KC3 to affect the data input to the D flip flop DFFl, which makes it possible to load the pin state without using up the PLD resources to transfer the pin state to the D flip flop. Thus, the PLD resources are used to determine what signal activity involving the D flip flop is to be engaged and specialized circuitry is then invoked to perform the selected activity. Figure 21 shows an arrangement similar to that shown in Figure 19 but employing three - logic - input Universal Boolean Function Generators UBFG3 in place of the two - logic - input generators UBFG2 as shown in Figure 19. As previously explained, this three input Boolean function generator requires eight control input signals to achieve full logic function generation of the three input signals. Thus, in Figure 21, UBFG3/1. UBFG3/2 and UBFG 3/3 of the control logic circuits UCL2, UCL3A and UCL3B receive an additional logic input UO from respective control logic circuits UCLlA, UCL1B and UCLlC. The necessary four additional signals K12..K15, K16..K19, and K20..K23 for each of these UBFGs are provided by additional groups of programmably controlled logic generation cells KC12..KC15, KC16..KC19, and KC20..KC23, respectively. Figure 22 shows further extensions of the arrangement shown in Figure 21. Instead of connecting the logic output UO from the control logic circuit UCLlA directly to the multiplexer MUXA, it is connected to provide one of a pair of logic inputs to a two - logic - input Universal Boolean Function Generator UBFG2/4. The output U2 from the control logic circuit UCL2 provides the second logic input for UBFG2/4 while the output from UBFG2/4 is connected to an input of the two-to-one multiplexer MUXA. A set of four programmably controlled logic signal generator cells KC24..KC27 are connected to provide signals to the inputs CN0..CN3 for the UBFG2/4. The function generation cells KC24..KC27 receive a Q input from the flip flop DFFl and an external pin input from pin Pi. (It should be noted that whereas in Figure 21 UBFG3/1 of the control logic circuit UCL2 has three logic inputs, it is shown in Figure 22 as a generator UBFG2/1 having two logic inputs. Also in Figure 22, the multiplexer MUXB is shown as receiving true and inverted outputs from a two-logic input Universal Boolean Function Generator UBFG2/5 connected (in a manner analogous to UFBG2/4) to receive as inputs, the logic control signal UO from the control logic circuit UCL1B and the logic output signal U2 from the control logic circuit UCL3A. Control signals K28..K31 for UBFG2/5 are derived from four programmably controlled logic signal generator KC28..KC31 which receive Q2 and P2 inputs from the flip flop DFF2 and the external pin P2. Figure 22 also shows an alternative manner of selecting output signals that can be used instead of multiplexers. For example, the multiplexer MUXC of Figure 21 is replaced in Figure 22 by an Universal Boolean Function Generator UBFG2/6 connected to receive one logic input signal UO from the control logic circuit UCL1C, the second logic input signal being provided by the Q3 output from the flip flop DFF3. A group of programmably controlled logic function cells KC32..KC35 receive Q3 and P3 inputs from the flip flop DFF3 and the external pin P3, respectively. The logic signals output from those function cells are connected to provide control input signals K32..K35 for control inputs CN0..CN3 of the UBFG2/6. This arrangement provides additional versatility compared with use of a multiplexer for output signal selection. Figure 23 illustrates a further development of the arrangement shown in Figure 22 in which pairs of temporary stores or registers, e.g., D flip flops DFFIA,DFF1B; DFF2A,DFF2B; and DFF3A,DFF3B replace individual flip flops. The output VI from the UBFG2/1 of the control logic circuit UCL2 is connected to provide D inputs to the flip flop pair DFFIA,DFF1B while the outputs WI from the AND gates of the control logic circuits UCL3A and UCL3B are connected to provide D inputs to the flip flop pairs DFF2A,DFF2B and DFF3A,DFF3B, respectively. The states of the D inputs of the flip flops DFF1B, DFF2B and DFF3B are transferred to their Q outputs by clock signals on the clock line CLOCK when those flip flops are enabled by signals EN applied over the ENABLE line. Similarly, the states of the D inputs of the flip flops DFFIA, DFF2A and DFF3A are transferred to their Q outputs by clock signals on the clock line CLOCK when those flip flops are enabled by signals EN* applied over the ENABLE line. The Q outputs from both flip flops DFFIA and DFF1B are connected to the output line Ql; the Q outputs from the flip flops DFF2A and DFF2B are connected to the output line Q2; and the Q outputs the flip flops DFF3A and DFF3B are connected to the output line Q3. In this manner, connection of the Q outputs from the flip flops to their associated output multiplexer and to their associated generation cells can be selected either by the EN signals or by the EN* signals. ' In relation to Figures 21-23, the function cells KC12..KC35 are implemented in the same manner as the function cells KC0..KC3. It will be appreciated that the control signals MO, Ml, etc. for the programmably controlled logic signal generator cells KC0..KC35 can be provided by values stored in memory cells, which may be programmable and individual to each particular function cell. In Figures 18-23 a variety of programmable logic function networks have been shown for connection to receive logic inputs derived from output OR gates OG of a PLD. Individual ones of the various networks shown in the respective Figures 18-23 may be selected as required to provide a particular overall logic function in conjunction with the PLD from which the OR gate outputs are derived. Although four logic inputs derived from PLD OR gates OG have been shown by way of example, this is not critical. However, increases in the number of inputs would increase the complexity of the programmable OR circuits POR. Moreover, it is not essential that all of the POR circuits of the UCL networks shown in Figures 18- 23 receive logic inputs from the same PLD OR gates OG. Figure 24 shows in diagrammatic form, a logic network embodying the folded logic arrays and associated circuit configurations based on those described herein. The network includes two pairs of triangularly folded programmable logic devices PLDL and PLDR which may be based on the configurations described with reference to Figures 1-15, comprising a pair of PLDs arranged in a generally rectangular format as ' depicted by Figure 16. The outputs from selected OR gates OG of each PLD of the pairs PLDL and PLDR are connected to programmable OR gates POR disposed in an array PORA. The array PORA together with UBFGs and logic signal generator cells KC located in the Register Function Cells array RFC, flip-flops DFF located in the Register blocks DFFs' additional programmable OR gates located in the Combination Logic array PORB, multiplexers MUX in the Multiplexer block, and output selection circuits located in the Output Function block OE, are interconnected to provide logic functionality associated with circuits such as described with reference to Figures 18-23. Thus, for example, circuits such as UCL2, UCL3A and UCL3B together with the associated UBFGs, function cells KC, flip flops DFF and multiplexers MUX can be realized by appropriate interconnections between the blocks Programmable PORA, RFC, DFF and MUX. Circuits such as UCLlA, UCL1B and UCL1C can be realized by interconnections between the blocks PORB and MUX. Outputs from the multiplexer in the block MUX are transferred to the output pins I/O by outputs from PLDL and PLDR applied to output enable circuits in the output enable block OE. Outputs from flip flops in the blocks DFF also are connected as feedback logic inputs to the input selections IGL and IGR. Logic inputs such as A X B X and C..D,. are passed from input/output pins I/O and input pins I and Clocks into input selectors IGL and IGR which select pairs of inputs and perform the functionability of the circuit IG shown in Figure 3, supplying the resultant minterms to AND gates of the programmable cells PC2 in the arrays PLDL and PLDR. Direct, or fast, outputs from the arrays PLDL and PLDR arrays are obtained by connections from the outputs of OR gates OG of those arrays and output pins FO. In a particular embodiment of the invention implemented according to the arrangement depicted in Figure 24, each of the arrays PLDL and PLDR comprises two triangular folded PLD arrays each of which has eighteen PLFGs made up of eight pairs of FAND10, FAND12, FAND1 ...FAND22 AND gate arrays plus four pairs of FAND24, the OR gates OG of which provide inputs to the programmable OR gate arrays PORA and PORB. An additional pair of PLFGs comprising FAND24 AND gate arrays have OR gates OG, the output from one of which is connected directly to the output pins FO. Outputs from the OR gate OG of the other FAND24 AND gate array in each of the arrays PLDL and PLDR provide output enable and UP/DOWN count control signals. The overall circuit can be integrated on a semiconductor chip and accommodated in a 28 pin DIP package, and has been designed under the type designation IT 91AL10L. Interconnections between pairs of PLD arrays as described with reference to Figures 1-15 to provide yet more complex functionality will be described with -. n reference to embodiments of the invention illustrated by Figures 25-30. Figure 25 depicts an interconnected logic array comprising two programmable folded logic devices PLDl and PLD2, each having seven sets of programmable logic function generators FAND12 .. FAND24 and configured in a triangular array such as described with reference to Figures 1-15, but with the OR gates OG6..0G12 in the two devices arranged along the hypotenuse of each triangle for diagrammatic convenience. Logic input pairs A0,B0 .. All,Bll are applied to the programmable logic device PLDl and logic input pairs CO,DO .. C11,D11 to the logic device PLD2. One of the two triangles is inverted with the hypotenuse of one triangle spaced from and facing that of the other triangle. Logic combination networks LCN are arranged in the intervening space so that an overall rectangular configuration is obtained. Each of the logic combination networks LCN100, LCN200, LCN400 and LCN500 receives one or more inputs from both PLDl and PLD2 while the logic combination network LCN300 receives inputs either from PLDl or from PLD2. The inputs to the networks LCN may be derived from the AND gate groups SGA by corrections from the outputs of selected OR gates OGx or from the inputs to the selected OR gates OGx from their associated AND gate group SGX in PLDl and PLD2. A Logic Combination Network LCN may receive its inputs from OR gates OG or AND-gate groups SG having different width FAND groups in PLDl and PLD2 (e.g. LCN 100 is shown as receiving inputs from the OR gates OG12 of the PLFGs FAND22 in PLDl and PLD2) or from OR gates of same width FANDs (e.g. LCN400 is shown as receiving inputs from the AND-gates LC of PLFGs FAND18 in both PLDl and PLD2) . • _ι The network LCN300 may receive inputs from two or more OR-gates OG of PLDl or of PLD2 (e.g. one LCN300 is shown as receiving inputs from the OR-gates OG10 and OG11 in PLDl and another LCN has inputs from the OR-gates OG8 and OG9 in PLD2) and these inputs may be grouped in multiples other than two. Such arrangements permit not only outputs M and N from the individual OR gates OG of the two programmable logic devices PLDl and PLD2 to be obtained, but also one or more outputs 0 and/or P from each logic combination network LCN based on logic signals derived from either or both of the devices PLDl and PLD2. The output (s) 0,P from the logic combination networks LCN may be used externally or as feedback logic input (s) (e.g., as members of the logic A, B and/or C, D input sets) to one or both of PLDl and PLD2. Figures 26-30 show examples of various logic control networks LCN and their connections to the programmable logic devices PLDl and PLD2. The input signals to CNl..., DN1... of each of the control networks LCN in Figures 27-37 which are user programmable may conveniently be derived from values stored in a user programmable volatile or non-volatile memory which may be the same memory used to supply the programmable control inputs to the PLFGs in the programmable logic devices PLDl and PLD2. This permits even greater versatility and user management of complex logic functions to be obtained. Figure 26 shows an example of a logic control network LCN100 comprising four AND gates AC1..AC4 whose outputs are input to a common OR gate producing an output O(P) . The AND gates AC1..AC4 receive first inputs from respective AND gates of a subgroup SGA6 (FAND12) in PLDl and second inputs from respective AND gates of a subgroup SGA12 (FAND24) in PLD2. Inputs to the AND gates AC1..AC4 could be derived from AND gates of subgroup SG of FANDs of the same width it desired, e.g., FAND6 in both PLDl and PLD2. The logic function outputs M,N and/or 0(P) may be used externally of the interconnected logic array or feedback as logic inputs to selected PLFGs in PLDl and PLD2. In normal circumstances, it is unlikely that both outputs M and O(P) or N and O(P) would be used, in which case a pair of multiplexers may be included as shown in Figure 26 to select either output O(P) from both sides or output M from one side and output N from the other side. Inputs to the AND gates of the network LCN 100 alternatively could be obtained from FAND arrays of the same width in PLDl and PLD2. Instead of the particular configuration of AND/OR gates shown in Figure 26, the network LCN could employ other configurations of logic gates (AND, OR, NAND, NOR, and/or INVERTER) to obtain desired fixed logic networks. Moreover, a Universal Boolean Function Generator(s) , for example similar to that described with reference to Figure 3, could be used in place of one or more of the fixed AND gates and Or gates logic network LCN shown in Figure 26. Also, instead of obtaining inputs from the output AND gates AG of a PLFG, outputs from pairs of OR gates OG of PLDl and PLD2 could be used. The interconnected logic array described with reference to Figure 26 enables very wide products (AND gate outputs in LCN) to be used in a sum (OR gate output in LCN) . This minimizes the possibility of needing a logic signal requiring more inputs than can be supported by either PLDl or PLD2. Figure 27 shows an example of a logic combination network LCN200 wherein two programmable Universsal Boolean logic Function Generators UBFG20 and UBFG2P, as described with reference to Figure 3, each receives logic inputs Mx,Nx from OR gates OGx of identical width FAND arrays in PLDl and PLD2. The FAND arrays may be of the same or different widths. The generators UBF20 and UBFG2P produce respective outputs 0 and P independently determined by programmable sets of logic signals to the control inputs CN1-4 and DNl-4. Figure 28 shows an example of a logic control network LCN300 employing two programmable Universal Boolean Function Generators UBFG20 and UBFG2P. The function generator UBFC20 receives a pair of logic inputs Mx,My from the OR gates OGx and OGy of two different programmable logic function generators FAND of PLDl. The function generator UBFG2P receives a pair of logic inputs Nx,Ny from the OR gates OGx and OGy of two different programmable logic function generators FAND of PLD2. The logic function generators FAND need not be the same width in each of PLDl and PLD2 nor need the function generators FAND be located in adjacent FAND arrays of a programmable logic device. Each of the generators UBFG20 and UBFG2P is independently user programmable by respective sets of logic signals to control inputs CNl-4 and DNl-4. The connections within and between PLDl and PLD2 provided by the network LCN as described with reference to Figs 27 and 28 each allows for much more complex logic signals to be generated by either or both PLDl and PLD2. For example, considering Fig 27: let Mx = MP1 or MP2 or MP3 or MP4; and Nx = NP1 or ... NP4. -. P can equal Mx & Nx = MP1 & NPl or ... MP4 & NP1 or MP1 & NP2 or ... MP4 & NP2 or MP1 & NP4 or MP4 & NP4 where P represents the output from UBFG2P in Fig 27. Figure 29 shows another example of a logic combination network LCN300 employing two programmable 3- input Universal Boolean logic Function Generators UBFG30 and UBFG3P. The function generator UBFG30 receives a triplet of logic inputs comprising the outputs Mx,My from two different OR gates OGx and OGy of PLDl and the output Ny from the OR gate OGy of PLD2. The function generator UBFG3P receives a triplet of logic inputs comprising the outputs Nx,Ny from the two different OR gates OGx and OGy of PLD2 and the output Mx from the OR gate OGx of PLDl. The OR gates OGx and OGy need not be associated with the same width FAND array in each of PLDl and PLD2 nor need the OR gates OGx and OGy be associated with adjacent FAND arrays of PLDl and/or PLD2. Construction of the generators UBFG30 and UBFG3P is readily derived from Figure 3 adapted to provide for decoding of a logic input triple (instead of a pair) which involves use of 8 (instead of 4) user programmable control inputs CN1..CN8 and DNl.. DN8 (connected to row lines RLO—RL7) and eight associated decode gates. Figure 30 shows a further example of a logic control network LCN400 employing two programmable 4-input Boolean logic function generators UBFG40 and UBFG4P. Each of the function generators UBFGO and UBFG4P receives a quadruplet of logic inputs comprising the outputs Mx,My from two different OR gates OGx and OGy of PLDl and the outputs Nx,Ny from the OR gates OGx and OGy of PLD2. The OR gates OGx and OGy need not be associated with the same width FAND arrays in each of PLDl and PLD2 nor need the OR gates OGx and OGy be associated with adjacent FAND arrays of PLDl and/or PLD2. Construction of the generators UBFG40 and UBFG4P is readily derived from Figure 3 adapted to provide for decoding of a logic input quadruple (instead of a pair) which involves use of 16 (instead of 4) user programmable control inputs CN1..CN16 and DNl.. DN16 (connected to row lines RL0...RL15) and sixteen associated decode gates. It will be appreciated that the interconnections within and between the programmable logic devices PLDl and PLD2 described with reference to FIGS 22 and 23 permit the creation of even more complex logic signals. Logic combination networks such as described with reference to figures 19-23 may be used to connect various of the FAND arrays in a pair of programmable logic devices PLDl and PLD2 to provide a configurable logic network capable of user programmation both within PLDl and PLD2 as well as of the logic combination networks LCN, to perform a wide variety of logic functions at least some of which may have significant complexity. The use of logic combination networks LCN as described above to obtain interconnections between OR gates OGx of two PLDs may be further expanded. For example, logic combination networks such as LCN400 could be connected to receive inputs from OR gates OGx of three different PLDs which might or might not be neighboring. Likewise, logic combination networks such as LCN500 might be connected to receive inputs from OR gates OGs of three or four different PLDs. Examples of particular utility for such connections may be appreciated from Figures 16 and 17. Thus, in the three-PLD configuration shown in Figure 16, logic combination networks such as LCN400 or LCN500 might be used to receive inputs from all three PLDs. In Figure 17, three input logic combination networks LCN 400 might usefully be employed at locations where three PLDs neighbor each other to receive inputs from OR gates OG in each of the three PLDs. Logic combination networks LCN500 might usefully be disposed at locations where four PLDs neighbor each other, to receive inputs from OR gates OG in each of the four PLDs. However, as earlier noted, logic inputs to any of the logic combination networks might be obtained from remotely located OR gates OG in various ones of the PLDs. Although there are advantages associated with use of folded triangular PLD arrays, other folded configurations may be used, some of which are depicted in Figures 16 and 17. Also, the embodiments described above with reference to Figs 18-23 can be implemented with rectangular configurations for PLDl and PLD2. In such a modified arrangement, all of the FANDs of the PLFGs would be associated with the same number of input logic pairs A,B or C,D. For example, PLDl and PLD2 might each have a series of same width PLFGs (e.g. FAND24) or PLDl might have PLFGs of one width (e.g. FANDIO) while PLD2 might have PLFGs of a different rank (e.g. FAND16) . Furthermore, embodiments of the invention may be implemented using conventional programmable circuits to provide the logic input signals to the LCN network. Such conventional programmable circuits include Programmable Logic Arrays (PLAs), Programmable Gate Arrays (PGA) and Programmable Memory Arrays (PMA) . PLAs include arrays in which a combinational logic network implements either a sum of products or a product of sums decomposition of logic functions. PLAs may be factory or field programmable. PGAs are based on factory programmation of uncommitted logic gates to provide a collection of desired logic functions. A PMA is based on building blocks requiring 2 ~ bits of memory for n logic inputs for implementing any logical function of the n inputs. The control inputs CN1..., DNl... to the logic combination networks LCN which are programmable may conveniently be derived from values stored in a memory. This memory may be a user programmable volatile or non¬ volatile memory or factory programmable for example the same memory used to supply the programmable control inputs to the programmable cells PC2 in the programmable logic devices PLDl and PLD2. Instead of being connected to receive signals from indicated memory cells, at least some of the control inputs CN1..CN4 and/or DN1..DN4 for any or all of LCN200, LCN300, LCN400 and LCN500 could be connected to receive inputs from a selectable one of several programmable memory cells which could be integrated in the same semiconductor chip as the overall system, and locations convenient to the particular LCN networks to which they are to provide control inputs. Additionally, embodiments of the invention do not need to employ folded or rectangular user programmable PLDs employing PLFGs in the AND gate array as described above. Alternatively, logic network such as any of LCN100 - LCN500 could be connected to receive as inputs corresponding to M x , N x , M y , N x , logic outputs from conventional programmable logic devices such as PALs or PLAs wherein an array of AND logic gates (or OR logic gates) receives logic inputs from which product terms "3 O (sum terms) are generated and applied as inputs to an array of OR logic gates (AND logic gates) to produce sums of product term outputs (product of sums term outputs) from device, either or both of the AND and OR logic gate arrays being programmable. Additional versatility can be obtained and also still more complex user programmable configurations, by using the outputs 0, P from selected as logic inputs to additional programmable Boolean function generators. This could be achieved, for example, by replacing the logic signals OFk, OFl, OFm, and OFn from respective PLD OR output gates OG as shown in Figures 18-23, with logic signals Ok, 01, Pm, and Pn output from logic combination networks LCN that receive logic inputs from two or more PLDs as described with reference to Figures 25-30. Since the operation of the thus modified circuits of Figures 18-23 is unchanged, no additional explantion is required. However, it will be apparent that the levels of complexity and versatility achievable using the logic signals Ok, 01, Pm, and Pn as inputs to the user programmable control logic circuits UCLl, UCL2, UCL3, and UCL4 in Figures 18-23 are significantly increased. Furthermore, the 0, P outputs from the circuits LCN may be derived from more than two PLDs, as previously explained. Individual ones of the various networks shown in the respective Figures 18-23 may be selected as required to provide a particular overall logic function network in conjunction with the PLDs interconnected in the LCNs which provide their logic inputs Ok, 01, Pm, Pn. Although four logic inputs derived from LCNs have been described by way of example, this is not critical. However, increases in the number of inputs would increase the complexity of the programmable OR circuits POR. [Moreover, it is not essential that all of the POR circuits of the UCL networks shown in Figures 18-23 receive the same four logic inputs Ok, 01, Pm, Pn.] An example of a configurable logic network embodying the invention might include two programmable logic devices PLDA and PLDB, arranged in a rectangular configuration as indicated in Figure 16. Selected OR gates OG of one programmable logic device PLDA and selected OR gates OG of the programmable logic device PLDB could be connected to logic control networks selected from networks such as LCN100, LCN200 and LCN400 as shown in Figures 26,27,29, and 30. Figure 31 depicts a multipurpose logic circuit employing UCL2, UCL3A and UCL3B stages, and associated temporary data registers DFFl, DFF2 and DFF3 strobed by the CLOCK signal and connected and operating in the manner described with reference to Figure 19. The Q output of the flip flop DFFl is also connected to provide first logic input to each of a pair of three logic input Universal Boolean Function Generators UBFG3/S1 and UBFG3/C1, a second logic input to both generators being provided from an external port Pi. The Q outputs of the flip flops DFF2 and DFF3 are similarly connected as the first logic inputs to UBFG3/S2, UBFG3/C2 and UBFG3/S3, UBFG3/C3, respectively, which receive second logic inputs from external ports P2" and P3 respectively. Then UBFG3 generators are implemented in a similar manner to the IG/PC2 circuit described with reference to Figure 2, modified so that the IG circuit provides the minterm set of three logic inputs as input signals to eight AND gates in the programmable cell. The AND gates also receive programmable inputs which can be selectively connected on outputs from the generator as a function of the three logic signal inputs to the programmable logic cell. The third logic input CO to the UBFG3/S1 is provided by an output from a programmable OR circuit PORC (constructed as shown in Figure 31) which receives logic inputs Ok, 01, Pn and Pn derived from LCNs as previously described. The outputs from UBFG3/C1 and UBFG3/C2 provide third logic inputs to UBFG3/S2, UBFG3/C2 and UBFG3/S3, UBFG3/C3 respectively. Logic outputs SI, S2 and S3 from UBFG3/S1,S2, /S3 are connected as inputs to the programmable logic signal generators KC0..KC3; KC4..KC7; and KC8..KC11, respectively. These logic signal generator groups implement the following signal table in which Si represents the output from the UBFG3/Si, i = 1, 2, 3 ... Each UBFG3/Si has a set of control signals SCN0..SCN7 and produces an output from these control signals derived from any selected function of the logic input signals Ci-1, Qi and Pi. Similarly, each UBFG3/C: has a set of control signals CCN0..CCN7 and produces an output signal Ci from those control signals derived from any selected function of the logic input signals Ci-1, Qi and Pi. The control signals SCN0...SCN7 and CCN0..CCN7 respectively can be shared between UBFG3/Si generators and UBFG3/Ci generators in two or more stages. Alternatively, the control signals can be provided locally to the UBFG3/Si and UBFG3/Ci generators of a particular stage, for example by a group of programmable memory cells integrated in the same semiconductor chip as the generator and located at a conveniently accessible location. Let the following formulae define the output signal of the generators UBFG3/Si and UBFG3/Ci respectively: Si = SCNO & Qi* & Pi* & Ci-1* or SCN1 & Qi* & Pi* & Ci-1 or SCN2 & Qi* & Pi & Ci-1* or SCN3 & Qi* & Pi & Ci-1 or SCN4 & Qi & Pi* & Ci-1* or SCN5 & Qi & Pi* & Ci-1 or SCN6 & Qi & Pi & Ci-1* or SCN7 & Qi & Pi & Ci-1 Ci = CCNO * Qi* & Pi* & Ci-1* or CCN1 & Qi* * Pi* & Ci-1 or CCN2 & Qi* & Pi & Ci-1* or CCN3 & Qi* & Pi & Ci-1 or CCN4 & Qi & Pi* & Ci-1* or CCN5 & Qi & Pi* & Ci-1 or CCN6 & Qi & Pi & Ci-1* or CCN7 & Qi & Pi & Ci-1 Consider the SCNO-7 and CCNO-7 signals as being shared amongst the UBFG3/Si and UBFG3/Ci generators. The following functions of Qi, Pi and Ci-1 will implement incrementing where CO is assumed to be 1: Si = Qi XOR Ci-1 QI & Ci-1* or Qi* & Ci-1 Qi & Pi & Ci-1* or Qi & Pi* & Ci-1* or Qi* & Pi & Ci-1* or Qi & Pi* & Ci-1 Ci Qi & Ci-1 Qi & Pi & Ci-1 or Qi & Pi* & Ci-1 for i=l, 2, 3, . . . . The following functions of Qi, Pi and Ci-1 implement addition with CO as carry input: Si = Qi xor Ci-1 xor Pi = Qi* & ( Ci-1 xor Pi) or Qi & (Ci-1 xor Pi)* Qi* & Pi* & Ci-1 or Qi* & Pi & Ci-1* or Qi & Pi & Ci-1 or Qi* & Pi* & Ci-1* Ci Qi & Ci-1 or Qi & Pi or Ci-1 & Pi = Qi & Pi & Ci-1 or Qi & Pi & Ci-1* or Qi & Pi* & Ci-1 or Qi* & Pi & Ci-1 for i = 1, 2, 3, .... The following functions i, Pi and Ci-1 implement shift right with CO as shift input: Si = Ci-1 Ci = Qi for i= 1, 2, 3, ... The above arithmetic operations can be readily coded into the SSCNO to SSCN7 and CCNO to CCN7 control values of 0 and 1. The discussion so far has focused on shared control bits for the SCN and CCN signals. By using some locally integrated memory to generate each SSCN and CCN control signal uniquely, the configuration can be programmably determined so that different logic operations can be performed by each of the UBFG3/Si and UBFG3/Ci generators. Figure 32 depicts a modification of Figure 31 in which the UBFG3/Si and UBFG3Ci pairs are replaced by dedicated, fixed logic adder stages SUMO, SUMl, SUM2 and a third adder stage SUM3 incorporated together with a Carry Out Stage Cy x Out. The SUMO stage receives inputs from the Q output of the flip flop DFFl, Pi port, and a Carry In Cy x In signal derived from the programmable OR circuit PORC as described with reference to Figure 31, and generates an output logic signal SO connected as an input to the logic signal generators KC0.KC3. The stages SUMl, SUM2 and SUM3 are similarly structured to SUMO but in addition receives Q and P logic inputs from each of the preceding stages as well as the Carry In signal Cy x In. The Carry Out stage Cy.. Out receives the same input signals as the SUM3 stage and generates a Carry Out signal Cy Out. Operation of the circuit shown in Figure 32 may be readily derived from the functional equations describing the operation of Figure 31, given above, and taking into consideration that for Figure 32, Si is the ith bit of the 2's complement sum of the Q bit vector with the P vector, given CO as the Carry Input signal Cy x In. By use of dedicated adder logic stages as described with reference to Figure 32, significantly faster operation can be obtained compared with operation of Figure 31 as an adder circuit. Of course, this increase in operating speed represents a trade off for the functional versatility of Figure 31. Figure 33 shows in diagrammatic form, a configurable logic network CLN embodying circuit configurations based on those described herein. The network CLN includes two pairs of triangularly folded programmable logic devices PLDL and PLDR which may be based on the configurations described with reference to Figures 1-15, comprising a pair of PLDs arranged in a generally rectangular format as depicted by Figure 16. The outputs from selected OR gates OG of each PLD of the pairs PLDL and PLDR are connected to programmable OR gates POR disposed in an array PORA. The array PORA together with UBFGs and function cells KC located in the Register Function Cells array RFC, flip-flops DFF located in the Register blocks DFFs additional programmable OR gates located in the Combination Logic array, multiplexers MUX in the Multiplexer block, and output selection circuits located in the Output Function block are interconnected to provide logic functionality associated with circuits such as described with reference to Figures 18-23 and 31-36. Thus, for example, circuits such as UCL2, UCL3A and UCL3B together with the associated UBFGs, logic signal generator cells KC, flip flops DFF and multiplexers MUX can be realized by appropriate interconnections between the blocks Programmable PORA, RFC, DFF and MUX. Circuits such as UCLlA, UCL1B and UCL1C can be realized by interconnections between the blocks PORB and MUX. Logic combination circuits such as LCN200..LCN500 could be realized by connections between PLDL, PLDR and UBFGs in the block RFC. Outputs from the multiplexer in the block MUX are transferred to the output pins I/O by outputs from PLDL and PLDR applied by output enable circuits in the output enable block OE. Output from flip flops in the blocks DFF also are connected as feedback logic inputs to the input selections IGL and IGR. Logic inputs such as A X B X and C X D X are clocked from input/output pins I/O into input selectors IGL and IGR which perform the functionability of the circuit IG shown in Figure 3, supplying the resultant minterms to AND gates of the programmable cells PC2 in the arrays PLDL and PLDR. Direct, or fast, outputs from the arrays PLDL and PLDR arrays are obtained by connections from the outputs of the OR gates OG of those arrays and output pins OF. In a particular embodiment of the invention implemented according to the arrangement depicted in Figure 33, each of the arrays PLDL and PLDR comprises two triangular folded PLD arrays each of which has eighteen PLFGs made up of eight pairs of FANDIO, FAND12, FAND14...FAND24 AND gate arrays the OR gates OG of which provide inputs to the programmable OR gate arrays PORA and PORB. An additional pair of PLFGs comprising FAND24 AND gate arrays have OR gates OG, the outputs from each is connected directly to the output pins OF. Outputs from the OR gate OG of the other FAND24 AND gate array in each of the arrays PLDL and PLDR provide output enable and UP/DOWN count control signals. The overall circuit can be integrated on a semiconductor chip accommodated in a 28 pin DIP package, and has been designed under the type designation IT91AL101. While particular embodiments of the invention have been described, these embodiments are examples illustrative of the invention and are not to be construed as limiting the invention. INDUSTRIAL APPLICABILITY PLDs embodying the invention have utility in applications such as high speed combinatorial logic, system controllers and complex state machines. Thus, they may advantageously be employed as state machine controllers, such as communications controllers between high speed electronic systems having different clocks. For example, in a computer system, one or more conventional PLDs may typically be employed in conjunction with each of various subsystems such as video, RAM, communications, and peripheral interface subsystems, for controlling communications with the CPU. By employing PLD's embodying the invention, integration of the necessary PLDs together with the associated programmable control memory on a single semiconductor chip or wafer in a cost effective manner is facilitated. Flexibility in operation also is enhanced because the programmation of complex logic functions implemented by the PLDs can readily be changed by a user, especially when a user programmable memory is employed to store the control input values.

Claims: WE CLAIM: 1. A programmable logic device including a plurality of groups (SGA12..SGAi) of AND logic function gates, each said AND logic function gate having a plurality of inputs, the AND logic function gates in each group having respective outputs connected to inputs of a logic OR function output gate (OG12,..OGl) associated with that AND logic function gate group; each AND logic function gate group (SGA12) including individual output AND logic function gates (AG) having inputs that are programmable by respective programmable logic function generators (PLFG) of a set of PLFGs (FAND24) operatively associated with that output AND logic function gate; each PLFG having one or more sets of logic inputs (Ax,Bx,...) and including means for generating any logic function (F(A,B)) gates of the or each set of logic inputs for use as inputs to a said output AND logic function gate according to programmable control inputs (E00..E11) applied to said PLFG, each set of PLFGs (FAND24) receiving the same set or sets of logic inputs (A0B0..AllBll) ; wherein for at least some of said AND logic function gate groups (SGA12; ... SGAI) , there are different numbers of logic input sets (A0B0..AllBll; ... AllBll). 2. A programmable logic device according to Claim 2, wherein in each PLFG there are n programmable control inputs, where n represents the number of logic inputs in each said set of logic inputs for that PLFG. 3. A programmable logic device according to Claim 2, wherein each said PLFG in a said set of PLFGs comprises a group of logic gates connected to receive the same set of logic input pairs and a group of said programmable inputs, and a common output gate connected to receive outputs derived from said group of logic gates. (Fig 3) 4. A programmable logic device according to Claim 3, wherein each PLFG includes for each logic input pair of that PLFG, an individual programmable cell connected to receive a first set of logic signals comprising minterms of said logic input pair, said programmable cell also including an output gate connected to receive inputs determined by said first set of logic signals and a plurality of programmable inputs from said group of programmable inputs for that PLFG. 5. A programmable logic device according to Claim 4, wherein said programmable cell comprises four AND logic function gates connected to provide respective inputs to said output gate of that programmable cell, said four AND logic function gates connected to receive said minterm of said logic input pair and respective ones of said programmable inputs. 6. A programmable logic device according to nay preceding claim, wherein said programmable control inputs are stored in a programmable memory. 7. A programmable logic device according to any of the preceding claims, wherein said groups of AND logic function gates are arranged to form an approximately right triangular array. 8. A configurable logic network having a plurality of programmable logic devices (PLD) , each programmable logic device comprising an AND logic array having inputs for receiving signals and generating product term output signals an OR logic array having inputs for receiving signals and generating sum term output signals at least one of said logic arrays being programmable said logic arrays interconnected to apply output signals from one of said AND and OR logic arrays as input signals to the other one of said AND and OR logic arrays, said other one of the AND and OR logic arrays providing PLD output signals and logic combination means for receiving PLD output signals from different ones of said plurality of PLDs to produce at least one output logic signal from said configurable logic network. (Figs 25-30) 9. A programmable logic device according to Claim 8 wherein each said PLD comprises a programmable logic device according to any of Claims 1-5. 10. A configurable logic network according to Claim 8, wherein said at least one programmable logic array comprises a plurality of sets of logic function generators (PLFG) , each set having a common output gate; each PLFG having a group of logic gates connected to receive first and second sets of logic signals, said first set of logic signals comprising logic inputs for said programmable logic array, and said second set of logic signals being user programmable, said logic gates connected to apply inputs to a PLFG output gate determined according to said first and second sets of logic signals; said PLFG output gates connected to provide inputs to said common output gate for that set of PLFGs. 11. A configurable logic network according to Claim 8 or Claim 10, wherein said plurality of PLDs comprises first and second PLDs. 12. A configurable logic network according to any of Claims 8-10, wherein said logic combination means includes a plurality of logic function generators (PLFG) ; each PLFG (UBFG20) having a group of logic gates connected to receive first inputs (Mx, Nx) comprising PLD output signals from said plurality of PLDs, and second inputs comprising respective sets of user programmable signals (CNx,DNx), said group of logic gates connected to apply inputs to an output gate of that PLFG determined according to said first and second inputs; wherein the output gates of said plurality of PLFGs provide respective output logic signals (Ox,Px) from said configurable logic network. (Figs 27-30) 13. A configurable logic network according to any of Claims 8-10, wherein said logic combination means produces a plurality of output logic signals from said configurable logic network, said configurable logic network further including control logic circuitry connected to logically combine a selected group of said output logic signals to produce an output that is configurable by control inputs to said control logic circuitry. (Figs 31-33) 14. A configurable logic network according to any of Claims 8-10, wherein said logic combination means is disposed in regions between neighboring ones of said PLDs. 15. A configurable logic network according to any of Claims 8-10, wherein said logic combination means includes at least one logic function generator having a group or logic gates connected to receive first logic inputs derived from the outputs of OR gates of different ones of said PLDs, and second programmable inputs, said group of logic gates connected to apply inputs to an output gate of said logic function generator. (Figs 27-30) 16. A configurable logic network according to any of Claims 8-10, wherein said logic combination means includes first and second logic function generators, each said generator having a group of logic gates connected to receive first logic inputs, and second programmable inputs, said group of logic gates connected to apply inputs to an output gate of said logic function generator wherein said first logic function generator receives first logic inputs derived from outputs from first OR gates in different ones of said PLDs, and said second logic function generator receives first logic inputs from second OR gates in different ones of said PLDs. (Figs 27-30) 17. A configurable logic network according to Claim 8, further including means for selectively deriving first logic function signals from a group of said output logic signals from different ones of said logic combination networks. (Figs 18-23, 31-33) 18. A configurable logic network according to Claim 8, wherein said means for selectively deriving comprises at least one OR logic function generator connected to derive said first logic function signals under control of programmable inputs to said OR logic function generator. (Figs 18-23, 31-33) 19. A configurable logic network according to Claim 18, wherein said means for selectively deriving comprises a plurality of said OR logic function generators each having individually controllable programmable inputs. 5 20. A configurable logic network according to Claim 19, further including logic function generator means (UBFG2/x) connected to receive a plurality of said first logic function signals to control generation of an output logic 10 function signal (VI...) by selection of programmable second logic function signals (K0,...) received by said logic function generator, a store (DFFx) connected to receive said output logic function signal means for transferring a signal (Q) derived from said output logic function signal 15 as an input to a logic signal generator means (KC0-KC3; ... ) for deriving said second logic function signals according to predetermined selection signals applied to said logic signal generator, said second logic function signals each selected from a group corresponding at least 20 to said output logic function signal and Boolean logic value signals. (Figs 31-33) 21. A configurable logic network according to Claim 20, wherein said predetermined selection signals are contained 25 in a programmable memory. 22. A configurable logic network according to Claim 20 or Claim 21, including means for applying a further input signal to said logic signal generator, and wherein said 30 second logic function signals correspond to one of at least said output logic function signal, said further input signal, and Boolean logic value signals. ■ m c D. 23. A configurable logic network according to Claim 17, wherein said means for selectively deriving comprises a plurality of logic combination circuits each of which receives output signals from a plurality of said logic combination networks and has individually controllable programmable inputs to determine the logic output signals from said logic combination circuit; said network further including a plurality of successive logic stages, each said logic stage comprising: logic function generator means for receiving a plurality of individually programmable ones of said first logic output signals to control generation of an output logic function signal by selection of programmable second logic function signals received by said logic function generator a temporary store connected to receive said output logic function signal means for transferring an output signal from said temporary store as an input to a logic signal generator means for deriving said second logic function signals according to predetermined selection signals applied to said logic signal generator, said second logic function signals each selected from a group corresponding at least to said output logic function signal and Boolean Logic value signals. 24. A configurable logic network according to Claim 23, wherein said logic signal generator means comprises a group of logic signal selectors (KC) each producing an individual second logic function signal, and each said logic signal selector has inputs connected to receive said output signal from said temporary store (DFF) and said selection signals. 25. A configurable logic network according to Claim 23, wherein at least a plurality of neighboring ones of said successive logic stages each includes means for logically combining the output signal from said store of that logic stage with the output signal from said store of a first neighboring logic stage to generate a further input signal to said logic signal generator means for input to one of the logic signal selectors of a second neighboring logic stage for selection as one of said second logic function signals from that logic signal selector, whereby said plurality of neighboring logic stages are operable to perform a counter function. (Figs 19-23) 26. A configurable logic network according to Claim 25, wherein said first neighboring logic stage precedes said one stage, and said second neighboring logic stage follows said one logic stage in the succession of logic stages, whereby said plurality of neighboring logic stages are operable to perform an arithmetic function. (Fig 32) 27. A configurable logic network according to Claim 24, wherein at least a plurality of neighboring logic stages each includes means for supplying said output signal from said store of that stage to a logic signal selector of a neighboring stage for selection as one of said second logic function signals from that logic selector to enable a shift function to be implemented. 28. A configurable logic network according to any of Claims 23-27, wherein said store comprises a register.

Inventors: JENNINGS EARLE W III, LANDERS GEORGE HERMAN, JENNINGS, EARLE, W., III, LANDERS, GEORGE, HERMAN
Applicants: INFINITE TECHNOLOGY CORP, INFINITE TECHNOLOGY CORPORATION
Application year: 1993
Main classification: H03K19
IPC codes: H03K19