Method for transferring charge, charge transfer device and solid state image sensing device using the same

Abstract: A charge transfer device has a plurality of charge transfer sections arranged in parallel to each other and having a plurality of transfer electrodes, respectively for transferring signal charges generated by signal charge generating sections in response to light; a plurality of connecting sections formed between the plural transfer sections, for transferring a signal charge existing under some transfer electrode of the plural charge transfer sections to under another transfer electrode corresponding to the other charge transfer section on the basis of a drive pulse; and sections for combining a charge remaining at the primary charge transfer section with the signal charge previously transferred, when the charge is transferred to the other charge transfer section, by transferring the remaining charge from the primary charge transfer section to the other charge transfer section through the other connecting section among the plural connecting sections.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for transferring charge and a charge transfer device, and more specifically to a multiline reading CCD (charge coupled device) register for reading signals from pixels (picture elements) arranged at fine pitches (intervals). In addition, the present invention relates to a solid-state image sensing device including such charge transfer device. Description of the Prior Art The charge transfer device such as the CCD register is now widely used as signal charge transfer sections for the solid-state image sensing device. In particular, the multiline reading CCD register has become important more and more, because of its adaptability to a high resolution image sensor of fine pitch. A conventional structure of a charge transfer device will be described hereinbelow by taking the case of a CCD linear image sensor using the multiline reading CCD register. Fig. 1 is a plan view showing an example of the conventional CCD linear image sensor formed on a semiconductor substrate. In the drawing, there is shown a two-line reading CCD register, by which signal charges generated by pixels 1 arranged in a row (i.e. a photoelectric conversion section) are read by two CCD registers 3 and 5. A shift gate 2 is disposed so as to correspond to all the pixels, and transfer gates 4 are arranged alternately along a row of the pixels 1 so as to correspond to every other pixel. When predetermined driving pulses are applied to respective transfer electrodes of the respective sections, signal charges are transferred from the pixels 1 of odd numbers to the outer CCD register 5 and from the pixels 1 of even numbers to the inner CCD register 3, as shown by dashed arrows in Fig. 1. The transferred charges are outputted to the outside through output buffers 6 and 7, respectively. In the structure as described above, since twice the number of signal charges can be transferred by the use of the two CCD registers of the same pitch, it is possible to arrange the pixels at double the pitch. In other words, in the linear image sensor using the multiline reading CCD register, it is possible to increase the pixel density in an arrangement. Figs. 2 and 3 are cross-sectional views showing the CCD linear image sensor, taken along the lines A - A' and B - B' both shown in Fig. 1. In Figs. 2 and 3, a potential distribution diagram is also shown, respectively. Further, Fig. 4 is an enlarged view showing the essential portions of the solid-state image sensing device of the CCD linear image sensor. Further, Fig. 5 is a drive timing chart between the transfer times tl and t5, during which a predetermined signal charge is transferred in the CCD linear image sensor. The shift gate 2 and the transfer gate 4 are connected to exclusive drive pulse wires SH and TG, respectively, and drive pulse wires Φ1 and Φ2 are connected to the transfer electrodes of the CCD registers 3 and 5 alternately. For example, as shown in Fig. 4, the drive pulse wire Φ1 is connected to the transfer electrodes at the cross section taken along the line A - A' shown in Fig. 1, and the drive pulse wire Φ2 is connected to the transfer electrodes at the cross section taken along the line B - B' shown in Fig. 1. First, at the time t1, the signal charges are stored in the pixels 1. At the succeeding time t2, a pulse voltage is applied to the shift gate 2 to open the gate, so that the signal charges are transferred from the pixels 1 to the shift gate 2. Thereafter, at the time t3, the transferred signal charges are shifted to the CCD registers 31 and 32, respectively. Further, at the time t4, only the signal charge in the CCD register 31 is shifted to the transfer gate 4, and further to the CCD register 51 at the time t5. After that, the signal charges are transferred within the CCD by two-phase pulses and then outputted to the outside. The problem involved in the conventional multiline reading CCD register is that the signal charges remain without being transferred during the transfer operation between the registers. In case the signal charges remain without being transferred, vertical strips appear on the display plane, so that the picture quality is deteriorated markedly. In addition, in case only one bit remains in one line, the IC is defective, thus resulting in the cause of a drop in IC production yield. The reason why the charges remain is that the channel width is narrowed at the output side of the first register so that the barrier is produced due to the narrow channel effect or the charges remain in the channel due to contamination. Although these problems have been solved to some extent by improving the pattern design and the manufacturing process of the charge transfer device, it is extremely difficult to perfectly eliminate the remaining charges in the line. In addition, since the quantity of charges to be processed decreases with increasing sensitivity of the image sensing device and also the number of signals increases with increasing number of pixels, there exists a problem in that the probability of occurrence of the remaining charges increases. Patent abstracts of Japan, vol. 11, no. 309 (E-547), 8 October 1987 & JP-A-62 104 076 disclose a method and a device for transferring charges generated by signal charge generating sections through a plurality of charge transfer sections arranged in parallel to each other. A transfer operation in which signal charges from M columns of a vertical shift register group to M rows of a horizontal shift register are transferred, is repeated several times. Such repeating operation contributes to thoroughly eliminate residual charges. This means that the transfer of charges between a column of a vertical shift register to a corresponding row of a horizontal shift register is repeated. Since the vertical shift register group and the horizontal shift register group have a one-to-one correspondence, the signal charge of a vertical shift register is transferred to a corresponding horizontal shift register through only one route. By repeating transfer through the same route, a remaining or residual charge is combined with the charge which was previously transferred. SUMMARY OF THE INVENTION An object of the present invention is to provide a new method of transferring charges which can reduce the amount of remaining charges during the charge transfer operation for improvement of picture quality. Another object of the present invention is to provide a new charge transfer device which can realize the method of transferring charges. A still further object of the present invention is to provide a solid-state image sensing device including the above-mentioned charge transfer device. According to a first aspect of the present invention, there is provided a method of transferring charges according to claim 1. According to a second aspect of the present invention, there is provided a charge transfer device according to claim 6. According to a third aspect of the present invention, there is provided a solid-state image sensing device, according to claim 13. According to the charge transfer device, the method of transferring charges, and the solid-state image sensing device using same of the present invention, the remaining parts of the charges are transferred from the first or primary charge transfer section to the second or secondary charge transfer section register after the remaining parts of the charges have been moved to other (different) transfer electrodes of the first charge transfer section. The above-mentioned transfer operation for the remaining parts of the charges is performed at least once. When performed plural times in sequence, since the remaining parts of the charges can be transferred between the charge transfer sections more perfectly, it is possible to reduce the remaining charges. Preferred embodiments of the invention are indicated in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS In the attached drawings: Fig. 1 is a plan view showing a prior art linear image sensor; Fig. 2 is a cross-sectional view taken along the line A - A' shown in Fig. 1 and a potential distribution diagram thereof together; Fig. 3 is a cross-sectional view taken along the line B-B' shown in Fig. 1 and a potential distribution diagram thereof together; Fig. 4 is an enlarged plan view showing the essential portion of the linear image sensor shown in Fig. 1; Fig. 5 is a timing chart showing the drive timing chart of the linear image sensor shown in Fig. 1; Fig. 6 is a plan view showing a first embodiment of the charge transfer device formed on a semiconductor substrate according to the present invention; Fig. 7 is an enlarged plan view showing the charge transfer device shown in Fig. 6; Fig. 8 is a cross-sectional view taken along the line A-A' shown in Fig. 6 and a potential distribution diagram thereof together; Fig. 9 is a cross-sectional view taken along the line B-B' shown in Fig. 6 and a potential distribution diagram thereof together; Fig. 10 is a drive timing chart of the first embodiment of the present invention; Fig. 11 is an enlarged plane view showing the electrode structure of the first embodiment of the charge transfer device according to the present invention; Fig. 12 is a cross-sectional view taken along the line C - C' shown in Fig. 11 and a potential distribution diagram thereof together; Fig. 13 is an enlarged plan view showing a second embodiment of the charge transfer device according to the present invention; Fig. 14 is a drive timing chart of the second embodiment of the present invention; Fig. 15 is an illustration for assistance in explaining the charge transfer operation of the second embodiment according to the present invention; Fig. 16 is an illustration for assistance in explaining the charge transfer operation of the second embodiment according to the present invention in combination with Fig. 15; Fig. 17 is an enlarged plan view showing a third embodiment of the charge transfer device according to the present invention; Fig. 18 is a cross-sectional view taken along the line E - E' shown in Fig. 17 and a potential distribution diagram thereof together; Fig. 19 is a drive timing chart of the third embodiment of the present invention; Fig. 20 is an enlarged plan view showing a fourth embodiment of the charge transfer device according to the present invention; Fig. 21 is a drive timing chart of the fourth embodiment of the present invention; Fig. 22 is a cross-sectional view taken along the line F - F' shown in Fig. 20 and a potential distribution diagram thereof together; Fig. 23 is an enlarged plan view showing a fifth embodiment of the charge transfer device according to the present invention; Fig. 24 is a cross-sectional view taken along the line G - G' shown in Fig. 23 and a potential distribution diagram thereof together; Fig. 25 is a drive timing chart of the fifth embodiment of the present invention; Fig. 26 is an enlarged plan view showing a sixth embodiment of the charge transfer device according to the present invention; Fig. 27 is a cross-sectional view taken along the line H - H' shown in Fig. 26 and a potential distribution diagram thereof together; Fig. 28 is a drive timing chart of the sixth embodiment of the present invention; Fig. 29 is an enlarged plan view showing a seventh embodiment of the charge transfer device according to the present invention; Fig. 30 is a plan view showing an eighth embodiment of the charge transfer device according to the present invention, in which the present invention is applied to an area sensor; Fig. 31 is an enlarged plan view showing the eighth embodiment of the charge transfer device according to the present invention; Fig. 32 is a cross-sectional view taken along the line H - H' shown in Fig. 29 and a potential distribution diagram thereof together; and Fig. 33 is a drive timing chart of the eighth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described hereinbelow with reference to the attached drawings. First, a first embodiment will be described with reference to Figs. 6 to 12. Fig. 6 is a plan view showing a CCD linear image sensor including charge transfer sections 3 and 5 (e.g. CCD registers) formed on a p-type silicon semiconductor substrate. The linear image sensor shown in Fig. 6 is of two-line reading type, in which signal charges generated by a plurality of pixels 1 arranged in a row are read through two CCD registers 3 and 5. The shift gate 2 is provided for all the pixels, and the transfer gates 4 are arranged alternately along the row of the pixels 1. When predetermined drive pulses are applied to respective electrodes of the shift gate 2 and the transfer gate 4, signal charges are transferred from the pixels 1 of odd numbers to the outer CCD register 5 and from the pixels 1 of even numbers to the inner CCD register 3, respectively as shown by dashed arrows in Fig. 7. Here. Fig. 7 is an enlarged plan view showing the essential portions of the charge transfer device shown in Fig. 6. Further, the transferred charges are outputted to the outside through output buffers 6 and 7, respectively. In the structure as described above, since twice the number of signal charges can be transferred from the pixels to the outside with the use of two CCD registers of the same pitch, it is possible to arrange the pixels at double the pitch. As a result, in the linear image sensor using the multiline reading CCD register, it is possible to increase the pixel arrangement density. Further, in this embodiment, it should be noted that an storage section 8 composed of storage electrodes 81, 82, ... is arranged additionally between the shift gate 2 and the first CCD register (first charge transfer section) 3. Figs. 8 and 9 are cross-sectional views taken along the lines A - A' and B - B' of the semiconductor substrate shown in Fig. 6, in which potential distribution diagrams at the same cross sections are also shown together, respectively. Further, Fig. 10 is a drive timing chart between the transfer times t1 and t10 during which a predetermined signal charge of the CCD linear image sensor is transferred. The shift gate 2, the storage section 8 and the transfer gate 4 are connected to exclusive drive pulse wires SH, ST and TG, respectively, and drive pulse wires Φ1 and Φ2 are connected to the transfer electrodes of the CCD registers 3 and 5 alternately. For example, with reference to Figs. 6 and 7, the drive pulse wire Φ1 is connected to the transfer electrodes arranged at the cross section line A - A' shown in Fig. 6, and the drive pulse wire Φ2 is connected to the transfer electrodes arranged at the cross section line B - B' shown in Fig. 6. The feature of this embodiment resides in the waveform of the drive pulses applied through the drive pulse wires Φ1 and Φ2. In more detail, in the case of the prior art CCD registers 3 and 5 as shown in Fig. 1, the drive pulses applied through the drive pulse wires Φ1 and Φ2 do not include any pulses between the times t1 and t5 during which one signal charge is transferred from the pixels 1 to the CCD registers 3 and 5, respectively as shown in Fig. 5. In the present invention, however, the drive pulses applied through the drive pulse wires Φ1 and Φ2 include some pulses generated at predetermined timings, between the times t1 and t10 during which one signal charge is transferred from the pixels 1 to the CCD registers 3 and 5, respectively, as shown in Fig. 10. The above-mentioned additional pulses serve to transfer a remaining charge so that the remaining charge is combined with the charge now being transferred, in the case where part of the signal charge to be transferred remains. This operation will be described in further details hereinbelow. At the time t1, a signal charge is generated in the pixel 1. At the succeeding time t2, the signal charge is shifted to the storage section 8 through the shift gate 2. At the time t3, only the signal charge at the storage electrode 81 is shifted to the transfer electrode 31 of the CCD register 3. Further, at the succeeding time t4, a pulse is applied to the pulse wire TG and thereby the signal charge is shifted to the transfer gate 4. At the time t5, since the pulse applied through the pulse wire TG is released, the signal charge is shifted to under the transfer electrode 51 of the CCD register 5 so that the first transfer between the two registers 3 and 5 ends. At the next times t6 and t7, the signal charge transferred under the transfer electrode 51 is further shifted to under the transfer electrode 53 through under the transfer electrode 54, and at the same time if any charge remains under the transfer electrode 31 of the CCD register 3, the remained charge is shifted to under the transfer electrode 33 through under the transfer electrode 34. At the succeeding times t8 and t9, the second transfer operation between the two registers 3 and 5 is performed through the transfer gate electrode 42 to shift the remaining charge from the transfer electrode 33 of the CCD register 3 to the transfer electrode 53 of the CCD register 5 for combining the shifted remaining signal charge with the signal charge already shifted. Here, since a voltage is kept applied to the storage section 8 during the period between the times t4 and t8, the potential well is deep at this storage section 8 and therefore the charge at the storage electrode 82 is kept stored under the storage section 8, so that it is possible to prevent this charge from being mixed with the preceding signal charge. Finally, at the time t10, the charge under the storage electrode 82 is shifted to under the transfer electrode 32, and further transferred within the CCD registers by the two phase clocks. As described above, it is possible to restore the remaining charge as the signal charge effectively. In the case where the signal charge is required to be transferred repeatedly between the two registers, the same transfer operation between the times t6 and t8 is to be repeated. In the structure as described above, since the same signal charge can be transferred several times between the registers through different electrodes, it is possible to reduce the possibility of occurrence of remaining charge markedly. Furthermore, where the storage section is provided between the pixels and the CCD resister, it is possible to further prevent the signal charge from being mixed with each other. Furthermore, since the one transfer time between the two registers is 1 µsec or less in usual, even if several transfer operations are repeated between the registers, the influence upon the total integration time is negligible. In this embodiment, the operation in which signal charges are transferred to a neighboring transfer gate and then transferred to another charge transfer section is repeatedly performed. However, it is possible to repeatedly transfer to another charge transfer section at a far transfer gate by repeating charge transfer operation between times t5 to t7. The structure of the transfer electrodes of the charge transfer sections (CCD registers) 3 and 5 of this embodiment will be described in detail with reference to Fig. 11. Fig. 11 is an enlarged plan view showing the charge transfer device formed on a semiconductor substrate 10, and Fig. 12 is a cross-sectional view showing the charge transfer section (CCD register) 5, taken along the line C - C' shown in Fig. 11. As understood by these drawings, each transfer electrode is composed of a pair of electrodes. The respective electrodes are connected to the drive pulse wires Φ1 and Φ2 alternately to transfer signal charges within the charge transfer section through the drive pulse wires. For instance, the transfer electrode 51 of the charge transfer section 5 is composed of two electrodes 511 and 512 of different potential, both being connected to the drive pulse wire Φ1. On the other hand, the transfer electrode 54 is composed of two electrodes 541 and 542, both being connected to the drive pulse wire Φ2. The second embodiment of the present invention will be described hereinbelow with reference to Figs. 13 to 16. Here, in the same way as in the first embodiment, a two-line reading CCD linear image sensor including the CCD registers is formed on a silicon semiconductor substrate 10. Fig. 13 is a plan view showing the essential portion of the image sensor formed on the semiconductor substrate 10. The image sensor comprises a pixel section 1, a shift gate 2, a first CCD register 3, a transfer section 4, a second CCD register 5 and a storage section 8, in the same way as in the first embodiment. In the first embodiment, as shown in Fig. 7, the charge transfer sections 3 and 5 each composed of a plurality of transfer electrodes arranged so as to construct the first and second CCD registers are arranged in two lines; the transfer electrodes of the predetermined columns of these two CCD registers 3 and 5 are connected by the drive pulse wires so as to form a single transfer stage; the drive pulse wires for constituting a plurality of the transfer stages are arranged alternately by two different pulse patterns; and the signal charges within the respective CCC registers are transferred in response to the two phase clocks. In comparison with the first embodiment, in this second embodiment, the transfer electrodes of the respective CCD registers 3 and 5 are provided with two-split subelectrodes, respectively. For instance, the transfer electrodes 31, 32 34 and 33 of the CCD register 3 are composed of electrodes 311 and 312, 321 and 322, 341 and 342 ,and 331 and 332, respectively. Further, the transfer electrodes 51, 52, 54 and 53 of the CCD register 5 are composed of electrodes 511 and 512, 521 and 522, 541 and 542 ,and 531 and 532, respectively. Further, drive pulse wires of different pulse patterns are connected alternately to the respective electrodes of these CCD registers. In more detail, a drive pulse wire Φ3 is connected to the electrodes 312 and 512, and a drive pulse wire Φ4 is connected to the electrodes 342 and 542, respectively. Fig. 14 is a drive timing chart between the transfer times t1 and t12 during which a single signal charge is transferred forward and reversely. The charge transfer operation between the two registers during the times between t1 and t9 is the same as in the first embodiment, and therefore the remaining charge is combined with the charge already transferred. Thereafter, during the period between the time t10 and t11, the signal charge is transferred reversely to the CCD register 5. At the time t11, the charge is transferred to the transfer electrode 52 of the CCD register 5. At and after t12, the respective signal charges are transferred within the CCD registers 3 and 5 toward the output section. When the signal charges are transferred as described above, since the signal charges are shifted in the CCD register 5 during the charge transfer operation between the two registers, there exists the case where the charge reading timing does not match each other between the two CCD registers 3 and 5. To overcome this problem, the following method is adopted in this embodiment. Namely, in this second embodiment, the signal charge is transferred from the electrode 511 to the electrode 531 of the transfer electrode 51 of the charge transfer section 5, and further transferred reversely from the electrode 531 to the transfer electrode 52. The operation from the reverse transfer to the forward retransfer until being outputted is shown by the numerals (1) to (11) in Fig. 14. Further, the signal charge is transferred on the basis of the changes (shown by the numerals (1) to (11) in Figs. 15 and 16) in potential distribution of the semiconductor substrate at the cross section taken along the line D - D' shown in Fig. 13. In Figs. 15 and 16, the numerals (1) to (7) denote the reverse transfer operation; and the numerals (8) to (11) denote the ordinary forward transfer operation. In this second embodiment, although the charge transfer section 5 is of 4-phase structure, the charge can be transferred by 2-phase drive. The above-mentioned method is effective when the charges are transferred between the two registers repeatedly many times or through the transfer gates arranged far away from the registers. Further, in this embodiment, it is unnecessary to adjust the number of stages of the CCD registers. As described above, in this embodiment, since the position and the time at which the charge transfer starts within the registers on the basis of the reverse transfer operation, it is possible to output the signals from both the CCD registers at the same time, so that the signal processing at the later stages can be more facilitated. The third embodiment of the present invention will be described hereinbelow with reference to Figs. 17 and 19. Fig. 17 is an enlarged plane view showing the charge transfer device, in which the charge transfer sections 3 and 5 are shown partially; Fig. 18 is a cross-sectional view taken along the line E - E' shown in Fig. 17 together with a potential distribution diagram; and Fig. 19 is a drive timing diagram thereof. In the first embodiment, the transfer electrodes of the inner charge transfer section 3 (i.e. the first CCD register) are connected to the corresponding transfer electrodes (arranged in the same column) of the outer charge transfer section 5 (i.e. the second CCD register) via the same drive pulse wire, as shown in Fig. 11. In this third embodiment, however, the transfer electrodes of the inner charge transfer section 3 are connected to the different transfer electrodes (arranged in the different columns) of the outer charge transfer section 5, as shown in Fig. 17. That is, the drive pulses applied to the inner and outer CCD registers 3 and 5 are out of phase with respect to each other. By changing the phases of the drive pulses as described above, it is possible to combine the remaining charge with the signal charge at the transfer electrodes of the charge transfer section 5 at the same timing. Therefore, the potential distribution under the transfer gate 4 can be simplified as shown in Fig. 18. In the above-mentioned embodiments of the charge transfer device according to the present invention, the two CCD registers are shown. Without being limited thereto, it is of course possible to use three or more CCD registers. In the case of the solid-state image sensing device, if three or more CCD registers are used for instance, since the arrangement density of the pixels can be increased, it is possible to form the semiconductor integrated circuit at a higher integration rate. In the case of the three charge transfer sections (i.e. there CCD registers), two transfer gates are arranged between the two charge transfer sections, respectively. That is, in the above-mentioned embodiments, two pixels are arranged to one transfer gate. In this case, however, three pixels are arranged to one transfer gate. Further, since it is necessary to shift the signal charge several times in order to combine the remaining charge with the signal charge, it is necessary to provide a sufficient number of packets by increasing the number of transfer stages at each charge transfer section more than that corresponding to all the signals. Further, in the above-mentioned embodiments, two phase driving method is adopted as the method of driving the charge transfer device. Without being limited thereto, it is of course possible to adopt the three or four phase driving methods. The fourth embodiment of the present invention will be described hereinbelow with reference to Figs. 20 to 22. In this embodiment, the charge transfer device is driven by three phase driving method. Fig. 20 is an enlarged plan view showing the charge transfer section formed on a semiconductor substrate 10. Fig. 22 is a cross-sectional view taken along the line F - F' shown in Fig. 20 together with a potential distribution diagram; and Fig. 21 is a drive timing diagram thereof. In this embodiment, when the signal charge is transferred, the remaining charge is transferred along another route and further the signal charge and the remaining charge are combined finally at the charge transfer section 5 in accordance with the potential distribution (as shown in Fig. 22) obtained by providing the drive pulse timing pattern (as shown in Fig. 21). In the method as described above, it is possible to read the two pixels by use of three electrodes. In this method, however, the driving method is rather complicated. The fifth embodiment of the present invention will be described with reference to Figs. 23 to 25. Fig. 23 is an enlarged plane view showing the charge transfer section formed on a semiconductor substrate 10. Fig. 24 is a cross-sectional view taken along the line G - G' shown in Fig. 23 together with a potential distribution diagram; and Fig. 25 is a drive timing diagram thereof. The points different from the third embodiment shown in Fig. 7 are that the transfer gate 4 is omitted and further the CCD register 3 and the CCD register 5 are arranged in such a way as to be directly adjacent to each other alternately. In more detail, the length of the CCD registers 51 and 53 to which the drive pulse wire Φ1 is connected is longer than that of the CCD registers 52 and 54 to which the drive pulse wire Φ2 is connected. Further, the inner ends of the CCD registers 51 and 53 are adjacent to the outer ends of the CCD registers 31 and 33, respectively. The operation of this fifth embodiment will be described with reference to Figs. 23 to 25. At the time t1, a signal charge is stored at the pixel 1. At the time t2, the charge is shifted to the storage electrode 8 via the shift gate 2. At the time t3, only the charge under the storage electrode 81 is shifted to the CCD register 31. At the time t5, the first transfer between the two registers is made to shift the charge from the CCD register 31 to the CCD register 51. At the times t6 and t7, the charge under the CCD register 51 and a remaining charge under the CCD register 31 are both shifted to the CCD registers 53 and 33, respectively. Further, at the time t9, the second transfer between the two registers is made. Since the potential is deep at the storage electrode 8 between the times t4 and t7, the charge under the storage electrode 8 is kept stored as it is. At the time t10 finally, the charge under the storage electrode 82 is shifter from the storage electrode 8 to the CCD register 32. Thereafter, the charge is transferred within the CCD registers by the two phase clocks. As described above, it is possible to transfer the charges without arranging the transfer gate between the charge transfer sections (e.g. two CCD registers) 3 and 5. In this fifth embodiment, if phases of drive pulses Φ3 and Φ5 are offset during charge transfer operation of transferring charges through the charge transfer sections 3 and 5, there may be a problem that charges under charge transfer sections 3 and 5 are mixed. To prevent this, if impurity concentrations under charge transfer sections 3 and 5 are made different or voltages of drive pulses Φ3 and Φ5 are made different during transfer of charges in order to make the depth of potential well under the charge transfer section 5 shallower than that of the charge transfer section 3, there will be no mixing of charges under the charge transfer sections 3 and 5. The sixth embodiment of the present invention will be described with reference to Figs. 26 to 28. Fig. 26 is an enlarged plan view showing the charge transfer section formed on a semiconductor substrate 10. Fig. 27 is a cross-sectional view taken along the line H - H' shown in Fig. 26 together with a potential distribution diagram; and Fig. 28 is a drive timing diagram thereof. The feature of this embodiment is to omit the storage section 8 (ST) for prevention of charge mixture. The potential distribution at the cross sectional portion H - H' of the charge transfer section formed on the semiconductor substrate as shown in Fig. 26 varies in accordance with the drive pulse timing pattern as shown in Fig. 28. Therefore, when the signal charge is transferred, the remaining charge is shifted via another route and further both are combined with each other finally at the charge transfer section 5. In this embodiment, the binary pulse voltage is replaced with a ternary pulse voltage for prevention of charge mixture, as shown in Fig. 28. The seventh embodiment will be described with reference to Fig. 29. The feature of this embodiment is to provide a difference in the number of the transfer electrodes between the first charge transfer section (i.e. first CCD register) 3 and the second charge transfer section (i.e. second CCD register) 5. In this embodiment, since there exists a difference in the number of the transfer stages, it is possible to match the read timing of the first charge transfer section 3 with that of the second charge transfer section 5. For instance, when a charge is transferred from the first charge transfer section 3 to the second charge transfer section 5 through the transfer gate 41 as shown by the line A - a in Fig. 29, the number of the transfer stages (i.e. the number of electrodes) between the transfer gate 41 and the output side is determined to be m stages in the first charge transfer section 3 and to be n stages in the second charge transfer section 5. This is because when the numbers of the transfer stages of both the sections 3 and 5 are the same with respect to each other, there exists the case where the signal charge reading timing is different from each other. Therefore, it is possible to match the timings of both by appropriately changing the numbers of stages (m or n) of the transfer electrodes in both the sections 3 and 5. The eighth embodiment of the present invention will be described with reference to Figs. 30 to 33. The feature of this embodiment is to apply the charge transfer device to a two-dimensional area sensor. In the case of the linear sensor, the pixels are arranged in a horizontal line. In the case of the area sensor, however, the pixels are arranged in two dimensional way so as to have a plurality of vertically arranged pixels. The charges are generated at the respective pixels arranged along the vertical columns. The generated charges are transferred from vertical CCDs (referred to as VCCDs, hereinafter) formed in parallel to each other along the vertical columns to the first charge transfer section 3, to the transfer gate 4, and further to the second charge transfer section 5. Further, the transferred charges are outputted to the outside through output buffers 6 and 7. In the transfer sections provided for the pixels, charges are driven by drive pulses of ΦV1, ΦV2, ΦV3, and ΦV4, respectively. In the charge transfer sections 3 and 5, charges are driven by drive pulses ΦH1 and ΦH2, respectively. Each of the charge transfer sections is composed of a horizontal CCD (referred to as HCCD, hereinafter). Fig. 30 shows the case of the interline transfer type area sensor. However, the structure of a frame transfer type area sensor is basically the same as that shown in Fig. 30. Fig. 31 is an enlarged plan view showing partially the area sensor for assistance in explaining the transfer operation of signal charges. Fig. 32 is a cross-sectional view taken along the line J - J' shown in Fig. 31 together with a potential distribution diagram; and Fig. 33 is a drive timing diagram thereof. In accordance with the drive timing pattern, the signal charges are transferred through the transfer sections and combined with the remaining charge just before the output sections. In addition to the method of storing the signal charges as explained already in relation to the above-mentioned embodiments, another method of storing the succeeding-line signal charge under the storage section (ST) or the shift gate (SH) at the connecting portion between the pixel and the charge transfer section will be described hereinbelow. The one method is to divide the storage electrodes of the storage section 8 into two types, and further to control the respective electrodes independently for prevention of mixture between the signal charges. Alternatively, it is possible to divide the number of signals into a half and to combine the divided signals before being outputted. In this later case, the number of the pixels is regarded as a half thereof. Although not miniaturized in this method, since the signal charges can be read in parallel, it is possible to increase the signal reading speed. The effect of reducing the remaining charges in accordance with the driving methods of the above-mentioned embodiments will be described hereinbelow from the probability standpoint. First, the probability that the remaining charges are reduced down to zero in a single line during the transfer between the two registers will be calculated. In the case of the prior art, since the transfer between the two registers is only once, the probability PO (M) at which the remaining charge is zero can be expressed as PO (M) = (1 - P) M where M denotes the number of buckets for signal charges; and P denotes the probability at which a defective remaining charge occurs when a single signal is transferred between the registers. In the case where the transfer between the two registers is repeated once, if P1 (M) is a probability at which no remaining charge occurs at the two or more continuously adjacent transfer gates of M-piece transfer gates; A1 (M) is a probability at which remaining charges occur at the m-th gate; and B1 is a probability at which no remaining charges occur at the same m-th gate, the following equations (2) and (3) can be established. The equation (2) can be expressed as where P1 (M) = A1 (M) + B1 (M) In the case where the transfer between the registers is repeated two and three times, the probability can be obtained in the same way as above. That is, where the transfer between the registers is repeated twice, in the same way as in the single repetition, if P2 (M) is a probability at which three or more continuous no remaining charges occur in all the transfer gates, and further the present or absence of remaining charge at the (M - 1)-th gate and the (M)-th gate is classified as listed in Table 1 below, the following equations (3) and (4) can be established. The equation (4) can be expressed as where P2 (M) = A2 (M) + B2 (M) + C2 (M) + D2 (M) (M -1) (M) A2 (M) Yes Yes B2 (M) No Yes C2 (M) Yes No D2 (M) No No Next, in the case where the transfer between the registers is repeated three times, in the same way as in the single repetition, if P3 (M) is a probability at which four or more continuous no remaining charges occur in all the transfer gate, and further the presence and absence of remaining charge at the (M-1)-th gate and the (M)-th gate is classified, the following equations (6) and (7) can be established. The equation (6) is expressed as where P3 (M) = A3 (M) + B3 (M) + C3 (M) + D3 (M) + E3 (M) + F3 (M) + G3 (M) + H3 (M) On the basis of the above-mentioned equations (1) to (7), the probability that the remaining charge is zero for 1000 signals can be obtained as listed in Table 2 below P P(0) P(1) P(2) P(3) 0. 0001 0. 905 >0. 999 >0. 999 >0. 999 0. 001 0. 368 0. 999 0. 999 0. 999 0. 01 4 E-5 0. 906 0. 999 >0. 999 0. 1 2 E-46 1 E-4 0. 406 0. 914 Table 2 lists the probabilities P (n) at which the number of the remaining charges becomes zero for 1000 signals, which can be obtained by expanding the probability P at which the remaining charge occurs for a single signal. Further, n (0, 1, ...) denotes the number of repetitions of the transfers between the registers. The Table 2 indicates that the remaining charges can be reduced markedly by simply repeating the number of transfer between the registers. This marked effect can be obtained easily by changing the drive signal timing without modifying the structure thereof. As described above, in the charge transfer device according to the present invention, it is possible to prevent the charges from remaining at the charge transfer sections, by repeating the charge transfers between the registers when the charge transfer device is driven. In addition, it is also possible to prevent the transferred signal charge from being mixed with the succeeding signal charge, by applying a driving pulse to the storage section formed on the semiconductor substrate during the signal transfer operation.

Claims: A method of transferring charges generated by signal charge generating sections (1) and clocked by drive pulses ( 1 ,  2 ;  1 -  3 ;  1 -  4 ), through a plurality of transfer electrodes (31-34, 51-54) of a plurality of charge transfer sections (3, 5) arranged in parallel to each other, comprising the steps of: transferring in a first transfer operation, a first part of a signal charge existing under a transfer electrode (31) of a primary charge transfer section (3), through one (41) of a plurality of connecting sections (4), to under a transfer electrode (51) of a secondary charge transfer section (5), said plurality of connecting sections (4) being provided between said primary and secondary charge transfer sections (3, 5), on the basis of a predetermined drive pulse; and after said first part of said signal charge has been transferred to the secondary charge transfer section (5), transferring a remaining part of the charge left under said transfer electrode (31) of said primary charge transfer section (3) along said primary charge transfer section (3) and through another connecting section (42) among the plurality of connection sections (4) in a second transfer operation, to the secondary charge transfer section (5) to combine the remaining part of the charge with the first part of the signal charge previously transferred. A method according to claim 1, wherein said remaining part of the charge is combined with said first part of the signal charge previously transferred twice or more times for each signal reading operation. A method according to claim 1, wherein until said remaining part of the charge is combined with said first part of the signal charge previously transferred to said secondary charge transfer section (5), a succeeding charge is temporarily stored in a charge storage section (8). A method according to claim 1, wherein after said remaining part of the charge has been combined with said first part of the signal charge previously transferred to said secondary charge transfer section (5), the combined signal charge is transferred reversely to under the transfer electrode (521) of said secondary charge transfer section (5) . A method according to claim 1, wherein during the operation of combining said remaining part of the charge with said first part of the signal charge previously transferred to the secondary charge transfer section (5), at least one of said remaining part of the charge and said first part of the charge previously transferred is transferred reversely in any of charge transfer sections. A charge transfer device, comprising: a plurality of charge transfer sections (3, 5) arranged in parallel to each other and having a plurality of transfer electrodes (31-34; 51-54), respectively for transferring signal charges generated by signal charge generating sections (1); a plurality of connecting sections (4) formed between said plural charge transfer sections (3, 5), for transferring a first part of a signal charge existing under some transfer electrode (31) of a primary charge transfer section (3) to under another transfer electrode (51) of a secondary charge transfer section (5) on the basis of a predetermined drive pulse; and means for combining a remaining part of the charge left under said transfer electrode (31) of said primary charge transfer section (3) with said first part of the signal charge previously transferred, by transferring said remaining part of the charge from said primary charge transfer section (3) to said secondary charge transfer section (5) along said primary charge transfer section (3) and through another connecting section (42) among the plurality of connecting sections (4). A charge transfer device of claim 6, wherein said connecting sections (4) are transfer gates (41, 42) formed between specific transfer electrodes (31, 33) of said primary charge transfer section (3) and transfer electrodes (51, 53) of said secondary charge transfer sections (5), respectively for controlling the charge transfer. A charge transfer device of claim 7, wherein said specific transfer electrodes (31,33 in Fig.7) are arranged alternately with transfer electrodes (32,34 in Fig. 7) along a row of pixels (1). A charge transfer device of claim 6, which further comprises charge storage sections (8) for temporarily storing a succeeding charge, when a first part of a signal charge existing under the one transfer electrode (31) of said primary charge transfer section (3) is being transferred to under said transfer electrode (51) of said secondary charge transfer section (5) on the basis of a predetermined drive pulse. A charge transfer device of claim 6, wherein the plurality of transfer electrodes of said plural charge transfer sections are connected to a drive pulse wire for transferring a signal charge through said charge transfer sections in either one of the forward direction and the reverse direction. A charge transfer device according to claim 6, wherein said plural charge transfer sections (3, 5) have a different number (m, n) of transfer electrodes. A charge transfer device of claim 6, wherein the number of transfer electrodes in said charge transfer sections through which one signal charge packet can be transferred is larger than the total number of signal charge packets. A solid-state image sensing device, comprising on a substrate: a signal charge generating section (1) for generating signal charges in response to incident light; and said charge transfer device according to any one of claims 6 to 12, for transferring the signal charges generated by said signal charge generating section (1).

Inventors: MONOI MAKOTO, MONOI, MAKOTO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1993
Main classification: H04N3
IPC codes: H04N3, H01L27, H01L21, H01L29, H04N5